blob: 987afebea09379507f2c8505e7f4c14acbde079c [file] [log] [blame]
Sandeep Paulraj358934a2009-12-16 22:02:18 +00001/*
2 * Copyright (C) 2009 Texas Instruments.
Brian Niebuhr43abb112010-10-06 18:34:47 +05303 * Copyright (C) 2010 EF Johnson Technologies
Sandeep Paulraj358934a2009-12-16 22:02:18 +00004 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
Sandeep Paulraj358934a2009-12-16 22:02:18 +000014 */
15
16#include <linux/interrupt.h>
17#include <linux/io.h>
18#include <linux/gpio.h>
19#include <linux/module.h>
20#include <linux/delay.h>
21#include <linux/platform_device.h>
22#include <linux/err.h>
23#include <linux/clk.h>
Matt Porter048177c2012-08-22 21:09:36 -040024#include <linux/dmaengine.h>
Sandeep Paulraj358934a2009-12-16 22:02:18 +000025#include <linux/dma-mapping.h>
Matt Porter048177c2012-08-22 21:09:36 -040026#include <linux/edma.h>
Murali Karicheriaae71472012-12-11 16:20:39 -050027#include <linux/of.h>
28#include <linux/of_device.h>
Murali Karicheria88e34e2014-08-01 19:40:32 +030029#include <linux/of_gpio.h>
Sandeep Paulraj358934a2009-12-16 22:02:18 +000030#include <linux/spi/spi.h>
31#include <linux/spi/spi_bitbang.h>
Tejun Heo5a0e3ad2010-03-24 17:04:11 +090032#include <linux/slab.h>
Sandeep Paulraj358934a2009-12-16 22:02:18 +000033
Arnd Bergmannec2a0832012-08-24 15:11:34 +020034#include <linux/platform_data/spi-davinci.h>
Sandeep Paulraj358934a2009-12-16 22:02:18 +000035
36#define SPI_NO_RESOURCE ((resource_size_t)-1)
37
Sandeep Paulraj358934a2009-12-16 22:02:18 +000038#define CS_DEFAULT 0xFF
39
Sandeep Paulraj358934a2009-12-16 22:02:18 +000040#define SPIFMT_PHASE_MASK BIT(16)
41#define SPIFMT_POLARITY_MASK BIT(17)
42#define SPIFMT_DISTIMER_MASK BIT(18)
43#define SPIFMT_SHIFTDIR_MASK BIT(20)
44#define SPIFMT_WAITENA_MASK BIT(21)
45#define SPIFMT_PARITYENA_MASK BIT(22)
46#define SPIFMT_ODD_PARITY_MASK BIT(23)
47#define SPIFMT_WDELAY_MASK 0x3f000000u
48#define SPIFMT_WDELAY_SHIFT 24
Brian Niebuhr7fe00922010-08-13 13:27:23 +053049#define SPIFMT_PRESCALE_SHIFT 8
Sandeep Paulraj358934a2009-12-16 22:02:18 +000050
Sandeep Paulraj358934a2009-12-16 22:02:18 +000051/* SPIPC0 */
52#define SPIPC0_DIFUN_MASK BIT(11) /* MISO */
53#define SPIPC0_DOFUN_MASK BIT(10) /* MOSI */
54#define SPIPC0_CLKFUN_MASK BIT(9) /* CLK */
55#define SPIPC0_SPIENA_MASK BIT(8) /* nREADY */
Sandeep Paulraj358934a2009-12-16 22:02:18 +000056
57#define SPIINT_MASKALL 0x0101035F
Brian Niebuhre0d205e2010-09-02 16:52:06 +053058#define SPIINT_MASKINT 0x0000015F
59#define SPI_INTLVL_1 0x000001FF
60#define SPI_INTLVL_0 0x00000000
Sandeep Paulraj358934a2009-12-16 22:02:18 +000061
Brian Niebuhrcfbc5d12010-08-12 12:27:33 +053062/* SPIDAT1 (upper 16 bit defines) */
63#define SPIDAT1_CSHOLD_MASK BIT(12)
Murali Karicheri365a7bb2014-09-16 14:25:05 +030064#define SPIDAT1_WDEL BIT(10)
Brian Niebuhrcfbc5d12010-08-12 12:27:33 +053065
66/* SPIGCR1 */
Sandeep Paulraj358934a2009-12-16 22:02:18 +000067#define SPIGCR1_CLKMOD_MASK BIT(1)
68#define SPIGCR1_MASTER_MASK BIT(0)
Brian Niebuhr3f27b572010-10-06 18:25:43 +053069#define SPIGCR1_POWERDOWN_MASK BIT(8)
Sandeep Paulraj358934a2009-12-16 22:02:18 +000070#define SPIGCR1_LOOPBACK_MASK BIT(16)
Sekhar Nori8e206f12010-08-20 16:20:49 +053071#define SPIGCR1_SPIENA_MASK BIT(24)
Sandeep Paulraj358934a2009-12-16 22:02:18 +000072
73/* SPIBUF */
74#define SPIBUF_TXFULL_MASK BIT(29)
75#define SPIBUF_RXEMPTY_MASK BIT(31)
76
Brian Niebuhr7abbf232010-08-19 15:07:38 +053077/* SPIDELAY */
78#define SPIDELAY_C2TDELAY_SHIFT 24
79#define SPIDELAY_C2TDELAY_MASK (0xFF << SPIDELAY_C2TDELAY_SHIFT)
80#define SPIDELAY_T2CDELAY_SHIFT 16
81#define SPIDELAY_T2CDELAY_MASK (0xFF << SPIDELAY_T2CDELAY_SHIFT)
82#define SPIDELAY_T2EDELAY_SHIFT 8
83#define SPIDELAY_T2EDELAY_MASK (0xFF << SPIDELAY_T2EDELAY_SHIFT)
84#define SPIDELAY_C2EDELAY_SHIFT 0
85#define SPIDELAY_C2EDELAY_MASK 0xFF
86
Sandeep Paulraj358934a2009-12-16 22:02:18 +000087/* Error Masks */
88#define SPIFLG_DLEN_ERR_MASK BIT(0)
89#define SPIFLG_TIMEOUT_MASK BIT(1)
90#define SPIFLG_PARERR_MASK BIT(2)
91#define SPIFLG_DESYNC_MASK BIT(3)
92#define SPIFLG_BITERR_MASK BIT(4)
93#define SPIFLG_OVRRUN_MASK BIT(6)
Sandeep Paulraj358934a2009-12-16 22:02:18 +000094#define SPIFLG_BUF_INIT_ACTIVE_MASK BIT(24)
Brian Niebuhr839c9962010-08-23 16:39:19 +053095#define SPIFLG_ERROR_MASK (SPIFLG_DLEN_ERR_MASK \
96 | SPIFLG_TIMEOUT_MASK | SPIFLG_PARERR_MASK \
97 | SPIFLG_DESYNC_MASK | SPIFLG_BITERR_MASK \
98 | SPIFLG_OVRRUN_MASK)
Sandeep Paulraj358934a2009-12-16 22:02:18 +000099
Sandeep Paulraj358934a2009-12-16 22:02:18 +0000100#define SPIINT_DMA_REQ_EN BIT(16)
Sandeep Paulraj358934a2009-12-16 22:02:18 +0000101
Sandeep Paulraj358934a2009-12-16 22:02:18 +0000102/* SPI Controller registers */
103#define SPIGCR0 0x00
104#define SPIGCR1 0x04
105#define SPIINT 0x08
106#define SPILVL 0x0c
107#define SPIFLG 0x10
108#define SPIPC0 0x14
Sandeep Paulraj358934a2009-12-16 22:02:18 +0000109#define SPIDAT1 0x3c
110#define SPIBUF 0x40
Sandeep Paulraj358934a2009-12-16 22:02:18 +0000111#define SPIDELAY 0x48
112#define SPIDEF 0x4c
113#define SPIFMT0 0x50
Sandeep Paulraj358934a2009-12-16 22:02:18 +0000114
Sandeep Paulraj358934a2009-12-16 22:02:18 +0000115/* SPI Controller driver's private data. */
116struct davinci_spi {
117 struct spi_bitbang bitbang;
118 struct clk *clk;
119
120 u8 version;
121 resource_size_t pbase;
122 void __iomem *base;
Brian Niebuhre0d205e2010-09-02 16:52:06 +0530123 u32 irq;
124 struct completion done;
Sandeep Paulraj358934a2009-12-16 22:02:18 +0000125
126 const void *tx;
127 void *rx;
Brian Niebuhre0d205e2010-09-02 16:52:06 +0530128 int rcount;
129 int wcount;
Matt Porter048177c2012-08-22 21:09:36 -0400130
131 struct dma_chan *dma_rx;
132 struct dma_chan *dma_tx;
133 int dma_rx_chnum;
134 int dma_tx_chnum;
135
Murali Karicheriaae71472012-12-11 16:20:39 -0500136 struct davinci_spi_platform_data pdata;
Sandeep Paulraj358934a2009-12-16 22:02:18 +0000137
138 void (*get_rx)(u32 rx_data, struct davinci_spi *);
139 u32 (*get_tx)(struct davinci_spi *);
140
Murali Karicheri7480e752014-07-31 20:33:14 +0300141 u8 *bytes_per_word;
Sandeep Paulraj358934a2009-12-16 22:02:18 +0000142};
143
Brian Niebuhr53a31b02010-08-16 15:05:51 +0530144static struct davinci_spi_config davinci_spi_default_cfg;
145
Sekhar Nori212d4b62010-10-11 10:41:39 +0530146static void davinci_spi_rx_buf_u8(u32 data, struct davinci_spi *dspi)
Sandeep Paulraj358934a2009-12-16 22:02:18 +0000147{
Sekhar Nori212d4b62010-10-11 10:41:39 +0530148 if (dspi->rx) {
149 u8 *rx = dspi->rx;
Brian Niebuhr53d454a2010-08-19 17:04:25 +0530150 *rx++ = (u8)data;
Sekhar Nori212d4b62010-10-11 10:41:39 +0530151 dspi->rx = rx;
Brian Niebuhr53d454a2010-08-19 17:04:25 +0530152 }
Sandeep Paulraj358934a2009-12-16 22:02:18 +0000153}
154
Sekhar Nori212d4b62010-10-11 10:41:39 +0530155static void davinci_spi_rx_buf_u16(u32 data, struct davinci_spi *dspi)
Sandeep Paulraj358934a2009-12-16 22:02:18 +0000156{
Sekhar Nori212d4b62010-10-11 10:41:39 +0530157 if (dspi->rx) {
158 u16 *rx = dspi->rx;
Brian Niebuhr53d454a2010-08-19 17:04:25 +0530159 *rx++ = (u16)data;
Sekhar Nori212d4b62010-10-11 10:41:39 +0530160 dspi->rx = rx;
Brian Niebuhr53d454a2010-08-19 17:04:25 +0530161 }
Sandeep Paulraj358934a2009-12-16 22:02:18 +0000162}
163
Sekhar Nori212d4b62010-10-11 10:41:39 +0530164static u32 davinci_spi_tx_buf_u8(struct davinci_spi *dspi)
Sandeep Paulraj358934a2009-12-16 22:02:18 +0000165{
Brian Niebuhr53d454a2010-08-19 17:04:25 +0530166 u32 data = 0;
Jingoo Han859c3372014-09-02 11:48:00 +0900167
Sekhar Nori212d4b62010-10-11 10:41:39 +0530168 if (dspi->tx) {
169 const u8 *tx = dspi->tx;
Jingoo Han859c3372014-09-02 11:48:00 +0900170
Brian Niebuhr53d454a2010-08-19 17:04:25 +0530171 data = *tx++;
Sekhar Nori212d4b62010-10-11 10:41:39 +0530172 dspi->tx = tx;
Brian Niebuhr53d454a2010-08-19 17:04:25 +0530173 }
Sandeep Paulraj358934a2009-12-16 22:02:18 +0000174 return data;
175}
176
Sekhar Nori212d4b62010-10-11 10:41:39 +0530177static u32 davinci_spi_tx_buf_u16(struct davinci_spi *dspi)
Sandeep Paulraj358934a2009-12-16 22:02:18 +0000178{
Brian Niebuhr53d454a2010-08-19 17:04:25 +0530179 u32 data = 0;
Jingoo Han859c3372014-09-02 11:48:00 +0900180
Sekhar Nori212d4b62010-10-11 10:41:39 +0530181 if (dspi->tx) {
182 const u16 *tx = dspi->tx;
Jingoo Han859c3372014-09-02 11:48:00 +0900183
Brian Niebuhr53d454a2010-08-19 17:04:25 +0530184 data = *tx++;
Sekhar Nori212d4b62010-10-11 10:41:39 +0530185 dspi->tx = tx;
Brian Niebuhr53d454a2010-08-19 17:04:25 +0530186 }
Sandeep Paulraj358934a2009-12-16 22:02:18 +0000187 return data;
188}
189
190static inline void set_io_bits(void __iomem *addr, u32 bits)
191{
192 u32 v = ioread32(addr);
193
194 v |= bits;
195 iowrite32(v, addr);
196}
197
198static inline void clear_io_bits(void __iomem *addr, u32 bits)
199{
200 u32 v = ioread32(addr);
201
202 v &= ~bits;
203 iowrite32(v, addr);
204}
205
Sandeep Paulraj358934a2009-12-16 22:02:18 +0000206/*
207 * Interface to control the chip select signal
208 */
209static void davinci_spi_chipselect(struct spi_device *spi, int value)
210{
Sekhar Nori212d4b62010-10-11 10:41:39 +0530211 struct davinci_spi *dspi;
Sandeep Paulraj358934a2009-12-16 22:02:18 +0000212 struct davinci_spi_platform_data *pdata;
Murali Karicheri365a7bb2014-09-16 14:25:05 +0300213 struct davinci_spi_config *spicfg = spi->controller_data;
Brian Niebuhr7978b8c2010-08-13 10:11:03 +0530214 u8 chip_sel = spi->chip_select;
Sekhar Nori212d4b62010-10-11 10:41:39 +0530215 u16 spidat1 = CS_DEFAULT;
Brian Niebuhr23853972010-08-13 10:57:44 +0530216 bool gpio_chipsel = false;
Murali Karicheria88e34e2014-08-01 19:40:32 +0300217 int gpio;
Sandeep Paulraj358934a2009-12-16 22:02:18 +0000218
Sekhar Nori212d4b62010-10-11 10:41:39 +0530219 dspi = spi_master_get_devdata(spi->master);
Murali Karicheriaae71472012-12-11 16:20:39 -0500220 pdata = &dspi->pdata;
Sandeep Paulraj358934a2009-12-16 22:02:18 +0000221
Grygorii Strashkoc0600142014-08-01 19:40:33 +0300222 if (spi->cs_gpio >= 0) {
Murali Karicheria88e34e2014-08-01 19:40:32 +0300223 /* SPI core parse and update master->cs_gpio */
Brian Niebuhr23853972010-08-13 10:57:44 +0530224 gpio_chipsel = true;
Murali Karicheria88e34e2014-08-01 19:40:32 +0300225 gpio = spi->cs_gpio;
Murali Karicheria88e34e2014-08-01 19:40:32 +0300226 }
Brian Niebuhr23853972010-08-13 10:57:44 +0530227
Murali Karicheri365a7bb2014-09-16 14:25:05 +0300228 /* program delay transfers if tx_delay is non zero */
229 if (spicfg->wdelay)
230 spidat1 |= SPIDAT1_WDEL;
231
Sandeep Paulraj358934a2009-12-16 22:02:18 +0000232 /*
233 * Board specific chip select logic decides the polarity and cs
234 * line for the controller
235 */
Brian Niebuhr23853972010-08-13 10:57:44 +0530236 if (gpio_chipsel) {
237 if (value == BITBANG_CS_ACTIVE)
Grygorii Strashkoc0600142014-08-01 19:40:33 +0300238 gpio_set_value(gpio, spi->mode & SPI_CS_HIGH);
Brian Niebuhr23853972010-08-13 10:57:44 +0530239 else
Grygorii Strashkoc0600142014-08-01 19:40:33 +0300240 gpio_set_value(gpio, !(spi->mode & SPI_CS_HIGH));
Brian Niebuhr23853972010-08-13 10:57:44 +0530241 } else {
242 if (value == BITBANG_CS_ACTIVE) {
Sekhar Nori212d4b62010-10-11 10:41:39 +0530243 spidat1 |= SPIDAT1_CSHOLD_MASK;
244 spidat1 &= ~(0x1 << chip_sel);
Brian Niebuhr23853972010-08-13 10:57:44 +0530245 }
Brian Niebuhr23853972010-08-13 10:57:44 +0530246 }
Murali Karicheri365a7bb2014-09-16 14:25:05 +0300247
248 iowrite16(spidat1, dspi->base + SPIDAT1 + 2);
Sandeep Paulraj358934a2009-12-16 22:02:18 +0000249}
250
251/**
Brian Niebuhr7fe00922010-08-13 13:27:23 +0530252 * davinci_spi_get_prescale - Calculates the correct prescale value
253 * @maxspeed_hz: the maximum rate the SPI clock can run at
254 *
255 * This function calculates the prescale value that generates a clock rate
256 * less than or equal to the specified maximum.
257 *
258 * Returns: calculated prescale - 1 for easy programming into SPI registers
259 * or negative error number if valid prescalar cannot be updated.
260 */
Sekhar Nori212d4b62010-10-11 10:41:39 +0530261static inline int davinci_spi_get_prescale(struct davinci_spi *dspi,
Brian Niebuhr7fe00922010-08-13 13:27:23 +0530262 u32 max_speed_hz)
263{
264 int ret;
265
Sekhar Nori212d4b62010-10-11 10:41:39 +0530266 ret = DIV_ROUND_UP(clk_get_rate(dspi->clk), max_speed_hz);
Brian Niebuhr7fe00922010-08-13 13:27:23 +0530267
Murali Karicherie0b047b2015-06-10 03:23:42 -0400268 if (ret < 1 || ret > 256)
Brian Niebuhr7fe00922010-08-13 13:27:23 +0530269 return -EINVAL;
270
271 return ret - 1;
272}
273
274/**
Sandeep Paulraj358934a2009-12-16 22:02:18 +0000275 * davinci_spi_setup_transfer - This functions will determine transfer method
276 * @spi: spi device on which data transfer to be done
277 * @t: spi transfer in which transfer info is filled
278 *
279 * This function determines data transfer method (8/16/32 bit transfer).
280 * It will also set the SPI Clock Control register according to
281 * SPI slave device freq.
282 */
283static int davinci_spi_setup_transfer(struct spi_device *spi,
284 struct spi_transfer *t)
285{
286
Sekhar Nori212d4b62010-10-11 10:41:39 +0530287 struct davinci_spi *dspi;
Brian Niebuhr25f33512010-08-19 12:15:22 +0530288 struct davinci_spi_config *spicfg;
Sandeep Paulraj358934a2009-12-16 22:02:18 +0000289 u8 bits_per_word = 0;
Sachin Kamat32ea3942013-09-11 16:05:04 +0530290 u32 hz = 0, spifmt = 0;
291 int prescale;
Sandeep Paulraj358934a2009-12-16 22:02:18 +0000292
Sekhar Nori212d4b62010-10-11 10:41:39 +0530293 dspi = spi_master_get_devdata(spi->master);
Murali Karicheri365a7bb2014-09-16 14:25:05 +0300294 spicfg = spi->controller_data;
Brian Niebuhr25f33512010-08-19 12:15:22 +0530295 if (!spicfg)
296 spicfg = &davinci_spi_default_cfg;
Sandeep Paulraj358934a2009-12-16 22:02:18 +0000297
298 if (t) {
299 bits_per_word = t->bits_per_word;
300 hz = t->speed_hz;
301 }
302
303 /* if bits_per_word is not set then set it default */
304 if (!bits_per_word)
305 bits_per_word = spi->bits_per_word;
306
307 /*
308 * Assign function pointer to appropriate transfer method
309 * 8bit, 16bit or 32bit transfer
310 */
Stephen Warren24778be2013-05-21 20:36:35 -0600311 if (bits_per_word <= 8) {
Sekhar Nori212d4b62010-10-11 10:41:39 +0530312 dspi->get_rx = davinci_spi_rx_buf_u8;
313 dspi->get_tx = davinci_spi_tx_buf_u8;
314 dspi->bytes_per_word[spi->chip_select] = 1;
Stephen Warren24778be2013-05-21 20:36:35 -0600315 } else {
Sekhar Nori212d4b62010-10-11 10:41:39 +0530316 dspi->get_rx = davinci_spi_rx_buf_u16;
317 dspi->get_tx = davinci_spi_tx_buf_u16;
318 dspi->bytes_per_word[spi->chip_select] = 2;
Stephen Warren24778be2013-05-21 20:36:35 -0600319 }
Sandeep Paulraj358934a2009-12-16 22:02:18 +0000320
321 if (!hz)
322 hz = spi->max_speed_hz;
323
Brian Niebuhr25f33512010-08-19 12:15:22 +0530324 /* Set up SPIFMTn register, unique to this chipselect. */
325
Sekhar Nori212d4b62010-10-11 10:41:39 +0530326 prescale = davinci_spi_get_prescale(dspi, hz);
Brian Niebuhr7fe00922010-08-13 13:27:23 +0530327 if (prescale < 0)
328 return prescale;
329
Brian Niebuhr25f33512010-08-19 12:15:22 +0530330 spifmt = (prescale << SPIFMT_PRESCALE_SHIFT) | (bits_per_word & 0x1f);
Sandeep Paulraj358934a2009-12-16 22:02:18 +0000331
Brian Niebuhr25f33512010-08-19 12:15:22 +0530332 if (spi->mode & SPI_LSB_FIRST)
333 spifmt |= SPIFMT_SHIFTDIR_MASK;
334
335 if (spi->mode & SPI_CPOL)
336 spifmt |= SPIFMT_POLARITY_MASK;
337
338 if (!(spi->mode & SPI_CPHA))
339 spifmt |= SPIFMT_PHASE_MASK;
340
341 /*
Murali Karicheri365a7bb2014-09-16 14:25:05 +0300342 * Assume wdelay is used only on SPI peripherals that has this field
343 * in SPIFMTn register and when it's configured from board file or DT.
344 */
345 if (spicfg->wdelay)
346 spifmt |= ((spicfg->wdelay << SPIFMT_WDELAY_SHIFT)
347 & SPIFMT_WDELAY_MASK);
348
349 /*
Brian Niebuhr25f33512010-08-19 12:15:22 +0530350 * Version 1 hardware supports two basic SPI modes:
351 * - Standard SPI mode uses 4 pins, with chipselect
352 * - 3 pin SPI is a 4 pin variant without CS (SPI_NO_CS)
353 * (distinct from SPI_3WIRE, with just one data wire;
354 * or similar variants without MOSI or without MISO)
355 *
356 * Version 2 hardware supports an optional handshaking signal,
357 * so it can support two more modes:
358 * - 5 pin SPI variant is standard SPI plus SPI_READY
359 * - 4 pin with enable is (SPI_READY | SPI_NO_CS)
360 */
361
Sekhar Nori212d4b62010-10-11 10:41:39 +0530362 if (dspi->version == SPI_VERSION_2) {
Brian Niebuhr25f33512010-08-19 12:15:22 +0530363
Brian Niebuhr7abbf232010-08-19 15:07:38 +0530364 u32 delay = 0;
365
Brian Niebuhr25f33512010-08-19 12:15:22 +0530366 if (spicfg->odd_parity)
367 spifmt |= SPIFMT_ODD_PARITY_MASK;
368
369 if (spicfg->parity_enable)
370 spifmt |= SPIFMT_PARITYENA_MASK;
371
Brian Niebuhr7abbf232010-08-19 15:07:38 +0530372 if (spicfg->timer_disable) {
Brian Niebuhr25f33512010-08-19 12:15:22 +0530373 spifmt |= SPIFMT_DISTIMER_MASK;
Brian Niebuhr7abbf232010-08-19 15:07:38 +0530374 } else {
375 delay |= (spicfg->c2tdelay << SPIDELAY_C2TDELAY_SHIFT)
376 & SPIDELAY_C2TDELAY_MASK;
377 delay |= (spicfg->t2cdelay << SPIDELAY_T2CDELAY_SHIFT)
378 & SPIDELAY_T2CDELAY_MASK;
379 }
Brian Niebuhr25f33512010-08-19 12:15:22 +0530380
Brian Niebuhr7abbf232010-08-19 15:07:38 +0530381 if (spi->mode & SPI_READY) {
Brian Niebuhr25f33512010-08-19 12:15:22 +0530382 spifmt |= SPIFMT_WAITENA_MASK;
Brian Niebuhr7abbf232010-08-19 15:07:38 +0530383 delay |= (spicfg->t2edelay << SPIDELAY_T2EDELAY_SHIFT)
384 & SPIDELAY_T2EDELAY_MASK;
385 delay |= (spicfg->c2edelay << SPIDELAY_C2EDELAY_SHIFT)
386 & SPIDELAY_C2EDELAY_MASK;
387 }
388
Sekhar Nori212d4b62010-10-11 10:41:39 +0530389 iowrite32(delay, dspi->base + SPIDELAY);
Brian Niebuhr25f33512010-08-19 12:15:22 +0530390 }
391
Sekhar Nori212d4b62010-10-11 10:41:39 +0530392 iowrite32(spifmt, dspi->base + SPIFMT0);
Sandeep Paulraj358934a2009-12-16 22:02:18 +0000393
394 return 0;
395}
396
Murali Karicheri365a7bb2014-09-16 14:25:05 +0300397static int davinci_spi_of_setup(struct spi_device *spi)
398{
399 struct davinci_spi_config *spicfg = spi->controller_data;
400 struct device_node *np = spi->dev.of_node;
401 u32 prop;
402
403 if (spicfg == NULL && np) {
404 spicfg = kzalloc(sizeof(*spicfg), GFP_KERNEL);
405 if (!spicfg)
406 return -ENOMEM;
407 *spicfg = davinci_spi_default_cfg;
408 /* override with dt configured values */
409 if (!of_property_read_u32(np, "ti,spi-wdelay", &prop))
410 spicfg->wdelay = (u8)prop;
411 spi->controller_data = spicfg;
412 }
413
414 return 0;
415}
416
Sandeep Paulraj358934a2009-12-16 22:02:18 +0000417/**
418 * davinci_spi_setup - This functions will set default transfer method
419 * @spi: spi device on which data transfer to be done
420 *
421 * This functions sets the default transfer method.
422 */
Sandeep Paulraj358934a2009-12-16 22:02:18 +0000423static int davinci_spi_setup(struct spi_device *spi)
424{
Brian Niebuhrb23a5d42010-09-24 18:53:32 +0530425 int retval = 0;
Sekhar Nori212d4b62010-10-11 10:41:39 +0530426 struct davinci_spi *dspi;
Brian Niebuhrbe884712010-09-03 12:15:28 +0530427 struct davinci_spi_platform_data *pdata;
Murali Karicheria88e34e2014-08-01 19:40:32 +0300428 struct spi_master *master = spi->master;
429 struct device_node *np = spi->dev.of_node;
430 bool internal_cs = true;
Sandeep Paulraj358934a2009-12-16 22:02:18 +0000431
Sekhar Nori212d4b62010-10-11 10:41:39 +0530432 dspi = spi_master_get_devdata(spi->master);
Murali Karicheriaae71472012-12-11 16:20:39 -0500433 pdata = &dspi->pdata;
Sandeep Paulraj358934a2009-12-16 22:02:18 +0000434
Brian Niebuhrbe884712010-09-03 12:15:28 +0530435 if (!(spi->mode & SPI_NO_CS)) {
Murali Karicheria88e34e2014-08-01 19:40:32 +0300436 if (np && (master->cs_gpios != NULL) && (spi->cs_gpio >= 0)) {
Grygorii Strashko8936dec2014-09-12 17:54:00 +0300437 retval = gpio_direction_output(
438 spi->cs_gpio, !(spi->mode & SPI_CS_HIGH));
Murali Karicheria88e34e2014-08-01 19:40:32 +0300439 internal_cs = false;
440 } else if (pdata->chip_sel &&
441 spi->chip_select < pdata->num_chipselect &&
442 pdata->chip_sel[spi->chip_select] != SPI_INTERN_CS) {
Grygorii Strashkoc0600142014-08-01 19:40:33 +0300443 spi->cs_gpio = pdata->chip_sel[spi->chip_select];
Grygorii Strashko8936dec2014-09-12 17:54:00 +0300444 retval = gpio_direction_output(
445 spi->cs_gpio, !(spi->mode & SPI_CS_HIGH));
Murali Karicheria88e34e2014-08-01 19:40:32 +0300446 internal_cs = false;
447 }
Brian Niebuhrbe884712010-09-03 12:15:28 +0530448
Grygorii Strashko3f2dad92014-08-21 18:25:05 +0300449 if (retval) {
450 dev_err(&spi->dev, "GPIO %d setup failed (%d)\n",
451 spi->cs_gpio, retval);
452 return retval;
453 }
Grygorii Strashkoc0600142014-08-01 19:40:33 +0300454
Grygorii Strashko3f2dad92014-08-21 18:25:05 +0300455 if (internal_cs)
456 set_io_bits(dspi->base + SPIPC0, 1 << spi->chip_select);
457 }
Murali Karicheria88e34e2014-08-01 19:40:32 +0300458
Brian Niebuhrbe884712010-09-03 12:15:28 +0530459 if (spi->mode & SPI_READY)
Sekhar Nori212d4b62010-10-11 10:41:39 +0530460 set_io_bits(dspi->base + SPIPC0, SPIPC0_SPIENA_MASK);
Brian Niebuhrbe884712010-09-03 12:15:28 +0530461
462 if (spi->mode & SPI_LOOP)
Sekhar Nori212d4b62010-10-11 10:41:39 +0530463 set_io_bits(dspi->base + SPIGCR1, SPIGCR1_LOOPBACK_MASK);
Brian Niebuhrbe884712010-09-03 12:15:28 +0530464 else
Sekhar Nori212d4b62010-10-11 10:41:39 +0530465 clear_io_bits(dspi->base + SPIGCR1, SPIGCR1_LOOPBACK_MASK);
Brian Niebuhrbe884712010-09-03 12:15:28 +0530466
Murali Karicheri365a7bb2014-09-16 14:25:05 +0300467 return davinci_spi_of_setup(spi);
468}
469
470static void davinci_spi_cleanup(struct spi_device *spi)
471{
472 struct davinci_spi_config *spicfg = spi->controller_data;
473
474 spi->controller_data = NULL;
475 if (spi->dev.of_node)
476 kfree(spicfg);
Sandeep Paulraj358934a2009-12-16 22:02:18 +0000477}
478
Sekhar Nori212d4b62010-10-11 10:41:39 +0530479static int davinci_spi_check_error(struct davinci_spi *dspi, int int_status)
Sandeep Paulraj358934a2009-12-16 22:02:18 +0000480{
Sekhar Nori212d4b62010-10-11 10:41:39 +0530481 struct device *sdev = dspi->bitbang.master->dev.parent;
Sandeep Paulraj358934a2009-12-16 22:02:18 +0000482
483 if (int_status & SPIFLG_TIMEOUT_MASK) {
484 dev_dbg(sdev, "SPI Time-out Error\n");
485 return -ETIMEDOUT;
486 }
487 if (int_status & SPIFLG_DESYNC_MASK) {
488 dev_dbg(sdev, "SPI Desynchronization Error\n");
489 return -EIO;
490 }
491 if (int_status & SPIFLG_BITERR_MASK) {
492 dev_dbg(sdev, "SPI Bit error\n");
493 return -EIO;
494 }
495
Sekhar Nori212d4b62010-10-11 10:41:39 +0530496 if (dspi->version == SPI_VERSION_2) {
Sandeep Paulraj358934a2009-12-16 22:02:18 +0000497 if (int_status & SPIFLG_DLEN_ERR_MASK) {
498 dev_dbg(sdev, "SPI Data Length Error\n");
499 return -EIO;
500 }
501 if (int_status & SPIFLG_PARERR_MASK) {
502 dev_dbg(sdev, "SPI Parity Error\n");
503 return -EIO;
504 }
505 if (int_status & SPIFLG_OVRRUN_MASK) {
506 dev_dbg(sdev, "SPI Data Overrun error\n");
507 return -EIO;
508 }
Sandeep Paulraj358934a2009-12-16 22:02:18 +0000509 if (int_status & SPIFLG_BUF_INIT_ACTIVE_MASK) {
510 dev_dbg(sdev, "SPI Buffer Init Active\n");
511 return -EBUSY;
512 }
513 }
514
515 return 0;
516}
517
518/**
Brian Niebuhre0d205e2010-09-02 16:52:06 +0530519 * davinci_spi_process_events - check for and handle any SPI controller events
Sekhar Nori212d4b62010-10-11 10:41:39 +0530520 * @dspi: the controller data
Brian Niebuhre0d205e2010-09-02 16:52:06 +0530521 *
522 * This function will check the SPIFLG register and handle any events that are
523 * detected there
524 */
Sekhar Nori212d4b62010-10-11 10:41:39 +0530525static int davinci_spi_process_events(struct davinci_spi *dspi)
Brian Niebuhre0d205e2010-09-02 16:52:06 +0530526{
Sekhar Nori212d4b62010-10-11 10:41:39 +0530527 u32 buf, status, errors = 0, spidat1;
Brian Niebuhre0d205e2010-09-02 16:52:06 +0530528
Sekhar Nori212d4b62010-10-11 10:41:39 +0530529 buf = ioread32(dspi->base + SPIBUF);
Brian Niebuhre0d205e2010-09-02 16:52:06 +0530530
Sekhar Nori212d4b62010-10-11 10:41:39 +0530531 if (dspi->rcount > 0 && !(buf & SPIBUF_RXEMPTY_MASK)) {
532 dspi->get_rx(buf & 0xFFFF, dspi);
533 dspi->rcount--;
Brian Niebuhre0d205e2010-09-02 16:52:06 +0530534 }
535
Sekhar Nori212d4b62010-10-11 10:41:39 +0530536 status = ioread32(dspi->base + SPIFLG);
Brian Niebuhre0d205e2010-09-02 16:52:06 +0530537
538 if (unlikely(status & SPIFLG_ERROR_MASK)) {
539 errors = status & SPIFLG_ERROR_MASK;
540 goto out;
541 }
542
Sekhar Nori212d4b62010-10-11 10:41:39 +0530543 if (dspi->wcount > 0 && !(buf & SPIBUF_TXFULL_MASK)) {
544 spidat1 = ioread32(dspi->base + SPIDAT1);
545 dspi->wcount--;
546 spidat1 &= ~0xFFFF;
547 spidat1 |= 0xFFFF & dspi->get_tx(dspi);
548 iowrite32(spidat1, dspi->base + SPIDAT1);
Brian Niebuhre0d205e2010-09-02 16:52:06 +0530549 }
550
551out:
552 return errors;
553}
554
Matt Porter048177c2012-08-22 21:09:36 -0400555static void davinci_spi_dma_rx_callback(void *data)
Brian Niebuhr87467bd2010-10-06 17:03:10 +0530556{
Matt Porter048177c2012-08-22 21:09:36 -0400557 struct davinci_spi *dspi = (struct davinci_spi *)data;
Brian Niebuhr87467bd2010-10-06 17:03:10 +0530558
Matt Porter048177c2012-08-22 21:09:36 -0400559 dspi->rcount = 0;
Brian Niebuhr87467bd2010-10-06 17:03:10 +0530560
Matt Porter048177c2012-08-22 21:09:36 -0400561 if (!dspi->wcount && !dspi->rcount)
562 complete(&dspi->done);
563}
Brian Niebuhr87467bd2010-10-06 17:03:10 +0530564
Matt Porter048177c2012-08-22 21:09:36 -0400565static void davinci_spi_dma_tx_callback(void *data)
566{
567 struct davinci_spi *dspi = (struct davinci_spi *)data;
568
569 dspi->wcount = 0;
570
571 if (!dspi->wcount && !dspi->rcount)
Sekhar Nori212d4b62010-10-11 10:41:39 +0530572 complete(&dspi->done);
Brian Niebuhr87467bd2010-10-06 17:03:10 +0530573}
574
Brian Niebuhre0d205e2010-09-02 16:52:06 +0530575/**
Sandeep Paulraj358934a2009-12-16 22:02:18 +0000576 * davinci_spi_bufs - functions which will handle transfer data
577 * @spi: spi device on which data transfer to be done
578 * @t: spi transfer in which transfer info is filled
579 *
580 * This function will put data to be transferred into data register
581 * of SPI controller and then wait until the completion will be marked
582 * by the IRQ Handler.
583 */
Brian Niebuhr87467bd2010-10-06 17:03:10 +0530584static int davinci_spi_bufs(struct spi_device *spi, struct spi_transfer *t)
Sandeep Paulraj358934a2009-12-16 22:02:18 +0000585{
Sekhar Nori212d4b62010-10-11 10:41:39 +0530586 struct davinci_spi *dspi;
Matt Porter048177c2012-08-22 21:09:36 -0400587 int data_type, ret = -ENOMEM;
Sekhar Nori212d4b62010-10-11 10:41:39 +0530588 u32 tx_data, spidat1;
Brian Niebuhr839c9962010-08-23 16:39:19 +0530589 u32 errors = 0;
Brian Niebuhre0d205e2010-09-02 16:52:06 +0530590 struct davinci_spi_config *spicfg;
Sandeep Paulraj358934a2009-12-16 22:02:18 +0000591 struct davinci_spi_platform_data *pdata;
Brian Niebuhr87467bd2010-10-06 17:03:10 +0530592 unsigned uninitialized_var(rx_buf_count);
Matt Porter048177c2012-08-22 21:09:36 -0400593 void *dummy_buf = NULL;
594 struct scatterlist sg_rx, sg_tx;
Sandeep Paulraj358934a2009-12-16 22:02:18 +0000595
Sekhar Nori212d4b62010-10-11 10:41:39 +0530596 dspi = spi_master_get_devdata(spi->master);
Murali Karicheriaae71472012-12-11 16:20:39 -0500597 pdata = &dspi->pdata;
Brian Niebuhre0d205e2010-09-02 16:52:06 +0530598 spicfg = (struct davinci_spi_config *)spi->controller_data;
599 if (!spicfg)
600 spicfg = &davinci_spi_default_cfg;
Brian Niebuhr87467bd2010-10-06 17:03:10 +0530601
602 /* convert len to words based on bits_per_word */
Sekhar Nori212d4b62010-10-11 10:41:39 +0530603 data_type = dspi->bytes_per_word[spi->chip_select];
Sandeep Paulraj358934a2009-12-16 22:02:18 +0000604
Sekhar Nori212d4b62010-10-11 10:41:39 +0530605 dspi->tx = t->tx_buf;
606 dspi->rx = t->rx_buf;
607 dspi->wcount = t->len / data_type;
608 dspi->rcount = dspi->wcount;
Brian Niebuhr7978b8c2010-08-13 10:11:03 +0530609
Sekhar Nori212d4b62010-10-11 10:41:39 +0530610 spidat1 = ioread32(dspi->base + SPIDAT1);
Brian Niebuhr839c9962010-08-23 16:39:19 +0530611
Sekhar Nori212d4b62010-10-11 10:41:39 +0530612 clear_io_bits(dspi->base + SPIGCR1, SPIGCR1_POWERDOWN_MASK);
613 set_io_bits(dspi->base + SPIGCR1, SPIGCR1_SPIENA_MASK);
Sandeep Paulraj358934a2009-12-16 22:02:18 +0000614
Wolfram Sang16735d02013-11-14 14:32:02 -0800615 reinit_completion(&dspi->done);
Brian Niebuhr87467bd2010-10-06 17:03:10 +0530616
617 if (spicfg->io_type == SPI_IO_TYPE_INTR)
Sekhar Nori212d4b62010-10-11 10:41:39 +0530618 set_io_bits(dspi->base + SPIINT, SPIINT_MASKINT);
Brian Niebuhr87467bd2010-10-06 17:03:10 +0530619
620 if (spicfg->io_type != SPI_IO_TYPE_DMA) {
621 /* start the transfer */
Sekhar Nori212d4b62010-10-11 10:41:39 +0530622 dspi->wcount--;
623 tx_data = dspi->get_tx(dspi);
624 spidat1 &= 0xFFFF0000;
625 spidat1 |= tx_data & 0xFFFF;
626 iowrite32(spidat1, dspi->base + SPIDAT1);
Brian Niebuhr87467bd2010-10-06 17:03:10 +0530627 } else {
Matt Porter048177c2012-08-22 21:09:36 -0400628 struct dma_slave_config dma_rx_conf = {
629 .direction = DMA_DEV_TO_MEM,
630 .src_addr = (unsigned long)dspi->pbase + SPIBUF,
631 .src_addr_width = data_type,
632 .src_maxburst = 1,
633 };
634 struct dma_slave_config dma_tx_conf = {
635 .direction = DMA_MEM_TO_DEV,
636 .dst_addr = (unsigned long)dspi->pbase + SPIDAT1,
637 .dst_addr_width = data_type,
638 .dst_maxburst = 1,
639 };
640 struct dma_async_tx_descriptor *rxdesc;
641 struct dma_async_tx_descriptor *txdesc;
642 void *buf;
Brian Niebuhr87467bd2010-10-06 17:03:10 +0530643
Matt Porter048177c2012-08-22 21:09:36 -0400644 dummy_buf = kzalloc(t->len, GFP_KERNEL);
645 if (!dummy_buf)
646 goto err_alloc_dummy_buf;
Brian Niebuhr87467bd2010-10-06 17:03:10 +0530647
Matt Porter048177c2012-08-22 21:09:36 -0400648 dmaengine_slave_config(dspi->dma_rx, &dma_rx_conf);
649 dmaengine_slave_config(dspi->dma_tx, &dma_tx_conf);
Brian Niebuhr87467bd2010-10-06 17:03:10 +0530650
Matt Porter048177c2012-08-22 21:09:36 -0400651 sg_init_table(&sg_rx, 1);
652 if (!t->rx_buf)
653 buf = dummy_buf;
Michael Williamsonb1178b22011-03-14 11:49:02 -0400654 else
Matt Porter048177c2012-08-22 21:09:36 -0400655 buf = t->rx_buf;
656 t->rx_dma = dma_map_single(&spi->dev, buf,
657 t->len, DMA_FROM_DEVICE);
658 if (!t->rx_dma) {
659 ret = -EFAULT;
660 goto err_rx_map;
Brian Niebuhr87467bd2010-10-06 17:03:10 +0530661 }
Matt Porter048177c2012-08-22 21:09:36 -0400662 sg_dma_address(&sg_rx) = t->rx_dma;
663 sg_dma_len(&sg_rx) = t->len;
Brian Niebuhr87467bd2010-10-06 17:03:10 +0530664
Matt Porter048177c2012-08-22 21:09:36 -0400665 sg_init_table(&sg_tx, 1);
666 if (!t->tx_buf)
667 buf = dummy_buf;
668 else
669 buf = (void *)t->tx_buf;
670 t->tx_dma = dma_map_single(&spi->dev, buf,
Christian Eggers89c66ee2013-07-29 20:54:09 +0200671 t->len, DMA_TO_DEVICE);
Matt Porter048177c2012-08-22 21:09:36 -0400672 if (!t->tx_dma) {
673 ret = -EFAULT;
674 goto err_tx_map;
Brian Niebuhr87467bd2010-10-06 17:03:10 +0530675 }
Matt Porter048177c2012-08-22 21:09:36 -0400676 sg_dma_address(&sg_tx) = t->tx_dma;
677 sg_dma_len(&sg_tx) = t->len;
Brian Niebuhr87467bd2010-10-06 17:03:10 +0530678
Matt Porter048177c2012-08-22 21:09:36 -0400679 rxdesc = dmaengine_prep_slave_sg(dspi->dma_rx,
680 &sg_rx, 1, DMA_DEV_TO_MEM,
681 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
682 if (!rxdesc)
683 goto err_desc;
684
685 txdesc = dmaengine_prep_slave_sg(dspi->dma_tx,
686 &sg_tx, 1, DMA_MEM_TO_DEV,
687 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
688 if (!txdesc)
689 goto err_desc;
690
691 rxdesc->callback = davinci_spi_dma_rx_callback;
692 rxdesc->callback_param = (void *)dspi;
693 txdesc->callback = davinci_spi_dma_tx_callback;
694 txdesc->callback_param = (void *)dspi;
Brian Niebuhr87467bd2010-10-06 17:03:10 +0530695
696 if (pdata->cshold_bug)
Sekhar Nori212d4b62010-10-11 10:41:39 +0530697 iowrite16(spidat1 >> 16, dspi->base + SPIDAT1 + 2);
Brian Niebuhr87467bd2010-10-06 17:03:10 +0530698
Matt Porter048177c2012-08-22 21:09:36 -0400699 dmaengine_submit(rxdesc);
700 dmaengine_submit(txdesc);
701
702 dma_async_issue_pending(dspi->dma_rx);
703 dma_async_issue_pending(dspi->dma_tx);
704
Sekhar Nori212d4b62010-10-11 10:41:39 +0530705 set_io_bits(dspi->base + SPIINT, SPIINT_DMA_REQ_EN);
Brian Niebuhre0d205e2010-09-02 16:52:06 +0530706 }
Brian Niebuhrcf90fe72010-08-20 17:02:49 +0530707
Brian Niebuhre0d205e2010-09-02 16:52:06 +0530708 /* Wait for the transfer to complete */
Brian Niebuhr87467bd2010-10-06 17:03:10 +0530709 if (spicfg->io_type != SPI_IO_TYPE_POLL) {
Sekhar Nori212d4b62010-10-11 10:41:39 +0530710 wait_for_completion_interruptible(&(dspi->done));
Brian Niebuhre0d205e2010-09-02 16:52:06 +0530711 } else {
Sekhar Nori212d4b62010-10-11 10:41:39 +0530712 while (dspi->rcount > 0 || dspi->wcount > 0) {
713 errors = davinci_spi_process_events(dspi);
Brian Niebuhre0d205e2010-09-02 16:52:06 +0530714 if (errors)
715 break;
716 cpu_relax();
Sandeep Paulraj358934a2009-12-16 22:02:18 +0000717 }
718 }
719
Sekhar Nori212d4b62010-10-11 10:41:39 +0530720 clear_io_bits(dspi->base + SPIINT, SPIINT_MASKALL);
Brian Niebuhr87467bd2010-10-06 17:03:10 +0530721 if (spicfg->io_type == SPI_IO_TYPE_DMA) {
Sekhar Nori212d4b62010-10-11 10:41:39 +0530722 clear_io_bits(dspi->base + SPIINT, SPIINT_DMA_REQ_EN);
Matt Porter048177c2012-08-22 21:09:36 -0400723
724 dma_unmap_single(&spi->dev, t->rx_dma,
725 t->len, DMA_FROM_DEVICE);
726 dma_unmap_single(&spi->dev, t->tx_dma,
727 t->len, DMA_TO_DEVICE);
728 kfree(dummy_buf);
Brian Niebuhr87467bd2010-10-06 17:03:10 +0530729 }
Brian Niebuhre0d205e2010-09-02 16:52:06 +0530730
Sekhar Nori212d4b62010-10-11 10:41:39 +0530731 clear_io_bits(dspi->base + SPIGCR1, SPIGCR1_SPIENA_MASK);
732 set_io_bits(dspi->base + SPIGCR1, SPIGCR1_POWERDOWN_MASK);
Brian Niebuhr3f27b572010-10-06 18:25:43 +0530733
Sandeep Paulraj358934a2009-12-16 22:02:18 +0000734 /*
735 * Check for bit error, desync error,parity error,timeout error and
736 * receive overflow errors
737 */
Brian Niebuhr839c9962010-08-23 16:39:19 +0530738 if (errors) {
Sekhar Nori212d4b62010-10-11 10:41:39 +0530739 ret = davinci_spi_check_error(dspi, errors);
Brian Niebuhr839c9962010-08-23 16:39:19 +0530740 WARN(!ret, "%s: error reported but no error found!\n",
741 dev_name(&spi->dev));
Sandeep Paulraj358934a2009-12-16 22:02:18 +0000742 return ret;
Brian Niebuhr839c9962010-08-23 16:39:19 +0530743 }
Sandeep Paulraj358934a2009-12-16 22:02:18 +0000744
Sekhar Nori212d4b62010-10-11 10:41:39 +0530745 if (dspi->rcount != 0 || dspi->wcount != 0) {
Matt Porter048177c2012-08-22 21:09:36 -0400746 dev_err(&spi->dev, "SPI data transfer error\n");
Brian Niebuhr87467bd2010-10-06 17:03:10 +0530747 return -EIO;
748 }
749
Sandeep Paulraj358934a2009-12-16 22:02:18 +0000750 return t->len;
Matt Porter048177c2012-08-22 21:09:36 -0400751
752err_desc:
753 dma_unmap_single(&spi->dev, t->tx_dma, t->len, DMA_TO_DEVICE);
754err_tx_map:
755 dma_unmap_single(&spi->dev, t->rx_dma, t->len, DMA_FROM_DEVICE);
756err_rx_map:
757 kfree(dummy_buf);
758err_alloc_dummy_buf:
759 return ret;
Sandeep Paulraj358934a2009-12-16 22:02:18 +0000760}
761
Brian Niebuhre0d205e2010-09-02 16:52:06 +0530762/**
Murali Karicheri32310aa2012-12-21 15:13:26 -0500763 * dummy_thread_fn - dummy thread function
764 * @irq: IRQ number for this SPI Master
765 * @context_data: structure for SPI Master controller davinci_spi
766 *
767 * This is to satisfy the request_threaded_irq() API so that the irq
768 * handler is called in interrupt context.
769 */
770static irqreturn_t dummy_thread_fn(s32 irq, void *data)
771{
772 return IRQ_HANDLED;
773}
774
775/**
Brian Niebuhre0d205e2010-09-02 16:52:06 +0530776 * davinci_spi_irq - Interrupt handler for SPI Master Controller
777 * @irq: IRQ number for this SPI Master
778 * @context_data: structure for SPI Master controller davinci_spi
779 *
780 * ISR will determine that interrupt arrives either for READ or WRITE command.
781 * According to command it will do the appropriate action. It will check
782 * transfer length and if it is not zero then dispatch transfer command again.
783 * If transfer length is zero then it will indicate the COMPLETION so that
784 * davinci_spi_bufs function can go ahead.
785 */
Sekhar Nori212d4b62010-10-11 10:41:39 +0530786static irqreturn_t davinci_spi_irq(s32 irq, void *data)
Brian Niebuhre0d205e2010-09-02 16:52:06 +0530787{
Sekhar Nori212d4b62010-10-11 10:41:39 +0530788 struct davinci_spi *dspi = data;
Brian Niebuhre0d205e2010-09-02 16:52:06 +0530789 int status;
790
Sekhar Nori212d4b62010-10-11 10:41:39 +0530791 status = davinci_spi_process_events(dspi);
Brian Niebuhre0d205e2010-09-02 16:52:06 +0530792 if (unlikely(status != 0))
Sekhar Nori212d4b62010-10-11 10:41:39 +0530793 clear_io_bits(dspi->base + SPIINT, SPIINT_MASKINT);
Brian Niebuhre0d205e2010-09-02 16:52:06 +0530794
Sekhar Nori212d4b62010-10-11 10:41:39 +0530795 if ((!dspi->rcount && !dspi->wcount) || status)
796 complete(&dspi->done);
Brian Niebuhre0d205e2010-09-02 16:52:06 +0530797
798 return IRQ_HANDLED;
799}
800
Sekhar Nori212d4b62010-10-11 10:41:39 +0530801static int davinci_spi_request_dma(struct davinci_spi *dspi)
Sekhar Nori903ca252010-10-01 14:51:40 +0530802{
Matt Porter048177c2012-08-22 21:09:36 -0400803 dma_cap_mask_t mask;
804 struct device *sdev = dspi->bitbang.master->dev.parent;
Sekhar Nori903ca252010-10-01 14:51:40 +0530805 int r;
806
Matt Porter048177c2012-08-22 21:09:36 -0400807 dma_cap_zero(mask);
808 dma_cap_set(DMA_SLAVE, mask);
809
810 dspi->dma_rx = dma_request_channel(mask, edma_filter_fn,
811 &dspi->dma_rx_chnum);
812 if (!dspi->dma_rx) {
813 dev_err(sdev, "request RX DMA channel failed\n");
814 r = -ENODEV;
Brian Niebuhr523c37e2010-10-04 17:35:34 +0530815 goto rx_dma_failed;
Sekhar Nori903ca252010-10-01 14:51:40 +0530816 }
817
Matt Porter048177c2012-08-22 21:09:36 -0400818 dspi->dma_tx = dma_request_channel(mask, edma_filter_fn,
819 &dspi->dma_tx_chnum);
820 if (!dspi->dma_tx) {
821 dev_err(sdev, "request TX DMA channel failed\n");
822 r = -ENODEV;
Brian Niebuhr523c37e2010-10-04 17:35:34 +0530823 goto tx_dma_failed;
Sekhar Nori903ca252010-10-01 14:51:40 +0530824 }
825
826 return 0;
Matt Porter048177c2012-08-22 21:09:36 -0400827
Brian Niebuhr523c37e2010-10-04 17:35:34 +0530828tx_dma_failed:
Matt Porter048177c2012-08-22 21:09:36 -0400829 dma_release_channel(dspi->dma_rx);
Brian Niebuhr523c37e2010-10-04 17:35:34 +0530830rx_dma_failed:
831 return r;
Sekhar Nori903ca252010-10-01 14:51:40 +0530832}
833
Murali Karicheriaae71472012-12-11 16:20:39 -0500834#if defined(CONFIG_OF)
835static const struct of_device_id davinci_spi_of_match[] = {
836 {
Manjunathappa, Prakash804413f2013-04-03 19:39:06 +0530837 .compatible = "ti,dm6441-spi",
Murali Karicheriaae71472012-12-11 16:20:39 -0500838 },
839 {
Manjunathappa, Prakash804413f2013-04-03 19:39:06 +0530840 .compatible = "ti,da830-spi",
Murali Karicheriaae71472012-12-11 16:20:39 -0500841 .data = (void *)SPI_VERSION_2,
842 },
843 { },
844};
Manjunathappa, Prakash0d2d0cc2013-02-25 16:14:07 +0530845MODULE_DEVICE_TABLE(of, davinci_spi_of_match);
Murali Karicheriaae71472012-12-11 16:20:39 -0500846
847/**
848 * spi_davinci_get_pdata - Get platform data from DTS binding
849 * @pdev: ptr to platform data
850 * @dspi: ptr to driver data
851 *
852 * Parses and populates pdata in dspi from device tree bindings.
853 *
854 * NOTE: Not all platform data params are supported currently.
855 */
856static int spi_davinci_get_pdata(struct platform_device *pdev,
857 struct davinci_spi *dspi)
858{
859 struct device_node *node = pdev->dev.of_node;
860 struct davinci_spi_platform_data *pdata;
861 unsigned int num_cs, intr_line = 0;
862 const struct of_device_id *match;
863
864 pdata = &dspi->pdata;
865
866 pdata->version = SPI_VERSION_1;
Axel Linb53b34f2014-02-06 11:45:08 +0800867 match = of_match_device(davinci_spi_of_match, &pdev->dev);
Murali Karicheriaae71472012-12-11 16:20:39 -0500868 if (!match)
869 return -ENODEV;
870
871 /* match data has the SPI version number for SPI_VERSION_2 */
872 if (match->data == (void *)SPI_VERSION_2)
873 pdata->version = SPI_VERSION_2;
874
875 /*
876 * default num_cs is 1 and all chipsel are internal to the chip
Murali Karicheria88e34e2014-08-01 19:40:32 +0300877 * indicated by chip_sel being NULL or cs_gpios being NULL or
878 * set to -ENOENT. num-cs includes internal as well as gpios.
Murali Karicheriaae71472012-12-11 16:20:39 -0500879 * indicated by chip_sel being NULL. GPIO based CS is not
880 * supported yet in DT bindings.
881 */
882 num_cs = 1;
883 of_property_read_u32(node, "num-cs", &num_cs);
884 pdata->num_chipselect = num_cs;
885 of_property_read_u32(node, "ti,davinci-spi-intr-line", &intr_line);
886 pdata->intr_line = intr_line;
887 return 0;
888}
889#else
Murali Karicheriaae71472012-12-11 16:20:39 -0500890static struct davinci_spi_platform_data
891 *spi_davinci_get_pdata(struct platform_device *pdev,
892 struct davinci_spi *dspi)
893{
894 return -ENODEV;
895}
896#endif
897
Sandeep Paulraj358934a2009-12-16 22:02:18 +0000898/**
Sandeep Paulraj358934a2009-12-16 22:02:18 +0000899 * davinci_spi_probe - probe function for SPI Master Controller
900 * @pdev: platform_device structure which contains plateform specific data
Brian Niebuhr035540f2010-10-06 18:32:40 +0530901 *
902 * According to Linux Device Model this function will be invoked by Linux
903 * with platform_device struct which contains the device specific info.
904 * This function will map the SPI controller's memory, register IRQ,
905 * Reset SPI controller and setting its registers to default value.
906 * It will invoke spi_bitbang_start to create work queue so that client driver
907 * can register transfer method to work queue.
Sandeep Paulraj358934a2009-12-16 22:02:18 +0000908 */
Grant Likelyfd4a3192012-12-07 16:57:14 +0000909static int davinci_spi_probe(struct platform_device *pdev)
Sandeep Paulraj358934a2009-12-16 22:02:18 +0000910{
911 struct spi_master *master;
Sekhar Nori212d4b62010-10-11 10:41:39 +0530912 struct davinci_spi *dspi;
Sandeep Paulraj358934a2009-12-16 22:02:18 +0000913 struct davinci_spi_platform_data *pdata;
Jingoo Han5b3bb592013-12-09 19:12:03 +0900914 struct resource *r;
Sandeep Paulraj358934a2009-12-16 22:02:18 +0000915 resource_size_t dma_rx_chan = SPI_NO_RESOURCE;
916 resource_size_t dma_tx_chan = SPI_NO_RESOURCE;
Grygorii Strashkoc0600142014-08-01 19:40:33 +0300917 int ret = 0;
Brian Niebuhrf34bd4c2010-09-03 11:56:35 +0530918 u32 spipc0;
Sandeep Paulraj358934a2009-12-16 22:02:18 +0000919
Sandeep Paulraj358934a2009-12-16 22:02:18 +0000920 master = spi_alloc_master(&pdev->dev, sizeof(struct davinci_spi));
921 if (master == NULL) {
922 ret = -ENOMEM;
923 goto err;
924 }
925
Jingoo Han24b5a822013-05-23 19:20:40 +0900926 platform_set_drvdata(pdev, master);
Sandeep Paulraj358934a2009-12-16 22:02:18 +0000927
Sekhar Nori212d4b62010-10-11 10:41:39 +0530928 dspi = spi_master_get_devdata(master);
Sandeep Paulraj358934a2009-12-16 22:02:18 +0000929
Jingoo Han8074cf02013-07-30 16:58:59 +0900930 if (dev_get_platdata(&pdev->dev)) {
931 pdata = dev_get_platdata(&pdev->dev);
Murali Karicheriaae71472012-12-11 16:20:39 -0500932 dspi->pdata = *pdata;
933 } else {
934 /* update dspi pdata with that from the DT */
935 ret = spi_davinci_get_pdata(pdev, dspi);
936 if (ret < 0)
937 goto free_master;
938 }
939
940 /* pdata in dspi is now updated and point pdata to that */
941 pdata = &dspi->pdata;
942
Murali Karicheri7480e752014-07-31 20:33:14 +0300943 dspi->bytes_per_word = devm_kzalloc(&pdev->dev,
944 sizeof(*dspi->bytes_per_word) *
945 pdata->num_chipselect, GFP_KERNEL);
946 if (dspi->bytes_per_word == NULL) {
947 ret = -ENOMEM;
948 goto free_master;
949 }
950
Sandeep Paulraj358934a2009-12-16 22:02:18 +0000951 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
952 if (r == NULL) {
953 ret = -ENOENT;
954 goto free_master;
955 }
956
Sekhar Nori212d4b62010-10-11 10:41:39 +0530957 dspi->pbase = r->start;
Sandeep Paulraj358934a2009-12-16 22:02:18 +0000958
Jingoo Han5b3bb592013-12-09 19:12:03 +0900959 dspi->base = devm_ioremap_resource(&pdev->dev, r);
960 if (IS_ERR(dspi->base)) {
961 ret = PTR_ERR(dspi->base);
Sandeep Paulraj358934a2009-12-16 22:02:18 +0000962 goto free_master;
963 }
964
Sekhar Nori212d4b62010-10-11 10:41:39 +0530965 dspi->irq = platform_get_irq(pdev, 0);
966 if (dspi->irq <= 0) {
Brian Niebuhre0d205e2010-09-02 16:52:06 +0530967 ret = -EINVAL;
Jingoo Han5b3bb592013-12-09 19:12:03 +0900968 goto free_master;
Brian Niebuhre0d205e2010-09-02 16:52:06 +0530969 }
970
Jingoo Han5b3bb592013-12-09 19:12:03 +0900971 ret = devm_request_threaded_irq(&pdev->dev, dspi->irq, davinci_spi_irq,
972 dummy_thread_fn, 0, dev_name(&pdev->dev), dspi);
Brian Niebuhre0d205e2010-09-02 16:52:06 +0530973 if (ret)
Jingoo Han5b3bb592013-12-09 19:12:03 +0900974 goto free_master;
Brian Niebuhre0d205e2010-09-02 16:52:06 +0530975
Axel Lin94c69f72013-09-10 15:43:41 +0800976 dspi->bitbang.master = master;
Sandeep Paulraj358934a2009-12-16 22:02:18 +0000977
Jingoo Han5b3bb592013-12-09 19:12:03 +0900978 dspi->clk = devm_clk_get(&pdev->dev, NULL);
Sekhar Nori212d4b62010-10-11 10:41:39 +0530979 if (IS_ERR(dspi->clk)) {
Sandeep Paulraj358934a2009-12-16 22:02:18 +0000980 ret = -ENODEV;
Jingoo Han5b3bb592013-12-09 19:12:03 +0900981 goto free_master;
Sandeep Paulraj358934a2009-12-16 22:02:18 +0000982 }
Murali Karicheriaae71472012-12-11 16:20:39 -0500983 clk_prepare_enable(dspi->clk);
Sandeep Paulraj358934a2009-12-16 22:02:18 +0000984
Murali Karicheriaae71472012-12-11 16:20:39 -0500985 master->dev.of_node = pdev->dev.of_node;
Sandeep Paulraj358934a2009-12-16 22:02:18 +0000986 master->bus_num = pdev->id;
987 master->num_chipselect = pdata->num_chipselect;
Stephen Warren24778be2013-05-21 20:36:35 -0600988 master->bits_per_word_mask = SPI_BPW_RANGE_MASK(2, 16);
Sandeep Paulraj358934a2009-12-16 22:02:18 +0000989 master->setup = davinci_spi_setup;
Murali Karicheri365a7bb2014-09-16 14:25:05 +0300990 master->cleanup = davinci_spi_cleanup;
Sandeep Paulraj358934a2009-12-16 22:02:18 +0000991
Sekhar Nori212d4b62010-10-11 10:41:39 +0530992 dspi->bitbang.chipselect = davinci_spi_chipselect;
993 dspi->bitbang.setup_transfer = davinci_spi_setup_transfer;
Sandeep Paulraj358934a2009-12-16 22:02:18 +0000994
Sekhar Nori212d4b62010-10-11 10:41:39 +0530995 dspi->version = pdata->version;
Sandeep Paulraj358934a2009-12-16 22:02:18 +0000996
Sekhar Nori212d4b62010-10-11 10:41:39 +0530997 dspi->bitbang.flags = SPI_NO_CS | SPI_LSB_FIRST | SPI_LOOP;
998 if (dspi->version == SPI_VERSION_2)
999 dspi->bitbang.flags |= SPI_READY;
Sandeep Paulraj358934a2009-12-16 22:02:18 +00001000
Grygorii Strashko8936dec2014-09-12 17:54:00 +03001001 if (pdev->dev.of_node) {
1002 int i;
1003
1004 for (i = 0; i < pdata->num_chipselect; i++) {
1005 int cs_gpio = of_get_named_gpio(pdev->dev.of_node,
1006 "cs-gpios", i);
1007
1008 if (cs_gpio == -EPROBE_DEFER) {
1009 ret = cs_gpio;
1010 goto free_clk;
1011 }
1012
1013 if (gpio_is_valid(cs_gpio)) {
1014 ret = devm_gpio_request(&pdev->dev, cs_gpio,
1015 dev_name(&pdev->dev));
1016 if (ret)
1017 goto free_clk;
1018 }
1019 }
1020 }
1021
Sekhar Nori903ca252010-10-01 14:51:40 +05301022 r = platform_get_resource(pdev, IORESOURCE_DMA, 0);
1023 if (r)
1024 dma_rx_chan = r->start;
1025 r = platform_get_resource(pdev, IORESOURCE_DMA, 1);
1026 if (r)
1027 dma_tx_chan = r->start;
Sandeep Paulraj358934a2009-12-16 22:02:18 +00001028
Sekhar Nori212d4b62010-10-11 10:41:39 +05301029 dspi->bitbang.txrx_bufs = davinci_spi_bufs;
Sekhar Nori903ca252010-10-01 14:51:40 +05301030 if (dma_rx_chan != SPI_NO_RESOURCE &&
Michael Williamson2e3e2a52011-02-08 07:59:55 -05001031 dma_tx_chan != SPI_NO_RESOURCE) {
Matt Porter048177c2012-08-22 21:09:36 -04001032 dspi->dma_rx_chnum = dma_rx_chan;
1033 dspi->dma_tx_chnum = dma_tx_chan;
Brian Niebuhr96fd8812010-09-27 22:23:23 +05301034
Sekhar Nori212d4b62010-10-11 10:41:39 +05301035 ret = davinci_spi_request_dma(dspi);
Sekhar Nori903ca252010-10-01 14:51:40 +05301036 if (ret)
1037 goto free_clk;
1038
Brian Niebuhr87467bd2010-10-06 17:03:10 +05301039 dev_info(&pdev->dev, "DMA: supported\n");
Jingoo Han859c3372014-09-02 11:48:00 +09001040 dev_info(&pdev->dev, "DMA: RX channel: %pa, TX channel: %pa, event queue: %d\n",
1041 &dma_rx_chan, &dma_tx_chan,
Michael Williamson2e3e2a52011-02-08 07:59:55 -05001042 pdata->dma_event_q);
Sandeep Paulraj358934a2009-12-16 22:02:18 +00001043 }
1044
Sekhar Nori212d4b62010-10-11 10:41:39 +05301045 dspi->get_rx = davinci_spi_rx_buf_u8;
1046 dspi->get_tx = davinci_spi_tx_buf_u8;
Sandeep Paulraj358934a2009-12-16 22:02:18 +00001047
Sekhar Nori212d4b62010-10-11 10:41:39 +05301048 init_completion(&dspi->done);
Brian Niebuhre0d205e2010-09-02 16:52:06 +05301049
Sandeep Paulraj358934a2009-12-16 22:02:18 +00001050 /* Reset In/OUT SPI module */
Sekhar Nori212d4b62010-10-11 10:41:39 +05301051 iowrite32(0, dspi->base + SPIGCR0);
Sandeep Paulraj358934a2009-12-16 22:02:18 +00001052 udelay(100);
Sekhar Nori212d4b62010-10-11 10:41:39 +05301053 iowrite32(1, dspi->base + SPIGCR0);
Sandeep Paulraj358934a2009-12-16 22:02:18 +00001054
Brian Niebuhrbe884712010-09-03 12:15:28 +05301055 /* Set up SPIPC0. CS and ENA init is done in davinci_spi_setup */
Brian Niebuhrf34bd4c2010-09-03 11:56:35 +05301056 spipc0 = SPIPC0_DIFUN_MASK | SPIPC0_DOFUN_MASK | SPIPC0_CLKFUN_MASK;
Sekhar Nori212d4b62010-10-11 10:41:39 +05301057 iowrite32(spipc0, dspi->base + SPIPC0);
Brian Niebuhrf34bd4c2010-09-03 11:56:35 +05301058
Brian Niebuhre0d205e2010-09-02 16:52:06 +05301059 if (pdata->intr_line)
Sekhar Nori212d4b62010-10-11 10:41:39 +05301060 iowrite32(SPI_INTLVL_1, dspi->base + SPILVL);
Brian Niebuhre0d205e2010-09-02 16:52:06 +05301061 else
Sekhar Nori212d4b62010-10-11 10:41:39 +05301062 iowrite32(SPI_INTLVL_0, dspi->base + SPILVL);
Brian Niebuhre0d205e2010-09-02 16:52:06 +05301063
Sekhar Nori212d4b62010-10-11 10:41:39 +05301064 iowrite32(CS_DEFAULT, dspi->base + SPIDEF);
Brian Niebuhr843a7132010-08-12 12:49:05 +05301065
Sandeep Paulraj358934a2009-12-16 22:02:18 +00001066 /* master mode default */
Sekhar Nori212d4b62010-10-11 10:41:39 +05301067 set_io_bits(dspi->base + SPIGCR1, SPIGCR1_CLKMOD_MASK);
1068 set_io_bits(dspi->base + SPIGCR1, SPIGCR1_MASTER_MASK);
1069 set_io_bits(dspi->base + SPIGCR1, SPIGCR1_POWERDOWN_MASK);
Sandeep Paulraj358934a2009-12-16 22:02:18 +00001070
Sekhar Nori212d4b62010-10-11 10:41:39 +05301071 ret = spi_bitbang_start(&dspi->bitbang);
Sandeep Paulraj358934a2009-12-16 22:02:18 +00001072 if (ret)
Sekhar Nori903ca252010-10-01 14:51:40 +05301073 goto free_dma;
Sandeep Paulraj358934a2009-12-16 22:02:18 +00001074
Sekhar Nori212d4b62010-10-11 10:41:39 +05301075 dev_info(&pdev->dev, "Controller at 0x%p\n", dspi->base);
Sandeep Paulraj358934a2009-12-16 22:02:18 +00001076
Sandeep Paulraj358934a2009-12-16 22:02:18 +00001077 return ret;
1078
Sekhar Nori903ca252010-10-01 14:51:40 +05301079free_dma:
Matt Porter048177c2012-08-22 21:09:36 -04001080 dma_release_channel(dspi->dma_rx);
1081 dma_release_channel(dspi->dma_tx);
Sandeep Paulraj358934a2009-12-16 22:02:18 +00001082free_clk:
Murali Karicheriaae71472012-12-11 16:20:39 -05001083 clk_disable_unprepare(dspi->clk);
Sandeep Paulraj358934a2009-12-16 22:02:18 +00001084free_master:
Axel Lin94c69f72013-09-10 15:43:41 +08001085 spi_master_put(master);
Sandeep Paulraj358934a2009-12-16 22:02:18 +00001086err:
1087 return ret;
1088}
1089
1090/**
1091 * davinci_spi_remove - remove function for SPI Master Controller
1092 * @pdev: platform_device structure which contains plateform specific data
1093 *
1094 * This function will do the reverse action of davinci_spi_probe function
1095 * It will free the IRQ and SPI controller's memory region.
1096 * It will also call spi_bitbang_stop to destroy the work queue which was
1097 * created by spi_bitbang_start.
1098 */
Grant Likelyfd4a3192012-12-07 16:57:14 +00001099static int davinci_spi_remove(struct platform_device *pdev)
Sandeep Paulraj358934a2009-12-16 22:02:18 +00001100{
Sekhar Nori212d4b62010-10-11 10:41:39 +05301101 struct davinci_spi *dspi;
Sandeep Paulraj358934a2009-12-16 22:02:18 +00001102 struct spi_master *master;
1103
Jingoo Han24b5a822013-05-23 19:20:40 +09001104 master = platform_get_drvdata(pdev);
Sekhar Nori212d4b62010-10-11 10:41:39 +05301105 dspi = spi_master_get_devdata(master);
Sandeep Paulraj358934a2009-12-16 22:02:18 +00001106
Sekhar Nori212d4b62010-10-11 10:41:39 +05301107 spi_bitbang_stop(&dspi->bitbang);
Sandeep Paulraj358934a2009-12-16 22:02:18 +00001108
Murali Karicheriaae71472012-12-11 16:20:39 -05001109 clk_disable_unprepare(dspi->clk);
Axel Lin94c69f72013-09-10 15:43:41 +08001110 spi_master_put(master);
Sandeep Paulraj358934a2009-12-16 22:02:18 +00001111
1112 return 0;
1113}
1114
1115static struct platform_driver davinci_spi_driver = {
Brian Niebuhrd8c174c2010-10-06 18:47:16 +05301116 .driver = {
1117 .name = "spi_davinci",
Axel Linb53b34f2014-02-06 11:45:08 +08001118 .of_match_table = of_match_ptr(davinci_spi_of_match),
Brian Niebuhrd8c174c2010-10-06 18:47:16 +05301119 },
Grant Likely940ab882011-10-05 11:29:49 -06001120 .probe = davinci_spi_probe,
Grant Likelyfd4a3192012-12-07 16:57:14 +00001121 .remove = davinci_spi_remove,
Sandeep Paulraj358934a2009-12-16 22:02:18 +00001122};
Grant Likely940ab882011-10-05 11:29:49 -06001123module_platform_driver(davinci_spi_driver);
Sandeep Paulraj358934a2009-12-16 22:02:18 +00001124
1125MODULE_DESCRIPTION("TI DaVinci SPI Master Controller Driver");
1126MODULE_LICENSE("GPL");