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gerrit-public.fairphone.software / kernel / msm-4.9 / 218abe6fe31b2059a6a647eddbe9c3ee08fa26fd / . / arch / arm / boot / dts / imx6qdl.dtsi
blob: 8f34a3cd27413782e572f252d5a671fcb0bb7ff6 [file] [log] [blame]
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]1/*
2 * Copyright 2011 Freescale Semiconductor, Inc.
3 * Copyright 2011 Linaro Ltd.
4 *
5 * The code contained herein is licensed under the GNU General Public
6 * License. You may obtain a copy of the GNU General Public License
7 * Version 2 or later at the following locations:
8 *
9 * http://www.opensource.org/licenses/gpl-license.html
10 * http://www.gnu.org/copyleft/gpl.html
11 */
12
13/include/ "skeleton.dtsi"
14
15/ {
16 aliases {
Richard Zhao8f9ffec2011-12-14 09:26:45 +0800[diff] [blame]17 serial0 = &uart1;
18 serial1 = &uart2;
19 serial2 = &uart3;
20 serial3 = &uart4;
21 serial4 = &uart5;
Shawn Guo5230f8f2012-08-05 14:01:28 +0800[diff] [blame]22 gpio0 = &gpio1;
23 gpio1 = &gpio2;
24 gpio2 = &gpio3;
25 gpio3 = &gpio4;
26 gpio4 = &gpio5;
27 gpio5 = &gpio6;
28 gpio6 = &gpio7;
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]29 };
30
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]31 intc: interrupt-controller@00a01000 {
32 compatible = "arm,cortex-a9-gic";
33 #interrupt-cells = <3>;
34 #address-cells = <1>;
35 #size-cells = <1>;
36 interrupt-controller;
37 reg = <0x00a01000 0x1000>,
38 <0x00a00100 0x100>;
39 };
40
41 clocks {
42 #address-cells = <1>;
43 #size-cells = <0>;
44
45 ckil {
46 compatible = "fsl,imx-ckil", "fixed-clock";
47 clock-frequency = <32768>;
48 };
49
50 ckih1 {
51 compatible = "fsl,imx-ckih1", "fixed-clock";
52 clock-frequency = <0>;
53 };
54
55 osc {
56 compatible = "fsl,imx-osc", "fixed-clock";
57 clock-frequency = <24000000>;
58 };
59 };
60
61 soc {
62 #address-cells = <1>;
63 #size-cells = <1>;
64 compatible = "simple-bus";
65 interrupt-parent = <&intc>;
66 ranges;
67
Huang Shijiee5d0f9f2012-06-06 21:22:57 -0400[diff] [blame]68 dma-apbh@00110000 {
69 compatible = "fsl,imx6q-dma-apbh", "fsl,imx28-dma-apbh";
70 reg = <0x00110000 0x2000>;
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame]71 clocks = <&clks 106>;
Huang Shijiee5d0f9f2012-06-06 21:22:57 -0400[diff] [blame]72 };
73
Shawn Guobe4ccfc2012-12-31 11:32:48 +0800[diff] [blame]74 gpmi: gpmi-nand@00112000 {
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame]75 compatible = "fsl,imx6q-gpmi-nand";
76 #address-cells = <1>;
77 #size-cells = <1>;
78 reg = <0x00112000 0x2000>, <0x00114000 0x2000>;
79 reg-names = "gpmi-nand", "bch";
80 interrupts = <0 13 0x04>, <0 15 0x04>;
81 interrupt-names = "gpmi-dma", "bch";
82 clocks = <&clks 152>, <&clks 153>, <&clks 151>,
83 <&clks 150>, <&clks 149>;
84 clock-names = "gpmi_io", "gpmi_apb", "gpmi_bch",
85 "gpmi_bch_apb", "per1_bch";
86 fsl,gpmi-dma-channel = <0>;
87 status = "disabled";
Huang Shijiecf922fa2012-07-01 23:38:46 -0400[diff] [blame]88 };
89
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]90 timer@00a00600 {
Marc Zyngier58458e02012-01-10 19:44:19 +0000[diff] [blame]91 compatible = "arm,cortex-a9-twd-timer";
92 reg = <0x00a00600 0x20>;
93 interrupts = <1 13 0xf01>;
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]94 };
95
96 L2: l2-cache@00a02000 {
97 compatible = "arm,pl310-cache";
98 reg = <0x00a02000 0x1000>;
99 interrupts = <0 92 0x04>;
100 cache-unified;
101 cache-level = <2>;
102 };
103
Dirk Behme218abe62013-02-15 15:10:01 +0100[diff] [blame^]104 pmu {
105 compatible = "arm,cortex-a9-pmu";
106 interrupts = <0 94 0x04>;
107 };
108
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]109 aips-bus@02000000 { /* AIPS1 */
110 compatible = "fsl,aips-bus", "simple-bus";
111 #address-cells = <1>;
112 #size-cells = <1>;
113 reg = <0x02000000 0x100000>;
114 ranges;
115
116 spba-bus@02000000 {
117 compatible = "fsl,spba-bus", "simple-bus";
118 #address-cells = <1>;
119 #size-cells = <1>;
120 reg = <0x02000000 0x40000>;
121 ranges;
122
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]123 spdif: spdif@02004000 {
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]124 reg = <0x02004000 0x4000>;
125 interrupts = <0 52 0x04>;
126 };
127
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]128 ecspi1: ecspi@02008000 {
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]129 #address-cells = <1>;
130 #size-cells = <0>;
131 compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
132 reg = <0x02008000 0x4000>;
133 interrupts = <0 31 0x04>;
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame]134 clocks = <&clks 112>, <&clks 112>;
135 clock-names = "ipg", "per";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]136 status = "disabled";
137 };
138
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]139 ecspi2: ecspi@0200c000 {
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]140 #address-cells = <1>;
141 #size-cells = <0>;
142 compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
143 reg = <0x0200c000 0x4000>;
144 interrupts = <0 32 0x04>;
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame]145 clocks = <&clks 113>, <&clks 113>;
146 clock-names = "ipg", "per";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]147 status = "disabled";
148 };
149
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]150 ecspi3: ecspi@02010000 {
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]151 #address-cells = <1>;
152 #size-cells = <0>;
153 compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
154 reg = <0x02010000 0x4000>;
155 interrupts = <0 33 0x04>;
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame]156 clocks = <&clks 114>, <&clks 114>;
157 clock-names = "ipg", "per";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]158 status = "disabled";
159 };
160
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]161 ecspi4: ecspi@02014000 {
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]162 #address-cells = <1>;
163 #size-cells = <0>;
164 compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
165 reg = <0x02014000 0x4000>;
166 interrupts = <0 34 0x04>;
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame]167 clocks = <&clks 115>, <&clks 115>;
168 clock-names = "ipg", "per";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]169 status = "disabled";
170 };
171
Shawn Guo0c456cf2012-04-02 14:39:26 +0800[diff] [blame]172 uart1: serial@02020000 {
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]173 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
174 reg = <0x02020000 0x4000>;
175 interrupts = <0 26 0x04>;
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame]176 clocks = <&clks 160>, <&clks 161>;
177 clock-names = "ipg", "per";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]178 status = "disabled";
179 };
180
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]181 esai: esai@02024000 {
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]182 reg = <0x02024000 0x4000>;
183 interrupts = <0 51 0x04>;
184 };
185
Richard Zhaob1a5da82012-05-02 10:29:10 +0800[diff] [blame]186 ssi1: ssi@02028000 {
187 compatible = "fsl,imx6q-ssi","fsl,imx21-ssi";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]188 reg = <0x02028000 0x4000>;
189 interrupts = <0 46 0x04>;
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame]190 clocks = <&clks 178>;
Richard Zhaob1a5da82012-05-02 10:29:10 +0800[diff] [blame]191 fsl,fifo-depth = <15>;
192 fsl,ssi-dma-events = <38 37>;
193 status = "disabled";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]194 };
195
Richard Zhaob1a5da82012-05-02 10:29:10 +0800[diff] [blame]196 ssi2: ssi@0202c000 {
197 compatible = "fsl,imx6q-ssi","fsl,imx21-ssi";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]198 reg = <0x0202c000 0x4000>;
199 interrupts = <0 47 0x04>;
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame]200 clocks = <&clks 179>;
Richard Zhaob1a5da82012-05-02 10:29:10 +0800[diff] [blame]201 fsl,fifo-depth = <15>;
202 fsl,ssi-dma-events = <42 41>;
203 status = "disabled";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]204 };
205
Richard Zhaob1a5da82012-05-02 10:29:10 +0800[diff] [blame]206 ssi3: ssi@02030000 {
207 compatible = "fsl,imx6q-ssi","fsl,imx21-ssi";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]208 reg = <0x02030000 0x4000>;
209 interrupts = <0 48 0x04>;
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame]210 clocks = <&clks 180>;
Richard Zhaob1a5da82012-05-02 10:29:10 +0800[diff] [blame]211 fsl,fifo-depth = <15>;
212 fsl,ssi-dma-events = <46 45>;
213 status = "disabled";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]214 };
215
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]216 asrc: asrc@02034000 {
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]217 reg = <0x02034000 0x4000>;
218 interrupts = <0 50 0x04>;
219 };
220
221 spba@0203c000 {
222 reg = <0x0203c000 0x4000>;
223 };
224 };
225
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]226 vpu: vpu@02040000 {
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]227 reg = <0x02040000 0x3c000>;
228 interrupts = <0 3 0x04 0 12 0x04>;
229 };
230
231 aipstz@0207c000 { /* AIPSTZ1 */
232 reg = <0x0207c000 0x4000>;
233 };
234
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]235 pwm1: pwm@02080000 {
Sascha Hauer33b38582012-11-21 12:18:28 +0100[diff] [blame]236 #pwm-cells = <2>;
237 compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]238 reg = <0x02080000 0x4000>;
239 interrupts = <0 83 0x04>;
Sascha Hauer33b38582012-11-21 12:18:28 +0100[diff] [blame]240 clocks = <&clks 62>, <&clks 145>;
241 clock-names = "ipg", "per";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]242 };
243
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]244 pwm2: pwm@02084000 {
Sascha Hauer33b38582012-11-21 12:18:28 +0100[diff] [blame]245 #pwm-cells = <2>;
246 compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]247 reg = <0x02084000 0x4000>;
248 interrupts = <0 84 0x04>;
Sascha Hauer33b38582012-11-21 12:18:28 +0100[diff] [blame]249 clocks = <&clks 62>, <&clks 146>;
250 clock-names = "ipg", "per";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]251 };
252
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]253 pwm3: pwm@02088000 {
Sascha Hauer33b38582012-11-21 12:18:28 +0100[diff] [blame]254 #pwm-cells = <2>;
255 compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]256 reg = <0x02088000 0x4000>;
257 interrupts = <0 85 0x04>;
Sascha Hauer33b38582012-11-21 12:18:28 +0100[diff] [blame]258 clocks = <&clks 62>, <&clks 147>;
259 clock-names = "ipg", "per";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]260 };
261
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]262 pwm4: pwm@0208c000 {
Sascha Hauer33b38582012-11-21 12:18:28 +0100[diff] [blame]263 #pwm-cells = <2>;
264 compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]265 reg = <0x0208c000 0x4000>;
266 interrupts = <0 86 0x04>;
Sascha Hauer33b38582012-11-21 12:18:28 +0100[diff] [blame]267 clocks = <&clks 62>, <&clks 148>;
268 clock-names = "ipg", "per";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]269 };
270
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]271 can1: flexcan@02090000 {
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]272 reg = <0x02090000 0x4000>;
273 interrupts = <0 110 0x04>;
274 };
275
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]276 can2: flexcan@02094000 {
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]277 reg = <0x02094000 0x4000>;
278 interrupts = <0 111 0x04>;
279 };
280
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]281 gpt: gpt@02098000 {
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]282 compatible = "fsl,imx6q-gpt";
283 reg = <0x02098000 0x4000>;
284 interrupts = <0 55 0x04>;
285 };
286
Richard Zhao4d191862011-12-14 09:26:44 +0800[diff] [blame]287 gpio1: gpio@0209c000 {
Benoît Thébaudeauaeb27742012-06-22 21:04:06 +0200[diff] [blame]288 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]289 reg = <0x0209c000 0x4000>;
290 interrupts = <0 66 0x04 0 67 0x04>;
291 gpio-controller;
292 #gpio-cells = <2>;
293 interrupt-controller;
Shawn Guo88cde8b2012-07-06 20:03:37 +0800[diff] [blame]294 #interrupt-cells = <2>;
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]295 };
296
Richard Zhao4d191862011-12-14 09:26:44 +0800[diff] [blame]297 gpio2: gpio@020a0000 {
Benoît Thébaudeauaeb27742012-06-22 21:04:06 +0200[diff] [blame]298 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]299 reg = <0x020a0000 0x4000>;
300 interrupts = <0 68 0x04 0 69 0x04>;
301 gpio-controller;
302 #gpio-cells = <2>;
303 interrupt-controller;
Shawn Guo88cde8b2012-07-06 20:03:37 +0800[diff] [blame]304 #interrupt-cells = <2>;
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]305 };
306
Richard Zhao4d191862011-12-14 09:26:44 +0800[diff] [blame]307 gpio3: gpio@020a4000 {
Benoît Thébaudeauaeb27742012-06-22 21:04:06 +0200[diff] [blame]308 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]309 reg = <0x020a4000 0x4000>;
310 interrupts = <0 70 0x04 0 71 0x04>;
311 gpio-controller;
312 #gpio-cells = <2>;
313 interrupt-controller;
Shawn Guo88cde8b2012-07-06 20:03:37 +0800[diff] [blame]314 #interrupt-cells = <2>;
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]315 };
316
Richard Zhao4d191862011-12-14 09:26:44 +0800[diff] [blame]317 gpio4: gpio@020a8000 {
Benoît Thébaudeauaeb27742012-06-22 21:04:06 +0200[diff] [blame]318 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]319 reg = <0x020a8000 0x4000>;
320 interrupts = <0 72 0x04 0 73 0x04>;
321 gpio-controller;
322 #gpio-cells = <2>;
323 interrupt-controller;
Shawn Guo88cde8b2012-07-06 20:03:37 +0800[diff] [blame]324 #interrupt-cells = <2>;
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]325 };
326
Richard Zhao4d191862011-12-14 09:26:44 +0800[diff] [blame]327 gpio5: gpio@020ac000 {
Benoît Thébaudeauaeb27742012-06-22 21:04:06 +0200[diff] [blame]328 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]329 reg = <0x020ac000 0x4000>;
330 interrupts = <0 74 0x04 0 75 0x04>;
331 gpio-controller;
332 #gpio-cells = <2>;
333 interrupt-controller;
Shawn Guo88cde8b2012-07-06 20:03:37 +0800[diff] [blame]334 #interrupt-cells = <2>;
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]335 };
336
Richard Zhao4d191862011-12-14 09:26:44 +0800[diff] [blame]337 gpio6: gpio@020b0000 {
Benoît Thébaudeauaeb27742012-06-22 21:04:06 +0200[diff] [blame]338 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]339 reg = <0x020b0000 0x4000>;
340 interrupts = <0 76 0x04 0 77 0x04>;
341 gpio-controller;
342 #gpio-cells = <2>;
343 interrupt-controller;
Shawn Guo88cde8b2012-07-06 20:03:37 +0800[diff] [blame]344 #interrupt-cells = <2>;
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]345 };
346
Richard Zhao4d191862011-12-14 09:26:44 +0800[diff] [blame]347 gpio7: gpio@020b4000 {
Benoît Thébaudeauaeb27742012-06-22 21:04:06 +0200[diff] [blame]348 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]349 reg = <0x020b4000 0x4000>;
350 interrupts = <0 78 0x04 0 79 0x04>;
351 gpio-controller;
352 #gpio-cells = <2>;
353 interrupt-controller;
Shawn Guo88cde8b2012-07-06 20:03:37 +0800[diff] [blame]354 #interrupt-cells = <2>;
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]355 };
356
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]357 kpp: kpp@020b8000 {
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]358 reg = <0x020b8000 0x4000>;
359 interrupts = <0 82 0x04>;
360 };
361
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]362 wdog1: wdog@020bc000 {
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]363 compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt";
364 reg = <0x020bc000 0x4000>;
365 interrupts = <0 80 0x04>;
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame]366 clocks = <&clks 0>;
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]367 };
368
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]369 wdog2: wdog@020c0000 {
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]370 compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt";
371 reg = <0x020c0000 0x4000>;
372 interrupts = <0 81 0x04>;
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame]373 clocks = <&clks 0>;
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]374 status = "disabled";
375 };
376
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame]377 clks: ccm@020c4000 {
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]378 compatible = "fsl,imx6q-ccm";
379 reg = <0x020c4000 0x4000>;
380 interrupts = <0 87 0x04 0 88 0x04>;
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame]381 #clock-cells = <1>;
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]382 };
383
Dong Aishengbaa64152012-09-05 10:57:15 +0800[diff] [blame]384 anatop: anatop@020c8000 {
385 compatible = "fsl,imx6q-anatop", "syscon", "simple-bus";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]386 reg = <0x020c8000 0x1000>;
387 interrupts = <0 49 0x04 0 54 0x04 0 127 0x04>;
Ying-Chun Liu (PaulLiu)a1e327e2012-03-30 21:46:53 +0800[diff] [blame]388
389 regulator-1p1@110 {
390 compatible = "fsl,anatop-regulator";
391 regulator-name = "vdd1p1";
392 regulator-min-microvolt = <800000>;
393 regulator-max-microvolt = <1375000>;
394 regulator-always-on;
395 anatop-reg-offset = <0x110>;
396 anatop-vol-bit-shift = <8>;
397 anatop-vol-bit-width = <5>;
398 anatop-min-bit-val = <4>;
399 anatop-min-voltage = <800000>;
400 anatop-max-voltage = <1375000>;
401 };
402
403 regulator-3p0@120 {
404 compatible = "fsl,anatop-regulator";
405 regulator-name = "vdd3p0";
406 regulator-min-microvolt = <2800000>;
407 regulator-max-microvolt = <3150000>;
408 regulator-always-on;
409 anatop-reg-offset = <0x120>;
410 anatop-vol-bit-shift = <8>;
411 anatop-vol-bit-width = <5>;
412 anatop-min-bit-val = <0>;
413 anatop-min-voltage = <2625000>;
414 anatop-max-voltage = <3400000>;
415 };
416
417 regulator-2p5@130 {
418 compatible = "fsl,anatop-regulator";
419 regulator-name = "vdd2p5";
420 regulator-min-microvolt = <2000000>;
421 regulator-max-microvolt = <2750000>;
422 regulator-always-on;
423 anatop-reg-offset = <0x130>;
424 anatop-vol-bit-shift = <8>;
425 anatop-vol-bit-width = <5>;
426 anatop-min-bit-val = <0>;
427 anatop-min-voltage = <2000000>;
428 anatop-max-voltage = <2750000>;
429 };
430
Shawn Guo96574a62013-01-08 14:25:14 +0800[diff] [blame]431 reg_arm: regulator-vddcore@140 {
Ying-Chun Liu (PaulLiu)a1e327e2012-03-30 21:46:53 +0800[diff] [blame]432 compatible = "fsl,anatop-regulator";
433 regulator-name = "cpu";
434 regulator-min-microvolt = <725000>;
435 regulator-max-microvolt = <1450000>;
436 regulator-always-on;
437 anatop-reg-offset = <0x140>;
438 anatop-vol-bit-shift = <0>;
439 anatop-vol-bit-width = <5>;
Anson Huang46743dd2013-01-30 17:33:44 -0500[diff] [blame]440 anatop-delay-reg-offset = <0x170>;
441 anatop-delay-bit-shift = <24>;
442 anatop-delay-bit-width = <2>;
Ying-Chun Liu (PaulLiu)a1e327e2012-03-30 21:46:53 +0800[diff] [blame]443 anatop-min-bit-val = <1>;
444 anatop-min-voltage = <725000>;
445 anatop-max-voltage = <1450000>;
446 };
447
Shawn Guo96574a62013-01-08 14:25:14 +0800[diff] [blame]448 reg_pu: regulator-vddpu@140 {
Ying-Chun Liu (PaulLiu)a1e327e2012-03-30 21:46:53 +0800[diff] [blame]449 compatible = "fsl,anatop-regulator";
450 regulator-name = "vddpu";
451 regulator-min-microvolt = <725000>;
452 regulator-max-microvolt = <1450000>;
453 regulator-always-on;
454 anatop-reg-offset = <0x140>;
455 anatop-vol-bit-shift = <9>;
456 anatop-vol-bit-width = <5>;
Anson Huang46743dd2013-01-30 17:33:44 -0500[diff] [blame]457 anatop-delay-reg-offset = <0x170>;
458 anatop-delay-bit-shift = <26>;
459 anatop-delay-bit-width = <2>;
Ying-Chun Liu (PaulLiu)a1e327e2012-03-30 21:46:53 +0800[diff] [blame]460 anatop-min-bit-val = <1>;
461 anatop-min-voltage = <725000>;
462 anatop-max-voltage = <1450000>;
463 };
464
Shawn Guo96574a62013-01-08 14:25:14 +0800[diff] [blame]465 reg_soc: regulator-vddsoc@140 {
Ying-Chun Liu (PaulLiu)a1e327e2012-03-30 21:46:53 +0800[diff] [blame]466 compatible = "fsl,anatop-regulator";
467 regulator-name = "vddsoc";
468 regulator-min-microvolt = <725000>;
469 regulator-max-microvolt = <1450000>;
470 regulator-always-on;
471 anatop-reg-offset = <0x140>;
472 anatop-vol-bit-shift = <18>;
473 anatop-vol-bit-width = <5>;
Anson Huang46743dd2013-01-30 17:33:44 -0500[diff] [blame]474 anatop-delay-reg-offset = <0x170>;
475 anatop-delay-bit-shift = <28>;
476 anatop-delay-bit-width = <2>;
Ying-Chun Liu (PaulLiu)a1e327e2012-03-30 21:46:53 +0800[diff] [blame]477 anatop-min-bit-val = <1>;
478 anatop-min-voltage = <725000>;
479 anatop-max-voltage = <1450000>;
480 };
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]481 };
482
Richard Zhao74bd88f2012-07-12 14:21:41 +0800[diff] [blame]483 usbphy1: usbphy@020c9000 {
484 compatible = "fsl,imx6q-usbphy", "fsl,imx23-usbphy";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]485 reg = <0x020c9000 0x1000>;
486 interrupts = <0 44 0x04>;
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame]487 clocks = <&clks 182>;
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]488 };
489
Richard Zhao74bd88f2012-07-12 14:21:41 +0800[diff] [blame]490 usbphy2: usbphy@020ca000 {
491 compatible = "fsl,imx6q-usbphy", "fsl,imx23-usbphy";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]492 reg = <0x020ca000 0x1000>;
493 interrupts = <0 45 0x04>;
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame]494 clocks = <&clks 183>;
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]495 };
496
497 snvs@020cc000 {
Shawn Guoc9250382012-07-02 20:13:03 +0800[diff] [blame]498 compatible = "fsl,sec-v4.0-mon", "simple-bus";
499 #address-cells = <1>;
500 #size-cells = <1>;
501 ranges = <0 0x020cc000 0x4000>;
502
503 snvs-rtc-lp@34 {
504 compatible = "fsl,sec-v4.0-mon-rtc-lp";
505 reg = <0x34 0x58>;
506 interrupts = <0 19 0x04 0 20 0x04>;
507 };
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]508 };
509
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]510 epit1: epit@020d0000 { /* EPIT1 */
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]511 reg = <0x020d0000 0x4000>;
512 interrupts = <0 56 0x04>;
513 };
514
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]515 epit2: epit@020d4000 { /* EPIT2 */
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]516 reg = <0x020d4000 0x4000>;
517 interrupts = <0 57 0x04>;
518 };
519
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]520 src: src@020d8000 {
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]521 compatible = "fsl,imx6q-src";
522 reg = <0x020d8000 0x4000>;
523 interrupts = <0 91 0x04 0 96 0x04>;
524 };
525
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]526 gpc: gpc@020dc000 {
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]527 compatible = "fsl,imx6q-gpc";
528 reg = <0x020dc000 0x4000>;
529 interrupts = <0 89 0x04 0 90 0x04>;
530 };
531
Dong Aishengdf37e0c2012-09-05 10:57:14 +0800[diff] [blame]532 gpr: iomuxc-gpr@020e0000 {
533 compatible = "fsl,imx6q-iomuxc-gpr", "syscon";
534 reg = <0x020e0000 0x38>;
535 };
536
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]537 dcic1: dcic@020e4000 {
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]538 reg = <0x020e4000 0x4000>;
539 interrupts = <0 124 0x04>;
540 };
541
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]542 dcic2: dcic@020e8000 {
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]543 reg = <0x020e8000 0x4000>;
544 interrupts = <0 125 0x04>;
545 };
546
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]547 sdma: sdma@020ec000 {
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]548 compatible = "fsl,imx6q-sdma", "fsl,imx35-sdma";
549 reg = <0x020ec000 0x4000>;
550 interrupts = <0 2 0x04>;
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame]551 clocks = <&clks 155>, <&clks 155>;
552 clock-names = "ipg", "ahb";
Fabio Estevamd6b9c592013-01-17 12:13:25 -0200[diff] [blame]553 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6q.bin";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]554 };
555 };
556
557 aips-bus@02100000 { /* AIPS2 */
558 compatible = "fsl,aips-bus", "simple-bus";
559 #address-cells = <1>;
560 #size-cells = <1>;
561 reg = <0x02100000 0x100000>;
562 ranges;
563
564 caam@02100000 {
565 reg = <0x02100000 0x40000>;
566 interrupts = <0 105 0x04 0 106 0x04>;
567 };
568
569 aipstz@0217c000 { /* AIPSTZ2 */
570 reg = <0x0217c000 0x4000>;
571 };
572
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]573 usbotg: usb@02184000 {
Richard Zhao74bd88f2012-07-12 14:21:41 +0800[diff] [blame]574 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
575 reg = <0x02184000 0x200>;
576 interrupts = <0 43 0x04>;
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame]577 clocks = <&clks 162>;
Richard Zhao74bd88f2012-07-12 14:21:41 +0800[diff] [blame]578 fsl,usbphy = <&usbphy1>;
Richard Zhao28342c62012-09-14 14:42:45 +0800[diff] [blame]579 fsl,usbmisc = <&usbmisc 0>;
Richard Zhao74bd88f2012-07-12 14:21:41 +0800[diff] [blame]580 status = "disabled";
581 };
582
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]583 usbh1: usb@02184200 {
Richard Zhao74bd88f2012-07-12 14:21:41 +0800[diff] [blame]584 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
585 reg = <0x02184200 0x200>;
586 interrupts = <0 40 0x04>;
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame]587 clocks = <&clks 162>;
Richard Zhao74bd88f2012-07-12 14:21:41 +0800[diff] [blame]588 fsl,usbphy = <&usbphy2>;
Richard Zhao28342c62012-09-14 14:42:45 +0800[diff] [blame]589 fsl,usbmisc = <&usbmisc 1>;
Richard Zhao74bd88f2012-07-12 14:21:41 +0800[diff] [blame]590 status = "disabled";
591 };
592
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]593 usbh2: usb@02184400 {
Richard Zhao74bd88f2012-07-12 14:21:41 +0800[diff] [blame]594 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
595 reg = <0x02184400 0x200>;
596 interrupts = <0 41 0x04>;
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame]597 clocks = <&clks 162>;
Richard Zhao28342c62012-09-14 14:42:45 +0800[diff] [blame]598 fsl,usbmisc = <&usbmisc 2>;
Richard Zhao74bd88f2012-07-12 14:21:41 +0800[diff] [blame]599 status = "disabled";
600 };
601
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]602 usbh3: usb@02184600 {
Richard Zhao74bd88f2012-07-12 14:21:41 +0800[diff] [blame]603 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
604 reg = <0x02184600 0x200>;
605 interrupts = <0 42 0x04>;
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame]606 clocks = <&clks 162>;
Richard Zhao28342c62012-09-14 14:42:45 +0800[diff] [blame]607 fsl,usbmisc = <&usbmisc 3>;
Richard Zhao74bd88f2012-07-12 14:21:41 +0800[diff] [blame]608 status = "disabled";
609 };
610
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]611 usbmisc: usbmisc: usbmisc@02184800 {
Richard Zhao28342c62012-09-14 14:42:45 +0800[diff] [blame]612 #index-cells = <1>;
613 compatible = "fsl,imx6q-usbmisc";
614 reg = <0x02184800 0x200>;
615 clocks = <&clks 162>;
616 };
617
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]618 fec: ethernet@02188000 {
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]619 compatible = "fsl,imx6q-fec";
620 reg = <0x02188000 0x4000>;
621 interrupts = <0 118 0x04 0 119 0x04>;
Frank Li8dd5c662013-02-05 14:21:06 +0800[diff] [blame]622 clocks = <&clks 117>, <&clks 117>, <&clks 190>;
Frank Li76298382012-10-30 18:24:57 +0000[diff] [blame]623 clock-names = "ipg", "ahb", "ptp";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]624 status = "disabled";
625 };
626
627 mlb@0218c000 {
628 reg = <0x0218c000 0x4000>;
629 interrupts = <0 53 0x04 0 117 0x04 0 126 0x04>;
630 };
631
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]632 usdhc1: usdhc@02190000 {
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]633 compatible = "fsl,imx6q-usdhc";
634 reg = <0x02190000 0x4000>;
635 interrupts = <0 22 0x04>;
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame]636 clocks = <&clks 163>, <&clks 163>, <&clks 163>;
637 clock-names = "ipg", "ahb", "per";
Sascha Hauerc104b6a2012-09-25 11:49:33 +0200[diff] [blame]638 bus-width = <4>;
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]639 status = "disabled";
640 };
641
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]642 usdhc2: usdhc@02194000 {
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]643 compatible = "fsl,imx6q-usdhc";
644 reg = <0x02194000 0x4000>;
645 interrupts = <0 23 0x04>;
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame]646 clocks = <&clks 164>, <&clks 164>, <&clks 164>;
647 clock-names = "ipg", "ahb", "per";
Sascha Hauerc104b6a2012-09-25 11:49:33 +0200[diff] [blame]648 bus-width = <4>;
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]649 status = "disabled";
650 };
651
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]652 usdhc3: usdhc@02198000 {
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]653 compatible = "fsl,imx6q-usdhc";
654 reg = <0x02198000 0x4000>;
655 interrupts = <0 24 0x04>;
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame]656 clocks = <&clks 165>, <&clks 165>, <&clks 165>;
657 clock-names = "ipg", "ahb", "per";
Sascha Hauerc104b6a2012-09-25 11:49:33 +0200[diff] [blame]658 bus-width = <4>;
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]659 status = "disabled";
660 };
661
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]662 usdhc4: usdhc@0219c000 {
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]663 compatible = "fsl,imx6q-usdhc";
664 reg = <0x0219c000 0x4000>;
665 interrupts = <0 25 0x04>;
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame]666 clocks = <&clks 166>, <&clks 166>, <&clks 166>;
667 clock-names = "ipg", "ahb", "per";
Sascha Hauerc104b6a2012-09-25 11:49:33 +0200[diff] [blame]668 bus-width = <4>;
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]669 status = "disabled";
670 };
671
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]672 i2c1: i2c@021a0000 {
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]673 #address-cells = <1>;
674 #size-cells = <0>;
Shawn Guo5bdfba22012-09-14 15:19:00 +0800[diff] [blame]675 compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]676 reg = <0x021a0000 0x4000>;
677 interrupts = <0 36 0x04>;
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame]678 clocks = <&clks 125>;
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]679 status = "disabled";
680 };
681
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]682 i2c2: i2c@021a4000 {
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]683 #address-cells = <1>;
684 #size-cells = <0>;
Shawn Guo5bdfba22012-09-14 15:19:00 +0800[diff] [blame]685 compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]686 reg = <0x021a4000 0x4000>;
687 interrupts = <0 37 0x04>;
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame]688 clocks = <&clks 126>;
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]689 status = "disabled";
690 };
691
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]692 i2c3: i2c@021a8000 {
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]693 #address-cells = <1>;
694 #size-cells = <0>;
Shawn Guo5bdfba22012-09-14 15:19:00 +0800[diff] [blame]695 compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]696 reg = <0x021a8000 0x4000>;
697 interrupts = <0 38 0x04>;
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame]698 clocks = <&clks 127>;
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]699 status = "disabled";
700 };
701
702 romcp@021ac000 {
703 reg = <0x021ac000 0x4000>;
704 };
705
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]706 mmdc0: mmdc@021b0000 { /* MMDC0 */
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]707 compatible = "fsl,imx6q-mmdc";
708 reg = <0x021b0000 0x4000>;
709 };
710
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]711 mmdc1: mmdc@021b4000 { /* MMDC1 */
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]712 reg = <0x021b4000 0x4000>;
713 };
714
715 weim@021b8000 {
716 reg = <0x021b8000 0x4000>;
717 interrupts = <0 14 0x04>;
718 };
719
720 ocotp@021bc000 {
Shawn Guo96574a62013-01-08 14:25:14 +0800[diff] [blame]721 compatible = "fsl,imx6q-ocotp";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]722 reg = <0x021bc000 0x4000>;
723 };
724
725 ocotp@021c0000 {
726 reg = <0x021c0000 0x4000>;
727 interrupts = <0 21 0x04>;
728 };
729
730 tzasc@021d0000 { /* TZASC1 */
731 reg = <0x021d0000 0x4000>;
732 interrupts = <0 108 0x04>;
733 };
734
735 tzasc@021d4000 { /* TZASC2 */
736 reg = <0x021d4000 0x4000>;
737 interrupts = <0 109 0x04>;
738 };
739
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]740 audmux: audmux@021d8000 {
Richard Zhaof965cd52012-05-02 10:32:26 +0800[diff] [blame]741 compatible = "fsl,imx6q-audmux", "fsl,imx31-audmux";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]742 reg = <0x021d8000 0x4000>;
Richard Zhaof965cd52012-05-02 10:32:26 +0800[diff] [blame]743 status = "disabled";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]744 };
745
746 mipi@021dc000 { /* MIPI-CSI */
747 reg = <0x021dc000 0x4000>;
748 };
749
750 mipi@021e0000 { /* MIPI-DSI */
751 reg = <0x021e0000 0x4000>;
752 };
753
754 vdoa@021e4000 {
755 reg = <0x021e4000 0x4000>;
756 interrupts = <0 18 0x04>;
757 };
758
Shawn Guo0c456cf2012-04-02 14:39:26 +0800[diff] [blame]759 uart2: serial@021e8000 {
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]760 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
761 reg = <0x021e8000 0x4000>;
762 interrupts = <0 27 0x04>;
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame]763 clocks = <&clks 160>, <&clks 161>;
764 clock-names = "ipg", "per";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]765 status = "disabled";
766 };
767
Shawn Guo0c456cf2012-04-02 14:39:26 +0800[diff] [blame]768 uart3: serial@021ec000 {
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]769 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
770 reg = <0x021ec000 0x4000>;
771 interrupts = <0 28 0x04>;
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame]772 clocks = <&clks 160>, <&clks 161>;
773 clock-names = "ipg", "per";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]774 status = "disabled";
775 };
776
Shawn Guo0c456cf2012-04-02 14:39:26 +0800[diff] [blame]777 uart4: serial@021f0000 {
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]778 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
779 reg = <0x021f0000 0x4000>;
780 interrupts = <0 29 0x04>;
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame]781 clocks = <&clks 160>, <&clks 161>;
782 clock-names = "ipg", "per";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]783 status = "disabled";
784 };
785
Shawn Guo0c456cf2012-04-02 14:39:26 +0800[diff] [blame]786 uart5: serial@021f4000 {
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]787 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
788 reg = <0x021f4000 0x4000>;
789 interrupts = <0 30 0x04>;
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame]790 clocks = <&clks 160>, <&clks 161>;
791 clock-names = "ipg", "per";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]792 status = "disabled";
793 };
794 };
Sascha Hauer91660d72012-11-12 15:52:21 +0100[diff] [blame]795
796 ipu1: ipu@02400000 {
797 #crtc-cells = <1>;
798 compatible = "fsl,imx6q-ipu";
799 reg = <0x02400000 0x400000>;
800 interrupts = <0 6 0x4 0 5 0x4>;
801 clocks = <&clks 130>, <&clks 131>, <&clks 132>;
802 clock-names = "bus", "di0", "di1";
803 };
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]804 };
805};