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gerrit-public.fairphone.software / kernel / msm-4.9 / 23c14ed2eccc925c2afabcfb7e46b4b45d7fdf70 / . / drivers / gpu / drm / nouveau / core / subdev / device / nvc0.c
blob: e0ad5b104e5035a90d7ace6fa3abca519d3c3ed6 [file] [log] [blame]
Ben Skeggs9274f4a2012-07-06 07:36:43 +1000[diff] [blame]1/*
2 * Copyright 2012 Red Hat Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Ben Skeggs
23 */
24
25#include <subdev/device.h>
Ben Skeggs70c0f262012-07-10 10:49:22 +1000[diff] [blame]26#include <subdev/bios.h>
Ben Skeggse0996ae2012-07-10 12:20:17 +1000[diff] [blame]27#include <subdev/gpio.h>
Ben Skeggs4196faa2012-07-10 14:36:38 +1000[diff] [blame]28#include <subdev/i2c.h>
Ben Skeggs8aceb7d2012-07-10 16:45:24 +1000[diff] [blame]29#include <subdev/clock.h>
Martin Peresaa1b9b42012-09-02 02:55:58 +0200[diff] [blame]30#include <subdev/therm.h>
Ben Skeggsd38ac522012-07-22 16:41:26 +1000[diff] [blame]31#include <subdev/mxm.h>
Ben Skeggscb75d972012-07-11 10:44:20 +1000[diff] [blame]32#include <subdev/devinit.h>
Ben Skeggs7d9115d2012-07-11 15:58:56 +1000[diff] [blame]33#include <subdev/mc.h>
Ben Skeggs5a5c7432012-07-11 16:08:25 +1000[diff] [blame]34#include <subdev/timer.h>
Ben Skeggs861d2102012-07-11 19:05:01 +1000[diff] [blame]35#include <subdev/fb.h>
36#include <subdev/ltcg.h>
Ben Skeggsc0abf5c2012-09-26 13:05:01 +1000[diff] [blame]37#include <subdev/ibus.h>
Ben Skeggs3863c9b2012-07-14 19:09:17 +1000[diff] [blame]38#include <subdev/instmem.h>
39#include <subdev/vm.h>
40#include <subdev/bar.h>
Ben Skeggs9274f4a2012-07-06 07:36:43 +1000[diff] [blame]41
Ben Skeggsebb945a2012-07-20 08:17:34 +1000[diff] [blame]42#include <engine/dmaobj.h>
43#include <engine/fifo.h>
44#include <engine/software.h>
45#include <engine/graph.h>
46#include <engine/vp.h>
47#include <engine/bsp.h>
48#include <engine/ppp.h>
49#include <engine/copy.h>
50#include <engine/disp.h>
51
Ben Skeggs9274f4a2012-07-06 07:36:43 +1000[diff] [blame]52int
53nvc0_identify(struct nouveau_device *device)
54{
55 switch (device->chipset) {
56 case 0xc0:
Ben Skeggs2094dd82012-07-27 08:28:20 +1000[diff] [blame]57 device->cname = "GF100";
Ben Skeggs70c0f262012-07-10 10:49:22 +1000[diff] [blame]58 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
Ben Skeggse0996ae2012-07-10 12:20:17 +1000[diff] [blame]59 device->oclass[NVDEV_SUBDEV_GPIO ] = &nv50_gpio_oclass;
Ben Skeggs4196faa2012-07-10 14:36:38 +1000[diff] [blame]60 device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass;
Ben Skeggs8aceb7d2012-07-10 16:45:24 +1000[diff] [blame]61 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nvc0_clock_oclass;
Martin Peresaa1b9b42012-09-02 02:55:58 +0200[diff] [blame]62 device->oclass[NVDEV_SUBDEV_THERM ] = &nv50_therm_oclass;
Ben Skeggsd38ac522012-07-22 16:41:26 +1000[diff] [blame]63 device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
Ben Skeggscb75d972012-07-11 10:44:20 +1000[diff] [blame]64 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv50_devinit_oclass;
Ben Skeggs7d9115d2012-07-11 15:58:56 +1000[diff] [blame]65 device->oclass[NVDEV_SUBDEV_MC ] = &nvc0_mc_oclass;
Ben Skeggs5a5c7432012-07-11 16:08:25 +1000[diff] [blame]66 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
Ben Skeggs861d2102012-07-11 19:05:01 +1000[diff] [blame]67 device->oclass[NVDEV_SUBDEV_FB ] = &nvc0_fb_oclass;
68 device->oclass[NVDEV_SUBDEV_LTCG ] = &nvc0_ltcg_oclass;
Ben Skeggsc0abf5c2012-09-26 13:05:01 +1000[diff] [blame]69 device->oclass[NVDEV_SUBDEV_IBUS ] = &nvc0_ibus_oclass;
Ben Skeggs3863c9b2012-07-14 19:09:17 +1000[diff] [blame]70 device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv50_instmem_oclass;
71 device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass;
72 device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass;
Ben Skeggsebb945a2012-07-20 08:17:34 +1000[diff] [blame]73 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nvc0_dmaeng_oclass;
74 device->oclass[NVDEV_ENGINE_FIFO ] = &nvc0_fifo_oclass;
75 device->oclass[NVDEV_ENGINE_SW ] = &nvc0_software_oclass;
76 device->oclass[NVDEV_ENGINE_GR ] = &nvc0_graph_oclass;
77 device->oclass[NVDEV_ENGINE_VP ] = &nv84_vp_oclass;
Maarten Lankhorst23c14ed2012-11-23 11:08:23 +1000[diff] [blame^]78 device->oclass[NVDEV_ENGINE_BSP ] = &nvc0_bsp_oclass;
Ben Skeggsebb945a2012-07-20 08:17:34 +1000[diff] [blame]79 device->oclass[NVDEV_ENGINE_PPP ] = &nv98_ppp_oclass;
80 device->oclass[NVDEV_ENGINE_COPY0 ] = &nvc0_copy0_oclass;
81 device->oclass[NVDEV_ENGINE_COPY1 ] = &nvc0_copy1_oclass;
Ben Skeggs70cabe42012-08-14 10:04:04 +1000[diff] [blame]82 device->oclass[NVDEV_ENGINE_DISP ] = &nva3_disp_oclass;
Ben Skeggs9274f4a2012-07-06 07:36:43 +1000[diff] [blame]83 break;
84 case 0xc4:
Ben Skeggs2094dd82012-07-27 08:28:20 +1000[diff] [blame]85 device->cname = "GF104";
Ben Skeggs70c0f262012-07-10 10:49:22 +1000[diff] [blame]86 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
Ben Skeggse0996ae2012-07-10 12:20:17 +1000[diff] [blame]87 device->oclass[NVDEV_SUBDEV_GPIO ] = &nv50_gpio_oclass;
Ben Skeggs4196faa2012-07-10 14:36:38 +1000[diff] [blame]88 device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass;
Ben Skeggs8aceb7d2012-07-10 16:45:24 +1000[diff] [blame]89 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nvc0_clock_oclass;
Martin Peresaa1b9b42012-09-02 02:55:58 +0200[diff] [blame]90 device->oclass[NVDEV_SUBDEV_THERM ] = &nv50_therm_oclass;
Ben Skeggsd38ac522012-07-22 16:41:26 +1000[diff] [blame]91 device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
Ben Skeggscb75d972012-07-11 10:44:20 +1000[diff] [blame]92 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv50_devinit_oclass;
Ben Skeggs7d9115d2012-07-11 15:58:56 +1000[diff] [blame]93 device->oclass[NVDEV_SUBDEV_MC ] = &nvc0_mc_oclass;
Ben Skeggs5a5c7432012-07-11 16:08:25 +1000[diff] [blame]94 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
Ben Skeggs861d2102012-07-11 19:05:01 +1000[diff] [blame]95 device->oclass[NVDEV_SUBDEV_FB ] = &nvc0_fb_oclass;
96 device->oclass[NVDEV_SUBDEV_LTCG ] = &nvc0_ltcg_oclass;
Ben Skeggsc0abf5c2012-09-26 13:05:01 +1000[diff] [blame]97 device->oclass[NVDEV_SUBDEV_IBUS ] = &nvc0_ibus_oclass;
Ben Skeggs3863c9b2012-07-14 19:09:17 +1000[diff] [blame]98 device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv50_instmem_oclass;
99 device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass;
100 device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass;
Ben Skeggsebb945a2012-07-20 08:17:34 +1000[diff] [blame]101 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nvc0_dmaeng_oclass;
102 device->oclass[NVDEV_ENGINE_FIFO ] = &nvc0_fifo_oclass;
103 device->oclass[NVDEV_ENGINE_SW ] = &nvc0_software_oclass;
104 device->oclass[NVDEV_ENGINE_GR ] = &nvc0_graph_oclass;
105 device->oclass[NVDEV_ENGINE_VP ] = &nv84_vp_oclass;
Maarten Lankhorst23c14ed2012-11-23 11:08:23 +1000[diff] [blame^]106 device->oclass[NVDEV_ENGINE_BSP ] = &nvc0_bsp_oclass;
Ben Skeggsebb945a2012-07-20 08:17:34 +1000[diff] [blame]107 device->oclass[NVDEV_ENGINE_PPP ] = &nv98_ppp_oclass;
108 device->oclass[NVDEV_ENGINE_COPY0 ] = &nvc0_copy0_oclass;
109 device->oclass[NVDEV_ENGINE_COPY1 ] = &nvc0_copy1_oclass;
Ben Skeggs70cabe42012-08-14 10:04:04 +1000[diff] [blame]110 device->oclass[NVDEV_ENGINE_DISP ] = &nva3_disp_oclass;
Ben Skeggs9274f4a2012-07-06 07:36:43 +1000[diff] [blame]111 break;
112 case 0xc3:
Ben Skeggs2094dd82012-07-27 08:28:20 +1000[diff] [blame]113 device->cname = "GF106";
Ben Skeggs70c0f262012-07-10 10:49:22 +1000[diff] [blame]114 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
Ben Skeggse0996ae2012-07-10 12:20:17 +1000[diff] [blame]115 device->oclass[NVDEV_SUBDEV_GPIO ] = &nv50_gpio_oclass;
Ben Skeggs4196faa2012-07-10 14:36:38 +1000[diff] [blame]116 device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass;
Ben Skeggs8aceb7d2012-07-10 16:45:24 +1000[diff] [blame]117 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nvc0_clock_oclass;
Martin Peresaa1b9b42012-09-02 02:55:58 +0200[diff] [blame]118 device->oclass[NVDEV_SUBDEV_THERM ] = &nv50_therm_oclass;
Ben Skeggsd38ac522012-07-22 16:41:26 +1000[diff] [blame]119 device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
Ben Skeggscb75d972012-07-11 10:44:20 +1000[diff] [blame]120 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv50_devinit_oclass;
Ben Skeggs7d9115d2012-07-11 15:58:56 +1000[diff] [blame]121 device->oclass[NVDEV_SUBDEV_MC ] = &nvc0_mc_oclass;
Ben Skeggs5a5c7432012-07-11 16:08:25 +1000[diff] [blame]122 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
Ben Skeggs861d2102012-07-11 19:05:01 +1000[diff] [blame]123 device->oclass[NVDEV_SUBDEV_FB ] = &nvc0_fb_oclass;
124 device->oclass[NVDEV_SUBDEV_LTCG ] = &nvc0_ltcg_oclass;
Ben Skeggsc0abf5c2012-09-26 13:05:01 +1000[diff] [blame]125 device->oclass[NVDEV_SUBDEV_IBUS ] = &nvc0_ibus_oclass;
Ben Skeggs3863c9b2012-07-14 19:09:17 +1000[diff] [blame]126 device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv50_instmem_oclass;
127 device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass;
128 device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass;
Ben Skeggsebb945a2012-07-20 08:17:34 +1000[diff] [blame]129 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nvc0_dmaeng_oclass;
130 device->oclass[NVDEV_ENGINE_FIFO ] = &nvc0_fifo_oclass;
131 device->oclass[NVDEV_ENGINE_SW ] = &nvc0_software_oclass;
132 device->oclass[NVDEV_ENGINE_GR ] = &nvc0_graph_oclass;
133 device->oclass[NVDEV_ENGINE_VP ] = &nv84_vp_oclass;
Maarten Lankhorst23c14ed2012-11-23 11:08:23 +1000[diff] [blame^]134 device->oclass[NVDEV_ENGINE_BSP ] = &nvc0_bsp_oclass;
Ben Skeggsebb945a2012-07-20 08:17:34 +1000[diff] [blame]135 device->oclass[NVDEV_ENGINE_PPP ] = &nv98_ppp_oclass;
136 device->oclass[NVDEV_ENGINE_COPY0 ] = &nvc0_copy0_oclass;
137 device->oclass[NVDEV_ENGINE_COPY1 ] = &nvc0_copy1_oclass;
Ben Skeggs70cabe42012-08-14 10:04:04 +1000[diff] [blame]138 device->oclass[NVDEV_ENGINE_DISP ] = &nva3_disp_oclass;
Ben Skeggs9274f4a2012-07-06 07:36:43 +1000[diff] [blame]139 break;
140 case 0xce:
Ben Skeggs2094dd82012-07-27 08:28:20 +1000[diff] [blame]141 device->cname = "GF114";
Ben Skeggs70c0f262012-07-10 10:49:22 +1000[diff] [blame]142 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
Ben Skeggse0996ae2012-07-10 12:20:17 +1000[diff] [blame]143 device->oclass[NVDEV_SUBDEV_GPIO ] = &nv50_gpio_oclass;
Ben Skeggs4196faa2012-07-10 14:36:38 +1000[diff] [blame]144 device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass;
Ben Skeggs8aceb7d2012-07-10 16:45:24 +1000[diff] [blame]145 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nvc0_clock_oclass;
Martin Peresaa1b9b42012-09-02 02:55:58 +0200[diff] [blame]146 device->oclass[NVDEV_SUBDEV_THERM ] = &nv50_therm_oclass;
Ben Skeggsd38ac522012-07-22 16:41:26 +1000[diff] [blame]147 device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
Ben Skeggscb75d972012-07-11 10:44:20 +1000[diff] [blame]148 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv50_devinit_oclass;
Ben Skeggs7d9115d2012-07-11 15:58:56 +1000[diff] [blame]149 device->oclass[NVDEV_SUBDEV_MC ] = &nvc0_mc_oclass;
Ben Skeggs5a5c7432012-07-11 16:08:25 +1000[diff] [blame]150 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
Ben Skeggs861d2102012-07-11 19:05:01 +1000[diff] [blame]151 device->oclass[NVDEV_SUBDEV_FB ] = &nvc0_fb_oclass;
152 device->oclass[NVDEV_SUBDEV_LTCG ] = &nvc0_ltcg_oclass;
Ben Skeggsc0abf5c2012-09-26 13:05:01 +1000[diff] [blame]153 device->oclass[NVDEV_SUBDEV_IBUS ] = &nvc0_ibus_oclass;
Ben Skeggs3863c9b2012-07-14 19:09:17 +1000[diff] [blame]154 device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv50_instmem_oclass;
155 device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass;
156 device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass;
Ben Skeggsebb945a2012-07-20 08:17:34 +1000[diff] [blame]157 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nvc0_dmaeng_oclass;
158 device->oclass[NVDEV_ENGINE_FIFO ] = &nvc0_fifo_oclass;
159 device->oclass[NVDEV_ENGINE_SW ] = &nvc0_software_oclass;
160 device->oclass[NVDEV_ENGINE_GR ] = &nvc0_graph_oclass;
161 device->oclass[NVDEV_ENGINE_VP ] = &nv84_vp_oclass;
Maarten Lankhorst23c14ed2012-11-23 11:08:23 +1000[diff] [blame^]162 device->oclass[NVDEV_ENGINE_BSP ] = &nvc0_bsp_oclass;
Ben Skeggsebb945a2012-07-20 08:17:34 +1000[diff] [blame]163 device->oclass[NVDEV_ENGINE_PPP ] = &nv98_ppp_oclass;
164 device->oclass[NVDEV_ENGINE_COPY0 ] = &nvc0_copy0_oclass;
165 device->oclass[NVDEV_ENGINE_COPY1 ] = &nvc0_copy1_oclass;
Ben Skeggs70cabe42012-08-14 10:04:04 +1000[diff] [blame]166 device->oclass[NVDEV_ENGINE_DISP ] = &nva3_disp_oclass;
Ben Skeggs9274f4a2012-07-06 07:36:43 +1000[diff] [blame]167 break;
168 case 0xcf:
Ben Skeggs2094dd82012-07-27 08:28:20 +1000[diff] [blame]169 device->cname = "GF116";
Ben Skeggs70c0f262012-07-10 10:49:22 +1000[diff] [blame]170 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
Ben Skeggse0996ae2012-07-10 12:20:17 +1000[diff] [blame]171 device->oclass[NVDEV_SUBDEV_GPIO ] = &nv50_gpio_oclass;
Ben Skeggs4196faa2012-07-10 14:36:38 +1000[diff] [blame]172 device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass;
Ben Skeggs8aceb7d2012-07-10 16:45:24 +1000[diff] [blame]173 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nvc0_clock_oclass;
Martin Peresaa1b9b42012-09-02 02:55:58 +0200[diff] [blame]174 device->oclass[NVDEV_SUBDEV_THERM ] = &nv50_therm_oclass;
Ben Skeggsd38ac522012-07-22 16:41:26 +1000[diff] [blame]175 device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
Ben Skeggscb75d972012-07-11 10:44:20 +1000[diff] [blame]176 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv50_devinit_oclass;
Ben Skeggs7d9115d2012-07-11 15:58:56 +1000[diff] [blame]177 device->oclass[NVDEV_SUBDEV_MC ] = &nvc0_mc_oclass;
Ben Skeggs5a5c7432012-07-11 16:08:25 +1000[diff] [blame]178 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
Ben Skeggs861d2102012-07-11 19:05:01 +1000[diff] [blame]179 device->oclass[NVDEV_SUBDEV_FB ] = &nvc0_fb_oclass;
180 device->oclass[NVDEV_SUBDEV_LTCG ] = &nvc0_ltcg_oclass;
Ben Skeggsc0abf5c2012-09-26 13:05:01 +1000[diff] [blame]181 device->oclass[NVDEV_SUBDEV_IBUS ] = &nvc0_ibus_oclass;
Ben Skeggs3863c9b2012-07-14 19:09:17 +1000[diff] [blame]182 device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv50_instmem_oclass;
183 device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass;
184 device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass;
Ben Skeggsebb945a2012-07-20 08:17:34 +1000[diff] [blame]185 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nvc0_dmaeng_oclass;
186 device->oclass[NVDEV_ENGINE_FIFO ] = &nvc0_fifo_oclass;
187 device->oclass[NVDEV_ENGINE_SW ] = &nvc0_software_oclass;
188 device->oclass[NVDEV_ENGINE_GR ] = &nvc0_graph_oclass;
189 device->oclass[NVDEV_ENGINE_VP ] = &nv84_vp_oclass;
Maarten Lankhorst23c14ed2012-11-23 11:08:23 +1000[diff] [blame^]190 device->oclass[NVDEV_ENGINE_BSP ] = &nvc0_bsp_oclass;
Ben Skeggsebb945a2012-07-20 08:17:34 +1000[diff] [blame]191 device->oclass[NVDEV_ENGINE_PPP ] = &nv98_ppp_oclass;
192 device->oclass[NVDEV_ENGINE_COPY0 ] = &nvc0_copy0_oclass;
193 device->oclass[NVDEV_ENGINE_COPY1 ] = &nvc0_copy1_oclass;
Ben Skeggs70cabe42012-08-14 10:04:04 +1000[diff] [blame]194 device->oclass[NVDEV_ENGINE_DISP ] = &nva3_disp_oclass;
Ben Skeggs9274f4a2012-07-06 07:36:43 +1000[diff] [blame]195 break;
196 case 0xc1:
Ben Skeggs2094dd82012-07-27 08:28:20 +1000[diff] [blame]197 device->cname = "GF108";
Ben Skeggs70c0f262012-07-10 10:49:22 +1000[diff] [blame]198 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
Ben Skeggse0996ae2012-07-10 12:20:17 +1000[diff] [blame]199 device->oclass[NVDEV_SUBDEV_GPIO ] = &nv50_gpio_oclass;
Ben Skeggs4196faa2012-07-10 14:36:38 +1000[diff] [blame]200 device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass;
Ben Skeggs8aceb7d2012-07-10 16:45:24 +1000[diff] [blame]201 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nvc0_clock_oclass;
Martin Peresaa1b9b42012-09-02 02:55:58 +0200[diff] [blame]202 device->oclass[NVDEV_SUBDEV_THERM ] = &nv50_therm_oclass;
Ben Skeggsd38ac522012-07-22 16:41:26 +1000[diff] [blame]203 device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
Ben Skeggscb75d972012-07-11 10:44:20 +1000[diff] [blame]204 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv50_devinit_oclass;
Ben Skeggs7d9115d2012-07-11 15:58:56 +1000[diff] [blame]205 device->oclass[NVDEV_SUBDEV_MC ] = &nvc0_mc_oclass;
Ben Skeggs5a5c7432012-07-11 16:08:25 +1000[diff] [blame]206 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
Ben Skeggs861d2102012-07-11 19:05:01 +1000[diff] [blame]207 device->oclass[NVDEV_SUBDEV_FB ] = &nvc0_fb_oclass;
208 device->oclass[NVDEV_SUBDEV_LTCG ] = &nvc0_ltcg_oclass;
Ben Skeggsc0abf5c2012-09-26 13:05:01 +1000[diff] [blame]209 device->oclass[NVDEV_SUBDEV_IBUS ] = &nvc0_ibus_oclass;
Ben Skeggs3863c9b2012-07-14 19:09:17 +1000[diff] [blame]210 device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv50_instmem_oclass;
211 device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass;
212 device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass;
Ben Skeggsebb945a2012-07-20 08:17:34 +1000[diff] [blame]213 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nvc0_dmaeng_oclass;
214 device->oclass[NVDEV_ENGINE_FIFO ] = &nvc0_fifo_oclass;
215 device->oclass[NVDEV_ENGINE_SW ] = &nvc0_software_oclass;
216 device->oclass[NVDEV_ENGINE_GR ] = &nvc0_graph_oclass;
217 device->oclass[NVDEV_ENGINE_VP ] = &nv84_vp_oclass;
Maarten Lankhorst23c14ed2012-11-23 11:08:23 +1000[diff] [blame^]218 device->oclass[NVDEV_ENGINE_BSP ] = &nvc0_bsp_oclass;
Ben Skeggsebb945a2012-07-20 08:17:34 +1000[diff] [blame]219 device->oclass[NVDEV_ENGINE_PPP ] = &nv98_ppp_oclass;
220 device->oclass[NVDEV_ENGINE_COPY0 ] = &nvc0_copy0_oclass;
221 device->oclass[NVDEV_ENGINE_COPY1 ] = &nvc0_copy1_oclass;
Ben Skeggs70cabe42012-08-14 10:04:04 +1000[diff] [blame]222 device->oclass[NVDEV_ENGINE_DISP ] = &nva3_disp_oclass;
Ben Skeggs9274f4a2012-07-06 07:36:43 +1000[diff] [blame]223 break;
224 case 0xc8:
Ben Skeggs2094dd82012-07-27 08:28:20 +1000[diff] [blame]225 device->cname = "GF110";
Ben Skeggs70c0f262012-07-10 10:49:22 +1000[diff] [blame]226 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
Ben Skeggse0996ae2012-07-10 12:20:17 +1000[diff] [blame]227 device->oclass[NVDEV_SUBDEV_GPIO ] = &nv50_gpio_oclass;
Ben Skeggs4196faa2012-07-10 14:36:38 +1000[diff] [blame]228 device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass;
Ben Skeggs8aceb7d2012-07-10 16:45:24 +1000[diff] [blame]229 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nvc0_clock_oclass;
Martin Peresaa1b9b42012-09-02 02:55:58 +0200[diff] [blame]230 device->oclass[NVDEV_SUBDEV_THERM ] = &nv50_therm_oclass;
Ben Skeggsd38ac522012-07-22 16:41:26 +1000[diff] [blame]231 device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
Ben Skeggscb75d972012-07-11 10:44:20 +1000[diff] [blame]232 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv50_devinit_oclass;
Ben Skeggs7d9115d2012-07-11 15:58:56 +1000[diff] [blame]233 device->oclass[NVDEV_SUBDEV_MC ] = &nvc0_mc_oclass;
Ben Skeggs5a5c7432012-07-11 16:08:25 +1000[diff] [blame]234 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
Ben Skeggs861d2102012-07-11 19:05:01 +1000[diff] [blame]235 device->oclass[NVDEV_SUBDEV_FB ] = &nvc0_fb_oclass;
236 device->oclass[NVDEV_SUBDEV_LTCG ] = &nvc0_ltcg_oclass;
Ben Skeggsc0abf5c2012-09-26 13:05:01 +1000[diff] [blame]237 device->oclass[NVDEV_SUBDEV_IBUS ] = &nvc0_ibus_oclass;
Ben Skeggs3863c9b2012-07-14 19:09:17 +1000[diff] [blame]238 device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv50_instmem_oclass;
239 device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass;
240 device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass;
Ben Skeggsebb945a2012-07-20 08:17:34 +1000[diff] [blame]241 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nvc0_dmaeng_oclass;
242 device->oclass[NVDEV_ENGINE_FIFO ] = &nvc0_fifo_oclass;
243 device->oclass[NVDEV_ENGINE_SW ] = &nvc0_software_oclass;
244 device->oclass[NVDEV_ENGINE_GR ] = &nvc0_graph_oclass;
245 device->oclass[NVDEV_ENGINE_VP ] = &nv84_vp_oclass;
Maarten Lankhorst23c14ed2012-11-23 11:08:23 +1000[diff] [blame^]246 device->oclass[NVDEV_ENGINE_BSP ] = &nvc0_bsp_oclass;
Ben Skeggsebb945a2012-07-20 08:17:34 +1000[diff] [blame]247 device->oclass[NVDEV_ENGINE_PPP ] = &nv98_ppp_oclass;
248 device->oclass[NVDEV_ENGINE_COPY0 ] = &nvc0_copy0_oclass;
249 device->oclass[NVDEV_ENGINE_COPY1 ] = &nvc0_copy1_oclass;
Ben Skeggs70cabe42012-08-14 10:04:04 +1000[diff] [blame]250 device->oclass[NVDEV_ENGINE_DISP ] = &nva3_disp_oclass;
Ben Skeggs9274f4a2012-07-06 07:36:43 +1000[diff] [blame]251 break;
252 case 0xd9:
Ben Skeggs2094dd82012-07-27 08:28:20 +1000[diff] [blame]253 device->cname = "GF119";
Ben Skeggs70c0f262012-07-10 10:49:22 +1000[diff] [blame]254 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
Ben Skeggse0996ae2012-07-10 12:20:17 +1000[diff] [blame]255 device->oclass[NVDEV_SUBDEV_GPIO ] = &nvd0_gpio_oclass;
Ben Skeggs4196faa2012-07-10 14:36:38 +1000[diff] [blame]256 device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass;
Ben Skeggs8aceb7d2012-07-10 16:45:24 +1000[diff] [blame]257 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nvc0_clock_oclass;
Martin Peresaa1b9b42012-09-02 02:55:58 +0200[diff] [blame]258 device->oclass[NVDEV_SUBDEV_THERM ] = &nv50_therm_oclass;
Ben Skeggsd38ac522012-07-22 16:41:26 +1000[diff] [blame]259 device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
Ben Skeggscb75d972012-07-11 10:44:20 +1000[diff] [blame]260 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv50_devinit_oclass;
Ben Skeggs7d9115d2012-07-11 15:58:56 +1000[diff] [blame]261 device->oclass[NVDEV_SUBDEV_MC ] = &nvc0_mc_oclass;
Ben Skeggs5a5c7432012-07-11 16:08:25 +1000[diff] [blame]262 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
Ben Skeggs861d2102012-07-11 19:05:01 +1000[diff] [blame]263 device->oclass[NVDEV_SUBDEV_FB ] = &nvc0_fb_oclass;
264 device->oclass[NVDEV_SUBDEV_LTCG ] = &nvc0_ltcg_oclass;
Ben Skeggsc0abf5c2012-09-26 13:05:01 +1000[diff] [blame]265 device->oclass[NVDEV_SUBDEV_IBUS ] = &nvc0_ibus_oclass;
Ben Skeggs3863c9b2012-07-14 19:09:17 +1000[diff] [blame]266 device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv50_instmem_oclass;
267 device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass;
268 device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass;
Ben Skeggs344e1072012-10-08 14:11:35 +1000[diff] [blame]269 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nvd0_dmaeng_oclass;
Ben Skeggsebb945a2012-07-20 08:17:34 +1000[diff] [blame]270 device->oclass[NVDEV_ENGINE_FIFO ] = &nvc0_fifo_oclass;
271 device->oclass[NVDEV_ENGINE_SW ] = &nvc0_software_oclass;
272 device->oclass[NVDEV_ENGINE_GR ] = &nvc0_graph_oclass;
273 device->oclass[NVDEV_ENGINE_VP ] = &nv84_vp_oclass;
Maarten Lankhorst23c14ed2012-11-23 11:08:23 +1000[diff] [blame^]274 device->oclass[NVDEV_ENGINE_BSP ] = &nvc0_bsp_oclass;
Ben Skeggsebb945a2012-07-20 08:17:34 +1000[diff] [blame]275 device->oclass[NVDEV_ENGINE_PPP ] = &nv98_ppp_oclass;
276 device->oclass[NVDEV_ENGINE_COPY0 ] = &nvc0_copy0_oclass;
277 device->oclass[NVDEV_ENGINE_DISP ] = &nvd0_disp_oclass;
Ben Skeggs9274f4a2012-07-06 07:36:43 +1000[diff] [blame]278 break;
279 default:
280 nv_fatal(device, "unknown Fermi chipset\n");
281 return -EINVAL;
282 }
283
284 return 0;
285}