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Praneeth Paladugu6e6fbdb2017-01-16 15:43:01 -08001/* Copyright (c) 2012-2017, The Linux Foundation. All rights reserved.
2 *
3 * This program is free software; you can redistribute it and/or modify
4 * it under the terms of the GNU General Public License version 2 and
5 * only version 2 as published by the Free Software Foundation.
6 *
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
11 *
12 */
13
14#ifndef __H_VIDC_HFI_HELPER_H__
15#define __H_VIDC_HFI_HELPER_H__
16
17#define HFI_COMMON_BASE (0)
18#define HFI_OX_BASE (0x01000000)
19
20#define HFI_VIDEO_DOMAIN_ENCODER (HFI_COMMON_BASE + 0x1)
21#define HFI_VIDEO_DOMAIN_DECODER (HFI_COMMON_BASE + 0x2)
22#define HFI_VIDEO_DOMAIN_VPE (HFI_COMMON_BASE + 0x4)
23#define HFI_VIDEO_DOMAIN_MBI (HFI_COMMON_BASE + 0x8)
24
25#define HFI_DOMAIN_BASE_COMMON (HFI_COMMON_BASE + 0)
26#define HFI_DOMAIN_BASE_VDEC (HFI_COMMON_BASE + 0x01000000)
27#define HFI_DOMAIN_BASE_VENC (HFI_COMMON_BASE + 0x02000000)
28#define HFI_DOMAIN_BASE_VPE (HFI_COMMON_BASE + 0x03000000)
29
30#define HFI_VIDEO_ARCH_OX (HFI_COMMON_BASE + 0x1)
31
32#define HFI_ARCH_COMMON_OFFSET (0)
33#define HFI_ARCH_OX_OFFSET (0x00200000)
34
35#define HFI_CMD_START_OFFSET (0x00010000)
36#define HFI_MSG_START_OFFSET (0x00020000)
37
38#define HFI_ERR_NONE HFI_COMMON_BASE
39#define HFI_ERR_SYS_FATAL (HFI_COMMON_BASE + 0x1)
40#define HFI_ERR_SYS_INVALID_PARAMETER (HFI_COMMON_BASE + 0x2)
41#define HFI_ERR_SYS_VERSION_MISMATCH (HFI_COMMON_BASE + 0x3)
42#define HFI_ERR_SYS_INSUFFICIENT_RESOURCES (HFI_COMMON_BASE + 0x4)
43#define HFI_ERR_SYS_MAX_SESSIONS_REACHED (HFI_COMMON_BASE + 0x5)
44#define HFI_ERR_SYS_UNSUPPORTED_CODEC (HFI_COMMON_BASE + 0x6)
45#define HFI_ERR_SYS_SESSION_IN_USE (HFI_COMMON_BASE + 0x7)
46#define HFI_ERR_SYS_SESSION_ID_OUT_OF_RANGE (HFI_COMMON_BASE + 0x8)
47#define HFI_ERR_SYS_UNSUPPORTED_DOMAIN (HFI_COMMON_BASE + 0x9)
48
49#define HFI_ERR_SESSION_FATAL (HFI_COMMON_BASE + 0x1001)
50#define HFI_ERR_SESSION_INVALID_PARAMETER (HFI_COMMON_BASE + 0x1002)
51#define HFI_ERR_SESSION_BAD_POINTER (HFI_COMMON_BASE + 0x1003)
52#define HFI_ERR_SESSION_INVALID_SESSION_ID (HFI_COMMON_BASE + 0x1004)
53#define HFI_ERR_SESSION_INVALID_STREAM_ID (HFI_COMMON_BASE + 0x1005)
54#define HFI_ERR_SESSION_INCORRECT_STATE_OPERATION \
55 (HFI_COMMON_BASE + 0x1006)
56#define HFI_ERR_SESSION_UNSUPPORTED_PROPERTY (HFI_COMMON_BASE + 0x1007)
57
58#define HFI_ERR_SESSION_UNSUPPORTED_SETTING (HFI_COMMON_BASE + 0x1008)
59
60#define HFI_ERR_SESSION_INSUFFICIENT_RESOURCES (HFI_COMMON_BASE + 0x1009)
61
62#define HFI_ERR_SESSION_STREAM_CORRUPT_OUTPUT_STALLED \
63 (HFI_COMMON_BASE + 0x100A)
64
65#define HFI_ERR_SESSION_STREAM_CORRUPT (HFI_COMMON_BASE + 0x100B)
66#define HFI_ERR_SESSION_ENC_OVERFLOW (HFI_COMMON_BASE + 0x100C)
67#define HFI_ERR_SESSION_UNSUPPORTED_STREAM (HFI_COMMON_BASE + 0x100D)
68#define HFI_ERR_SESSION_CMDSIZE (HFI_COMMON_BASE + 0x100E)
69#define HFI_ERR_SESSION_UNSUPPORT_CMD (HFI_COMMON_BASE + 0x100F)
70#define HFI_ERR_SESSION_UNSUPPORT_BUFFERTYPE (HFI_COMMON_BASE + 0x1010)
71#define HFI_ERR_SESSION_BUFFERCOUNT_TOOSMALL (HFI_COMMON_BASE + 0x1011)
72#define HFI_ERR_SESSION_INVALID_SCALE_FACTOR (HFI_COMMON_BASE + 0x1012)
73#define HFI_ERR_SESSION_UPSCALE_NOT_SUPPORTED (HFI_COMMON_BASE + 0x1013)
74
75#define HFI_EVENT_SYS_ERROR (HFI_COMMON_BASE + 0x1)
76#define HFI_EVENT_SESSION_ERROR (HFI_COMMON_BASE + 0x2)
77
78#define HFI_VIDEO_CODEC_H264 0x00000002
Praneeth Paladugu6e6fbdb2017-01-16 15:43:01 -080079#define HFI_VIDEO_CODEC_MPEG1 0x00000008
80#define HFI_VIDEO_CODEC_MPEG2 0x00000010
Praneeth Paladugu6e6fbdb2017-01-16 15:43:01 -080081#define HFI_VIDEO_CODEC_VP8 0x00001000
82#define HFI_VIDEO_CODEC_HEVC 0x00002000
83#define HFI_VIDEO_CODEC_VP9 0x00004000
Surajit Podder285ff282017-05-26 09:24:10 +053084#define HFI_VIDEO_CODEC_TME 0x00008000
Praneeth Paladugu6e6fbdb2017-01-16 15:43:01 -080085
Umesh Pandey3cfce632017-03-02 13:56:18 -080086#define HFI_PROFILE_UNKNOWN 0x00000000
Praneeth Paladugu6e6fbdb2017-01-16 15:43:01 -080087#define HFI_H264_PROFILE_BASELINE 0x00000001
88#define HFI_H264_PROFILE_MAIN 0x00000002
89#define HFI_H264_PROFILE_HIGH 0x00000004
90#define HFI_H264_PROFILE_STEREO_HIGH 0x00000008
91#define HFI_H264_PROFILE_MULTIVIEW_HIGH 0x00000010
92#define HFI_H264_PROFILE_CONSTRAINED_BASE 0x00000020
93#define HFI_H264_PROFILE_CONSTRAINED_HIGH 0x00000040
94
Umesh Pandey3cfce632017-03-02 13:56:18 -080095#define HFI_LEVEL_UNKNOWN 0x00000000
Praneeth Paladugu6e6fbdb2017-01-16 15:43:01 -080096#define HFI_H264_LEVEL_1 0x00000001
97#define HFI_H264_LEVEL_1b 0x00000002
98#define HFI_H264_LEVEL_11 0x00000004
99#define HFI_H264_LEVEL_12 0x00000008
100#define HFI_H264_LEVEL_13 0x00000010
101#define HFI_H264_LEVEL_2 0x00000020
102#define HFI_H264_LEVEL_21 0x00000040
103#define HFI_H264_LEVEL_22 0x00000080
104#define HFI_H264_LEVEL_3 0x00000100
105#define HFI_H264_LEVEL_31 0x00000200
106#define HFI_H264_LEVEL_32 0x00000400
107#define HFI_H264_LEVEL_4 0x00000800
108#define HFI_H264_LEVEL_41 0x00001000
109#define HFI_H264_LEVEL_42 0x00002000
110#define HFI_H264_LEVEL_5 0x00004000
111#define HFI_H264_LEVEL_51 0x00008000
Chinmay Sawarkar2de3f772017-02-07 12:03:44 -0800112#define HFI_H264_LEVEL_52 0x00010000
Praneeth Paladugu6e6fbdb2017-01-16 15:43:01 -0800113
114#define HFI_MPEG2_PROFILE_SIMPLE 0x00000001
115#define HFI_MPEG2_PROFILE_MAIN 0x00000002
116#define HFI_MPEG2_PROFILE_422 0x00000004
117#define HFI_MPEG2_PROFILE_SNR 0x00000008
118#define HFI_MPEG2_PROFILE_SPATIAL 0x00000010
119#define HFI_MPEG2_PROFILE_HIGH 0x00000020
120
121#define HFI_MPEG2_LEVEL_LL 0x00000001
122#define HFI_MPEG2_LEVEL_ML 0x00000002
123#define HFI_MPEG2_LEVEL_H14 0x00000004
124#define HFI_MPEG2_LEVEL_HL 0x00000008
125
Chinmay Sawarkar7f1cc152017-05-05 18:16:36 -0700126#define HFI_VPX_PROFILE_MAIN 0x00000001
127
128#define HFI_VPX_LEVEL_VERSION_0 0x00000001
129#define HFI_VPX_LEVEL_VERSION_1 0x00000002
130#define HFI_VPX_LEVEL_VERSION_2 0x00000004
131#define HFI_VPX_LEVEL_VERSION_3 0x00000008
Praneeth Paladugu6e6fbdb2017-01-16 15:43:01 -0800132
Praneeth Paladugu6e6fbdb2017-01-16 15:43:01 -0800133#define HFI_HEVC_PROFILE_MAIN 0x00000001
134#define HFI_HEVC_PROFILE_MAIN10 0x00000002
135#define HFI_HEVC_PROFILE_MAIN_STILL_PIC 0x00000004
136
137#define HFI_HEVC_LEVEL_1 0x00000001
138#define HFI_HEVC_LEVEL_2 0x00000002
139#define HFI_HEVC_LEVEL_21 0x00000004
140#define HFI_HEVC_LEVEL_3 0x00000008
141#define HFI_HEVC_LEVEL_31 0x00000010
142#define HFI_HEVC_LEVEL_4 0x00000020
143#define HFI_HEVC_LEVEL_41 0x00000040
144#define HFI_HEVC_LEVEL_5 0x00000080
145#define HFI_HEVC_LEVEL_51 0x00000100
146#define HFI_HEVC_LEVEL_52 0x00000200
147#define HFI_HEVC_LEVEL_6 0x00000400
148#define HFI_HEVC_LEVEL_61 0x00000800
149#define HFI_HEVC_LEVEL_62 0x00001000
150
151#define HFI_HEVC_TIER_MAIN 0x1
152#define HFI_HEVC_TIER_HIGH0 0x2
153
Surajit Podder285ff282017-05-26 09:24:10 +0530154#define HFI_TME_PROFILE_DEFAULT 0x00000001
155#define HFI_TME_PROFILE_FRC 0x00000002
156#define HFI_TME_PROFILE_ASW 0x00000004
157#define HFI_TME_PROFILE_DFS_BOKEH 0x00000008
158
159#define HFI_TME_LEVEL_INTEGER 0x00000001
160
Praneeth Paladugu6e6fbdb2017-01-16 15:43:01 -0800161#define HFI_BUFFER_INPUT (HFI_COMMON_BASE + 0x1)
162#define HFI_BUFFER_OUTPUT (HFI_COMMON_BASE + 0x2)
163#define HFI_BUFFER_OUTPUT2 (HFI_COMMON_BASE + 0x3)
164#define HFI_BUFFER_INTERNAL_PERSIST (HFI_COMMON_BASE + 0x4)
165#define HFI_BUFFER_INTERNAL_PERSIST_1 (HFI_COMMON_BASE + 0x5)
Chinmay Sawarkare6468ec2017-05-23 18:20:51 -0700166#define HFI_BUFFER_COMMON_INTERNAL_SCRATCH (HFI_COMMON_BASE + 0x6)
167#define HFI_BUFFER_COMMON_INTERNAL_SCRATCH_1 (HFI_COMMON_BASE + 0x7)
168#define HFI_BUFFER_COMMON_INTERNAL_SCRATCH_2 (HFI_COMMON_BASE + 0x8)
169#define HFI_BUFFER_COMMON_INTERNAL_RECON (HFI_COMMON_BASE + 0x9)
170#define HFI_BUFFER_EXTRADATA_OUTPUT (HFI_COMMON_BASE + 0xA)
171#define HFI_BUFFER_EXTRADATA_OUTPUT2 (HFI_COMMON_BASE + 0xB)
172#define HFI_BUFFER_EXTRADATA_INPUT (HFI_COMMON_BASE + 0xC)
Praneeth Paladugu6e6fbdb2017-01-16 15:43:01 -0800173
174#define HFI_BITDEPTH_8 (HFI_COMMON_BASE + 0x0)
175#define HFI_BITDEPTH_9 (HFI_COMMON_BASE + 0x1)
176#define HFI_BITDEPTH_10 (HFI_COMMON_BASE + 0x2)
177
178#define HFI_VENC_PERFMODE_MAX_QUALITY 0x1
179#define HFI_VENC_PERFMODE_POWER_SAVE 0x2
180
Praneeth Paladugu238977b2016-12-06 12:51:26 -0800181#define HFI_WORKMODE_1 (HFI_COMMON_BASE + 0x1)
182#define HFI_WORKMODE_2 (HFI_COMMON_BASE + 0x2)
183
Praneeth Paladugu6e6fbdb2017-01-16 15:43:01 -0800184struct hfi_buffer_info {
185 u32 buffer_addr;
186 u32 extra_data_addr;
187};
188
189#define HFI_PROPERTY_SYS_COMMON_START \
190 (HFI_DOMAIN_BASE_COMMON + HFI_ARCH_COMMON_OFFSET + 0x0000)
191#define HFI_PROPERTY_SYS_DEBUG_CONFIG \
192 (HFI_PROPERTY_SYS_COMMON_START + 0x001)
193#define HFI_PROPERTY_SYS_RESOURCE_OCMEM_REQUIREMENT_INFO \
194 (HFI_PROPERTY_SYS_COMMON_START + 0x002)
195#define HFI_PROPERTY_SYS_CONFIG_VCODEC_CLKFREQ \
196 (HFI_PROPERTY_SYS_COMMON_START + 0x003)
197#define HFI_PROPERTY_SYS_IDLE_INDICATOR \
198 (HFI_PROPERTY_SYS_COMMON_START + 0x004)
199#define HFI_PROPERTY_SYS_CODEC_POWER_PLANE_CTRL \
200 (HFI_PROPERTY_SYS_COMMON_START + 0x005)
201#define HFI_PROPERTY_SYS_IMAGE_VERSION \
202 (HFI_PROPERTY_SYS_COMMON_START + 0x006)
203#define HFI_PROPERTY_SYS_CONFIG_COVERAGE \
204 (HFI_PROPERTY_SYS_COMMON_START + 0x007)
205
206#define HFI_PROPERTY_PARAM_COMMON_START \
207 (HFI_DOMAIN_BASE_COMMON + HFI_ARCH_COMMON_OFFSET + 0x1000)
208#define HFI_PROPERTY_PARAM_FRAME_SIZE \
209 (HFI_PROPERTY_PARAM_COMMON_START + 0x001)
210#define HFI_PROPERTY_PARAM_UNCOMPRESSED_PLANE_ACTUAL_INFO \
211 (HFI_PROPERTY_PARAM_COMMON_START + 0x002)
212#define HFI_PROPERTY_PARAM_UNCOMPRESSED_FORMAT_SELECT \
213 (HFI_PROPERTY_PARAM_COMMON_START + 0x003)
214#define HFI_PROPERTY_PARAM_UNCOMPRESSED_FORMAT_SUPPORTED \
215 (HFI_PROPERTY_PARAM_COMMON_START + 0x004)
216#define HFI_PROPERTY_PARAM_PROFILE_LEVEL_CURRENT \
217 (HFI_PROPERTY_PARAM_COMMON_START + 0x005)
218#define HFI_PROPERTY_PARAM_PROFILE_LEVEL_SUPPORTED \
219 (HFI_PROPERTY_PARAM_COMMON_START + 0x006)
220#define HFI_PROPERTY_PARAM_CAPABILITY_SUPPORTED \
221 (HFI_PROPERTY_PARAM_COMMON_START + 0x007)
222#define HFI_PROPERTY_PARAM_PROPERTIES_SUPPORTED \
223 (HFI_PROPERTY_PARAM_COMMON_START + 0x008)
224#define HFI_PROPERTY_PARAM_CODEC_SUPPORTED \
225 (HFI_PROPERTY_PARAM_COMMON_START + 0x009)
226#define HFI_PROPERTY_PARAM_NAL_STREAM_FORMAT_SUPPORTED \
227 (HFI_PROPERTY_PARAM_COMMON_START + 0x00A)
228#define HFI_PROPERTY_PARAM_NAL_STREAM_FORMAT_SELECT \
229 (HFI_PROPERTY_PARAM_COMMON_START + 0x00B)
230#define HFI_PROPERTY_PARAM_MULTI_VIEW_FORMAT \
231 (HFI_PROPERTY_PARAM_COMMON_START + 0x00C)
Praneeth Paladugu6e6fbdb2017-01-16 15:43:01 -0800232#define HFI_PROPERTY_PARAM_CODEC_MASK_SUPPORTED \
233 (HFI_PROPERTY_PARAM_COMMON_START + 0x00E)
Praneeth Paladugu6e6fbdb2017-01-16 15:43:01 -0800234#define HFI_PROPERTY_PARAM_MAX_SESSIONS_SUPPORTED \
235 (HFI_PROPERTY_PARAM_COMMON_START + 0x010)
Karthikeyan Periasamya0e4bad2017-04-26 12:51:10 -0700236#define HFI_PROPERTY_PARAM_SECURE_SESSION \
237 (HFI_PROPERTY_PARAM_COMMON_START + 0x011)
Praneeth Paladugu238977b2016-12-06 12:51:26 -0800238#define HFI_PROPERTY_PARAM_WORK_MODE \
239 (HFI_PROPERTY_PARAM_COMMON_START + 0x015)
Surajit Podder285ff282017-05-26 09:24:10 +0530240#define HFI_PROPERTY_TME_VERSION_SUPPORTED \
241 (HFI_PROPERTY_PARAM_COMMON_START + 0x016)
Praneeth Paladugu6e6fbdb2017-01-16 15:43:01 -0800242
243#define HFI_PROPERTY_CONFIG_COMMON_START \
244 (HFI_DOMAIN_BASE_COMMON + HFI_ARCH_COMMON_OFFSET + 0x2000)
245#define HFI_PROPERTY_CONFIG_FRAME_RATE \
246 (HFI_PROPERTY_CONFIG_COMMON_START + 0x001)
Praneeth Paladugu238977b2016-12-06 12:51:26 -0800247#define HFI_PROPERTY_CONFIG_VIDEOCORES_USAGE \
248 (HFI_PROPERTY_CONFIG_COMMON_START + 0x002)
Praneeth Paladugu6e6fbdb2017-01-16 15:43:01 -0800249
250#define HFI_PROPERTY_PARAM_VDEC_COMMON_START \
251 (HFI_DOMAIN_BASE_VDEC + HFI_ARCH_COMMON_OFFSET + 0x3000)
252#define HFI_PROPERTY_PARAM_VDEC_MULTI_STREAM \
253 (HFI_PROPERTY_PARAM_VDEC_COMMON_START + 0x001)
254#define HFI_PROPERTY_PARAM_VDEC_CONCEAL_COLOR \
255 (HFI_PROPERTY_PARAM_VDEC_COMMON_START + 0x002)
Praneeth Paladugu6e6fbdb2017-01-16 15:43:01 -0800256#define HFI_PROPERTY_PARAM_VDEC_PIXEL_BITDEPTH \
257 (HFI_PROPERTY_PARAM_VDEC_COMMON_START + 0x007)
258#define HFI_PROPERTY_PARAM_VDEC_PIC_STRUCT \
259 (HFI_PROPERTY_PARAM_VDEC_COMMON_START + 0x009)
260#define HFI_PROPERTY_PARAM_VDEC_COLOUR_SPACE \
261 (HFI_PROPERTY_PARAM_VDEC_COMMON_START + 0x00A)
262
263
264#define HFI_PROPERTY_CONFIG_VDEC_COMMON_START \
265 (HFI_DOMAIN_BASE_VDEC + HFI_ARCH_COMMON_OFFSET + 0x4000)
266
267#define HFI_PROPERTY_PARAM_VENC_COMMON_START \
268 (HFI_DOMAIN_BASE_VENC + HFI_ARCH_COMMON_OFFSET + 0x5000)
269#define HFI_PROPERTY_PARAM_VENC_SLICE_DELIVERY_MODE \
270 (HFI_PROPERTY_PARAM_VENC_COMMON_START + 0x001)
271#define HFI_PROPERTY_PARAM_VENC_H264_ENTROPY_CONTROL \
272 (HFI_PROPERTY_PARAM_VENC_COMMON_START + 0x002)
273#define HFI_PROPERTY_PARAM_VENC_H264_DEBLOCK_CONTROL \
274 (HFI_PROPERTY_PARAM_VENC_COMMON_START + 0x003)
275#define HFI_PROPERTY_PARAM_VENC_RATE_CONTROL \
276 (HFI_PROPERTY_PARAM_VENC_COMMON_START + 0x004)
Umesh Pandey3cfce632017-03-02 13:56:18 -0800277#define HFI_PROPERTY_PARAM_VENC_SESSION_QP_RANGE \
278 (HFI_PROPERTY_PARAM_VENC_COMMON_START + 0x009)
Praneeth Paladugu6e6fbdb2017-01-16 15:43:01 -0800279#define HFI_PROPERTY_PARAM_VENC_OPEN_GOP \
280 (HFI_PROPERTY_PARAM_VENC_COMMON_START + 0x00C)
281#define HFI_PROPERTY_PARAM_VENC_INTRA_REFRESH \
282 (HFI_PROPERTY_PARAM_VENC_COMMON_START + 0x00D)
283#define HFI_PROPERTY_PARAM_VENC_MULTI_SLICE_CONTROL \
284 (HFI_PROPERTY_PARAM_VENC_COMMON_START + 0x00E)
285#define HFI_PROPERTY_PARAM_VENC_VBV_HRD_BUF_SIZE \
286 (HFI_PROPERTY_PARAM_VENC_COMMON_START + 0x00F)
287#define HFI_PROPERTY_PARAM_VENC_QUALITY_VS_SPEED \
288 (HFI_PROPERTY_PARAM_VENC_COMMON_START + 0x010)
Praneeth Paladugu6e6fbdb2017-01-16 15:43:01 -0800289#define HFI_PROPERTY_PARAM_VENC_H264_SPS_ID \
290 (HFI_PROPERTY_PARAM_VENC_COMMON_START + 0x014)
291#define HFI_PROPERTY_PARAM_VENC_H264_PPS_ID \
292 (HFI_PROPERTY_PARAM_VENC_COMMON_START + 0x015)
Umesh Pandey7fce7ee2017-03-13 17:59:48 -0700293#define HFI_PROPERTY_PARAM_VENC_GENERATE_AUDNAL \
Praneeth Paladugu6e6fbdb2017-01-16 15:43:01 -0800294 (HFI_PROPERTY_PARAM_VENC_COMMON_START + 0x016)
295#define HFI_PROPERTY_PARAM_VENC_ASPECT_RATIO \
296 (HFI_PROPERTY_PARAM_VENC_COMMON_START + 0x017)
297#define HFI_PROPERTY_PARAM_VENC_NUMREF \
298 (HFI_PROPERTY_PARAM_VENC_COMMON_START + 0x018)
Praneeth Paladugu6e6fbdb2017-01-16 15:43:01 -0800299#define HFI_PROPERTY_PARAM_VENC_LTRMODE \
300 (HFI_PROPERTY_PARAM_VENC_COMMON_START + 0x01C)
301#define HFI_PROPERTY_PARAM_VENC_VIDEO_SIGNAL_INFO \
302 (HFI_PROPERTY_PARAM_VENC_COMMON_START + 0x01D)
Chinmay Sawarkard0054622017-05-04 13:50:59 -0700303#define HFI_PROPERTY_PARAM_VENC_VUI_TIMING_INFO \
Praneeth Paladugu6e6fbdb2017-01-16 15:43:01 -0800304 (HFI_PROPERTY_PARAM_VENC_COMMON_START + 0x01E)
Praneeth Paladugu6e6fbdb2017-01-16 15:43:01 -0800305#define HFI_PROPERTY_PARAM_VENC_LOW_LATENCY_MODE \
306 (HFI_PROPERTY_PARAM_VENC_COMMON_START + 0x022)
307#define HFI_PROPERTY_PARAM_VENC_PRESERVE_TEXT_QUALITY \
308 (HFI_PROPERTY_PARAM_VENC_COMMON_START + 0x023)
309#define HFI_PROPERTY_PARAM_VENC_H264_8X8_TRANSFORM \
310 (HFI_PROPERTY_PARAM_VENC_COMMON_START + 0x025)
311#define HFI_PROPERTY_PARAM_VENC_HIER_P_MAX_NUM_ENH_LAYER \
312 (HFI_PROPERTY_PARAM_VENC_COMMON_START + 0x026)
313#define HFI_PROPERTY_PARAM_VENC_DISABLE_RC_TIMESTAMP \
314 (HFI_PROPERTY_PARAM_VENC_COMMON_START + 0x027)
Praneeth Paladugu6e6fbdb2017-01-16 15:43:01 -0800315#define HFI_PROPERTY_PARAM_VENC_VPX_ERROR_RESILIENCE_MODE \
316 (HFI_PROPERTY_PARAM_VENC_COMMON_START + 0x029)
Praneeth Paladugu6e6fbdb2017-01-16 15:43:01 -0800317#define HFI_PROPERTY_PARAM_VENC_HIER_B_MAX_NUM_ENH_LAYER \
318 (HFI_PROPERTY_PARAM_VENC_COMMON_START + 0x02C)
319#define HFI_PROPERTY_PARAM_VENC_HIER_P_HYBRID_MODE \
320 (HFI_PROPERTY_PARAM_VENC_COMMON_START + 0x02F)
321#define HFI_PROPERTY_PARAM_VENC_BITRATE_TYPE \
322 (HFI_PROPERTY_PARAM_VENC_COMMON_START + 0x031)
323#define HFI_PROPERTY_PARAM_VENC_VQZIP_SEI_TYPE \
324 (HFI_PROPERTY_PARAM_VENC_COMMON_START + 0x033)
325#define HFI_PROPERTY_PARAM_VENC_IFRAMESIZE \
326 (HFI_PROPERTY_PARAM_VENC_COMMON_START + 0x034)
327
328#define HFI_PROPERTY_CONFIG_VENC_COMMON_START \
329 (HFI_DOMAIN_BASE_VENC + HFI_ARCH_COMMON_OFFSET + 0x6000)
330#define HFI_PROPERTY_CONFIG_VENC_TARGET_BITRATE \
331 (HFI_PROPERTY_CONFIG_VENC_COMMON_START + 0x001)
332#define HFI_PROPERTY_CONFIG_VENC_IDR_PERIOD \
333 (HFI_PROPERTY_CONFIG_VENC_COMMON_START + 0x002)
334#define HFI_PROPERTY_CONFIG_VENC_INTRA_PERIOD \
335 (HFI_PROPERTY_CONFIG_VENC_COMMON_START + 0x003)
336#define HFI_PROPERTY_CONFIG_VENC_REQUEST_SYNC_FRAME \
337 (HFI_PROPERTY_CONFIG_VENC_COMMON_START + 0x004)
338#define HFI_PROPERTY_CONFIG_VENC_SLICE_SIZE \
339 (HFI_PROPERTY_CONFIG_VENC_COMMON_START + 0x005)
Praneeth Paladugu6e6fbdb2017-01-16 15:43:01 -0800340#define HFI_PROPERTY_CONFIG_VENC_SYNC_FRAME_SEQUENCE_HEADER \
341 (HFI_PROPERTY_CONFIG_VENC_COMMON_START + 0x008)
342#define HFI_PROPERTY_CONFIG_VENC_MARKLTRFRAME \
343 (HFI_PROPERTY_CONFIG_VENC_COMMON_START + 0x009)
344#define HFI_PROPERTY_CONFIG_VENC_USELTRFRAME \
345 (HFI_PROPERTY_CONFIG_VENC_COMMON_START + 0x00A)
346#define HFI_PROPERTY_CONFIG_VENC_HIER_P_ENH_LAYER \
347 (HFI_PROPERTY_CONFIG_VENC_COMMON_START + 0x00B)
Praneeth Paladugu6e6fbdb2017-01-16 15:43:01 -0800348#define HFI_PROPERTY_CONFIG_VENC_PERF_MODE \
349 (HFI_PROPERTY_CONFIG_VENC_COMMON_START + 0x00E)
350#define HFI_PROPERTY_CONFIG_VENC_BASELAYER_PRIORITYID \
351 (HFI_PROPERTY_CONFIG_VENC_COMMON_START + 0x00F)
Chinmay Sawarkar79f56a62017-06-30 12:46:39 -0700352#define HFI_PROPERTY_CONFIG_VENC_BLUR_FRAME_SIZE \
353 (HFI_PROPERTY_CONFIG_VENC_COMMON_START + 0x010)
Shivendra Kakrania90cf3c72017-06-23 13:35:11 -0700354#define HFI_PROPERTY_CONFIG_VENC_FRAME_QP \
Praneeth Paladugu7fbd2792017-01-27 13:39:03 -0800355 (HFI_PROPERTY_CONFIG_VENC_COMMON_START + 0x012)
356
Chinmay Sawarkar582c72a2017-05-24 14:29:12 -0700357#define HFI_PROPERTY_PARAM_VPE_COMMON_START \
358 (HFI_DOMAIN_BASE_VPE + HFI_ARCH_COMMON_OFFSET + 0x7000)
359#define HFI_PROPERTY_PARAM_VPE_ROTATION \
360 (HFI_PROPERTY_PARAM_VPE_COMMON_START + 0x001)
Praneeth Paladugu6e6fbdb2017-01-16 15:43:01 -0800361
362#define HFI_PROPERTY_CONFIG_VPE_COMMON_START \
363 (HFI_DOMAIN_BASE_VPE + HFI_ARCH_COMMON_OFFSET + 0x8000)
Praneeth Paladugu6e6fbdb2017-01-16 15:43:01 -0800364
365struct hfi_pic_struct {
366 u32 progressive_only;
367};
368
369struct hfi_bitrate {
370 u32 bit_rate;
371 u32 layer_id;
372};
373
374struct hfi_colour_space {
375 u32 colour_space;
376};
377
378#define HFI_CAPABILITY_FRAME_WIDTH (HFI_COMMON_BASE + 0x1)
379#define HFI_CAPABILITY_FRAME_HEIGHT (HFI_COMMON_BASE + 0x2)
380#define HFI_CAPABILITY_MBS_PER_FRAME (HFI_COMMON_BASE + 0x3)
381#define HFI_CAPABILITY_MBS_PER_SECOND (HFI_COMMON_BASE + 0x4)
382#define HFI_CAPABILITY_FRAMERATE (HFI_COMMON_BASE + 0x5)
383#define HFI_CAPABILITY_SCALE_X (HFI_COMMON_BASE + 0x6)
384#define HFI_CAPABILITY_SCALE_Y (HFI_COMMON_BASE + 0x7)
385#define HFI_CAPABILITY_BITRATE (HFI_COMMON_BASE + 0x8)
386#define HFI_CAPABILITY_BFRAME (HFI_COMMON_BASE + 0x9)
387#define HFI_CAPABILITY_PEAKBITRATE (HFI_COMMON_BASE + 0xa)
388#define HFI_CAPABILITY_HIER_P_NUM_ENH_LAYERS (HFI_COMMON_BASE + 0x10)
389#define HFI_CAPABILITY_ENC_LTR_COUNT (HFI_COMMON_BASE + 0x11)
390#define HFI_CAPABILITY_CP_OUTPUT2_THRESH (HFI_COMMON_BASE + 0x12)
391#define HFI_CAPABILITY_HIER_B_NUM_ENH_LAYERS (HFI_COMMON_BASE + 0x13)
392#define HFI_CAPABILITY_LCU_SIZE (HFI_COMMON_BASE + 0x14)
393#define HFI_CAPABILITY_HIER_P_HYBRID_NUM_ENH_LAYERS (HFI_COMMON_BASE + 0x15)
394#define HFI_CAPABILITY_MBS_PER_SECOND_POWERSAVE (HFI_COMMON_BASE + 0x16)
Praneeth Paladugu520c7592017-01-26 13:53:14 -0800395#define HFI_CAPABILITY_EXTRADATA (HFI_COMMON_BASE + 0X17)
396#define HFI_CAPABILITY_PROFILE (HFI_COMMON_BASE + 0X18)
397#define HFI_CAPABILITY_LEVEL (HFI_COMMON_BASE + 0X19)
398#define HFI_CAPABILITY_I_FRAME_QP (HFI_COMMON_BASE + 0X20)
399#define HFI_CAPABILITY_P_FRAME_QP (HFI_COMMON_BASE + 0X21)
400#define HFI_CAPABILITY_B_FRAME_QP (HFI_COMMON_BASE + 0X22)
401#define HFI_CAPABILITY_RATE_CONTROL_MODES (HFI_COMMON_BASE + 0X23)
402#define HFI_CAPABILITY_BLUR_WIDTH (HFI_COMMON_BASE + 0X24)
403#define HFI_CAPABILITY_BLUR_HEIGHT (HFI_COMMON_BASE + 0X25)
404#define HFI_CAPABILITY_SLICE_DELIVERY_MODES (HFI_COMMON_BASE + 0X26)
405#define HFI_CAPABILITY_SLICE_BYTE (HFI_COMMON_BASE + 0X27)
406#define HFI_CAPABILITY_SLICE_MB (HFI_COMMON_BASE + 0X28)
407#define HFI_CAPABILITY_SECURE (HFI_COMMON_BASE + 0X29)
408#define HFI_CAPABILITY_MAX_NUM_B_FRAMES (HFI_COMMON_BASE + 0X2A)
409#define HFI_CAPABILITY_MAX_VIDEOCORES (HFI_COMMON_BASE + 0X2B)
410#define HFI_CAPABILITY_MAX_WORKMODES (HFI_COMMON_BASE + 0X2C)
411#define HFI_CAPABILITY_UBWC_CR_STATS (HFI_COMMON_BASE + 0X2D)
Praneeth Paladugu6e6fbdb2017-01-16 15:43:01 -0800412
413struct hfi_capability_supported {
414 u32 capability_type;
415 u32 min;
416 u32 max;
417 u32 step_size;
418};
419
420struct hfi_capability_supported_info {
421 u32 num_capabilities;
422 struct hfi_capability_supported rg_data[1];
423};
424
425#define HFI_DEBUG_MSG_LOW 0x00000001
426#define HFI_DEBUG_MSG_MEDIUM 0x00000002
427#define HFI_DEBUG_MSG_HIGH 0x00000004
428#define HFI_DEBUG_MSG_ERROR 0x00000008
429#define HFI_DEBUG_MSG_FATAL 0x00000010
430#define HFI_DEBUG_MSG_PERF 0x00000020
431
432#define HFI_DEBUG_MODE_QUEUE 0x00000001
433#define HFI_DEBUG_MODE_QDSS 0x00000002
434
435struct hfi_debug_config {
436 u32 debug_config;
437 u32 debug_mode;
438};
439
440struct hfi_enable {
441 u32 enable;
442};
443
444#define HFI_H264_DB_MODE_DISABLE (HFI_COMMON_BASE + 0x1)
445#define HFI_H264_DB_MODE_SKIP_SLICE_BOUNDARY \
446 (HFI_COMMON_BASE + 0x2)
447#define HFI_H264_DB_MODE_ALL_BOUNDARY (HFI_COMMON_BASE + 0x3)
448
449struct hfi_h264_db_control {
450 u32 mode;
451 u32 slice_alpha_offset;
452 u32 slice_beta_offset;
453};
454
455#define HFI_H264_ENTROPY_CAVLC (HFI_COMMON_BASE + 0x1)
456#define HFI_H264_ENTROPY_CABAC (HFI_COMMON_BASE + 0x2)
457
458#define HFI_H264_CABAC_MODEL_0 (HFI_COMMON_BASE + 0x1)
459#define HFI_H264_CABAC_MODEL_1 (HFI_COMMON_BASE + 0x2)
460#define HFI_H264_CABAC_MODEL_2 (HFI_COMMON_BASE + 0x3)
461
462struct hfi_h264_entropy_control {
463 u32 entropy_mode;
464 u32 cabac_model;
465};
466
467struct hfi_frame_rate {
468 u32 buffer_type;
469 u32 frame_rate;
470};
471
472#define HFI_INTRA_REFRESH_NONE (HFI_COMMON_BASE + 0x1)
473#define HFI_INTRA_REFRESH_CYCLIC (HFI_COMMON_BASE + 0x2)
Saurabh Kothawade11e05722017-05-16 19:07:58 -0700474#define HFI_INTRA_REFRESH_RANDOM (HFI_COMMON_BASE + 0x5)
Praneeth Paladugu6e6fbdb2017-01-16 15:43:01 -0800475
476struct hfi_intra_refresh {
477 u32 mode;
Praneeth Paladugu6e6fbdb2017-01-16 15:43:01 -0800478 u32 mbs;
479};
480
481struct hfi_idr_period {
482 u32 idr_period;
483};
484
Chinmay Sawarkar582c72a2017-05-24 14:29:12 -0700485struct hfi_vpe_rotation_type {
Praneeth Paladugu6e6fbdb2017-01-16 15:43:01 -0800486 u32 rotation;
487 u32 flip;
488};
489
Praneeth Paladugu6e6fbdb2017-01-16 15:43:01 -0800490struct hfi_conceal_color {
Umesh Pandey42313a72017-07-05 18:20:06 -0700491 u32 conceal_color_8bit;
492 u32 conceal_color_10bit;
Praneeth Paladugu6e6fbdb2017-01-16 15:43:01 -0800493};
494
495struct hfi_intra_period {
496 u32 pframes;
497 u32 bframes;
498};
499
Praneeth Paladugu6e6fbdb2017-01-16 15:43:01 -0800500struct hfi_multi_stream {
501 u32 buffer_type;
502 u32 enable;
Praneeth Paladugu6e6fbdb2017-01-16 15:43:01 -0800503};
504
505struct hfi_multi_view_format {
506 u32 views;
507 u32 rg_view_order[1];
508};
509
510#define HFI_MULTI_SLICE_OFF (HFI_COMMON_BASE + 0x1)
511#define HFI_MULTI_SLICE_BY_MB_COUNT (HFI_COMMON_BASE + 0x2)
512#define HFI_MULTI_SLICE_BY_BYTE_COUNT (HFI_COMMON_BASE + 0x3)
Praneeth Paladugu6e6fbdb2017-01-16 15:43:01 -0800513
514struct hfi_multi_slice_control {
515 u32 multi_slice;
516 u32 slice_size;
517};
518
519#define HFI_NAL_FORMAT_STARTCODES 0x00000001
520#define HFI_NAL_FORMAT_ONE_NAL_PER_BUFFER 0x00000002
521#define HFI_NAL_FORMAT_ONE_BYTE_LENGTH 0x00000004
522#define HFI_NAL_FORMAT_TWO_BYTE_LENGTH 0x00000008
523#define HFI_NAL_FORMAT_FOUR_BYTE_LENGTH 0x00000010
524
525struct hfi_nal_stream_format_supported {
526 u32 nal_stream_format_supported;
527};
528
529struct hfi_nal_stream_format_select {
530 u32 nal_stream_format_select;
531};
532#define HFI_PICTURE_TYPE_I 0x01
533#define HFI_PICTURE_TYPE_P 0x02
534#define HFI_PICTURE_TYPE_B 0x04
535#define HFI_PICTURE_TYPE_IDR 0x08
536#define HFI_PICTURE_TYPE_CRA 0x10
537
538struct hfi_profile_level {
539 u32 profile;
540 u32 level;
541};
542
543struct hfi_profile_level_supported {
544 u32 profile_count;
545 struct hfi_profile_level rg_profile_level[1];
546};
547
548struct hfi_quality_vs_speed {
549 u32 quality_vs_speed;
550};
551
552struct hfi_quantization {
Chinmay Sawarkar2de3f772017-02-07 12:03:44 -0800553 u32 qp_packed;
Praneeth Paladugu6e6fbdb2017-01-16 15:43:01 -0800554 u32 layer_id;
Vaibhav Deshu Venkatesh3a147162017-04-27 16:21:12 -0700555 u32 enable;
556 u32 reserved[3];
Praneeth Paladugu6e6fbdb2017-01-16 15:43:01 -0800557};
558
Praneeth Paladugu6e6fbdb2017-01-16 15:43:01 -0800559struct hfi_quantization_range {
Chinmay Sawarkar2de3f772017-02-07 12:03:44 -0800560 struct hfi_quantization min_qp;
561 struct hfi_quantization max_qp;
Umesh Pandey3cfce632017-03-02 13:56:18 -0800562 u32 reserved[4];
Praneeth Paladugu6e6fbdb2017-01-16 15:43:01 -0800563};
564
565#define HFI_LTR_MODE_DISABLE 0x0
566#define HFI_LTR_MODE_MANUAL 0x1
Praneeth Paladugu6e6fbdb2017-01-16 15:43:01 -0800567
568struct hfi_ltr_mode {
569 u32 ltr_mode;
570 u32 ltr_count;
571 u32 trust_mode;
572};
573
574struct hfi_ltr_use {
575 u32 ref_ltr;
576 u32 use_constrnt;
577 u32 frames;
578};
579
580struct hfi_ltr_mark {
581 u32 mark_frame;
582};
583
584struct hfi_frame_size {
585 u32 buffer_type;
586 u32 width;
587 u32 height;
588};
589
Praneeth Paladugu238977b2016-12-06 12:51:26 -0800590struct hfi_videocores_usage_type {
591 u32 video_core_enable_mask;
592};
593
594struct hfi_video_work_mode {
595 u32 video_work_mode;
596};
597
Praneeth Paladugu6e6fbdb2017-01-16 15:43:01 -0800598struct hfi_video_signal_metadata {
599 u32 enable;
600 u32 video_format;
601 u32 video_full_range;
602 u32 color_description;
603 u32 color_primaries;
604 u32 transfer_characteristics;
605 u32 matrix_coeffs;
606};
607
Chinmay Sawarkard0054622017-05-04 13:50:59 -0700608struct hfi_vui_timing_info {
Praneeth Paladugu6e6fbdb2017-01-16 15:43:01 -0800609 u32 enable;
610 u32 fixed_frame_rate;
611 u32 time_scale;
612};
613
614struct hfi_bit_depth {
615 u32 buffer_type;
616 u32 bit_depth;
617};
618
619struct hfi_picture_type {
620 u32 is_sync_frame;
621 u32 picture_type;
622};
623
624/* Base Offset for UBWC color formats */
625#define HFI_COLOR_FORMAT_UBWC_BASE (0x8000)
626/* Base Offset for 10-bit color formats */
627#define HFI_COLOR_FORMAT_10_BIT_BASE (0x4000)
628
629#define HFI_COLOR_FORMAT_MONOCHROME (HFI_COMMON_BASE + 0x1)
630#define HFI_COLOR_FORMAT_NV12 (HFI_COMMON_BASE + 0x2)
631#define HFI_COLOR_FORMAT_NV21 (HFI_COMMON_BASE + 0x3)
632#define HFI_COLOR_FORMAT_NV12_4x4TILE (HFI_COMMON_BASE + 0x4)
633#define HFI_COLOR_FORMAT_NV21_4x4TILE (HFI_COMMON_BASE + 0x5)
634#define HFI_COLOR_FORMAT_YUYV (HFI_COMMON_BASE + 0x6)
635#define HFI_COLOR_FORMAT_YVYU (HFI_COMMON_BASE + 0x7)
636#define HFI_COLOR_FORMAT_UYVY (HFI_COMMON_BASE + 0x8)
637#define HFI_COLOR_FORMAT_VYUY (HFI_COMMON_BASE + 0x9)
638#define HFI_COLOR_FORMAT_RGB565 (HFI_COMMON_BASE + 0xA)
639#define HFI_COLOR_FORMAT_BGR565 (HFI_COMMON_BASE + 0xB)
640#define HFI_COLOR_FORMAT_RGB888 (HFI_COMMON_BASE + 0xC)
641#define HFI_COLOR_FORMAT_BGR888 (HFI_COMMON_BASE + 0xD)
642#define HFI_COLOR_FORMAT_YUV444 (HFI_COMMON_BASE + 0xE)
643#define HFI_COLOR_FORMAT_RGBA8888 (HFI_COMMON_BASE + 0x10)
644
Chinmay Sawarkar2de3f772017-02-07 12:03:44 -0800645#define HFI_COLOR_FORMAT_YUV420_TP10 \
Umesh Pandey3cfce632017-03-02 13:56:18 -0800646 (HFI_COLOR_FORMAT_10_BIT_BASE + HFI_COLOR_FORMAT_NV12)
647#define HFI_COLOR_FORMAT_P010 \
648 (HFI_COLOR_FORMAT_10_BIT_BASE + HFI_COLOR_FORMAT_NV12 + 0x1)
Praneeth Paladugu6e6fbdb2017-01-16 15:43:01 -0800649
650#define HFI_COLOR_FORMAT_NV12_UBWC \
651 (HFI_COLOR_FORMAT_UBWC_BASE + HFI_COLOR_FORMAT_NV12)
652
653#define HFI_COLOR_FORMAT_YUV420_TP10_UBWC \
654 (HFI_COLOR_FORMAT_UBWC_BASE + HFI_COLOR_FORMAT_YUV420_TP10)
655
656#define HFI_COLOR_FORMAT_RGBA8888_UBWC \
657 (HFI_COLOR_FORMAT_UBWC_BASE + HFI_COLOR_FORMAT_RGBA8888)
658
659#define HFI_MAX_MATRIX_COEFFS 9
660#define HFI_MAX_BIAS_COEFFS 3
661#define HFI_MAX_LIMIT_COEFFS 6
662
663#define HFI_STATISTICS_MODE_DEFAULT 0x10
664#define HFI_STATISTICS_MODE_1 0x11
665#define HFI_STATISTICS_MODE_2 0x12
666#define HFI_STATISTICS_MODE_3 0x13
667
668struct hfi_uncompressed_format_select {
669 u32 buffer_type;
670 u32 format;
671};
672
673struct hfi_uncompressed_format_supported {
674 u32 buffer_type;
675 u32 format_entries;
676 u32 rg_format_info[1];
677};
678
679struct hfi_uncompressed_plane_actual {
680 u32 actual_stride;
681 u32 actual_plane_buffer_height;
682};
683
684struct hfi_uncompressed_plane_actual_info {
685 u32 buffer_type;
686 u32 num_planes;
687 struct hfi_uncompressed_plane_actual rg_plane_format[1];
688};
689
690struct hfi_uncompressed_plane_constraints {
691 u32 stride_multiples;
692 u32 max_stride;
693 u32 min_plane_buffer_height_multiple;
694 u32 buffer_alignment;
695};
696
697struct hfi_uncompressed_plane_info {
698 u32 format;
699 u32 num_planes;
700 struct hfi_uncompressed_plane_constraints rg_plane_format[1];
701};
702
703struct hfi_codec_supported {
704 u32 decoder_codec_supported;
705 u32 encoder_codec_supported;
706};
707
708struct hfi_properties_supported {
709 u32 num_properties;
710 u32 rg_properties[1];
711};
712
713struct hfi_max_sessions_supported {
714 u32 max_sessions;
715};
716
717struct hfi_vpe_color_space_conversion {
718 u32 csc_matrix[HFI_MAX_MATRIX_COEFFS];
719 u32 csc_bias[HFI_MAX_BIAS_COEFFS];
720 u32 csc_limit[HFI_MAX_LIMIT_COEFFS];
721};
722
Praneeth Paladugu6e6fbdb2017-01-16 15:43:01 -0800723#define HFI_ROTATE_NONE (HFI_COMMON_BASE + 0x1)
724#define HFI_ROTATE_90 (HFI_COMMON_BASE + 0x2)
725#define HFI_ROTATE_180 (HFI_COMMON_BASE + 0x3)
726#define HFI_ROTATE_270 (HFI_COMMON_BASE + 0x4)
727
728#define HFI_FLIP_NONE (HFI_COMMON_BASE + 0x1)
729#define HFI_FLIP_HORIZONTAL (HFI_COMMON_BASE + 0x2)
Chinmay Sawarkar582c72a2017-05-24 14:29:12 -0700730#define HFI_FLIP_VERTICAL (HFI_COMMON_BASE + 0x4)
Praneeth Paladugu6e6fbdb2017-01-16 15:43:01 -0800731
Shivendra Kakraniac1f60e02017-04-13 00:07:26 -0700732#define HFI_RESOURCE_SYSCACHE 0x00000002
Praneeth Paladugu6e6fbdb2017-01-16 15:43:01 -0800733
Shivendra Kakraniac1f60e02017-04-13 00:07:26 -0700734struct hfi_resource_subcache_type {
Praneeth Paladugu6e6fbdb2017-01-16 15:43:01 -0800735 u32 size;
Shivendra Kakraniac1f60e02017-04-13 00:07:26 -0700736 u32 sc_id;
Praneeth Paladugu6e6fbdb2017-01-16 15:43:01 -0800737};
738
Shivendra Kakraniac1f60e02017-04-13 00:07:26 -0700739struct hfi_resource_syscache_info_type {
Praneeth Paladugu6e6fbdb2017-01-16 15:43:01 -0800740 u32 num_entries;
Shivendra Kakraniac1f60e02017-04-13 00:07:26 -0700741 struct hfi_resource_subcache_type rg_subcache_entries[1];
Praneeth Paladugu6e6fbdb2017-01-16 15:43:01 -0800742};
743
744struct hfi_property_sys_image_version_info_type {
745 u32 string_size;
746 u8 str_image_version[1];
747};
748
749struct hfi_venc_config_advanced {
750 u8 pipe2d;
751 u8 hw_mode;
752 u8 low_delay_enforce;
753 u8 worker_vppsg_delay;
754 u32 close_gop;
755 u32 h264_constrain_intra_pred;
756 u32 h264_transform_8x8_flag;
Praneeth Paladugu6e6fbdb2017-01-16 15:43:01 -0800757 u32 multi_refp_en;
758 u32 qmatrix_en;
759 u8 vpp_info_packet_mode;
760 u8 ref_tile_mode;
761 u8 bitstream_flush_mode;
762 u32 vppsg_vspap_fb_sync_delay;
763 u32 rc_initial_delay;
764 u32 peak_bitrate_constraint;
765 u32 ds_display_frame_width;
766 u32 ds_display_frame_height;
767 u32 perf_tune_param_ptr;
768 u32 input_x_offset;
769 u32 input_y_offset;
770 u32 input_roi_width;
771 u32 input_roi_height;
772 u32 vsp_fifo_dma_sel;
773 u32 h264_num_ref_frames;
774};
775
776struct hfi_vbv_hrd_bufsize {
777 u32 buffer_size;
778};
779
780struct hfi_codec_mask_supported {
781 u32 codecs;
782 u32 video_domains;
783};
784
Praneeth Paladugu6e6fbdb2017-01-16 15:43:01 -0800785struct hfi_aspect_ratio {
786 u32 aspect_width;
787 u32 aspect_height;
788};
789
790#define HFI_IFRAME_SIZE_DEFAULT (HFI_COMMON_BASE + 0x1)
791#define HFI_IFRAME_SIZE_MEDIUM (HFI_COMMON_BASE + 0x2)
792#define HFI_IFRAME_SIZE_HIGH (HFI_COMMON_BASE + 0x3)
793#define HFI_IFRAME_SIZE_UNLIMITED (HFI_COMMON_BASE + 0x4)
794struct hfi_iframe_size {
795 u32 type;
796};
797
Praneeth Paladugu6e6fbdb2017-01-16 15:43:01 -0800798
799#define HFI_CMD_SYS_COMMON_START \
800(HFI_DOMAIN_BASE_COMMON + HFI_ARCH_COMMON_OFFSET + HFI_CMD_START_OFFSET \
801 + 0x0000)
802#define HFI_CMD_SYS_INIT (HFI_CMD_SYS_COMMON_START + 0x001)
803#define HFI_CMD_SYS_PC_PREP (HFI_CMD_SYS_COMMON_START + 0x002)
804#define HFI_CMD_SYS_SET_RESOURCE (HFI_CMD_SYS_COMMON_START + 0x003)
805#define HFI_CMD_SYS_RELEASE_RESOURCE (HFI_CMD_SYS_COMMON_START + 0x004)
806#define HFI_CMD_SYS_SET_PROPERTY (HFI_CMD_SYS_COMMON_START + 0x005)
807#define HFI_CMD_SYS_GET_PROPERTY (HFI_CMD_SYS_COMMON_START + 0x006)
808#define HFI_CMD_SYS_SESSION_INIT (HFI_CMD_SYS_COMMON_START + 0x007)
809#define HFI_CMD_SYS_SESSION_END (HFI_CMD_SYS_COMMON_START + 0x008)
810#define HFI_CMD_SYS_SET_BUFFERS (HFI_CMD_SYS_COMMON_START + 0x009)
811#define HFI_CMD_SYS_TEST_START (HFI_CMD_SYS_COMMON_START + 0x100)
812
813#define HFI_CMD_SESSION_COMMON_START \
814 (HFI_DOMAIN_BASE_COMMON + HFI_ARCH_COMMON_OFFSET + \
815 HFI_CMD_START_OFFSET + 0x1000)
816#define HFI_CMD_SESSION_SET_PROPERTY \
817 (HFI_CMD_SESSION_COMMON_START + 0x001)
818#define HFI_CMD_SESSION_SET_BUFFERS \
819 (HFI_CMD_SESSION_COMMON_START + 0x002)
820#define HFI_CMD_SESSION_GET_SEQUENCE_HEADER \
821 (HFI_CMD_SESSION_COMMON_START + 0x003)
822
823#define HFI_MSG_SYS_COMMON_START \
824 (HFI_DOMAIN_BASE_COMMON + HFI_ARCH_COMMON_OFFSET + \
825 HFI_MSG_START_OFFSET + 0x0000)
826#define HFI_MSG_SYS_INIT_DONE (HFI_MSG_SYS_COMMON_START + 0x1)
827#define HFI_MSG_SYS_PC_PREP_DONE (HFI_MSG_SYS_COMMON_START + 0x2)
828#define HFI_MSG_SYS_RELEASE_RESOURCE (HFI_MSG_SYS_COMMON_START + 0x3)
829#define HFI_MSG_SYS_DEBUG (HFI_MSG_SYS_COMMON_START + 0x4)
830#define HFI_MSG_SYS_SESSION_INIT_DONE (HFI_MSG_SYS_COMMON_START + 0x6)
831#define HFI_MSG_SYS_SESSION_END_DONE (HFI_MSG_SYS_COMMON_START + 0x7)
832#define HFI_MSG_SYS_IDLE (HFI_MSG_SYS_COMMON_START + 0x8)
833#define HFI_MSG_SYS_COV (HFI_MSG_SYS_COMMON_START + 0x9)
834#define HFI_MSG_SYS_PROPERTY_INFO (HFI_MSG_SYS_COMMON_START + 0xA)
835#define HFI_MSG_SESSION_SYNC_DONE (HFI_MSG_SESSION_OX_START + 0xD)
836
837#define HFI_MSG_SESSION_COMMON_START \
838 (HFI_DOMAIN_BASE_COMMON + HFI_ARCH_COMMON_OFFSET + \
839 HFI_MSG_START_OFFSET + 0x1000)
840#define HFI_MSG_EVENT_NOTIFY (HFI_MSG_SESSION_COMMON_START + 0x1)
841#define HFI_MSG_SESSION_GET_SEQUENCE_HEADER_DONE \
842 (HFI_MSG_SESSION_COMMON_START + 0x2)
843
844#define HFI_CMD_SYS_TEST_SSR (HFI_CMD_SYS_TEST_START + 0x1)
845#define HFI_TEST_SSR_SW_ERR_FATAL 0x1
846#define HFI_TEST_SSR_SW_DIV_BY_ZERO 0x2
847#define HFI_TEST_SSR_HW_WDOG_IRQ 0x3
848
849struct vidc_hal_cmd_pkt_hdr {
850 u32 size;
851 u32 packet_type;
852};
853
854struct vidc_hal_msg_pkt_hdr {
855 u32 size;
856 u32 packet;
857};
858
859struct vidc_hal_session_cmd_pkt {
860 u32 size;
861 u32 packet_type;
862 u32 session_id;
863};
864
865struct hfi_cmd_sys_init_packet {
866 u32 size;
867 u32 packet_type;
868 u32 arch_type;
869};
870
871struct hfi_cmd_sys_pc_prep_packet {
872 u32 size;
873 u32 packet_type;
874};
875
876struct hfi_cmd_sys_set_resource_packet {
877 u32 size;
878 u32 packet_type;
879 u32 resource_handle;
880 u32 resource_type;
881 u32 rg_resource_data[1];
882};
883
884struct hfi_cmd_sys_release_resource_packet {
885 u32 size;
886 u32 packet_type;
887 u32 resource_type;
888 u32 resource_handle;
889};
890
891struct hfi_cmd_sys_set_property_packet {
892 u32 size;
893 u32 packet_type;
894 u32 num_properties;
895 u32 rg_property_data[1];
896};
897
898struct hfi_cmd_sys_get_property_packet {
899 u32 size;
900 u32 packet_type;
901 u32 num_properties;
902 u32 rg_property_data[1];
903};
904
905struct hfi_cmd_sys_session_init_packet {
906 u32 size;
907 u32 packet_type;
908 u32 session_id;
909 u32 session_domain;
910 u32 session_codec;
911};
912
913struct hfi_cmd_sys_session_end_packet {
914 u32 size;
915 u32 packet_type;
916 u32 session_id;
917};
918
919struct hfi_cmd_sys_set_buffers_packet {
920 u32 size;
921 u32 packet_type;
922 u32 buffer_type;
923 u32 buffer_size;
924 u32 num_buffers;
925 u32 rg_buffer_addr[1];
926};
927
928struct hfi_cmd_session_set_property_packet {
929 u32 size;
930 u32 packet_type;
931 u32 session_id;
932 u32 num_properties;
933 u32 rg_property_data[0];
934};
935
936struct hfi_cmd_session_set_buffers_packet {
937 u32 size;
938 u32 packet_type;
939 u32 session_id;
940 u32 buffer_type;
941 u32 buffer_size;
942 u32 extra_data_size;
943 u32 min_buffer_size;
944 u32 num_buffers;
945 u32 rg_buffer_info[1];
946};
947
Praneeth Paladugu6e6fbdb2017-01-16 15:43:01 -0800948struct hfi_cmd_session_sync_process_packet {
949 u32 size;
950 u32 packet_type;
951 u32 session_id;
952 u32 sync_id;
953 u32 rg_data[1];
954};
955
956struct hfi_msg_event_notify_packet {
957 u32 size;
958 u32 packet_type;
959 u32 session_id;
960 u32 event_id;
961 u32 event_data1;
962 u32 event_data2;
963 u32 rg_ext_event_data[1];
964};
965
966struct hfi_msg_release_buffer_ref_event_packet {
967 u32 packet_buffer;
968 u32 extra_data_buffer;
969 u32 output_tag;
970};
971
972struct hfi_msg_sys_init_done_packet {
973 u32 size;
974 u32 packet_type;
975 u32 error_type;
976 u32 num_properties;
977 u32 rg_property_data[1];
978};
979
980struct hfi_msg_sys_pc_prep_done_packet {
981 u32 size;
982 u32 packet_type;
983 u32 error_type;
984};
985
986struct hfi_msg_sys_release_resource_done_packet {
987 u32 size;
988 u32 packet_type;
989 u32 resource_handle;
990 u32 error_type;
991};
992
993struct hfi_msg_sys_session_init_done_packet {
994 u32 size;
995 u32 packet_type;
996 u32 session_id;
997 u32 error_type;
998 u32 num_properties;
999 u32 rg_property_data[1];
1000};
1001
1002struct hfi_msg_sys_session_end_done_packet {
1003 u32 size;
1004 u32 packet_type;
1005 u32 session_id;
1006 u32 error_type;
1007};
1008
1009struct hfi_msg_session_get_sequence_header_done_packet {
1010 u32 size;
1011 u32 packet_type;
1012 u32 session_id;
1013 u32 error_type;
1014 u32 header_len;
1015 u32 sequence_header;
1016};
1017
1018struct hfi_msg_sys_debug_packet {
1019 u32 size;
1020 u32 packet_type;
1021 u32 msg_type;
1022 u32 msg_size;
1023 u32 time_stamp_hi;
1024 u32 time_stamp_lo;
1025 u8 rg_msg_data[1];
1026};
1027
1028struct hfi_msg_sys_coverage_packet {
1029 u32 size;
1030 u32 packet_type;
1031 u32 msg_size;
1032 u32 time_stamp_hi;
1033 u32 time_stamp_lo;
1034 u8 rg_msg_data[1];
1035};
1036
1037enum HFI_VENUS_QTBL_STATUS {
1038 HFI_VENUS_QTBL_DISABLED = 0x00,
1039 HFI_VENUS_QTBL_ENABLED = 0x01,
1040 HFI_VENUS_QTBL_INITIALIZING = 0x02,
1041 HFI_VENUS_QTBL_DEINITIALIZING = 0x03
1042};
1043
1044enum HFI_VENUS_CTRL_INIT_STATUS {
1045 HFI_VENUS_CTRL_NOT_INIT = 0x0,
1046 HFI_VENUS_CTRL_READY = 0x1,
1047 HFI_VENUS_CTRL_ERROR_FATAL = 0x2
1048};
1049
1050struct hfi_sfr_struct {
1051 u32 bufSize;
1052 u8 rg_data[1];
1053};
1054
1055struct hfi_cmd_sys_test_ssr_packet {
1056 u32 size;
1057 u32 packet_type;
1058 u32 trigger_type;
1059};
1060#endif