blob: 19b43f37e1a3324f474d4a76f750e45d317c131f [file] [log] [blame]
Bryan Wu1394f032007-05-06 14:50:22 -07001#
2# For a description of the syntax of this configuration file,
3# see Documentation/kbuild/kconfig-language.txt.
4#
5
Mike Frysinger53f8a252007-11-15 15:48:01 +08006mainmenu "Blackfin Kernel Configuration"
Bryan Wu1394f032007-05-06 14:50:22 -07007
8config MMU
9 bool
10 default n
11
12config FPU
13 bool
14 default n
15
16config RWSEM_GENERIC_SPINLOCK
17 bool
18 default y
19
20config RWSEM_XCHGADD_ALGORITHM
21 bool
22 default n
23
24config BLACKFIN
25 bool
26 default y
Sam Ravnborgec7748b2008-02-09 10:46:40 +010027 select HAVE_IDE
Mathieu Desnoyers42d4b832008-02-02 15:10:34 -050028 select HAVE_OPROFILE
Bryan Wu1394f032007-05-06 14:50:22 -070029
Aubrey Lie3defff2007-05-21 18:09:11 +080030config ZONE_DMA
31 bool
32 default y
33
Bryan Wu1394f032007-05-06 14:50:22 -070034config GENERIC_FIND_NEXT_BIT
35 bool
36 default y
37
38config GENERIC_HWEIGHT
39 bool
40 default y
41
42config GENERIC_HARDIRQS
43 bool
44 default y
45
46config GENERIC_IRQ_PROBE
Mike Frysingere4e9a7a2007-11-15 20:39:34 +080047 bool
Bryan Wu1394f032007-05-06 14:50:22 -070048 default y
49
Michael Hennerichb2d15832007-07-24 15:46:36 +080050config GENERIC_GPIO
Bryan Wu1394f032007-05-06 14:50:22 -070051 bool
52 default y
53
54config FORCE_MAX_ZONEORDER
55 int
56 default "14"
57
58config GENERIC_CALIBRATE_DELAY
59 bool
60 default y
61
Mathieu Desnoyers7d2284b2008-01-15 12:42:02 -050062config HARDWARE_PM
63 def_bool y
64 depends on OPROFILE
65
Bryan Wu1394f032007-05-06 14:50:22 -070066source "init/Kconfig"
Matt Helsleydc52ddc2008-10-18 20:27:21 -070067
Bryan Wu1394f032007-05-06 14:50:22 -070068source "kernel/Kconfig.preempt"
69
Matt Helsleydc52ddc2008-10-18 20:27:21 -070070source "kernel/Kconfig.freezer"
71
Bryan Wu1394f032007-05-06 14:50:22 -070072menu "Blackfin Processor Options"
73
74comment "Processor and Board Settings"
75
76choice
77 prompt "CPU"
78 default BF533
79
Bryan Wu2f6f4bc2008-11-18 17:48:21 +080080config BF512
81 bool "BF512"
82 help
83 BF512 Processor Support.
84
85config BF514
86 bool "BF514"
87 help
88 BF514 Processor Support.
89
90config BF516
91 bool "BF516"
92 help
93 BF516 Processor Support.
94
95config BF518
96 bool "BF518"
97 help
98 BF518 Processor Support.
99
Michael Hennerich59003142007-10-21 16:54:27 +0800100config BF522
101 bool "BF522"
102 help
103 BF522 Processor Support.
104
Mike Frysinger1545a112007-12-24 16:54:48 +0800105config BF523
106 bool "BF523"
107 help
108 BF523 Processor Support.
109
110config BF524
111 bool "BF524"
112 help
113 BF524 Processor Support.
114
Michael Hennerich59003142007-10-21 16:54:27 +0800115config BF525
116 bool "BF525"
117 help
118 BF525 Processor Support.
119
Mike Frysinger1545a112007-12-24 16:54:48 +0800120config BF526
121 bool "BF526"
122 help
123 BF526 Processor Support.
124
Michael Hennerich59003142007-10-21 16:54:27 +0800125config BF527
126 bool "BF527"
127 help
128 BF527 Processor Support.
129
Bryan Wu1394f032007-05-06 14:50:22 -0700130config BF531
131 bool "BF531"
132 help
133 BF531 Processor Support.
134
135config BF532
136 bool "BF532"
137 help
138 BF532 Processor Support.
139
140config BF533
141 bool "BF533"
142 help
143 BF533 Processor Support.
144
145config BF534
146 bool "BF534"
147 help
148 BF534 Processor Support.
149
150config BF536
151 bool "BF536"
152 help
153 BF536 Processor Support.
154
155config BF537
156 bool "BF537"
157 help
158 BF537 Processor Support.
159
Michael Hennerichdc26aec2008-11-18 17:48:22 +0800160config BF538
161 bool "BF538"
162 help
163 BF538 Processor Support.
164
165config BF539
166 bool "BF539"
167 help
168 BF539 Processor Support.
169
Roy Huang24a07a12007-07-12 22:41:45 +0800170config BF542
171 bool "BF542"
172 help
173 BF542 Processor Support.
174
175config BF544
176 bool "BF544"
177 help
178 BF544 Processor Support.
179
Mike Frysinger7c7fd172007-11-15 21:10:21 +0800180config BF547
181 bool "BF547"
182 help
183 BF547 Processor Support.
184
Roy Huang24a07a12007-07-12 22:41:45 +0800185config BF548
186 bool "BF548"
187 help
188 BF548 Processor Support.
189
190config BF549
191 bool "BF549"
192 help
193 BF549 Processor Support.
194
Bryan Wu1394f032007-05-06 14:50:22 -0700195config BF561
196 bool "BF561"
197 help
Mike Frysingercd88b4d2008-10-09 12:03:22 +0800198 BF561 Processor Support.
Bryan Wu1394f032007-05-06 14:50:22 -0700199
200endchoice
201
Mike Frysinger0c0497c2008-10-09 17:32:28 +0800202config BF_REV_MIN
203 int
Bryan Wu2f6f4bc2008-11-18 17:48:21 +0800204 default 0 if (BF51x || BF52x || BF54x)
Mike Frysinger0c0497c2008-10-09 17:32:28 +0800205 default 2 if (BF537 || BF536 || BF534)
206 default 3 if (BF561 ||BF533 || BF532 || BF531)
Bryan Wu2f6f4bc2008-11-18 17:48:21 +0800207 default 4 if (BF538 || BF539)
Mike Frysinger0c0497c2008-10-09 17:32:28 +0800208
209config BF_REV_MAX
210 int
Bryan Wu2f6f4bc2008-11-18 17:48:21 +0800211 default 2 if (BF51x || BF52x || BF54x)
Mike Frysinger0c0497c2008-10-09 17:32:28 +0800212 default 3 if (BF537 || BF536 || BF534)
Bryan Wu2f6f4bc2008-11-18 17:48:21 +0800213 default 5 if (BF561 || BF538 || BF539)
Mike Frysinger0c0497c2008-10-09 17:32:28 +0800214 default 6 if (BF533 || BF532 || BF531)
215
Bryan Wu1394f032007-05-06 14:50:22 -0700216choice
217 prompt "Silicon Rev"
Bryan Wu2f6f4bc2008-11-18 17:48:21 +0800218 default BF_REV_0_1 if (BF51x || BF52x || BF54x)
Mike Frysinger46ce0d92008-10-09 12:05:31 +0800219 default BF_REV_0_2 if (BF534 || BF536 || BF537)
220 default BF_REV_0_3 if (BF531 || BF532 || BF533 || BF561)
Roy Huang24a07a12007-07-12 22:41:45 +0800221
222config BF_REV_0_0
223 bool "0.0"
Bryan Wu2f6f4bc2008-11-18 17:48:21 +0800224 depends on (BF51x || BF52x || BF54x)
Michael Hennerich59003142007-10-21 16:54:27 +0800225
226config BF_REV_0_1
Mike Frysingerd07f4382007-11-15 15:49:17 +0800227 bool "0.1"
228 depends on (BF52x || BF54x)
Bryan Wu1394f032007-05-06 14:50:22 -0700229
230config BF_REV_0_2
231 bool "0.2"
Mike Frysinger49f72532008-10-09 12:06:27 +0800232 depends on (BF52x || BF537 || BF536 || BF534 || BF54x)
Bryan Wu1394f032007-05-06 14:50:22 -0700233
234config BF_REV_0_3
235 bool "0.3"
236 depends on (BF561 || BF537 || BF536 || BF534 || BF533 || BF532 || BF531)
237
238config BF_REV_0_4
239 bool "0.4"
Michael Hennerichdc26aec2008-11-18 17:48:22 +0800240 depends on (BF561 || BF533 || BF532 || BF531 || BF538 || BF539)
Bryan Wu1394f032007-05-06 14:50:22 -0700241
242config BF_REV_0_5
243 bool "0.5"
Michael Hennerichdc26aec2008-11-18 17:48:22 +0800244 depends on (BF561 || BF533 || BF532 || BF531 || BF538 || BF539)
Bryan Wu1394f032007-05-06 14:50:22 -0700245
Mike Frysinger49f72532008-10-09 12:06:27 +0800246config BF_REV_0_6
247 bool "0.6"
248 depends on (BF533 || BF532 || BF531)
249
Jie Zhangde3025f2007-06-25 18:04:12 +0800250config BF_REV_ANY
251 bool "any"
252
253config BF_REV_NONE
254 bool "none"
255
Bryan Wu1394f032007-05-06 14:50:22 -0700256endchoice
257
Bryan Wu2f6f4bc2008-11-18 17:48:21 +0800258config BF51x
259 bool
260 depends on (BF512 || BF514 || BF516 || BF518)
261 default y
262
Michael Hennerich59003142007-10-21 16:54:27 +0800263config BF52x
264 bool
Mike Frysinger1545a112007-12-24 16:54:48 +0800265 depends on (BF522 || BF523 || BF524 || BF525 || BF526 || BF527)
Michael Hennerich59003142007-10-21 16:54:27 +0800266 default y
267
Roy Huang24a07a12007-07-12 22:41:45 +0800268config BF53x
269 bool
270 depends on (BF531 || BF532 || BF533 || BF534 || BF536 || BF537)
271 default y
272
273config BF54x
274 bool
Mike Frysinger7c7fd172007-11-15 21:10:21 +0800275 depends on (BF542 || BF544 || BF547 || BF548 || BF549)
Roy Huang24a07a12007-07-12 22:41:45 +0800276 default y
277
Bryan Wu1394f032007-05-06 14:50:22 -0700278config MEM_GENERIC_BOARD
279 bool
280 depends on GENERIC_BOARD
281 default y
282
283config MEM_MT48LC64M4A2FB_7E
284 bool
285 depends on (BFIN533_STAMP)
286 default y
287
288config MEM_MT48LC16M16A2TG_75
289 bool
290 depends on (BFIN533_EZKIT || BFIN561_EZKIT \
Javier Herreroab472a02007-10-29 16:14:44 +0800291 || BFIN533_BLUETECHNIX_CM || BFIN537_BLUETECHNIX_CM \
Michael Hennerich9db144f2008-07-19 17:16:07 +0800292 || H8606_HVSISTEMAS || BFIN527_BLUETECHNIX_CM)
Bryan Wu1394f032007-05-06 14:50:22 -0700293 default y
294
295config MEM_MT48LC32M8A2_75
296 bool
Michael Hennerichdc26aec2008-11-18 17:48:22 +0800297 depends on (BFIN537_STAMP || PNAV10 || BFIN538_EZKIT)
Bryan Wu1394f032007-05-06 14:50:22 -0700298 default y
299
300config MEM_MT48LC8M32B2B5_7
301 bool
302 depends on (BFIN561_BLUETECHNIX_CM)
303 default y
304
Michael Hennerich59003142007-10-21 16:54:27 +0800305config MEM_MT48LC32M16A2TG_75
306 bool
Michael Hennerich8cc71172008-10-13 14:45:06 +0800307 depends on (BFIN527_EZKIT || BFIN532_IP0X || BLACKSTAMP || BFIN526_EZBRD)
Michael Hennerich59003142007-10-21 16:54:27 +0800308 default y
309
Bryan Wu2f6f4bc2008-11-18 17:48:21 +0800310source "arch/blackfin/mach-bf518/Kconfig"
Michael Hennerich59003142007-10-21 16:54:27 +0800311source "arch/blackfin/mach-bf527/Kconfig"
Bryan Wu1394f032007-05-06 14:50:22 -0700312source "arch/blackfin/mach-bf533/Kconfig"
313source "arch/blackfin/mach-bf561/Kconfig"
314source "arch/blackfin/mach-bf537/Kconfig"
Michael Hennerichdc26aec2008-11-18 17:48:22 +0800315source "arch/blackfin/mach-bf538/Kconfig"
Roy Huang24a07a12007-07-12 22:41:45 +0800316source "arch/blackfin/mach-bf548/Kconfig"
Bryan Wu1394f032007-05-06 14:50:22 -0700317
318menu "Board customizations"
319
320config CMDLINE_BOOL
321 bool "Default bootloader kernel arguments"
322
323config CMDLINE
324 string "Initial kernel command string"
325 depends on CMDLINE_BOOL
326 default "console=ttyBF0,57600"
327 help
328 If you don't have a boot loader capable of passing a command line string
329 to the kernel, you may specify one here. As a minimum, you should specify
330 the memory size and the root device (e.g., mem=8M, root=/dev/nfs).
331
Mike Frysinger5f004c22008-04-25 02:11:24 +0800332config BOOT_LOAD
333 hex "Kernel load address for booting"
334 default "0x1000"
335 range 0x1000 0x20000000
336 help
337 This option allows you to set the load address of the kernel.
338 This can be useful if you are on a board which has a small amount
339 of memory or you wish to reserve some memory at the beginning of
340 the address space.
341
342 Note that you need to keep this value above 4k (0x1000) as this
343 memory region is used to capture NULL pointer references as well
344 as some core kernel functions.
345
Michael Hennerich8cc71172008-10-13 14:45:06 +0800346config ROM_BASE
347 hex "Kernel ROM Base"
348 default "0x20040000"
349 range 0x20000000 0x20400000 if !(BF54x || BF561)
350 range 0x20000000 0x30000000 if (BF54x || BF561)
351 help
352
Robin Getzf16295e2007-08-03 18:07:17 +0800353comment "Clock/PLL Setup"
Bryan Wu1394f032007-05-06 14:50:22 -0700354
355config CLKIN_HZ
Sonic Zhang2fb6cb42008-04-25 04:39:28 +0800356 int "Frequency of the crystal on the board in Hz"
Bryan Wu1394f032007-05-06 14:50:22 -0700357 default "11059200" if BFIN533_STAMP
358 default "27000000" if BFIN533_EZKIT
Bryan Wu2f6f4bc2008-11-18 17:48:21 +0800359 default "25000000" if (BFIN537_STAMP || BFIN527_EZKIT || H8606_HVSISTEMAS || BLACKSTAMP || BFIN526_EZBRD || BFIN538_EZKIT || BFIN518F-EZBRD)
Bryan Wu1394f032007-05-06 14:50:22 -0700360 default "30000000" if BFIN561_EZKIT
361 default "24576000" if PNAV10
Mike Frysinger5d1617b2008-04-24 05:03:26 +0800362 default "10000000" if BFIN532_IP0X
Bryan Wu1394f032007-05-06 14:50:22 -0700363 help
364 The frequency of CLKIN crystal oscillator on the board in Hz.
Sonic Zhang2fb6cb42008-04-25 04:39:28 +0800365 Warning: This value should match the crystal on the board. Otherwise,
366 peripherals won't work properly.
Bryan Wu1394f032007-05-06 14:50:22 -0700367
Robin Getzf16295e2007-08-03 18:07:17 +0800368config BFIN_KERNEL_CLOCK
369 bool "Re-program Clocks while Kernel boots?"
370 default n
371 help
372 This option decides if kernel clocks are re-programed from the
373 bootloader settings. If the clocks are not set, the SDRAM settings
374 are also not changed, and the Bootloader does 100% of the hardware
375 configuration.
376
377config PLL_BYPASS
Mike Frysingere4e9a7a2007-11-15 20:39:34 +0800378 bool "Bypass PLL"
379 depends on BFIN_KERNEL_CLOCK
380 default n
Robin Getzf16295e2007-08-03 18:07:17 +0800381
382config CLKIN_HALF
383 bool "Half Clock In"
384 depends on BFIN_KERNEL_CLOCK && (! PLL_BYPASS)
385 default n
386 help
387 If this is set the clock will be divided by 2, before it goes to the PLL.
388
389config VCO_MULT
390 int "VCO Multiplier"
391 depends on BFIN_KERNEL_CLOCK && (! PLL_BYPASS)
392 range 1 64
393 default "22" if BFIN533_EZKIT
394 default "45" if BFIN533_STAMP
Michael Hennerichdc26aec2008-11-18 17:48:22 +0800395 default "20" if (BFIN537_STAMP || BFIN527_EZKIT || BFIN548_EZKIT || BFIN548_BLUETECHNIX_CM || BFIN538_EZKIT)
Robin Getzf16295e2007-08-03 18:07:17 +0800396 default "22" if BFIN533_BLUETECHNIX_CM
Michael Hennerich9db144f2008-07-19 17:16:07 +0800397 default "20" if (BFIN537_BLUETECHNIX_CM || BFIN527_BLUETECHNIX_CM || BFIN561_BLUETECHNIX_CM)
Robin Getzf16295e2007-08-03 18:07:17 +0800398 default "20" if BFIN561_EZKIT
Bryan Wu2f6f4bc2008-11-18 17:48:21 +0800399 default "16" if (H8606_HVSISTEMAS || BLACKSTAMP || BFIN526_EZBRD || BFIN518F_EZBRD)
Robin Getzf16295e2007-08-03 18:07:17 +0800400 help
401 This controls the frequency of the on-chip PLL. This can be between 1 and 64.
402 PLL Frequency = (Crystal Frequency) * (this setting)
403
404choice
405 prompt "Core Clock Divider"
406 depends on BFIN_KERNEL_CLOCK
407 default CCLK_DIV_1
408 help
409 This sets the frequency of the core. It can be 1, 2, 4 or 8
410 Core Frequency = (PLL frequency) / (this setting)
411
412config CCLK_DIV_1
413 bool "1"
414
415config CCLK_DIV_2
416 bool "2"
417
418config CCLK_DIV_4
419 bool "4"
420
421config CCLK_DIV_8
422 bool "8"
423endchoice
424
425config SCLK_DIV
426 int "System Clock Divider"
427 depends on BFIN_KERNEL_CLOCK
428 range 1 15
Mike Frysinger5f004c22008-04-25 02:11:24 +0800429 default 5
Robin Getzf16295e2007-08-03 18:07:17 +0800430 help
431 This sets the frequency of the system clock (including SDRAM or DDR).
432 This can be between 1 and 15
433 System Clock = (PLL frequency) / (this setting)
434
Mike Frysinger5f004c22008-04-25 02:11:24 +0800435choice
436 prompt "DDR SDRAM Chip Type"
437 depends on BFIN_KERNEL_CLOCK
438 depends on BF54x
439 default MEM_MT46V32M16_5B
440
441config MEM_MT46V32M16_6T
442 bool "MT46V32M16_6T"
443
444config MEM_MT46V32M16_5B
445 bool "MT46V32M16_5B"
446endchoice
447
Mike Frysinger7eb2c232008-10-08 17:39:02 +0800448config MAX_MEM_SIZE
449 int "Max SDRAM Memory Size in MBytes"
450 depends on !MPU
451 default 512
452 help
453 This is the max memory size that the kernel will create CPLB
454 tables for. Your system will not be able to handle any more.
455
Robin Getzf16295e2007-08-03 18:07:17 +0800456#
457# Max & Min Speeds for various Chips
458#
459config MAX_VCO_HZ
460 int
Bryan Wu2f6f4bc2008-11-18 17:48:21 +0800461 default 400000000 if BF512
462 default 400000000 if BF514
463 default 400000000 if BF516
464 default 400000000 if BF518
Robin Getzf16295e2007-08-03 18:07:17 +0800465 default 600000000 if BF522
Mike Frysinger1545a112007-12-24 16:54:48 +0800466 default 400000000 if BF523
467 default 400000000 if BF524
Robin Getzf16295e2007-08-03 18:07:17 +0800468 default 600000000 if BF525
Mike Frysinger1545a112007-12-24 16:54:48 +0800469 default 400000000 if BF526
Robin Getzf16295e2007-08-03 18:07:17 +0800470 default 600000000 if BF527
471 default 400000000 if BF531
472 default 400000000 if BF532
473 default 750000000 if BF533
474 default 500000000 if BF534
475 default 400000000 if BF536
476 default 600000000 if BF537
Robin Getzf72eecb2007-11-21 16:29:20 +0800477 default 533333333 if BF538
478 default 533333333 if BF539
Robin Getzf16295e2007-08-03 18:07:17 +0800479 default 600000000 if BF542
Robin Getzf72eecb2007-11-21 16:29:20 +0800480 default 533333333 if BF544
Mike Frysinger1545a112007-12-24 16:54:48 +0800481 default 600000000 if BF547
482 default 600000000 if BF548
Robin Getzf72eecb2007-11-21 16:29:20 +0800483 default 533333333 if BF549
Robin Getzf16295e2007-08-03 18:07:17 +0800484 default 600000000 if BF561
485
486config MIN_VCO_HZ
487 int
488 default 50000000
489
490config MAX_SCLK_HZ
491 int
Robin Getzf72eecb2007-11-21 16:29:20 +0800492 default 133333333
Robin Getzf16295e2007-08-03 18:07:17 +0800493
494config MIN_SCLK_HZ
495 int
496 default 27000000
497
498comment "Kernel Timer/Scheduler"
499
500source kernel/Kconfig.hz
501
Vitja Makarov8b5f79f2008-02-29 12:24:23 +0800502config GENERIC_TIME
503 bool "Generic time"
504 default y
505
506config GENERIC_CLOCKEVENTS
507 bool "Generic clock events"
508 depends on GENERIC_TIME
509 default y
510
511config CYCLES_CLOCKSOURCE
512 bool "Use 'CYCLES' as a clocksource (EXPERIMENTAL)"
513 depends on EXPERIMENTAL
514 depends on GENERIC_CLOCKEVENTS
515 depends on !BFIN_SCRATCH_REG_CYCLES
516 default n
517 help
518 If you say Y here, you will enable support for using the 'cycles'
519 registers as a clock source. Doing so means you will be unable to
520 safely write to the 'cycles' register during runtime. You will
521 still be able to read it (such as for performance monitoring), but
522 writing the registers will most likely crash the kernel.
523
524source kernel/time/Kconfig
525
Mike Frysinger5f004c22008-04-25 02:11:24 +0800526comment "Misc"
Sonic Zhang971d5bc2008-01-27 16:32:31 +0800527
Mike Frysingerf0b5d122007-08-05 17:03:59 +0800528choice
529 prompt "Blackfin Exception Scratch Register"
530 default BFIN_SCRATCH_REG_RETN
531 help
532 Select the resource to reserve for the Exception handler:
533 - RETN: Non-Maskable Interrupt (NMI)
534 - RETE: Exception Return (JTAG/ICE)
535 - CYCLES: Performance counter
536
537 If you are unsure, please select "RETN".
538
539config BFIN_SCRATCH_REG_RETN
540 bool "RETN"
541 help
542 Use the RETN register in the Blackfin exception handler
543 as a stack scratch register. This means you cannot
544 safely use NMI on the Blackfin while running Linux, but
545 you can debug the system with a JTAG ICE and use the
546 CYCLES performance registers.
547
548 If you are unsure, please select "RETN".
549
550config BFIN_SCRATCH_REG_RETE
551 bool "RETE"
552 help
553 Use the RETE register in the Blackfin exception handler
554 as a stack scratch register. This means you cannot
555 safely use a JTAG ICE while debugging a Blackfin board,
556 but you can safely use the CYCLES performance registers
557 and the NMI.
558
559 If you are unsure, please select "RETN".
560
561config BFIN_SCRATCH_REG_CYCLES
562 bool "CYCLES"
563 help
564 Use the CYCLES register in the Blackfin exception handler
565 as a stack scratch register. This means you cannot
566 safely use the CYCLES performance registers on a Blackfin
567 board at anytime, but you can debug the system with a JTAG
568 ICE and use the NMI.
569
570 If you are unsure, please select "RETN".
571
572endchoice
573
Bryan Wu1394f032007-05-06 14:50:22 -0700574endmenu
575
576
577menu "Blackfin Kernel Optimizations"
578
Bryan Wu1394f032007-05-06 14:50:22 -0700579comment "Memory Optimizations"
580
581config I_ENTRY_L1
582 bool "Locate interrupt entry code in L1 Memory"
583 default y
584 help
Matt LaPlante01dd2fb2007-10-20 01:34:40 +0200585 If enabled, interrupt entry code (STORE/RESTORE CONTEXT) is linked
586 into L1 instruction memory. (less latency)
Bryan Wu1394f032007-05-06 14:50:22 -0700587
588config EXCPT_IRQ_SYSC_L1
Matt LaPlante01dd2fb2007-10-20 01:34:40 +0200589 bool "Locate entire ASM lowlevel exception / interrupt - Syscall and CPLB handler code in L1 Memory"
Bryan Wu1394f032007-05-06 14:50:22 -0700590 default y
591 help
Matt LaPlante01dd2fb2007-10-20 01:34:40 +0200592 If enabled, the entire ASM lowlevel exception and interrupt entry code
Michael Hennerichcfefe3c2008-02-09 04:12:37 +0800593 (STORE/RESTORE CONTEXT) is linked into L1 instruction memory.
Matt LaPlante01dd2fb2007-10-20 01:34:40 +0200594 (less latency)
Bryan Wu1394f032007-05-06 14:50:22 -0700595
596config DO_IRQ_L1
597 bool "Locate frequently called do_irq dispatcher function in L1 Memory"
598 default y
599 help
Matt LaPlante01dd2fb2007-10-20 01:34:40 +0200600 If enabled, the frequently called do_irq dispatcher function is linked
601 into L1 instruction memory. (less latency)
Bryan Wu1394f032007-05-06 14:50:22 -0700602
603config CORE_TIMER_IRQ_L1
604 bool "Locate frequently called timer_interrupt() function in L1 Memory"
605 default y
606 help
Matt LaPlante01dd2fb2007-10-20 01:34:40 +0200607 If enabled, the frequently called timer_interrupt() function is linked
608 into L1 instruction memory. (less latency)
Bryan Wu1394f032007-05-06 14:50:22 -0700609
610config IDLE_L1
611 bool "Locate frequently idle function in L1 Memory"
612 default y
613 help
Matt LaPlante01dd2fb2007-10-20 01:34:40 +0200614 If enabled, the frequently called idle function is linked
615 into L1 instruction memory. (less latency)
Bryan Wu1394f032007-05-06 14:50:22 -0700616
617config SCHEDULE_L1
618 bool "Locate kernel schedule function in L1 Memory"
619 default y
620 help
Matt LaPlante01dd2fb2007-10-20 01:34:40 +0200621 If enabled, the frequently called kernel schedule is linked
622 into L1 instruction memory. (less latency)
Bryan Wu1394f032007-05-06 14:50:22 -0700623
624config ARITHMETIC_OPS_L1
625 bool "Locate kernel owned arithmetic functions in L1 Memory"
626 default y
627 help
Matt LaPlante01dd2fb2007-10-20 01:34:40 +0200628 If enabled, arithmetic functions are linked
629 into L1 instruction memory. (less latency)
Bryan Wu1394f032007-05-06 14:50:22 -0700630
631config ACCESS_OK_L1
632 bool "Locate access_ok function in L1 Memory"
633 default y
634 help
Matt LaPlante01dd2fb2007-10-20 01:34:40 +0200635 If enabled, the access_ok function is linked
636 into L1 instruction memory. (less latency)
Bryan Wu1394f032007-05-06 14:50:22 -0700637
638config MEMSET_L1
639 bool "Locate memset function in L1 Memory"
640 default y
641 help
Matt LaPlante01dd2fb2007-10-20 01:34:40 +0200642 If enabled, the memset function is linked
643 into L1 instruction memory. (less latency)
Bryan Wu1394f032007-05-06 14:50:22 -0700644
645config MEMCPY_L1
646 bool "Locate memcpy function in L1 Memory"
647 default y
648 help
Matt LaPlante01dd2fb2007-10-20 01:34:40 +0200649 If enabled, the memcpy function is linked
650 into L1 instruction memory. (less latency)
Bryan Wu1394f032007-05-06 14:50:22 -0700651
652config SYS_BFIN_SPINLOCK_L1
653 bool "Locate sys_bfin_spinlock function in L1 Memory"
654 default y
655 help
Matt LaPlante01dd2fb2007-10-20 01:34:40 +0200656 If enabled, sys_bfin_spinlock function is linked
657 into L1 instruction memory. (less latency)
Bryan Wu1394f032007-05-06 14:50:22 -0700658
659config IP_CHECKSUM_L1
660 bool "Locate IP Checksum function in L1 Memory"
661 default n
662 help
Matt LaPlante01dd2fb2007-10-20 01:34:40 +0200663 If enabled, the IP Checksum function is linked
664 into L1 instruction memory. (less latency)
Bryan Wu1394f032007-05-06 14:50:22 -0700665
666config CACHELINE_ALIGNED_L1
667 bool "Locate cacheline_aligned data to L1 Data Memory"
Michael Hennerich157cc5a2007-07-12 16:20:21 +0800668 default y if !BF54x
669 default n if BF54x
Bryan Wu1394f032007-05-06 14:50:22 -0700670 depends on !BF531
671 help
Matt LaPlante01dd2fb2007-10-20 01:34:40 +0200672 If enabled, cacheline_anligned data is linked
673 into L1 data memory. (less latency)
Bryan Wu1394f032007-05-06 14:50:22 -0700674
675config SYSCALL_TAB_L1
676 bool "Locate Syscall Table L1 Data Memory"
677 default n
678 depends on !BF531
679 help
Matt LaPlante01dd2fb2007-10-20 01:34:40 +0200680 If enabled, the Syscall LUT is linked
681 into L1 data memory. (less latency)
Bryan Wu1394f032007-05-06 14:50:22 -0700682
683config CPLB_SWITCH_TAB_L1
684 bool "Locate CPLB Switch Tables L1 Data Memory"
685 default n
686 depends on !BF531
687 help
Matt LaPlante01dd2fb2007-10-20 01:34:40 +0200688 If enabled, the CPLB Switch Tables are linked
689 into L1 data memory. (less latency)
Bryan Wu1394f032007-05-06 14:50:22 -0700690
Graf Yangca87b7a2008-10-08 17:30:01 +0800691config APP_STACK_L1
692 bool "Support locating application stack in L1 Scratch Memory"
693 default y
694 help
695 If enabled the application stack can be located in L1
696 scratch memory (less latency).
697
698 Currently only works with FLAT binaries.
699
Mike Frysinger6ad2b842008-10-28 11:03:09 +0800700config EXCEPTION_L1_SCRATCH
701 bool "Locate exception stack in L1 Scratch Memory"
702 default n
703 depends on !APP_STACK_L1 && !SYSCALL_TAB_L1
704 help
705 Whenever an exception occurs, use the L1 Scratch memory for
706 stack storage. You cannot place the stacks of FLAT binaries
707 in L1 when using this option.
708
709 If you don't use L1 Scratch, then you should say Y here.
710
Robin Getz251383c2008-08-14 15:12:55 +0800711comment "Speed Optimizations"
712config BFIN_INS_LOWOVERHEAD
713 bool "ins[bwl] low overhead, higher interrupt latency"
714 default y
715 help
716 Reads on the Blackfin are speculative. In Blackfin terms, this means
717 they can be interrupted at any time (even after they have been issued
718 on to the external bus), and re-issued after the interrupt occurs.
719 For memory - this is not a big deal, since memory does not change if
720 it sees a read.
721
722 If a FIFO is sitting on the end of the read, it will see two reads,
723 when the core only sees one since the FIFO receives both the read
724 which is cancelled (and not delivered to the core) and the one which
725 is re-issued (which is delivered to the core).
726
727 To solve this, interrupts are turned off before reads occur to
728 I/O space. This option controls which the overhead/latency of
729 controlling interrupts during this time
730 "n" turns interrupts off every read
731 (higher overhead, but lower interrupt latency)
732 "y" turns interrupts off every loop
733 (low overhead, but longer interrupt latency)
734
735 default behavior is to leave this set to on (type "Y"). If you are experiencing
736 interrupt latency issues, it is safe and OK to turn this off.
737
Bryan Wu1394f032007-05-06 14:50:22 -0700738endmenu
739
740
741choice
742 prompt "Kernel executes from"
743 help
744 Choose the memory type that the kernel will be running in.
745
746config RAMKERNEL
747 bool "RAM"
748 help
749 The kernel will be resident in RAM when running.
750
751config ROMKERNEL
752 bool "ROM"
753 help
754 The kernel will be resident in FLASH/ROM when running.
755
756endchoice
757
758source "mm/Kconfig"
759
Mike Frysinger780431e2007-10-21 23:37:54 +0800760config BFIN_GPTIMERS
761 tristate "Enable Blackfin General Purpose Timers API"
762 default n
763 help
764 Enable support for the General Purpose Timers API. If you
765 are unsure, say N.
766
767 To compile this driver as a module, choose M here: the module
768 will be called gptimers.ko.
769
Bryan Wu1394f032007-05-06 14:50:22 -0700770config BFIN_DMA_5XX
771 bool "Enable DMA Support"
Bryan Wu1394f032007-05-06 14:50:22 -0700772 default y
773 help
Mike Frysingerd292b002008-10-28 11:15:36 +0800774 DMA driver for Blackfin parts.
Bryan Wu1394f032007-05-06 14:50:22 -0700775
776choice
Mike Frysingerd292b002008-10-28 11:15:36 +0800777 prompt "Uncached DMA region"
Bryan Wu1394f032007-05-06 14:50:22 -0700778 default DMA_UNCACHED_1M
Adrian Bunk247537b2007-09-26 20:02:52 +0200779 depends on BFIN_DMA_5XX
Cliff Cai86ad7932008-05-17 16:36:52 +0800780config DMA_UNCACHED_4M
781 bool "Enable 4M DMA region"
Bryan Wu1394f032007-05-06 14:50:22 -0700782config DMA_UNCACHED_2M
783 bool "Enable 2M DMA region"
784config DMA_UNCACHED_1M
785 bool "Enable 1M DMA region"
786config DMA_UNCACHED_NONE
787 bool "Disable DMA region"
788endchoice
789
790
791comment "Cache Support"
Robin Getz3bebca22007-10-10 23:55:26 +0800792config BFIN_ICACHE
Bryan Wu1394f032007-05-06 14:50:22 -0700793 bool "Enable ICACHE"
Robin Getz3bebca22007-10-10 23:55:26 +0800794config BFIN_DCACHE
Bryan Wu1394f032007-05-06 14:50:22 -0700795 bool "Enable DCACHE"
Robin Getz3bebca22007-10-10 23:55:26 +0800796config BFIN_DCACHE_BANKA
Bryan Wu1394f032007-05-06 14:50:22 -0700797 bool "Enable only 16k BankA DCACHE - BankB is SRAM"
Robin Getz3bebca22007-10-10 23:55:26 +0800798 depends on BFIN_DCACHE && !BF531
Bryan Wu1394f032007-05-06 14:50:22 -0700799 default n
Robin Getz3bebca22007-10-10 23:55:26 +0800800config BFIN_ICACHE_LOCK
801 bool "Enable Instruction Cache Locking"
Bryan Wu1394f032007-05-06 14:50:22 -0700802
803choice
804 prompt "Policy"
Robin Getz3bebca22007-10-10 23:55:26 +0800805 depends on BFIN_DCACHE
806 default BFIN_WB
807config BFIN_WB
Bryan Wu1394f032007-05-06 14:50:22 -0700808 bool "Write back"
809 help
810 Write Back Policy:
811 Cached data will be written back to SDRAM only when needed.
812 This can give a nice increase in performance, but beware of
813 broken drivers that do not properly invalidate/flush their
814 cache.
815
816 Write Through Policy:
817 Cached data will always be written back to SDRAM when the
818 cache is updated. This is a completely safe setting, but
819 performance is worse than Write Back.
820
821 If you are unsure of the options and you want to be safe,
822 then go with Write Through.
823
Robin Getz3bebca22007-10-10 23:55:26 +0800824config BFIN_WT
Bryan Wu1394f032007-05-06 14:50:22 -0700825 bool "Write through"
826 help
827 Write Back Policy:
828 Cached data will be written back to SDRAM only when needed.
829 This can give a nice increase in performance, but beware of
830 broken drivers that do not properly invalidate/flush their
831 cache.
832
833 Write Through Policy:
834 Cached data will always be written back to SDRAM when the
835 cache is updated. This is a completely safe setting, but
836 performance is worse than Write Back.
837
838 If you are unsure of the options and you want to be safe,
839 then go with Write Through.
840
841endchoice
842
Sonic Zhangf099f392008-10-09 14:11:57 +0800843config BFIN_L2_CACHEABLE
844 bool "Cache L2 SRAM"
845 depends on (BFIN_DCACHE || BFIN_ICACHE) && (BF54x || BF561)
846 default n
847 help
848 Select to make L2 SRAM cacheable in L1 data and instruction cache.
849
Bernd Schmidtb97b8a92008-01-27 18:39:16 +0800850config MPU
851 bool "Enable the memory protection unit (EXPERIMENTAL)"
852 default n
853 help
854 Use the processor's MPU to protect applications from accessing
855 memory they do not own. This comes at a performance penalty
856 and is recommended only for debugging.
857
Bryan Wu1394f032007-05-06 14:50:22 -0700858comment "Asynchonous Memory Configuration"
859
Mike Frysingerddf416b2007-10-10 18:06:47 +0800860menu "EBIU_AMGCTL Global Control"
Bryan Wu1394f032007-05-06 14:50:22 -0700861config C_AMCKEN
862 bool "Enable CLKOUT"
863 default y
864
865config C_CDPRIO
866 bool "DMA has priority over core for ext. accesses"
867 default n
868
869config C_B0PEN
870 depends on BF561
871 bool "Bank 0 16 bit packing enable"
872 default y
873
874config C_B1PEN
875 depends on BF561
876 bool "Bank 1 16 bit packing enable"
877 default y
878
879config C_B2PEN
880 depends on BF561
881 bool "Bank 2 16 bit packing enable"
882 default y
883
884config C_B3PEN
885 depends on BF561
886 bool "Bank 3 16 bit packing enable"
887 default n
888
889choice
890 prompt"Enable Asynchonous Memory Banks"
891 default C_AMBEN_ALL
892
893config C_AMBEN
894 bool "Disable All Banks"
895
896config C_AMBEN_B0
897 bool "Enable Bank 0"
898
899config C_AMBEN_B0_B1
900 bool "Enable Bank 0 & 1"
901
902config C_AMBEN_B0_B1_B2
903 bool "Enable Bank 0 & 1 & 2"
904
905config C_AMBEN_ALL
906 bool "Enable All Banks"
907endchoice
908endmenu
909
910menu "EBIU_AMBCTL Control"
911config BANK_0
912 hex "Bank 0"
913 default 0x7BB0
914
915config BANK_1
916 hex "Bank 1"
917 default 0x7BB0
Michael Hennerich197fba52008-05-07 17:03:27 +0800918 default 0x5558 if BF54x
Bryan Wu1394f032007-05-06 14:50:22 -0700919
920config BANK_2
921 hex "Bank 2"
922 default 0x7BB0
923
924config BANK_3
925 hex "Bank 3"
926 default 0x99B3
927endmenu
928
Sonic Zhange40540b2007-11-21 23:49:52 +0800929config EBIU_MBSCTLVAL
930 hex "EBIU Bank Select Control Register"
931 depends on BF54x
932 default 0
933
934config EBIU_MODEVAL
935 hex "Flash Memory Mode Control Register"
936 depends on BF54x
937 default 1
938
939config EBIU_FCTLVAL
940 hex "Flash Memory Bank Control Register"
941 depends on BF54x
942 default 6
Bryan Wu1394f032007-05-06 14:50:22 -0700943endmenu
944
945#############################################################################
946menu "Bus options (PCI, PCMCIA, EISA, MCA, ISA)"
947
948config PCI
949 bool "PCI support"
Adrian Bunka95ca3b2008-08-27 10:55:05 +0800950 depends on BROKEN
Bryan Wu1394f032007-05-06 14:50:22 -0700951 help
952 Support for PCI bus.
953
954source "drivers/pci/Kconfig"
955
956config HOTPLUG
957 bool "Support for hot-pluggable device"
958 help
959 Say Y here if you want to plug devices into your computer while
960 the system is running, and be able to use them quickly. In many
961 cases, the devices can likewise be unplugged at any time too.
962
963 One well known example of this is PCMCIA- or PC-cards, credit-card
964 size devices such as network cards, modems or hard drives which are
965 plugged into slots found on all modern laptop computers. Another
966 example, used on modern desktops as well as laptops, is USB.
967
Johannes Berga81792f2008-07-08 19:00:25 +0200968 Enable HOTPLUG and build a modular kernel. Get agent software
969 (from <http://linux-hotplug.sourceforge.net/>) and install it.
Bryan Wu1394f032007-05-06 14:50:22 -0700970 Then your kernel will automatically call out to a user mode "policy
971 agent" (/sbin/hotplug) to load modules and set up software needed
972 to use devices as you hotplug them.
973
974source "drivers/pcmcia/Kconfig"
975
976source "drivers/pci/hotplug/Kconfig"
977
978endmenu
979
980menu "Executable file formats"
981
982source "fs/Kconfig.binfmt"
983
984endmenu
985
986menu "Power management options"
987source "kernel/power/Kconfig"
988
Johannes Bergf4cb5702007-12-08 02:14:00 +0100989config ARCH_SUSPEND_POSSIBLE
990 def_bool y
991 depends on !SMP
992
Bryan Wu1394f032007-05-06 14:50:22 -0700993choice
Michael Hennerich1efc80b2008-07-19 16:57:32 +0800994 prompt "Standby Power Saving Mode"
Bryan Wu1394f032007-05-06 14:50:22 -0700995 depends on PM
Michael Hennerichcfefe3c2008-02-09 04:12:37 +0800996 default PM_BFIN_SLEEP_DEEPER
997config PM_BFIN_SLEEP_DEEPER
998 bool "Sleep Deeper"
Bryan Wu1394f032007-05-06 14:50:22 -0700999 help
Michael Hennerichcfefe3c2008-02-09 04:12:37 +08001000 Sleep "Deeper" Mode (High Power Savings) - This mode reduces dynamic
1001 power dissipation by disabling the clock to the processor core (CCLK).
1002 Furthermore, Standby sets the internal power supply voltage (VDDINT)
1003 to 0.85 V to provide the greatest power savings, while preserving the
1004 processor state.
1005 The PLL and system clock (SCLK) continue to operate at a very low
1006 frequency of about 3.3 MHz. To preserve data integrity in the SDRAM,
1007 the SDRAM is put into Self Refresh Mode. Typically an external event
1008 such as GPIO interrupt or RTC activity wakes up the processor.
1009 Various Peripherals such as UART, SPORT, PPI may not function as
1010 normal during Sleep Deeper, due to the reduced SCLK frequency.
1011 When in the sleep mode, system DMA access to L1 memory is not supported.
Bryan Wu1394f032007-05-06 14:50:22 -07001012
Michael Hennerich1efc80b2008-07-19 16:57:32 +08001013 If unsure, select "Sleep Deeper".
1014
Michael Hennerichcfefe3c2008-02-09 04:12:37 +08001015config PM_BFIN_SLEEP
1016 bool "Sleep"
1017 help
1018 Sleep Mode (High Power Savings) - The sleep mode reduces power
1019 dissipation by disabling the clock to the processor core (CCLK).
1020 The PLL and system clock (SCLK), however, continue to operate in
1021 this mode. Typically an external event or RTC activity will wake
Michael Hennerich1efc80b2008-07-19 16:57:32 +08001022 up the processor. When in the sleep mode, system DMA access to L1
1023 memory is not supported.
1024
1025 If unsure, select "Sleep Deeper".
Bryan Wu1394f032007-05-06 14:50:22 -07001026endchoice
1027
Michael Hennerichcfefe3c2008-02-09 04:12:37 +08001028config PM_WAKEUP_BY_GPIO
Michael Hennerich1efc80b2008-07-19 16:57:32 +08001029 bool "Allow Wakeup from Standby by GPIO"
Bryan Wu1394f032007-05-06 14:50:22 -07001030
1031config PM_WAKEUP_GPIO_NUMBER
Michael Hennerich1efc80b2008-07-19 16:57:32 +08001032 int "GPIO number"
Bryan Wu1394f032007-05-06 14:50:22 -07001033 range 0 47
1034 depends on PM_WAKEUP_BY_GPIO
1035 default 2 if BFIN537_STAMP
1036
1037choice
1038 prompt "GPIO Polarity"
1039 depends on PM_WAKEUP_BY_GPIO
1040 default PM_WAKEUP_GPIO_POLAR_H
1041config PM_WAKEUP_GPIO_POLAR_H
1042 bool "Active High"
1043config PM_WAKEUP_GPIO_POLAR_L
1044 bool "Active Low"
1045config PM_WAKEUP_GPIO_POLAR_EDGE_F
1046 bool "Falling EDGE"
1047config PM_WAKEUP_GPIO_POLAR_EDGE_R
1048 bool "Rising EDGE"
1049config PM_WAKEUP_GPIO_POLAR_EDGE_B
1050 bool "Both EDGE"
1051endchoice
1052
Michael Hennerich1efc80b2008-07-19 16:57:32 +08001053comment "Possible Suspend Mem / Hibernate Wake-Up Sources"
1054 depends on PM
1055
Michael Hennerich1efc80b2008-07-19 16:57:32 +08001056config PM_BFIN_WAKE_PH6
1057 bool "Allow Wake-Up from on-chip PHY or PH6 GP"
Bryan Wu2f6f4bc2008-11-18 17:48:21 +08001058 depends on PM && (BF51x || BF52x || BF534 || BF536 || BF537)
Michael Hennerich1efc80b2008-07-19 16:57:32 +08001059 default n
1060 help
1061 Enable PHY and PH6 GP Wake-Up (Voltage Regulator Power-Up)
1062
Michael Hennerich1efc80b2008-07-19 16:57:32 +08001063config PM_BFIN_WAKE_GP
1064 bool "Allow Wake-Up from GPIOs"
1065 depends on PM && BF54x
1066 default n
1067 help
1068 Enable General-Purpose Wake-Up (Voltage Regulator Power-Up)
Bryan Wu1394f032007-05-06 14:50:22 -07001069endmenu
1070
Bryan Wu1394f032007-05-06 14:50:22 -07001071menu "CPU Frequency scaling"
1072
1073source "drivers/cpufreq/Kconfig"
1074
Michael Hennerich14b03202008-05-07 11:41:26 +08001075config CPU_VOLTAGE
1076 bool "CPU Voltage scaling"
1077 depends on EXPERIMENTAL
1078 depends on CPU_FREQ
1079 default n
1080 help
1081 Say Y here if you want CPU voltage scaling according to the CPU frequency.
1082 This option violates the PLL BYPASS recommendation in the Blackfin Processor
1083 manuals. There is a theoretical risk that during VDDINT transitions
1084 the PLL may unlock.
1085
Bryan Wu1394f032007-05-06 14:50:22 -07001086endmenu
1087
Bryan Wu1394f032007-05-06 14:50:22 -07001088source "net/Kconfig"
1089
1090source "drivers/Kconfig"
1091
1092source "fs/Kconfig"
1093
Mike Frysinger74ce8322007-11-21 23:50:49 +08001094source "arch/blackfin/Kconfig.debug"
Bryan Wu1394f032007-05-06 14:50:22 -07001095
1096source "security/Kconfig"
1097
1098source "crypto/Kconfig"
1099
1100source "lib/Kconfig"