Ben Skeggs | 4b223ee | 2010-08-03 10:00:56 +1000 | [diff] [blame] | 1 | /* |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 2 | * Copyright 2012 Red Hat Inc. |
Ben Skeggs | 4b223ee | 2010-08-03 10:00:56 +1000 | [diff] [blame] | 3 | * |
| 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 5 | * copy of this software and associated documentation files (the "Software"), |
| 6 | * to deal in the Software without restriction, including without limitation |
| 7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| 8 | * and/or sell copies of the Software, and to permit persons to whom the |
| 9 | * Software is furnished to do so, subject to the following conditions: |
| 10 | * |
| 11 | * The above copyright notice and this permission notice shall be included in |
| 12 | * all copies or substantial portions of the Software. |
| 13 | * |
| 14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
| 18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
| 19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
| 20 | * OTHER DEALINGS IN THE SOFTWARE. |
| 21 | * |
| 22 | * Authors: Ben Skeggs |
| 23 | */ |
| 24 | |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 25 | #include <core/client.h> |
| 26 | #include <core/handle.h> |
| 27 | #include <core/namedb.h> |
| 28 | #include <core/gpuobj.h> |
| 29 | #include <core/engctx.h> |
Ben Skeggs | 9bd2ddb | 2013-01-31 13:51:20 +1000 | [diff] [blame] | 30 | #include <core/event.h> |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 31 | #include <core/class.h> |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 32 | #include <core/enum.h> |
Ben Skeggs | 4b223ee | 2010-08-03 10:00:56 +1000 | [diff] [blame] | 33 | |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 34 | #include <subdev/timer.h> |
| 35 | #include <subdev/bar.h> |
Ben Skeggs | 5222555 | 2013-12-23 01:51:16 +1000 | [diff] [blame] | 36 | #include <subdev/fb.h> |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 37 | #include <subdev/vm.h> |
| 38 | |
| 39 | #include <engine/dmaobj.h> |
Ben Skeggs | 02a841d | 2012-07-04 23:44:54 +1000 | [diff] [blame] | 40 | #include <engine/fifo.h> |
Ben Skeggs | b2b0993 | 2010-11-24 10:47:15 +1000 | [diff] [blame] | 41 | |
| 42 | struct nvc0_fifo_priv { |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 43 | struct nouveau_fifo base; |
Ben Skeggs | a07d0e7 | 2014-02-22 00:28:47 +1000 | [diff] [blame] | 44 | struct { |
| 45 | struct nouveau_gpuobj *mem[2]; |
| 46 | int active; |
| 47 | wait_queue_head_t wait; |
| 48 | } runlist; |
Ben Skeggs | 9da226f | 2012-07-13 16:54:45 +1000 | [diff] [blame] | 49 | struct { |
| 50 | struct nouveau_gpuobj *mem; |
| 51 | struct nouveau_vma bar; |
| 52 | } user; |
Ben Skeggs | ec9c088 | 2010-12-31 12:10:49 +1000 | [diff] [blame] | 53 | int spoon_nr; |
Ben Skeggs | b2b0993 | 2010-11-24 10:47:15 +1000 | [diff] [blame] | 54 | }; |
| 55 | |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 56 | struct nvc0_fifo_base { |
| 57 | struct nouveau_fifo_base base; |
| 58 | struct nouveau_gpuobj *pgd; |
| 59 | struct nouveau_vm *vm; |
| 60 | }; |
| 61 | |
Ben Skeggs | b2b0993 | 2010-11-24 10:47:15 +1000 | [diff] [blame] | 62 | struct nvc0_fifo_chan { |
Ben Skeggs | c420b2d | 2012-05-01 20:48:08 +1000 | [diff] [blame] | 63 | struct nouveau_fifo_chan base; |
Ben Skeggs | e2822b7 | 2014-02-22 00:52:45 +1000 | [diff] [blame] | 64 | enum { |
| 65 | STOPPED, |
| 66 | RUNNING, |
| 67 | KILLED |
| 68 | } state; |
Ben Skeggs | b2b0993 | 2010-11-24 10:47:15 +1000 | [diff] [blame] | 69 | }; |
| 70 | |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 71 | /******************************************************************************* |
| 72 | * FIFO channel objects |
| 73 | ******************************************************************************/ |
| 74 | |
Ben Skeggs | b2b0993 | 2010-11-24 10:47:15 +1000 | [diff] [blame] | 75 | static void |
Ben Skeggs | 0357466 | 2014-01-28 11:47:46 +1000 | [diff] [blame] | 76 | nvc0_fifo_runlist_update(struct nvc0_fifo_priv *priv) |
Ben Skeggs | b2b0993 | 2010-11-24 10:47:15 +1000 | [diff] [blame] | 77 | { |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 78 | struct nouveau_bar *bar = nouveau_bar(priv); |
Ben Skeggs | b2b0993 | 2010-11-24 10:47:15 +1000 | [diff] [blame] | 79 | struct nouveau_gpuobj *cur; |
| 80 | int i, p; |
| 81 | |
Ben Skeggs | fadb171 | 2013-05-13 10:02:11 +1000 | [diff] [blame] | 82 | mutex_lock(&nv_subdev(priv)->mutex); |
Ben Skeggs | a07d0e7 | 2014-02-22 00:28:47 +1000 | [diff] [blame] | 83 | cur = priv->runlist.mem[priv->runlist.active]; |
| 84 | priv->runlist.active = !priv->runlist.active; |
Ben Skeggs | b2b0993 | 2010-11-24 10:47:15 +1000 | [diff] [blame] | 85 | |
| 86 | for (i = 0, p = 0; i < 128; i++) { |
Ben Skeggs | e2822b7 | 2014-02-22 00:52:45 +1000 | [diff] [blame] | 87 | struct nvc0_fifo_chan *chan = (void *)priv->base.channel[i]; |
| 88 | if (chan && chan->state == RUNNING) { |
| 89 | nv_wo32(cur, p + 0, i); |
| 90 | nv_wo32(cur, p + 4, 0x00000004); |
| 91 | p += 8; |
| 92 | } |
Ben Skeggs | b2b0993 | 2010-11-24 10:47:15 +1000 | [diff] [blame] | 93 | } |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 94 | bar->flush(bar); |
Ben Skeggs | b2b0993 | 2010-11-24 10:47:15 +1000 | [diff] [blame] | 95 | |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 96 | nv_wr32(priv, 0x002270, cur->addr >> 12); |
| 97 | nv_wr32(priv, 0x002274, 0x01f00000 | (p >> 3)); |
Ben Skeggs | e2822b7 | 2014-02-22 00:52:45 +1000 | [diff] [blame] | 98 | |
Ben Skeggs | 3cf6290 | 2014-02-22 01:05:01 +1000 | [diff] [blame^] | 99 | if (wait_event_timeout(priv->runlist.wait, |
| 100 | !(nv_rd32(priv, 0x00227c) & 0x00100000), |
| 101 | msecs_to_jiffies(2000)) == 0) |
| 102 | nv_error(priv, "runlist update timeout\n"); |
Ben Skeggs | fadb171 | 2013-05-13 10:02:11 +1000 | [diff] [blame] | 103 | mutex_unlock(&nv_subdev(priv)->mutex); |
Ben Skeggs | b2b0993 | 2010-11-24 10:47:15 +1000 | [diff] [blame] | 104 | } |
Ben Skeggs | 4b223ee | 2010-08-03 10:00:56 +1000 | [diff] [blame] | 105 | |
Ben Skeggs | c420b2d | 2012-05-01 20:48:08 +1000 | [diff] [blame] | 106 | static int |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 107 | nvc0_fifo_context_attach(struct nouveau_object *parent, |
| 108 | struct nouveau_object *object) |
Ben Skeggs | 4b223ee | 2010-08-03 10:00:56 +1000 | [diff] [blame] | 109 | { |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 110 | struct nouveau_bar *bar = nouveau_bar(parent); |
| 111 | struct nvc0_fifo_base *base = (void *)parent->parent; |
| 112 | struct nouveau_engctx *ectx = (void *)object; |
| 113 | u32 addr; |
| 114 | int ret; |
Ben Skeggs | b2b0993 | 2010-11-24 10:47:15 +1000 | [diff] [blame] | 115 | |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 116 | switch (nv_engidx(object->engine)) { |
| 117 | case NVDEV_ENGINE_SW : return 0; |
| 118 | case NVDEV_ENGINE_GR : addr = 0x0210; break; |
| 119 | case NVDEV_ENGINE_COPY0: addr = 0x0230; break; |
| 120 | case NVDEV_ENGINE_COPY1: addr = 0x0240; break; |
Maarten Lankhorst | 23c14ed | 2012-11-23 11:08:23 +1000 | [diff] [blame] | 121 | case NVDEV_ENGINE_BSP : addr = 0x0270; break; |
| 122 | case NVDEV_ENGINE_VP : addr = 0x0250; break; |
| 123 | case NVDEV_ENGINE_PPP : addr = 0x0260; break; |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 124 | default: |
| 125 | return -EINVAL; |
Ben Skeggs | b2b0993 | 2010-11-24 10:47:15 +1000 | [diff] [blame] | 126 | } |
| 127 | |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 128 | if (!ectx->vma.node) { |
| 129 | ret = nouveau_gpuobj_map_vm(nv_gpuobj(ectx), base->vm, |
| 130 | NV_MEM_ACCESS_RW, &ectx->vma); |
| 131 | if (ret) |
| 132 | return ret; |
Ben Skeggs | 4c2d422 | 2012-08-10 15:10:34 +1000 | [diff] [blame] | 133 | |
| 134 | nv_engctx(ectx)->addr = nv_gpuobj(base)->addr >> 12; |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 135 | } |
Ben Skeggs | b2b0993 | 2010-11-24 10:47:15 +1000 | [diff] [blame] | 136 | |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 137 | nv_wo32(base, addr + 0x00, lower_32_bits(ectx->vma.offset) | 4); |
| 138 | nv_wo32(base, addr + 0x04, upper_32_bits(ectx->vma.offset)); |
| 139 | bar->flush(bar); |
| 140 | return 0; |
| 141 | } |
Ben Skeggs | b2b0993 | 2010-11-24 10:47:15 +1000 | [diff] [blame] | 142 | |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 143 | static int |
| 144 | nvc0_fifo_context_detach(struct nouveau_object *parent, bool suspend, |
| 145 | struct nouveau_object *object) |
| 146 | { |
| 147 | struct nouveau_bar *bar = nouveau_bar(parent); |
| 148 | struct nvc0_fifo_priv *priv = (void *)parent->engine; |
| 149 | struct nvc0_fifo_base *base = (void *)parent->parent; |
| 150 | struct nvc0_fifo_chan *chan = (void *)parent; |
| 151 | u32 addr; |
| 152 | |
| 153 | switch (nv_engidx(object->engine)) { |
| 154 | case NVDEV_ENGINE_SW : return 0; |
| 155 | case NVDEV_ENGINE_GR : addr = 0x0210; break; |
| 156 | case NVDEV_ENGINE_COPY0: addr = 0x0230; break; |
| 157 | case NVDEV_ENGINE_COPY1: addr = 0x0240; break; |
Maarten Lankhorst | 23c14ed | 2012-11-23 11:08:23 +1000 | [diff] [blame] | 158 | case NVDEV_ENGINE_BSP : addr = 0x0270; break; |
| 159 | case NVDEV_ENGINE_VP : addr = 0x0250; break; |
| 160 | case NVDEV_ENGINE_PPP : addr = 0x0260; break; |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 161 | default: |
| 162 | return -EINVAL; |
| 163 | } |
| 164 | |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 165 | nv_wr32(priv, 0x002634, chan->base.chid); |
| 166 | if (!nv_wait(priv, 0x002634, 0xffffffff, chan->base.chid)) { |
Marcin Slusarz | 93260d3 | 2012-12-09 23:00:34 +0100 | [diff] [blame] | 167 | nv_error(priv, "channel %d [%s] kick timeout\n", |
| 168 | chan->base.chid, nouveau_client_name(chan)); |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 169 | if (suspend) |
| 170 | return -EBUSY; |
| 171 | } |
| 172 | |
Ben Skeggs | edc260d | 2012-11-27 11:05:36 +1000 | [diff] [blame] | 173 | nv_wo32(base, addr + 0x00, 0x00000000); |
| 174 | nv_wo32(base, addr + 0x04, 0x00000000); |
| 175 | bar->flush(bar); |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 176 | return 0; |
| 177 | } |
| 178 | |
| 179 | static int |
| 180 | nvc0_fifo_chan_ctor(struct nouveau_object *parent, |
| 181 | struct nouveau_object *engine, |
| 182 | struct nouveau_oclass *oclass, void *data, u32 size, |
| 183 | struct nouveau_object **pobject) |
| 184 | { |
| 185 | struct nouveau_bar *bar = nouveau_bar(parent); |
| 186 | struct nvc0_fifo_priv *priv = (void *)engine; |
| 187 | struct nvc0_fifo_base *base = (void *)parent; |
| 188 | struct nvc0_fifo_chan *chan; |
Ben Skeggs | dbff2de | 2012-08-06 18:16:37 +1000 | [diff] [blame] | 189 | struct nv50_channel_ind_class *args = data; |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 190 | u64 usermem, ioffset, ilength; |
| 191 | int ret, i; |
| 192 | |
| 193 | if (size < sizeof(*args)) |
| 194 | return -EINVAL; |
| 195 | |
| 196 | ret = nouveau_fifo_channel_create(parent, engine, oclass, 1, |
| 197 | priv->user.bar.offset, 0x1000, |
| 198 | args->pushbuf, |
Martin Peres | 507ceb1 | 2012-11-27 00:30:32 +0100 | [diff] [blame] | 199 | (1ULL << NVDEV_ENGINE_SW) | |
| 200 | (1ULL << NVDEV_ENGINE_GR) | |
| 201 | (1ULL << NVDEV_ENGINE_COPY0) | |
| 202 | (1ULL << NVDEV_ENGINE_COPY1) | |
| 203 | (1ULL << NVDEV_ENGINE_BSP) | |
| 204 | (1ULL << NVDEV_ENGINE_VP) | |
| 205 | (1ULL << NVDEV_ENGINE_PPP), &chan); |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 206 | *pobject = nv_object(chan); |
Ben Skeggs | c420b2d | 2012-05-01 20:48:08 +1000 | [diff] [blame] | 207 | if (ret) |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 208 | return ret; |
| 209 | |
| 210 | nv_parent(chan)->context_attach = nvc0_fifo_context_attach; |
| 211 | nv_parent(chan)->context_detach = nvc0_fifo_context_detach; |
| 212 | |
| 213 | usermem = chan->base.chid * 0x1000; |
| 214 | ioffset = args->ioffset; |
Ilia Mirkin | 57be046 | 2013-07-27 00:27:00 -0400 | [diff] [blame] | 215 | ilength = order_base_2(args->ilength / 8); |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 216 | |
| 217 | for (i = 0; i < 0x1000; i += 4) |
| 218 | nv_wo32(priv->user.mem, usermem + i, 0x00000000); |
| 219 | |
| 220 | nv_wo32(base, 0x08, lower_32_bits(priv->user.mem->addr + usermem)); |
| 221 | nv_wo32(base, 0x0c, upper_32_bits(priv->user.mem->addr + usermem)); |
| 222 | nv_wo32(base, 0x10, 0x0000face); |
| 223 | nv_wo32(base, 0x30, 0xfffff902); |
| 224 | nv_wo32(base, 0x48, lower_32_bits(ioffset)); |
| 225 | nv_wo32(base, 0x4c, upper_32_bits(ioffset) | (ilength << 16)); |
| 226 | nv_wo32(base, 0x54, 0x00000002); |
| 227 | nv_wo32(base, 0x84, 0x20400000); |
| 228 | nv_wo32(base, 0x94, 0x30000001); |
| 229 | nv_wo32(base, 0x9c, 0x00000100); |
| 230 | nv_wo32(base, 0xa4, 0x1f1f1f1f); |
| 231 | nv_wo32(base, 0xa8, 0x1f1f1f1f); |
| 232 | nv_wo32(base, 0xac, 0x0000001f); |
| 233 | nv_wo32(base, 0xb8, 0xf8000000); |
| 234 | nv_wo32(base, 0xf8, 0x10003080); /* 0x002310 */ |
| 235 | nv_wo32(base, 0xfc, 0x10000010); /* 0x002350 */ |
| 236 | bar->flush(bar); |
| 237 | return 0; |
| 238 | } |
| 239 | |
| 240 | static int |
| 241 | nvc0_fifo_chan_init(struct nouveau_object *object) |
| 242 | { |
| 243 | struct nouveau_gpuobj *base = nv_gpuobj(object->parent); |
| 244 | struct nvc0_fifo_priv *priv = (void *)object->engine; |
| 245 | struct nvc0_fifo_chan *chan = (void *)object; |
| 246 | u32 chid = chan->base.chid; |
| 247 | int ret; |
| 248 | |
| 249 | ret = nouveau_fifo_channel_init(&chan->base); |
| 250 | if (ret) |
| 251 | return ret; |
| 252 | |
| 253 | nv_wr32(priv, 0x003000 + (chid * 8), 0xc0000000 | base->addr >> 12); |
Ben Skeggs | e2822b7 | 2014-02-22 00:52:45 +1000 | [diff] [blame] | 254 | |
| 255 | if (chan->state == STOPPED && (chan->state = RUNNING) == RUNNING) { |
| 256 | nv_wr32(priv, 0x003004 + (chid * 8), 0x001f0001); |
| 257 | nvc0_fifo_runlist_update(priv); |
| 258 | } |
| 259 | |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 260 | return 0; |
| 261 | } |
| 262 | |
Ben Skeggs | e99bf01 | 2014-02-22 00:18:17 +1000 | [diff] [blame] | 263 | static void nvc0_fifo_intr_engine(struct nvc0_fifo_priv *priv); |
| 264 | |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 265 | static int |
| 266 | nvc0_fifo_chan_fini(struct nouveau_object *object, bool suspend) |
| 267 | { |
| 268 | struct nvc0_fifo_priv *priv = (void *)object->engine; |
| 269 | struct nvc0_fifo_chan *chan = (void *)object; |
| 270 | u32 chid = chan->base.chid; |
| 271 | |
Ben Skeggs | e2822b7 | 2014-02-22 00:52:45 +1000 | [diff] [blame] | 272 | if (chan->state == RUNNING && (chan->state = STOPPED) == STOPPED) { |
| 273 | nv_mask(priv, 0x003004 + (chid * 8), 0x00000001, 0x00000000); |
| 274 | nvc0_fifo_runlist_update(priv); |
| 275 | } |
Ben Skeggs | e99bf01 | 2014-02-22 00:18:17 +1000 | [diff] [blame] | 276 | |
| 277 | nvc0_fifo_intr_engine(priv); |
| 278 | |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 279 | nv_wr32(priv, 0x003000 + (chid * 8), 0x00000000); |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 280 | return nouveau_fifo_channel_fini(&chan->base, suspend); |
| 281 | } |
| 282 | |
| 283 | static struct nouveau_ofuncs |
| 284 | nvc0_fifo_ofuncs = { |
| 285 | .ctor = nvc0_fifo_chan_ctor, |
| 286 | .dtor = _nouveau_fifo_channel_dtor, |
| 287 | .init = nvc0_fifo_chan_init, |
| 288 | .fini = nvc0_fifo_chan_fini, |
| 289 | .rd32 = _nouveau_fifo_channel_rd32, |
| 290 | .wr32 = _nouveau_fifo_channel_wr32, |
| 291 | }; |
| 292 | |
| 293 | static struct nouveau_oclass |
| 294 | nvc0_fifo_sclass[] = { |
Ben Skeggs | c97f8c9 | 2012-08-19 16:03:00 +1000 | [diff] [blame] | 295 | { NVC0_CHANNEL_IND_CLASS, &nvc0_fifo_ofuncs }, |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 296 | {} |
| 297 | }; |
| 298 | |
| 299 | /******************************************************************************* |
| 300 | * FIFO context - instmem heap and vm setup |
| 301 | ******************************************************************************/ |
| 302 | |
| 303 | static int |
| 304 | nvc0_fifo_context_ctor(struct nouveau_object *parent, |
| 305 | struct nouveau_object *engine, |
| 306 | struct nouveau_oclass *oclass, void *data, u32 size, |
| 307 | struct nouveau_object **pobject) |
| 308 | { |
| 309 | struct nvc0_fifo_base *base; |
| 310 | int ret; |
| 311 | |
| 312 | ret = nouveau_fifo_context_create(parent, engine, oclass, NULL, 0x1000, |
| 313 | 0x1000, NVOBJ_FLAG_ZERO_ALLOC | |
| 314 | NVOBJ_FLAG_HEAP, &base); |
| 315 | *pobject = nv_object(base); |
| 316 | if (ret) |
| 317 | return ret; |
| 318 | |
Ben Skeggs | f50c805 | 2013-04-24 18:02:35 +1000 | [diff] [blame] | 319 | ret = nouveau_gpuobj_new(nv_object(base), NULL, 0x10000, 0x1000, 0, |
| 320 | &base->pgd); |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 321 | if (ret) |
| 322 | return ret; |
| 323 | |
| 324 | nv_wo32(base, 0x0200, lower_32_bits(base->pgd->addr)); |
| 325 | nv_wo32(base, 0x0204, upper_32_bits(base->pgd->addr)); |
| 326 | nv_wo32(base, 0x0208, 0xffffffff); |
| 327 | nv_wo32(base, 0x020c, 0x000000ff); |
| 328 | |
| 329 | ret = nouveau_vm_ref(nouveau_client(parent)->vm, &base->vm, base->pgd); |
| 330 | if (ret) |
| 331 | return ret; |
| 332 | |
| 333 | return 0; |
Ben Skeggs | 4b223ee | 2010-08-03 10:00:56 +1000 | [diff] [blame] | 334 | } |
| 335 | |
Ben Skeggs | c420b2d | 2012-05-01 20:48:08 +1000 | [diff] [blame] | 336 | static void |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 337 | nvc0_fifo_context_dtor(struct nouveau_object *object) |
Ben Skeggs | 4b223ee | 2010-08-03 10:00:56 +1000 | [diff] [blame] | 338 | { |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 339 | struct nvc0_fifo_base *base = (void *)object; |
| 340 | nouveau_vm_ref(NULL, &base->vm, base->pgd); |
| 341 | nouveau_gpuobj_ref(NULL, &base->pgd); |
| 342 | nouveau_fifo_context_destroy(&base->base); |
Ben Skeggs | b2b0993 | 2010-11-24 10:47:15 +1000 | [diff] [blame] | 343 | } |
| 344 | |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 345 | static struct nouveau_oclass |
| 346 | nvc0_fifo_cclass = { |
| 347 | .handle = NV_ENGCTX(FIFO, 0xc0), |
| 348 | .ofuncs = &(struct nouveau_ofuncs) { |
| 349 | .ctor = nvc0_fifo_context_ctor, |
| 350 | .dtor = nvc0_fifo_context_dtor, |
| 351 | .init = _nouveau_fifo_context_init, |
| 352 | .fini = _nouveau_fifo_context_fini, |
| 353 | .rd32 = _nouveau_fifo_context_rd32, |
| 354 | .wr32 = _nouveau_fifo_context_wr32, |
| 355 | }, |
| 356 | }; |
Ben Skeggs | b2b0993 | 2010-11-24 10:47:15 +1000 | [diff] [blame] | 357 | |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 358 | /******************************************************************************* |
| 359 | * PFIFO engine |
| 360 | ******************************************************************************/ |
Ben Skeggs | c420b2d | 2012-05-01 20:48:08 +1000 | [diff] [blame] | 361 | |
Ben Skeggs | 083c214 | 2014-02-22 00:31:29 +1000 | [diff] [blame] | 362 | static int |
| 363 | nvc0_fifo_swmthd(struct nvc0_fifo_priv *priv, u32 chid, u32 mthd, u32 data) |
| 364 | { |
| 365 | struct nvc0_fifo_chan *chan = NULL; |
| 366 | struct nouveau_handle *bind; |
| 367 | unsigned long flags; |
| 368 | int ret = -EINVAL; |
| 369 | |
| 370 | spin_lock_irqsave(&priv->base.lock, flags); |
| 371 | if (likely(chid >= priv->base.min && chid <= priv->base.max)) |
| 372 | chan = (void *)priv->base.channel[chid]; |
| 373 | if (unlikely(!chan)) |
| 374 | goto out; |
| 375 | |
| 376 | bind = nouveau_namedb_get_class(nv_namedb(chan), 0x906e); |
| 377 | if (likely(bind)) { |
| 378 | if (!mthd || !nv_call(bind->object, mthd, data)) |
| 379 | ret = 0; |
| 380 | nouveau_namedb_put(bind); |
| 381 | } |
| 382 | |
| 383 | out: |
| 384 | spin_unlock_irqrestore(&priv->base.lock, flags); |
| 385 | return ret; |
| 386 | } |
| 387 | |
Ben Skeggs | d439a5a | 2014-02-22 00:39:36 +1000 | [diff] [blame] | 388 | static const struct nouveau_enum |
Ben Skeggs | 4047653 | 2014-02-22 01:18:46 +1000 | [diff] [blame] | 389 | nvc0_fifo_sched_reason[] = { |
| 390 | { 0x0a, "CTXSW_TIMEOUT" }, |
| 391 | {} |
| 392 | }; |
| 393 | |
| 394 | static void |
| 395 | nvc0_fifo_intr_sched(struct nvc0_fifo_priv *priv) |
| 396 | { |
| 397 | u32 intr = nv_rd32(priv, 0x00254c); |
| 398 | u32 code = intr & 0x000000ff; |
| 399 | const struct nouveau_enum *en; |
| 400 | char enunk[6] = ""; |
| 401 | |
| 402 | en = nouveau_enum_find(nvc0_fifo_sched_reason, code); |
| 403 | if (!en) |
| 404 | snprintf(enunk, sizeof(enunk), "UNK%02x", code); |
| 405 | |
| 406 | nv_error(priv, "SCHED_ERROR [ %s ]\n", en ? en->name : enunk); |
| 407 | } |
| 408 | |
| 409 | static const struct nouveau_enum |
Ben Skeggs | d439a5a | 2014-02-22 00:39:36 +1000 | [diff] [blame] | 410 | nvc0_fifo_fault_engine[] = { |
Marcin Slusarz | 93260d3 | 2012-12-09 23:00:34 +0100 | [diff] [blame] | 411 | { 0x00, "PGRAPH", NULL, NVDEV_ENGINE_GR }, |
Ben Skeggs | 7a31347 | 2011-03-29 00:52:59 +1000 | [diff] [blame] | 412 | { 0x03, "PEEPHOLE" }, |
| 413 | { 0x04, "BAR1" }, |
| 414 | { 0x05, "BAR3" }, |
Marcin Slusarz | 93260d3 | 2012-12-09 23:00:34 +0100 | [diff] [blame] | 415 | { 0x07, "PFIFO", NULL, NVDEV_ENGINE_FIFO }, |
| 416 | { 0x10, "PBSP", NULL, NVDEV_ENGINE_BSP }, |
| 417 | { 0x11, "PPPP", NULL, NVDEV_ENGINE_PPP }, |
Ben Skeggs | 7a31347 | 2011-03-29 00:52:59 +1000 | [diff] [blame] | 418 | { 0x13, "PCOUNTER" }, |
Marcin Slusarz | 93260d3 | 2012-12-09 23:00:34 +0100 | [diff] [blame] | 419 | { 0x14, "PVP", NULL, NVDEV_ENGINE_VP }, |
| 420 | { 0x15, "PCOPY0", NULL, NVDEV_ENGINE_COPY0 }, |
| 421 | { 0x16, "PCOPY1", NULL, NVDEV_ENGINE_COPY1 }, |
Ben Skeggs | 7a31347 | 2011-03-29 00:52:59 +1000 | [diff] [blame] | 422 | { 0x17, "PDAEMON" }, |
Ben Skeggs | b2b0993 | 2010-11-24 10:47:15 +1000 | [diff] [blame] | 423 | {} |
| 424 | }; |
| 425 | |
Ben Skeggs | d439a5a | 2014-02-22 00:39:36 +1000 | [diff] [blame] | 426 | static const struct nouveau_enum |
| 427 | nvc0_fifo_fault_reason[] = { |
Ben Skeggs | e296663 | 2011-03-29 08:57:34 +1000 | [diff] [blame] | 428 | { 0x00, "PT_NOT_PRESENT" }, |
| 429 | { 0x01, "PT_TOO_SHORT" }, |
| 430 | { 0x02, "PAGE_NOT_PRESENT" }, |
| 431 | { 0x03, "VM_LIMIT_EXCEEDED" }, |
| 432 | { 0x04, "NO_CHANNEL" }, |
| 433 | { 0x05, "PAGE_SYSTEM_ONLY" }, |
| 434 | { 0x06, "PAGE_READ_ONLY" }, |
| 435 | { 0x0a, "COMPRESSED_SYSRAM" }, |
| 436 | { 0x0c, "INVALID_STORAGE_TYPE" }, |
Ben Skeggs | b2b0993 | 2010-11-24 10:47:15 +1000 | [diff] [blame] | 437 | {} |
| 438 | }; |
| 439 | |
Ben Skeggs | d439a5a | 2014-02-22 00:39:36 +1000 | [diff] [blame] | 440 | static const struct nouveau_enum |
| 441 | nvc0_fifo_fault_hubclient[] = { |
Ben Skeggs | 7795bee | 2011-03-29 09:28:24 +1000 | [diff] [blame] | 442 | { 0x01, "PCOPY0" }, |
| 443 | { 0x02, "PCOPY1" }, |
| 444 | { 0x04, "DISPATCH" }, |
| 445 | { 0x05, "CTXCTL" }, |
| 446 | { 0x06, "PFIFO" }, |
| 447 | { 0x07, "BAR_READ" }, |
| 448 | { 0x08, "BAR_WRITE" }, |
| 449 | { 0x0b, "PVP" }, |
| 450 | { 0x0c, "PPPP" }, |
| 451 | { 0x0d, "PBSP" }, |
| 452 | { 0x11, "PCOUNTER" }, |
| 453 | { 0x12, "PDAEMON" }, |
| 454 | { 0x14, "CCACHE" }, |
| 455 | { 0x15, "CCACHE_POST" }, |
| 456 | {} |
| 457 | }; |
| 458 | |
Ben Skeggs | d439a5a | 2014-02-22 00:39:36 +1000 | [diff] [blame] | 459 | static const struct nouveau_enum |
| 460 | nvc0_fifo_fault_gpcclient[] = { |
Ben Skeggs | 7795bee | 2011-03-29 09:28:24 +1000 | [diff] [blame] | 461 | { 0x01, "TEX" }, |
| 462 | { 0x0c, "ESETUP" }, |
| 463 | { 0x0e, "CTXCTL" }, |
| 464 | { 0x0f, "PROP" }, |
| 465 | {} |
| 466 | }; |
| 467 | |
Ben Skeggs | b2b0993 | 2010-11-24 10:47:15 +1000 | [diff] [blame] | 468 | static void |
Ben Skeggs | d439a5a | 2014-02-22 00:39:36 +1000 | [diff] [blame] | 469 | nvc0_fifo_intr_fault(struct nvc0_fifo_priv *priv, int unit) |
Ben Skeggs | b2b0993 | 2010-11-24 10:47:15 +1000 | [diff] [blame] | 470 | { |
Ben Skeggs | b3ccd34 | 2012-09-06 20:26:38 -0400 | [diff] [blame] | 471 | u32 inst = nv_rd32(priv, 0x002800 + (unit * 0x10)); |
| 472 | u32 valo = nv_rd32(priv, 0x002804 + (unit * 0x10)); |
| 473 | u32 vahi = nv_rd32(priv, 0x002808 + (unit * 0x10)); |
| 474 | u32 stat = nv_rd32(priv, 0x00280c + (unit * 0x10)); |
Ben Skeggs | d439a5a | 2014-02-22 00:39:36 +1000 | [diff] [blame] | 475 | u32 gpc = (stat & 0x1f000000) >> 24; |
Ben Skeggs | 7795bee | 2011-03-29 09:28:24 +1000 | [diff] [blame] | 476 | u32 client = (stat & 0x00001f00) >> 8; |
Ben Skeggs | d439a5a | 2014-02-22 00:39:36 +1000 | [diff] [blame] | 477 | u32 write = (stat & 0x00000080); |
| 478 | u32 hub = (stat & 0x00000040); |
| 479 | u32 reason = (stat & 0x0000000f); |
Marcin Slusarz | 93260d3 | 2012-12-09 23:00:34 +0100 | [diff] [blame] | 480 | struct nouveau_object *engctx = NULL; |
Ben Skeggs | d439a5a | 2014-02-22 00:39:36 +1000 | [diff] [blame] | 481 | struct nouveau_engine *engine; |
| 482 | const struct nouveau_enum *er, *eu, *ec; |
| 483 | char erunk[6] = ""; |
| 484 | char euunk[6] = ""; |
| 485 | char ecunk[6] = ""; |
| 486 | char gpcid[3] = ""; |
Ben Skeggs | b2b0993 | 2010-11-24 10:47:15 +1000 | [diff] [blame] | 487 | |
Ben Skeggs | b3ccd34 | 2012-09-06 20:26:38 -0400 | [diff] [blame] | 488 | switch (unit) { |
| 489 | case 3: /* PEEPHOLE */ |
| 490 | nv_mask(priv, 0x001718, 0x00000000, 0x00000000); |
| 491 | break; |
| 492 | case 4: /* BAR1 */ |
| 493 | nv_mask(priv, 0x001704, 0x00000000, 0x00000000); |
| 494 | break; |
| 495 | case 5: /* BAR3 */ |
| 496 | nv_mask(priv, 0x001714, 0x00000000, 0x00000000); |
| 497 | break; |
| 498 | default: |
| 499 | break; |
| 500 | } |
| 501 | |
Ben Skeggs | d439a5a | 2014-02-22 00:39:36 +1000 | [diff] [blame] | 502 | er = nouveau_enum_find(nvc0_fifo_fault_reason, reason); |
| 503 | if (!er) |
| 504 | snprintf(erunk, sizeof(erunk), "UNK%02X", reason); |
| 505 | |
| 506 | eu = nouveau_enum_find(nvc0_fifo_fault_engine, unit); |
| 507 | if (eu) { |
| 508 | if (eu->data2) { |
| 509 | engine = nouveau_engine(priv, eu->data2); |
| 510 | if (engine) |
| 511 | engctx = nouveau_engctx_get(engine, inst); |
| 512 | } |
Ben Skeggs | 7795bee | 2011-03-29 09:28:24 +1000 | [diff] [blame] | 513 | } else { |
Ben Skeggs | d439a5a | 2014-02-22 00:39:36 +1000 | [diff] [blame] | 514 | snprintf(euunk, sizeof(euunk), "UNK%02x", unit); |
Ben Skeggs | 7795bee | 2011-03-29 09:28:24 +1000 | [diff] [blame] | 515 | } |
Marcin Slusarz | 93260d3 | 2012-12-09 23:00:34 +0100 | [diff] [blame] | 516 | |
Ben Skeggs | d439a5a | 2014-02-22 00:39:36 +1000 | [diff] [blame] | 517 | if (hub) { |
| 518 | ec = nouveau_enum_find(nvc0_fifo_fault_hubclient, client); |
| 519 | } else { |
| 520 | ec = nouveau_enum_find(nvc0_fifo_fault_gpcclient, client); |
| 521 | snprintf(gpcid, sizeof(gpcid), "%d", gpc); |
Marcin Slusarz | 93260d3 | 2012-12-09 23:00:34 +0100 | [diff] [blame] | 522 | } |
Ben Skeggs | d439a5a | 2014-02-22 00:39:36 +1000 | [diff] [blame] | 523 | |
| 524 | if (!ec) |
| 525 | snprintf(ecunk, sizeof(ecunk), "UNK%02x", client); |
| 526 | |
| 527 | nv_error(priv, "%s fault at 0x%010llx [%s] from %s/%s%s%s%s on " |
| 528 | "channel 0x%010llx [%s]\n", write ? "write" : "read", |
| 529 | (u64)vahi << 32 | valo, er ? er->name : erunk, |
| 530 | eu ? eu->name : euunk, hub ? "" : "GPC", gpcid, hub ? "" : "/", |
| 531 | ec ? ec->name : ecunk, (u64)inst << 12, |
| 532 | nouveau_client_name(engctx)); |
Marcin Slusarz | 93260d3 | 2012-12-09 23:00:34 +0100 | [diff] [blame] | 533 | |
| 534 | nouveau_engctx_put(engctx); |
Ben Skeggs | b2b0993 | 2010-11-24 10:47:15 +1000 | [diff] [blame] | 535 | } |
| 536 | |
Ben Skeggs | 083c214 | 2014-02-22 00:31:29 +1000 | [diff] [blame] | 537 | static const struct nouveau_bitfield |
| 538 | nvc0_fifo_pbdma_intr[] = { |
| 539 | /* { 0x00008000, "" } seen with null ib push */ |
| 540 | { 0x00200000, "ILLEGAL_MTHD" }, |
| 541 | { 0x00800000, "EMPTY_SUBC" }, |
| 542 | {} |
| 543 | }; |
Ben Skeggs | d5316e2 | 2012-03-21 13:53:49 +1000 | [diff] [blame] | 544 | |
Ben Skeggs | b2b0993 | 2010-11-24 10:47:15 +1000 | [diff] [blame] | 545 | static void |
Ben Skeggs | 083c214 | 2014-02-22 00:31:29 +1000 | [diff] [blame] | 546 | nvc0_fifo_intr_pbdma(struct nvc0_fifo_priv *priv, int unit) |
Ben Skeggs | b2b0993 | 2010-11-24 10:47:15 +1000 | [diff] [blame] | 547 | { |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 548 | u32 stat = nv_rd32(priv, 0x040108 + (unit * 0x2000)); |
| 549 | u32 addr = nv_rd32(priv, 0x0400c0 + (unit * 0x2000)); |
| 550 | u32 data = nv_rd32(priv, 0x0400c4 + (unit * 0x2000)); |
| 551 | u32 chid = nv_rd32(priv, 0x040120 + (unit * 0x2000)) & 0x7f; |
| 552 | u32 subc = (addr & 0x00070000) >> 16; |
Ben Skeggs | b2b0993 | 2010-11-24 10:47:15 +1000 | [diff] [blame] | 553 | u32 mthd = (addr & 0x00003ffc); |
Ben Skeggs | d5316e2 | 2012-03-21 13:53:49 +1000 | [diff] [blame] | 554 | u32 show = stat; |
Ben Skeggs | b2b0993 | 2010-11-24 10:47:15 +1000 | [diff] [blame] | 555 | |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 556 | if (stat & 0x00800000) { |
| 557 | if (!nvc0_fifo_swmthd(priv, chid, mthd, data)) |
| 558 | show &= ~0x00800000; |
Ben Skeggs | d5316e2 | 2012-03-21 13:53:49 +1000 | [diff] [blame] | 559 | } |
Ben Skeggs | b2b0993 | 2010-11-24 10:47:15 +1000 | [diff] [blame] | 560 | |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 561 | if (show) { |
Ben Skeggs | 0357466 | 2014-01-28 11:47:46 +1000 | [diff] [blame] | 562 | nv_error(priv, "PBDMA%d:", unit); |
| 563 | nouveau_bitfield_print(nvc0_fifo_pbdma_intr, show); |
Marcin Slusarz | f533da1 | 2012-12-09 15:45:20 +0100 | [diff] [blame] | 564 | pr_cont("\n"); |
Marcin Slusarz | 93260d3 | 2012-12-09 23:00:34 +0100 | [diff] [blame] | 565 | nv_error(priv, |
Ben Skeggs | 0357466 | 2014-01-28 11:47:46 +1000 | [diff] [blame] | 566 | "PBDMA%d: ch %d [%s] subc %d mthd 0x%04x data 0x%08x\n", |
Marcin Slusarz | 93260d3 | 2012-12-09 23:00:34 +0100 | [diff] [blame] | 567 | unit, chid, |
| 568 | nouveau_client_name_for_fifo_chid(&priv->base, chid), |
| 569 | subc, mthd, data); |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 570 | } |
| 571 | |
| 572 | nv_wr32(priv, 0x0400c0 + (unit * 0x2000), 0x80600008); |
| 573 | nv_wr32(priv, 0x040108 + (unit * 0x2000), stat); |
Ben Skeggs | b2b0993 | 2010-11-24 10:47:15 +1000 | [diff] [blame] | 574 | } |
| 575 | |
| 576 | static void |
Ben Skeggs | a07d0e7 | 2014-02-22 00:28:47 +1000 | [diff] [blame] | 577 | nvc0_fifo_intr_runlist(struct nvc0_fifo_priv *priv) |
| 578 | { |
| 579 | u32 intr = nv_rd32(priv, 0x002a00); |
| 580 | |
| 581 | if (intr & 0x10000000) { |
| 582 | wake_up(&priv->runlist.wait); |
| 583 | nv_wr32(priv, 0x002a00, 0x10000000); |
| 584 | intr &= ~0x10000000; |
| 585 | } |
| 586 | |
| 587 | if (intr) { |
| 588 | nv_error(priv, "RUNLIST 0x%08x\n", intr); |
| 589 | nv_wr32(priv, 0x002a00, intr); |
| 590 | } |
| 591 | } |
| 592 | |
| 593 | static void |
Ben Skeggs | e99bf01 | 2014-02-22 00:18:17 +1000 | [diff] [blame] | 594 | nvc0_fifo_intr_engine_unit(struct nvc0_fifo_priv *priv, int engn) |
| 595 | { |
| 596 | u32 intr = nv_rd32(priv, 0x0025a8 + (engn * 0x04)); |
| 597 | u32 inte = nv_rd32(priv, 0x002628); |
| 598 | u32 unkn; |
| 599 | |
| 600 | for (unkn = 0; unkn < 8; unkn++) { |
| 601 | u32 ints = (intr >> (unkn * 0x04)) & inte; |
| 602 | if (ints & 0x1) { |
| 603 | nouveau_event_trigger(priv->base.uevent, 0); |
| 604 | ints &= ~1; |
| 605 | } |
| 606 | if (ints) { |
| 607 | nv_error(priv, "ENGINE %d %d %01x", engn, unkn, ints); |
| 608 | nv_mask(priv, 0x002628, ints, 0); |
| 609 | } |
| 610 | } |
| 611 | |
| 612 | nv_wr32(priv, 0x0025a8 + (engn * 0x04), intr); |
| 613 | } |
| 614 | |
| 615 | static void |
| 616 | nvc0_fifo_intr_engine(struct nvc0_fifo_priv *priv) |
| 617 | { |
| 618 | u32 mask = nv_rd32(priv, 0x0025a4); |
| 619 | while (mask) { |
| 620 | u32 unit = __ffs(mask); |
| 621 | nvc0_fifo_intr_engine_unit(priv, unit); |
| 622 | mask &= ~(1 << unit); |
| 623 | } |
| 624 | } |
| 625 | |
| 626 | static void |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 627 | nvc0_fifo_intr(struct nouveau_subdev *subdev) |
Ben Skeggs | b2b0993 | 2010-11-24 10:47:15 +1000 | [diff] [blame] | 628 | { |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 629 | struct nvc0_fifo_priv *priv = (void *)subdev; |
| 630 | u32 mask = nv_rd32(priv, 0x002140); |
| 631 | u32 stat = nv_rd32(priv, 0x002100) & mask; |
Ben Skeggs | b2b0993 | 2010-11-24 10:47:15 +1000 | [diff] [blame] | 632 | |
Ben Skeggs | 32256c8 | 2013-01-31 19:49:33 -0500 | [diff] [blame] | 633 | if (stat & 0x00000001) { |
| 634 | u32 intr = nv_rd32(priv, 0x00252c); |
| 635 | nv_warn(priv, "INTR 0x00000001: 0x%08x\n", intr); |
| 636 | nv_wr32(priv, 0x002100, 0x00000001); |
| 637 | stat &= ~0x00000001; |
| 638 | } |
| 639 | |
Ben Skeggs | cc8cd64 | 2011-01-28 13:42:16 +1000 | [diff] [blame] | 640 | if (stat & 0x00000100) { |
Ben Skeggs | 4047653 | 2014-02-22 01:18:46 +1000 | [diff] [blame] | 641 | nvc0_fifo_intr_sched(priv); |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 642 | nv_wr32(priv, 0x002100, 0x00000100); |
Ben Skeggs | cc8cd64 | 2011-01-28 13:42:16 +1000 | [diff] [blame] | 643 | stat &= ~0x00000100; |
| 644 | } |
| 645 | |
Ben Skeggs | 32256c8 | 2013-01-31 19:49:33 -0500 | [diff] [blame] | 646 | if (stat & 0x00010000) { |
| 647 | u32 intr = nv_rd32(priv, 0x00256c); |
| 648 | nv_warn(priv, "INTR 0x00010000: 0x%08x\n", intr); |
| 649 | nv_wr32(priv, 0x002100, 0x00010000); |
| 650 | stat &= ~0x00010000; |
| 651 | } |
| 652 | |
| 653 | if (stat & 0x01000000) { |
| 654 | u32 intr = nv_rd32(priv, 0x00258c); |
| 655 | nv_warn(priv, "INTR 0x01000000: 0x%08x\n", intr); |
| 656 | nv_wr32(priv, 0x002100, 0x01000000); |
| 657 | stat &= ~0x01000000; |
| 658 | } |
| 659 | |
Ben Skeggs | b2b0993 | 2010-11-24 10:47:15 +1000 | [diff] [blame] | 660 | if (stat & 0x10000000) { |
Ben Skeggs | d439a5a | 2014-02-22 00:39:36 +1000 | [diff] [blame] | 661 | u32 mask = nv_rd32(priv, 0x00259c); |
| 662 | while (mask) { |
| 663 | u32 unit = __ffs(mask); |
| 664 | nvc0_fifo_intr_fault(priv, unit); |
| 665 | nv_wr32(priv, 0x00259c, (1 << unit)); |
| 666 | mask &= ~(1 << unit); |
Ben Skeggs | b2b0993 | 2010-11-24 10:47:15 +1000 | [diff] [blame] | 667 | } |
Ben Skeggs | b2b0993 | 2010-11-24 10:47:15 +1000 | [diff] [blame] | 668 | stat &= ~0x10000000; |
| 669 | } |
| 670 | |
| 671 | if (stat & 0x20000000) { |
Ben Skeggs | 083c214 | 2014-02-22 00:31:29 +1000 | [diff] [blame] | 672 | u32 mask = nv_rd32(priv, 0x0025a0); |
| 673 | while (mask) { |
| 674 | u32 unit = __ffs(mask); |
| 675 | nvc0_fifo_intr_pbdma(priv, unit); |
| 676 | nv_wr32(priv, 0x0025a0, (1 << unit)); |
| 677 | mask &= ~(1 << unit); |
Ben Skeggs | b2b0993 | 2010-11-24 10:47:15 +1000 | [diff] [blame] | 678 | } |
Ben Skeggs | b2b0993 | 2010-11-24 10:47:15 +1000 | [diff] [blame] | 679 | stat &= ~0x20000000; |
| 680 | } |
| 681 | |
Ben Skeggs | cc8cd64 | 2011-01-28 13:42:16 +1000 | [diff] [blame] | 682 | if (stat & 0x40000000) { |
Ben Skeggs | a07d0e7 | 2014-02-22 00:28:47 +1000 | [diff] [blame] | 683 | nvc0_fifo_intr_runlist(priv); |
Ben Skeggs | cc8cd64 | 2011-01-28 13:42:16 +1000 | [diff] [blame] | 684 | stat &= ~0x40000000; |
| 685 | } |
| 686 | |
Ben Skeggs | 32256c8 | 2013-01-31 19:49:33 -0500 | [diff] [blame] | 687 | if (stat & 0x80000000) { |
Ben Skeggs | e99bf01 | 2014-02-22 00:18:17 +1000 | [diff] [blame] | 688 | nvc0_fifo_intr_engine(priv); |
Ben Skeggs | 32256c8 | 2013-01-31 19:49:33 -0500 | [diff] [blame] | 689 | stat &= ~0x80000000; |
| 690 | } |
| 691 | |
Ben Skeggs | b2b0993 | 2010-11-24 10:47:15 +1000 | [diff] [blame] | 692 | if (stat) { |
Ben Skeggs | 22a7a27 | 2014-02-22 00:19:19 +1000 | [diff] [blame] | 693 | nv_error(priv, "INTR 0x%08x\n", stat); |
| 694 | nv_mask(priv, 0x002140, stat, 0x00000000); |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 695 | nv_wr32(priv, 0x002100, stat); |
Ben Skeggs | b2b0993 | 2010-11-24 10:47:15 +1000 | [diff] [blame] | 696 | } |
Ben Skeggs | b2b0993 | 2010-11-24 10:47:15 +1000 | [diff] [blame] | 697 | } |
Ben Skeggs | c420b2d | 2012-05-01 20:48:08 +1000 | [diff] [blame] | 698 | |
Ben Skeggs | 9bd2ddb | 2013-01-31 13:51:20 +1000 | [diff] [blame] | 699 | static void |
| 700 | nvc0_fifo_uevent_enable(struct nouveau_event *event, int index) |
| 701 | { |
| 702 | struct nvc0_fifo_priv *priv = event->priv; |
| 703 | nv_mask(priv, 0x002140, 0x80000000, 0x80000000); |
| 704 | } |
| 705 | |
| 706 | static void |
| 707 | nvc0_fifo_uevent_disable(struct nouveau_event *event, int index) |
| 708 | { |
| 709 | struct nvc0_fifo_priv *priv = event->priv; |
| 710 | nv_mask(priv, 0x002140, 0x80000000, 0x00000000); |
| 711 | } |
| 712 | |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 713 | static int |
| 714 | nvc0_fifo_ctor(struct nouveau_object *parent, struct nouveau_object *engine, |
| 715 | struct nouveau_oclass *oclass, void *data, u32 size, |
| 716 | struct nouveau_object **pobject) |
Ben Skeggs | c420b2d | 2012-05-01 20:48:08 +1000 | [diff] [blame] | 717 | { |
Ben Skeggs | c420b2d | 2012-05-01 20:48:08 +1000 | [diff] [blame] | 718 | struct nvc0_fifo_priv *priv; |
| 719 | int ret; |
| 720 | |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 721 | ret = nouveau_fifo_create(parent, engine, oclass, 0, 127, &priv); |
| 722 | *pobject = nv_object(priv); |
Ben Skeggs | c420b2d | 2012-05-01 20:48:08 +1000 | [diff] [blame] | 723 | if (ret) |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 724 | return ret; |
Ben Skeggs | c420b2d | 2012-05-01 20:48:08 +1000 | [diff] [blame] | 725 | |
Ben Skeggs | f50c805 | 2013-04-24 18:02:35 +1000 | [diff] [blame] | 726 | ret = nouveau_gpuobj_new(nv_object(priv), NULL, 0x1000, 0x1000, 0, |
Ben Skeggs | a07d0e7 | 2014-02-22 00:28:47 +1000 | [diff] [blame] | 727 | &priv->runlist.mem[0]); |
Ben Skeggs | c420b2d | 2012-05-01 20:48:08 +1000 | [diff] [blame] | 728 | if (ret) |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 729 | return ret; |
Ben Skeggs | c420b2d | 2012-05-01 20:48:08 +1000 | [diff] [blame] | 730 | |
Ben Skeggs | f50c805 | 2013-04-24 18:02:35 +1000 | [diff] [blame] | 731 | ret = nouveau_gpuobj_new(nv_object(priv), NULL, 0x1000, 0x1000, 0, |
Ben Skeggs | a07d0e7 | 2014-02-22 00:28:47 +1000 | [diff] [blame] | 732 | &priv->runlist.mem[1]); |
Ben Skeggs | c420b2d | 2012-05-01 20:48:08 +1000 | [diff] [blame] | 733 | if (ret) |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 734 | return ret; |
Ben Skeggs | c420b2d | 2012-05-01 20:48:08 +1000 | [diff] [blame] | 735 | |
Ben Skeggs | a07d0e7 | 2014-02-22 00:28:47 +1000 | [diff] [blame] | 736 | init_waitqueue_head(&priv->runlist.wait); |
| 737 | |
Ben Skeggs | f50c805 | 2013-04-24 18:02:35 +1000 | [diff] [blame] | 738 | ret = nouveau_gpuobj_new(nv_object(priv), NULL, 128 * 0x1000, 0x1000, 0, |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 739 | &priv->user.mem); |
Ben Skeggs | 9da226f | 2012-07-13 16:54:45 +1000 | [diff] [blame] | 740 | if (ret) |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 741 | return ret; |
Ben Skeggs | 9da226f | 2012-07-13 16:54:45 +1000 | [diff] [blame] | 742 | |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 743 | ret = nouveau_gpuobj_map(priv->user.mem, NV_MEM_ACCESS_RW, |
| 744 | &priv->user.bar); |
Ben Skeggs | c420b2d | 2012-05-01 20:48:08 +1000 | [diff] [blame] | 745 | if (ret) |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 746 | return ret; |
| 747 | |
Ben Skeggs | 9bd2ddb | 2013-01-31 13:51:20 +1000 | [diff] [blame] | 748 | priv->base.uevent->enable = nvc0_fifo_uevent_enable; |
| 749 | priv->base.uevent->disable = nvc0_fifo_uevent_disable; |
| 750 | priv->base.uevent->priv = priv; |
| 751 | |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 752 | nv_subdev(priv)->unit = 0x00000100; |
| 753 | nv_subdev(priv)->intr = nvc0_fifo_intr; |
| 754 | nv_engine(priv)->cclass = &nvc0_fifo_cclass; |
| 755 | nv_engine(priv)->sclass = nvc0_fifo_sclass; |
| 756 | return 0; |
Ben Skeggs | c420b2d | 2012-05-01 20:48:08 +1000 | [diff] [blame] | 757 | } |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 758 | |
| 759 | static void |
| 760 | nvc0_fifo_dtor(struct nouveau_object *object) |
| 761 | { |
| 762 | struct nvc0_fifo_priv *priv = (void *)object; |
| 763 | |
| 764 | nouveau_gpuobj_unmap(&priv->user.bar); |
| 765 | nouveau_gpuobj_ref(NULL, &priv->user.mem); |
Ben Skeggs | a07d0e7 | 2014-02-22 00:28:47 +1000 | [diff] [blame] | 766 | nouveau_gpuobj_ref(NULL, &priv->runlist.mem[0]); |
| 767 | nouveau_gpuobj_ref(NULL, &priv->runlist.mem[1]); |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 768 | |
| 769 | nouveau_fifo_destroy(&priv->base); |
| 770 | } |
| 771 | |
| 772 | static int |
| 773 | nvc0_fifo_init(struct nouveau_object *object) |
| 774 | { |
| 775 | struct nvc0_fifo_priv *priv = (void *)object; |
| 776 | int ret, i; |
| 777 | |
| 778 | ret = nouveau_fifo_init(&priv->base); |
| 779 | if (ret) |
| 780 | return ret; |
| 781 | |
| 782 | nv_wr32(priv, 0x000204, 0xffffffff); |
| 783 | nv_wr32(priv, 0x002204, 0xffffffff); |
| 784 | |
| 785 | priv->spoon_nr = hweight32(nv_rd32(priv, 0x002204)); |
Ben Skeggs | 0357466 | 2014-01-28 11:47:46 +1000 | [diff] [blame] | 786 | nv_debug(priv, "%d PBDMA unit(s)\n", priv->spoon_nr); |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 787 | |
Ben Skeggs | 0357466 | 2014-01-28 11:47:46 +1000 | [diff] [blame] | 788 | /* assign engines to PBDMAs */ |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 789 | if (priv->spoon_nr >= 3) { |
| 790 | nv_wr32(priv, 0x002208, ~(1 << 0)); /* PGRAPH */ |
| 791 | nv_wr32(priv, 0x00220c, ~(1 << 1)); /* PVP */ |
| 792 | nv_wr32(priv, 0x002210, ~(1 << 1)); /* PPP */ |
| 793 | nv_wr32(priv, 0x002214, ~(1 << 1)); /* PBSP */ |
| 794 | nv_wr32(priv, 0x002218, ~(1 << 2)); /* PCE0 */ |
| 795 | nv_wr32(priv, 0x00221c, ~(1 << 1)); /* PCE1 */ |
| 796 | } |
| 797 | |
Ben Skeggs | 0357466 | 2014-01-28 11:47:46 +1000 | [diff] [blame] | 798 | /* PBDMA[n] */ |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 799 | for (i = 0; i < priv->spoon_nr; i++) { |
| 800 | nv_mask(priv, 0x04013c + (i * 0x2000), 0x10000100, 0x00000000); |
| 801 | nv_wr32(priv, 0x040108 + (i * 0x2000), 0xffffffff); /* INTR */ |
| 802 | nv_wr32(priv, 0x04010c + (i * 0x2000), 0xfffffeff); /* INTREN */ |
| 803 | } |
| 804 | |
| 805 | nv_mask(priv, 0x002200, 0x00000001, 0x00000001); |
| 806 | nv_wr32(priv, 0x002254, 0x10000000 | priv->user.bar.offset >> 12); |
| 807 | |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 808 | nv_wr32(priv, 0x002100, 0xffffffff); |
Ben Skeggs | a07d0e7 | 2014-02-22 00:28:47 +1000 | [diff] [blame] | 809 | nv_wr32(priv, 0x002140, 0x7fffffff); |
Ben Skeggs | e99bf01 | 2014-02-22 00:18:17 +1000 | [diff] [blame] | 810 | nv_wr32(priv, 0x002628, 0x00000001); /* ENGINE_INTR_EN */ |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 811 | return 0; |
| 812 | } |
| 813 | |
Ben Skeggs | 16c4f22 | 2013-11-05 14:26:58 +1000 | [diff] [blame] | 814 | struct nouveau_oclass * |
| 815 | nvc0_fifo_oclass = &(struct nouveau_oclass) { |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 816 | .handle = NV_ENGINE(FIFO, 0xc0), |
| 817 | .ofuncs = &(struct nouveau_ofuncs) { |
| 818 | .ctor = nvc0_fifo_ctor, |
| 819 | .dtor = nvc0_fifo_dtor, |
| 820 | .init = nvc0_fifo_init, |
| 821 | .fini = _nouveau_fifo_fini, |
| 822 | }, |
| 823 | }; |