blob: aaa01971efe9be983c901c9c53eb15df82b820dc [file] [log] [blame]
Benoit Goby79ad3b52011-03-09 16:28:56 -08001/*
2 * EHCI-compliant USB host controller driver for NVIDIA Tegra SoCs
3 *
4 * Copyright (C) 2010 Google, Inc.
Venu Byravarasubbdabdb2013-01-17 20:15:37 +00005 * Copyright (C) 2009 - 2013 NVIDIA Corporation
Benoit Goby79ad3b52011-03-09 16:28:56 -08006 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the
9 * Free Software Foundation; either version 2 of the License, or (at your
10 * option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * more details.
16 *
17 */
18
19#include <linux/clk.h>
Manjunath Goudar9fc5f242013-06-13 11:24:12 -060020#include <linux/dma-mapping.h>
Kishon Vijay Abraham Ided017e2012-06-26 17:40:32 +053021#include <linux/err.h>
Olof Johansson4a53f4e2011-11-04 09:12:40 +000022#include <linux/gpio.h>
Manjunath Goudar9fc5f242013-06-13 11:24:12 -060023#include <linux/io.h>
24#include <linux/irq.h>
25#include <linux/module.h>
Olof Johansson4a53f4e2011-11-04 09:12:40 +000026#include <linux/of.h>
Tuomas Tynkkynen327d8b42013-08-12 16:06:54 +030027#include <linux/of_device.h>
Olof Johansson4a53f4e2011-11-04 09:12:40 +000028#include <linux/of_gpio.h>
Manjunath Goudar9fc5f242013-06-13 11:24:12 -060029#include <linux/platform_device.h>
Alan Sternebf20de2012-05-01 11:28:49 -040030#include <linux/pm_runtime.h>
Stephen Warren75606f52013-11-06 16:53:58 -070031#include <linux/reset.h>
Manjunath Goudar9fc5f242013-06-13 11:24:12 -060032#include <linux/slab.h>
Venu Byravarasubbdabdb2013-01-17 20:15:37 +000033#include <linux/usb/ehci_def.h>
Venu Byravarasu1ba82162012-09-05 18:50:23 +053034#include <linux/usb/tegra_usb_phy.h>
Manjunath Goudar9fc5f242013-06-13 11:24:12 -060035#include <linux/usb.h>
36#include <linux/usb/hcd.h>
37#include <linux/usb/otg.h>
38
39#include "ehci.h"
Stephen Warren54388b22012-10-02 16:49:25 -060040
Manjunath Goudar9fc5f242013-06-13 11:24:12 -060041#define PORT_WAKE_BITS (PORT_WKOC_E|PORT_WKDISC_E|PORT_WKCONN_E)
42
Robert Morellfbf98652011-03-09 16:28:57 -080043#define TEGRA_USB_DMA_ALIGN 32
44
Manjunath Goudar9fc5f242013-06-13 11:24:12 -060045#define DRIVER_DESC "Tegra EHCI driver"
46#define DRV_NAME "tegra-ehci"
47
48static struct hc_driver __read_mostly tegra_ehci_hc_driver;
Tuomas Tynkkynena47cc242014-07-04 04:09:38 +030049static bool usb1_reset_attempted;
Manjunath Goudar9fc5f242013-06-13 11:24:12 -060050
Tuomas Tynkkynen327d8b42013-08-12 16:06:54 +030051struct tegra_ehci_soc_config {
52 bool has_hostpc;
53};
54
Benoit Goby79ad3b52011-03-09 16:28:56 -080055struct tegra_ehci_hcd {
Benoit Goby79ad3b52011-03-09 16:28:56 -080056 struct tegra_usb_phy *phy;
57 struct clk *clk;
Stephen Warren75606f52013-11-06 16:53:58 -070058 struct reset_control *rst;
Benoit Goby79ad3b52011-03-09 16:28:56 -080059 int port_resuming;
Venu Byravarasu585355c2012-12-13 20:59:08 +000060 bool needs_double_reset;
Benoit Goby79ad3b52011-03-09 16:28:56 -080061 enum tegra_usb_phy_port_speed port_speed;
62};
63
Tuomas Tynkkynena47cc242014-07-04 04:09:38 +030064/*
65 * The 1st USB controller contains some UTMI pad registers that are global for
66 * all the controllers on the chip. Those registers are also cleared when
67 * reset is asserted to the 1st controller. This means that the 1st controller
68 * can only be reset when no other controlled has finished probing. So we'll
69 * reset the 1st controller before doing any other setup on any of the
70 * controllers, and then never again.
71 *
72 * Since this is a PHY issue, the Tegra PHY driver should probably be doing
73 * the resetting of the USB controllers. But to keep compatibility with old
74 * device trees that don't have reset phandles in the PHYs, do it here.
75 * Those old DTs will be vulnerable to total USB breakage if the 1st EHCI
76 * device isn't the first one to finish probing, so warn them.
77 */
78static int tegra_reset_usb_controller(struct platform_device *pdev)
79{
80 struct device_node *phy_np;
81 struct usb_hcd *hcd = platform_get_drvdata(pdev);
82 struct tegra_ehci_hcd *tegra =
83 (struct tegra_ehci_hcd *)hcd_to_ehci(hcd)->priv;
84
85 phy_np = of_parse_phandle(pdev->dev.of_node, "nvidia,phy", 0);
86 if (!phy_np)
87 return -ENOENT;
88
89 if (!usb1_reset_attempted) {
90 struct reset_control *usb1_reset;
91
92 usb1_reset = of_reset_control_get(phy_np, "usb");
93 if (IS_ERR(usb1_reset)) {
94 dev_warn(&pdev->dev,
95 "can't get utmi-pads reset from the PHY\n");
96 dev_warn(&pdev->dev,
97 "continuing, but please update your DT\n");
98 } else {
99 reset_control_assert(usb1_reset);
100 udelay(1);
101 reset_control_deassert(usb1_reset);
102 }
103
104 reset_control_put(usb1_reset);
105 usb1_reset_attempted = true;
106 }
107
108 if (!of_property_read_bool(phy_np, "nvidia,has-utmi-pad-registers")) {
109 reset_control_assert(tegra->rst);
110 udelay(1);
111 reset_control_deassert(tegra->rst);
112 }
113
114 of_node_put(phy_np);
115
116 return 0;
117}
118
Jim Lin1f594b62011-04-17 11:58:25 +0300119static int tegra_ehci_internal_port_reset(
120 struct ehci_hcd *ehci,
121 u32 __iomem *portsc_reg
122)
123{
124 u32 temp;
125 unsigned long flags;
126 int retval = 0;
127 int i, tries;
128 u32 saved_usbintr;
129
130 spin_lock_irqsave(&ehci->lock, flags);
131 saved_usbintr = ehci_readl(ehci, &ehci->regs->intr_enable);
132 /* disable USB interrupt */
133 ehci_writel(ehci, 0, &ehci->regs->intr_enable);
134 spin_unlock_irqrestore(&ehci->lock, flags);
135
136 /*
137 * Here we have to do Port Reset at most twice for
138 * Port Enable bit to be set.
139 */
140 for (i = 0; i < 2; i++) {
141 temp = ehci_readl(ehci, portsc_reg);
142 temp |= PORT_RESET;
143 ehci_writel(ehci, temp, portsc_reg);
144 mdelay(10);
145 temp &= ~PORT_RESET;
146 ehci_writel(ehci, temp, portsc_reg);
147 mdelay(1);
148 tries = 100;
149 do {
150 mdelay(1);
151 /*
152 * Up to this point, Port Enable bit is
153 * expected to be set after 2 ms waiting.
154 * USB1 usually takes extra 45 ms, for safety,
155 * we take 100 ms as timeout.
156 */
157 temp = ehci_readl(ehci, portsc_reg);
158 } while (!(temp & PORT_PE) && tries--);
159 if (temp & PORT_PE)
160 break;
161 }
162 if (i == 2)
163 retval = -ETIMEDOUT;
164
165 /*
166 * Clear Connect Status Change bit if it's set.
167 * We can't clear PORT_PEC. It will also cause PORT_PE to be cleared.
168 */
169 if (temp & PORT_CSC)
170 ehci_writel(ehci, PORT_CSC, portsc_reg);
171
172 /*
173 * Write to clear any interrupt status bits that might be set
174 * during port reset.
175 */
176 temp = ehci_readl(ehci, &ehci->regs->status);
177 ehci_writel(ehci, temp, &ehci->regs->status);
178
179 /* restore original interrupt enable bits */
180 ehci_writel(ehci, saved_usbintr, &ehci->regs->intr_enable);
181 return retval;
182}
183
Benoit Goby79ad3b52011-03-09 16:28:56 -0800184static int tegra_ehci_hub_control(
185 struct usb_hcd *hcd,
186 u16 typeReq,
187 u16 wValue,
188 u16 wIndex,
189 char *buf,
190 u16 wLength
191)
192{
Stephen Warrenc19d14d2013-06-13 11:24:13 -0600193 struct ehci_hcd *ehci = hcd_to_ehci(hcd);
194 struct tegra_ehci_hcd *tegra = (struct tegra_ehci_hcd *)ehci->priv;
Benoit Goby79ad3b52011-03-09 16:28:56 -0800195 u32 __iomem *status_reg;
196 u32 temp;
197 unsigned long flags;
198 int retval = 0;
199
200 status_reg = &ehci->regs->port_status[(wIndex & 0xff) - 1];
201
202 spin_lock_irqsave(&ehci->lock, flags);
203
Stephen Warren6d5f89c2012-04-18 15:32:46 -0600204 if (typeReq == GetPortStatus) {
Benoit Goby79ad3b52011-03-09 16:28:56 -0800205 temp = ehci_readl(ehci, status_reg);
206 if (tegra->port_resuming && !(temp & PORT_SUSPEND)) {
207 /* Resume completed, re-enable disconnect detection */
208 tegra->port_resuming = 0;
Antoine Tenart3d46e732014-09-24 23:05:50 +0400209 tegra_usb_phy_postresume(hcd->usb_phy);
Benoit Goby79ad3b52011-03-09 16:28:56 -0800210 }
211 }
212
213 else if (typeReq == SetPortFeature && wValue == USB_PORT_FEAT_SUSPEND) {
214 temp = ehci_readl(ehci, status_reg);
215 if ((temp & PORT_PE) == 0 || (temp & PORT_RESET) != 0) {
216 retval = -EPIPE;
217 goto done;
218 }
219
Stephen Warrenb0876572012-04-25 12:31:10 -0600220 temp &= ~(PORT_RWC_BITS | PORT_WKCONN_E);
Benoit Goby79ad3b52011-03-09 16:28:56 -0800221 temp |= PORT_WKDISC_E | PORT_WKOC_E;
222 ehci_writel(ehci, temp | PORT_SUSPEND, status_reg);
223
224 /*
225 * If a transaction is in progress, there may be a delay in
226 * suspending the port. Poll until the port is suspended.
227 */
Manjunath Goudar2f3a6b82013-06-13 11:24:09 -0600228 if (ehci_handshake(ehci, status_reg, PORT_SUSPEND,
Benoit Goby79ad3b52011-03-09 16:28:56 -0800229 PORT_SUSPEND, 5000))
230 pr_err("%s: timeout waiting for SUSPEND\n", __func__);
231
232 set_bit((wIndex & 0xff) - 1, &ehci->suspended_ports);
233 goto done;
234 }
235
Jim Lin1f594b62011-04-17 11:58:25 +0300236 /* For USB1 port we need to issue Port Reset twice internally */
Venu Byravarasu585355c2012-12-13 20:59:08 +0000237 if (tegra->needs_double_reset &&
Jim Lin1f594b62011-04-17 11:58:25 +0300238 (typeReq == SetPortFeature && wValue == USB_PORT_FEAT_RESET)) {
239 spin_unlock_irqrestore(&ehci->lock, flags);
240 return tegra_ehci_internal_port_reset(ehci, status_reg);
241 }
242
Benoit Goby79ad3b52011-03-09 16:28:56 -0800243 /*
244 * Tegra host controller will time the resume operation to clear the bit
245 * when the port control state switches to HS or FS Idle. This behavior
246 * is different from EHCI where the host controller driver is required
247 * to set this bit to a zero after the resume duration is timed in the
248 * driver.
249 */
250 else if (typeReq == ClearPortFeature &&
251 wValue == USB_PORT_FEAT_SUSPEND) {
252 temp = ehci_readl(ehci, status_reg);
253 if ((temp & PORT_RESET) || !(temp & PORT_PE)) {
254 retval = -EPIPE;
255 goto done;
256 }
257
258 if (!(temp & PORT_SUSPEND))
259 goto done;
260
261 /* Disable disconnect detection during port resume */
Antoine Tenart3d46e732014-09-24 23:05:50 +0400262 tegra_usb_phy_preresume(hcd->usb_phy);
Benoit Goby79ad3b52011-03-09 16:28:56 -0800263
264 ehci->reset_done[wIndex-1] = jiffies + msecs_to_jiffies(25);
265
266 temp &= ~(PORT_RWC_BITS | PORT_WAKE_BITS);
267 /* start resume signalling */
268 ehci_writel(ehci, temp | PORT_RESUME, status_reg);
Alan Sterna448e4d2012-04-03 15:24:30 -0400269 set_bit(wIndex-1, &ehci->resuming_ports);
Benoit Goby79ad3b52011-03-09 16:28:56 -0800270
271 spin_unlock_irqrestore(&ehci->lock, flags);
272 msleep(20);
273 spin_lock_irqsave(&ehci->lock, flags);
274
275 /* Poll until the controller clears RESUME and SUSPEND */
Manjunath Goudar2f3a6b82013-06-13 11:24:09 -0600276 if (ehci_handshake(ehci, status_reg, PORT_RESUME, 0, 2000))
Benoit Goby79ad3b52011-03-09 16:28:56 -0800277 pr_err("%s: timeout waiting for RESUME\n", __func__);
Manjunath Goudar2f3a6b82013-06-13 11:24:09 -0600278 if (ehci_handshake(ehci, status_reg, PORT_SUSPEND, 0, 2000))
Benoit Goby79ad3b52011-03-09 16:28:56 -0800279 pr_err("%s: timeout waiting for SUSPEND\n", __func__);
280
281 ehci->reset_done[wIndex-1] = 0;
Alan Sterna448e4d2012-04-03 15:24:30 -0400282 clear_bit(wIndex-1, &ehci->resuming_ports);
Benoit Goby79ad3b52011-03-09 16:28:56 -0800283
284 tegra->port_resuming = 1;
285 goto done;
286 }
287
288 spin_unlock_irqrestore(&ehci->lock, flags);
289
290 /* Handle the hub control events here */
Laurent Pinchart37769932014-04-16 18:00:10 +0200291 return ehci_hub_control(hcd, typeReq, wValue, wIndex, buf, wLength);
Manjunath Goudar9fc5f242013-06-13 11:24:12 -0600292
Benoit Goby79ad3b52011-03-09 16:28:56 -0800293done:
294 spin_unlock_irqrestore(&ehci->lock, flags);
295 return retval;
296}
297
Venu Byravarasufe375772012-04-05 11:25:30 +0530298struct dma_aligned_buffer {
Robert Morellfbf98652011-03-09 16:28:57 -0800299 void *kmalloc_ptr;
300 void *old_xfer_buffer;
301 u8 data[0];
302};
303
Venu Byravarasufe375772012-04-05 11:25:30 +0530304static void free_dma_aligned_buffer(struct urb *urb)
Robert Morellfbf98652011-03-09 16:28:57 -0800305{
Venu Byravarasufe375772012-04-05 11:25:30 +0530306 struct dma_aligned_buffer *temp;
Robert Morellfbf98652011-03-09 16:28:57 -0800307
308 if (!(urb->transfer_flags & URB_ALIGNED_TEMP_BUFFER))
309 return;
310
Venu Byravarasufe375772012-04-05 11:25:30 +0530311 temp = container_of(urb->transfer_buffer,
312 struct dma_aligned_buffer, data);
Robert Morellfbf98652011-03-09 16:28:57 -0800313
Venu Byravarasufe375772012-04-05 11:25:30 +0530314 if (usb_urb_dir_in(urb))
Robert Morellfbf98652011-03-09 16:28:57 -0800315 memcpy(temp->old_xfer_buffer, temp->data,
316 urb->transfer_buffer_length);
317 urb->transfer_buffer = temp->old_xfer_buffer;
318 kfree(temp->kmalloc_ptr);
319
320 urb->transfer_flags &= ~URB_ALIGNED_TEMP_BUFFER;
321}
322
Venu Byravarasufe375772012-04-05 11:25:30 +0530323static int alloc_dma_aligned_buffer(struct urb *urb, gfp_t mem_flags)
Robert Morellfbf98652011-03-09 16:28:57 -0800324{
Venu Byravarasufe375772012-04-05 11:25:30 +0530325 struct dma_aligned_buffer *temp, *kmalloc_ptr;
Robert Morellfbf98652011-03-09 16:28:57 -0800326 size_t kmalloc_size;
327
328 if (urb->num_sgs || urb->sg ||
329 urb->transfer_buffer_length == 0 ||
330 !((uintptr_t)urb->transfer_buffer & (TEGRA_USB_DMA_ALIGN - 1)))
331 return 0;
332
Robert Morellfbf98652011-03-09 16:28:57 -0800333 /* Allocate a buffer with enough padding for alignment */
334 kmalloc_size = urb->transfer_buffer_length +
Venu Byravarasufe375772012-04-05 11:25:30 +0530335 sizeof(struct dma_aligned_buffer) + TEGRA_USB_DMA_ALIGN - 1;
Robert Morellfbf98652011-03-09 16:28:57 -0800336
337 kmalloc_ptr = kmalloc(kmalloc_size, mem_flags);
338 if (!kmalloc_ptr)
339 return -ENOMEM;
340
Venu Byravarasufe375772012-04-05 11:25:30 +0530341 /* Position our struct dma_aligned_buffer such that data is aligned */
Robert Morellfbf98652011-03-09 16:28:57 -0800342 temp = PTR_ALIGN(kmalloc_ptr + 1, TEGRA_USB_DMA_ALIGN) - 1;
Robert Morellfbf98652011-03-09 16:28:57 -0800343 temp->kmalloc_ptr = kmalloc_ptr;
344 temp->old_xfer_buffer = urb->transfer_buffer;
Venu Byravarasufe375772012-04-05 11:25:30 +0530345 if (usb_urb_dir_out(urb))
Robert Morellfbf98652011-03-09 16:28:57 -0800346 memcpy(temp->data, urb->transfer_buffer,
347 urb->transfer_buffer_length);
348 urb->transfer_buffer = temp->data;
349
350 urb->transfer_flags |= URB_ALIGNED_TEMP_BUFFER;
351
352 return 0;
353}
354
355static int tegra_ehci_map_urb_for_dma(struct usb_hcd *hcd, struct urb *urb,
356 gfp_t mem_flags)
357{
358 int ret;
359
Venu Byravarasufe375772012-04-05 11:25:30 +0530360 ret = alloc_dma_aligned_buffer(urb, mem_flags);
Robert Morellfbf98652011-03-09 16:28:57 -0800361 if (ret)
362 return ret;
363
364 ret = usb_hcd_map_urb_for_dma(hcd, urb, mem_flags);
365 if (ret)
Venu Byravarasufe375772012-04-05 11:25:30 +0530366 free_dma_aligned_buffer(urb);
Robert Morellfbf98652011-03-09 16:28:57 -0800367
368 return ret;
369}
370
371static void tegra_ehci_unmap_urb_for_dma(struct usb_hcd *hcd, struct urb *urb)
372{
373 usb_hcd_unmap_urb_for_dma(hcd, urb);
Venu Byravarasufe375772012-04-05 11:25:30 +0530374 free_dma_aligned_buffer(urb);
Robert Morellfbf98652011-03-09 16:28:57 -0800375}
376
Tuomas Tynkkynen327d8b42013-08-12 16:06:54 +0300377static const struct tegra_ehci_soc_config tegra30_soc_config = {
378 .has_hostpc = true,
379};
380
381static const struct tegra_ehci_soc_config tegra20_soc_config = {
382 .has_hostpc = false,
383};
384
Jingoo Han1b450492014-06-18 13:37:24 +0900385static const struct of_device_id tegra_ehci_of_match[] = {
Tuomas Tynkkynen327d8b42013-08-12 16:06:54 +0300386 { .compatible = "nvidia,tegra30-ehci", .data = &tegra30_soc_config },
387 { .compatible = "nvidia,tegra20-ehci", .data = &tegra20_soc_config },
388 { },
389};
390
Benoit Goby79ad3b52011-03-09 16:28:56 -0800391static int tegra_ehci_probe(struct platform_device *pdev)
392{
Tuomas Tynkkynen327d8b42013-08-12 16:06:54 +0300393 const struct of_device_id *match;
394 const struct tegra_ehci_soc_config *soc_config;
Benoit Goby79ad3b52011-03-09 16:28:56 -0800395 struct resource *res;
396 struct usb_hcd *hcd;
Stephen Warrenc19d14d2013-06-13 11:24:13 -0600397 struct ehci_hcd *ehci;
Benoit Goby79ad3b52011-03-09 16:28:56 -0800398 struct tegra_ehci_hcd *tegra;
Benoit Goby79ad3b52011-03-09 16:28:56 -0800399 int err = 0;
400 int irq;
Venu Byravarasubbdabdb2013-01-17 20:15:37 +0000401 struct usb_phy *u_phy;
Benoit Goby79ad3b52011-03-09 16:28:56 -0800402
Tuomas Tynkkynen327d8b42013-08-12 16:06:54 +0300403 match = of_match_device(tegra_ehci_of_match, &pdev->dev);
404 if (!match) {
405 dev_err(&pdev->dev, "Error: No device match found\n");
406 return -ENODEV;
407 }
408 soc_config = match->data;
409
Olof Johansson4a53f4e2011-11-04 09:12:40 +0000410 /* Right now device-tree probed devices don't get dma_mask set.
411 * Since shared usb code relies on it, set it here for now.
412 * Once we have dma capability bindings this can go away.
413 */
Russell Kinge1fd7342013-06-27 12:36:37 +0100414 err = dma_coerce_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
Russell King22d9d8e2013-06-10 16:28:49 +0100415 if (err)
416 return err;
Olof Johansson4a53f4e2011-11-04 09:12:40 +0000417
Stephen Warrenc19d14d2013-06-13 11:24:13 -0600418 hcd = usb_create_hcd(&tegra_ehci_hc_driver, &pdev->dev,
419 dev_name(&pdev->dev));
420 if (!hcd) {
421 dev_err(&pdev->dev, "Unable to create HCD\n");
Mikko Perttunenf5b8c8b2013-07-17 10:37:49 +0300422 return -ENOMEM;
Stephen Warrenc19d14d2013-06-13 11:24:13 -0600423 }
424 platform_set_drvdata(pdev, hcd);
425 ehci = hcd_to_ehci(hcd);
426 tegra = (struct tegra_ehci_hcd *)ehci->priv;
427
428 hcd->has_tt = 1;
Benoit Goby79ad3b52011-03-09 16:28:56 -0800429
Julia Lawallbc2ff982012-07-30 16:43:41 +0200430 tegra->clk = devm_clk_get(&pdev->dev, NULL);
Benoit Goby79ad3b52011-03-09 16:28:56 -0800431 if (IS_ERR(tegra->clk)) {
432 dev_err(&pdev->dev, "Can't get ehci clock\n");
Stephen Warrenc19d14d2013-06-13 11:24:13 -0600433 err = PTR_ERR(tegra->clk);
434 goto cleanup_hcd_create;
Benoit Goby79ad3b52011-03-09 16:28:56 -0800435 }
436
Stephen Warren75606f52013-11-06 16:53:58 -0700437 tegra->rst = devm_reset_control_get(&pdev->dev, "usb");
438 if (IS_ERR(tegra->rst)) {
439 dev_err(&pdev->dev, "Can't get ehci reset\n");
440 err = PTR_ERR(tegra->rst);
441 goto cleanup_hcd_create;
442 }
443
Prashant Gaikwad20de12c2012-06-05 09:59:38 +0530444 err = clk_prepare_enable(tegra->clk);
Benoit Goby79ad3b52011-03-09 16:28:56 -0800445 if (err)
Wei Yongjundafbe922013-09-27 16:22:08 +0800446 goto cleanup_hcd_create;
Benoit Goby79ad3b52011-03-09 16:28:56 -0800447
Tuomas Tynkkynena47cc242014-07-04 04:09:38 +0300448 err = tegra_reset_usb_controller(pdev);
449 if (err)
450 goto cleanup_clk_en;
Venu Byravarasueb5369e2013-04-03 16:11:12 +0530451
Tuomas Tynkkynen7db71a92013-07-25 21:38:06 +0300452 u_phy = devm_usb_get_phy_by_phandle(&pdev->dev, "nvidia,phy", 0);
Venu Byravarasu2d22b422013-05-16 19:43:02 +0530453 if (IS_ERR(u_phy)) {
454 err = PTR_ERR(u_phy);
Stephen Warrenc19d14d2013-06-13 11:24:13 -0600455 goto cleanup_clk_en;
Venu Byravarasu2d22b422013-05-16 19:43:02 +0530456 }
Antoine Tenart3d46e732014-09-24 23:05:50 +0400457 hcd->usb_phy = u_phy;
Venu Byravarasu2d22b422013-05-16 19:43:02 +0530458
Venu Byravarasu585355c2012-12-13 20:59:08 +0000459 tegra->needs_double_reset = of_property_read_bool(pdev->dev.of_node,
460 "nvidia,needs-double-reset");
461
Benoit Goby79ad3b52011-03-09 16:28:56 -0800462 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
463 if (!res) {
464 dev_err(&pdev->dev, "Failed to get I/O memory\n");
465 err = -ENXIO;
Stephen Warrenc19d14d2013-06-13 11:24:13 -0600466 goto cleanup_clk_en;
Benoit Goby79ad3b52011-03-09 16:28:56 -0800467 }
468 hcd->rsrc_start = res->start;
469 hcd->rsrc_len = resource_size(res);
Vivek Gautam6ba96dc2014-05-10 17:30:09 +0530470 hcd->regs = devm_ioremap_resource(&pdev->dev, res);
471 if (IS_ERR(hcd->regs)) {
472 err = PTR_ERR(hcd->regs);
Stephen Warrenc19d14d2013-06-13 11:24:13 -0600473 goto cleanup_clk_en;
Benoit Goby79ad3b52011-03-09 16:28:56 -0800474 }
Stephen Warrenc19d14d2013-06-13 11:24:13 -0600475 ehci->caps = hcd->regs + 0x100;
Tuomas Tynkkynen327d8b42013-08-12 16:06:54 +0300476 ehci->has_hostpc = soc_config->has_hostpc;
Benoit Goby79ad3b52011-03-09 16:28:56 -0800477
Antoine Tenart3d46e732014-09-24 23:05:50 +0400478 err = usb_phy_init(hcd->usb_phy);
Venu Byravarasu2d22b422013-05-16 19:43:02 +0530479 if (err) {
480 dev_err(&pdev->dev, "Failed to initialize phy\n");
Stephen Warrenc19d14d2013-06-13 11:24:13 -0600481 goto cleanup_clk_en;
Olof Johansson4a53f4e2011-11-04 09:12:40 +0000482 }
483
Venu Byravarasubbdabdb2013-01-17 20:15:37 +0000484 u_phy->otg = devm_kzalloc(&pdev->dev, sizeof(struct usb_otg),
485 GFP_KERNEL);
486 if (!u_phy->otg) {
487 dev_err(&pdev->dev, "Failed to alloc memory for otg\n");
488 err = -ENOMEM;
Venu Byravarasu2d22b422013-05-16 19:43:02 +0530489 goto cleanup_phy;
Venu Byravarasubbdabdb2013-01-17 20:15:37 +0000490 }
491 u_phy->otg->host = hcd_to_bus(hcd);
492
Antoine Tenart3d46e732014-09-24 23:05:50 +0400493 err = usb_phy_set_suspend(hcd->usb_phy, 0);
Benoit Goby79ad3b52011-03-09 16:28:56 -0800494 if (err) {
495 dev_err(&pdev->dev, "Failed to power on the phy\n");
Venu Byravarasu2d22b422013-05-16 19:43:02 +0530496 goto cleanup_phy;
Benoit Goby79ad3b52011-03-09 16:28:56 -0800497 }
498
Benoit Goby79ad3b52011-03-09 16:28:56 -0800499 irq = platform_get_irq(pdev, 0);
500 if (!irq) {
501 dev_err(&pdev->dev, "Failed to get IRQ\n");
502 err = -ENODEV;
Venu Byravarasu2d22b422013-05-16 19:43:02 +0530503 goto cleanup_phy;
Benoit Goby79ad3b52011-03-09 16:28:56 -0800504 }
Benoit Goby79ad3b52011-03-09 16:28:56 -0800505
Tuomas Tynkkynende3f2332013-07-25 21:38:02 +0300506 otg_set_host(u_phy->otg, &hcd->self);
Benoit Goby79ad3b52011-03-09 16:28:56 -0800507
Yong Zhangb5dd18d2011-09-07 16:10:52 +0800508 err = usb_add_hcd(hcd, irq, IRQF_SHARED);
Benoit Goby79ad3b52011-03-09 16:28:56 -0800509 if (err) {
510 dev_err(&pdev->dev, "Failed to add USB HCD\n");
Tuomas Tynkkynende3f2332013-07-25 21:38:02 +0300511 goto cleanup_otg_set_host;
Benoit Goby79ad3b52011-03-09 16:28:56 -0800512 }
Peter Chen3c9740a2013-11-05 10:46:02 +0800513 device_wakeup_enable(hcd->self.controller);
Benoit Goby79ad3b52011-03-09 16:28:56 -0800514
515 return err;
516
Tuomas Tynkkynende3f2332013-07-25 21:38:02 +0300517cleanup_otg_set_host:
518 otg_set_host(u_phy->otg, NULL);
Thierry Reding8fefcfd2013-06-14 13:21:21 +0200519cleanup_phy:
Antoine Tenart3d46e732014-09-24 23:05:50 +0400520 usb_phy_shutdown(hcd->usb_phy);
Stephen Warrenc19d14d2013-06-13 11:24:13 -0600521cleanup_clk_en:
522 clk_disable_unprepare(tegra->clk);
Venu Byravarasu2d22b422013-05-16 19:43:02 +0530523cleanup_hcd_create:
Benoit Goby79ad3b52011-03-09 16:28:56 -0800524 usb_put_hcd(hcd);
Benoit Goby79ad3b52011-03-09 16:28:56 -0800525 return err;
526}
527
Benoit Goby79ad3b52011-03-09 16:28:56 -0800528static int tegra_ehci_remove(struct platform_device *pdev)
529{
Stephen Warrenc19d14d2013-06-13 11:24:13 -0600530 struct usb_hcd *hcd = platform_get_drvdata(pdev);
531 struct tegra_ehci_hcd *tegra =
532 (struct tegra_ehci_hcd *)hcd_to_ehci(hcd)->priv;
Benoit Goby79ad3b52011-03-09 16:28:56 -0800533
Antoine Tenart3d46e732014-09-24 23:05:50 +0400534 otg_set_host(hcd->usb_phy->otg, NULL);
Benoit Goby79ad3b52011-03-09 16:28:56 -0800535
Antoine Tenart3d46e732014-09-24 23:05:50 +0400536 usb_phy_shutdown(hcd->usb_phy);
Benoit Goby79ad3b52011-03-09 16:28:56 -0800537 usb_remove_hcd(hcd);
Venu Byravarasuecc8a0c2012-08-10 11:42:43 +0530538
Prashant Gaikwad20de12c2012-06-05 09:59:38 +0530539 clk_disable_unprepare(tegra->clk);
Benoit Goby79ad3b52011-03-09 16:28:56 -0800540
Tuomas Tynkkynen6a70b622014-06-17 17:17:40 +0300541 usb_put_hcd(hcd);
542
Benoit Goby79ad3b52011-03-09 16:28:56 -0800543 return 0;
544}
545
546static void tegra_ehci_hcd_shutdown(struct platform_device *pdev)
547{
Stephen Warrenc19d14d2013-06-13 11:24:13 -0600548 struct usb_hcd *hcd = platform_get_drvdata(pdev);
Benoit Goby79ad3b52011-03-09 16:28:56 -0800549
550 if (hcd->driver->shutdown)
551 hcd->driver->shutdown(hcd);
552}
553
554static struct platform_driver tegra_ehci_driver = {
555 .probe = tegra_ehci_probe,
556 .remove = tegra_ehci_remove,
Benoit Goby79ad3b52011-03-09 16:28:56 -0800557 .shutdown = tegra_ehci_hcd_shutdown,
558 .driver = {
Manjunath Goudar9fc5f242013-06-13 11:24:12 -0600559 .name = DRV_NAME,
Olof Johansson4a53f4e2011-11-04 09:12:40 +0000560 .of_match_table = tegra_ehci_of_match,
Benoit Goby79ad3b52011-03-09 16:28:56 -0800561 }
562};
Manjunath Goudar9fc5f242013-06-13 11:24:12 -0600563
Stephen Warren4f2fe2d2014-04-14 15:21:23 -0600564static int tegra_ehci_reset(struct usb_hcd *hcd)
565{
566 struct ehci_hcd *ehci = hcd_to_ehci(hcd);
567 int retval;
568 int txfifothresh;
569
570 retval = ehci_setup(hcd);
571 if (retval)
572 return retval;
573
574 /*
575 * We should really pull this value out of tegra_ehci_soc_config, but
576 * to avoid needing access to it, make use of the fact that Tegra20 is
577 * the only one so far that needs a value of 10, and Tegra20 is the
578 * only one which doesn't set has_hostpc.
579 */
580 txfifothresh = ehci->has_hostpc ? 0x10 : 10;
581 ehci_writel(ehci, txfifothresh << 16, &ehci->regs->txfill_tuning);
582
583 return 0;
584}
585
Manjunath Goudar9fc5f242013-06-13 11:24:12 -0600586static const struct ehci_driver_overrides tegra_overrides __initconst = {
587 .extra_priv_size = sizeof(struct tegra_ehci_hcd),
Stephen Warren4f2fe2d2014-04-14 15:21:23 -0600588 .reset = tegra_ehci_reset,
Manjunath Goudar9fc5f242013-06-13 11:24:12 -0600589};
590
591static int __init ehci_tegra_init(void)
592{
593 if (usb_disabled())
594 return -ENODEV;
595
596 pr_info(DRV_NAME ": " DRIVER_DESC "\n");
597
598 ehci_init_driver(&tegra_ehci_hc_driver, &tegra_overrides);
599
600 /*
601 * The Tegra HW has some unusual quirks, which require Tegra-specific
602 * workarounds. We override certain hc_driver functions here to
603 * achieve that. We explicitly do not enhance ehci_driver_overrides to
604 * allow this more easily, since this is an unusual case, and we don't
605 * want to encourage others to override these functions by making it
606 * too easy.
607 */
608
Manjunath Goudar9fc5f242013-06-13 11:24:12 -0600609 tegra_ehci_hc_driver.map_urb_for_dma = tegra_ehci_map_urb_for_dma;
610 tegra_ehci_hc_driver.unmap_urb_for_dma = tegra_ehci_unmap_urb_for_dma;
611 tegra_ehci_hc_driver.hub_control = tegra_ehci_hub_control;
612
613 return platform_driver_register(&tegra_ehci_driver);
614}
615module_init(ehci_tegra_init);
616
617static void __exit ehci_tegra_cleanup(void)
618{
619 platform_driver_unregister(&tegra_ehci_driver);
620}
621module_exit(ehci_tegra_cleanup);
622
623MODULE_DESCRIPTION(DRIVER_DESC);
624MODULE_LICENSE("GPL");
625MODULE_ALIAS("platform:" DRV_NAME);
626MODULE_DEVICE_TABLE(of, tegra_ehci_of_match);