Joerg Roedel | 8d283c3 | 2008-06-26 21:27:38 +0200 | [diff] [blame] | 1 | /* |
Joerg Roedel | 5d0d715 | 2010-10-13 11:13:21 +0200 | [diff] [blame] | 2 | * Copyright (C) 2007-2010 Advanced Micro Devices, Inc. |
Joerg Roedel | 63ce3ae | 2015-02-04 16:12:55 +0100 | [diff] [blame] | 3 | * Author: Joerg Roedel <jroedel@suse.de> |
Joerg Roedel | 8d283c3 | 2008-06-26 21:27:38 +0200 | [diff] [blame] | 4 | * Leo Duran <leo.duran@amd.com> |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify it |
| 7 | * under the terms of the GNU General Public License version 2 as published |
| 8 | * by the Free Software Foundation. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
| 14 | * |
| 15 | * You should have received a copy of the GNU General Public License |
| 16 | * along with this program; if not, write to the Free Software |
| 17 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
| 18 | */ |
| 19 | |
H. Peter Anvin | 1965aae | 2008-10-22 22:26:29 -0700 | [diff] [blame] | 20 | #ifndef _ASM_X86_AMD_IOMMU_TYPES_H |
| 21 | #define _ASM_X86_AMD_IOMMU_TYPES_H |
Joerg Roedel | 8d283c3 | 2008-06-26 21:27:38 +0200 | [diff] [blame] | 22 | |
| 23 | #include <linux/types.h> |
Joerg Roedel | 5d214fe | 2010-02-08 14:44:49 +0100 | [diff] [blame] | 24 | #include <linux/mutex.h> |
Joerg Roedel | 8d283c3 | 2008-06-26 21:27:38 +0200 | [diff] [blame] | 25 | #include <linux/list.h> |
| 26 | #include <linux/spinlock.h> |
Shuah Khan | c5081cd | 2013-02-27 17:07:19 -0700 | [diff] [blame] | 27 | #include <linux/pci.h> |
Bjorn Helgaas | 4b180d9 | 2014-02-14 14:08:51 -0700 | [diff] [blame] | 28 | #include <linux/irqreturn.h> |
Joerg Roedel | 8d283c3 | 2008-06-26 21:27:38 +0200 | [diff] [blame] | 29 | |
| 30 | /* |
Joerg Roedel | bb52777 | 2009-11-20 14:31:51 +0100 | [diff] [blame] | 31 | * Maximum number of IOMMUs supported |
| 32 | */ |
| 33 | #define MAX_IOMMUS 32 |
| 34 | |
| 35 | /* |
Joerg Roedel | 8d283c3 | 2008-06-26 21:27:38 +0200 | [diff] [blame] | 36 | * some size calculation constants |
| 37 | */ |
Joerg Roedel | 83f5aac | 2008-07-11 17:14:34 +0200 | [diff] [blame] | 38 | #define DEV_TABLE_ENTRY_SIZE 32 |
Joerg Roedel | 8d283c3 | 2008-06-26 21:27:38 +0200 | [diff] [blame] | 39 | #define ALIAS_TABLE_ENTRY_SIZE 2 |
| 40 | #define RLOOKUP_TABLE_ENTRY_SIZE (sizeof(void *)) |
| 41 | |
Joerg Roedel | 8d283c3 | 2008-06-26 21:27:38 +0200 | [diff] [blame] | 42 | /* Capability offsets used by the driver */ |
| 43 | #define MMIO_CAP_HDR_OFFSET 0x00 |
| 44 | #define MMIO_RANGE_OFFSET 0x0c |
Joerg Roedel | a80dc3e | 2008-09-11 16:51:41 +0200 | [diff] [blame] | 45 | #define MMIO_MISC_OFFSET 0x10 |
Joerg Roedel | 8d283c3 | 2008-06-26 21:27:38 +0200 | [diff] [blame] | 46 | |
| 47 | /* Masks, shifts and macros to parse the device range capability */ |
| 48 | #define MMIO_RANGE_LD_MASK 0xff000000 |
| 49 | #define MMIO_RANGE_FD_MASK 0x00ff0000 |
| 50 | #define MMIO_RANGE_BUS_MASK 0x0000ff00 |
| 51 | #define MMIO_RANGE_LD_SHIFT 24 |
| 52 | #define MMIO_RANGE_FD_SHIFT 16 |
| 53 | #define MMIO_RANGE_BUS_SHIFT 8 |
| 54 | #define MMIO_GET_LD(x) (((x) & MMIO_RANGE_LD_MASK) >> MMIO_RANGE_LD_SHIFT) |
| 55 | #define MMIO_GET_FD(x) (((x) & MMIO_RANGE_FD_MASK) >> MMIO_RANGE_FD_SHIFT) |
| 56 | #define MMIO_GET_BUS(x) (((x) & MMIO_RANGE_BUS_MASK) >> MMIO_RANGE_BUS_SHIFT) |
Joerg Roedel | a80dc3e | 2008-09-11 16:51:41 +0200 | [diff] [blame] | 57 | #define MMIO_MSI_NUM(x) ((x) & 0x1f) |
Joerg Roedel | 8d283c3 | 2008-06-26 21:27:38 +0200 | [diff] [blame] | 58 | |
| 59 | /* Flag masks for the AMD IOMMU exclusion range */ |
| 60 | #define MMIO_EXCL_ENABLE_MASK 0x01ULL |
| 61 | #define MMIO_EXCL_ALLOW_MASK 0x02ULL |
| 62 | |
| 63 | /* Used offsets into the MMIO space */ |
| 64 | #define MMIO_DEV_TABLE_OFFSET 0x0000 |
| 65 | #define MMIO_CMD_BUF_OFFSET 0x0008 |
| 66 | #define MMIO_EVT_BUF_OFFSET 0x0010 |
| 67 | #define MMIO_CONTROL_OFFSET 0x0018 |
| 68 | #define MMIO_EXCL_BASE_OFFSET 0x0020 |
| 69 | #define MMIO_EXCL_LIMIT_OFFSET 0x0028 |
Joerg Roedel | d99ddec | 2011-04-11 11:03:18 +0200 | [diff] [blame] | 70 | #define MMIO_EXT_FEATURES 0x0030 |
Joerg Roedel | 1a29ac0 | 2011-11-10 15:41:40 +0100 | [diff] [blame] | 71 | #define MMIO_PPR_LOG_OFFSET 0x0038 |
Joerg Roedel | 8d283c3 | 2008-06-26 21:27:38 +0200 | [diff] [blame] | 72 | #define MMIO_CMD_HEAD_OFFSET 0x2000 |
| 73 | #define MMIO_CMD_TAIL_OFFSET 0x2008 |
| 74 | #define MMIO_EVT_HEAD_OFFSET 0x2010 |
| 75 | #define MMIO_EVT_TAIL_OFFSET 0x2018 |
| 76 | #define MMIO_STATUS_OFFSET 0x2020 |
Joerg Roedel | 1a29ac0 | 2011-11-10 15:41:40 +0100 | [diff] [blame] | 77 | #define MMIO_PPR_HEAD_OFFSET 0x2030 |
| 78 | #define MMIO_PPR_TAIL_OFFSET 0x2038 |
Steven L Kinney | 30861dd | 2013-06-05 16:11:48 -0500 | [diff] [blame] | 79 | #define MMIO_CNTR_CONF_OFFSET 0x4000 |
| 80 | #define MMIO_CNTR_REG_OFFSET 0x40000 |
| 81 | #define MMIO_REG_END_OFFSET 0x80000 |
| 82 | |
Joerg Roedel | 8d283c3 | 2008-06-26 21:27:38 +0200 | [diff] [blame] | 83 | |
Joerg Roedel | d99ddec | 2011-04-11 11:03:18 +0200 | [diff] [blame] | 84 | |
| 85 | /* Extended Feature Bits */ |
| 86 | #define FEATURE_PREFETCH (1ULL<<0) |
| 87 | #define FEATURE_PPR (1ULL<<1) |
| 88 | #define FEATURE_X2APIC (1ULL<<2) |
| 89 | #define FEATURE_NX (1ULL<<3) |
| 90 | #define FEATURE_GT (1ULL<<4) |
| 91 | #define FEATURE_IA (1ULL<<6) |
| 92 | #define FEATURE_GA (1ULL<<7) |
| 93 | #define FEATURE_HE (1ULL<<8) |
| 94 | #define FEATURE_PC (1ULL<<9) |
| 95 | |
Joerg Roedel | 62f71ab | 2011-11-10 14:41:57 +0100 | [diff] [blame] | 96 | #define FEATURE_PASID_SHIFT 32 |
| 97 | #define FEATURE_PASID_MASK (0x1fULL << FEATURE_PASID_SHIFT) |
| 98 | |
Joerg Roedel | 52815b7 | 2011-11-17 17:24:28 +0100 | [diff] [blame] | 99 | #define FEATURE_GLXVAL_SHIFT 14 |
| 100 | #define FEATURE_GLXVAL_MASK (0x03ULL << FEATURE_GLXVAL_SHIFT) |
| 101 | |
Suravee Suthikulpanit | a919a01 | 2014-03-05 18:54:18 -0600 | [diff] [blame] | 102 | /* Note: |
| 103 | * The current driver only support 16-bit PASID. |
| 104 | * Currently, hardware only implement upto 16-bit PASID |
| 105 | * even though the spec says it could have upto 20 bits. |
| 106 | */ |
| 107 | #define PASID_MASK 0x0000ffff |
Joerg Roedel | 52815b7 | 2011-11-17 17:24:28 +0100 | [diff] [blame] | 108 | |
Joerg Roedel | 519c31b | 2008-08-14 19:55:15 +0200 | [diff] [blame] | 109 | /* MMIO status bits */ |
Suravee Suthikulpanit | 925fe08 | 2013-03-27 18:51:52 -0500 | [diff] [blame] | 110 | #define MMIO_STATUS_EVT_INT_MASK (1 << 1) |
Joerg Roedel | 72e1dcc | 2011-11-10 19:13:51 +0100 | [diff] [blame] | 111 | #define MMIO_STATUS_COM_WAIT_INT_MASK (1 << 2) |
| 112 | #define MMIO_STATUS_PPR_INT_MASK (1 << 6) |
Joerg Roedel | 519c31b | 2008-08-14 19:55:15 +0200 | [diff] [blame] | 113 | |
Joerg Roedel | 90008ee | 2008-09-09 16:41:05 +0200 | [diff] [blame] | 114 | /* event logging constants */ |
| 115 | #define EVENT_ENTRY_SIZE 0x10 |
| 116 | #define EVENT_TYPE_SHIFT 28 |
| 117 | #define EVENT_TYPE_MASK 0xf |
| 118 | #define EVENT_TYPE_ILL_DEV 0x1 |
| 119 | #define EVENT_TYPE_IO_FAULT 0x2 |
| 120 | #define EVENT_TYPE_DEV_TAB_ERR 0x3 |
| 121 | #define EVENT_TYPE_PAGE_TAB_ERR 0x4 |
| 122 | #define EVENT_TYPE_ILL_CMD 0x5 |
| 123 | #define EVENT_TYPE_CMD_HARD_ERR 0x6 |
| 124 | #define EVENT_TYPE_IOTLB_INV_TO 0x7 |
| 125 | #define EVENT_TYPE_INV_DEV_REQ 0x8 |
| 126 | #define EVENT_DEVID_MASK 0xffff |
| 127 | #define EVENT_DEVID_SHIFT 0 |
| 128 | #define EVENT_DOMID_MASK 0xffff |
| 129 | #define EVENT_DOMID_SHIFT 0 |
| 130 | #define EVENT_FLAGS_MASK 0xfff |
| 131 | #define EVENT_FLAGS_SHIFT 0x10 |
| 132 | |
Joerg Roedel | 8d283c3 | 2008-06-26 21:27:38 +0200 | [diff] [blame] | 133 | /* feature control bits */ |
| 134 | #define CONTROL_IOMMU_EN 0x00ULL |
| 135 | #define CONTROL_HT_TUN_EN 0x01ULL |
| 136 | #define CONTROL_EVT_LOG_EN 0x02ULL |
| 137 | #define CONTROL_EVT_INT_EN 0x03ULL |
| 138 | #define CONTROL_COMWAIT_EN 0x04ULL |
Joerg Roedel | 1456e9d | 2011-12-22 14:51:53 +0100 | [diff] [blame] | 139 | #define CONTROL_INV_TIMEOUT 0x05ULL |
Joerg Roedel | 8d283c3 | 2008-06-26 21:27:38 +0200 | [diff] [blame] | 140 | #define CONTROL_PASSPW_EN 0x08ULL |
| 141 | #define CONTROL_RESPASSPW_EN 0x09ULL |
| 142 | #define CONTROL_COHERENT_EN 0x0aULL |
| 143 | #define CONTROL_ISOC_EN 0x0bULL |
| 144 | #define CONTROL_CMDBUF_EN 0x0cULL |
| 145 | #define CONTROL_PPFLOG_EN 0x0dULL |
| 146 | #define CONTROL_PPFINT_EN 0x0eULL |
Joerg Roedel | 1a29ac0 | 2011-11-10 15:41:40 +0100 | [diff] [blame] | 147 | #define CONTROL_PPR_EN 0x0fULL |
Joerg Roedel | cbc33a9 | 2011-11-25 11:41:31 +0100 | [diff] [blame] | 148 | #define CONTROL_GT_EN 0x10ULL |
Joerg Roedel | 8d283c3 | 2008-06-26 21:27:38 +0200 | [diff] [blame] | 149 | |
Joerg Roedel | 1456e9d | 2011-12-22 14:51:53 +0100 | [diff] [blame] | 150 | #define CTRL_INV_TO_MASK (7 << CONTROL_INV_TIMEOUT) |
| 151 | #define CTRL_INV_TO_NONE 0 |
| 152 | #define CTRL_INV_TO_1MS 1 |
| 153 | #define CTRL_INV_TO_10MS 2 |
| 154 | #define CTRL_INV_TO_100MS 3 |
| 155 | #define CTRL_INV_TO_1S 4 |
| 156 | #define CTRL_INV_TO_10S 5 |
| 157 | #define CTRL_INV_TO_100S 6 |
| 158 | |
Joerg Roedel | 8d283c3 | 2008-06-26 21:27:38 +0200 | [diff] [blame] | 159 | /* command specific defines */ |
| 160 | #define CMD_COMPL_WAIT 0x01 |
| 161 | #define CMD_INV_DEV_ENTRY 0x02 |
Joerg Roedel | cb41ed8 | 2011-04-05 11:00:53 +0200 | [diff] [blame] | 162 | #define CMD_INV_IOMMU_PAGES 0x03 |
| 163 | #define CMD_INV_IOTLB_PAGES 0x04 |
Joerg Roedel | 7ef2798 | 2012-06-21 16:46:04 +0200 | [diff] [blame] | 164 | #define CMD_INV_IRT 0x05 |
Joerg Roedel | c99afa2 | 2011-11-21 18:19:25 +0100 | [diff] [blame] | 165 | #define CMD_COMPLETE_PPR 0x07 |
Joerg Roedel | 58fc7f1 | 2011-04-11 11:13:24 +0200 | [diff] [blame] | 166 | #define CMD_INV_ALL 0x08 |
Joerg Roedel | 8d283c3 | 2008-06-26 21:27:38 +0200 | [diff] [blame] | 167 | |
| 168 | #define CMD_COMPL_WAIT_STORE_MASK 0x01 |
Joerg Roedel | 519c31b | 2008-08-14 19:55:15 +0200 | [diff] [blame] | 169 | #define CMD_COMPL_WAIT_INT_MASK 0x02 |
Joerg Roedel | 8d283c3 | 2008-06-26 21:27:38 +0200 | [diff] [blame] | 170 | #define CMD_INV_IOMMU_PAGES_SIZE_MASK 0x01 |
| 171 | #define CMD_INV_IOMMU_PAGES_PDE_MASK 0x02 |
Joerg Roedel | 22e266c | 2011-11-21 15:59:08 +0100 | [diff] [blame] | 172 | #define CMD_INV_IOMMU_PAGES_GN_MASK 0x04 |
Joerg Roedel | 8d283c3 | 2008-06-26 21:27:38 +0200 | [diff] [blame] | 173 | |
Joerg Roedel | c99afa2 | 2011-11-21 18:19:25 +0100 | [diff] [blame] | 174 | #define PPR_STATUS_MASK 0xf |
| 175 | #define PPR_STATUS_SHIFT 12 |
| 176 | |
Joerg Roedel | 999ba41 | 2008-07-03 19:35:08 +0200 | [diff] [blame] | 177 | #define CMD_INV_IOMMU_ALL_PAGES_ADDRESS 0x7fffffffffffffffULL |
| 178 | |
Joerg Roedel | 8d283c3 | 2008-06-26 21:27:38 +0200 | [diff] [blame] | 179 | /* macros and definitions for device table entries */ |
| 180 | #define DEV_ENTRY_VALID 0x00 |
| 181 | #define DEV_ENTRY_TRANSLATION 0x01 |
| 182 | #define DEV_ENTRY_IR 0x3d |
| 183 | #define DEV_ENTRY_IW 0x3e |
Joerg Roedel | 9f5f5fb | 2008-08-14 19:55:16 +0200 | [diff] [blame] | 184 | #define DEV_ENTRY_NO_PAGE_FAULT 0x62 |
Joerg Roedel | 8d283c3 | 2008-06-26 21:27:38 +0200 | [diff] [blame] | 185 | #define DEV_ENTRY_EX 0x67 |
| 186 | #define DEV_ENTRY_SYSMGT1 0x68 |
| 187 | #define DEV_ENTRY_SYSMGT2 0x69 |
Joerg Roedel | 0ea2c42 | 2012-06-15 18:05:20 +0200 | [diff] [blame] | 188 | #define DEV_ENTRY_IRQ_TBL_EN 0x80 |
Joerg Roedel | 8d283c3 | 2008-06-26 21:27:38 +0200 | [diff] [blame] | 189 | #define DEV_ENTRY_INIT_PASS 0xb8 |
| 190 | #define DEV_ENTRY_EINT_PASS 0xb9 |
| 191 | #define DEV_ENTRY_NMI_PASS 0xba |
| 192 | #define DEV_ENTRY_LINT0_PASS 0xbe |
| 193 | #define DEV_ENTRY_LINT1_PASS 0xbf |
Joerg Roedel | 38ddf41 | 2008-09-11 10:38:32 +0200 | [diff] [blame] | 194 | #define DEV_ENTRY_MODE_MASK 0x07 |
| 195 | #define DEV_ENTRY_MODE_SHIFT 0x09 |
Joerg Roedel | 8d283c3 | 2008-06-26 21:27:38 +0200 | [diff] [blame] | 196 | |
Joerg Roedel | 7ef2798 | 2012-06-21 16:46:04 +0200 | [diff] [blame] | 197 | #define MAX_DEV_TABLE_ENTRIES 0xffff |
| 198 | |
Joerg Roedel | 8d283c3 | 2008-06-26 21:27:38 +0200 | [diff] [blame] | 199 | /* constants to configure the command buffer */ |
| 200 | #define CMD_BUFFER_SIZE 8192 |
Chris Wright | 549c90d | 2010-04-02 18:27:53 -0700 | [diff] [blame] | 201 | #define CMD_BUFFER_UNINITIALIZED 1 |
Joerg Roedel | 8d283c3 | 2008-06-26 21:27:38 +0200 | [diff] [blame] | 202 | #define CMD_BUFFER_ENTRIES 512 |
| 203 | #define MMIO_CMD_SIZE_SHIFT 56 |
| 204 | #define MMIO_CMD_SIZE_512 (0x9ULL << MMIO_CMD_SIZE_SHIFT) |
| 205 | |
Joerg Roedel | 335503e | 2008-09-05 14:29:07 +0200 | [diff] [blame] | 206 | /* constants for event buffer handling */ |
| 207 | #define EVT_BUFFER_SIZE 8192 /* 512 entries */ |
| 208 | #define EVT_LEN_MASK (0x9ULL << 56) |
| 209 | |
Joerg Roedel | 1a29ac0 | 2011-11-10 15:41:40 +0100 | [diff] [blame] | 210 | /* Constants for PPR Log handling */ |
| 211 | #define PPR_LOG_ENTRIES 512 |
| 212 | #define PPR_LOG_SIZE_SHIFT 56 |
| 213 | #define PPR_LOG_SIZE_512 (0x9ULL << PPR_LOG_SIZE_SHIFT) |
| 214 | #define PPR_ENTRY_SIZE 16 |
| 215 | #define PPR_LOG_SIZE (PPR_ENTRY_SIZE * PPR_LOG_ENTRIES) |
| 216 | |
Joerg Roedel | 72e1dcc | 2011-11-10 19:13:51 +0100 | [diff] [blame] | 217 | #define PPR_REQ_TYPE(x) (((x) >> 60) & 0xfULL) |
| 218 | #define PPR_FLAGS(x) (((x) >> 48) & 0xfffULL) |
| 219 | #define PPR_DEVID(x) ((x) & 0xffffULL) |
| 220 | #define PPR_TAG(x) (((x) >> 32) & 0x3ffULL) |
| 221 | #define PPR_PASID1(x) (((x) >> 16) & 0xffffULL) |
| 222 | #define PPR_PASID2(x) (((x) >> 42) & 0xfULL) |
| 223 | #define PPR_PASID(x) ((PPR_PASID2(x) << 16) | PPR_PASID1(x)) |
| 224 | |
| 225 | #define PPR_REQ_FAULT 0x01 |
| 226 | |
Joerg Roedel | 0feae53 | 2009-08-26 15:26:30 +0200 | [diff] [blame] | 227 | #define PAGE_MODE_NONE 0x00 |
Joerg Roedel | 8d283c3 | 2008-06-26 21:27:38 +0200 | [diff] [blame] | 228 | #define PAGE_MODE_1_LEVEL 0x01 |
| 229 | #define PAGE_MODE_2_LEVEL 0x02 |
| 230 | #define PAGE_MODE_3_LEVEL 0x03 |
Joerg Roedel | 9355a08 | 2009-09-02 14:24:08 +0200 | [diff] [blame] | 231 | #define PAGE_MODE_4_LEVEL 0x04 |
| 232 | #define PAGE_MODE_5_LEVEL 0x05 |
| 233 | #define PAGE_MODE_6_LEVEL 0x06 |
Joerg Roedel | 8d283c3 | 2008-06-26 21:27:38 +0200 | [diff] [blame] | 234 | |
Joerg Roedel | 9355a08 | 2009-09-02 14:24:08 +0200 | [diff] [blame] | 235 | #define PM_LEVEL_SHIFT(x) (12 + ((x) * 9)) |
| 236 | #define PM_LEVEL_SIZE(x) (((x) < 6) ? \ |
| 237 | ((1ULL << PM_LEVEL_SHIFT((x))) - 1): \ |
| 238 | (0xffffffffffffffffULL)) |
| 239 | #define PM_LEVEL_INDEX(x, a) (((a) >> PM_LEVEL_SHIFT((x))) & 0x1ffULL) |
Joerg Roedel | 50020fb | 2009-09-02 15:38:40 +0200 | [diff] [blame] | 240 | #define PM_LEVEL_ENC(x) (((x) << 9) & 0xe00ULL) |
| 241 | #define PM_LEVEL_PDE(x, a) ((a) | PM_LEVEL_ENC((x)) | \ |
| 242 | IOMMU_PTE_P | IOMMU_PTE_IR | IOMMU_PTE_IW) |
Joerg Roedel | a6b256b | 2009-09-03 12:21:31 +0200 | [diff] [blame] | 243 | #define PM_PTE_LEVEL(pte) (((pte) >> 9) & 0x7ULL) |
Joerg Roedel | 8d283c3 | 2008-06-26 21:27:38 +0200 | [diff] [blame] | 244 | |
Joerg Roedel | abdc5eb | 2009-09-03 11:33:51 +0200 | [diff] [blame] | 245 | #define PM_MAP_4k 0 |
| 246 | #define PM_ADDR_MASK 0x000ffffffffff000ULL |
| 247 | #define PM_MAP_MASK(lvl) (PM_ADDR_MASK & \ |
| 248 | (~((1ULL << (12 + ((lvl) * 9))) - 1))) |
| 249 | #define PM_ALIGNED(lvl, addr) ((PM_MAP_MASK(lvl) & (addr)) == (addr)) |
Joerg Roedel | 8d283c3 | 2008-06-26 21:27:38 +0200 | [diff] [blame] | 250 | |
Joerg Roedel | cbb9d72 | 2010-01-15 14:41:15 +0100 | [diff] [blame] | 251 | /* |
| 252 | * Returns the page table level to use for a given page size |
| 253 | * Pagesize is expected to be a power-of-two |
| 254 | */ |
| 255 | #define PAGE_SIZE_LEVEL(pagesize) \ |
| 256 | ((__ffs(pagesize) - 12) / 9) |
| 257 | /* |
| 258 | * Returns the number of ptes to use for a given page size |
| 259 | * Pagesize is expected to be a power-of-two |
| 260 | */ |
| 261 | #define PAGE_SIZE_PTE_COUNT(pagesize) \ |
| 262 | (1ULL << ((__ffs(pagesize) - 12) % 9)) |
| 263 | |
| 264 | /* |
| 265 | * Aligns a given io-virtual address to a given page size |
| 266 | * Pagesize is expected to be a power-of-two |
| 267 | */ |
| 268 | #define PAGE_SIZE_ALIGN(address, pagesize) \ |
| 269 | ((address) & ~((pagesize) - 1)) |
| 270 | /* |
Frank Arnold | df805ab | 2012-08-27 19:21:04 +0200 | [diff] [blame] | 271 | * Creates an IOMMU PTE for an address and a given pagesize |
Joerg Roedel | cbb9d72 | 2010-01-15 14:41:15 +0100 | [diff] [blame] | 272 | * The PTE has no permission bits set |
| 273 | * Pagesize is expected to be a power-of-two larger than 4096 |
| 274 | */ |
| 275 | #define PAGE_SIZE_PTE(address, pagesize) \ |
| 276 | (((address) | ((pagesize) - 1)) & \ |
| 277 | (~(pagesize >> 1)) & PM_ADDR_MASK) |
| 278 | |
Joerg Roedel | 24cd772 | 2010-01-19 17:27:39 +0100 | [diff] [blame] | 279 | /* |
| 280 | * Takes a PTE value with mode=0x07 and returns the page size it maps |
| 281 | */ |
| 282 | #define PTE_PAGE_SIZE(pte) \ |
| 283 | (1ULL << (1 + ffz(((pte) | 0xfffULL)))) |
| 284 | |
Joerg Roedel | 3039ca1 | 2015-04-01 14:58:48 +0200 | [diff] [blame] | 285 | /* |
| 286 | * Takes a page-table level and returns the default page-size for this level |
| 287 | */ |
| 288 | #define PTE_LEVEL_PAGE_SIZE(level) \ |
| 289 | (1ULL << (12 + (9 * (level)))) |
| 290 | |
Joerg Roedel | 8d283c3 | 2008-06-26 21:27:38 +0200 | [diff] [blame] | 291 | #define IOMMU_PTE_P (1ULL << 0) |
Joerg Roedel | 38ddf41 | 2008-09-11 10:38:32 +0200 | [diff] [blame] | 292 | #define IOMMU_PTE_TV (1ULL << 1) |
Joerg Roedel | 8d283c3 | 2008-06-26 21:27:38 +0200 | [diff] [blame] | 293 | #define IOMMU_PTE_U (1ULL << 59) |
| 294 | #define IOMMU_PTE_FC (1ULL << 60) |
| 295 | #define IOMMU_PTE_IR (1ULL << 61) |
| 296 | #define IOMMU_PTE_IW (1ULL << 62) |
| 297 | |
Joerg Roedel | ca9cab3 | 2015-10-20 17:33:40 +0200 | [diff] [blame] | 298 | #define DTE_FLAG_IOTLB (1ULL << 32) |
| 299 | #define DTE_FLAG_GV (1ULL << 55) |
Joerg Roedel | cbf3ccd | 2015-10-20 14:59:36 +0200 | [diff] [blame] | 300 | #define DTE_FLAG_MASK (0x3ffULL << 32) |
Joerg Roedel | 52815b7 | 2011-11-17 17:24:28 +0100 | [diff] [blame] | 301 | #define DTE_GLX_SHIFT (56) |
| 302 | #define DTE_GLX_MASK (3) |
| 303 | |
| 304 | #define DTE_GCR3_VAL_A(x) (((x) >> 12) & 0x00007ULL) |
| 305 | #define DTE_GCR3_VAL_B(x) (((x) >> 15) & 0x0ffffULL) |
| 306 | #define DTE_GCR3_VAL_C(x) (((x) >> 31) & 0xfffffULL) |
| 307 | |
| 308 | #define DTE_GCR3_INDEX_A 0 |
| 309 | #define DTE_GCR3_INDEX_B 1 |
| 310 | #define DTE_GCR3_INDEX_C 1 |
| 311 | |
| 312 | #define DTE_GCR3_SHIFT_A 58 |
| 313 | #define DTE_GCR3_SHIFT_B 16 |
| 314 | #define DTE_GCR3_SHIFT_C 43 |
| 315 | |
Joerg Roedel | b16137b | 2011-11-21 16:50:23 +0100 | [diff] [blame] | 316 | #define GCR3_VALID 0x01ULL |
Joerg Roedel | fd7b553 | 2011-04-05 15:31:08 +0200 | [diff] [blame] | 317 | |
Joerg Roedel | 8d283c3 | 2008-06-26 21:27:38 +0200 | [diff] [blame] | 318 | #define IOMMU_PAGE_MASK (((1ULL << 52) - 1) & ~0xfffULL) |
| 319 | #define IOMMU_PTE_PRESENT(pte) ((pte) & IOMMU_PTE_P) |
| 320 | #define IOMMU_PTE_PAGE(pte) (phys_to_virt((pte) & IOMMU_PAGE_MASK)) |
| 321 | #define IOMMU_PTE_MODE(pte) (((pte) >> 9) & 0x07) |
| 322 | |
| 323 | #define IOMMU_PROT_MASK 0x03 |
| 324 | #define IOMMU_PROT_IR 0x01 |
| 325 | #define IOMMU_PROT_IW 0x02 |
| 326 | |
| 327 | /* IOMMU capabilities */ |
| 328 | #define IOMMU_CAP_IOTLB 24 |
| 329 | #define IOMMU_CAP_NPCACHE 26 |
Joerg Roedel | d99ddec | 2011-04-11 11:03:18 +0200 | [diff] [blame] | 330 | #define IOMMU_CAP_EFR 27 |
Joerg Roedel | 8d283c3 | 2008-06-26 21:27:38 +0200 | [diff] [blame] | 331 | |
| 332 | #define MAX_DOMAIN_ID 65536 |
| 333 | |
Joerg Roedel | 9fdb19d | 2008-12-02 17:46:25 +0100 | [diff] [blame] | 334 | /* Protection domain flags */ |
| 335 | #define PD_DMA_OPS_MASK (1UL << 0) /* domain used for dma_ops */ |
Joerg Roedel | e2dc14a | 2008-12-10 18:48:59 +0100 | [diff] [blame] | 336 | #define PD_DEFAULT_MASK (1UL << 1) /* domain is a default dma_ops |
| 337 | domain for an IOMMU */ |
Joerg Roedel | 0feae53 | 2009-08-26 15:26:30 +0200 | [diff] [blame] | 338 | #define PD_PASSTHROUGH_MASK (1UL << 2) /* domain has no page |
| 339 | translation */ |
Joerg Roedel | 52815b7 | 2011-11-17 17:24:28 +0100 | [diff] [blame] | 340 | #define PD_IOMMUV2_MASK (1UL << 3) /* domain has gcr3 table */ |
Joerg Roedel | 0feae53 | 2009-08-26 15:26:30 +0200 | [diff] [blame] | 341 | |
Joerg Roedel | fefda11 | 2009-05-20 12:21:42 +0200 | [diff] [blame] | 342 | extern bool amd_iommu_dump; |
| 343 | #define DUMP_printk(format, arg...) \ |
| 344 | do { \ |
| 345 | if (amd_iommu_dump) \ |
Joerg Roedel | 4c6f40d | 2009-09-01 16:43:58 +0200 | [diff] [blame] | 346 | printk(KERN_INFO "AMD-Vi: " format, ## arg); \ |
Joerg Roedel | fefda11 | 2009-05-20 12:21:42 +0200 | [diff] [blame] | 347 | } while(0); |
Joerg Roedel | 9fdb19d | 2008-12-02 17:46:25 +0100 | [diff] [blame] | 348 | |
Joerg Roedel | 318afd4 | 2009-11-23 18:32:38 +0100 | [diff] [blame] | 349 | /* global flag if IOMMUs cache non-present entries */ |
| 350 | extern bool amd_iommu_np_cache; |
Joerg Roedel | 60f723b | 2011-04-05 12:50:24 +0200 | [diff] [blame] | 351 | /* Only true if all IOMMUs support device IOTLBs */ |
| 352 | extern bool amd_iommu_iotlb_sup; |
Joerg Roedel | 318afd4 | 2009-11-23 18:32:38 +0100 | [diff] [blame] | 353 | |
Joerg Roedel | 05152a0 | 2012-06-15 16:53:51 +0200 | [diff] [blame] | 354 | #define MAX_IRQS_PER_TABLE 256 |
| 355 | #define IRQ_TABLE_ALIGNMENT 128 |
| 356 | |
Joerg Roedel | 0ea2c42 | 2012-06-15 18:05:20 +0200 | [diff] [blame] | 357 | struct irq_remap_table { |
| 358 | spinlock_t lock; |
| 359 | unsigned min_index; |
| 360 | u32 *table; |
| 361 | }; |
| 362 | |
| 363 | extern struct irq_remap_table **irq_lookup_table; |
| 364 | |
Joerg Roedel | 05152a0 | 2012-06-15 16:53:51 +0200 | [diff] [blame] | 365 | /* Interrupt remapping feature used? */ |
| 366 | extern bool amd_iommu_irq_remap; |
| 367 | |
| 368 | /* kmem_cache to get tables with 128 byte alignement */ |
| 369 | extern struct kmem_cache *amd_iommu_irq_cache; |
| 370 | |
Joerg Roedel | 5694703 | 2008-07-11 17:14:20 +0200 | [diff] [blame] | 371 | /* |
Joerg Roedel | 3bd2217 | 2009-05-04 15:06:20 +0200 | [diff] [blame] | 372 | * Make iterating over all IOMMUs easier |
| 373 | */ |
| 374 | #define for_each_iommu(iommu) \ |
| 375 | list_for_each_entry((iommu), &amd_iommu_list, list) |
| 376 | #define for_each_iommu_safe(iommu, next) \ |
| 377 | list_for_each_entry_safe((iommu), (next), &amd_iommu_list, list) |
| 378 | |
Joerg Roedel | 384de72 | 2009-05-15 12:30:05 +0200 | [diff] [blame] | 379 | #define APERTURE_RANGE_SHIFT 27 /* 128 MB */ |
| 380 | #define APERTURE_RANGE_SIZE (1ULL << APERTURE_RANGE_SHIFT) |
| 381 | #define APERTURE_RANGE_PAGES (APERTURE_RANGE_SIZE >> PAGE_SHIFT) |
| 382 | #define APERTURE_MAX_RANGES 32 /* allows 4GB of DMA address space */ |
| 383 | #define APERTURE_RANGE_INDEX(a) ((a) >> APERTURE_RANGE_SHIFT) |
| 384 | #define APERTURE_PAGE_INDEX(a) (((a) >> 21) & 0x3fULL) |
Joerg Roedel | 8d283c3 | 2008-06-26 21:27:38 +0200 | [diff] [blame] | 385 | |
Joerg Roedel | 72e1dcc | 2011-11-10 19:13:51 +0100 | [diff] [blame] | 386 | |
| 387 | /* |
| 388 | * This struct is used to pass information about |
| 389 | * incoming PPR faults around. |
| 390 | */ |
| 391 | struct amd_iommu_fault { |
| 392 | u64 address; /* IO virtual address of the fault*/ |
| 393 | u32 pasid; /* Address space identifier */ |
| 394 | u16 device_id; /* Originating PCI device id */ |
| 395 | u16 tag; /* PPR tag */ |
| 396 | u16 flags; /* Fault flags */ |
| 397 | |
| 398 | }; |
| 399 | |
Joerg Roedel | 72e1dcc | 2011-11-10 19:13:51 +0100 | [diff] [blame] | 400 | |
Joerg Roedel | f3572db | 2011-11-23 12:36:25 +0100 | [diff] [blame] | 401 | struct iommu_domain; |
Jiang Liu | 7c71d30 | 2015-04-13 14:11:33 +0800 | [diff] [blame] | 402 | struct irq_domain; |
Joerg Roedel | f3572db | 2011-11-23 12:36:25 +0100 | [diff] [blame] | 403 | |
Joerg Roedel | 5694703 | 2008-07-11 17:14:20 +0200 | [diff] [blame] | 404 | /* |
| 405 | * This structure contains generic data for IOMMU protection domains |
| 406 | * independent of their use. |
| 407 | */ |
Joerg Roedel | 8d283c3 | 2008-06-26 21:27:38 +0200 | [diff] [blame] | 408 | struct protection_domain { |
Joerg Roedel | aeb26f5 | 2009-11-20 16:44:01 +0100 | [diff] [blame] | 409 | struct list_head list; /* for list of all protection domains */ |
Joerg Roedel | 7c392cb | 2009-11-26 11:13:32 +0100 | [diff] [blame] | 410 | struct list_head dev_list; /* List of all devices in this domain */ |
Joerg Roedel | 3f4b87b | 2015-03-26 13:43:07 +0100 | [diff] [blame] | 411 | struct iommu_domain domain; /* generic domain handle used by |
| 412 | iommu core code */ |
Joerg Roedel | 9fdb19d | 2008-12-02 17:46:25 +0100 | [diff] [blame] | 413 | spinlock_t lock; /* mostly used to lock the page table*/ |
Joerg Roedel | 5d214fe | 2010-02-08 14:44:49 +0100 | [diff] [blame] | 414 | struct mutex api_lock; /* protect page tables in the iommu-api path */ |
Joerg Roedel | 9fdb19d | 2008-12-02 17:46:25 +0100 | [diff] [blame] | 415 | u16 id; /* the domain id written to the device table */ |
| 416 | int mode; /* paging mode (0-6 levels) */ |
| 417 | u64 *pt_root; /* page table root pointer */ |
Joerg Roedel | 52815b7 | 2011-11-17 17:24:28 +0100 | [diff] [blame] | 418 | int glx; /* Number of levels for GCR3 table */ |
| 419 | u64 *gcr3_tbl; /* Guest CR3 table */ |
Joerg Roedel | 9fdb19d | 2008-12-02 17:46:25 +0100 | [diff] [blame] | 420 | unsigned long flags; /* flags to find out type of domain */ |
Joerg Roedel | 04bfdd8 | 2009-09-02 16:00:23 +0200 | [diff] [blame] | 421 | bool updated; /* complete domain flush required */ |
Joerg Roedel | 863c74e | 2008-12-02 17:56:36 +0100 | [diff] [blame] | 422 | unsigned dev_cnt; /* devices assigned to this domain */ |
Joerg Roedel | c459611 | 2009-11-20 14:57:32 +0100 | [diff] [blame] | 423 | unsigned dev_iommu[MAX_IOMMUS]; /* per-IOMMU reference count */ |
Joerg Roedel | 8d283c3 | 2008-06-26 21:27:38 +0200 | [diff] [blame] | 424 | }; |
| 425 | |
Joerg Roedel | 5694703 | 2008-07-11 17:14:20 +0200 | [diff] [blame] | 426 | /* |
Joerg Roedel | 5694703 | 2008-07-11 17:14:20 +0200 | [diff] [blame] | 427 | * Structure where we save information about one hardware AMD IOMMU in the |
| 428 | * system. |
| 429 | */ |
Joerg Roedel | 8d283c3 | 2008-06-26 21:27:38 +0200 | [diff] [blame] | 430 | struct amd_iommu { |
| 431 | struct list_head list; |
Joerg Roedel | 5694703 | 2008-07-11 17:14:20 +0200 | [diff] [blame] | 432 | |
Joerg Roedel | bb52777 | 2009-11-20 14:31:51 +0100 | [diff] [blame] | 433 | /* Index within the IOMMU array */ |
| 434 | int index; |
| 435 | |
Joerg Roedel | 5694703 | 2008-07-11 17:14:20 +0200 | [diff] [blame] | 436 | /* locks the accesses to the hardware */ |
Joerg Roedel | 8d283c3 | 2008-06-26 21:27:38 +0200 | [diff] [blame] | 437 | spinlock_t lock; |
| 438 | |
Joerg Roedel | 3eaf28a | 2008-09-08 15:55:10 +0200 | [diff] [blame] | 439 | /* Pointer to PCI device of this IOMMU */ |
| 440 | struct pci_dev *dev; |
| 441 | |
Joerg Roedel | c1bf94e | 2012-05-31 17:38:11 +0200 | [diff] [blame] | 442 | /* Cache pdev to root device for resume quirks */ |
| 443 | struct pci_dev *root_pdev; |
| 444 | |
Joerg Roedel | 5694703 | 2008-07-11 17:14:20 +0200 | [diff] [blame] | 445 | /* physical address of MMIO space */ |
Joerg Roedel | 8d283c3 | 2008-06-26 21:27:38 +0200 | [diff] [blame] | 446 | u64 mmio_phys; |
Steven L Kinney | 30861dd | 2013-06-05 16:11:48 -0500 | [diff] [blame] | 447 | |
| 448 | /* physical end address of MMIO space */ |
| 449 | u64 mmio_phys_end; |
| 450 | |
Joerg Roedel | 5694703 | 2008-07-11 17:14:20 +0200 | [diff] [blame] | 451 | /* virtual address of MMIO space */ |
Joerg Roedel | 98f1ad2 | 2012-07-06 13:28:37 +0200 | [diff] [blame] | 452 | u8 __iomem *mmio_base; |
Joerg Roedel | 5694703 | 2008-07-11 17:14:20 +0200 | [diff] [blame] | 453 | |
| 454 | /* capabilities of that IOMMU read from ACPI */ |
Joerg Roedel | 8d283c3 | 2008-06-26 21:27:38 +0200 | [diff] [blame] | 455 | u32 cap; |
Joerg Roedel | 5694703 | 2008-07-11 17:14:20 +0200 | [diff] [blame] | 456 | |
Joerg Roedel | e9bf519 | 2010-09-20 14:33:07 +0200 | [diff] [blame] | 457 | /* flags read from acpi table */ |
| 458 | u8 acpi_flags; |
| 459 | |
Joerg Roedel | d99ddec | 2011-04-11 11:03:18 +0200 | [diff] [blame] | 460 | /* Extended features */ |
| 461 | u64 features; |
| 462 | |
Joerg Roedel | 400a28a | 2011-11-28 15:11:02 +0100 | [diff] [blame] | 463 | /* IOMMUv2 */ |
| 464 | bool is_iommu_v2; |
| 465 | |
Joerg Roedel | 23c742d | 2012-06-12 11:47:34 +0200 | [diff] [blame] | 466 | /* PCI device id of the IOMMU device */ |
| 467 | u16 devid; |
| 468 | |
Richard Kennedy | eac9fbc | 2008-11-24 13:53:24 +0000 | [diff] [blame] | 469 | /* |
| 470 | * Capability pointer. There could be more than one IOMMU per PCI |
| 471 | * device function if there are more than one AMD IOMMU capability |
| 472 | * pointers. |
| 473 | */ |
| 474 | u16 cap_ptr; |
| 475 | |
Joerg Roedel | ee893c2 | 2008-09-08 14:48:04 +0200 | [diff] [blame] | 476 | /* pci domain of this IOMMU */ |
| 477 | u16 pci_seg; |
| 478 | |
Joerg Roedel | 5694703 | 2008-07-11 17:14:20 +0200 | [diff] [blame] | 479 | /* start of exclusion range of that IOMMU */ |
Joerg Roedel | 8d283c3 | 2008-06-26 21:27:38 +0200 | [diff] [blame] | 480 | u64 exclusion_start; |
Joerg Roedel | 5694703 | 2008-07-11 17:14:20 +0200 | [diff] [blame] | 481 | /* length of exclusion range of that IOMMU */ |
Joerg Roedel | 8d283c3 | 2008-06-26 21:27:38 +0200 | [diff] [blame] | 482 | u64 exclusion_length; |
| 483 | |
Joerg Roedel | 5694703 | 2008-07-11 17:14:20 +0200 | [diff] [blame] | 484 | /* command buffer virtual address */ |
Joerg Roedel | 8d283c3 | 2008-06-26 21:27:38 +0200 | [diff] [blame] | 485 | u8 *cmd_buf; |
Joerg Roedel | 8d283c3 | 2008-06-26 21:27:38 +0200 | [diff] [blame] | 486 | |
Richard Kennedy | eac9fbc | 2008-11-24 13:53:24 +0000 | [diff] [blame] | 487 | /* event buffer virtual address */ |
| 488 | u8 *evt_buf; |
Joerg Roedel | 335503e | 2008-09-05 14:29:07 +0200 | [diff] [blame] | 489 | |
Joerg Roedel | 1a29ac0 | 2011-11-10 15:41:40 +0100 | [diff] [blame] | 490 | /* Base of the PPR log, if present */ |
| 491 | u8 *ppr_log; |
| 492 | |
Joerg Roedel | a80dc3e | 2008-09-11 16:51:41 +0200 | [diff] [blame] | 493 | /* true if interrupts for this IOMMU are already enabled */ |
| 494 | bool int_enabled; |
| 495 | |
Richard Kennedy | eac9fbc | 2008-11-24 13:53:24 +0000 | [diff] [blame] | 496 | /* if one, we need to send a completion wait command */ |
Joerg Roedel | 0cfd7aa | 2008-12-10 19:58:00 +0100 | [diff] [blame] | 497 | bool need_sync; |
Richard Kennedy | eac9fbc | 2008-11-24 13:53:24 +0000 | [diff] [blame] | 498 | |
Alex Williamson | 066f2e9 | 2014-06-12 16:12:37 -0600 | [diff] [blame] | 499 | /* IOMMU sysfs device */ |
| 500 | struct device *iommu_dev; |
| 501 | |
Joerg Roedel | 4c894f4 | 2010-09-23 15:15:19 +0200 | [diff] [blame] | 502 | /* |
Matthew Garrett | 5bcd757 | 2010-10-04 14:59:31 -0400 | [diff] [blame] | 503 | * We can't rely on the BIOS to restore all values on reinit, so we |
| 504 | * need to stash them |
Joerg Roedel | 4c894f4 | 2010-09-23 15:15:19 +0200 | [diff] [blame] | 505 | */ |
Matthew Garrett | 5bcd757 | 2010-10-04 14:59:31 -0400 | [diff] [blame] | 506 | |
| 507 | /* The iommu BAR */ |
| 508 | u32 stored_addr_lo; |
| 509 | u32 stored_addr_hi; |
| 510 | |
| 511 | /* |
| 512 | * Each iommu has 6 l1s, each of which is documented as having 0x12 |
| 513 | * registers |
| 514 | */ |
| 515 | u32 stored_l1[6][0x12]; |
| 516 | |
| 517 | /* The l2 indirect registers */ |
| 518 | u32 stored_l2[0x83]; |
Steven L Kinney | 30861dd | 2013-06-05 16:11:48 -0500 | [diff] [blame] | 519 | |
| 520 | /* The maximum PC banks and counters/bank (PCSup=1) */ |
| 521 | u8 max_banks; |
| 522 | u8 max_counters; |
Jiang Liu | 7c71d30 | 2015-04-13 14:11:33 +0800 | [diff] [blame] | 523 | #ifdef CONFIG_IRQ_REMAP |
| 524 | struct irq_domain *ir_domain; |
| 525 | struct irq_domain *msi_domain; |
| 526 | #endif |
Joerg Roedel | 4bf5bee | 2016-09-14 11:41:59 +0200 | [diff] [blame] | 527 | |
| 528 | volatile u64 __aligned(8) cmd_sem; |
Joerg Roedel | 8d283c3 | 2008-06-26 21:27:38 +0200 | [diff] [blame] | 529 | }; |
| 530 | |
Wan Zongshun | 2a0cb4e | 2016-04-01 09:06:00 -0400 | [diff] [blame] | 531 | #define ACPIHID_UID_LEN 256 |
| 532 | #define ACPIHID_HID_LEN 9 |
| 533 | |
| 534 | struct acpihid_map_entry { |
| 535 | struct list_head list; |
| 536 | u8 uid[ACPIHID_UID_LEN]; |
| 537 | u8 hid[ACPIHID_HID_LEN]; |
| 538 | u16 devid; |
| 539 | u16 root_devid; |
| 540 | bool cmd_line; |
| 541 | struct iommu_group *group; |
| 542 | }; |
| 543 | |
Joerg Roedel | 6efed63 | 2012-06-14 15:52:58 +0200 | [diff] [blame] | 544 | struct devid_map { |
| 545 | struct list_head list; |
| 546 | u8 id; |
| 547 | u16 devid; |
Joerg Roedel | 31cff67 | 2013-04-09 16:53:58 +0200 | [diff] [blame] | 548 | bool cmd_line; |
Joerg Roedel | 6efed63 | 2012-06-14 15:52:58 +0200 | [diff] [blame] | 549 | }; |
| 550 | |
| 551 | /* Map HPET and IOAPIC ids to the devid used by the IOMMU */ |
| 552 | extern struct list_head ioapic_map; |
| 553 | extern struct list_head hpet_map; |
Wan Zongshun | 2a0cb4e | 2016-04-01 09:06:00 -0400 | [diff] [blame] | 554 | extern struct list_head acpihid_map; |
Joerg Roedel | 6efed63 | 2012-06-14 15:52:58 +0200 | [diff] [blame] | 555 | |
Joerg Roedel | 5694703 | 2008-07-11 17:14:20 +0200 | [diff] [blame] | 556 | /* |
| 557 | * List with all IOMMUs in the system. This list is not locked because it is |
| 558 | * only written and read at driver initialization or suspend time |
| 559 | */ |
Joerg Roedel | 8d283c3 | 2008-06-26 21:27:38 +0200 | [diff] [blame] | 560 | extern struct list_head amd_iommu_list; |
| 561 | |
Joerg Roedel | 5694703 | 2008-07-11 17:14:20 +0200 | [diff] [blame] | 562 | /* |
Joerg Roedel | bb52777 | 2009-11-20 14:31:51 +0100 | [diff] [blame] | 563 | * Array with pointers to each IOMMU struct |
| 564 | * The indices are referenced in the protection domains |
| 565 | */ |
| 566 | extern struct amd_iommu *amd_iommus[MAX_IOMMUS]; |
| 567 | |
| 568 | /* Number of IOMMUs present in the system */ |
| 569 | extern int amd_iommus_present; |
| 570 | |
| 571 | /* |
Joerg Roedel | aeb26f5 | 2009-11-20 16:44:01 +0100 | [diff] [blame] | 572 | * Declarations for the global list of all protection domains |
| 573 | */ |
| 574 | extern spinlock_t amd_iommu_pd_lock; |
| 575 | extern struct list_head amd_iommu_pd_list; |
| 576 | |
| 577 | /* |
Joerg Roedel | 5694703 | 2008-07-11 17:14:20 +0200 | [diff] [blame] | 578 | * Structure defining one entry in the device table |
| 579 | */ |
Joerg Roedel | 8d283c3 | 2008-06-26 21:27:38 +0200 | [diff] [blame] | 580 | struct dev_table_entry { |
Joerg Roedel | ee6c286 | 2011-11-09 12:06:03 +0100 | [diff] [blame] | 581 | u64 data[4]; |
Joerg Roedel | 8d283c3 | 2008-06-26 21:27:38 +0200 | [diff] [blame] | 582 | }; |
| 583 | |
Joerg Roedel | 5694703 | 2008-07-11 17:14:20 +0200 | [diff] [blame] | 584 | /* |
| 585 | * One entry for unity mappings parsed out of the ACPI table. |
| 586 | */ |
Joerg Roedel | 8d283c3 | 2008-06-26 21:27:38 +0200 | [diff] [blame] | 587 | struct unity_map_entry { |
| 588 | struct list_head list; |
Joerg Roedel | 5694703 | 2008-07-11 17:14:20 +0200 | [diff] [blame] | 589 | |
| 590 | /* starting device id this entry is used for (including) */ |
Joerg Roedel | 8d283c3 | 2008-06-26 21:27:38 +0200 | [diff] [blame] | 591 | u16 devid_start; |
Joerg Roedel | 5694703 | 2008-07-11 17:14:20 +0200 | [diff] [blame] | 592 | /* end device id this entry is used for (including) */ |
Joerg Roedel | 8d283c3 | 2008-06-26 21:27:38 +0200 | [diff] [blame] | 593 | u16 devid_end; |
Joerg Roedel | 5694703 | 2008-07-11 17:14:20 +0200 | [diff] [blame] | 594 | |
| 595 | /* start address to unity map (including) */ |
Joerg Roedel | 8d283c3 | 2008-06-26 21:27:38 +0200 | [diff] [blame] | 596 | u64 address_start; |
Joerg Roedel | 5694703 | 2008-07-11 17:14:20 +0200 | [diff] [blame] | 597 | /* end address to unity map (including) */ |
Joerg Roedel | 8d283c3 | 2008-06-26 21:27:38 +0200 | [diff] [blame] | 598 | u64 address_end; |
Joerg Roedel | 5694703 | 2008-07-11 17:14:20 +0200 | [diff] [blame] | 599 | |
| 600 | /* required protection */ |
Joerg Roedel | 8d283c3 | 2008-06-26 21:27:38 +0200 | [diff] [blame] | 601 | int prot; |
| 602 | }; |
| 603 | |
Joerg Roedel | 5694703 | 2008-07-11 17:14:20 +0200 | [diff] [blame] | 604 | /* |
| 605 | * List of all unity mappings. It is not locked because as runtime it is only |
| 606 | * read. It is created at ACPI table parsing time. |
| 607 | */ |
Joerg Roedel | 8d283c3 | 2008-06-26 21:27:38 +0200 | [diff] [blame] | 608 | extern struct list_head amd_iommu_unity_map; |
| 609 | |
Joerg Roedel | 5694703 | 2008-07-11 17:14:20 +0200 | [diff] [blame] | 610 | /* |
| 611 | * Data structures for device handling |
| 612 | */ |
| 613 | |
| 614 | /* |
| 615 | * Device table used by hardware. Read and write accesses by software are |
| 616 | * locked with the amd_iommu_pd_table lock. |
| 617 | */ |
Joerg Roedel | 8d283c3 | 2008-06-26 21:27:38 +0200 | [diff] [blame] | 618 | extern struct dev_table_entry *amd_iommu_dev_table; |
Joerg Roedel | 5694703 | 2008-07-11 17:14:20 +0200 | [diff] [blame] | 619 | |
| 620 | /* |
| 621 | * Alias table to find requestor ids to device ids. Not locked because only |
| 622 | * read on runtime. |
| 623 | */ |
Joerg Roedel | 8d283c3 | 2008-06-26 21:27:38 +0200 | [diff] [blame] | 624 | extern u16 *amd_iommu_alias_table; |
Joerg Roedel | 5694703 | 2008-07-11 17:14:20 +0200 | [diff] [blame] | 625 | |
| 626 | /* |
| 627 | * Reverse lookup table to find the IOMMU which translates a specific device. |
| 628 | */ |
Joerg Roedel | 8d283c3 | 2008-06-26 21:27:38 +0200 | [diff] [blame] | 629 | extern struct amd_iommu **amd_iommu_rlookup_table; |
| 630 | |
Joerg Roedel | 5694703 | 2008-07-11 17:14:20 +0200 | [diff] [blame] | 631 | /* size of the dma_ops aperture as power of 2 */ |
Joerg Roedel | 8d283c3 | 2008-06-26 21:27:38 +0200 | [diff] [blame] | 632 | extern unsigned amd_iommu_aperture_order; |
| 633 | |
Joerg Roedel | 5694703 | 2008-07-11 17:14:20 +0200 | [diff] [blame] | 634 | /* largest PCI device id we expect translation requests for */ |
Joerg Roedel | 8d283c3 | 2008-06-26 21:27:38 +0200 | [diff] [blame] | 635 | extern u16 amd_iommu_last_bdf; |
| 636 | |
Joerg Roedel | 5694703 | 2008-07-11 17:14:20 +0200 | [diff] [blame] | 637 | /* allocation bitmap for domain ids */ |
Joerg Roedel | 8d283c3 | 2008-06-26 21:27:38 +0200 | [diff] [blame] | 638 | extern unsigned long *amd_iommu_pd_alloc_bitmap; |
| 639 | |
FUJITA Tomonori | afa9fdc | 2008-09-20 01:23:30 +0900 | [diff] [blame] | 640 | /* |
| 641 | * If true, the addresses will be flushed on unmap time, not when |
| 642 | * they are reused |
| 643 | */ |
Viresh Kumar | 621a5f7 | 2015-09-26 15:04:07 -0700 | [diff] [blame] | 644 | extern bool amd_iommu_unmap_flush; |
FUJITA Tomonori | afa9fdc | 2008-09-20 01:23:30 +0900 | [diff] [blame] | 645 | |
Suravee Suthikulpanit | a919a01 | 2014-03-05 18:54:18 -0600 | [diff] [blame] | 646 | /* Smallest max PASID supported by any IOMMU in the system */ |
| 647 | extern u32 amd_iommu_max_pasid; |
Joerg Roedel | 62f71ab | 2011-11-10 14:41:57 +0100 | [diff] [blame] | 648 | |
Joerg Roedel | 400a28a | 2011-11-28 15:11:02 +0100 | [diff] [blame] | 649 | extern bool amd_iommu_v2_present; |
| 650 | |
Joerg Roedel | 5abcdba | 2011-12-01 15:49:45 +0100 | [diff] [blame] | 651 | extern bool amd_iommu_force_isolation; |
| 652 | |
Joerg Roedel | 52815b7 | 2011-11-17 17:24:28 +0100 | [diff] [blame] | 653 | /* Max levels of glxval supported */ |
| 654 | extern int amd_iommu_max_glx_val; |
| 655 | |
Joerg Roedel | 98f1ad2 | 2012-07-06 13:28:37 +0200 | [diff] [blame] | 656 | /* |
| 657 | * This function flushes all internal caches of |
| 658 | * the IOMMU used by this driver. |
| 659 | */ |
| 660 | extern void iommu_flush_all_caches(struct amd_iommu *iommu); |
| 661 | |
Joerg Roedel | 6efed63 | 2012-06-14 15:52:58 +0200 | [diff] [blame] | 662 | static inline int get_ioapic_devid(int id) |
| 663 | { |
| 664 | struct devid_map *entry; |
| 665 | |
| 666 | list_for_each_entry(entry, &ioapic_map, list) { |
| 667 | if (entry->id == id) |
| 668 | return entry->devid; |
| 669 | } |
| 670 | |
| 671 | return -EINVAL; |
| 672 | } |
| 673 | |
| 674 | static inline int get_hpet_devid(int id) |
| 675 | { |
| 676 | struct devid_map *entry; |
| 677 | |
| 678 | list_for_each_entry(entry, &hpet_map, list) { |
| 679 | if (entry->id == id) |
| 680 | return entry->devid; |
| 681 | } |
| 682 | |
| 683 | return -EINVAL; |
| 684 | } |
| 685 | |
H. Peter Anvin | 1965aae | 2008-10-22 22:26:29 -0700 | [diff] [blame] | 686 | #endif /* _ASM_X86_AMD_IOMMU_TYPES_H */ |