blob: 14b13f07cd1fa87658f22f8352ff6bc32b3935ac [file] [log] [blame]
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07001/*
Sujith Manoharan5b681382011-05-17 13:36:18 +05302 * Copyright (c) 2008-2011 Atheros Communications Inc.
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07003 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17#include <linux/io.h>
Tejun Heo5a0e3ad2010-03-24 17:04:11 +090018#include <linux/slab.h>
Paul Gortmaker9d9779e2011-07-03 15:21:01 -040019#include <linux/module.h>
Felix Fietkau09d8e312013-11-18 20:14:43 +010020#include <linux/time.h>
Felix Fietkauc67ce332013-12-14 18:03:38 +010021#include <linux/bitops.h>
Felix Fietkau5ca06eb2014-10-25 17:19:35 +020022#include <linux/etherdevice.h>
Miaoqing Pan61b559d2015-04-01 10:19:57 +080023#include <linux/gpio.h>
Luis R. Rodriguezf078f202008-08-04 00:16:41 -070024#include <asm/unaligned.h>
25
Luis R. Rodriguezaf03abe2009-09-09 02:33:11 -070026#include "hw.h"
Luis R. Rodriguezd70357d2010-04-15 17:38:06 -040027#include "hw-ops.h"
Luis R. Rodriguezb622a722010-04-15 17:39:28 -040028#include "ar9003_mac.h"
Sujith Manoharanf4701b52012-02-22 12:41:18 +053029#include "ar9003_mci.h"
Sujith Manoharan362cd032012-09-16 08:06:36 +053030#include "ar9003_phy.h"
Ben Greear462e58f2012-04-12 10:04:00 -070031#include "ath9k.h"
Luis R. Rodriguezf078f202008-08-04 00:16:41 -070032
Sujithcbe61d82009-02-09 13:27:12 +053033static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type);
Luis R. Rodriguezf078f202008-08-04 00:16:41 -070034
Luis R. Rodriguez7322fd12009-09-23 23:07:00 -040035MODULE_AUTHOR("Atheros Communications");
36MODULE_DESCRIPTION("Support for Atheros 802.11n wireless LAN cards.");
37MODULE_SUPPORTED_DEVICE("Atheros 802.11n WLAN cards");
38MODULE_LICENSE("Dual BSD/GPL");
39
Felix Fietkaudfdac8a2010-10-08 22:13:51 +020040static void ath9k_hw_set_clockrate(struct ath_hw *ah)
Sujithf1dc5602008-10-29 10:16:30 +053041{
Felix Fietkaudfdac8a2010-10-08 22:13:51 +020042 struct ath_common *common = ath9k_hw_common(ah);
Felix Fietkaue4744ec2013-10-11 23:31:01 +020043 struct ath9k_channel *chan = ah->curchan;
Felix Fietkaudfdac8a2010-10-08 22:13:51 +020044 unsigned int clockrate;
Sujithcbe61d82009-02-09 13:27:12 +053045
Felix Fietkau087b6ff2011-07-09 11:12:49 +070046 /* AR9287 v1.3+ uses async FIFO and runs the MAC at 117 MHz */
47 if (AR_SREV_9287(ah) && AR_SREV_9287_13_OR_LATER(ah))
48 clockrate = 117;
Felix Fietkaue4744ec2013-10-11 23:31:01 +020049 else if (!chan) /* should really check for CCK instead */
Felix Fietkaudfdac8a2010-10-08 22:13:51 +020050 clockrate = ATH9K_CLOCK_RATE_CCK;
Felix Fietkaue4744ec2013-10-11 23:31:01 +020051 else if (IS_CHAN_2GHZ(chan))
Felix Fietkaudfdac8a2010-10-08 22:13:51 +020052 clockrate = ATH9K_CLOCK_RATE_2GHZ_OFDM;
53 else if (ah->caps.hw_caps & ATH9K_HW_CAP_FASTCLOCK)
54 clockrate = ATH9K_CLOCK_FAST_RATE_5GHZ_OFDM;
Vasanthakumar Thiagarajane5553722010-04-26 15:04:33 -040055 else
Felix Fietkaudfdac8a2010-10-08 22:13:51 +020056 clockrate = ATH9K_CLOCK_RATE_5GHZ_OFDM;
57
Michal Nazarewiczbeae4162013-11-29 18:06:46 +010058 if (chan) {
59 if (IS_CHAN_HT40(chan))
60 clockrate *= 2;
Felix Fietkaue4744ec2013-10-11 23:31:01 +020061 if (IS_CHAN_HALF_RATE(chan))
Felix Fietkau906c7202011-07-09 11:12:48 +070062 clockrate /= 2;
Felix Fietkaue4744ec2013-10-11 23:31:01 +020063 if (IS_CHAN_QUARTER_RATE(chan))
Felix Fietkau906c7202011-07-09 11:12:48 +070064 clockrate /= 4;
65 }
66
Felix Fietkaudfdac8a2010-10-08 22:13:51 +020067 common->clockrate = clockrate;
Sujithf1dc5602008-10-29 10:16:30 +053068}
Luis R. Rodriguezf078f202008-08-04 00:16:41 -070069
Sujithcbe61d82009-02-09 13:27:12 +053070static u32 ath9k_hw_mac_to_clks(struct ath_hw *ah, u32 usecs)
Sujithf1dc5602008-10-29 10:16:30 +053071{
Felix Fietkaudfdac8a2010-10-08 22:13:51 +020072 struct ath_common *common = ath9k_hw_common(ah);
Sujithcbe61d82009-02-09 13:27:12 +053073
Felix Fietkaudfdac8a2010-10-08 22:13:51 +020074 return usecs * common->clockrate;
Sujithf1dc5602008-10-29 10:16:30 +053075}
76
Sujith0caa7b12009-02-16 13:23:20 +053077bool ath9k_hw_wait(struct ath_hw *ah, u32 reg, u32 mask, u32 val, u32 timeout)
Luis R. Rodriguezf078f202008-08-04 00:16:41 -070078{
79 int i;
80
Sujith0caa7b12009-02-16 13:23:20 +053081 BUG_ON(timeout < AH_TIME_QUANTUM);
82
83 for (i = 0; i < (timeout / AH_TIME_QUANTUM); i++) {
Luis R. Rodriguezf078f202008-08-04 00:16:41 -070084 if ((REG_READ(ah, reg) & mask) == val)
85 return true;
86
87 udelay(AH_TIME_QUANTUM);
88 }
Sujith04bd4632008-11-28 22:18:05 +053089
Joe Perchesd2182b62011-12-15 14:55:53 -080090 ath_dbg(ath9k_hw_common(ah), ANY,
Joe Perches226afe62010-12-02 19:12:37 -080091 "timeout (%d us) on reg 0x%x: 0x%08x & 0x%08x != 0x%08x\n",
92 timeout, reg, REG_READ(ah, reg), mask, val);
Sujithf1dc5602008-10-29 10:16:30 +053093
Luis R. Rodriguezf078f202008-08-04 00:16:41 -070094 return false;
95}
Luis R. Rodriguez7322fd12009-09-23 23:07:00 -040096EXPORT_SYMBOL(ath9k_hw_wait);
Luis R. Rodriguezf078f202008-08-04 00:16:41 -070097
Felix Fietkau7c5adc82012-04-19 21:18:26 +020098void ath9k_hw_synth_delay(struct ath_hw *ah, struct ath9k_channel *chan,
99 int hw_delay)
100{
Felix Fietkau1a5e6322013-10-11 23:30:54 +0200101 hw_delay /= 10;
Felix Fietkau7c5adc82012-04-19 21:18:26 +0200102
103 if (IS_CHAN_HALF_RATE(chan))
104 hw_delay *= 2;
105 else if (IS_CHAN_QUARTER_RATE(chan))
106 hw_delay *= 4;
107
108 udelay(hw_delay + BASE_ACTIVATE_DELAY);
109}
110
Felix Fietkau0166b4b2013-01-20 18:51:55 +0100111void ath9k_hw_write_array(struct ath_hw *ah, const struct ar5416IniArray *array,
Felix Fietkaua9b6b252011-03-23 20:57:27 +0100112 int column, unsigned int *writecnt)
113{
114 int r;
115
116 ENABLE_REGWRITE_BUFFER(ah);
117 for (r = 0; r < array->ia_rows; r++) {
118 REG_WRITE(ah, INI_RA(array, r, 0),
119 INI_RA(array, r, column));
120 DO_DELAY(*writecnt);
121 }
122 REGWRITE_BUFFER_FLUSH(ah);
123}
124
Oleksij Rempela57cb452015-03-22 19:29:51 +0100125void ath9k_hw_read_array(struct ath_hw *ah, u32 array[][2], int size)
126{
127 u32 *tmp_reg_list, *tmp_data;
128 int i;
129
130 tmp_reg_list = kmalloc(size * sizeof(u32), GFP_KERNEL);
131 if (!tmp_reg_list) {
132 dev_err(ah->dev, "%s: tmp_reg_list: alloc filed\n", __func__);
133 return;
134 }
135
136 tmp_data = kmalloc(size * sizeof(u32), GFP_KERNEL);
137 if (!tmp_data) {
138 dev_err(ah->dev, "%s tmp_data: alloc filed\n", __func__);
139 goto error_tmp_data;
140 }
141
142 for (i = 0; i < size; i++)
143 tmp_reg_list[i] = array[i][0];
144
145 REG_READ_MULTI(ah, tmp_reg_list, tmp_data, size);
146
147 for (i = 0; i < size; i++)
148 array[i][1] = tmp_data[i];
149
150 kfree(tmp_data);
151error_tmp_data:
152 kfree(tmp_reg_list);
153}
154
Luis R. Rodriguezf078f202008-08-04 00:16:41 -0700155u32 ath9k_hw_reverse_bits(u32 val, u32 n)
156{
157 u32 retval;
158 int i;
159
160 for (i = 0, retval = 0; i < n; i++) {
161 retval = (retval << 1) | (val & 1);
162 val >>= 1;
163 }
164 return retval;
165}
166
Sujithcbe61d82009-02-09 13:27:12 +0530167u16 ath9k_hw_computetxtime(struct ath_hw *ah,
Felix Fietkau545750d2009-11-23 22:21:01 +0100168 u8 phy, int kbps,
Sujithf1dc5602008-10-29 10:16:30 +0530169 u32 frameLen, u16 rateix,
170 bool shortPreamble)
171{
172 u32 bitsPerSymbol, numBits, numSymbols, phyTime, txTime;
Sujithf1dc5602008-10-29 10:16:30 +0530173
174 if (kbps == 0)
175 return 0;
176
Felix Fietkau545750d2009-11-23 22:21:01 +0100177 switch (phy) {
Sujith46d14a52008-11-18 09:08:13 +0530178 case WLAN_RC_PHY_CCK:
Sujithf1dc5602008-10-29 10:16:30 +0530179 phyTime = CCK_PREAMBLE_BITS + CCK_PLCP_BITS;
Felix Fietkau545750d2009-11-23 22:21:01 +0100180 if (shortPreamble)
Sujithf1dc5602008-10-29 10:16:30 +0530181 phyTime >>= 1;
182 numBits = frameLen << 3;
183 txTime = CCK_SIFS_TIME + phyTime + ((numBits * 1000) / kbps);
184 break;
Sujith46d14a52008-11-18 09:08:13 +0530185 case WLAN_RC_PHY_OFDM:
Sujith2660b812009-02-09 13:27:26 +0530186 if (ah->curchan && IS_CHAN_QUARTER_RATE(ah->curchan)) {
Sujithf1dc5602008-10-29 10:16:30 +0530187 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_QUARTER) / 1000;
188 numBits = OFDM_PLCP_BITS + (frameLen << 3);
189 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
190 txTime = OFDM_SIFS_TIME_QUARTER
191 + OFDM_PREAMBLE_TIME_QUARTER
192 + (numSymbols * OFDM_SYMBOL_TIME_QUARTER);
Sujith2660b812009-02-09 13:27:26 +0530193 } else if (ah->curchan &&
194 IS_CHAN_HALF_RATE(ah->curchan)) {
Sujithf1dc5602008-10-29 10:16:30 +0530195 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_HALF) / 1000;
196 numBits = OFDM_PLCP_BITS + (frameLen << 3);
197 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
198 txTime = OFDM_SIFS_TIME_HALF +
199 OFDM_PREAMBLE_TIME_HALF
200 + (numSymbols * OFDM_SYMBOL_TIME_HALF);
201 } else {
202 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME) / 1000;
203 numBits = OFDM_PLCP_BITS + (frameLen << 3);
204 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
205 txTime = OFDM_SIFS_TIME + OFDM_PREAMBLE_TIME
206 + (numSymbols * OFDM_SYMBOL_TIME);
207 }
208 break;
209 default:
Joe Perches38002762010-12-02 19:12:36 -0800210 ath_err(ath9k_hw_common(ah),
211 "Unknown phy %u (rate ix %u)\n", phy, rateix);
Sujithf1dc5602008-10-29 10:16:30 +0530212 txTime = 0;
213 break;
214 }
215
216 return txTime;
217}
Luis R. Rodriguez7322fd12009-09-23 23:07:00 -0400218EXPORT_SYMBOL(ath9k_hw_computetxtime);
Sujithf1dc5602008-10-29 10:16:30 +0530219
Sujithcbe61d82009-02-09 13:27:12 +0530220void ath9k_hw_get_channel_centers(struct ath_hw *ah,
Sujithf1dc5602008-10-29 10:16:30 +0530221 struct ath9k_channel *chan,
222 struct chan_centers *centers)
223{
224 int8_t extoff;
Sujithf1dc5602008-10-29 10:16:30 +0530225
226 if (!IS_CHAN_HT40(chan)) {
227 centers->ctl_center = centers->ext_center =
228 centers->synth_center = chan->channel;
229 return;
230 }
231
Felix Fietkau88969342013-10-11 23:30:53 +0200232 if (IS_CHAN_HT40PLUS(chan)) {
Sujithf1dc5602008-10-29 10:16:30 +0530233 centers->synth_center =
234 chan->channel + HT40_CHANNEL_CENTER_SHIFT;
235 extoff = 1;
236 } else {
237 centers->synth_center =
238 chan->channel - HT40_CHANNEL_CENTER_SHIFT;
239 extoff = -1;
240 }
241
242 centers->ctl_center =
243 centers->synth_center - (extoff * HT40_CHANNEL_CENTER_SHIFT);
Luis R. Rodriguez64200142009-09-13 22:05:04 -0700244 /* 25 MHz spacing is supported by hw but not on upper layers */
Sujithf1dc5602008-10-29 10:16:30 +0530245 centers->ext_center =
Luis R. Rodriguez64200142009-09-13 22:05:04 -0700246 centers->synth_center + (extoff * HT40_CHANNEL_CENTER_SHIFT);
Sujithf1dc5602008-10-29 10:16:30 +0530247}
248
249/******************/
250/* Chip Revisions */
251/******************/
252
Sujithcbe61d82009-02-09 13:27:12 +0530253static void ath9k_hw_read_revisions(struct ath_hw *ah)
Sujithf1dc5602008-10-29 10:16:30 +0530254{
255 u32 val;
256
Felix Fietkau09c74f72014-09-27 22:49:43 +0200257 if (ah->get_mac_revision)
258 ah->hw_version.macRev = ah->get_mac_revision();
259
Vasanthakumar Thiagarajanecb1d382011-04-19 19:29:18 +0530260 switch (ah->hw_version.devid) {
261 case AR5416_AR9100_DEVID:
262 ah->hw_version.macVersion = AR_SREV_VERSION_9100;
263 break;
Gabor Juhos37625612011-06-21 11:23:23 +0200264 case AR9300_DEVID_AR9330:
265 ah->hw_version.macVersion = AR_SREV_VERSION_9330;
Felix Fietkau09c74f72014-09-27 22:49:43 +0200266 if (!ah->get_mac_revision) {
Gabor Juhos37625612011-06-21 11:23:23 +0200267 val = REG_READ(ah, AR_SREV);
268 ah->hw_version.macRev = MS(val, AR_SREV_REVISION2);
269 }
270 return;
Vasanthakumar Thiagarajanecb1d382011-04-19 19:29:18 +0530271 case AR9300_DEVID_AR9340:
272 ah->hw_version.macVersion = AR_SREV_VERSION_9340;
Vasanthakumar Thiagarajanecb1d382011-04-19 19:29:18 +0530273 return;
Gabor Juhos813831d2012-07-03 19:13:17 +0200274 case AR9300_DEVID_QCA955X:
275 ah->hw_version.macVersion = AR_SREV_VERSION_9550;
276 return;
Sujith Manoharane6b1e462013-12-31 08:11:59 +0530277 case AR9300_DEVID_AR953X:
278 ah->hw_version.macVersion = AR_SREV_VERSION_9531;
279 return;
Miaoqing Pan2131fab2014-12-19 06:33:56 +0530280 case AR9300_DEVID_QCA956X:
281 ah->hw_version.macVersion = AR_SREV_VERSION_9561;
Felix Fietkau78655982015-06-21 19:47:46 +0200282 return;
Vasanthakumar Thiagarajanecb1d382011-04-19 19:29:18 +0530283 }
284
Sujithf1dc5602008-10-29 10:16:30 +0530285 val = REG_READ(ah, AR_SREV) & AR_SREV_ID;
286
287 if (val == 0xFF) {
288 val = REG_READ(ah, AR_SREV);
Sujithd535a422009-02-09 13:27:06 +0530289 ah->hw_version.macVersion =
290 (val & AR_SREV_VERSION2) >> AR_SREV_TYPE2_S;
291 ah->hw_version.macRev = MS(val, AR_SREV_REVISION2);
Mohammed Shafi Shajakhan76ed94b2011-09-30 11:31:28 +0530292
Sujith Manoharan77fac462012-09-11 20:09:18 +0530293 if (AR_SREV_9462(ah) || AR_SREV_9565(ah))
Mohammed Shafi Shajakhan76ed94b2011-09-30 11:31:28 +0530294 ah->is_pciexpress = true;
295 else
296 ah->is_pciexpress = (val &
297 AR_SREV_TYPE2_HOST_MODE) ? 0 : 1;
Sujithf1dc5602008-10-29 10:16:30 +0530298 } else {
299 if (!AR_SREV_9100(ah))
Sujithd535a422009-02-09 13:27:06 +0530300 ah->hw_version.macVersion = MS(val, AR_SREV_VERSION);
Sujithf1dc5602008-10-29 10:16:30 +0530301
Sujithd535a422009-02-09 13:27:06 +0530302 ah->hw_version.macRev = val & AR_SREV_REVISION;
Sujithf1dc5602008-10-29 10:16:30 +0530303
Sujithd535a422009-02-09 13:27:06 +0530304 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCIE)
Sujith2660b812009-02-09 13:27:26 +0530305 ah->is_pciexpress = true;
Sujithf1dc5602008-10-29 10:16:30 +0530306 }
307}
308
Sujithf1dc5602008-10-29 10:16:30 +0530309/************************************/
310/* HW Attach, Detach, Init Routines */
311/************************************/
312
Sujithcbe61d82009-02-09 13:27:12 +0530313static void ath9k_hw_disablepcie(struct ath_hw *ah)
Sujithf1dc5602008-10-29 10:16:30 +0530314{
Felix Fietkau040b74f2010-12-12 00:51:07 +0100315 if (!AR_SREV_5416(ah))
Sujithf1dc5602008-10-29 10:16:30 +0530316 return;
317
318 REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00);
319 REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
320 REG_WRITE(ah, AR_PCIE_SERDES, 0x28000029);
321 REG_WRITE(ah, AR_PCIE_SERDES, 0x57160824);
322 REG_WRITE(ah, AR_PCIE_SERDES, 0x25980579);
323 REG_WRITE(ah, AR_PCIE_SERDES, 0x00000000);
324 REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
325 REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
326 REG_WRITE(ah, AR_PCIE_SERDES, 0x000e1007);
327
328 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
329}
330
Senthil Balasubramanian1f3f0612010-04-15 17:38:29 -0400331/* This should work for all families including legacy */
Sujithcbe61d82009-02-09 13:27:12 +0530332static bool ath9k_hw_chip_test(struct ath_hw *ah)
Sujithf1dc5602008-10-29 10:16:30 +0530333{
Luis R. Rodriguezc46917b2009-09-13 02:42:02 -0700334 struct ath_common *common = ath9k_hw_common(ah);
Senthil Balasubramanian1f3f0612010-04-15 17:38:29 -0400335 u32 regAddr[2] = { AR_STA_ID0 };
Sujithf1dc5602008-10-29 10:16:30 +0530336 u32 regHold[2];
Joe Perches07b2fa52010-11-20 18:38:53 -0800337 static const u32 patternData[4] = {
338 0x55555555, 0xaaaaaaaa, 0x66666666, 0x99999999
339 };
Senthil Balasubramanian1f3f0612010-04-15 17:38:29 -0400340 int i, j, loop_max;
Sujithf1dc5602008-10-29 10:16:30 +0530341
Senthil Balasubramanian1f3f0612010-04-15 17:38:29 -0400342 if (!AR_SREV_9300_20_OR_LATER(ah)) {
343 loop_max = 2;
344 regAddr[1] = AR_PHY_BASE + (8 << 2);
345 } else
346 loop_max = 1;
347
348 for (i = 0; i < loop_max; i++) {
Sujithf1dc5602008-10-29 10:16:30 +0530349 u32 addr = regAddr[i];
350 u32 wrData, rdData;
351
352 regHold[i] = REG_READ(ah, addr);
353 for (j = 0; j < 0x100; j++) {
354 wrData = (j << 16) | j;
355 REG_WRITE(ah, addr, wrData);
356 rdData = REG_READ(ah, addr);
357 if (rdData != wrData) {
Joe Perches38002762010-12-02 19:12:36 -0800358 ath_err(common,
359 "address test failed addr: 0x%08x - wr:0x%08x != rd:0x%08x\n",
360 addr, wrData, rdData);
Sujithf1dc5602008-10-29 10:16:30 +0530361 return false;
362 }
363 }
364 for (j = 0; j < 4; j++) {
365 wrData = patternData[j];
366 REG_WRITE(ah, addr, wrData);
367 rdData = REG_READ(ah, addr);
368 if (wrData != rdData) {
Joe Perches38002762010-12-02 19:12:36 -0800369 ath_err(common,
370 "address test failed addr: 0x%08x - wr:0x%08x != rd:0x%08x\n",
371 addr, wrData, rdData);
Sujithf1dc5602008-10-29 10:16:30 +0530372 return false;
373 }
374 }
375 REG_WRITE(ah, regAddr[i], regHold[i]);
376 }
377 udelay(100);
Sujithcbe61d82009-02-09 13:27:12 +0530378
Sujithf1dc5602008-10-29 10:16:30 +0530379 return true;
380}
381
Luis R. Rodriguezb8b0f372009-08-03 12:24:43 -0700382static void ath9k_hw_init_config(struct ath_hw *ah)
Luis R. Rodriguezf078f202008-08-04 00:16:41 -0700383{
Sujith Manoharanf57cf932013-12-28 09:47:12 +0530384 struct ath_common *common = ath9k_hw_common(ah);
385
Felix Fietkau689e7562012-04-12 22:35:56 +0200386 ah->config.dma_beacon_response_time = 1;
387 ah->config.sw_beacon_response_time = 6;
Viresh Kumar621a5f72015-09-26 15:04:07 -0700388 ah->config.cwm_ignore_extcca = false;
Sujith2660b812009-02-09 13:27:26 +0530389 ah->config.analog_shiftreg = 1;
Luis R. Rodriguezf078f202008-08-04 00:16:41 -0700390
Sujith0ce024c2009-12-14 14:57:00 +0530391 ah->config.rx_intr_mitigation = true;
Luis R. Rodriguez61584252009-03-12 18:18:49 -0400392
Sujith Manoharana64e1a42014-01-23 08:20:30 +0530393 if (AR_SREV_9300_20_OR_LATER(ah)) {
394 ah->config.rimt_last = 500;
395 ah->config.rimt_first = 2000;
396 } else {
397 ah->config.rimt_last = 250;
398 ah->config.rimt_first = 700;
399 }
400
Sujith Manoharan656cd752015-03-09 14:20:08 +0530401 if (AR_SREV_9462(ah) || AR_SREV_9565(ah))
402 ah->config.pll_pwrsave = 7;
403
Luis R. Rodriguez61584252009-03-12 18:18:49 -0400404 /*
405 * We need this for PCI devices only (Cardbus, PCI, miniPCI)
406 * _and_ if on non-uniprocessor systems (Multiprocessor/HT).
407 * This means we use it for all AR5416 devices, and the few
408 * minor PCI AR9280 devices out there.
409 *
410 * Serialization is required because these devices do not handle
411 * well the case of two concurrent reads/writes due to the latency
412 * involved. During one read/write another read/write can be issued
413 * on another CPU while the previous read/write may still be working
414 * on our hardware, if we hit this case the hardware poops in a loop.
415 * We prevent this by serializing reads and writes.
416 *
417 * This issue is not present on PCI-Express devices or pre-AR5416
418 * devices (legacy, 802.11abg).
419 */
420 if (num_possible_cpus() > 1)
David S. Miller2d6a5e92009-03-17 15:01:30 -0700421 ah->config.serialize_regmode = SER_REG_MODE_AUTO;
Sujith Manoharanf57cf932013-12-28 09:47:12 +0530422
423 if (NR_CPUS > 1 && ah->config.serialize_regmode == SER_REG_MODE_AUTO) {
424 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCI ||
425 ((AR_SREV_9160(ah) || AR_SREV_9280(ah) || AR_SREV_9287(ah)) &&
426 !ah->is_pciexpress)) {
427 ah->config.serialize_regmode = SER_REG_MODE_ON;
428 } else {
429 ah->config.serialize_regmode = SER_REG_MODE_OFF;
430 }
431 }
432
433 ath_dbg(common, RESET, "serialize_regmode is %d\n",
434 ah->config.serialize_regmode);
435
436 if (AR_SREV_9285(ah) || AR_SREV_9271(ah))
437 ah->config.max_txtrig_level = MAX_TX_FIFO_THRESHOLD >> 1;
438 else
439 ah->config.max_txtrig_level = MAX_TX_FIFO_THRESHOLD;
Luis R. Rodriguezf078f202008-08-04 00:16:41 -0700440}
441
Luis R. Rodriguez50aca252009-08-03 12:24:42 -0700442static void ath9k_hw_init_defaults(struct ath_hw *ah)
Luis R. Rodriguezf078f202008-08-04 00:16:41 -0700443{
Luis R. Rodriguez608b88c2009-08-17 18:07:23 -0700444 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
445
446 regulatory->country_code = CTRY_DEFAULT;
447 regulatory->power_limit = MAX_RATE_POWER;
Luis R. Rodriguez608b88c2009-08-17 18:07:23 -0700448
Sujithd535a422009-02-09 13:27:06 +0530449 ah->hw_version.magic = AR5416_MAGIC;
Sujithd535a422009-02-09 13:27:06 +0530450 ah->hw_version.subvendorid = 0;
Luis R. Rodriguezf078f202008-08-04 00:16:41 -0700451
Sujith Manoharanf57cf932013-12-28 09:47:12 +0530452 ah->sta_id1_defaults = AR_STA_ID1_CRPT_MIC_ENABLE |
453 AR_STA_ID1_MCAST_KSRCH;
Felix Fietkauf1717602011-03-19 13:55:41 +0100454 if (AR_SREV_9100(ah))
455 ah->sta_id1_defaults |= AR_STA_ID1_AR9100_BA_FIX;
Sujith Manoharanf57cf932013-12-28 09:47:12 +0530456
Benjamin Berg11b0ac22016-07-04 14:37:24 +0200457 ah->slottime = 9;
Sujith2660b812009-02-09 13:27:26 +0530458 ah->globaltxtimeout = (u32) -1;
Gabor Juhoscbdec972009-07-24 17:27:22 +0200459 ah->power_mode = ATH9K_PM_UNDEFINED;
Felix Fietkau8efa7a82012-03-14 16:40:23 +0100460 ah->htc_reset_init = true;
Sujith Manoharanf57cf932013-12-28 09:47:12 +0530461
Felix Fietkauc09396e2015-03-15 08:07:04 +0100462 ah->tpc_enabled = false;
Lorenzo Bianconia9abe302014-12-19 00:18:12 +0100463
Sujith Manoharanf57cf932013-12-28 09:47:12 +0530464 ah->ani_function = ATH9K_ANI_ALL;
465 if (!AR_SREV_9300_20_OR_LATER(ah))
466 ah->ani_function &= ~ATH9K_ANI_MRC_CCK;
467
468 if (AR_SREV_9285(ah) || AR_SREV_9271(ah))
469 ah->tx_trig_level = (AR_FTRIG_256B >> AR_FTRIG_S);
470 else
471 ah->tx_trig_level = (AR_FTRIG_512B >> AR_FTRIG_S);
Luis R. Rodriguezf078f202008-08-04 00:16:41 -0700472}
473
Martin Blumenstingld323cb72016-06-23 16:57:12 +0200474static void ath9k_hw_init_macaddr(struct ath_hw *ah)
Luis R. Rodriguezf078f202008-08-04 00:16:41 -0700475{
Luis R. Rodriguez15107182009-09-10 09:22:37 -0700476 struct ath_common *common = ath9k_hw_common(ah);
Luis R. Rodriguezf078f202008-08-04 00:16:41 -0700477 int i;
Sujithf1dc5602008-10-29 10:16:30 +0530478 u16 eeval;
Joe Perches07b2fa52010-11-20 18:38:53 -0800479 static const u32 EEP_MAC[] = { EEP_MAC_LSW, EEP_MAC_MID, EEP_MAC_MSW };
Luis R. Rodriguezf078f202008-08-04 00:16:41 -0700480
Martin Blumenstingl0cefa972016-06-23 16:57:11 +0200481 /* MAC address may already be loaded via ath9k_platform_data */
482 if (is_valid_ether_addr(common->macaddr))
Martin Blumenstingld323cb72016-06-23 16:57:12 +0200483 return;
Martin Blumenstingl0cefa972016-06-23 16:57:11 +0200484
Sujithf1dc5602008-10-29 10:16:30 +0530485 for (i = 0; i < 3; i++) {
Luis R. Rodriguez49101672010-04-15 17:39:13 -0400486 eeval = ah->eep_ops->get_eeprom(ah, EEP_MAC[i]);
Luis R. Rodriguez15107182009-09-10 09:22:37 -0700487 common->macaddr[2 * i] = eeval >> 8;
488 common->macaddr[2 * i + 1] = eeval & 0xff;
Luis R. Rodriguezf078f202008-08-04 00:16:41 -0700489 }
Felix Fietkau5ca06eb2014-10-25 17:19:35 +0200490
Martin Blumenstingl0cefa972016-06-23 16:57:11 +0200491 if (is_valid_ether_addr(common->macaddr))
Martin Blumenstingld323cb72016-06-23 16:57:12 +0200492 return;
Martin Blumenstingl0cefa972016-06-23 16:57:11 +0200493
494 ath_err(common, "eeprom contains invalid mac address: %pM\n",
495 common->macaddr);
496
497 random_ether_addr(common->macaddr);
498 ath_err(common, "random mac address will be used: %pM\n",
499 common->macaddr);
Luis R. Rodriguezf078f202008-08-04 00:16:41 -0700500
Martin Blumenstingld323cb72016-06-23 16:57:12 +0200501 return;
Luis R. Rodriguezf078f202008-08-04 00:16:41 -0700502}
503
Luis R. Rodriguezf637cfd2009-08-03 12:24:46 -0700504static int ath9k_hw_post_init(struct ath_hw *ah)
Luis R. Rodriguezf078f202008-08-04 00:16:41 -0700505{
Sujith Manoharan6cae913d2011-01-04 13:16:37 +0530506 struct ath_common *common = ath9k_hw_common(ah);
Luis R. Rodriguezf078f202008-08-04 00:16:41 -0700507 int ecode;
508
Sujith Manoharan6cae913d2011-01-04 13:16:37 +0530509 if (common->bus_ops->ath_bus_type != ATH_USB) {
Sujith527d4852010-03-17 14:25:16 +0530510 if (!ath9k_hw_chip_test(ah))
511 return -ENODEV;
512 }
Luis R. Rodriguezf078f202008-08-04 00:16:41 -0700513
Luis R. Rodriguezebd5a142010-04-15 17:39:18 -0400514 if (!AR_SREV_9300_20_OR_LATER(ah)) {
515 ecode = ar9002_hw_rf_claim(ah);
516 if (ecode != 0)
517 return ecode;
518 }
Luis R. Rodriguezf078f202008-08-04 00:16:41 -0700519
Luis R. Rodriguezf637cfd2009-08-03 12:24:46 -0700520 ecode = ath9k_hw_eeprom_init(ah);
Luis R. Rodriguezf078f202008-08-04 00:16:41 -0700521 if (ecode != 0)
522 return ecode;
Sujith7d01b222009-03-13 08:55:55 +0530523
Joe Perchesd2182b62011-12-15 14:55:53 -0800524 ath_dbg(ath9k_hw_common(ah), CONFIG, "Eeprom VER: %d, REV: %d\n",
Joe Perches226afe62010-12-02 19:12:37 -0800525 ah->eep_ops->get_eeprom_ver(ah),
526 ah->eep_ops->get_eeprom_rev(ah));
Sujith7d01b222009-03-13 08:55:55 +0530527
Sujith Manoharane3233002013-06-03 09:19:26 +0530528 ath9k_hw_ani_init(ah);
Sujithf1dc5602008-10-29 10:16:30 +0530529
Sujith Manoharand3b371c2013-09-03 10:28:55 +0530530 /*
531 * EEPROM needs to be initialized before we do this.
532 * This is required for regulatory compliance.
533 */
Sujith Manoharan0c7c2bb2013-12-06 16:28:50 +0530534 if (AR_SREV_9300_20_OR_LATER(ah)) {
Sujith Manoharand3b371c2013-09-03 10:28:55 +0530535 u16 regdmn = ah->eep_ops->get_eeprom(ah, EEP_REG_0);
536 if ((regdmn & 0xF0) == CTL_FCC) {
Sujith Manoharan0c7c2bb2013-12-06 16:28:50 +0530537 ah->nf_2g.max = AR_PHY_CCA_MAX_GOOD_VAL_9300_FCC_2GHZ;
538 ah->nf_5g.max = AR_PHY_CCA_MAX_GOOD_VAL_9300_FCC_5GHZ;
Sujith Manoharand3b371c2013-09-03 10:28:55 +0530539 }
540 }
541
Luis R. Rodriguezf078f202008-08-04 00:16:41 -0700542 return 0;
543}
544
Felix Fietkauc1b976d2012-12-12 13:14:23 +0100545static int ath9k_hw_attach_ops(struct ath_hw *ah)
Luis R. Rodriguezee2bb462009-08-03 12:24:39 -0700546{
Felix Fietkauc1b976d2012-12-12 13:14:23 +0100547 if (!AR_SREV_9300_20_OR_LATER(ah))
548 return ar9002_hw_attach_ops(ah);
549
550 ar9003_hw_attach_ops(ah);
551 return 0;
Luis R. Rodriguezee2bb462009-08-03 12:24:39 -0700552}
553
Luis R. Rodriguezd70357d2010-04-15 17:38:06 -0400554/* Called for all hardware families */
555static int __ath9k_hw_init(struct ath_hw *ah)
Luis R. Rodriguezaa4058a2009-08-03 12:24:45 -0700556{
Luis R. Rodriguezc46917b2009-09-13 02:42:02 -0700557 struct ath_common *common = ath9k_hw_common(ah);
Luis R. Rodriguez95fafca2009-08-03 12:24:54 -0700558 int r = 0;
Luis R. Rodriguezaa4058a2009-08-03 12:24:45 -0700559
Senthil Balasubramanianac45c122010-12-22 21:14:20 +0530560 ath9k_hw_read_revisions(ah);
561
Sujith Manoharande825822013-12-28 09:47:11 +0530562 switch (ah->hw_version.macVersion) {
563 case AR_SREV_VERSION_5416_PCI:
564 case AR_SREV_VERSION_5416_PCIE:
565 case AR_SREV_VERSION_9160:
566 case AR_SREV_VERSION_9100:
567 case AR_SREV_VERSION_9280:
568 case AR_SREV_VERSION_9285:
569 case AR_SREV_VERSION_9287:
570 case AR_SREV_VERSION_9271:
571 case AR_SREV_VERSION_9300:
572 case AR_SREV_VERSION_9330:
573 case AR_SREV_VERSION_9485:
574 case AR_SREV_VERSION_9340:
575 case AR_SREV_VERSION_9462:
576 case AR_SREV_VERSION_9550:
577 case AR_SREV_VERSION_9565:
Sujith Manoharane6b1e462013-12-31 08:11:59 +0530578 case AR_SREV_VERSION_9531:
Miaoqing Pan2131fab2014-12-19 06:33:56 +0530579 case AR_SREV_VERSION_9561:
Sujith Manoharande825822013-12-28 09:47:11 +0530580 break;
581 default:
582 ath_err(common,
583 "Mac Chip Rev 0x%02x.%x is not supported by this driver\n",
584 ah->hw_version.macVersion, ah->hw_version.macRev);
585 return -EOPNOTSUPP;
586 }
587
Senthil Balasubramanian0a8d7cb2010-12-22 19:17:18 +0530588 /*
589 * Read back AR_WA into a permanent copy and set bits 14 and 17.
590 * We need to do this to avoid RMW of this register. We cannot
591 * read the reg when chip is asleep.
592 */
Sujith Manoharan27251e02013-08-27 11:34:39 +0530593 if (AR_SREV_9300_20_OR_LATER(ah)) {
594 ah->WARegVal = REG_READ(ah, AR_WA);
595 ah->WARegVal |= (AR_WA_D3_L1_DISABLE |
596 AR_WA_ASPM_TIMER_BASED_DISABLE);
597 }
Senthil Balasubramanian0a8d7cb2010-12-22 19:17:18 +0530598
Luis R. Rodriguezaa4058a2009-08-03 12:24:45 -0700599 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)) {
Joe Perches38002762010-12-02 19:12:36 -0800600 ath_err(common, "Couldn't reset chip\n");
Luis R. Rodriguez95fafca2009-08-03 12:24:54 -0700601 return -EIO;
Luis R. Rodriguezaa4058a2009-08-03 12:24:45 -0700602 }
603
Sujith Manoharana4a29542012-09-10 09:20:03 +0530604 if (AR_SREV_9565(ah)) {
605 ah->WARegVal |= AR_WA_BIT22;
606 REG_WRITE(ah, AR_WA, ah->WARegVal);
607 }
608
Luis R. Rodriguezbab1f622010-04-15 17:38:20 -0400609 ath9k_hw_init_defaults(ah);
610 ath9k_hw_init_config(ah);
611
Felix Fietkauc1b976d2012-12-12 13:14:23 +0100612 r = ath9k_hw_attach_ops(ah);
613 if (r)
614 return r;
Luis R. Rodriguezd70357d2010-04-15 17:38:06 -0400615
Luis R. Rodriguez9ecdef42009-09-09 21:10:09 -0700616 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) {
Joe Perches38002762010-12-02 19:12:36 -0800617 ath_err(common, "Couldn't wakeup chip\n");
Luis R. Rodriguez95fafca2009-08-03 12:24:54 -0700618 return -EIO;
Luis R. Rodriguezaa4058a2009-08-03 12:24:45 -0700619 }
620
Gabor Juhos2c8e5932011-06-21 11:23:21 +0200621 if (AR_SREV_9271(ah) || AR_SREV_9100(ah) || AR_SREV_9340(ah) ||
Gabor Juhosc95b5842012-07-03 19:13:20 +0200622 AR_SREV_9330(ah) || AR_SREV_9550(ah))
Luis R. Rodriguezd7e7d222009-08-03 23:14:12 -0400623 ah->is_pciexpress = false;
624
Luis R. Rodriguezaa4058a2009-08-03 12:24:45 -0700625 ah->hw_version.phyRev = REG_READ(ah, AR_PHY_CHIP_ID);
Luis R. Rodriguezaa4058a2009-08-03 12:24:45 -0700626 ath9k_hw_init_cal_settings(ah);
627
Stanislaw Gruszka69ce6742011-08-05 13:10:34 +0200628 if (!ah->is_pciexpress)
Luis R. Rodriguezaa4058a2009-08-03 12:24:45 -0700629 ath9k_hw_disablepcie(ah);
630
Luis R. Rodriguezf637cfd2009-08-03 12:24:46 -0700631 r = ath9k_hw_post_init(ah);
Luis R. Rodriguezaa4058a2009-08-03 12:24:45 -0700632 if (r)
Luis R. Rodriguez95fafca2009-08-03 12:24:54 -0700633 return r;
Luis R. Rodriguezaa4058a2009-08-03 12:24:45 -0700634
635 ath9k_hw_init_mode_gain_regs(ah);
Gabor Juhosa9a29ce2009-11-27 12:01:35 +0100636 r = ath9k_hw_fill_cap_info(ah);
637 if (r)
638 return r;
639
Martin Blumenstingld323cb72016-06-23 16:57:12 +0200640 ath9k_hw_init_macaddr(ah);
Sujith Manoharan45987022013-12-24 10:44:18 +0530641 ath9k_hw_init_hang_checks(ah);
Luis R. Rodriguezf078f202008-08-04 00:16:41 -0700642
Luis R. Rodriguez211f5852009-10-06 21:19:07 -0400643 common->state = ATH_HW_INITIALIZED;
644
Luis R. Rodriguez4f3acf82009-08-03 12:24:36 -0700645 return 0;
Luis R. Rodriguezf078f202008-08-04 00:16:41 -0700646}
647
Luis R. Rodriguezd70357d2010-04-15 17:38:06 -0400648int ath9k_hw_init(struct ath_hw *ah)
Sujithf1dc5602008-10-29 10:16:30 +0530649{
Luis R. Rodriguezd70357d2010-04-15 17:38:06 -0400650 int ret;
651 struct ath_common *common = ath9k_hw_common(ah);
Sujithf1dc5602008-10-29 10:16:30 +0530652
Sujith Manoharan77fac462012-09-11 20:09:18 +0530653 /* These are all the AR5008/AR9001/AR9002/AR9003 hardware family of chipsets */
Luis R. Rodriguezd70357d2010-04-15 17:38:06 -0400654 switch (ah->hw_version.devid) {
655 case AR5416_DEVID_PCI:
656 case AR5416_DEVID_PCIE:
657 case AR5416_AR9100_DEVID:
658 case AR9160_DEVID_PCI:
659 case AR9280_DEVID_PCI:
660 case AR9280_DEVID_PCIE:
661 case AR9285_DEVID_PCIE:
Senthil Balasubramaniandb3cc532010-04-15 17:38:18 -0400662 case AR9287_DEVID_PCI:
663 case AR9287_DEVID_PCIE:
Luis R. Rodriguezd70357d2010-04-15 17:38:06 -0400664 case AR2427_DEVID_PCIE:
Senthil Balasubramaniandb3cc532010-04-15 17:38:18 -0400665 case AR9300_DEVID_PCIE:
Vasanthakumar Thiagarajan3050c912010-12-06 04:27:36 -0800666 case AR9300_DEVID_AR9485_PCIE:
Gabor Juhos999a7a82011-06-21 11:23:52 +0200667 case AR9300_DEVID_AR9330:
Vasanthakumar Thiagarajanbca04682011-04-19 19:29:20 +0530668 case AR9300_DEVID_AR9340:
Gabor Juhos2b943a32012-07-03 19:13:34 +0200669 case AR9300_DEVID_QCA955X:
Luis R. Rodriguez5a63ef02011-08-24 15:36:08 -0700670 case AR9300_DEVID_AR9580:
Rajkumar Manoharan423e38e2011-10-13 11:00:44 +0530671 case AR9300_DEVID_AR9462:
Mohammed Shafi Shajakhand4e59792012-08-02 11:58:50 +0530672 case AR9485_DEVID_AR1111:
Sujith Manoharan77fac462012-09-11 20:09:18 +0530673 case AR9300_DEVID_AR9565:
Sujith Manoharane6b1e462013-12-31 08:11:59 +0530674 case AR9300_DEVID_AR953X:
Miaoqing Pan2131fab2014-12-19 06:33:56 +0530675 case AR9300_DEVID_QCA956X:
Luis R. Rodriguezd70357d2010-04-15 17:38:06 -0400676 break;
677 default:
678 if (common->bus_ops->ath_bus_type == ATH_USB)
679 break;
Joe Perches38002762010-12-02 19:12:36 -0800680 ath_err(common, "Hardware device ID 0x%04x not supported\n",
681 ah->hw_version.devid);
Luis R. Rodriguezd70357d2010-04-15 17:38:06 -0400682 return -EOPNOTSUPP;
683 }
Sujithf1dc5602008-10-29 10:16:30 +0530684
Luis R. Rodriguezd70357d2010-04-15 17:38:06 -0400685 ret = __ath9k_hw_init(ah);
686 if (ret) {
Joe Perches38002762010-12-02 19:12:36 -0800687 ath_err(common,
688 "Unable to initialize hardware; initialization status: %d\n",
689 ret);
Luis R. Rodriguezd70357d2010-04-15 17:38:06 -0400690 return ret;
691 }
Sujithf1dc5602008-10-29 10:16:30 +0530692
Lorenzo Bianconic774d572014-09-16 02:13:09 +0200693 ath_dynack_init(ah);
694
Luis R. Rodriguezd70357d2010-04-15 17:38:06 -0400695 return 0;
Sujithf1dc5602008-10-29 10:16:30 +0530696}
Luis R. Rodriguezd70357d2010-04-15 17:38:06 -0400697EXPORT_SYMBOL(ath9k_hw_init);
Sujithf1dc5602008-10-29 10:16:30 +0530698
Sujithcbe61d82009-02-09 13:27:12 +0530699static void ath9k_hw_init_qos(struct ath_hw *ah)
Sujithf1dc5602008-10-29 10:16:30 +0530700{
Sujith7d0d0df2010-04-16 11:53:57 +0530701 ENABLE_REGWRITE_BUFFER(ah);
702
Sujithf1dc5602008-10-29 10:16:30 +0530703 REG_WRITE(ah, AR_MIC_QOS_CONTROL, 0x100aa);
704 REG_WRITE(ah, AR_MIC_QOS_SELECT, 0x3210);
705
706 REG_WRITE(ah, AR_QOS_NO_ACK,
707 SM(2, AR_QOS_NO_ACK_TWO_BIT) |
708 SM(5, AR_QOS_NO_ACK_BIT_OFF) |
709 SM(0, AR_QOS_NO_ACK_BYTE_OFF));
710
711 REG_WRITE(ah, AR_TXOP_X, AR_TXOP_X_VAL);
712 REG_WRITE(ah, AR_TXOP_0_3, 0xFFFFFFFF);
713 REG_WRITE(ah, AR_TXOP_4_7, 0xFFFFFFFF);
714 REG_WRITE(ah, AR_TXOP_8_11, 0xFFFFFFFF);
715 REG_WRITE(ah, AR_TXOP_12_15, 0xFFFFFFFF);
Sujith7d0d0df2010-04-16 11:53:57 +0530716
717 REGWRITE_BUFFER_FLUSH(ah);
Sujithf1dc5602008-10-29 10:16:30 +0530718}
719
Senthil Balasubramanianb84628e2011-04-22 11:32:12 +0530720u32 ar9003_get_pll_sqsum_dvc(struct ath_hw *ah)
Vivek Natarajanb1415812011-01-27 14:45:07 +0530721{
Mohammed Shafi Shajakhanf18e3c62012-06-18 13:13:30 +0530722 struct ath_common *common = ath9k_hw_common(ah);
723 int i = 0;
724
Felix Fietkauca7a4de2011-03-23 20:57:26 +0100725 REG_CLR_BIT(ah, PLL3, PLL3_DO_MEAS_MASK);
726 udelay(100);
727 REG_SET_BIT(ah, PLL3, PLL3_DO_MEAS_MASK);
728
Mohammed Shafi Shajakhanf18e3c62012-06-18 13:13:30 +0530729 while ((REG_READ(ah, PLL4) & PLL4_MEAS_DONE) == 0) {
730
Vivek Natarajanb1415812011-01-27 14:45:07 +0530731 udelay(100);
Vivek Natarajanb1415812011-01-27 14:45:07 +0530732
Mohammed Shafi Shajakhanf18e3c62012-06-18 13:13:30 +0530733 if (WARN_ON_ONCE(i >= 100)) {
734 ath_err(common, "PLL4 meaurement not done\n");
735 break;
736 }
737
738 i++;
739 }
740
Felix Fietkauca7a4de2011-03-23 20:57:26 +0100741 return (REG_READ(ah, PLL3) & SQSUM_DVC_MASK) >> 3;
Vivek Natarajanb1415812011-01-27 14:45:07 +0530742}
743EXPORT_SYMBOL(ar9003_get_pll_sqsum_dvc);
744
Sujithcbe61d82009-02-09 13:27:12 +0530745static void ath9k_hw_init_pll(struct ath_hw *ah,
Sujithf1dc5602008-10-29 10:16:30 +0530746 struct ath9k_channel *chan)
747{
Vasanthakumar Thiagarajand09b17f2010-12-06 04:27:44 -0800748 u32 pll;
749
Felix Fietkau5fb9b1b2014-09-29 20:45:42 +0200750 pll = ath9k_hw_compute_pll_control(ah, chan);
751
Sujith Manoharana4a29542012-09-10 09:20:03 +0530752 if (AR_SREV_9485(ah) || AR_SREV_9565(ah)) {
Vasanthakumar Thiagarajan3dfd7f62011-04-11 16:39:40 +0530753 /* program BB PLL ki and kd value, ki=0x4, kd=0x40 */
754 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
755 AR_CH0_BB_DPLL2_PLL_PWD, 0x1);
756 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
757 AR_CH0_DPLL2_KD, 0x40);
758 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
759 AR_CH0_DPLL2_KI, 0x4);
Vivek Natarajan22983c32011-01-27 14:45:09 +0530760
Vasanthakumar Thiagarajan3dfd7f62011-04-11 16:39:40 +0530761 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL1,
762 AR_CH0_BB_DPLL1_REFDIV, 0x5);
763 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL1,
764 AR_CH0_BB_DPLL1_NINI, 0x58);
765 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL1,
766 AR_CH0_BB_DPLL1_NFRAC, 0x0);
767
768 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
769 AR_CH0_BB_DPLL2_OUTDIV, 0x1);
770 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
771 AR_CH0_BB_DPLL2_LOCAL_PLL, 0x1);
772 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
773 AR_CH0_BB_DPLL2_EN_NEGTRIG, 0x1);
774
775 /* program BB PLL phase_shift to 0x6 */
776 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL3,
777 AR_CH0_BB_DPLL3_PHASE_SHIFT, 0x6);
778
779 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
780 AR_CH0_BB_DPLL2_PLL_PWD, 0x0);
Vivek Natarajan75e03512011-03-10 11:05:42 +0530781 udelay(1000);
Gabor Juhosa5415d62011-06-21 11:23:29 +0200782 } else if (AR_SREV_9330(ah)) {
783 u32 ddr_dpll2, pll_control2, kd;
784
785 if (ah->is_clk_25mhz) {
786 ddr_dpll2 = 0x18e82f01;
787 pll_control2 = 0xe04a3d;
788 kd = 0x1d;
789 } else {
790 ddr_dpll2 = 0x19e82f01;
791 pll_control2 = 0x886666;
792 kd = 0x3d;
793 }
794
795 /* program DDR PLL ki and kd value */
796 REG_WRITE(ah, AR_CH0_DDR_DPLL2, ddr_dpll2);
797
798 /* program DDR PLL phase_shift */
799 REG_RMW_FIELD(ah, AR_CH0_DDR_DPLL3,
800 AR_CH0_DPLL3_PHASE_SHIFT, 0x1);
801
Felix Fietkau5fb9b1b2014-09-29 20:45:42 +0200802 REG_WRITE(ah, AR_RTC_PLL_CONTROL,
803 pll | AR_RTC_9300_PLL_BYPASS);
Gabor Juhosa5415d62011-06-21 11:23:29 +0200804 udelay(1000);
805
806 /* program refdiv, nint, frac to RTC register */
807 REG_WRITE(ah, AR_RTC_PLL_CONTROL2, pll_control2);
808
809 /* program BB PLL kd and ki value */
810 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, AR_CH0_DPLL2_KD, kd);
811 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, AR_CH0_DPLL2_KI, 0x06);
812
813 /* program BB PLL phase_shift */
814 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL3,
815 AR_CH0_BB_DPLL3_PHASE_SHIFT, 0x1);
Miaoqing Panede6a5e2014-12-19 06:33:59 +0530816 } else if (AR_SREV_9340(ah) || AR_SREV_9550(ah) || AR_SREV_9531(ah) ||
817 AR_SREV_9561(ah)) {
Vasanthakumar Thiagarajan0b488ac2011-04-20 10:26:15 +0530818 u32 regval, pll2_divint, pll2_divfrac, refdiv;
819
Felix Fietkau5fb9b1b2014-09-29 20:45:42 +0200820 REG_WRITE(ah, AR_RTC_PLL_CONTROL,
821 pll | AR_RTC_9300_SOC_PLL_BYPASS);
Vasanthakumar Thiagarajan0b488ac2011-04-20 10:26:15 +0530822 udelay(1000);
823
824 REG_SET_BIT(ah, AR_PHY_PLL_MODE, 0x1 << 16);
825 udelay(100);
826
827 if (ah->is_clk_25mhz) {
Miaoqing Panede6a5e2014-12-19 06:33:59 +0530828 if (AR_SREV_9531(ah) || AR_SREV_9561(ah)) {
Sujith Manoharan2c323052013-12-31 08:12:02 +0530829 pll2_divint = 0x1c;
830 pll2_divfrac = 0xa3d2;
831 refdiv = 1;
832 } else {
833 pll2_divint = 0x54;
834 pll2_divfrac = 0x1eb85;
835 refdiv = 3;
836 }
Vasanthakumar Thiagarajan0b488ac2011-04-20 10:26:15 +0530837 } else {
Gabor Juhosfc05a312012-07-03 19:13:31 +0200838 if (AR_SREV_9340(ah)) {
839 pll2_divint = 88;
840 pll2_divfrac = 0;
841 refdiv = 5;
842 } else {
843 pll2_divint = 0x11;
Miaoqing Panede6a5e2014-12-19 06:33:59 +0530844 pll2_divfrac = (AR_SREV_9531(ah) ||
845 AR_SREV_9561(ah)) ?
846 0x26665 : 0x26666;
Gabor Juhosfc05a312012-07-03 19:13:31 +0200847 refdiv = 1;
848 }
Vasanthakumar Thiagarajan0b488ac2011-04-20 10:26:15 +0530849 }
850
851 regval = REG_READ(ah, AR_PHY_PLL_MODE);
Miaoqing Panede6a5e2014-12-19 06:33:59 +0530852 if (AR_SREV_9531(ah) || AR_SREV_9561(ah))
Sujith Manoharan2c323052013-12-31 08:12:02 +0530853 regval |= (0x1 << 22);
854 else
855 regval |= (0x1 << 16);
Vasanthakumar Thiagarajan0b488ac2011-04-20 10:26:15 +0530856 REG_WRITE(ah, AR_PHY_PLL_MODE, regval);
857 udelay(100);
858
859 REG_WRITE(ah, AR_PHY_PLL_CONTROL, (refdiv << 27) |
860 (pll2_divint << 18) | pll2_divfrac);
861 udelay(100);
862
863 regval = REG_READ(ah, AR_PHY_PLL_MODE);
Gabor Juhosfc05a312012-07-03 19:13:31 +0200864 if (AR_SREV_9340(ah))
Sujith Manoharan2c323052013-12-31 08:12:02 +0530865 regval = (regval & 0x80071fff) |
866 (0x1 << 30) |
867 (0x1 << 13) |
868 (0x4 << 26) |
869 (0x18 << 19);
Miaoqing Panede6a5e2014-12-19 06:33:59 +0530870 else if (AR_SREV_9531(ah) || AR_SREV_9561(ah)) {
Sujith Manoharan2c323052013-12-31 08:12:02 +0530871 regval = (regval & 0x01c00fff) |
872 (0x1 << 31) |
873 (0x2 << 29) |
874 (0xa << 25) |
Miaoqing Panede6a5e2014-12-19 06:33:59 +0530875 (0x1 << 19);
876
877 if (AR_SREV_9531(ah))
878 regval |= (0x6 << 12);
879 } else
Sujith Manoharan2c323052013-12-31 08:12:02 +0530880 regval = (regval & 0x80071fff) |
881 (0x3 << 30) |
882 (0x1 << 13) |
883 (0x4 << 26) |
884 (0x60 << 19);
Vasanthakumar Thiagarajan0b488ac2011-04-20 10:26:15 +0530885 REG_WRITE(ah, AR_PHY_PLL_MODE, regval);
Sujith Manoharan2c323052013-12-31 08:12:02 +0530886
Miaoqing Panede6a5e2014-12-19 06:33:59 +0530887 if (AR_SREV_9531(ah) || AR_SREV_9561(ah))
Sujith Manoharan2c323052013-12-31 08:12:02 +0530888 REG_WRITE(ah, AR_PHY_PLL_MODE,
889 REG_READ(ah, AR_PHY_PLL_MODE) & 0xffbfffff);
890 else
891 REG_WRITE(ah, AR_PHY_PLL_MODE,
892 REG_READ(ah, AR_PHY_PLL_MODE) & 0xfffeffff);
893
Vasanthakumar Thiagarajan0b488ac2011-04-20 10:26:15 +0530894 udelay(1000);
Vivek Natarajan22983c32011-01-27 14:45:09 +0530895 }
Vasanthakumar Thiagarajand09b17f2010-12-06 04:27:44 -0800896
Sujith Manoharan8565f8b2012-09-10 09:20:29 +0530897 if (AR_SREV_9565(ah))
898 pll |= 0x40000;
Gabor Juhosd03a66c2009-01-14 20:17:09 +0100899 REG_WRITE(ah, AR_RTC_PLL_CONTROL, pll);
Sujithf1dc5602008-10-29 10:16:30 +0530900
Gabor Juhosfc05a312012-07-03 19:13:31 +0200901 if (AR_SREV_9485(ah) || AR_SREV_9340(ah) || AR_SREV_9330(ah) ||
902 AR_SREV_9550(ah))
Vasanthakumar Thiagarajan3dfd7f62011-04-11 16:39:40 +0530903 udelay(1000);
904
Luis R. Rodriguezc75724d2009-10-19 02:33:34 -0400905 /* Switch the core clock for ar9271 to 117Mhz */
906 if (AR_SREV_9271(ah)) {
Sujith25e2ab12010-03-17 14:25:22 +0530907 udelay(500);
908 REG_WRITE(ah, 0x50040, 0x304);
Luis R. Rodriguezc75724d2009-10-19 02:33:34 -0400909 }
910
Sujithf1dc5602008-10-29 10:16:30 +0530911 udelay(RTC_PLL_SETTLE_DELAY);
912
913 REG_WRITE(ah, AR_RTC_SLEEP_CLK, AR_RTC_FORCE_DERIVED_CLK);
914}
915
Sujithcbe61d82009-02-09 13:27:12 +0530916static void ath9k_hw_init_interrupt_masks(struct ath_hw *ah,
Colin McCabed97809d2008-12-01 13:38:55 -0800917 enum nl80211_iftype opmode)
Sujithf1dc5602008-10-29 10:16:30 +0530918{
Vasanthakumar Thiagarajan79d1d2b2011-04-19 19:29:19 +0530919 u32 sync_default = AR_INTR_SYNC_DEFAULT;
Pavel Roskin152d5302010-03-31 18:05:37 -0400920 u32 imr_reg = AR_IMR_TXERR |
Sujithf1dc5602008-10-29 10:16:30 +0530921 AR_IMR_TXURN |
922 AR_IMR_RXERR |
923 AR_IMR_RXORN |
924 AR_IMR_BCNMISC;
925
Miaoqing Panede6a5e2014-12-19 06:33:59 +0530926 if (AR_SREV_9340(ah) || AR_SREV_9550(ah) || AR_SREV_9531(ah) ||
927 AR_SREV_9561(ah))
Vasanthakumar Thiagarajan79d1d2b2011-04-19 19:29:19 +0530928 sync_default &= ~AR_INTR_SYNC_HOST1_FATAL;
929
Vasanthakumar Thiagarajan66860242010-04-15 17:39:07 -0400930 if (AR_SREV_9300_20_OR_LATER(ah)) {
931 imr_reg |= AR_IMR_RXOK_HP;
932 if (ah->config.rx_intr_mitigation)
933 imr_reg |= AR_IMR_RXINTM | AR_IMR_RXMINTR;
934 else
935 imr_reg |= AR_IMR_RXOK_LP;
Sujithf1dc5602008-10-29 10:16:30 +0530936
Vasanthakumar Thiagarajan66860242010-04-15 17:39:07 -0400937 } else {
938 if (ah->config.rx_intr_mitigation)
939 imr_reg |= AR_IMR_RXINTM | AR_IMR_RXMINTR;
940 else
941 imr_reg |= AR_IMR_RXOK;
942 }
943
944 if (ah->config.tx_intr_mitigation)
945 imr_reg |= AR_IMR_TXINTM | AR_IMR_TXMINTR;
946 else
947 imr_reg |= AR_IMR_TXOK;
Sujithf1dc5602008-10-29 10:16:30 +0530948
Sujith7d0d0df2010-04-16 11:53:57 +0530949 ENABLE_REGWRITE_BUFFER(ah);
950
Pavel Roskin152d5302010-03-31 18:05:37 -0400951 REG_WRITE(ah, AR_IMR, imr_reg);
Pavel Roskin74bad5c2010-02-23 18:15:27 -0500952 ah->imrs2_reg |= AR_IMR_S2_GTT;
953 REG_WRITE(ah, AR_IMR_S2, ah->imrs2_reg);
Sujithf1dc5602008-10-29 10:16:30 +0530954
955 if (!AR_SREV_9100(ah)) {
956 REG_WRITE(ah, AR_INTR_SYNC_CAUSE, 0xFFFFFFFF);
Vasanthakumar Thiagarajan79d1d2b2011-04-19 19:29:19 +0530957 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, sync_default);
Sujithf1dc5602008-10-29 10:16:30 +0530958 REG_WRITE(ah, AR_INTR_SYNC_MASK, 0);
959 }
Vasanthakumar Thiagarajan66860242010-04-15 17:39:07 -0400960
Sujith7d0d0df2010-04-16 11:53:57 +0530961 REGWRITE_BUFFER_FLUSH(ah);
Sujith7d0d0df2010-04-16 11:53:57 +0530962
Vasanthakumar Thiagarajan66860242010-04-15 17:39:07 -0400963 if (AR_SREV_9300_20_OR_LATER(ah)) {
964 REG_WRITE(ah, AR_INTR_PRIO_ASYNC_ENABLE, 0);
965 REG_WRITE(ah, AR_INTR_PRIO_ASYNC_MASK, 0);
966 REG_WRITE(ah, AR_INTR_PRIO_SYNC_ENABLE, 0);
967 REG_WRITE(ah, AR_INTR_PRIO_SYNC_MASK, 0);
968 }
Sujithf1dc5602008-10-29 10:16:30 +0530969}
970
Felix Fietkaub6ba41b2011-07-09 11:12:50 +0700971static void ath9k_hw_set_sifs_time(struct ath_hw *ah, u32 us)
972{
973 u32 val = ath9k_hw_mac_to_clks(ah, us - 2);
974 val = min(val, (u32) 0xFFFF);
975 REG_WRITE(ah, AR_D_GBL_IFS_SIFS, val);
976}
977
Lorenzo Bianconi8e15e092014-09-16 02:13:07 +0200978void ath9k_hw_setslottime(struct ath_hw *ah, u32 us)
Sujithf1dc5602008-10-29 10:16:30 +0530979{
Felix Fietkau0005baf2010-01-15 02:33:40 +0100980 u32 val = ath9k_hw_mac_to_clks(ah, us);
981 val = min(val, (u32) 0xFFFF);
982 REG_WRITE(ah, AR_D_GBL_IFS_SLOT, val);
Sujithf1dc5602008-10-29 10:16:30 +0530983}
984
Lorenzo Bianconi8e15e092014-09-16 02:13:07 +0200985void ath9k_hw_set_ack_timeout(struct ath_hw *ah, u32 us)
Sujithf1dc5602008-10-29 10:16:30 +0530986{
Felix Fietkau0005baf2010-01-15 02:33:40 +0100987 u32 val = ath9k_hw_mac_to_clks(ah, us);
988 val = min(val, (u32) MS(0xFFFFFFFF, AR_TIME_OUT_ACK));
989 REG_RMW_FIELD(ah, AR_TIME_OUT, AR_TIME_OUT_ACK, val);
990}
991
Lorenzo Bianconi8e15e092014-09-16 02:13:07 +0200992void ath9k_hw_set_cts_timeout(struct ath_hw *ah, u32 us)
Felix Fietkau0005baf2010-01-15 02:33:40 +0100993{
994 u32 val = ath9k_hw_mac_to_clks(ah, us);
995 val = min(val, (u32) MS(0xFFFFFFFF, AR_TIME_OUT_CTS));
996 REG_RMW_FIELD(ah, AR_TIME_OUT, AR_TIME_OUT_CTS, val);
Sujithf1dc5602008-10-29 10:16:30 +0530997}
998
Sujithcbe61d82009-02-09 13:27:12 +0530999static bool ath9k_hw_set_global_txtimeout(struct ath_hw *ah, u32 tu)
Sujithf1dc5602008-10-29 10:16:30 +05301000{
Sujithf1dc5602008-10-29 10:16:30 +05301001 if (tu > 0xFFFF) {
Joe Perchesd2182b62011-12-15 14:55:53 -08001002 ath_dbg(ath9k_hw_common(ah), XMIT, "bad global tx timeout %u\n",
1003 tu);
Sujith2660b812009-02-09 13:27:26 +05301004 ah->globaltxtimeout = (u32) -1;
Sujithf1dc5602008-10-29 10:16:30 +05301005 return false;
1006 } else {
1007 REG_RMW_FIELD(ah, AR_GTXTO, AR_GTXTO_TIMEOUT_LIMIT, tu);
Sujith2660b812009-02-09 13:27:26 +05301008 ah->globaltxtimeout = tu;
Sujithf1dc5602008-10-29 10:16:30 +05301009 return true;
1010 }
1011}
1012
Felix Fietkau0005baf2010-01-15 02:33:40 +01001013void ath9k_hw_init_global_settings(struct ath_hw *ah)
Sujithf1dc5602008-10-29 10:16:30 +05301014{
Felix Fietkaub6ba41b2011-07-09 11:12:50 +07001015 struct ath_common *common = ath9k_hw_common(ah);
Felix Fietkaub6ba41b2011-07-09 11:12:50 +07001016 const struct ath9k_channel *chan = ah->curchan;
Felix Fietkaue115b7e2012-04-19 21:18:23 +02001017 int acktimeout, ctstimeout, ack_offset = 0;
Felix Fietkaue239d852010-01-15 02:34:58 +01001018 int slottime;
Felix Fietkau0005baf2010-01-15 02:33:40 +01001019 int sifstime;
Felix Fietkaub6ba41b2011-07-09 11:12:50 +07001020 int rx_lat = 0, tx_lat = 0, eifs = 0;
1021 u32 reg;
Felix Fietkau0005baf2010-01-15 02:33:40 +01001022
Joe Perchesd2182b62011-12-15 14:55:53 -08001023 ath_dbg(ath9k_hw_common(ah), RESET, "ah->misc_mode 0x%x\n",
Joe Perches226afe62010-12-02 19:12:37 -08001024 ah->misc_mode);
Sujithf1dc5602008-10-29 10:16:30 +05301025
Felix Fietkaub6ba41b2011-07-09 11:12:50 +07001026 if (!chan)
1027 return;
1028
Sujith2660b812009-02-09 13:27:26 +05301029 if (ah->misc_mode != 0)
Felix Fietkauca7a4de2011-03-23 20:57:26 +01001030 REG_SET_BIT(ah, AR_PCU_MISC, ah->misc_mode);
Felix Fietkau0005baf2010-01-15 02:33:40 +01001031
Rajkumar Manoharan81a91d52011-08-31 10:47:30 +05301032 if (IS_CHAN_A_FAST_CLOCK(ah, chan))
1033 rx_lat = 41;
1034 else
1035 rx_lat = 37;
Felix Fietkaub6ba41b2011-07-09 11:12:50 +07001036 tx_lat = 54;
1037
Felix Fietkaue88e4862012-04-19 21:18:22 +02001038 if (IS_CHAN_5GHZ(chan))
1039 sifstime = 16;
1040 else
1041 sifstime = 10;
1042
Felix Fietkaub6ba41b2011-07-09 11:12:50 +07001043 if (IS_CHAN_HALF_RATE(chan)) {
1044 eifs = 175;
1045 rx_lat *= 2;
1046 tx_lat *= 2;
1047 if (IS_CHAN_A_FAST_CLOCK(ah, chan))
1048 tx_lat += 11;
1049
Simon Wunderlich92367fe72013-08-14 08:01:30 +02001050 sifstime = 32;
Felix Fietkaue115b7e2012-04-19 21:18:23 +02001051 ack_offset = 16;
Felix Fietkaub6ba41b2011-07-09 11:12:50 +07001052 slottime = 13;
Felix Fietkaub6ba41b2011-07-09 11:12:50 +07001053 } else if (IS_CHAN_QUARTER_RATE(chan)) {
1054 eifs = 340;
Rajkumar Manoharan81a91d52011-08-31 10:47:30 +05301055 rx_lat = (rx_lat * 4) - 1;
Felix Fietkaub6ba41b2011-07-09 11:12:50 +07001056 tx_lat *= 4;
1057 if (IS_CHAN_A_FAST_CLOCK(ah, chan))
1058 tx_lat += 22;
1059
Simon Wunderlich92367fe72013-08-14 08:01:30 +02001060 sifstime = 64;
Felix Fietkaue115b7e2012-04-19 21:18:23 +02001061 ack_offset = 32;
Felix Fietkaub6ba41b2011-07-09 11:12:50 +07001062 slottime = 21;
Felix Fietkaub6ba41b2011-07-09 11:12:50 +07001063 } else {
Rajkumar Manoharana7be0392011-08-27 12:13:21 +05301064 if (AR_SREV_9287(ah) && AR_SREV_9287_13_OR_LATER(ah)) {
1065 eifs = AR_D_GBL_IFS_EIFS_ASYNC_FIFO;
1066 reg = AR_USEC_ASYNC_FIFO;
1067 } else {
1068 eifs = REG_READ(ah, AR_D_GBL_IFS_EIFS)/
1069 common->clockrate;
1070 reg = REG_READ(ah, AR_USEC);
1071 }
Felix Fietkaub6ba41b2011-07-09 11:12:50 +07001072 rx_lat = MS(reg, AR_USEC_RX_LAT);
1073 tx_lat = MS(reg, AR_USEC_TX_LAT);
1074
1075 slottime = ah->slottime;
Felix Fietkaub6ba41b2011-07-09 11:12:50 +07001076 }
Felix Fietkau0005baf2010-01-15 02:33:40 +01001077
Felix Fietkaue239d852010-01-15 02:34:58 +01001078 /* As defined by IEEE 802.11-2007 17.3.8.6 */
Mathias Kretschmerf77f8232013-04-22 22:34:41 +02001079 slottime += 3 * ah->coverage_class;
1080 acktimeout = slottime + sifstime + ack_offset;
Felix Fietkauadb50662011-08-28 01:52:10 +02001081 ctstimeout = acktimeout;
Felix Fietkau42c45682010-02-11 18:07:19 +01001082
1083 /*
1084 * Workaround for early ACK timeouts, add an offset to match the
Felix Fietkau55a2bb42012-02-05 21:15:18 +01001085 * initval's 64us ack timeout value. Use 48us for the CTS timeout.
Felix Fietkau42c45682010-02-11 18:07:19 +01001086 * This was initially only meant to work around an issue with delayed
1087 * BA frames in some implementations, but it has been found to fix ACK
1088 * timeout issues in other cases as well.
1089 */
Felix Fietkaue4744ec2013-10-11 23:31:01 +02001090 if (IS_CHAN_2GHZ(chan) &&
Felix Fietkaue115b7e2012-04-19 21:18:23 +02001091 !IS_CHAN_HALF_RATE(chan) && !IS_CHAN_QUARTER_RATE(chan)) {
Felix Fietkau42c45682010-02-11 18:07:19 +01001092 acktimeout += 64 - sifstime - ah->slottime;
Felix Fietkau55a2bb42012-02-05 21:15:18 +01001093 ctstimeout += 48 - sifstime - ah->slottime;
1094 }
1095
Lorenzo Bianconi7aefa8a2014-09-16 02:13:11 +02001096 if (ah->dynack.enabled) {
1097 acktimeout = ah->dynack.ackto;
1098 ctstimeout = acktimeout;
1099 slottime = (acktimeout - 3) / 2;
1100 } else {
1101 ah->dynack.ackto = acktimeout;
1102 }
1103
Felix Fietkaub6ba41b2011-07-09 11:12:50 +07001104 ath9k_hw_set_sifs_time(ah, sifstime);
1105 ath9k_hw_setslottime(ah, slottime);
Felix Fietkau0005baf2010-01-15 02:33:40 +01001106 ath9k_hw_set_ack_timeout(ah, acktimeout);
Felix Fietkauadb50662011-08-28 01:52:10 +02001107 ath9k_hw_set_cts_timeout(ah, ctstimeout);
Sujith2660b812009-02-09 13:27:26 +05301108 if (ah->globaltxtimeout != (u32) -1)
1109 ath9k_hw_set_global_txtimeout(ah, ah->globaltxtimeout);
Felix Fietkaub6ba41b2011-07-09 11:12:50 +07001110
1111 REG_WRITE(ah, AR_D_GBL_IFS_EIFS, ath9k_hw_mac_to_clks(ah, eifs));
1112 REG_RMW(ah, AR_USEC,
1113 (common->clockrate - 1) |
1114 SM(rx_lat, AR_USEC_RX_LAT) |
1115 SM(tx_lat, AR_USEC_TX_LAT),
1116 AR_USEC_TX_LAT | AR_USEC_RX_LAT | AR_USEC_USEC);
1117
Sujithf1dc5602008-10-29 10:16:30 +05301118}
Felix Fietkau0005baf2010-01-15 02:33:40 +01001119EXPORT_SYMBOL(ath9k_hw_init_global_settings);
Sujithf1dc5602008-10-29 10:16:30 +05301120
Sujith285f2dd2010-01-08 10:36:07 +05301121void ath9k_hw_deinit(struct ath_hw *ah)
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07001122{
Luis R. Rodriguez211f5852009-10-06 21:19:07 -04001123 struct ath_common *common = ath9k_hw_common(ah);
1124
Sujith736b3a22010-03-17 14:25:24 +05301125 if (common->state < ATH_HW_INITIALIZED)
Felix Fietkauc1b976d2012-12-12 13:14:23 +01001126 return;
Luis R. Rodriguez211f5852009-10-06 21:19:07 -04001127
Luis R. Rodriguez9ecdef42009-09-09 21:10:09 -07001128 ath9k_hw_setpower(ah, ATH9K_PM_FULL_SLEEP);
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07001129}
Sujith285f2dd2010-01-08 10:36:07 +05301130EXPORT_SYMBOL(ath9k_hw_deinit);
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07001131
Sujithf1dc5602008-10-29 10:16:30 +05301132/*******/
1133/* INI */
1134/*******/
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07001135
Luis R. Rodriguez8fe65362010-04-15 17:38:14 -04001136u32 ath9k_regd_get_ctl(struct ath_regulatory *reg, struct ath9k_channel *chan)
Bob Copeland3a702e42009-03-30 22:30:29 -04001137{
1138 u32 ctl = ath_regd_get_band_ctl(reg, chan->chan->band);
1139
Felix Fietkau6b21fd22013-10-11 23:30:56 +02001140 if (IS_CHAN_2GHZ(chan))
Bob Copeland3a702e42009-03-30 22:30:29 -04001141 ctl |= CTL_11G;
1142 else
1143 ctl |= CTL_11A;
1144
1145 return ctl;
1146}
1147
Sujithf1dc5602008-10-29 10:16:30 +05301148/****************************************/
1149/* Reset and Channel Switching Routines */
1150/****************************************/
1151
Sujithcbe61d82009-02-09 13:27:12 +05301152static inline void ath9k_hw_set_dma(struct ath_hw *ah)
Sujithf1dc5602008-10-29 10:16:30 +05301153{
Felix Fietkau57b32222010-04-15 17:39:22 -04001154 struct ath_common *common = ath9k_hw_common(ah);
Felix Fietkau86c157b2013-05-23 12:20:56 +02001155 int txbuf_size;
Sujithf1dc5602008-10-29 10:16:30 +05301156
Sujith7d0d0df2010-04-16 11:53:57 +05301157 ENABLE_REGWRITE_BUFFER(ah);
1158
Luis R. Rodriguezd7e7d222009-08-03 23:14:12 -04001159 /*
1160 * set AHB_MODE not to do cacheline prefetches
1161 */
Felix Fietkauca7a4de2011-03-23 20:57:26 +01001162 if (!AR_SREV_9300_20_OR_LATER(ah))
1163 REG_SET_BIT(ah, AR_AHB_MODE, AR_AHB_PREFETCH_RD_EN);
Sujithf1dc5602008-10-29 10:16:30 +05301164
Luis R. Rodriguezd7e7d222009-08-03 23:14:12 -04001165 /*
1166 * let mac dma reads be in 128 byte chunks
1167 */
Felix Fietkauca7a4de2011-03-23 20:57:26 +01001168 REG_RMW(ah, AR_TXCFG, AR_TXCFG_DMASZ_128B, AR_TXCFG_DMASZ_MASK);
Sujithf1dc5602008-10-29 10:16:30 +05301169
Sujith7d0d0df2010-04-16 11:53:57 +05301170 REGWRITE_BUFFER_FLUSH(ah);
Sujith7d0d0df2010-04-16 11:53:57 +05301171
Luis R. Rodriguezd7e7d222009-08-03 23:14:12 -04001172 /*
1173 * Restore TX Trigger Level to its pre-reset value.
1174 * The initial value depends on whether aggregation is enabled, and is
1175 * adjusted whenever underruns are detected.
1176 */
Felix Fietkau57b32222010-04-15 17:39:22 -04001177 if (!AR_SREV_9300_20_OR_LATER(ah))
1178 REG_RMW_FIELD(ah, AR_TXCFG, AR_FTRIG, ah->tx_trig_level);
Sujithf1dc5602008-10-29 10:16:30 +05301179
Sujith7d0d0df2010-04-16 11:53:57 +05301180 ENABLE_REGWRITE_BUFFER(ah);
Sujithf1dc5602008-10-29 10:16:30 +05301181
Luis R. Rodriguezd7e7d222009-08-03 23:14:12 -04001182 /*
1183 * let mac dma writes be in 128 byte chunks
1184 */
Felix Fietkauca7a4de2011-03-23 20:57:26 +01001185 REG_RMW(ah, AR_RXCFG, AR_RXCFG_DMASZ_128B, AR_RXCFG_DMASZ_MASK);
Sujithf1dc5602008-10-29 10:16:30 +05301186
Luis R. Rodriguezd7e7d222009-08-03 23:14:12 -04001187 /*
1188 * Setup receive FIFO threshold to hold off TX activities
1189 */
Sujithf1dc5602008-10-29 10:16:30 +05301190 REG_WRITE(ah, AR_RXFIFO_CFG, 0x200);
1191
Felix Fietkau57b32222010-04-15 17:39:22 -04001192 if (AR_SREV_9300_20_OR_LATER(ah)) {
1193 REG_RMW_FIELD(ah, AR_RXBP_THRESH, AR_RXBP_THRESH_HP, 0x1);
1194 REG_RMW_FIELD(ah, AR_RXBP_THRESH, AR_RXBP_THRESH_LP, 0x1);
1195
1196 ath9k_hw_set_rx_bufsize(ah, common->rx_bufsize -
1197 ah->caps.rx_status_len);
1198 }
1199
Luis R. Rodriguezd7e7d222009-08-03 23:14:12 -04001200 /*
1201 * reduce the number of usable entries in PCU TXBUF to avoid
1202 * wrap around issues.
1203 */
Sujithf1dc5602008-10-29 10:16:30 +05301204 if (AR_SREV_9285(ah)) {
Luis R. Rodriguezd7e7d222009-08-03 23:14:12 -04001205 /* For AR9285 the number of Fifos are reduced to half.
1206 * So set the usable tx buf size also to half to
1207 * avoid data/delimiter underruns
1208 */
Felix Fietkau86c157b2013-05-23 12:20:56 +02001209 txbuf_size = AR_9285_PCU_TXBUF_CTRL_USABLE_SIZE;
1210 } else if (AR_SREV_9340_13_OR_LATER(ah)) {
1211 /* Uses fewer entries for AR934x v1.3+ to prevent rx overruns */
1212 txbuf_size = AR_9340_PCU_TXBUF_CTRL_USABLE_SIZE;
1213 } else {
1214 txbuf_size = AR_PCU_TXBUF_CTRL_USABLE_SIZE;
Sujithf1dc5602008-10-29 10:16:30 +05301215 }
Vasanthakumar Thiagarajan744d4022010-04-15 17:39:27 -04001216
Felix Fietkau86c157b2013-05-23 12:20:56 +02001217 if (!AR_SREV_9271(ah))
1218 REG_WRITE(ah, AR_PCU_TXBUF_CTRL, txbuf_size);
1219
Sujith7d0d0df2010-04-16 11:53:57 +05301220 REGWRITE_BUFFER_FLUSH(ah);
Sujith7d0d0df2010-04-16 11:53:57 +05301221
Vasanthakumar Thiagarajan744d4022010-04-15 17:39:27 -04001222 if (AR_SREV_9300_20_OR_LATER(ah))
1223 ath9k_hw_reset_txstatus_ring(ah);
Sujithf1dc5602008-10-29 10:16:30 +05301224}
1225
Sujithcbe61d82009-02-09 13:27:12 +05301226static void ath9k_hw_set_operating_mode(struct ath_hw *ah, int opmode)
Sujithf1dc5602008-10-29 10:16:30 +05301227{
Felix Fietkauca7a4de2011-03-23 20:57:26 +01001228 u32 mask = AR_STA_ID1_STA_AP | AR_STA_ID1_ADHOC;
1229 u32 set = AR_STA_ID1_KSRCH_MODE;
Sujithf1dc5602008-10-29 10:16:30 +05301230
Oleksij Rempel7b37e0d2015-03-22 19:29:57 +01001231 ENABLE_REG_RMW_BUFFER(ah);
Sujithf1dc5602008-10-29 10:16:30 +05301232 switch (opmode) {
Colin McCabed97809d2008-12-01 13:38:55 -08001233 case NL80211_IFTYPE_ADHOC:
Felix Fietkau83322eb2014-09-27 22:49:44 +02001234 if (!AR_SREV_9340_13(ah)) {
1235 set |= AR_STA_ID1_ADHOC;
1236 REG_SET_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
1237 break;
1238 }
1239 /* fall through */
Jan Kaisrlik862a3362015-09-17 14:03:46 +02001240 case NL80211_IFTYPE_OCB:
Thomas Pedersen2664d662013-05-08 10:16:48 -07001241 case NL80211_IFTYPE_MESH_POINT:
Felix Fietkauca7a4de2011-03-23 20:57:26 +01001242 case NL80211_IFTYPE_AP:
1243 set |= AR_STA_ID1_STA_AP;
1244 /* fall through */
Colin McCabed97809d2008-12-01 13:38:55 -08001245 case NL80211_IFTYPE_STATION:
Felix Fietkauca7a4de2011-03-23 20:57:26 +01001246 REG_CLR_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
Sujithf1dc5602008-10-29 10:16:30 +05301247 break;
Rajkumar Manoharan5f841b42010-10-27 18:31:15 +05301248 default:
Felix Fietkauca7a4de2011-03-23 20:57:26 +01001249 if (!ah->is_monitoring)
1250 set = 0;
Rajkumar Manoharan5f841b42010-10-27 18:31:15 +05301251 break;
Sujithf1dc5602008-10-29 10:16:30 +05301252 }
Felix Fietkauca7a4de2011-03-23 20:57:26 +01001253 REG_RMW(ah, AR_STA_ID1, set, mask);
Oleksij Rempel7b37e0d2015-03-22 19:29:57 +01001254 REG_RMW_BUFFER_FLUSH(ah);
Sujithf1dc5602008-10-29 10:16:30 +05301255}
1256
Luis R. Rodriguez8fe65362010-04-15 17:38:14 -04001257void ath9k_hw_get_delta_slope_vals(struct ath_hw *ah, u32 coef_scaled,
1258 u32 *coef_mantissa, u32 *coef_exponent)
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07001259{
1260 u32 coef_exp, coef_man;
1261
1262 for (coef_exp = 31; coef_exp > 0; coef_exp--)
1263 if ((coef_scaled >> coef_exp) & 0x1)
1264 break;
1265
1266 coef_exp = 14 - (coef_exp - COEF_SCALE_S);
1267
1268 coef_man = coef_scaled + (1 << (COEF_SCALE_S - coef_exp - 1));
1269
1270 *coef_mantissa = coef_man >> (COEF_SCALE_S - coef_exp);
1271 *coef_exponent = coef_exp - 16;
1272}
1273
Sujith Manoharand7df7a52013-12-18 09:53:27 +05301274/* AR9330 WAR:
1275 * call external reset function to reset WMAC if:
1276 * - doing a cold reset
1277 * - we have pending frames in the TX queues.
1278 */
1279static bool ath9k_hw_ar9330_reset_war(struct ath_hw *ah, int type)
1280{
1281 int i, npend = 0;
1282
1283 for (i = 0; i < AR_NUM_QCU; i++) {
1284 npend = ath9k_hw_numtxpending(ah, i);
1285 if (npend)
1286 break;
1287 }
1288
1289 if (ah->external_reset &&
1290 (npend || type == ATH9K_RESET_COLD)) {
1291 int reset_err = 0;
1292
1293 ath_dbg(ath9k_hw_common(ah), RESET,
1294 "reset MAC via external reset\n");
1295
1296 reset_err = ah->external_reset();
1297 if (reset_err) {
1298 ath_err(ath9k_hw_common(ah),
1299 "External reset failed, err=%d\n",
1300 reset_err);
1301 return false;
1302 }
1303
1304 REG_WRITE(ah, AR_RTC_RESET, 1);
1305 }
1306
1307 return true;
1308}
1309
Sujithcbe61d82009-02-09 13:27:12 +05301310static bool ath9k_hw_set_reset(struct ath_hw *ah, int type)
Sujithf1dc5602008-10-29 10:16:30 +05301311{
1312 u32 rst_flags;
1313 u32 tmpReg;
1314
Sujith70768492009-02-16 13:23:12 +05301315 if (AR_SREV_9100(ah)) {
Felix Fietkauca7a4de2011-03-23 20:57:26 +01001316 REG_RMW_FIELD(ah, AR_RTC_DERIVED_CLK,
1317 AR_RTC_DERIVED_CLK_PERIOD, 1);
Sujith70768492009-02-16 13:23:12 +05301318 (void)REG_READ(ah, AR_RTC_DERIVED_CLK);
1319 }
1320
Sujith7d0d0df2010-04-16 11:53:57 +05301321 ENABLE_REGWRITE_BUFFER(ah);
1322
Luis R. Rodriguez9a658d22010-06-21 18:38:47 -04001323 if (AR_SREV_9300_20_OR_LATER(ah)) {
1324 REG_WRITE(ah, AR_WA, ah->WARegVal);
1325 udelay(10);
1326 }
1327
Sujithf1dc5602008-10-29 10:16:30 +05301328 REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
1329 AR_RTC_FORCE_WAKE_ON_INT);
1330
1331 if (AR_SREV_9100(ah)) {
1332 rst_flags = AR_RTC_RC_MAC_WARM | AR_RTC_RC_MAC_COLD |
1333 AR_RTC_RC_COLD_RESET | AR_RTC_RC_WARM_RESET;
1334 } else {
1335 tmpReg = REG_READ(ah, AR_INTR_SYNC_CAUSE);
Felix Fietkaua37a9912013-05-23 12:20:55 +02001336 if (AR_SREV_9340(ah))
1337 tmpReg &= AR9340_INTR_SYNC_LOCAL_TIMEOUT;
1338 else
1339 tmpReg &= AR_INTR_SYNC_LOCAL_TIMEOUT |
1340 AR_INTR_SYNC_RADM_CPL_TIMEOUT;
1341
1342 if (tmpReg) {
Luis R. Rodriguez42d5bc32010-04-15 17:38:12 -04001343 u32 val;
Sujithf1dc5602008-10-29 10:16:30 +05301344 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0);
Luis R. Rodriguez42d5bc32010-04-15 17:38:12 -04001345
1346 val = AR_RC_HOSTIF;
1347 if (!AR_SREV_9300_20_OR_LATER(ah))
1348 val |= AR_RC_AHB;
1349 REG_WRITE(ah, AR_RC, val);
1350
1351 } else if (!AR_SREV_9300_20_OR_LATER(ah))
Sujithf1dc5602008-10-29 10:16:30 +05301352 REG_WRITE(ah, AR_RC, AR_RC_AHB);
Sujithf1dc5602008-10-29 10:16:30 +05301353
1354 rst_flags = AR_RTC_RC_MAC_WARM;
1355 if (type == ATH9K_RESET_COLD)
1356 rst_flags |= AR_RTC_RC_MAC_COLD;
1357 }
1358
Gabor Juhos7d95847c2011-06-21 11:23:51 +02001359 if (AR_SREV_9330(ah)) {
Sujith Manoharand7df7a52013-12-18 09:53:27 +05301360 if (!ath9k_hw_ar9330_reset_war(ah, type))
1361 return false;
Gabor Juhos7d95847c2011-06-21 11:23:51 +02001362 }
1363
Rajkumar Manoharan38634952012-06-11 12:19:32 +05301364 if (ath9k_hw_mci_is_enabled(ah))
Rajkumar Manoharan506847a2012-06-12 20:18:16 +05301365 ar9003_mci_check_gpm_offset(ah);
Rajkumar Manoharan38634952012-06-11 12:19:32 +05301366
Miaoqing Pan466b0f02016-01-18 09:33:50 +08001367 /* DMA HALT added to resolve ar9300 and ar9580 bus error during
1368 * RTC_RC reg read
1369 */
1370 if (AR_SREV_9300(ah) || AR_SREV_9580(ah)) {
1371 REG_SET_BIT(ah, AR_CFG, AR_CFG_HALT_REQ);
1372 ath9k_hw_wait(ah, AR_CFG, AR_CFG_HALT_ACK, AR_CFG_HALT_ACK,
1373 20 * AH_WAIT_TIMEOUT);
1374 REG_CLR_BIT(ah, AR_CFG, AR_CFG_HALT_REQ);
1375 }
1376
Gabor Juhosd03a66c2009-01-14 20:17:09 +01001377 REG_WRITE(ah, AR_RTC_RC, rst_flags);
Sujith7d0d0df2010-04-16 11:53:57 +05301378
1379 REGWRITE_BUFFER_FLUSH(ah);
Sujith7d0d0df2010-04-16 11:53:57 +05301380
Sujith Manoharan4dc78c432013-12-18 09:53:26 +05301381 if (AR_SREV_9300_20_OR_LATER(ah))
1382 udelay(50);
1383 else if (AR_SREV_9100(ah))
Sujith Manoharan3683a072014-02-04 08:37:52 +05301384 mdelay(10);
Sujith Manoharan4dc78c432013-12-18 09:53:26 +05301385 else
1386 udelay(100);
Sujithf1dc5602008-10-29 10:16:30 +05301387
Gabor Juhosd03a66c2009-01-14 20:17:09 +01001388 REG_WRITE(ah, AR_RTC_RC, 0);
Sujith0caa7b12009-02-16 13:23:20 +05301389 if (!ath9k_hw_wait(ah, AR_RTC_RC, AR_RTC_RC_M, 0, AH_WAIT_TIMEOUT)) {
Joe Perchesd2182b62011-12-15 14:55:53 -08001390 ath_dbg(ath9k_hw_common(ah), RESET, "RTC stuck in MAC reset\n");
Sujithf1dc5602008-10-29 10:16:30 +05301391 return false;
1392 }
1393
1394 if (!AR_SREV_9100(ah))
1395 REG_WRITE(ah, AR_RC, 0);
1396
Sujithf1dc5602008-10-29 10:16:30 +05301397 if (AR_SREV_9100(ah))
1398 udelay(50);
1399
1400 return true;
1401}
1402
Sujithcbe61d82009-02-09 13:27:12 +05301403static bool ath9k_hw_set_reset_power_on(struct ath_hw *ah)
Sujithf1dc5602008-10-29 10:16:30 +05301404{
Sujith7d0d0df2010-04-16 11:53:57 +05301405 ENABLE_REGWRITE_BUFFER(ah);
1406
Luis R. Rodriguez9a658d22010-06-21 18:38:47 -04001407 if (AR_SREV_9300_20_OR_LATER(ah)) {
1408 REG_WRITE(ah, AR_WA, ah->WARegVal);
1409 udelay(10);
1410 }
1411
Sujithf1dc5602008-10-29 10:16:30 +05301412 REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
1413 AR_RTC_FORCE_WAKE_ON_INT);
1414
Luis R. Rodriguez42d5bc32010-04-15 17:38:12 -04001415 if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah))
Vasanthakumar Thiagarajan1c29ce62009-08-31 17:48:36 +05301416 REG_WRITE(ah, AR_RC, AR_RC_AHB);
1417
Gabor Juhosd03a66c2009-01-14 20:17:09 +01001418 REG_WRITE(ah, AR_RTC_RESET, 0);
Vasanthakumar Thiagarajan1c29ce62009-08-31 17:48:36 +05301419
Sujith7d0d0df2010-04-16 11:53:57 +05301420 REGWRITE_BUFFER_FLUSH(ah);
Sujith7d0d0df2010-04-16 11:53:57 +05301421
Sujith Manoharanafe36532013-12-18 09:53:25 +05301422 udelay(2);
Senthil Balasubramanian84e21692010-04-15 17:38:30 -04001423
1424 if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah))
Vasanthakumar Thiagarajan1c29ce62009-08-31 17:48:36 +05301425 REG_WRITE(ah, AR_RC, 0);
1426
Gabor Juhosd03a66c2009-01-14 20:17:09 +01001427 REG_WRITE(ah, AR_RTC_RESET, 1);
Sujithf1dc5602008-10-29 10:16:30 +05301428
1429 if (!ath9k_hw_wait(ah,
1430 AR_RTC_STATUS,
1431 AR_RTC_STATUS_M,
Sujith0caa7b12009-02-16 13:23:20 +05301432 AR_RTC_STATUS_ON,
1433 AH_WAIT_TIMEOUT)) {
Joe Perchesd2182b62011-12-15 14:55:53 -08001434 ath_dbg(ath9k_hw_common(ah), RESET, "RTC not waking up\n");
Sujithf1dc5602008-10-29 10:16:30 +05301435 return false;
1436 }
1437
Sujithf1dc5602008-10-29 10:16:30 +05301438 return ath9k_hw_set_reset(ah, ATH9K_RESET_WARM);
1439}
1440
Sujithcbe61d82009-02-09 13:27:12 +05301441static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type)
Sujithf1dc5602008-10-29 10:16:30 +05301442{
Mohammed Shafi Shajakhan7a9233f2011-11-30 10:41:25 +05301443 bool ret = false;
Senthil Balasubramanian2577c6e2011-09-13 22:38:18 +05301444
Luis R. Rodriguez9a658d22010-06-21 18:38:47 -04001445 if (AR_SREV_9300_20_OR_LATER(ah)) {
1446 REG_WRITE(ah, AR_WA, ah->WARegVal);
1447 udelay(10);
1448 }
1449
Sujithf1dc5602008-10-29 10:16:30 +05301450 REG_WRITE(ah, AR_RTC_FORCE_WAKE,
1451 AR_RTC_FORCE_WAKE_EN | AR_RTC_FORCE_WAKE_ON_INT);
1452
Felix Fietkauceb26a62012-10-03 21:07:51 +02001453 if (!ah->reset_power_on)
1454 type = ATH9K_RESET_POWER_ON;
1455
Sujithf1dc5602008-10-29 10:16:30 +05301456 switch (type) {
1457 case ATH9K_RESET_POWER_ON:
Mohammed Shafi Shajakhan7a9233f2011-11-30 10:41:25 +05301458 ret = ath9k_hw_set_reset_power_on(ah);
Sujith Manoharanda8fb122012-11-17 21:20:50 +05301459 if (ret)
Felix Fietkauceb26a62012-10-03 21:07:51 +02001460 ah->reset_power_on = true;
Mohammed Shafi Shajakhan7a9233f2011-11-30 10:41:25 +05301461 break;
Sujithf1dc5602008-10-29 10:16:30 +05301462 case ATH9K_RESET_WARM:
1463 case ATH9K_RESET_COLD:
Mohammed Shafi Shajakhan7a9233f2011-11-30 10:41:25 +05301464 ret = ath9k_hw_set_reset(ah, type);
1465 break;
Sujithf1dc5602008-10-29 10:16:30 +05301466 default:
Mohammed Shafi Shajakhan7a9233f2011-11-30 10:41:25 +05301467 break;
Sujithf1dc5602008-10-29 10:16:30 +05301468 }
Mohammed Shafi Shajakhan7a9233f2011-11-30 10:41:25 +05301469
Mohammed Shafi Shajakhan7a9233f2011-11-30 10:41:25 +05301470 return ret;
Sujithf1dc5602008-10-29 10:16:30 +05301471}
1472
Sujithcbe61d82009-02-09 13:27:12 +05301473static bool ath9k_hw_chip_reset(struct ath_hw *ah,
Sujithf1dc5602008-10-29 10:16:30 +05301474 struct ath9k_channel *chan)
1475{
Felix Fietkau9c083af2012-03-03 15:17:02 +01001476 int reset_type = ATH9K_RESET_WARM;
1477
1478 if (AR_SREV_9280(ah)) {
1479 if (ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL))
1480 reset_type = ATH9K_RESET_POWER_ON;
1481 else
1482 reset_type = ATH9K_RESET_COLD;
Felix Fietkau3412f2f02013-02-25 20:51:07 +01001483 } else if (ah->chip_fullsleep || REG_READ(ah, AR_Q_TXE) ||
1484 (REG_READ(ah, AR_CR) & AR_CR_RXE))
1485 reset_type = ATH9K_RESET_COLD;
Felix Fietkau9c083af2012-03-03 15:17:02 +01001486
1487 if (!ath9k_hw_set_reset_reg(ah, reset_type))
Sujithf1dc5602008-10-29 10:16:30 +05301488 return false;
1489
Luis R. Rodriguez9ecdef42009-09-09 21:10:09 -07001490 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
Sujithf1dc5602008-10-29 10:16:30 +05301491 return false;
1492
Sujith2660b812009-02-09 13:27:26 +05301493 ah->chip_fullsleep = false;
Felix Fietkaubfc441a2012-05-24 14:32:22 +02001494
1495 if (AR_SREV_9330(ah))
1496 ar9003_hw_internal_regulator_apply(ah);
Sujithf1dc5602008-10-29 10:16:30 +05301497 ath9k_hw_init_pll(ah, chan);
Sujithf1dc5602008-10-29 10:16:30 +05301498
1499 return true;
1500}
1501
Sujithcbe61d82009-02-09 13:27:12 +05301502static bool ath9k_hw_channel_change(struct ath_hw *ah,
Luis R. Rodriguez25c56ee2009-09-13 23:04:44 -07001503 struct ath9k_channel *chan)
Sujithf1dc5602008-10-29 10:16:30 +05301504{
Luis R. Rodriguezc46917b2009-09-13 02:42:02 -07001505 struct ath_common *common = ath9k_hw_common(ah);
Sujith Manoharanb840cff2013-07-16 12:03:19 +05301506 struct ath9k_hw_capabilities *pCap = &ah->caps;
1507 bool band_switch = false, mode_diff = false;
Sujith Manoharan70e89a72013-07-16 12:03:22 +05301508 u8 ini_reloaded = 0;
Luis R. Rodriguez8fe65362010-04-15 17:38:14 -04001509 u32 qnum;
Luis R. Rodriguez0a3b7ba2009-10-19 02:33:40 -04001510 int r;
Rajkumar Manoharan5f0c04e2011-10-13 11:00:35 +05301511
Sujith Manoharanb840cff2013-07-16 12:03:19 +05301512 if (pCap->hw_caps & ATH9K_HW_CAP_FCC_BAND_SWITCH) {
Felix Fietkauaf02efb2013-11-18 20:14:44 +01001513 u32 flags_diff = chan->channelFlags ^ ah->curchan->channelFlags;
1514 band_switch = !!(flags_diff & CHANNEL_5GHZ);
1515 mode_diff = !!(flags_diff & ~CHANNEL_HT);
Sujith Manoharanb840cff2013-07-16 12:03:19 +05301516 }
Sujithf1dc5602008-10-29 10:16:30 +05301517
1518 for (qnum = 0; qnum < AR_NUM_QCU; qnum++) {
1519 if (ath9k_hw_numtxpending(ah, qnum)) {
Joe Perchesd2182b62011-12-15 14:55:53 -08001520 ath_dbg(common, QUEUE,
Joe Perches226afe62010-12-02 19:12:37 -08001521 "Transmit frames pending on queue %d\n", qnum);
Sujithf1dc5602008-10-29 10:16:30 +05301522 return false;
1523 }
1524 }
1525
Luis R. Rodriguez8fe65362010-04-15 17:38:14 -04001526 if (!ath9k_hw_rfbus_req(ah)) {
Joe Perches38002762010-12-02 19:12:36 -08001527 ath_err(common, "Could not kill baseband RX\n");
Sujithf1dc5602008-10-29 10:16:30 +05301528 return false;
1529 }
1530
Sujith Manoharanb840cff2013-07-16 12:03:19 +05301531 if (band_switch || mode_diff) {
Rajkumar Manoharan5f0c04e2011-10-13 11:00:35 +05301532 ath9k_hw_mark_phy_inactive(ah);
1533 udelay(5);
1534
Sujith Manoharan5f35c0f2013-07-16 12:03:20 +05301535 if (band_switch)
1536 ath9k_hw_init_pll(ah, chan);
Rajkumar Manoharan5f0c04e2011-10-13 11:00:35 +05301537
1538 if (ath9k_hw_fast_chan_change(ah, chan, &ini_reloaded)) {
1539 ath_err(common, "Failed to do fast channel change\n");
1540 return false;
1541 }
1542 }
1543
Luis R. Rodriguez8fe65362010-04-15 17:38:14 -04001544 ath9k_hw_set_channel_regs(ah, chan);
Sujithf1dc5602008-10-29 10:16:30 +05301545
Luis R. Rodriguez8fe65362010-04-15 17:38:14 -04001546 r = ath9k_hw_rf_set_freq(ah, chan);
Luis R. Rodriguez0a3b7ba2009-10-19 02:33:40 -04001547 if (r) {
Joe Perches38002762010-12-02 19:12:36 -08001548 ath_err(common, "Failed to set channel\n");
Luis R. Rodriguez0a3b7ba2009-10-19 02:33:40 -04001549 return false;
Sujithf1dc5602008-10-29 10:16:30 +05301550 }
Felix Fietkaudfdac8a2010-10-08 22:13:51 +02001551 ath9k_hw_set_clockrate(ah);
Gabor Juhos64ea57d2012-04-15 20:38:05 +02001552 ath9k_hw_apply_txpower(ah, chan, false);
Sujithf1dc5602008-10-29 10:16:30 +05301553
Felix Fietkau81c507a2013-10-11 23:30:55 +02001554 ath9k_hw_set_delta_slope(ah, chan);
Luis R. Rodriguez8fe65362010-04-15 17:38:14 -04001555 ath9k_hw_spur_mitigate_freq(ah, chan);
Sujithf1dc5602008-10-29 10:16:30 +05301556
Sujith Manoharan70e89a72013-07-16 12:03:22 +05301557 if (band_switch || ini_reloaded)
1558 ah->eep_ops->set_board_values(ah, chan);
1559
1560 ath9k_hw_init_bb(ah, chan);
1561 ath9k_hw_rfbus_done(ah);
1562
1563 if (band_switch || ini_reloaded) {
Rajkumar Manoharana126ff52011-10-13 11:00:42 +05301564 ah->ah_flags |= AH_FASTCC;
Sujith Manoharan70e89a72013-07-16 12:03:22 +05301565 ath9k_hw_init_cal(ah, chan);
Rajkumar Manoharana126ff52011-10-13 11:00:42 +05301566 ah->ah_flags &= ~AH_FASTCC;
Rajkumar Manoharan5f0c04e2011-10-13 11:00:35 +05301567 }
1568
Sujithf1dc5602008-10-29 10:16:30 +05301569 return true;
1570}
1571
Felix Fietkau691680b2011-03-19 13:55:38 +01001572static void ath9k_hw_apply_gpio_override(struct ath_hw *ah)
1573{
1574 u32 gpio_mask = ah->gpio_mask;
1575 int i;
1576
1577 for (i = 0; gpio_mask; i++, gpio_mask >>= 1) {
1578 if (!(gpio_mask & 1))
1579 continue;
1580
Miaoqing Panb2d70d42016-03-07 10:38:15 +08001581 ath9k_hw_gpio_request_out(ah, i, NULL,
1582 AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
Felix Fietkau691680b2011-03-19 13:55:38 +01001583 ath9k_hw_set_gpio(ah, i, !!(ah->gpio_val & BIT(i)));
Miaoqing Pandb222192016-03-07 10:38:16 +08001584 ath9k_hw_gpio_free(ah, i);
Felix Fietkau691680b2011-03-19 13:55:38 +01001585 }
1586}
1587
Sujith Manoharan1e516ca2013-09-11 21:30:27 +05301588void ath9k_hw_check_nav(struct ath_hw *ah)
1589{
1590 struct ath_common *common = ath9k_hw_common(ah);
1591 u32 val;
1592
1593 val = REG_READ(ah, AR_NAV);
1594 if (val != 0xdeadbeef && val > 0x7fff) {
1595 ath_dbg(common, BSTUCK, "Abnormal NAV: 0x%x\n", val);
1596 REG_WRITE(ah, AR_NAV, 0);
1597 }
1598}
1599EXPORT_SYMBOL(ath9k_hw_check_nav);
1600
Felix Fietkauc9c99e52010-04-19 19:57:29 +02001601bool ath9k_hw_check_alive(struct ath_hw *ah)
Johannes Berg3b319aa2009-06-13 14:50:26 +05301602{
Felix Fietkauc9c99e52010-04-19 19:57:29 +02001603 int count = 50;
Felix Fietkaud31a36a2014-02-24 22:26:05 +01001604 u32 reg, last_val;
Johannes Berg3b319aa2009-06-13 14:50:26 +05301605
Rajkumar Manoharan01e18912012-03-15 05:34:27 +05301606 if (AR_SREV_9300(ah))
1607 return !ath9k_hw_detect_mac_hang(ah);
1608
Felix Fietkaue17f83e2010-09-22 12:34:53 +02001609 if (AR_SREV_9285_12_OR_LATER(ah))
Felix Fietkauc9c99e52010-04-19 19:57:29 +02001610 return true;
Johannes Berg3b319aa2009-06-13 14:50:26 +05301611
Felix Fietkaud31a36a2014-02-24 22:26:05 +01001612 last_val = REG_READ(ah, AR_OBS_BUS_1);
Felix Fietkauc9c99e52010-04-19 19:57:29 +02001613 do {
1614 reg = REG_READ(ah, AR_OBS_BUS_1);
Felix Fietkaud31a36a2014-02-24 22:26:05 +01001615 if (reg != last_val)
1616 return true;
Felix Fietkauc9c99e52010-04-19 19:57:29 +02001617
Felix Fietkau105ff412014-03-09 09:51:16 +01001618 udelay(1);
Felix Fietkaud31a36a2014-02-24 22:26:05 +01001619 last_val = reg;
Felix Fietkauc9c99e52010-04-19 19:57:29 +02001620 if ((reg & 0x7E7FFFEF) == 0x00702400)
1621 continue;
1622
1623 switch (reg & 0x7E000B00) {
1624 case 0x1E000000:
1625 case 0x52000B00:
1626 case 0x18000B00:
1627 continue;
1628 default:
1629 return true;
1630 }
1631 } while (count-- > 0);
1632
1633 return false;
Johannes Berg3b319aa2009-06-13 14:50:26 +05301634}
Felix Fietkauc9c99e52010-04-19 19:57:29 +02001635EXPORT_SYMBOL(ath9k_hw_check_alive);
Johannes Berg3b319aa2009-06-13 14:50:26 +05301636
Sujith Manoharan15d2b582013-03-04 12:42:53 +05301637static void ath9k_hw_init_mfp(struct ath_hw *ah)
1638{
1639 /* Setup MFP options for CCMP */
1640 if (AR_SREV_9280_20_OR_LATER(ah)) {
1641 /* Mask Retry(b11), PwrMgt(b12), MoreData(b13) to 0 in mgmt
1642 * frames when constructing CCMP AAD. */
1643 REG_RMW_FIELD(ah, AR_AES_MUTE_MASK1, AR_AES_MUTE_MASK1_FC_MGMT,
1644 0xc7ff);
Chun-Yeow Yeoh60fc4962014-11-16 03:05:41 +08001645 if (AR_SREV_9271(ah) || AR_DEVID_7010(ah))
1646 ah->sw_mgmt_crypto_tx = true;
1647 else
1648 ah->sw_mgmt_crypto_tx = false;
Chun-Yeow Yeohe6510b12014-11-16 03:05:40 +08001649 ah->sw_mgmt_crypto_rx = false;
Sujith Manoharan15d2b582013-03-04 12:42:53 +05301650 } else if (AR_SREV_9160_10_OR_LATER(ah)) {
1651 /* Disable hardware crypto for management frames */
1652 REG_CLR_BIT(ah, AR_PCU_MISC_MODE2,
1653 AR_PCU_MISC_MODE2_MGMT_CRYPTO_ENABLE);
1654 REG_SET_BIT(ah, AR_PCU_MISC_MODE2,
1655 AR_PCU_MISC_MODE2_NO_CRYPTO_FOR_NON_DATA_PKT);
Chun-Yeow Yeohe6510b12014-11-16 03:05:40 +08001656 ah->sw_mgmt_crypto_tx = true;
1657 ah->sw_mgmt_crypto_rx = true;
Sujith Manoharan15d2b582013-03-04 12:42:53 +05301658 } else {
Chun-Yeow Yeohe6510b12014-11-16 03:05:40 +08001659 ah->sw_mgmt_crypto_tx = true;
1660 ah->sw_mgmt_crypto_rx = true;
Sujith Manoharan15d2b582013-03-04 12:42:53 +05301661 }
1662}
1663
1664static void ath9k_hw_reset_opmode(struct ath_hw *ah,
1665 u32 macStaId1, u32 saveDefAntenna)
1666{
1667 struct ath_common *common = ath9k_hw_common(ah);
1668
1669 ENABLE_REGWRITE_BUFFER(ah);
1670
Felix Fietkauecbbed32013-04-16 12:51:56 +02001671 REG_RMW(ah, AR_STA_ID1, macStaId1
Sujith Manoharan15d2b582013-03-04 12:42:53 +05301672 | AR_STA_ID1_RTS_USE_DEF
Felix Fietkauecbbed32013-04-16 12:51:56 +02001673 | ah->sta_id1_defaults,
1674 ~AR_STA_ID1_SADH_MASK);
Sujith Manoharan15d2b582013-03-04 12:42:53 +05301675 ath_hw_setbssidmask(common);
1676 REG_WRITE(ah, AR_DEF_ANTENNA, saveDefAntenna);
1677 ath9k_hw_write_associd(ah);
1678 REG_WRITE(ah, AR_ISR, ~0);
1679 REG_WRITE(ah, AR_RSSI_THR, INIT_RSSI_THR);
1680
1681 REGWRITE_BUFFER_FLUSH(ah);
1682
1683 ath9k_hw_set_operating_mode(ah, ah->opmode);
1684}
1685
1686static void ath9k_hw_init_queues(struct ath_hw *ah)
1687{
1688 int i;
1689
1690 ENABLE_REGWRITE_BUFFER(ah);
1691
1692 for (i = 0; i < AR_NUM_DCU; i++)
1693 REG_WRITE(ah, AR_DQCUMASK(i), 1 << i);
1694
1695 REGWRITE_BUFFER_FLUSH(ah);
1696
1697 ah->intr_txqs = 0;
1698 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
1699 ath9k_hw_resettxqueue(ah, i);
1700}
1701
1702/*
1703 * For big endian systems turn on swapping for descriptors
1704 */
1705static void ath9k_hw_init_desc(struct ath_hw *ah)
1706{
1707 struct ath_common *common = ath9k_hw_common(ah);
1708
1709 if (AR_SREV_9100(ah)) {
1710 u32 mask;
1711 mask = REG_READ(ah, AR_CFG);
1712 if (mask & (AR_CFG_SWRB | AR_CFG_SWTB | AR_CFG_SWRG)) {
1713 ath_dbg(common, RESET, "CFG Byte Swap Set 0x%x\n",
1714 mask);
1715 } else {
1716 mask = INIT_CONFIG_STATUS | AR_CFG_SWRB | AR_CFG_SWTB;
1717 REG_WRITE(ah, AR_CFG, mask);
1718 ath_dbg(common, RESET, "Setting CFG 0x%x\n",
1719 REG_READ(ah, AR_CFG));
1720 }
1721 } else {
1722 if (common->bus_ops->ath_bus_type == ATH_USB) {
1723 /* Configure AR9271 target WLAN */
1724 if (AR_SREV_9271(ah))
1725 REG_WRITE(ah, AR_CFG, AR_CFG_SWRB | AR_CFG_SWTB);
1726 else
1727 REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD);
1728 }
1729#ifdef __BIG_ENDIAN
1730 else if (AR_SREV_9330(ah) || AR_SREV_9340(ah) ||
Miaoqing Panede6a5e2014-12-19 06:33:59 +05301731 AR_SREV_9550(ah) || AR_SREV_9531(ah) ||
1732 AR_SREV_9561(ah))
Sujith Manoharan15d2b582013-03-04 12:42:53 +05301733 REG_RMW(ah, AR_CFG, AR_CFG_SWRB | AR_CFG_SWTB, 0);
1734 else
1735 REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD);
1736#endif
1737 }
1738}
1739
Sujith Manoharancaed6572012-03-14 14:40:46 +05301740/*
1741 * Fast channel change:
1742 * (Change synthesizer based on channel freq without resetting chip)
Sujith Manoharancaed6572012-03-14 14:40:46 +05301743 */
1744static int ath9k_hw_do_fastcc(struct ath_hw *ah, struct ath9k_channel *chan)
1745{
1746 struct ath_common *common = ath9k_hw_common(ah);
Sujith Manoharanb840cff2013-07-16 12:03:19 +05301747 struct ath9k_hw_capabilities *pCap = &ah->caps;
Sujith Manoharancaed6572012-03-14 14:40:46 +05301748 int ret;
1749
1750 if (AR_SREV_9280(ah) && common->bus_ops->ath_bus_type == ATH_PCI)
1751 goto fail;
1752
1753 if (ah->chip_fullsleep)
1754 goto fail;
1755
1756 if (!ah->curchan)
1757 goto fail;
1758
1759 if (chan->channel == ah->curchan->channel)
1760 goto fail;
1761
Felix Fietkaufeb7bc92012-04-19 21:18:28 +02001762 if ((ah->curchan->channelFlags | chan->channelFlags) &
1763 (CHANNEL_HALF | CHANNEL_QUARTER))
1764 goto fail;
1765
Sujith Manoharanb840cff2013-07-16 12:03:19 +05301766 /*
Felix Fietkau6b21fd22013-10-11 23:30:56 +02001767 * If cross-band fcc is not supoprted, bail out if channelFlags differ.
Sujith Manoharanb840cff2013-07-16 12:03:19 +05301768 */
Felix Fietkau6b21fd22013-10-11 23:30:56 +02001769 if (!(pCap->hw_caps & ATH9K_HW_CAP_FCC_BAND_SWITCH) &&
Felix Fietkauaf02efb2013-11-18 20:14:44 +01001770 ((chan->channelFlags ^ ah->curchan->channelFlags) & ~CHANNEL_HT))
Felix Fietkau6b21fd22013-10-11 23:30:56 +02001771 goto fail;
Sujith Manoharancaed6572012-03-14 14:40:46 +05301772
1773 if (!ath9k_hw_check_alive(ah))
1774 goto fail;
1775
1776 /*
1777 * For AR9462, make sure that calibration data for
1778 * re-using are present.
1779 */
Sujith Manoharan8a905552012-05-04 13:23:59 +05301780 if (AR_SREV_9462(ah) && (ah->caldata &&
Sujith Manoharan4b9b42b2013-09-11 16:36:31 +05301781 (!test_bit(TXIQCAL_DONE, &ah->caldata->cal_flags) ||
1782 !test_bit(TXCLCAL_DONE, &ah->caldata->cal_flags) ||
1783 !test_bit(RTT_DONE, &ah->caldata->cal_flags))))
Sujith Manoharancaed6572012-03-14 14:40:46 +05301784 goto fail;
1785
1786 ath_dbg(common, RESET, "FastChannelChange for %d -> %d\n",
1787 ah->curchan->channel, chan->channel);
1788
1789 ret = ath9k_hw_channel_change(ah, chan);
1790 if (!ret)
1791 goto fail;
1792
Sujith Manoharan5955b2b2012-06-04 16:27:30 +05301793 if (ath9k_hw_mci_is_enabled(ah))
Rajkumar Manoharan1bde95fa2012-06-11 12:19:33 +05301794 ar9003_mci_2g5g_switch(ah, false);
Sujith Manoharancaed6572012-03-14 14:40:46 +05301795
Rajkumar Manoharan88033312012-09-12 18:59:19 +05301796 ath9k_hw_loadnf(ah, ah->curchan);
1797 ath9k_hw_start_nfcal(ah, true);
1798
Sujith Manoharancaed6572012-03-14 14:40:46 +05301799 if (AR_SREV_9271(ah))
1800 ar9002_hw_load_ani_reg(ah, chan);
1801
1802 return 0;
1803fail:
1804 return -EINVAL;
1805}
1806
Felix Fietkau8d7e09d2014-06-11 16:18:01 +05301807u32 ath9k_hw_get_tsf_offset(struct timespec *last, struct timespec *cur)
1808{
1809 struct timespec ts;
1810 s64 usec;
1811
1812 if (!cur) {
1813 getrawmonotonic(&ts);
1814 cur = &ts;
1815 }
1816
1817 usec = cur->tv_sec * 1000000ULL + cur->tv_nsec / 1000;
1818 usec -= last->tv_sec * 1000000ULL + last->tv_nsec / 1000;
1819
1820 return (u32) usec;
1821}
1822EXPORT_SYMBOL(ath9k_hw_get_tsf_offset);
1823
Sujithcbe61d82009-02-09 13:27:12 +05301824int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
Sujith Manoharancaed6572012-03-14 14:40:46 +05301825 struct ath9k_hw_cal_data *caldata, bool fastcc)
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07001826{
Luis R. Rodriguez15107182009-09-10 09:22:37 -07001827 struct ath_common *common = ath9k_hw_common(ah);
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07001828 u32 saveLedState;
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07001829 u32 saveDefAntenna;
1830 u32 macStaId1;
Benjamin Bergbec9a942016-07-04 14:37:22 +02001831 struct timespec tsf_ts;
1832 u32 tsf_offset;
Sujith46fe7822009-09-17 09:25:25 +05301833 u64 tsf = 0;
Sujith Manoharan15d2b582013-03-04 12:42:53 +05301834 int r;
Sujith Manoharancaed6572012-03-14 14:40:46 +05301835 bool start_mci_reset = false;
Mohammed Shafi Shajakhan63d32962011-11-30 10:41:27 +05301836 bool save_fullsleep = ah->chip_fullsleep;
1837
Sujith Manoharan5955b2b2012-06-04 16:27:30 +05301838 if (ath9k_hw_mci_is_enabled(ah)) {
Sujith Manoharan528e5d32012-02-22 12:41:12 +05301839 start_mci_reset = ar9003_mci_start_reset(ah, chan);
1840 if (start_mci_reset)
1841 return 0;
Mohammed Shafi Shajakhan63d32962011-11-30 10:41:27 +05301842 }
1843
Luis R. Rodriguez9ecdef42009-09-09 21:10:09 -07001844 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
Luis R. Rodriguezae8d2852008-12-23 15:58:40 -08001845 return -EIO;
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07001846
Sujith Manoharancaed6572012-03-14 14:40:46 +05301847 if (ah->curchan && !ah->chip_fullsleep)
1848 ath9k_hw_getnf(ah, ah->curchan);
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07001849
Felix Fietkau20bd2a02010-07-31 00:12:00 +02001850 ah->caldata = caldata;
Sujith Manoharanfcb9a3d2013-03-04 12:42:52 +05301851 if (caldata && (chan->channel != caldata->channel ||
Felix Fietkau6b21fd22013-10-11 23:30:56 +02001852 chan->channelFlags != caldata->channelFlags)) {
Felix Fietkau20bd2a02010-07-31 00:12:00 +02001853 /* Operating channel changed, reset channel calibration data */
1854 memset(caldata, 0, sizeof(*caldata));
1855 ath9k_init_nfcal_hist_buffer(ah, chan);
Felix Fietkau51dea9b2012-08-27 17:00:07 +02001856 } else if (caldata) {
Sujith Manoharan4b9b42b2013-09-11 16:36:31 +05301857 clear_bit(PAPRD_PACKET_SENT, &caldata->cal_flags);
Felix Fietkau20bd2a02010-07-31 00:12:00 +02001858 }
Lorenzo Bianconi5bc225a2013-10-11 14:09:54 +02001859 ah->noise = ath9k_hw_getchan_noise(ah, chan, chan->noisefloor);
Felix Fietkau20bd2a02010-07-31 00:12:00 +02001860
Sujith Manoharancaed6572012-03-14 14:40:46 +05301861 if (fastcc) {
1862 r = ath9k_hw_do_fastcc(ah, chan);
1863 if (!r)
1864 return r;
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07001865 }
1866
Sujith Manoharan5955b2b2012-06-04 16:27:30 +05301867 if (ath9k_hw_mci_is_enabled(ah))
Sujith Manoharan528e5d32012-02-22 12:41:12 +05301868 ar9003_mci_stop_bt(ah, save_fullsleep);
Mohammed Shafi Shajakhan63d32962011-11-30 10:41:27 +05301869
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07001870 saveDefAntenna = REG_READ(ah, AR_DEF_ANTENNA);
1871 if (saveDefAntenna == 0)
1872 saveDefAntenna = 1;
1873
1874 macStaId1 = REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_BASE_RATE_11B;
1875
Felix Fietkau09d8e312013-11-18 20:14:43 +01001876 /* Save TSF before chip reset, a cold reset clears it */
Benjamin Bergbec9a942016-07-04 14:37:22 +02001877 getrawmonotonic(&tsf_ts);
Felix Fietkau09d8e312013-11-18 20:14:43 +01001878 tsf = ath9k_hw_gettsf64(ah);
Sujith46fe7822009-09-17 09:25:25 +05301879
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07001880 saveLedState = REG_READ(ah, AR_CFG_LED) &
1881 (AR_CFG_LED_ASSOC_CTL | AR_CFG_LED_MODE_SEL |
1882 AR_CFG_LED_BLINK_THRESH_SEL | AR_CFG_LED_BLINK_SLOW);
1883
1884 ath9k_hw_mark_phy_inactive(ah);
1885
Vasanthakumar Thiagarajan45ef6a0b2010-12-15 07:30:53 -08001886 ah->paprd_table_write_done = false;
1887
Sujith05020d22010-03-17 14:25:23 +05301888 /* Only required on the first reset */
Luis R. Rodriguezd7e7d222009-08-03 23:14:12 -04001889 if (AR_SREV_9271(ah) && ah->htc_reset_init) {
1890 REG_WRITE(ah,
1891 AR9271_RESET_POWER_DOWN_CONTROL,
1892 AR9271_RADIO_RF_RST);
1893 udelay(50);
1894 }
1895
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07001896 if (!ath9k_hw_chip_reset(ah, chan)) {
Joe Perches38002762010-12-02 19:12:36 -08001897 ath_err(common, "Chip reset failed\n");
Luis R. Rodriguezae8d2852008-12-23 15:58:40 -08001898 return -EINVAL;
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07001899 }
1900
Sujith05020d22010-03-17 14:25:23 +05301901 /* Only required on the first reset */
Luis R. Rodriguezd7e7d222009-08-03 23:14:12 -04001902 if (AR_SREV_9271(ah) && ah->htc_reset_init) {
1903 ah->htc_reset_init = false;
1904 REG_WRITE(ah,
1905 AR9271_RESET_POWER_DOWN_CONTROL,
1906 AR9271_GATE_MAC_CTL);
1907 udelay(50);
1908 }
1909
Sujith46fe7822009-09-17 09:25:25 +05301910 /* Restore TSF */
Benjamin Bergbec9a942016-07-04 14:37:22 +02001911 tsf_offset = ath9k_hw_get_tsf_offset(&tsf_ts, NULL);
1912 ath9k_hw_settsf64(ah, tsf + tsf_offset);
Sujith46fe7822009-09-17 09:25:25 +05301913
Felix Fietkau7a370812010-09-22 12:34:52 +02001914 if (AR_SREV_9280_20_OR_LATER(ah))
Vasanthakumar Thiagarajan369391d2009-01-21 19:24:13 +05301915 REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL, AR_GPIO_JTAG_DISABLE);
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07001916
Sujithe9141f72010-06-01 15:14:10 +05301917 if (!AR_SREV_9300_20_OR_LATER(ah))
1918 ar9002_hw_enable_async_fifo(ah);
1919
Luis R. Rodriguez25c56ee2009-09-13 23:04:44 -07001920 r = ath9k_hw_process_ini(ah, chan);
Luis R. Rodriguezae8d2852008-12-23 15:58:40 -08001921 if (r)
1922 return r;
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07001923
Lorenzo Bianconi935d00c2013-12-12 18:10:16 +01001924 ath9k_hw_set_rfmode(ah, chan);
1925
Sujith Manoharan5955b2b2012-06-04 16:27:30 +05301926 if (ath9k_hw_mci_is_enabled(ah))
Mohammed Shafi Shajakhan63d32962011-11-30 10:41:27 +05301927 ar9003_mci_reset(ah, false, IS_CHAN_2GHZ(chan), save_fullsleep);
1928
Felix Fietkauf860d522010-06-30 02:07:48 +02001929 /*
1930 * Some AR91xx SoC devices frequently fail to accept TSF writes
1931 * right after the chip reset. When that happens, write a new
Benjamin Bergbec9a942016-07-04 14:37:22 +02001932 * value after the initvals have been applied.
Felix Fietkauf860d522010-06-30 02:07:48 +02001933 */
1934 if (AR_SREV_9100(ah) && (ath9k_hw_gettsf64(ah) < tsf)) {
Benjamin Bergbec9a942016-07-04 14:37:22 +02001935 tsf_offset = ath9k_hw_get_tsf_offset(&tsf_ts, NULL);
1936 ath9k_hw_settsf64(ah, tsf + tsf_offset);
Felix Fietkauf860d522010-06-30 02:07:48 +02001937 }
1938
Sujith Manoharan15d2b582013-03-04 12:42:53 +05301939 ath9k_hw_init_mfp(ah);
Jouni Malinen0ced0e12009-01-08 13:32:13 +02001940
Felix Fietkau81c507a2013-10-11 23:30:55 +02001941 ath9k_hw_set_delta_slope(ah, chan);
Luis R. Rodriguez8fe65362010-04-15 17:38:14 -04001942 ath9k_hw_spur_mitigate_freq(ah, chan);
Sujithd6509152009-03-13 08:56:05 +05301943 ah->eep_ops->set_board_values(ah, chan);
Luis R. Rodrigueza7765822009-10-19 02:33:45 -04001944
Sujith Manoharan15d2b582013-03-04 12:42:53 +05301945 ath9k_hw_reset_opmode(ah, macStaId1, saveDefAntenna);
Sujith Manoharan00e00032011-01-26 21:59:05 +05301946
Luis R. Rodriguez8fe65362010-04-15 17:38:14 -04001947 r = ath9k_hw_rf_set_freq(ah, chan);
Luis R. Rodriguez0a3b7ba2009-10-19 02:33:40 -04001948 if (r)
1949 return r;
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07001950
Felix Fietkaudfdac8a2010-10-08 22:13:51 +02001951 ath9k_hw_set_clockrate(ah);
1952
Sujith Manoharan15d2b582013-03-04 12:42:53 +05301953 ath9k_hw_init_queues(ah);
Sujith2660b812009-02-09 13:27:26 +05301954 ath9k_hw_init_interrupt_masks(ah, ah->opmode);
Luis R. Rodrigueze36b27a2010-06-12 00:33:45 -04001955 ath9k_hw_ani_cache_ini_regs(ah);
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07001956 ath9k_hw_init_qos(ah);
1957
Sujith2660b812009-02-09 13:27:26 +05301958 if (ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
Miaoqing Panb2d70d42016-03-07 10:38:15 +08001959 ath9k_hw_gpio_request_in(ah, ah->rfkill_gpio, "ath9k-rfkill");
Johannes Berg3b319aa2009-06-13 14:50:26 +05301960
Felix Fietkau0005baf2010-01-15 02:33:40 +01001961 ath9k_hw_init_global_settings(ah);
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07001962
Felix Fietkaufe2b6af2011-07-09 11:12:51 +07001963 if (AR_SREV_9287(ah) && AR_SREV_9287_13_OR_LATER(ah)) {
1964 REG_SET_BIT(ah, AR_MAC_PCU_LOGIC_ANALYZER,
1965 AR_MAC_PCU_LOGIC_ANALYZER_DISBUG20768);
1966 REG_RMW_FIELD(ah, AR_AHB_MODE, AR_AHB_CUSTOM_BURST_EN,
1967 AR_AHB_CUSTOM_BURST_ASYNC_FIFO_VAL);
1968 REG_SET_BIT(ah, AR_PCU_MISC_MODE2,
1969 AR_PCU_MISC_MODE2_ENABLE_AGGWEP);
Vivek Natarajanac88b6e2009-07-23 10:59:57 +05301970 }
1971
Felix Fietkauca7a4de2011-03-23 20:57:26 +01001972 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PRESERVE_SEQNUM);
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07001973
1974 ath9k_hw_set_dma(ah);
1975
Rajkumar Manoharaned6ebd82012-06-11 12:19:34 +05301976 if (!ath9k_hw_mci_is_enabled(ah))
1977 REG_WRITE(ah, AR_OBS, 8);
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07001978
Oleksij Rempel7b37e0d2015-03-22 19:29:57 +01001979 ENABLE_REG_RMW_BUFFER(ah);
Sujith0ce024c2009-12-14 14:57:00 +05301980 if (ah->config.rx_intr_mitigation) {
Sujith Manoharana64e1a42014-01-23 08:20:30 +05301981 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_LAST, ah->config.rimt_last);
1982 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_FIRST, ah->config.rimt_first);
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07001983 }
1984
Vasanthakumar Thiagarajan7f62a132010-04-15 17:39:19 -04001985 if (ah->config.tx_intr_mitigation) {
1986 REG_RMW_FIELD(ah, AR_TIMT, AR_TIMT_LAST, 300);
1987 REG_RMW_FIELD(ah, AR_TIMT, AR_TIMT_FIRST, 750);
1988 }
Oleksij Rempel7b37e0d2015-03-22 19:29:57 +01001989 REG_RMW_BUFFER_FLUSH(ah);
Vasanthakumar Thiagarajan7f62a132010-04-15 17:39:19 -04001990
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07001991 ath9k_hw_init_bb(ah, chan);
1992
Rajkumar Manoharan77a5a662011-10-13 11:00:37 +05301993 if (caldata) {
Sujith Manoharan4b9b42b2013-09-11 16:36:31 +05301994 clear_bit(TXIQCAL_DONE, &caldata->cal_flags);
1995 clear_bit(TXCLCAL_DONE, &caldata->cal_flags);
Rajkumar Manoharan77a5a662011-10-13 11:00:37 +05301996 }
Luis R. Rodriguezae8d2852008-12-23 15:58:40 -08001997 if (!ath9k_hw_init_cal(ah, chan))
Joe Perches6badaaf2009-06-28 09:26:32 -07001998 return -EIO;
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07001999
Sujith Manoharan5955b2b2012-06-04 16:27:30 +05302000 if (ath9k_hw_mci_is_enabled(ah) && ar9003_mci_end_reset(ah, chan, caldata))
Sujith Manoharan528e5d32012-02-22 12:41:12 +05302001 return -EIO;
Mohammed Shafi Shajakhan63d32962011-11-30 10:41:27 +05302002
Sujith7d0d0df2010-04-16 11:53:57 +05302003 ENABLE_REGWRITE_BUFFER(ah);
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002004
Luis R. Rodriguez8fe65362010-04-15 17:38:14 -04002005 ath9k_hw_restore_chainmask(ah);
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002006 REG_WRITE(ah, AR_CFG_LED, saveLedState | AR_CFG_SCLK_32KHZ);
2007
Sujith7d0d0df2010-04-16 11:53:57 +05302008 REGWRITE_BUFFER_FLUSH(ah);
Sujith7d0d0df2010-04-16 11:53:57 +05302009
Sujith Manoharanf4c34af2014-11-16 06:11:03 +05302010 ath9k_hw_gen_timer_start_tsf2(ah);
2011
Sujith Manoharan15d2b582013-03-04 12:42:53 +05302012 ath9k_hw_init_desc(ah);
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002013
Sujith Manoharandbccdd12012-02-22 17:55:47 +05302014 if (ath9k_hw_btcoex_is_enabled(ah))
Vasanthakumar Thiagarajan42cc41e2009-08-26 21:08:45 +05302015 ath9k_hw_btcoex_enable(ah);
2016
Sujith Manoharan5955b2b2012-06-04 16:27:30 +05302017 if (ath9k_hw_mci_is_enabled(ah))
Sujith Manoharan528e5d32012-02-22 12:41:12 +05302018 ar9003_mci_check_bt(ah);
Mohammed Shafi Shajakhan63d32962011-11-30 10:41:27 +05302019
Felix Fietkau7b89fcc2014-10-25 17:19:32 +02002020 if (AR_SREV_9300_20_OR_LATER(ah)) {
2021 ath9k_hw_loadnf(ah, chan);
2022 ath9k_hw_start_nfcal(ah, true);
2023 }
Rajkumar Manoharan1fe860e2012-07-01 19:53:51 +05302024
Sujith Manoharana7abaf72013-12-24 10:44:21 +05302025 if (AR_SREV_9300_20_OR_LATER(ah))
Luis R. Rodriguezaea702b2010-05-13 13:33:43 -04002026 ar9003_hw_bb_watchdog_config(ah);
Sujith Manoharana7abaf72013-12-24 10:44:21 +05302027
2028 if (ah->config.hw_hang_checks & HW_PHYRESTART_CLC_WAR)
Rajkumar Manoharan51ac8cb2011-05-20 17:52:13 +05302029 ar9003_hw_disable_phy_restart(ah);
Rajkumar Manoharan51ac8cb2011-05-20 17:52:13 +05302030
Felix Fietkau691680b2011-03-19 13:55:38 +01002031 ath9k_hw_apply_gpio_override(ah);
2032
Sujith Manoharan7bdea962013-08-04 14:22:00 +05302033 if (AR_SREV_9565(ah) && common->bt_ant_diversity)
Sujith Manoharan362cd032012-09-16 08:06:36 +05302034 REG_SET_BIT(ah, AR_BTCOEX_WL_LNADIV, AR_BTCOEX_WL_LNADIV_FORCE_ON);
2035
Lorenzo Bianconi4307b0f2014-09-11 23:50:54 +02002036 if (ah->hw->conf.radar_enabled) {
2037 /* set HW specific DFS configuration */
Lorenzo Bianconi7a0a2602014-09-16 16:43:42 +02002038 ah->radar_conf.ext_channel = IS_CHAN_HT40(chan);
Lorenzo Bianconi4307b0f2014-09-11 23:50:54 +02002039 ath9k_hw_set_radar_params(ah);
2040 }
2041
Luis R. Rodriguezae8d2852008-12-23 15:58:40 -08002042 return 0;
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002043}
Luis R. Rodriguez7322fd12009-09-23 23:07:00 -04002044EXPORT_SYMBOL(ath9k_hw_reset);
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002045
Sujithf1dc5602008-10-29 10:16:30 +05302046/******************************/
2047/* Power Management (Chipset) */
2048/******************************/
2049
Luis R. Rodriguez42d5bc32010-04-15 17:38:12 -04002050/*
2051 * Notify Power Mgt is disabled in self-generated frames.
2052 * If requested, force chip to sleep.
2053 */
Sujith Manoharan31604cf2012-06-04 16:27:36 +05302054static void ath9k_set_power_sleep(struct ath_hw *ah)
Sujithf1dc5602008-10-29 10:16:30 +05302055{
2056 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
Senthil Balasubramanian2577c6e2011-09-13 22:38:18 +05302057
Sujith Manoharana4a29542012-09-10 09:20:03 +05302058 if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) {
Rajkumar Manoharan153dccd2012-06-04 16:28:47 +05302059 REG_CLR_BIT(ah, AR_TIMER_MODE, 0xff);
2060 REG_CLR_BIT(ah, AR_NDP2_TIMER_MODE, 0xff);
2061 REG_CLR_BIT(ah, AR_SLP32_INC, 0xfffff);
Sujith Manoharan31604cf2012-06-04 16:27:36 +05302062 /* xxx Required for WLAN only case ? */
2063 REG_WRITE(ah, AR_MCI_INTERRUPT_RX_MSG_EN, 0);
2064 udelay(100);
2065 }
Senthil Balasubramanian2577c6e2011-09-13 22:38:18 +05302066
Sujith Manoharan31604cf2012-06-04 16:27:36 +05302067 /*
2068 * Clear the RTC force wake bit to allow the
2069 * mac to go to sleep.
2070 */
2071 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN);
Senthil Balasubramanian2577c6e2011-09-13 22:38:18 +05302072
Rajkumar Manoharan153dccd2012-06-04 16:28:47 +05302073 if (ath9k_hw_mci_is_enabled(ah))
Sujith Manoharan31604cf2012-06-04 16:27:36 +05302074 udelay(100);
Sujithf1dc5602008-10-29 10:16:30 +05302075
Sujith Manoharan31604cf2012-06-04 16:27:36 +05302076 if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah))
2077 REG_WRITE(ah, AR_RC, AR_RC_AHB | AR_RC_HOSTIF);
2078
2079 /* Shutdown chip. Active low */
2080 if (!AR_SREV_5416(ah) && !AR_SREV_9271(ah)) {
2081 REG_CLR_BIT(ah, AR_RTC_RESET, AR_RTC_RESET_EN);
2082 udelay(2);
Sujithf1dc5602008-10-29 10:16:30 +05302083 }
Luis R. Rodriguez9a658d22010-06-21 18:38:47 -04002084
2085 /* Clear Bit 14 of AR_WA after putting chip into Full Sleep mode. */
Rafael J. Wysockia7322812011-11-26 23:37:43 +01002086 if (AR_SREV_9300_20_OR_LATER(ah))
2087 REG_WRITE(ah, AR_WA, ah->WARegVal & ~AR_WA_D3_L1_DISABLE);
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002088}
2089
Luis R. Rodriguezbbd79af2010-04-15 17:38:16 -04002090/*
2091 * Notify Power Management is enabled in self-generating
2092 * frames. If request, set power mode of chip to
2093 * auto/normal. Duration in units of 128us (1/8 TU).
2094 */
Sujith Manoharan31604cf2012-06-04 16:27:36 +05302095static void ath9k_set_power_network_sleep(struct ath_hw *ah)
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002096{
Sujith Manoharan31604cf2012-06-04 16:27:36 +05302097 struct ath9k_hw_capabilities *pCap = &ah->caps;
Senthil Balasubramanian2577c6e2011-09-13 22:38:18 +05302098
Sujithf1dc5602008-10-29 10:16:30 +05302099 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002100
Sujith Manoharan31604cf2012-06-04 16:27:36 +05302101 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
2102 /* Set WakeOnInterrupt bit; clear ForceWake bit */
2103 REG_WRITE(ah, AR_RTC_FORCE_WAKE,
2104 AR_RTC_FORCE_WAKE_ON_INT);
2105 } else {
Senthil Balasubramanian2577c6e2011-09-13 22:38:18 +05302106
Sujith Manoharan31604cf2012-06-04 16:27:36 +05302107 /* When chip goes into network sleep, it could be waken
2108 * up by MCI_INT interrupt caused by BT's HW messages
2109 * (LNA_xxx, CONT_xxx) which chould be in a very fast
2110 * rate (~100us). This will cause chip to leave and
2111 * re-enter network sleep mode frequently, which in
2112 * consequence will have WLAN MCI HW to generate lots of
2113 * SYS_WAKING and SYS_SLEEPING messages which will make
2114 * BT CPU to busy to process.
2115 */
Rajkumar Manoharan153dccd2012-06-04 16:28:47 +05302116 if (ath9k_hw_mci_is_enabled(ah))
2117 REG_CLR_BIT(ah, AR_MCI_INTERRUPT_RX_MSG_EN,
2118 AR_MCI_INTERRUPT_RX_HW_MSG_MASK);
Sujith Manoharan31604cf2012-06-04 16:27:36 +05302119 /*
2120 * Clear the RTC force wake bit to allow the
2121 * mac to go to sleep.
2122 */
Rajkumar Manoharan153dccd2012-06-04 16:28:47 +05302123 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN);
Sujith Manoharan31604cf2012-06-04 16:27:36 +05302124
Rajkumar Manoharan153dccd2012-06-04 16:28:47 +05302125 if (ath9k_hw_mci_is_enabled(ah))
Sujith Manoharan31604cf2012-06-04 16:27:36 +05302126 udelay(30);
Sujithf1dc5602008-10-29 10:16:30 +05302127 }
Luis R. Rodriguez9a658d22010-06-21 18:38:47 -04002128
2129 /* Clear Bit 14 of AR_WA after putting chip into Net Sleep mode. */
2130 if (AR_SREV_9300_20_OR_LATER(ah))
2131 REG_WRITE(ah, AR_WA, ah->WARegVal & ~AR_WA_D3_L1_DISABLE);
Sujithf1dc5602008-10-29 10:16:30 +05302132}
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002133
Sujith Manoharan31604cf2012-06-04 16:27:36 +05302134static bool ath9k_hw_set_power_awake(struct ath_hw *ah)
Sujithf1dc5602008-10-29 10:16:30 +05302135{
2136 u32 val;
2137 int i;
2138
Luis R. Rodriguez9a658d22010-06-21 18:38:47 -04002139 /* Set Bits 14 and 17 of AR_WA before powering on the chip. */
2140 if (AR_SREV_9300_20_OR_LATER(ah)) {
2141 REG_WRITE(ah, AR_WA, ah->WARegVal);
2142 udelay(10);
2143 }
2144
Sujith Manoharan31604cf2012-06-04 16:27:36 +05302145 if ((REG_READ(ah, AR_RTC_STATUS) &
2146 AR_RTC_STATUS_M) == AR_RTC_STATUS_SHUTDOWN) {
2147 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)) {
Sujithf1dc5602008-10-29 10:16:30 +05302148 return false;
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002149 }
Sujith Manoharan31604cf2012-06-04 16:27:36 +05302150 if (!AR_SREV_9300_20_OR_LATER(ah))
2151 ath9k_hw_init_pll(ah, NULL);
2152 }
2153 if (AR_SREV_9100(ah))
2154 REG_SET_BIT(ah, AR_RTC_RESET,
2155 AR_RTC_RESET_EN);
2156
2157 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE,
2158 AR_RTC_FORCE_WAKE_EN);
Sujith Manoharan04575f22013-12-28 09:47:13 +05302159 if (AR_SREV_9100(ah))
Sujith Manoharan3683a072014-02-04 08:37:52 +05302160 mdelay(10);
Sujith Manoharan04575f22013-12-28 09:47:13 +05302161 else
2162 udelay(50);
Sujith Manoharan31604cf2012-06-04 16:27:36 +05302163
2164 for (i = POWER_UP_TIME / 50; i > 0; i--) {
2165 val = REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M;
2166 if (val == AR_RTC_STATUS_ON)
2167 break;
2168 udelay(50);
2169 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE,
2170 AR_RTC_FORCE_WAKE_EN);
2171 }
2172 if (i == 0) {
2173 ath_err(ath9k_hw_common(ah),
2174 "Failed to wakeup in %uus\n",
2175 POWER_UP_TIME / 20);
2176 return false;
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002177 }
2178
Rajkumar Manoharancdbe4082012-10-25 17:16:53 +05302179 if (ath9k_hw_mci_is_enabled(ah))
2180 ar9003_mci_set_power_awake(ah);
2181
Sujithf1dc5602008-10-29 10:16:30 +05302182 REG_CLR_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
2183
2184 return true;
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002185}
2186
Luis R. Rodriguez9ecdef42009-09-09 21:10:09 -07002187bool ath9k_hw_setpower(struct ath_hw *ah, enum ath9k_power_mode mode)
Sujithf1dc5602008-10-29 10:16:30 +05302188{
Luis R. Rodriguezc46917b2009-09-13 02:42:02 -07002189 struct ath_common *common = ath9k_hw_common(ah);
Sujith Manoharan31604cf2012-06-04 16:27:36 +05302190 int status = true;
Sujithf1dc5602008-10-29 10:16:30 +05302191 static const char *modes[] = {
2192 "AWAKE",
2193 "FULL-SLEEP",
2194 "NETWORK SLEEP",
2195 "UNDEFINED"
2196 };
Sujithf1dc5602008-10-29 10:16:30 +05302197
Gabor Juhoscbdec972009-07-24 17:27:22 +02002198 if (ah->power_mode == mode)
2199 return status;
2200
Joe Perchesd2182b62011-12-15 14:55:53 -08002201 ath_dbg(common, RESET, "%s -> %s\n",
Joe Perches226afe62010-12-02 19:12:37 -08002202 modes[ah->power_mode], modes[mode]);
Sujithf1dc5602008-10-29 10:16:30 +05302203
2204 switch (mode) {
2205 case ATH9K_PM_AWAKE:
Sujith Manoharan31604cf2012-06-04 16:27:36 +05302206 status = ath9k_hw_set_power_awake(ah);
Sujithf1dc5602008-10-29 10:16:30 +05302207 break;
2208 case ATH9K_PM_FULL_SLEEP:
Sujith Manoharan5955b2b2012-06-04 16:27:30 +05302209 if (ath9k_hw_mci_is_enabled(ah))
Sujith Manoharand1ca8b82012-02-22 12:41:01 +05302210 ar9003_mci_set_full_sleep(ah);
Mohammed Shafi Shajakhan10109112011-11-30 10:41:24 +05302211
Sujith Manoharan31604cf2012-06-04 16:27:36 +05302212 ath9k_set_power_sleep(ah);
Sujith2660b812009-02-09 13:27:26 +05302213 ah->chip_fullsleep = true;
Sujithf1dc5602008-10-29 10:16:30 +05302214 break;
2215 case ATH9K_PM_NETWORK_SLEEP:
Sujith Manoharan31604cf2012-06-04 16:27:36 +05302216 ath9k_set_power_network_sleep(ah);
Sujithf1dc5602008-10-29 10:16:30 +05302217 break;
2218 default:
Joe Perches38002762010-12-02 19:12:36 -08002219 ath_err(common, "Unknown power mode %u\n", mode);
Sujithf1dc5602008-10-29 10:16:30 +05302220 return false;
2221 }
Sujith2660b812009-02-09 13:27:26 +05302222 ah->power_mode = mode;
Sujithf1dc5602008-10-29 10:16:30 +05302223
Luis R. Rodriguez69f4aab2010-12-07 15:13:23 -08002224 /*
2225 * XXX: If this warning never comes up after a while then
2226 * simply keep the ATH_DBG_WARN_ON_ONCE() but make
2227 * ath9k_hw_setpower() return type void.
2228 */
Sujith Manoharan97dcec52010-12-20 08:02:42 +05302229
2230 if (!(ah->ah_flags & AH_UNPLUGGED))
2231 ATH_DBG_WARN_ON_ONCE(!status);
Luis R. Rodriguez69f4aab2010-12-07 15:13:23 -08002232
Sujithf1dc5602008-10-29 10:16:30 +05302233 return status;
2234}
Luis R. Rodriguez7322fd12009-09-23 23:07:00 -04002235EXPORT_SYMBOL(ath9k_hw_setpower);
Sujithf1dc5602008-10-29 10:16:30 +05302236
Sujithf1dc5602008-10-29 10:16:30 +05302237/*******************/
2238/* Beacon Handling */
2239/*******************/
2240
Sujithcbe61d82009-02-09 13:27:12 +05302241void ath9k_hw_beaconinit(struct ath_hw *ah, u32 next_beacon, u32 beacon_period)
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002242{
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002243 int flags = 0;
2244
Sujith7d0d0df2010-04-16 11:53:57 +05302245 ENABLE_REGWRITE_BUFFER(ah);
2246
Sujith2660b812009-02-09 13:27:26 +05302247 switch (ah->opmode) {
Colin McCabed97809d2008-12-01 13:38:55 -08002248 case NL80211_IFTYPE_ADHOC:
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002249 REG_SET_BIT(ah, AR_TXCFG,
2250 AR_TXCFG_ADHOC_BEACON_ATIM_TX_POLICY);
Thomas Pedersen2664d662013-05-08 10:16:48 -07002251 case NL80211_IFTYPE_MESH_POINT:
Colin McCabed97809d2008-12-01 13:38:55 -08002252 case NL80211_IFTYPE_AP:
Felix Fietkaudd347f22011-03-22 21:54:17 +01002253 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, next_beacon);
2254 REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT, next_beacon -
2255 TU_TO_USEC(ah->config.dma_beacon_response_time));
2256 REG_WRITE(ah, AR_NEXT_SWBA, next_beacon -
2257 TU_TO_USEC(ah->config.sw_beacon_response_time));
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002258 flags |=
2259 AR_TBTT_TIMER_EN | AR_DBA_TIMER_EN | AR_SWBA_TIMER_EN;
2260 break;
Colin McCabed97809d2008-12-01 13:38:55 -08002261 default:
Joe Perchesd2182b62011-12-15 14:55:53 -08002262 ath_dbg(ath9k_hw_common(ah), BEACON,
2263 "%s: unsupported opmode: %d\n", __func__, ah->opmode);
Colin McCabed97809d2008-12-01 13:38:55 -08002264 return;
2265 break;
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002266 }
2267
Felix Fietkaudd347f22011-03-22 21:54:17 +01002268 REG_WRITE(ah, AR_BEACON_PERIOD, beacon_period);
2269 REG_WRITE(ah, AR_DMA_BEACON_PERIOD, beacon_period);
2270 REG_WRITE(ah, AR_SWBA_PERIOD, beacon_period);
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002271
Sujith7d0d0df2010-04-16 11:53:57 +05302272 REGWRITE_BUFFER_FLUSH(ah);
Sujith7d0d0df2010-04-16 11:53:57 +05302273
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002274 REG_SET_BIT(ah, AR_TIMER_MODE, flags);
2275}
Luis R. Rodriguez7322fd12009-09-23 23:07:00 -04002276EXPORT_SYMBOL(ath9k_hw_beaconinit);
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002277
Sujithcbe61d82009-02-09 13:27:12 +05302278void ath9k_hw_set_sta_beacon_timers(struct ath_hw *ah,
Sujithf1dc5602008-10-29 10:16:30 +05302279 const struct ath9k_beacon_state *bs)
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002280{
2281 u32 nextTbtt, beaconintval, dtimperiod, beacontimeout;
Sujith2660b812009-02-09 13:27:26 +05302282 struct ath9k_hw_capabilities *pCap = &ah->caps;
Luis R. Rodriguezc46917b2009-09-13 02:42:02 -07002283 struct ath_common *common = ath9k_hw_common(ah);
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002284
Sujith7d0d0df2010-04-16 11:53:57 +05302285 ENABLE_REGWRITE_BUFFER(ah);
2286
Felix Fietkau4ed15762013-12-14 18:03:44 +01002287 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, bs->bs_nexttbtt);
2288 REG_WRITE(ah, AR_BEACON_PERIOD, bs->bs_intval);
2289 REG_WRITE(ah, AR_DMA_BEACON_PERIOD, bs->bs_intval);
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002290
Sujith7d0d0df2010-04-16 11:53:57 +05302291 REGWRITE_BUFFER_FLUSH(ah);
Sujith7d0d0df2010-04-16 11:53:57 +05302292
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002293 REG_RMW_FIELD(ah, AR_RSSI_THR,
2294 AR_RSSI_THR_BM_THR, bs->bs_bmissthreshold);
2295
Rajkumar Manoharanf29f5c02011-05-20 17:52:11 +05302296 beaconintval = bs->bs_intval;
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002297
2298 if (bs->bs_sleepduration > beaconintval)
2299 beaconintval = bs->bs_sleepduration;
2300
2301 dtimperiod = bs->bs_dtimperiod;
2302 if (bs->bs_sleepduration > dtimperiod)
2303 dtimperiod = bs->bs_sleepduration;
2304
2305 if (beaconintval == dtimperiod)
2306 nextTbtt = bs->bs_nextdtim;
2307 else
2308 nextTbtt = bs->bs_nexttbtt;
2309
Janusz Dziedzic58bb9ca2015-11-27 09:37:06 +01002310 ath_dbg(common, BEACON, "next DTIM %u\n", bs->bs_nextdtim);
2311 ath_dbg(common, BEACON, "next beacon %u\n", nextTbtt);
2312 ath_dbg(common, BEACON, "beacon period %u\n", beaconintval);
2313 ath_dbg(common, BEACON, "DTIM period %u\n", dtimperiod);
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002314
Sujith7d0d0df2010-04-16 11:53:57 +05302315 ENABLE_REGWRITE_BUFFER(ah);
2316
Felix Fietkau4ed15762013-12-14 18:03:44 +01002317 REG_WRITE(ah, AR_NEXT_DTIM, bs->bs_nextdtim - SLEEP_SLOP);
2318 REG_WRITE(ah, AR_NEXT_TIM, nextTbtt - SLEEP_SLOP);
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002319
2320 REG_WRITE(ah, AR_SLEEP1,
2321 SM((CAB_TIMEOUT_VAL << 3), AR_SLEEP1_CAB_TIMEOUT)
2322 | AR_SLEEP1_ASSUME_DTIM);
2323
Sujith60b67f52008-08-07 10:52:38 +05302324 if (pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002325 beacontimeout = (BEACON_TIMEOUT_VAL << 3);
2326 else
2327 beacontimeout = MIN_BEACON_TIMEOUT_VAL;
2328
2329 REG_WRITE(ah, AR_SLEEP2,
2330 SM(beacontimeout, AR_SLEEP2_BEACON_TIMEOUT));
2331
Felix Fietkau4ed15762013-12-14 18:03:44 +01002332 REG_WRITE(ah, AR_TIM_PERIOD, beaconintval);
2333 REG_WRITE(ah, AR_DTIM_PERIOD, dtimperiod);
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002334
Sujith7d0d0df2010-04-16 11:53:57 +05302335 REGWRITE_BUFFER_FLUSH(ah);
Sujith7d0d0df2010-04-16 11:53:57 +05302336
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002337 REG_SET_BIT(ah, AR_TIMER_MODE,
2338 AR_TBTT_TIMER_EN | AR_TIM_TIMER_EN |
2339 AR_DTIM_TIMER_EN);
2340
Sujith4af9cf42009-02-12 10:06:47 +05302341 /* TSF Out of Range Threshold */
2342 REG_WRITE(ah, AR_TSFOOR_THRESHOLD, bs->bs_tsfoor_threshold);
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002343}
Luis R. Rodriguez7322fd12009-09-23 23:07:00 -04002344EXPORT_SYMBOL(ath9k_hw_set_sta_beacon_timers);
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002345
Sujithf1dc5602008-10-29 10:16:30 +05302346/*******************/
2347/* HW Capabilities */
2348/*******************/
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002349
Felix Fietkau60540692011-07-19 08:46:44 +02002350static u8 fixup_chainmask(u8 chip_chainmask, u8 eeprom_chainmask)
2351{
2352 eeprom_chainmask &= chip_chainmask;
2353 if (eeprom_chainmask)
2354 return eeprom_chainmask;
2355 else
2356 return chip_chainmask;
2357}
2358
Zefir Kurtisi9a66af32011-12-14 20:16:33 -08002359/**
2360 * ath9k_hw_dfs_tested - checks if DFS has been tested with used chipset
2361 * @ah: the atheros hardware data structure
2362 *
2363 * We enable DFS support upstream on chipsets which have passed a series
2364 * of tests. The testing requirements are going to be documented. Desired
2365 * test requirements are documented at:
2366 *
2367 * http://wireless.kernel.org/en/users/Drivers/ath9k/dfs
2368 *
2369 * Once a new chipset gets properly tested an individual commit can be used
2370 * to document the testing for DFS for that chipset.
2371 */
2372static bool ath9k_hw_dfs_tested(struct ath_hw *ah)
2373{
2374
2375 switch (ah->hw_version.macVersion) {
Zefir Kurtisi73e49372013-04-03 18:31:31 +02002376 /* for temporary testing DFS with 9280 */
2377 case AR_SREV_VERSION_9280:
Zefir Kurtisi9a66af32011-12-14 20:16:33 -08002378 /* AR9580 will likely be our first target to get testing on */
2379 case AR_SREV_VERSION_9580:
Zefir Kurtisi73e49372013-04-03 18:31:31 +02002380 return true;
Zefir Kurtisi9a66af32011-12-14 20:16:33 -08002381 default:
2382 return false;
2383 }
2384}
2385
Miaoqing Pana01ab812016-03-07 10:38:14 +08002386static void ath9k_gpio_cap_init(struct ath_hw *ah)
2387{
2388 struct ath9k_hw_capabilities *pCap = &ah->caps;
2389
2390 if (AR_SREV_9271(ah)) {
2391 pCap->num_gpio_pins = AR9271_NUM_GPIO;
2392 pCap->gpio_mask = AR9271_GPIO_MASK;
2393 } else if (AR_DEVID_7010(ah)) {
2394 pCap->num_gpio_pins = AR7010_NUM_GPIO;
2395 pCap->gpio_mask = AR7010_GPIO_MASK;
2396 } else if (AR_SREV_9287(ah)) {
2397 pCap->num_gpio_pins = AR9287_NUM_GPIO;
2398 pCap->gpio_mask = AR9287_GPIO_MASK;
2399 } else if (AR_SREV_9285(ah)) {
2400 pCap->num_gpio_pins = AR9285_NUM_GPIO;
2401 pCap->gpio_mask = AR9285_GPIO_MASK;
2402 } else if (AR_SREV_9280(ah)) {
2403 pCap->num_gpio_pins = AR9280_NUM_GPIO;
2404 pCap->gpio_mask = AR9280_GPIO_MASK;
2405 } else if (AR_SREV_9300(ah)) {
2406 pCap->num_gpio_pins = AR9300_NUM_GPIO;
2407 pCap->gpio_mask = AR9300_GPIO_MASK;
2408 } else if (AR_SREV_9330(ah)) {
2409 pCap->num_gpio_pins = AR9330_NUM_GPIO;
2410 pCap->gpio_mask = AR9330_GPIO_MASK;
2411 } else if (AR_SREV_9340(ah)) {
2412 pCap->num_gpio_pins = AR9340_NUM_GPIO;
2413 pCap->gpio_mask = AR9340_GPIO_MASK;
2414 } else if (AR_SREV_9462(ah)) {
2415 pCap->num_gpio_pins = AR9462_NUM_GPIO;
2416 pCap->gpio_mask = AR9462_GPIO_MASK;
2417 } else if (AR_SREV_9485(ah)) {
2418 pCap->num_gpio_pins = AR9485_NUM_GPIO;
2419 pCap->gpio_mask = AR9485_GPIO_MASK;
2420 } else if (AR_SREV_9531(ah)) {
2421 pCap->num_gpio_pins = AR9531_NUM_GPIO;
2422 pCap->gpio_mask = AR9531_GPIO_MASK;
2423 } else if (AR_SREV_9550(ah)) {
2424 pCap->num_gpio_pins = AR9550_NUM_GPIO;
2425 pCap->gpio_mask = AR9550_GPIO_MASK;
2426 } else if (AR_SREV_9561(ah)) {
2427 pCap->num_gpio_pins = AR9561_NUM_GPIO;
2428 pCap->gpio_mask = AR9561_GPIO_MASK;
2429 } else if (AR_SREV_9565(ah)) {
2430 pCap->num_gpio_pins = AR9565_NUM_GPIO;
2431 pCap->gpio_mask = AR9565_GPIO_MASK;
2432 } else if (AR_SREV_9580(ah)) {
2433 pCap->num_gpio_pins = AR9580_NUM_GPIO;
2434 pCap->gpio_mask = AR9580_GPIO_MASK;
2435 } else {
2436 pCap->num_gpio_pins = AR_NUM_GPIO;
2437 pCap->gpio_mask = AR_GPIO_MASK;
2438 }
2439}
2440
Gabor Juhosa9a29ce2009-11-27 12:01:35 +01002441int ath9k_hw_fill_cap_info(struct ath_hw *ah)
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002442{
Sujith2660b812009-02-09 13:27:26 +05302443 struct ath9k_hw_capabilities *pCap = &ah->caps;
Luis R. Rodriguez608b88c2009-08-17 18:07:23 -07002444 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
Luis R. Rodriguezc46917b2009-09-13 02:42:02 -07002445 struct ath_common *common = ath9k_hw_common(ah);
Luis R. Rodriguez608b88c2009-08-17 18:07:23 -07002446
Sujith Manoharan0ff2b5c2011-04-20 11:00:34 +05302447 u16 eeval;
Vasanthakumar Thiagarajan47c80de2010-12-06 04:27:43 -08002448 u8 ant_div_ctl1, tx_chainmask, rx_chainmask;
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002449
Sujithf74df6f2009-02-09 13:27:24 +05302450 eeval = ah->eep_ops->get_eeprom(ah, EEP_REG_0);
Luis R. Rodriguez608b88c2009-08-17 18:07:23 -07002451 regulatory->current_rd = eeval;
Sujithf1dc5602008-10-29 10:16:30 +05302452
Sujith2660b812009-02-09 13:27:26 +05302453 if (ah->opmode != NL80211_IFTYPE_AP &&
Sujithd535a422009-02-09 13:27:06 +05302454 ah->hw_version.subvendorid == AR_SUBVENDOR_ID_NEW_A) {
Luis R. Rodriguez608b88c2009-08-17 18:07:23 -07002455 if (regulatory->current_rd == 0x64 ||
2456 regulatory->current_rd == 0x65)
2457 regulatory->current_rd += 5;
2458 else if (regulatory->current_rd == 0x41)
2459 regulatory->current_rd = 0x43;
Joe Perchesd2182b62011-12-15 14:55:53 -08002460 ath_dbg(common, REGULATORY, "regdomain mapped to 0x%x\n",
2461 regulatory->current_rd);
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002462 }
Sujithdc2222a2008-08-14 13:26:55 +05302463
Sujithf74df6f2009-02-09 13:27:24 +05302464 eeval = ah->eep_ops->get_eeprom(ah, EEP_OP_MODE);
Felix Fietkau34689682014-10-25 17:19:34 +02002465
2466 if (eeval & AR5416_OPFLAGS_11A) {
2467 if (ah->disable_5ghz)
2468 ath_warn(common, "disabling 5GHz band\n");
2469 else
2470 pCap->hw_caps |= ATH9K_HW_CAP_5GHZ;
Gabor Juhosa9a29ce2009-11-27 12:01:35 +01002471 }
2472
Felix Fietkau34689682014-10-25 17:19:34 +02002473 if (eeval & AR5416_OPFLAGS_11G) {
2474 if (ah->disable_2ghz)
2475 ath_warn(common, "disabling 2GHz band\n");
2476 else
2477 pCap->hw_caps |= ATH9K_HW_CAP_2GHZ;
2478 }
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002479
Felix Fietkau34689682014-10-25 17:19:34 +02002480 if ((pCap->hw_caps & (ATH9K_HW_CAP_2GHZ | ATH9K_HW_CAP_5GHZ)) == 0) {
2481 ath_err(common, "both bands are disabled\n");
2482 return -EINVAL;
2483 }
Sujithf1dc5602008-10-29 10:16:30 +05302484
Miaoqing Pandb7b5422016-08-04 15:48:34 +08002485 ath9k_gpio_cap_init(ah);
2486
Sujith Manoharane41db612012-09-10 09:20:12 +05302487 if (AR_SREV_9485(ah) ||
2488 AR_SREV_9285(ah) ||
2489 AR_SREV_9330(ah) ||
2490 AR_SREV_9565(ah))
Sujith Manoharanee79ccd2014-11-16 06:11:04 +05302491 pCap->chip_chainmask = 1;
Felix Fietkau60540692011-07-19 08:46:44 +02002492 else if (!AR_SREV_9280_20_OR_LATER(ah))
Sujith Manoharanee79ccd2014-11-16 06:11:04 +05302493 pCap->chip_chainmask = 7;
2494 else if (!AR_SREV_9300_20_OR_LATER(ah) ||
2495 AR_SREV_9340(ah) ||
2496 AR_SREV_9462(ah) ||
2497 AR_SREV_9531(ah))
2498 pCap->chip_chainmask = 3;
Felix Fietkau60540692011-07-19 08:46:44 +02002499 else
Sujith Manoharanee79ccd2014-11-16 06:11:04 +05302500 pCap->chip_chainmask = 7;
Felix Fietkau60540692011-07-19 08:46:44 +02002501
Sujithf74df6f2009-02-09 13:27:24 +05302502 pCap->tx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_TX_MASK);
Luis R. Rodriguezd7e7d222009-08-03 23:14:12 -04002503 /*
2504 * For AR9271 we will temporarilly uses the rx chainmax as read from
2505 * the EEPROM.
2506 */
Sujith8147f5d2009-02-20 15:13:23 +05302507 if ((ah->hw_version.devid == AR5416_DEVID_PCI) &&
Luis R. Rodriguezd7e7d222009-08-03 23:14:12 -04002508 !(eeval & AR5416_OPFLAGS_11A) &&
2509 !(AR_SREV_9271(ah)))
2510 /* CB71: GPIO 0 is pulled down to indicate 3 rx chains */
Sujith8147f5d2009-02-20 15:13:23 +05302511 pCap->rx_chainmask = ath9k_hw_gpio_get(ah, 0) ? 0x5 : 0x7;
Felix Fietkau598cdd52011-03-19 13:55:42 +01002512 else if (AR_SREV_9100(ah))
2513 pCap->rx_chainmask = 0x7;
Sujith8147f5d2009-02-20 15:13:23 +05302514 else
Luis R. Rodriguezd7e7d222009-08-03 23:14:12 -04002515 /* Use rx_chainmask from EEPROM. */
Sujith8147f5d2009-02-20 15:13:23 +05302516 pCap->rx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_RX_MASK);
Sujithf1dc5602008-10-29 10:16:30 +05302517
Sujith Manoharanee79ccd2014-11-16 06:11:04 +05302518 pCap->tx_chainmask = fixup_chainmask(pCap->chip_chainmask, pCap->tx_chainmask);
2519 pCap->rx_chainmask = fixup_chainmask(pCap->chip_chainmask, pCap->rx_chainmask);
Felix Fietkau82b2d332011-09-03 01:40:23 +02002520 ah->txchainmask = pCap->tx_chainmask;
2521 ah->rxchainmask = pCap->rx_chainmask;
Felix Fietkau60540692011-07-19 08:46:44 +02002522
Felix Fietkau7a370812010-09-22 12:34:52 +02002523 ah->misc_mode |= AR_PCU_MIC_NEW_LOC_ENA;
Sujithf1dc5602008-10-29 10:16:30 +05302524
Felix Fietkau02d2ebb2010-11-22 15:39:39 +01002525 /* enable key search for every frame in an aggregate */
2526 if (AR_SREV_9300_20_OR_LATER(ah))
2527 ah->misc_mode |= AR_PCU_ALWAYS_PERFORM_KEYSEARCH;
2528
Bruno Randolfce2220d2010-09-17 11:36:25 +09002529 common->crypt_caps |= ATH_CRYPT_CAP_CIPHER_AESCCM;
2530
Felix Fietkau0db156e2011-03-23 20:57:29 +01002531 if (ah->hw_version.devid != AR2427_DEVID_PCIE)
Sujithf1dc5602008-10-29 10:16:30 +05302532 pCap->hw_caps |= ATH9K_HW_CAP_HT;
2533 else
2534 pCap->hw_caps &= ~ATH9K_HW_CAP_HT;
2535
Mohammed Shafi Shajakhan1b2538b2011-12-07 16:51:39 +05302536 if (AR_SREV_9160_10_OR_LATER(ah) || AR_SREV_9100(ah))
Sujithf1dc5602008-10-29 10:16:30 +05302537 pCap->rts_aggr_limit = ATH_AMPDU_LIMIT_MAX;
Mohammed Shafi Shajakhan1b2538b2011-12-07 16:51:39 +05302538 else
Sujithf1dc5602008-10-29 10:16:30 +05302539 pCap->rts_aggr_limit = (8 * 1024);
Sujithf1dc5602008-10-29 10:16:30 +05302540
Johannes Berg74e13062013-07-03 20:55:38 +02002541#ifdef CONFIG_ATH9K_RFKILL
Sujith2660b812009-02-09 13:27:26 +05302542 ah->rfsilent = ah->eep_ops->get_eeprom(ah, EEP_RF_SILENT);
2543 if (ah->rfsilent & EEP_RFSILENT_ENABLED) {
2544 ah->rfkill_gpio =
2545 MS(ah->rfsilent, EEP_RFSILENT_GPIO_SEL);
2546 ah->rfkill_polarity =
2547 MS(ah->rfsilent, EEP_RFSILENT_POLARITY);
Sujithf1dc5602008-10-29 10:16:30 +05302548
2549 pCap->hw_caps |= ATH9K_HW_CAP_RFSILENT;
2550 }
2551#endif
Vasanthakumar Thiagarajand5d11542010-05-17 18:57:56 -07002552 if (AR_SREV_9271(ah) || AR_SREV_9300_20_OR_LATER(ah))
Vivek Natarajanbde748a2010-04-05 14:48:05 +05302553 pCap->hw_caps |= ATH9K_HW_CAP_AUTOSLEEP;
2554 else
2555 pCap->hw_caps &= ~ATH9K_HW_CAP_AUTOSLEEP;
Sujithf1dc5602008-10-29 10:16:30 +05302556
Senthil Balasubramaniane7594072008-12-08 19:43:48 +05302557 if (AR_SREV_9280(ah) || AR_SREV_9285(ah))
Sujithf1dc5602008-10-29 10:16:30 +05302558 pCap->hw_caps &= ~ATH9K_HW_CAP_4KB_SPLITTRANS;
2559 else
2560 pCap->hw_caps |= ATH9K_HW_CAP_4KB_SPLITTRANS;
2561
Vasanthakumar Thiagarajanceb26442010-04-15 17:38:25 -04002562 if (AR_SREV_9300_20_OR_LATER(ah)) {
Vasanthakumar Thiagarajan784ad502010-12-06 04:27:40 -08002563 pCap->hw_caps |= ATH9K_HW_CAP_EDMA | ATH9K_HW_CAP_FASTCLOCK;
Miaoqing Panede6a5e2014-12-19 06:33:59 +05302564 if (!AR_SREV_9330(ah) && !AR_SREV_9485(ah) &&
2565 !AR_SREV_9561(ah) && !AR_SREV_9565(ah))
Vasanthakumar Thiagarajan784ad502010-12-06 04:27:40 -08002566 pCap->hw_caps |= ATH9K_HW_CAP_LDPC;
2567
Vasanthakumar Thiagarajanceb26442010-04-15 17:38:25 -04002568 pCap->rx_hp_qdepth = ATH9K_HW_RX_HP_QDEPTH;
2569 pCap->rx_lp_qdepth = ATH9K_HW_RX_LP_QDEPTH;
2570 pCap->rx_status_len = sizeof(struct ar9003_rxs);
Vasanthakumar Thiagarajan162c3be2010-04-15 17:38:41 -04002571 pCap->tx_desc_len = sizeof(struct ar9003_txc);
Vasanthakumar Thiagarajan5088c2f2010-04-15 17:39:34 -04002572 pCap->txs_len = sizeof(struct ar9003_txs);
Vasanthakumar Thiagarajan162c3be2010-04-15 17:38:41 -04002573 } else {
2574 pCap->tx_desc_len = sizeof(struct ath_desc);
Felix Fietkaua949b172011-07-09 11:12:47 +07002575 if (AR_SREV_9280_20(ah))
Felix Fietkau6b42e8d2010-04-26 15:04:35 -04002576 pCap->hw_caps |= ATH9K_HW_CAP_FASTCLOCK;
Vasanthakumar Thiagarajanceb26442010-04-15 17:38:25 -04002577 }
Vasanthakumar Thiagarajan1adf02f2010-04-15 17:38:24 -04002578
Vasanthakumar Thiagarajan6c84ce02010-04-15 17:39:16 -04002579 if (AR_SREV_9300_20_OR_LATER(ah))
2580 pCap->hw_caps |= ATH9K_HW_CAP_RAC_SUPPORTED;
2581
Miaoqing Panede6a5e2014-12-19 06:33:59 +05302582 if (AR_SREV_9561(ah))
2583 ah->ent_mode = 0x3BDA000;
2584 else if (AR_SREV_9300_20_OR_LATER(ah))
Senthil Balasubramanian6ee63f52010-11-10 05:03:16 -08002585 ah->ent_mode = REG_READ(ah, AR_ENT_OTP);
2586
Felix Fietkaua42acef2010-09-22 12:34:54 +02002587 if (AR_SREV_9287_11_OR_LATER(ah) || AR_SREV_9271(ah))
Vasanthakumar Thiagarajan6473d242010-05-13 18:42:38 -07002588 pCap->hw_caps |= ATH9K_HW_CAP_SGI_20;
2589
Sujith Manoharanf85c3372013-08-04 14:21:53 +05302590 if (AR_SREV_9285(ah)) {
Vasanthakumar Thiagarajan754dc532010-09-02 01:34:41 -07002591 if (ah->eep_ops->get_eeprom(ah, EEP_MODAL_VER) >= 3) {
2592 ant_div_ctl1 =
2593 ah->eep_ops->get_eeprom(ah, EEP_ANT_DIV_CTL1);
Sujith Manoharanf85c3372013-08-04 14:21:53 +05302594 if ((ant_div_ctl1 & 0x1) && ((ant_div_ctl1 >> 3) & 0x1)) {
Vasanthakumar Thiagarajan754dc532010-09-02 01:34:41 -07002595 pCap->hw_caps |= ATH9K_HW_CAP_ANT_DIV_COMB;
Sujith Manoharanf85c3372013-08-04 14:21:53 +05302596 ath_info(common, "Enable LNA combining\n");
2597 }
Vasanthakumar Thiagarajan754dc532010-09-02 01:34:41 -07002598 }
Sujith Manoharanf85c3372013-08-04 14:21:53 +05302599 }
2600
Mohammed Shafi Shajakhanea066d52010-11-23 20:42:27 +05302601 if (AR_SREV_9300_20_OR_LATER(ah)) {
2602 if (ah->eep_ops->get_eeprom(ah, EEP_CHAIN_MASK_REDUCE))
2603 pCap->hw_caps |= ATH9K_HW_CAP_APM;
2604 }
2605
Sujith Manoharan06236e52012-09-16 08:07:12 +05302606 if (AR_SREV_9330(ah) || AR_SREV_9485(ah) || AR_SREV_9565(ah)) {
Mohammed Shafi Shajakhan21d2c632011-05-13 20:29:31 +05302607 ant_div_ctl1 = ah->eep_ops->get_eeprom(ah, EEP_ANT_DIV_CTL1);
Sujith Manoharanf85c3372013-08-04 14:21:53 +05302608 if ((ant_div_ctl1 >> 0x6) == 0x3) {
Mohammed Shafi Shajakhan21d2c632011-05-13 20:29:31 +05302609 pCap->hw_caps |= ATH9K_HW_CAP_ANT_DIV_COMB;
Sujith Manoharanf85c3372013-08-04 14:21:53 +05302610 ath_info(common, "Enable LNA combining\n");
2611 }
Mohammed Shafi Shajakhan21d2c632011-05-13 20:29:31 +05302612 }
Vasanthakumar Thiagarajan754dc532010-09-02 01:34:41 -07002613
Zefir Kurtisi9a66af32011-12-14 20:16:33 -08002614 if (ath9k_hw_dfs_tested(ah))
2615 pCap->hw_caps |= ATH9K_HW_CAP_DFS;
2616
Vasanthakumar Thiagarajan47c80de2010-12-06 04:27:43 -08002617 tx_chainmask = pCap->tx_chainmask;
2618 rx_chainmask = pCap->rx_chainmask;
2619 while (tx_chainmask || rx_chainmask) {
2620 if (tx_chainmask & BIT(0))
2621 pCap->max_txchains++;
2622 if (rx_chainmask & BIT(0))
2623 pCap->max_rxchains++;
2624
2625 tx_chainmask >>= 1;
2626 rx_chainmask >>= 1;
2627 }
2628
Sujith Manoharana4a29542012-09-10 09:20:03 +05302629 if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) {
Mohammed Shafi Shajakhan3789d592012-03-09 12:01:55 +05302630 if (!(ah->ent_mode & AR_ENT_OTP_49GHZ_DISABLE))
2631 pCap->hw_caps |= ATH9K_HW_CAP_MCI;
2632
Sujith Manoharan2b5e54e2013-06-24 18:18:46 +05302633 if (AR_SREV_9462_20_OR_LATER(ah))
Mohammed Shafi Shajakhan3789d592012-03-09 12:01:55 +05302634 pCap->hw_caps |= ATH9K_HW_CAP_RTT;
Mohammed Shafi Shajakhan3789d592012-03-09 12:01:55 +05302635 }
2636
Sujith Manoharan0f21ee82012-12-10 07:22:37 +05302637 if (AR_SREV_9300_20_OR_LATER(ah) &&
2638 ah->eep_ops->get_eeprom(ah, EEP_PAPRD))
2639 pCap->hw_caps |= ATH9K_HW_CAP_PAPRD;
2640
Sujith Manoharan12a44422015-01-30 19:05:33 +05302641#ifdef CONFIG_ATH9K_WOW
2642 if (AR_SREV_9462_20_OR_LATER(ah) || AR_SREV_9565_11_OR_LATER(ah))
2643 ah->wow.max_patterns = MAX_NUM_PATTERN;
2644 else
2645 ah->wow.max_patterns = MAX_NUM_PATTERN_LEGACY;
2646#endif
2647
Gabor Juhosa9a29ce2009-11-27 12:01:35 +01002648 return 0;
Luis R. Rodriguez6f255422008-10-03 15:45:27 -07002649}
2650
Sujithf1dc5602008-10-29 10:16:30 +05302651/****************************/
2652/* GPIO / RFKILL / Antennae */
2653/****************************/
2654
Miaoqing Panb2d70d42016-03-07 10:38:15 +08002655static void ath9k_hw_gpio_cfg_output_mux(struct ath_hw *ah, u32 gpio, u32 type)
Sujithf1dc5602008-10-29 10:16:30 +05302656{
2657 int addr;
2658 u32 gpio_shift, tmp;
2659
2660 if (gpio > 11)
2661 addr = AR_GPIO_OUTPUT_MUX3;
2662 else if (gpio > 5)
2663 addr = AR_GPIO_OUTPUT_MUX2;
2664 else
2665 addr = AR_GPIO_OUTPUT_MUX1;
2666
2667 gpio_shift = (gpio % 6) * 5;
2668
Miaoqing Panb2d70d42016-03-07 10:38:15 +08002669 if (AR_SREV_9280_20_OR_LATER(ah) ||
2670 (addr != AR_GPIO_OUTPUT_MUX1)) {
Sujithf1dc5602008-10-29 10:16:30 +05302671 REG_RMW(ah, addr, (type << gpio_shift),
2672 (0x1f << gpio_shift));
2673 } else {
2674 tmp = REG_READ(ah, addr);
2675 tmp = ((tmp & 0x1F0) << 1) | (tmp & ~0x1F0);
2676 tmp &= ~(0x1f << gpio_shift);
2677 tmp |= (type << gpio_shift);
2678 REG_WRITE(ah, addr, tmp);
2679 }
2680}
2681
Miaoqing Panb2d70d42016-03-07 10:38:15 +08002682/* BSP should set the corresponding MUX register correctly.
2683 */
2684static void ath9k_hw_gpio_cfg_soc(struct ath_hw *ah, u32 gpio, bool out,
2685 const char *label)
Sujithf1dc5602008-10-29 10:16:30 +05302686{
Miaoqing Panb2d70d42016-03-07 10:38:15 +08002687 if (ah->caps.gpio_requested & BIT(gpio))
2688 return;
Sujithf1dc5602008-10-29 10:16:30 +05302689
Miaoqing Panb2d70d42016-03-07 10:38:15 +08002690 /* may be requested by BSP, free anyway */
2691 gpio_free(gpio);
2692
2693 if (gpio_request_one(gpio, out ? GPIOF_OUT_INIT_LOW : GPIOF_IN, label))
2694 return;
2695
2696 ah->caps.gpio_requested |= BIT(gpio);
2697}
2698
2699static void ath9k_hw_gpio_cfg_wmac(struct ath_hw *ah, u32 gpio, bool out,
2700 u32 ah_signal_type)
2701{
2702 u32 gpio_set, gpio_shift = gpio;
Sujithf1dc5602008-10-29 10:16:30 +05302703
Sujith88c1f4f2010-06-30 14:46:31 +05302704 if (AR_DEVID_7010(ah)) {
Miaoqing Panb2d70d42016-03-07 10:38:15 +08002705 gpio_set = out ?
2706 AR7010_GPIO_OE_AS_OUTPUT : AR7010_GPIO_OE_AS_INPUT;
2707 REG_RMW(ah, AR7010_GPIO_OE, gpio_set << gpio_shift,
2708 AR7010_GPIO_OE_MASK << gpio_shift);
2709 } else if (AR_SREV_SOC(ah)) {
2710 gpio_set = out ? 1 : 0;
2711 REG_RMW(ah, AR_GPIO_OE_OUT, gpio_set << gpio_shift,
2712 gpio_set << gpio_shift);
2713 } else {
2714 gpio_shift = gpio << 1;
2715 gpio_set = out ?
2716 AR_GPIO_OE_OUT_DRV_ALL : AR_GPIO_OE_OUT_DRV_NO;
2717 REG_RMW(ah, AR_GPIO_OE_OUT, gpio_set << gpio_shift,
2718 AR_GPIO_OE_OUT_DRV << gpio_shift);
Sujithf1dc5602008-10-29 10:16:30 +05302719
Miaoqing Panb2d70d42016-03-07 10:38:15 +08002720 if (out)
2721 ath9k_hw_gpio_cfg_output_mux(ah, gpio, ah_signal_type);
2722 }
Sujithf1dc5602008-10-29 10:16:30 +05302723}
Miaoqing Panb2d70d42016-03-07 10:38:15 +08002724
2725static void ath9k_hw_gpio_request(struct ath_hw *ah, u32 gpio, bool out,
2726 const char *label, u32 ah_signal_type)
2727{
2728 WARN_ON(gpio >= ah->caps.num_gpio_pins);
2729
2730 if (BIT(gpio) & ah->caps.gpio_mask)
2731 ath9k_hw_gpio_cfg_wmac(ah, gpio, out, ah_signal_type);
2732 else if (AR_SREV_SOC(ah))
2733 ath9k_hw_gpio_cfg_soc(ah, gpio, out, label);
2734 else
2735 WARN_ON(1);
2736}
2737
2738void ath9k_hw_gpio_request_in(struct ath_hw *ah, u32 gpio, const char *label)
2739{
2740 ath9k_hw_gpio_request(ah, gpio, false, label, 0);
2741}
2742EXPORT_SYMBOL(ath9k_hw_gpio_request_in);
2743
2744void ath9k_hw_gpio_request_out(struct ath_hw *ah, u32 gpio, const char *label,
2745 u32 ah_signal_type)
2746{
2747 ath9k_hw_gpio_request(ah, gpio, true, label, ah_signal_type);
2748}
2749EXPORT_SYMBOL(ath9k_hw_gpio_request_out);
2750
2751void ath9k_hw_gpio_free(struct ath_hw *ah, u32 gpio)
2752{
2753 if (!AR_SREV_SOC(ah))
2754 return;
2755
2756 WARN_ON(gpio >= ah->caps.num_gpio_pins);
2757
2758 if (ah->caps.gpio_requested & BIT(gpio)) {
2759 gpio_free(gpio);
2760 ah->caps.gpio_requested &= ~BIT(gpio);
2761 }
2762}
2763EXPORT_SYMBOL(ath9k_hw_gpio_free);
Sujithf1dc5602008-10-29 10:16:30 +05302764
Sujithcbe61d82009-02-09 13:27:12 +05302765u32 ath9k_hw_gpio_get(struct ath_hw *ah, u32 gpio)
Sujithf1dc5602008-10-29 10:16:30 +05302766{
Miaoqing Panb2d70d42016-03-07 10:38:15 +08002767 u32 val = 0xffffffff;
2768
Senthil Balasubramaniancb33c412008-12-24 18:03:58 +05302769#define MS_REG_READ(x, y) \
Miaoqing Panb2d70d42016-03-07 10:38:15 +08002770 (MS(REG_READ(ah, AR_GPIO_IN_OUT), x##_GPIO_IN_VAL) & BIT(y))
Senthil Balasubramaniancb33c412008-12-24 18:03:58 +05302771
Miaoqing Panb2d70d42016-03-07 10:38:15 +08002772 WARN_ON(gpio >= ah->caps.num_gpio_pins);
Sujithf1dc5602008-10-29 10:16:30 +05302773
Miaoqing Panb2d70d42016-03-07 10:38:15 +08002774 if (BIT(gpio) & ah->caps.gpio_mask) {
2775 if (AR_SREV_9271(ah))
2776 val = MS_REG_READ(AR9271, gpio);
2777 else if (AR_SREV_9287(ah))
2778 val = MS_REG_READ(AR9287, gpio);
2779 else if (AR_SREV_9285(ah))
2780 val = MS_REG_READ(AR9285, gpio);
2781 else if (AR_SREV_9280(ah))
2782 val = MS_REG_READ(AR928X, gpio);
2783 else if (AR_DEVID_7010(ah))
2784 val = REG_READ(ah, AR7010_GPIO_IN) & BIT(gpio);
2785 else if (AR_SREV_9300_20_OR_LATER(ah))
2786 val = REG_READ(ah, AR_GPIO_IN) & BIT(gpio);
2787 else
2788 val = MS_REG_READ(AR, gpio);
2789 } else if (BIT(gpio) & ah->caps.gpio_requested) {
2790 val = gpio_get_value(gpio) & BIT(gpio);
2791 } else {
2792 WARN_ON(1);
2793 }
2794
2795 return val;
Sujithf1dc5602008-10-29 10:16:30 +05302796}
Luis R. Rodriguez7322fd12009-09-23 23:07:00 -04002797EXPORT_SYMBOL(ath9k_hw_gpio_get);
Sujithf1dc5602008-10-29 10:16:30 +05302798
Sujithcbe61d82009-02-09 13:27:12 +05302799void ath9k_hw_set_gpio(struct ath_hw *ah, u32 gpio, u32 val)
Sujithf1dc5602008-10-29 10:16:30 +05302800{
Miaoqing Panb2d70d42016-03-07 10:38:15 +08002801 WARN_ON(gpio >= ah->caps.num_gpio_pins);
Sujith88c1f4f2010-06-30 14:46:31 +05302802
Miaoqing Panb2d70d42016-03-07 10:38:15 +08002803 if (AR_DEVID_7010(ah) || AR_SREV_9271(ah))
2804 val = !val;
Miaoqing Pan61b559d2015-04-01 10:19:57 +08002805 else
Miaoqing Panb2d70d42016-03-07 10:38:15 +08002806 val = !!val;
2807
2808 if (BIT(gpio) & ah->caps.gpio_mask) {
2809 u32 out_addr = AR_DEVID_7010(ah) ?
2810 AR7010_GPIO_OUT : AR_GPIO_IN_OUT;
2811
2812 REG_RMW(ah, out_addr, val << gpio, BIT(gpio));
2813 } else if (BIT(gpio) & ah->caps.gpio_requested) {
2814 gpio_set_value(gpio, val);
2815 } else {
2816 WARN_ON(1);
2817 }
Sujithf1dc5602008-10-29 10:16:30 +05302818}
Luis R. Rodriguez7322fd12009-09-23 23:07:00 -04002819EXPORT_SYMBOL(ath9k_hw_set_gpio);
Sujithf1dc5602008-10-29 10:16:30 +05302820
Sujithcbe61d82009-02-09 13:27:12 +05302821void ath9k_hw_setantenna(struct ath_hw *ah, u32 antenna)
Sujithf1dc5602008-10-29 10:16:30 +05302822{
2823 REG_WRITE(ah, AR_DEF_ANTENNA, (antenna & 0x7));
2824}
Luis R. Rodriguez7322fd12009-09-23 23:07:00 -04002825EXPORT_SYMBOL(ath9k_hw_setantenna);
Sujithf1dc5602008-10-29 10:16:30 +05302826
Sujithf1dc5602008-10-29 10:16:30 +05302827/*********************/
2828/* General Operation */
2829/*********************/
2830
Sujithcbe61d82009-02-09 13:27:12 +05302831u32 ath9k_hw_getrxfilter(struct ath_hw *ah)
Sujithf1dc5602008-10-29 10:16:30 +05302832{
2833 u32 bits = REG_READ(ah, AR_RX_FILTER);
2834 u32 phybits = REG_READ(ah, AR_PHY_ERR);
2835
2836 if (phybits & AR_PHY_ERR_RADAR)
2837 bits |= ATH9K_RX_FILTER_PHYRADAR;
2838 if (phybits & (AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING))
2839 bits |= ATH9K_RX_FILTER_PHYERR;
2840
2841 return bits;
2842}
Luis R. Rodriguez7322fd12009-09-23 23:07:00 -04002843EXPORT_SYMBOL(ath9k_hw_getrxfilter);
Sujithf1dc5602008-10-29 10:16:30 +05302844
Sujithcbe61d82009-02-09 13:27:12 +05302845void ath9k_hw_setrxfilter(struct ath_hw *ah, u32 bits)
Sujithf1dc5602008-10-29 10:16:30 +05302846{
2847 u32 phybits;
2848
Sujith7d0d0df2010-04-16 11:53:57 +05302849 ENABLE_REGWRITE_BUFFER(ah);
2850
Sujith7ea310b2009-09-03 12:08:43 +05302851 REG_WRITE(ah, AR_RX_FILTER, bits);
2852
Sujithf1dc5602008-10-29 10:16:30 +05302853 phybits = 0;
2854 if (bits & ATH9K_RX_FILTER_PHYRADAR)
2855 phybits |= AR_PHY_ERR_RADAR;
2856 if (bits & ATH9K_RX_FILTER_PHYERR)
2857 phybits |= AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING;
2858 REG_WRITE(ah, AR_PHY_ERR, phybits);
2859
2860 if (phybits)
Felix Fietkauca7a4de2011-03-23 20:57:26 +01002861 REG_SET_BIT(ah, AR_RXCFG, AR_RXCFG_ZLFDMA);
Sujithf1dc5602008-10-29 10:16:30 +05302862 else
Felix Fietkauca7a4de2011-03-23 20:57:26 +01002863 REG_CLR_BIT(ah, AR_RXCFG, AR_RXCFG_ZLFDMA);
Sujith7d0d0df2010-04-16 11:53:57 +05302864
2865 REGWRITE_BUFFER_FLUSH(ah);
Sujithf1dc5602008-10-29 10:16:30 +05302866}
Luis R. Rodriguez7322fd12009-09-23 23:07:00 -04002867EXPORT_SYMBOL(ath9k_hw_setrxfilter);
Sujithf1dc5602008-10-29 10:16:30 +05302868
Sujithcbe61d82009-02-09 13:27:12 +05302869bool ath9k_hw_phy_disable(struct ath_hw *ah)
Sujithf1dc5602008-10-29 10:16:30 +05302870{
Rajkumar Manoharan99922a42012-06-04 16:28:31 +05302871 if (ath9k_hw_mci_is_enabled(ah))
2872 ar9003_mci_bt_gain_ctrl(ah);
2873
Senthil Balasubramanian63a75b92009-09-18 15:07:03 +05302874 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM))
2875 return false;
2876
2877 ath9k_hw_init_pll(ah, NULL);
Felix Fietkau8efa7a82012-03-14 16:40:23 +01002878 ah->htc_reset_init = true;
Senthil Balasubramanian63a75b92009-09-18 15:07:03 +05302879 return true;
Sujithf1dc5602008-10-29 10:16:30 +05302880}
Luis R. Rodriguez7322fd12009-09-23 23:07:00 -04002881EXPORT_SYMBOL(ath9k_hw_phy_disable);
Sujithf1dc5602008-10-29 10:16:30 +05302882
Sujithcbe61d82009-02-09 13:27:12 +05302883bool ath9k_hw_disable(struct ath_hw *ah)
Sujithf1dc5602008-10-29 10:16:30 +05302884{
Luis R. Rodriguez9ecdef42009-09-09 21:10:09 -07002885 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
Sujithf1dc5602008-10-29 10:16:30 +05302886 return false;
2887
Senthil Balasubramanian63a75b92009-09-18 15:07:03 +05302888 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_COLD))
2889 return false;
2890
2891 ath9k_hw_init_pll(ah, NULL);
2892 return true;
Sujithf1dc5602008-10-29 10:16:30 +05302893}
Luis R. Rodriguez7322fd12009-09-23 23:07:00 -04002894EXPORT_SYMBOL(ath9k_hw_disable);
Sujithf1dc5602008-10-29 10:16:30 +05302895
Felix Fietkauca2c68c2011-10-08 20:06:20 +02002896static int get_antenna_gain(struct ath_hw *ah, struct ath9k_channel *chan)
Sujithf1dc5602008-10-29 10:16:30 +05302897{
Felix Fietkauca2c68c2011-10-08 20:06:20 +02002898 enum eeprom_param gain_param;
Felix Fietkau9c204b42011-07-27 15:01:05 +02002899
Felix Fietkauca2c68c2011-10-08 20:06:20 +02002900 if (IS_CHAN_2GHZ(chan))
2901 gain_param = EEP_ANTENNA_GAIN_2G;
2902 else
2903 gain_param = EEP_ANTENNA_GAIN_5G;
Sujithf1dc5602008-10-29 10:16:30 +05302904
Felix Fietkauca2c68c2011-10-08 20:06:20 +02002905 return ah->eep_ops->get_eeprom(ah, gain_param);
2906}
2907
Gabor Juhos64ea57d2012-04-15 20:38:05 +02002908void ath9k_hw_apply_txpower(struct ath_hw *ah, struct ath9k_channel *chan,
2909 bool test)
Felix Fietkauca2c68c2011-10-08 20:06:20 +02002910{
2911 struct ath_regulatory *reg = ath9k_hw_regulatory(ah);
2912 struct ieee80211_channel *channel;
Zefir Kurtisi71f51372016-04-01 11:37:08 +02002913 int chan_pwr, new_pwr;
Felix Fietkauca2c68c2011-10-08 20:06:20 +02002914
2915 if (!chan)
2916 return;
2917
2918 channel = chan->chan;
2919 chan_pwr = min_t(int, channel->max_power * 2, MAX_RATE_POWER);
2920 new_pwr = min_t(int, chan_pwr, reg->power_limit);
Sujithf1dc5602008-10-29 10:16:30 +05302921
Vasanthakumar Thiagarajan8fbff4b2009-05-08 17:54:51 -07002922 ah->eep_ops->set_txpower(ah, chan,
Felix Fietkauca2c68c2011-10-08 20:06:20 +02002923 ath9k_regd_get_ctl(reg, chan),
Zefir Kurtisi71f51372016-04-01 11:37:08 +02002924 get_antenna_gain(ah, chan), new_pwr, test);
Felix Fietkauca2c68c2011-10-08 20:06:20 +02002925}
2926
2927void ath9k_hw_set_txpowerlimit(struct ath_hw *ah, u32 limit, bool test)
2928{
2929 struct ath_regulatory *reg = ath9k_hw_regulatory(ah);
2930 struct ath9k_channel *chan = ah->curchan;
2931 struct ieee80211_channel *channel = chan->chan;
2932
Dan Carpenter48ef5c42011-10-17 10:28:23 +03002933 reg->power_limit = min_t(u32, limit, MAX_RATE_POWER);
Felix Fietkauca2c68c2011-10-08 20:06:20 +02002934 if (test)
2935 channel->max_power = MAX_RATE_POWER / 2;
2936
Gabor Juhos64ea57d2012-04-15 20:38:05 +02002937 ath9k_hw_apply_txpower(ah, chan, test);
Felix Fietkauca2c68c2011-10-08 20:06:20 +02002938
2939 if (test)
2940 channel->max_power = DIV_ROUND_UP(reg->max_power_level, 2);
Sujithf1dc5602008-10-29 10:16:30 +05302941}
Luis R. Rodriguez7322fd12009-09-23 23:07:00 -04002942EXPORT_SYMBOL(ath9k_hw_set_txpowerlimit);
Sujithf1dc5602008-10-29 10:16:30 +05302943
Sujithcbe61d82009-02-09 13:27:12 +05302944void ath9k_hw_setopmode(struct ath_hw *ah)
Sujithf1dc5602008-10-29 10:16:30 +05302945{
Sujith2660b812009-02-09 13:27:26 +05302946 ath9k_hw_set_operating_mode(ah, ah->opmode);
Sujithf1dc5602008-10-29 10:16:30 +05302947}
Luis R. Rodriguez7322fd12009-09-23 23:07:00 -04002948EXPORT_SYMBOL(ath9k_hw_setopmode);
Sujithf1dc5602008-10-29 10:16:30 +05302949
Sujithcbe61d82009-02-09 13:27:12 +05302950void ath9k_hw_setmcastfilter(struct ath_hw *ah, u32 filter0, u32 filter1)
Sujithf1dc5602008-10-29 10:16:30 +05302951{
2952 REG_WRITE(ah, AR_MCAST_FIL0, filter0);
2953 REG_WRITE(ah, AR_MCAST_FIL1, filter1);
2954}
Luis R. Rodriguez7322fd12009-09-23 23:07:00 -04002955EXPORT_SYMBOL(ath9k_hw_setmcastfilter);
Sujithf1dc5602008-10-29 10:16:30 +05302956
Luis R. Rodriguezf2b21432009-09-10 08:50:20 -07002957void ath9k_hw_write_associd(struct ath_hw *ah)
Sujithf1dc5602008-10-29 10:16:30 +05302958{
Luis R. Rodriguez15107182009-09-10 09:22:37 -07002959 struct ath_common *common = ath9k_hw_common(ah);
2960
2961 REG_WRITE(ah, AR_BSS_ID0, get_unaligned_le32(common->curbssid));
2962 REG_WRITE(ah, AR_BSS_ID1, get_unaligned_le16(common->curbssid + 4) |
2963 ((common->curaid & 0x3fff) << AR_BSS_ID1_AID_S));
Sujithf1dc5602008-10-29 10:16:30 +05302964}
Luis R. Rodriguez7322fd12009-09-23 23:07:00 -04002965EXPORT_SYMBOL(ath9k_hw_write_associd);
Sujithf1dc5602008-10-29 10:16:30 +05302966
Benoit Papillault1c0fc652010-04-16 00:07:26 +02002967#define ATH9K_MAX_TSF_READ 10
2968
Sujithcbe61d82009-02-09 13:27:12 +05302969u64 ath9k_hw_gettsf64(struct ath_hw *ah)
Sujithf1dc5602008-10-29 10:16:30 +05302970{
Benoit Papillault1c0fc652010-04-16 00:07:26 +02002971 u32 tsf_lower, tsf_upper1, tsf_upper2;
2972 int i;
Sujithf1dc5602008-10-29 10:16:30 +05302973
Benoit Papillault1c0fc652010-04-16 00:07:26 +02002974 tsf_upper1 = REG_READ(ah, AR_TSF_U32);
2975 for (i = 0; i < ATH9K_MAX_TSF_READ; i++) {
2976 tsf_lower = REG_READ(ah, AR_TSF_L32);
2977 tsf_upper2 = REG_READ(ah, AR_TSF_U32);
2978 if (tsf_upper2 == tsf_upper1)
2979 break;
2980 tsf_upper1 = tsf_upper2;
2981 }
Sujithf1dc5602008-10-29 10:16:30 +05302982
Benoit Papillault1c0fc652010-04-16 00:07:26 +02002983 WARN_ON( i == ATH9K_MAX_TSF_READ );
2984
2985 return (((u64)tsf_upper1 << 32) | tsf_lower);
Sujithf1dc5602008-10-29 10:16:30 +05302986}
Luis R. Rodriguez7322fd12009-09-23 23:07:00 -04002987EXPORT_SYMBOL(ath9k_hw_gettsf64);
Sujithf1dc5602008-10-29 10:16:30 +05302988
Sujithcbe61d82009-02-09 13:27:12 +05302989void ath9k_hw_settsf64(struct ath_hw *ah, u64 tsf64)
Alina Friedrichsen27abe062009-01-23 05:44:21 +01002990{
Alina Friedrichsen27abe062009-01-23 05:44:21 +01002991 REG_WRITE(ah, AR_TSF_L32, tsf64 & 0xffffffff);
Alina Friedrichsenb9a16192009-03-02 23:28:38 +01002992 REG_WRITE(ah, AR_TSF_U32, (tsf64 >> 32) & 0xffffffff);
Alina Friedrichsen27abe062009-01-23 05:44:21 +01002993}
Luis R. Rodriguez7322fd12009-09-23 23:07:00 -04002994EXPORT_SYMBOL(ath9k_hw_settsf64);
Alina Friedrichsen27abe062009-01-23 05:44:21 +01002995
Sujithcbe61d82009-02-09 13:27:12 +05302996void ath9k_hw_reset_tsf(struct ath_hw *ah)
Sujithf1dc5602008-10-29 10:16:30 +05302997{
Gabor Juhosf9b604f2009-06-21 00:02:15 +02002998 if (!ath9k_hw_wait(ah, AR_SLP32_MODE, AR_SLP32_TSF_WRITE_STATUS, 0,
2999 AH_TSF_WRITE_TIMEOUT))
Joe Perchesd2182b62011-12-15 14:55:53 -08003000 ath_dbg(ath9k_hw_common(ah), RESET,
Joe Perches226afe62010-12-02 19:12:37 -08003001 "AR_SLP32_TSF_WRITE_STATUS limit exceeded\n");
Gabor Juhosf9b604f2009-06-21 00:02:15 +02003002
Sujithf1dc5602008-10-29 10:16:30 +05303003 REG_WRITE(ah, AR_RESET_TSF, AR_RESET_TSF_ONCE);
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07003004}
Luis R. Rodriguez7322fd12009-09-23 23:07:00 -04003005EXPORT_SYMBOL(ath9k_hw_reset_tsf);
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07003006
Sujith Manoharan60ca9f82012-07-17 17:15:37 +05303007void ath9k_hw_set_tsfadjust(struct ath_hw *ah, bool set)
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07003008{
Sujith Manoharan60ca9f82012-07-17 17:15:37 +05303009 if (set)
Sujith2660b812009-02-09 13:27:26 +05303010 ah->misc_mode |= AR_PCU_TX_ADD_TSF;
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07003011 else
Sujith2660b812009-02-09 13:27:26 +05303012 ah->misc_mode &= ~AR_PCU_TX_ADD_TSF;
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07003013}
Luis R. Rodriguez7322fd12009-09-23 23:07:00 -04003014EXPORT_SYMBOL(ath9k_hw_set_tsfadjust);
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07003015
Felix Fietkaue4744ec2013-10-11 23:31:01 +02003016void ath9k_hw_set11nmac2040(struct ath_hw *ah, struct ath9k_channel *chan)
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07003017{
Sujithf1dc5602008-10-29 10:16:30 +05303018 u32 macmode;
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07003019
Felix Fietkaue4744ec2013-10-11 23:31:01 +02003020 if (IS_CHAN_HT40(chan) && !ah->config.cwm_ignore_extcca)
Sujithf1dc5602008-10-29 10:16:30 +05303021 macmode = AR_2040_JOINED_RX_CLEAR;
3022 else
3023 macmode = 0;
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07003024
Sujithf1dc5602008-10-29 10:16:30 +05303025 REG_WRITE(ah, AR_2040_MODE, macmode);
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07003026}
Vasanthakumar Thiagarajanff155a42009-08-26 21:08:49 +05303027
3028/* HW Generic timers configuration */
3029
3030static const struct ath_gen_timer_configuration gen_tmr_configuration[] =
3031{
3032 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
3033 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
3034 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
3035 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
3036 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
3037 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
3038 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
3039 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
3040 {AR_NEXT_NDP2_TIMER, AR_NDP2_PERIOD, AR_NDP2_TIMER_MODE, 0x0001},
3041 {AR_NEXT_NDP2_TIMER + 1*4, AR_NDP2_PERIOD + 1*4,
3042 AR_NDP2_TIMER_MODE, 0x0002},
3043 {AR_NEXT_NDP2_TIMER + 2*4, AR_NDP2_PERIOD + 2*4,
3044 AR_NDP2_TIMER_MODE, 0x0004},
3045 {AR_NEXT_NDP2_TIMER + 3*4, AR_NDP2_PERIOD + 3*4,
3046 AR_NDP2_TIMER_MODE, 0x0008},
3047 {AR_NEXT_NDP2_TIMER + 4*4, AR_NDP2_PERIOD + 4*4,
3048 AR_NDP2_TIMER_MODE, 0x0010},
3049 {AR_NEXT_NDP2_TIMER + 5*4, AR_NDP2_PERIOD + 5*4,
3050 AR_NDP2_TIMER_MODE, 0x0020},
3051 {AR_NEXT_NDP2_TIMER + 6*4, AR_NDP2_PERIOD + 6*4,
3052 AR_NDP2_TIMER_MODE, 0x0040},
3053 {AR_NEXT_NDP2_TIMER + 7*4, AR_NDP2_PERIOD + 7*4,
3054 AR_NDP2_TIMER_MODE, 0x0080}
3055};
3056
3057/* HW generic timer primitives */
3058
Felix Fietkaudd347f22011-03-22 21:54:17 +01003059u32 ath9k_hw_gettsf32(struct ath_hw *ah)
Vasanthakumar Thiagarajanff155a42009-08-26 21:08:49 +05303060{
3061 return REG_READ(ah, AR_TSF_L32);
3062}
Felix Fietkaudd347f22011-03-22 21:54:17 +01003063EXPORT_SYMBOL(ath9k_hw_gettsf32);
Vasanthakumar Thiagarajanff155a42009-08-26 21:08:49 +05303064
Sujith Manoharanf4c34af2014-11-16 06:11:03 +05303065void ath9k_hw_gen_timer_start_tsf2(struct ath_hw *ah)
3066{
3067 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
3068
3069 if (timer_table->tsf2_enabled) {
3070 REG_SET_BIT(ah, AR_DIRECT_CONNECT, AR_DC_AP_STA_EN);
3071 REG_SET_BIT(ah, AR_RESET_TSF, AR_RESET_TSF2_ONCE);
3072 }
3073}
3074
Vasanthakumar Thiagarajanff155a42009-08-26 21:08:49 +05303075struct ath_gen_timer *ath_gen_timer_alloc(struct ath_hw *ah,
3076 void (*trigger)(void *),
3077 void (*overflow)(void *),
3078 void *arg,
3079 u8 timer_index)
3080{
3081 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
3082 struct ath_gen_timer *timer;
3083
Felix Fietkauc67ce332013-12-14 18:03:38 +01003084 if ((timer_index < AR_FIRST_NDP_TIMER) ||
Sujith Manoharanf4c34af2014-11-16 06:11:03 +05303085 (timer_index >= ATH_MAX_GEN_TIMER))
3086 return NULL;
3087
3088 if ((timer_index > AR_FIRST_NDP_TIMER) &&
3089 !AR_SREV_9300_20_OR_LATER(ah))
Felix Fietkauc67ce332013-12-14 18:03:38 +01003090 return NULL;
3091
Vasanthakumar Thiagarajanff155a42009-08-26 21:08:49 +05303092 timer = kzalloc(sizeof(struct ath_gen_timer), GFP_KERNEL);
Joe Perches14f8dc42013-02-07 11:46:27 +00003093 if (timer == NULL)
Vasanthakumar Thiagarajanff155a42009-08-26 21:08:49 +05303094 return NULL;
Vasanthakumar Thiagarajanff155a42009-08-26 21:08:49 +05303095
3096 /* allocate a hardware generic timer slot */
3097 timer_table->timers[timer_index] = timer;
3098 timer->index = timer_index;
3099 timer->trigger = trigger;
3100 timer->overflow = overflow;
3101 timer->arg = arg;
3102
Sujith Manoharanf4c34af2014-11-16 06:11:03 +05303103 if ((timer_index > AR_FIRST_NDP_TIMER) && !timer_table->tsf2_enabled) {
3104 timer_table->tsf2_enabled = true;
3105 ath9k_hw_gen_timer_start_tsf2(ah);
3106 }
3107
Vasanthakumar Thiagarajanff155a42009-08-26 21:08:49 +05303108 return timer;
3109}
Luis R. Rodriguez7322fd12009-09-23 23:07:00 -04003110EXPORT_SYMBOL(ath_gen_timer_alloc);
Vasanthakumar Thiagarajanff155a42009-08-26 21:08:49 +05303111
Luis R. Rodriguezcd9bf682009-09-13 02:08:34 -07003112void ath9k_hw_gen_timer_start(struct ath_hw *ah,
3113 struct ath_gen_timer *timer,
Felix Fietkauc67ce332013-12-14 18:03:38 +01003114 u32 timer_next,
Luis R. Rodriguezcd9bf682009-09-13 02:08:34 -07003115 u32 timer_period)
Vasanthakumar Thiagarajanff155a42009-08-26 21:08:49 +05303116{
3117 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
Felix Fietkauc67ce332013-12-14 18:03:38 +01003118 u32 mask = 0;
Vasanthakumar Thiagarajanff155a42009-08-26 21:08:49 +05303119
Felix Fietkauc67ce332013-12-14 18:03:38 +01003120 timer_table->timer_mask |= BIT(timer->index);
Vasanthakumar Thiagarajanff155a42009-08-26 21:08:49 +05303121
3122 /*
Vasanthakumar Thiagarajanff155a42009-08-26 21:08:49 +05303123 * Program generic timer registers
3124 */
3125 REG_WRITE(ah, gen_tmr_configuration[timer->index].next_addr,
3126 timer_next);
3127 REG_WRITE(ah, gen_tmr_configuration[timer->index].period_addr,
3128 timer_period);
3129 REG_SET_BIT(ah, gen_tmr_configuration[timer->index].mode_addr,
3130 gen_tmr_configuration[timer->index].mode_mask);
3131
Sujith Manoharana4a29542012-09-10 09:20:03 +05303132 if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) {
Senthil Balasubramanian2577c6e2011-09-13 22:38:18 +05303133 /*
Rajkumar Manoharan423e38e2011-10-13 11:00:44 +05303134 * Starting from AR9462, each generic timer can select which tsf
Senthil Balasubramanian2577c6e2011-09-13 22:38:18 +05303135 * to use. But we still follow the old rule, 0 - 7 use tsf and
3136 * 8 - 15 use tsf2.
3137 */
3138 if ((timer->index < AR_GEN_TIMER_BANK_1_LEN))
3139 REG_CLR_BIT(ah, AR_MAC_PCU_GEN_TIMER_TSF_SEL,
3140 (1 << timer->index));
3141 else
3142 REG_SET_BIT(ah, AR_MAC_PCU_GEN_TIMER_TSF_SEL,
3143 (1 << timer->index));
3144 }
3145
Felix Fietkauc67ce332013-12-14 18:03:38 +01003146 if (timer->trigger)
3147 mask |= SM(AR_GENTMR_BIT(timer->index),
3148 AR_IMR_S5_GENTIMER_TRIG);
3149 if (timer->overflow)
3150 mask |= SM(AR_GENTMR_BIT(timer->index),
3151 AR_IMR_S5_GENTIMER_THRESH);
3152
3153 REG_SET_BIT(ah, AR_IMR_S5, mask);
3154
3155 if ((ah->imask & ATH9K_INT_GENTIMER) == 0) {
3156 ah->imask |= ATH9K_INT_GENTIMER;
3157 ath9k_hw_set_interrupts(ah);
3158 }
Vasanthakumar Thiagarajanff155a42009-08-26 21:08:49 +05303159}
Luis R. Rodriguez7322fd12009-09-23 23:07:00 -04003160EXPORT_SYMBOL(ath9k_hw_gen_timer_start);
Vasanthakumar Thiagarajanff155a42009-08-26 21:08:49 +05303161
Luis R. Rodriguezcd9bf682009-09-13 02:08:34 -07003162void ath9k_hw_gen_timer_stop(struct ath_hw *ah, struct ath_gen_timer *timer)
Vasanthakumar Thiagarajanff155a42009-08-26 21:08:49 +05303163{
3164 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
3165
Vasanthakumar Thiagarajanff155a42009-08-26 21:08:49 +05303166 /* Clear generic timer enable bits. */
3167 REG_CLR_BIT(ah, gen_tmr_configuration[timer->index].mode_addr,
3168 gen_tmr_configuration[timer->index].mode_mask);
3169
Sujith Manoharanb7f59762012-09-11 10:46:24 +05303170 if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) {
3171 /*
3172 * Need to switch back to TSF if it was using TSF2.
3173 */
3174 if ((timer->index >= AR_GEN_TIMER_BANK_1_LEN)) {
3175 REG_CLR_BIT(ah, AR_MAC_PCU_GEN_TIMER_TSF_SEL,
3176 (1 << timer->index));
3177 }
3178 }
3179
Vasanthakumar Thiagarajanff155a42009-08-26 21:08:49 +05303180 /* Disable both trigger and thresh interrupt masks */
3181 REG_CLR_BIT(ah, AR_IMR_S5,
3182 (SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_THRESH) |
3183 SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_TRIG)));
3184
Felix Fietkauc67ce332013-12-14 18:03:38 +01003185 timer_table->timer_mask &= ~BIT(timer->index);
3186
3187 if (timer_table->timer_mask == 0) {
3188 ah->imask &= ~ATH9K_INT_GENTIMER;
3189 ath9k_hw_set_interrupts(ah);
3190 }
Vasanthakumar Thiagarajanff155a42009-08-26 21:08:49 +05303191}
Luis R. Rodriguez7322fd12009-09-23 23:07:00 -04003192EXPORT_SYMBOL(ath9k_hw_gen_timer_stop);
Vasanthakumar Thiagarajanff155a42009-08-26 21:08:49 +05303193
3194void ath_gen_timer_free(struct ath_hw *ah, struct ath_gen_timer *timer)
3195{
3196 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
3197
3198 /* free the hardware generic timer slot */
3199 timer_table->timers[timer->index] = NULL;
3200 kfree(timer);
3201}
Luis R. Rodriguez7322fd12009-09-23 23:07:00 -04003202EXPORT_SYMBOL(ath_gen_timer_free);
Vasanthakumar Thiagarajanff155a42009-08-26 21:08:49 +05303203
3204/*
3205 * Generic Timer Interrupts handling
3206 */
3207void ath_gen_timer_isr(struct ath_hw *ah)
3208{
3209 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
3210 struct ath_gen_timer *timer;
Felix Fietkauc67ce332013-12-14 18:03:38 +01003211 unsigned long trigger_mask, thresh_mask;
3212 unsigned int index;
Vasanthakumar Thiagarajanff155a42009-08-26 21:08:49 +05303213
3214 /* get hardware generic timer interrupt status */
3215 trigger_mask = ah->intr_gen_timer_trigger;
3216 thresh_mask = ah->intr_gen_timer_thresh;
Felix Fietkauc67ce332013-12-14 18:03:38 +01003217 trigger_mask &= timer_table->timer_mask;
3218 thresh_mask &= timer_table->timer_mask;
Vasanthakumar Thiagarajanff155a42009-08-26 21:08:49 +05303219
Felix Fietkauc67ce332013-12-14 18:03:38 +01003220 for_each_set_bit(index, &thresh_mask, ARRAY_SIZE(timer_table->timers)) {
Vasanthakumar Thiagarajanff155a42009-08-26 21:08:49 +05303221 timer = timer_table->timers[index];
Felix Fietkauc67ce332013-12-14 18:03:38 +01003222 if (!timer)
3223 continue;
3224 if (!timer->overflow)
3225 continue;
Felix Fietkaua6a172b2013-12-20 16:18:45 +01003226
3227 trigger_mask &= ~BIT(index);
Vasanthakumar Thiagarajanff155a42009-08-26 21:08:49 +05303228 timer->overflow(timer->arg);
3229 }
3230
Felix Fietkauc67ce332013-12-14 18:03:38 +01003231 for_each_set_bit(index, &trigger_mask, ARRAY_SIZE(timer_table->timers)) {
Vasanthakumar Thiagarajanff155a42009-08-26 21:08:49 +05303232 timer = timer_table->timers[index];
Felix Fietkauc67ce332013-12-14 18:03:38 +01003233 if (!timer)
3234 continue;
3235 if (!timer->trigger)
3236 continue;
Vasanthakumar Thiagarajanff155a42009-08-26 21:08:49 +05303237 timer->trigger(timer->arg);
3238 }
3239}
Luis R. Rodriguez7322fd12009-09-23 23:07:00 -04003240EXPORT_SYMBOL(ath_gen_timer_isr);
Luis R. Rodriguez2da4f012009-10-27 12:59:33 -04003241
Sujith05020d22010-03-17 14:25:23 +05303242/********/
3243/* HTC */
3244/********/
3245
Luis R. Rodriguez2da4f012009-10-27 12:59:33 -04003246static struct {
3247 u32 version;
3248 const char * name;
3249} ath_mac_bb_names[] = {
3250 /* Devices with external radios */
3251 { AR_SREV_VERSION_5416_PCI, "5416" },
3252 { AR_SREV_VERSION_5416_PCIE, "5418" },
3253 { AR_SREV_VERSION_9100, "9100" },
3254 { AR_SREV_VERSION_9160, "9160" },
3255 /* Single-chip solutions */
3256 { AR_SREV_VERSION_9280, "9280" },
3257 { AR_SREV_VERSION_9285, "9285" },
Luis R. Rodriguez11158472009-10-27 12:59:35 -04003258 { AR_SREV_VERSION_9287, "9287" },
3259 { AR_SREV_VERSION_9271, "9271" },
Luis R. Rodriguezec839032010-04-15 17:39:20 -04003260 { AR_SREV_VERSION_9300, "9300" },
Gabor Juhos2c8e5932011-06-21 11:23:21 +02003261 { AR_SREV_VERSION_9330, "9330" },
Florian Fainelli397e5d52011-08-25 21:33:48 +02003262 { AR_SREV_VERSION_9340, "9340" },
Senthil Balasubramanian8f06ca22011-04-01 17:16:33 +05303263 { AR_SREV_VERSION_9485, "9485" },
Rajkumar Manoharan423e38e2011-10-13 11:00:44 +05303264 { AR_SREV_VERSION_9462, "9462" },
Gabor Juhos485124c2012-07-03 19:13:19 +02003265 { AR_SREV_VERSION_9550, "9550" },
Sujith Manoharan77fac462012-09-11 20:09:18 +05303266 { AR_SREV_VERSION_9565, "9565" },
Sujith Manoharanc08148b2014-03-17 15:02:46 +05303267 { AR_SREV_VERSION_9531, "9531" },
Miaoqing Pan1165dd92015-08-12 14:20:46 +08003268 { AR_SREV_VERSION_9561, "9561" },
Luis R. Rodriguez2da4f012009-10-27 12:59:33 -04003269};
3270
3271/* For devices with external radios */
3272static struct {
3273 u16 version;
3274 const char * name;
3275} ath_rf_names[] = {
3276 { 0, "5133" },
3277 { AR_RAD5133_SREV_MAJOR, "5133" },
3278 { AR_RAD5122_SREV_MAJOR, "5122" },
3279 { AR_RAD2133_SREV_MAJOR, "2133" },
3280 { AR_RAD2122_SREV_MAJOR, "2122" }
3281};
3282
3283/*
3284 * Return the MAC/BB name. "????" is returned if the MAC/BB is unknown.
3285 */
Luis R. Rodriguezf934c4d2009-10-27 12:59:34 -04003286static const char *ath9k_hw_mac_bb_name(u32 mac_bb_version)
Luis R. Rodriguez2da4f012009-10-27 12:59:33 -04003287{
3288 int i;
3289
3290 for (i=0; i<ARRAY_SIZE(ath_mac_bb_names); i++) {
3291 if (ath_mac_bb_names[i].version == mac_bb_version) {
3292 return ath_mac_bb_names[i].name;
3293 }
3294 }
3295
3296 return "????";
3297}
Luis R. Rodriguez2da4f012009-10-27 12:59:33 -04003298
3299/*
3300 * Return the RF name. "????" is returned if the RF is unknown.
3301 * Used for devices with external radios.
3302 */
Luis R. Rodriguezf934c4d2009-10-27 12:59:34 -04003303static const char *ath9k_hw_rf_name(u16 rf_version)
Luis R. Rodriguez2da4f012009-10-27 12:59:33 -04003304{
3305 int i;
3306
3307 for (i=0; i<ARRAY_SIZE(ath_rf_names); i++) {
3308 if (ath_rf_names[i].version == rf_version) {
3309 return ath_rf_names[i].name;
3310 }
3311 }
3312
3313 return "????";
3314}
Luis R. Rodriguezf934c4d2009-10-27 12:59:34 -04003315
3316void ath9k_hw_name(struct ath_hw *ah, char *hw_name, size_t len)
3317{
3318 int used;
3319
3320 /* chipsets >= AR9280 are single-chip */
Felix Fietkau7a370812010-09-22 12:34:52 +02003321 if (AR_SREV_9280_20_OR_LATER(ah)) {
Zefir Kurtisi5e88ba62013-09-05 14:11:57 +02003322 used = scnprintf(hw_name, len,
3323 "Atheros AR%s Rev:%x",
3324 ath9k_hw_mac_bb_name(ah->hw_version.macVersion),
3325 ah->hw_version.macRev);
Luis R. Rodriguezf934c4d2009-10-27 12:59:34 -04003326 }
3327 else {
Zefir Kurtisi5e88ba62013-09-05 14:11:57 +02003328 used = scnprintf(hw_name, len,
3329 "Atheros AR%s MAC/BB Rev:%x AR%s RF Rev:%x",
3330 ath9k_hw_mac_bb_name(ah->hw_version.macVersion),
3331 ah->hw_version.macRev,
3332 ath9k_hw_rf_name((ah->hw_version.analog5GhzRev
3333 & AR_RADIO_SREV_MAJOR)),
3334 ah->hw_version.phyRev);
Luis R. Rodriguezf934c4d2009-10-27 12:59:34 -04003335 }
3336
3337 hw_name[used] = '\0';
3338}
3339EXPORT_SYMBOL(ath9k_hw_name);