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Banajit Goswamib016de92017-02-15 21:02:30 -08001/* Copyright (c) 2016-2017, The Linux Foundation. All rights reserved.
Kyle Yan679cbee2016-07-27 16:55:20 -07002 *
3 * This program is free software; you can redistribute it and/or modify
4 * it under the terms of the GNU General Public License version 2 and
5 * only version 2 as published by the Free Software Foundation.
6 *
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
11 */
12
13&soc {
Channagoud Kadabieb7f0112017-04-03 20:39:27 -070014 tlmm: pinctrl@03400000 {
Kyle Yan6a20fae2017-02-14 13:34:41 -080015 compatible = "qcom,sdm845-pinctrl";
Channagoud Kadabieb7f0112017-04-03 20:39:27 -070016 reg = <0x03400000 0xc00000>;
Kyle Yan679cbee2016-07-27 16:55:20 -070017 interrupts = <0 208 0>;
18 gpio-controller;
19 #gpio-cells = <2>;
20 interrupt-controller;
21 #interrupt-cells = <2>;
Archana Sathyakumar00a36ab2017-03-03 14:38:26 -070022 interrupt-parent = <&pdc>;
Banajit Goswamib016de92017-02-15 21:02:30 -080023
Subhash Jadavaniafe2a792017-03-31 21:08:29 -070024 ufs_dev_reset_assert: ufs_dev_reset_assert {
25 config {
26 pins = "ufs_reset";
27 bias-pull-down; /* default: pull down */
28 /*
29 * UFS_RESET driver strengths are having
30 * different values/steps compared to typical
31 * GPIO drive strengths.
32 *
33 * Following table clarifies:
34 *
35 * HDRV value | UFS_RESET | Typical GPIO
36 * (dec) | (mA) | (mA)
37 * 0 | 0.8 | 2
38 * 1 | 1.55 | 4
39 * 2 | 2.35 | 6
40 * 3 | 3.1 | 8
41 * 4 | 3.9 | 10
42 * 5 | 4.65 | 12
43 * 6 | 5.4 | 14
44 * 7 | 6.15 | 16
45 *
46 * POR value for UFS_RESET HDRV is 3 which means
47 * 3.1mA and we want to use that. Hence just
48 * specify 8mA to "drive-strength" binding and
49 * that should result into writing 3 to HDRV
50 * field.
51 */
52 drive-strength = <8>; /* default: 3.1 mA */
53 output-low; /* active low reset */
54 };
55 };
56
57 ufs_dev_reset_deassert: ufs_dev_reset_deassert {
58 config {
59 pins = "ufs_reset";
60 bias-pull-down; /* default: pull down */
61 /*
62 * default: 3.1 mA
63 * check comments under ufs_dev_reset_assert
64 */
65 drive-strength = <8>;
66 output-high; /* active low reset */
67 };
68 };
69
Subbaraman Narayanamurthycd21c812017-03-30 18:36:49 -070070 flash_led3_front {
71 flash_led3_front_en: flash_led3_front_en {
72 mux {
73 pins = "gpio21";
Subbaraman Narayanamurthy58377f02017-03-21 20:38:43 -070074 function = "gpio";
75 };
76
77 config {
78 pins = "gpio21";
Subbaraman Narayanamurthycd21c812017-03-30 18:36:49 -070079 drive_strength = <2>;
80 output-high;
Subbaraman Narayanamurthy58377f02017-03-21 20:38:43 -070081 bias-disable;
Subbaraman Narayanamurthycd21c812017-03-30 18:36:49 -070082 };
83 };
84
85 flash_led3_front_dis: flash_led3_front_dis {
86 mux {
87 pins = "gpio21";
Subbaraman Narayanamurthy58377f02017-03-21 20:38:43 -070088 function = "gpio";
89 };
90
91 config {
92 pins = "gpio21";
Subbaraman Narayanamurthycd21c812017-03-30 18:36:49 -070093 drive_strength = <2>;
94 output-low;
Subbaraman Narayanamurthy58377f02017-03-21 20:38:43 -070095 bias-disable;
Subbaraman Narayanamurthycd21c812017-03-30 18:36:49 -070096 };
97 };
98 };
Subhash Jadavaniafe2a792017-03-31 21:08:29 -070099
Banajit Goswamib016de92017-02-15 21:02:30 -0800100 wcd9xxx_intr {
101 wcd_intr_default: wcd_intr_default{
102 mux {
103 pins = "gpio54";
104 function = "gpio";
105 };
106
107 config {
108 pins = "gpio54";
109 drive-strength = <2>; /* 2 mA */
110 bias-pull-down; /* pull down */
111 input-enable;
112 };
113 };
114 };
115
Subhash Jadavanidd416c42017-05-15 11:54:10 -0700116 storage_cd: storage_cd {
117 mux {
118 pins = "gpio126";
119 function = "gpio";
120 };
121
122 config {
123 pins = "gpio126";
124 bias-pull-up; /* pull up */
125 drive-strength = <2>; /* 2 MA */
126 };
127 };
128
Xiaonian Wang898e0902017-04-08 06:46:29 +0800129 sdc2_clk_on: sdc2_clk_on {
130 config {
131 pins = "sdc2_clk";
132 bias-disable; /* NO pull */
133 drive-strength = <16>; /* 16 MA */
134 };
135 };
136
137 sdc2_clk_off: sdc2_clk_off {
138 config {
139 pins = "sdc2_clk";
140 bias-disable; /* NO pull */
141 drive-strength = <2>; /* 2 MA */
142 };
143 };
144
145 sdc2_cmd_on: sdc2_cmd_on {
146 config {
147 pins = "sdc2_cmd";
148 bias-pull-up; /* pull up */
149 drive-strength = <10>; /* 10 MA */
150 };
151 };
152
153 sdc2_cmd_off: sdc2_cmd_off {
154 config {
155 pins = "sdc2_cmd";
156 bias-pull-up; /* pull up */
157 drive-strength = <2>; /* 2 MA */
158 };
159 };
160
161 sdc2_data_on: sdc2_data_on {
162 config {
163 pins = "sdc2_data";
164 bias-pull-up; /* pull up */
165 drive-strength = <10>; /* 10 MA */
166 };
167 };
168
169 sdc2_data_off: sdc2_data_off {
170 config {
171 pins = "sdc2_data";
172 bias-pull-up; /* pull up */
173 drive-strength = <2>; /* 2 MA */
174 };
175 };
176
Tony Truongc0e0a5f02017-03-15 11:57:40 -0700177 pcie0 {
178 pcie0_clkreq_default: pcie0_clkreq_default {
179 mux {
180 pins = "gpio36";
181 function = "pci_e0";
182 };
183
184 config {
185 pins = "gpio36";
186 drive-strength = <2>;
187 bias-pull-up;
188 };
189 };
190
191 pcie0_perst_default: pcie0_perst_default {
192 mux {
193 pins = "gpio35";
194 function = "gpio";
195 };
196
197 config {
198 pins = "gpio35";
199 drive-strength = <2>;
200 bias-pull-down;
201 };
202 };
203
204 pcie0_wake_default: pcie0_wake_default {
205 mux {
206 pins = "gpio37";
207 function = "gpio";
208 };
209
210 config {
211 pins = "gpio37";
212 drive-strength = <2>;
Tony Truong299dda12017-09-12 14:32:44 -0700213 bias-pull-up;
Tony Truongc0e0a5f02017-03-15 11:57:40 -0700214 };
215 };
216 };
217
Tony Truong16938352017-05-04 13:39:24 -0700218 pcie1 {
219 pcie1_clkreq_default: pcie1_clkreq_default {
220 mux {
221 pins = "gpio103";
222 function = "pci_e1";
223 };
224
225 config {
226 pins = "gpio103";
227 drive-strength = <2>;
228 bias-pull-up;
229 };
230 };
231
232 pcie1_perst_default: pcie1_perst_default {
233 mux {
234 pins = "gpio102";
235 function = "gpio";
236 };
237
238 config {
239 pins = "gpio102";
240 drive-strength = <2>;
241 bias-pull-down;
242 };
243 };
244
245 pcie1_wake_default: pcie1_wake_default {
246 mux {
247 pins = "gpio104";
248 function = "gpio";
249 };
250
251 config {
252 pins = "gpio104";
253 drive-strength = <2>;
254 bias-pull-down;
255 };
256 };
257 };
258
Banajit Goswamib016de92017-02-15 21:02:30 -0800259 cdc_reset_ctrl {
260 cdc_reset_sleep: cdc_reset_sleep {
261 mux {
262 pins = "gpio64";
263 function = "gpio";
264 };
265 config {
266 pins = "gpio64";
267 drive-strength = <2>;
268 bias-disable;
269 output-low;
270 };
271 };
272
273 cdc_reset_active:cdc_reset_active {
274 mux {
275 pins = "gpio64";
276 function = "gpio";
277 };
278 config {
279 pins = "gpio64";
280 drive-strength = <8>;
281 bias-pull-down;
282 output-high;
283 };
284 };
285 };
286
287 spkr_i2s_clk_pin {
288 spkr_i2s_clk_sleep: spkr_i2s_clk_sleep {
289 mux {
290 pins = "gpio69";
291 function = "spkr_i2s";
292 };
293
294 config {
295 pins = "gpio69";
296 drive-strength = <2>; /* 2 mA */
297 bias-pull-down; /* PULL DOWN */
298 };
299 };
300
301 spkr_i2s_clk_active: spkr_i2s_clk_active {
302 mux {
303 pins = "gpio69";
304 function = "spkr_i2s";
305 };
306
307 config {
308 pins = "gpio69";
309 drive-strength = <8>; /* 8 mA */
310 bias-disable; /* NO PULL */
311 };
312 };
313 };
314
315 wcd_gnd_mic_swap {
316 wcd_gnd_mic_swap_idle: wcd_gnd_mic_swap_idle {
317 mux {
318 pins = "gpio51";
319 function = "gpio";
320 };
321 config {
322 pins = "gpio51";
323 drive-strength = <2>;
324 bias-pull-down;
325 output-low;
326 };
327 };
328
329 wcd_gnd_mic_swap_active: wcd_gnd_mic_swap_active {
330 mux {
331 pins = "gpio51";
332 function = "gpio";
333 };
334 config {
335 pins = "gpio51";
336 drive-strength = <2>;
337 bias-disable;
338 output-high;
339 };
340 };
341 };
342
Karthikeyan Mani5bce47c2017-05-26 15:19:04 -0700343 /* USB C analog configuration */
344 wcd_usbc_analog_en1 {
345 wcd_usbc_analog_en1_idle: wcd_usbc_ana_en1_idle {
346 mux {
347 pins = "gpio49";
348 function = "gpio";
349 };
350 config {
351 pins = "gpio49";
352 drive-strength = <2>;
353 bias-pull-down;
354 output-low;
355 };
356 };
357
358 wcd_usbc_analog_en1_active: wcd_usbc_ana_en1_active {
359 mux {
360 pins = "gpio49";
361 function = "gpio";
362 };
363 config {
364 pins = "gpio49";
365 drive-strength = <2>;
366 bias-disable;
367 output-high;
368 };
369 };
370 };
371
372 wcd_usbc_analog_en2 {
373 wcd_usbc_analog_en2_idle: wcd_usbc_ana_en2_idle {
374 mux {
375 pins = "gpio51";
376 function = "gpio";
377 };
378 config {
379 pins = "gpio51";
380 drive-strength = <2>;
381 bias-pull-down;
382 output-low;
383 };
384 };
385
386 wcd_usbc_analog_en2_active: wcd_usbc_ana_en2_active {
387 mux {
388 pins = "gpio51";
389 function = "gpio";
390 };
391 config {
392 pins = "gpio51";
393 drive-strength = <2>;
394 bias-disable;
395 output-high;
396 };
397 };
398 };
399
Banajit Goswamib016de92017-02-15 21:02:30 -0800400 pri_aux_pcm_clk {
401 pri_aux_pcm_clk_sleep: pri_aux_pcm_clk_sleep {
402 mux {
403 pins = "gpio65";
404 function = "gpio";
405 };
406
407 config {
408 pins = "gpio65";
409 drive-strength = <2>; /* 2 mA */
410 bias-pull-down; /* PULL DOWN */
411 input-enable;
412 };
413 };
414
415 pri_aux_pcm_clk_active: pri_aux_pcm_clk_active {
416 mux {
417 pins = "gpio65";
418 function = "pri_mi2s";
419 };
420
421 config {
422 pins = "gpio65";
423 drive-strength = <8>; /* 8 mA */
424 bias-disable; /* NO PULL */
425 output-high;
426 };
427 };
428 };
429
430 pri_aux_pcm_sync {
431 pri_aux_pcm_sync_sleep: pri_aux_pcm_sync_sleep {
432 mux {
433 pins = "gpio66";
434 function = "gpio";
435 };
436
437 config {
438 pins = "gpio66";
439 drive-strength = <2>; /* 2 mA */
440 bias-pull-down; /* PULL DOWN */
441 input-enable;
442 };
443 };
444
445 pri_aux_pcm_sync_active: pri_aux_pcm_sync_active {
446 mux {
447 pins = "gpio66";
448 function = "pri_mi2s_ws";
449 };
450
451 config {
452 pins = "gpio66";
453 drive-strength = <8>; /* 8 mA */
454 bias-disable; /* NO PULL */
455 output-high;
456 };
457 };
458 };
459
460 pri_aux_pcm_din {
461 pri_aux_pcm_din_sleep: pri_aux_pcm_din_sleep {
462 mux {
463 pins = "gpio67";
464 function = "gpio";
465 };
466
467 config {
468 pins = "gpio67";
469 drive-strength = <2>; /* 2 mA */
470 bias-pull-down; /* PULL DOWN */
471 input-enable;
472 };
473 };
474
475 pri_aux_pcm_din_active: pri_aux_pcm_din_active {
476 mux {
477 pins = "gpio67";
478 function = "pri_mi2s";
479 };
480
481 config {
482 pins = "gpio67";
483 drive-strength = <8>; /* 8 mA */
484 bias-disable; /* NO PULL */
485 };
486 };
487 };
488
489 pri_aux_pcm_dout {
490 pri_aux_pcm_dout_sleep: pri_aux_pcm_dout_sleep {
491 mux {
492 pins = "gpio68";
493 function = "gpio";
494 };
495
496 config {
497 pins = "gpio68";
498 drive-strength = <2>; /* 2 mA */
499 bias-pull-down; /* PULL DOWN */
500 input-enable;
501 };
502 };
503
504 pri_aux_pcm_dout_active: pri_aux_pcm_dout_active {
505 mux {
506 pins = "gpio68";
507 function = "pri_mi2s";
508 };
509
510 config {
511 pins = "gpio68";
512 drive-strength = <8>; /* 8 mA */
513 bias-disable; /* NO PULL */
514 };
515 };
516 };
517
Shashank Babu Chinta Venkata2f40bc72017-03-21 15:31:38 -0700518 pmx_sde: pmx_sde {
519 sde_dsi_active: sde_dsi_active {
520 mux {
521 pins = "gpio6", "gpio52";
522 function = "gpio";
523 };
524
525 config {
526 pins = "gpio6", "gpio52";
527 drive-strength = <8>; /* 8 mA */
528 bias-disable = <0>; /* no pull */
529 };
530 };
531 sde_dsi_suspend: sde_dsi_suspend {
532 mux {
533 pins = "gpio6", "gpio52";
534 function = "gpio";
535 };
536
537 config {
538 pins = "gpio6", "gpio52";
539 drive-strength = <2>; /* 2 mA */
540 bias-pull-down; /* PULL DOWN */
541 };
542 };
543 };
544
545 pmx_sde_te {
546 sde_te_active: sde_te_active {
547 mux {
548 pins = "gpio10";
549 function = "mdp_vsync";
550 };
551
552 config {
553 pins = "gpio10";
554 drive-strength = <2>; /* 2 mA */
555 bias-pull-down; /* PULL DOWN */
556 };
557 };
558
559 sde_te_suspend: sde_te_suspend {
560 mux {
561 pins = "gpio10";
562 function = "mdp_vsync";
563 };
564
565 config {
566 pins = "gpio10";
567 drive-strength = <2>; /* 2 mA */
568 bias-pull-down; /* PULL DOWN */
569 };
570 };
571 };
572
Padmanabhan Komanduru887085e2017-05-02 14:57:12 -0700573 sde_dp_aux_active: sde_dp_aux_active {
574 mux {
575 pins = "gpio43", "gpio51";
576 function = "gpio";
577 };
578
579 config {
580 pins = "gpio43", "gpio51";
581 bias-disable = <0>; /* no pull */
582 drive-strength = <8>;
583 };
584 };
585
586 sde_dp_aux_suspend: sde_dp_aux_suspend {
587 mux {
588 pins = "gpio43", "gpio51";
589 function = "gpio";
590 };
591
592 config {
593 pins = "gpio43", "gpio51";
594 bias-pull-down;
595 drive-strength = <2>;
596 };
597 };
598
599 sde_dp_usbplug_cc_active: sde_dp_usbplug_cc_active {
600 mux {
601 pins = "gpio38";
602 function = "gpio";
603 };
604
605 config {
606 pins = "gpio38";
607 bias-disable;
608 drive-strength = <16>;
609 };
610 };
611
612 sde_dp_usbplug_cc_suspend: sde_dp_usbplug_cc_suspend {
613 mux {
614 pins = "gpio38";
615 function = "gpio";
616 };
617
618 config {
619 pins = "gpio38";
620 bias-pull-down;
621 drive-strength = <2>;
622 };
623 };
624
Banajit Goswamib016de92017-02-15 21:02:30 -0800625 sec_aux_pcm {
626 sec_aux_pcm_sleep: sec_aux_pcm_sleep {
627 mux {
628 pins = "gpio80", "gpio81";
629 function = "gpio";
630 };
631
632 config {
633 pins = "gpio80", "gpio81";
634 drive-strength = <2>; /* 2 mA */
635 bias-pull-down; /* PULL DOWN */
636 input-enable;
637 };
638 };
639
640 sec_aux_pcm_active: sec_aux_pcm_active {
641 mux {
642 pins = "gpio80", "gpio81";
643 function = "sec_mi2s";
644 };
645
646 config {
647 pins = "gpio80", "gpio81";
648 drive-strength = <8>; /* 8 mA */
649 bias-disable; /* NO PULL */
650 };
651 };
652 };
653
654 sec_aux_pcm_din {
655 sec_aux_pcm_din_sleep: sec_aux_pcm_din_sleep {
656 mux {
657 pins = "gpio82";
658 function = "gpio";
659 };
660
661 config {
662 pins = "gpio82";
663 drive-strength = <2>; /* 2 mA */
664 bias-pull-down; /* PULL DOWN */
665 input-enable;
666 };
667 };
668
669 sec_aux_pcm_din_active: sec_aux_pcm_din_active {
670 mux {
671 pins = "gpio82";
672 function = "sec_mi2s";
673 };
674
675 config {
676 pins = "gpio82";
677 drive-strength = <8>; /* 8 mA */
678 bias-disable; /* NO PULL */
679 };
680 };
681 };
682
683 sec_aux_pcm_dout {
684 sec_aux_pcm_dout_sleep: sec_aux_pcm_dout_sleep {
685 mux {
686 pins = "gpio83";
687 function = "gpio";
688 };
689
690 config {
691 pins = "gpio83";
692 drive-strength = <2>; /* 2 mA */
693 bias-pull-down; /* PULL DOWN */
694 input-enable;
695 };
696 };
697
698 sec_aux_pcm_dout_active: sec_aux_pcm_dout_active {
699 mux {
700 pins = "gpio83";
701 function = "sec_mi2s";
702 };
703
704 config {
705 pins = "gpio83";
706 drive-strength = <8>; /* 8 mA */
707 bias-disable; /* NO PULL */
708 };
709 };
710 };
711
712 tert_aux_pcm {
713 tert_aux_pcm_sleep: tert_aux_pcm_sleep {
714 mux {
715 pins = "gpio75", "gpio76";
716 function = "gpio";
717 };
718
719 config {
720 pins = "gpio75", "gpio76";
721 drive-strength = <2>; /* 2 mA */
722 bias-pull-down; /* PULL DOWN */
723 input-enable;
724 };
725 };
726
727 tert_aux_pcm_active: tert_aux_pcm_active {
728 mux {
729 pins = "gpio75", "gpio76";
730 function = "ter_mi2s";
731 };
732
733 config {
734 pins = "gpio75", "gpio76";
735 drive-strength = <8>; /* 8 mA */
736 bias-disable; /* NO PULL */
737 output-high;
738 };
739 };
740 };
741
742 tert_aux_pcm_din {
743 tert_aux_pcm_din_sleep: tert_aux_pcm_din_sleep {
744 mux {
745 pins = "gpio77";
746 function = "gpio";
747 };
748
749 config {
750 pins = "gpio77";
751 drive-strength = <2>; /* 2 mA */
752 bias-pull-down; /* PULL DOWN */
753 input-enable;
754 };
755 };
756
757 tert_aux_pcm_din_active: tert_aux_pcm_din_active {
758 mux {
759 pins = "gpio77";
760 function = "ter_mi2s";
761 };
762
763 config {
764 pins = "gpio77";
765 drive-strength = <8>; /* 8 mA */
766 bias-disable; /* NO PULL */
767 };
768 };
769 };
770
771 tert_aux_pcm_dout {
772 tert_aux_pcm_dout_sleep: tert_aux_pcm_dout_sleep {
773 mux {
774 pins = "gpio78";
775 function = "gpio";
776 };
777
778 config {
779 pins = "gpio78";
780 drive-strength = <2>; /* 2 mA */
781 bias-pull-down; /* PULL DOWN */
782 input-enable;
783 };
784 };
785
786 tert_aux_pcm_dout_active: tert_aux_pcm_dout_active {
787 mux {
788 pins = "gpio78";
789 function = "ter_mi2s";
790 };
791
792 config {
793 pins = "gpio78";
794 drive-strength = <8>; /* 8 mA */
795 bias-disable; /* NO PULL */
796 };
797 };
798 };
799
800 quat_aux_pcm {
801 quat_aux_pcm_sleep: quat_aux_pcm_sleep {
802 mux {
803 pins = "gpio58", "gpio59";
804 function = "gpio";
805 };
806
807 config {
808 pins = "gpio58", "gpio59";
809 drive-strength = <2>; /* 2 mA */
810 bias-pull-down; /* PULL DOWN */
811 input-enable;
812 };
813 };
814
815 quat_aux_pcm_active: quat_aux_pcm_active {
816 mux {
817 pins = "gpio58", "gpio59";
818 function = "qua_mi2s";
819 };
820
821 config {
822 pins = "gpio58", "gpio59";
823 drive-strength = <8>; /* 8 mA */
824 bias-disable; /* NO PULL */
825 output-high;
826 };
827 };
828 };
829
830 quat_aux_pcm_din {
831 quat_aux_pcm_din_sleep: quat_aux_pcm_din_sleep {
832 mux {
833 pins = "gpio60";
834 function = "gpio";
835 };
836
837 config {
838 pins = "gpio60";
839 drive-strength = <2>; /* 2 mA */
840 bias-pull-down; /* PULL DOWN */
841 input-enable;
842 };
843 };
844
845 quat_aux_pcm_din_active: quat_aux_pcm_din_active {
846 mux {
847 pins = "gpio60";
848 function = "qua_mi2s";
849 };
850
851 config {
852 pins = "gpio60";
853 drive-strength = <8>; /* 8 mA */
854 bias-disable; /* NO PULL */
855 };
856 };
857 };
858
859 quat_aux_pcm_dout {
860 quat_aux_pcm_dout_sleep: quat_aux_pcm_dout_sleep {
861 mux {
862 pins = "gpio61";
863 function = "gpio";
864 };
865
866 config {
867 pins = "gpio61";
868 drive-strength = <2>; /* 2 mA */
869 bias-pull-down; /* PULL DOWN */
870 input-enable;
871 };
872 };
873
874 quat_aux_pcm_dout_active: quat_aux_pcm_dout_active {
875 mux {
876 pins = "gpio61";
877 function = "qua_mi2s";
878 };
879
880 config {
881 pins = "gpio61";
882 drive-strength = <8>; /* 8 mA */
883 bias-disable; /* NO PULL */
884 };
885 };
886 };
887
888 pri_mi2s_mclk {
889 pri_mi2s_mclk_sleep: pri_mi2s_mclk_sleep {
890 mux {
891 pins = "gpio64";
892 function = "gpio";
893 };
894
895 config {
896 pins = "gpio64";
897 drive-strength = <2>; /* 2 mA */
898 bias-pull-down; /* PULL DOWN */
899 input-enable;
900 };
901 };
902
903 pri_mi2s_mclk_active: pri_mi2s_mclk_active {
904 mux {
905 pins = "gpio64";
906 function = "pri_mi2s";
907 };
908
909 config {
910 pins = "gpio64";
911 drive-strength = <8>; /* 8 mA */
912 bias-disable; /* NO PULL */
913 output-high;
914 };
915 };
916 };
917
918 pri_mi2s_sck {
919 pri_mi2s_sck_sleep: pri_mi2s_sck_sleep {
920 mux {
921 pins = "gpio65";
922 function = "gpio";
923 };
924
925 config {
926 pins = "gpio65";
927 drive-strength = <2>; /* 2 mA */
928 bias-pull-down; /* PULL DOWN */
929 input-enable;
930 };
931 };
932
933 pri_mi2s_sck_active: pri_mi2s_sck_active {
934 mux {
935 pins = "gpio65";
936 function = "pri_mi2s";
937 };
938
939 config {
940 pins = "gpio65";
941 drive-strength = <8>; /* 8 mA */
942 bias-disable; /* NO PULL */
943 output-high;
944 };
945 };
946 };
947
948 pri_mi2s_ws {
949 pri_mi2s_ws_sleep: pri_mi2s_ws_sleep {
950 mux {
951 pins = "gpio66";
952 function = "gpio";
953 };
954
955 config {
956 pins = "gpio66";
957 drive-strength = <2>; /* 2 mA */
958 bias-pull-down; /* PULL DOWN */
959 input-enable;
960 };
961 };
962
963 pri_mi2s_ws_active: pri_mi2s_ws_active {
964 mux {
965 pins = "gpio66";
966 function = "pri_mi2s_ws";
967 };
968
969 config {
970 pins = "gpio66";
971 drive-strength = <8>; /* 8 mA */
972 bias-disable; /* NO PULL */
973 output-high;
974 };
975 };
976 };
977
978 pri_mi2s_sd0 {
979 pri_mi2s_sd0_sleep: pri_mi2s_sd0_sleep {
980 mux {
981 pins = "gpio67";
982 function = "gpio";
983 };
984
985 config {
986 pins = "gpio67";
987 drive-strength = <2>; /* 2 mA */
988 bias-pull-down; /* PULL DOWN */
989 input-enable;
990 };
991 };
992
993 pri_mi2s_sd0_active: pri_mi2s_sd0_active {
994 mux {
995 pins = "gpio67";
996 function = "pri_mi2s";
997 };
998
999 config {
1000 pins = "gpio67";
1001 drive-strength = <8>; /* 8 mA */
1002 bias-disable; /* NO PULL */
1003 };
1004 };
1005 };
1006
1007 pri_mi2s_sd1 {
1008 pri_mi2s_sd1_sleep: pri_mi2s_sd1_sleep {
1009 mux {
1010 pins = "gpio68";
1011 function = "gpio";
1012 };
1013
1014 config {
1015 pins = "gpio68";
1016 drive-strength = <2>; /* 2 mA */
1017 bias-pull-down; /* PULL DOWN */
1018 input-enable;
1019 };
1020 };
1021
1022 pri_mi2s_sd1_active: pri_mi2s_sd1_active {
1023 mux {
1024 pins = "gpio68";
1025 function = "pri_mi2s";
1026 };
1027
1028 config {
1029 pins = "gpio68";
1030 drive-strength = <8>; /* 8 mA */
1031 bias-disable; /* NO PULL */
1032 };
1033 };
1034 };
1035
1036 sec_mi2s_mclk {
1037 sec_mi2s_mclk_sleep: sec_mi2s_mclk_sleep {
1038 mux {
1039 pins = "gpio79";
1040 function = "gpio";
1041 };
1042
1043 config {
1044 pins = "gpio79";
1045 drive-strength = <2>; /* 2 mA */
1046 bias-pull-down; /* PULL DOWN */
1047 input-enable;
1048 };
1049 };
1050
1051 sec_mi2s_mclk_active: sec_mi2s_mclk_active {
1052 mux {
1053 pins = "gpio79";
1054 function = "sec_mi2s";
1055 };
1056
1057 config {
1058 pins = "gpio79";
1059 drive-strength = <8>; /* 8 mA */
1060 bias-disable; /* NO PULL */
1061 };
1062 };
1063 };
1064
1065 sec_mi2s {
1066 sec_mi2s_sleep: sec_mi2s_sleep {
1067 mux {
1068 pins = "gpio80", "gpio81";
1069 function = "gpio";
1070 };
1071
1072 config {
1073 pins = "gpio80", "gpio81";
1074 drive-strength = <2>; /* 2 mA */
1075 bias-disable; /* NO PULL */
1076 input-enable;
1077 };
1078 };
1079
1080 sec_mi2s_active: sec_mi2s_active {
1081 mux {
1082 pins = "gpio80", "gpio81";
1083 function = "sec_mi2s";
1084 };
1085
1086 config {
1087 pins = "gpio80", "gpio81";
1088 drive-strength = <8>; /* 8 mA */
1089 bias-disable; /* NO PULL */
1090 };
1091 };
1092 };
1093
1094 sec_mi2s_sd0 {
1095 sec_mi2s_sd0_sleep: sec_mi2s_sd0_sleep {
1096 mux {
1097 pins = "gpio82";
1098 function = "gpio";
1099 };
1100
1101 config {
1102 pins = "gpio82";
1103 drive-strength = <2>; /* 2 mA */
1104 bias-pull-down; /* PULL DOWN */
1105 input-enable;
1106 };
1107 };
1108
1109 sec_mi2s_sd0_active: sec_mi2s_sd0_active {
1110 mux {
1111 pins = "gpio82";
1112 function = "sec_mi2s";
1113 };
1114
1115 config {
1116 pins = "gpio82";
1117 drive-strength = <8>; /* 8 mA */
1118 bias-disable; /* NO PULL */
1119 };
1120 };
1121 };
1122
1123 sec_mi2s_sd1 {
1124 sec_mi2s_sd1_sleep: sec_mi2s_sd1_sleep {
1125 mux {
1126 pins = "gpio83";
1127 function = "gpio";
1128 };
1129
1130 config {
1131 pins = "gpio83";
1132 drive-strength = <2>; /* 2 mA */
1133 bias-pull-down; /* PULL DOWN */
1134 input-enable;
1135 };
1136 };
1137
1138 sec_mi2s_sd1_active: sec_mi2s_sd1_active {
1139 mux {
1140 pins = "gpio83";
1141 function = "sec_mi2s";
1142 };
1143
1144 config {
1145 pins = "gpio83";
1146 drive-strength = <8>; /* 8 mA */
1147 bias-disable; /* NO PULL */
1148 };
1149 };
1150 };
1151
1152 tert_mi2s_mclk {
1153 tert_mi2s_mclk_sleep: tert_mi2s_mclk_sleep {
1154 mux {
1155 pins = "gpio74";
1156 function = "gpio";
1157 };
1158
1159 config {
1160 pins = "gpio74";
1161 drive-strength = <2>; /* 2 mA */
1162 bias-pull-down; /* PULL DOWN */
1163 input-enable;
1164 };
1165 };
1166
1167 tert_mi2s_mclk_active: tert_mi2s_mclk_active {
1168 mux {
1169 pins = "gpio74";
1170 function = "ter_mi2s";
1171 };
1172
1173 config {
1174 pins = "gpio74";
1175 drive-strength = <8>; /* 8 mA */
1176 bias-disable; /* NO PULL */
1177 };
1178 };
1179 };
1180
1181 tert_mi2s {
1182 tert_mi2s_sleep: tert_mi2s_sleep {
1183 mux {
1184 pins = "gpio75", "gpio76";
1185 function = "gpio";
1186 };
1187
1188 config {
1189 pins = "gpio75", "gpio76";
1190 drive-strength = <2>; /* 2 mA */
1191 bias-pull-down; /* PULL DOWN */
1192 input-enable;
1193 };
1194 };
1195
1196 tert_mi2s_active: tert_mi2s_active {
1197 mux {
1198 pins = "gpio75", "gpio76";
1199 function = "ter_mi2s";
1200 };
1201
1202 config {
1203 pins = "gpio75", "gpio76";
1204 drive-strength = <8>; /* 8 mA */
1205 bias-disable; /* NO PULL */
1206 output-high;
1207 };
1208 };
1209 };
1210
1211 tert_mi2s_sd0 {
1212 tert_mi2s_sd0_sleep: tert_mi2s_sd0_sleep {
1213 mux {
1214 pins = "gpio77";
1215 function = "gpio";
1216 };
1217
1218 config {
1219 pins = "gpio77";
1220 drive-strength = <2>; /* 2 mA */
1221 bias-pull-down; /* PULL DOWN */
1222 input-enable;
1223 };
1224 };
1225
1226 tert_mi2s_sd0_active: tert_mi2s_sd0_active {
1227 mux {
1228 pins = "gpio77";
1229 function = "ter_mi2s";
1230 };
1231
1232 config {
1233 pins = "gpio77";
1234 drive-strength = <8>; /* 8 mA */
1235 bias-disable; /* NO PULL */
1236 };
1237 };
1238 };
1239
1240 tert_mi2s_sd1 {
1241 tert_mi2s_sd1_sleep: tert_mi2s_sd1_sleep {
1242 mux {
1243 pins = "gpio78";
1244 function = "gpio";
1245 };
1246
1247 config {
1248 pins = "gpio78";
1249 drive-strength = <2>; /* 2 mA */
1250 bias-pull-down; /* PULL DOWN */
1251 input-enable;
1252 };
1253 };
1254
1255 tert_mi2s_sd1_active: tert_mi2s_sd1_active {
1256 mux {
1257 pins = "gpio78";
1258 function = "ter_mi2s";
1259 };
1260
1261 config {
1262 pins = "gpio78";
1263 drive-strength = <8>; /* 8 mA */
1264 bias-disable; /* NO PULL */
1265 };
1266 };
1267 };
1268
1269 quat_mi2s_mclk {
1270 quat_mi2s_mclk_sleep: quat_mi2s_mclk_sleep {
1271 mux {
1272 pins = "gpio57";
1273 function = "gpio";
1274 };
1275
1276 config {
1277 pins = "gpio57";
1278 drive-strength = <2>; /* 2 mA */
1279 bias-pull-down; /* PULL DOWN */
1280 input-enable;
1281 };
1282 };
1283
1284 quat_mi2s_mclk_active: quat_mi2s_mclk_active {
1285 mux {
1286 pins = "gpio57";
1287 function = "qua_mi2s";
1288 };
1289
1290 config {
1291 pins = "gpio57";
1292 drive-strength = <8>; /* 8 mA */
1293 bias-disable; /* NO PULL */
1294 };
1295 };
1296 };
1297
1298 quat_mi2s {
1299 quat_mi2s_sleep: quat_mi2s_sleep {
1300 mux {
1301 pins = "gpio58", "gpio59";
1302 function = "gpio";
1303 };
1304
1305 config {
1306 pins = "gpio58", "gpio59";
1307 drive-strength = <2>; /* 2 mA */
1308 bias-pull-down; /* PULL DOWN */
1309 input-enable;
1310 };
1311 };
1312
1313 quat_mi2s_active: quat_mi2s_active {
1314 mux {
1315 pins = "gpio58", "gpio59";
1316 function = "qua_mi2s";
1317 };
1318
1319 config {
1320 pins = "gpio58", "gpio59";
1321 drive-strength = <8>; /* 8 mA */
1322 bias-disable; /* NO PULL */
1323 output-high;
1324 };
1325 };
1326 };
1327
1328 quat_mi2s_sd0 {
1329 quat_mi2s_sd0_sleep: quat_mi2s_sd0_sleep {
1330 mux {
1331 pins = "gpio60";
1332 function = "gpio";
1333 };
1334
1335 config {
1336 pins = "gpio60";
1337 drive-strength = <2>; /* 2 mA */
1338 bias-pull-down; /* PULL DOWN */
1339 input-enable;
1340 };
1341 };
1342
1343 quat_mi2s_sd0_active: quat_mi2s_sd0_active {
1344 mux {
1345 pins = "gpio60";
1346 function = "qua_mi2s";
1347 };
1348
1349 config {
1350 pins = "gpio60";
1351 drive-strength = <8>; /* 8 mA */
1352 bias-disable; /* NO PULL */
1353 };
1354 };
1355 };
1356
1357 quat_mi2s_sd1 {
1358 quat_mi2s_sd1_sleep: quat_mi2s_sd1_sleep {
1359 mux {
1360 pins = "gpio61";
1361 function = "gpio";
1362 };
1363
1364 config {
1365 pins = "gpio61";
1366 drive-strength = <2>; /* 2 mA */
1367 bias-pull-down; /* PULL DOWN */
1368 input-enable;
1369 };
1370 };
1371
1372 quat_mi2s_sd1_active: quat_mi2s_sd1_active {
1373 mux {
1374 pins = "gpio61";
1375 function = "qua_mi2s";
1376 };
1377
1378 config {
1379 pins = "gpio61";
1380 drive-strength = <8>; /* 8 mA */
1381 bias-disable; /* NO PULL */
1382 };
1383 };
1384 };
1385
1386 quat_mi2s_sd2 {
1387 quat_mi2s_sd2_sleep: quat_mi2s_sd2_sleep {
1388 mux {
1389 pins = "gpio62";
1390 function = "gpio";
1391 };
1392
1393 config {
1394 pins = "gpio62";
1395 drive-strength = <2>; /* 2 mA */
1396 bias-pull-down; /* PULL DOWN */
1397 input-enable;
1398 };
1399 };
1400
1401 quat_mi2s_sd2_active: quat_mi2s_sd2_active {
1402 mux {
1403 pins = "gpio62";
1404 function = "qua_mi2s";
1405 };
1406
1407 config {
1408 pins = "gpio62";
1409 drive-strength = <8>; /* 8 mA */
1410 bias-disable; /* NO PULL */
1411 };
1412 };
1413 };
1414
1415 quat_mi2s_sd3 {
1416 quat_mi2s_sd3_sleep: quat_mi2s_sd3_sleep {
1417 mux {
1418 pins = "gpio63";
1419 function = "gpio";
1420 };
1421
1422 config {
1423 pins = "gpio63";
1424 drive-strength = <2>; /* 2 mA */
1425 bias-pull-down; /* PULL DOWN */
1426 input-enable;
1427 };
1428 };
1429
1430 quat_mi2s_sd3_active: quat_mi2s_sd3_active {
1431 mux {
1432 pins = "gpio63";
1433 function = "qua_mi2s";
1434 };
1435
1436 config {
1437 pins = "gpio63";
1438 drive-strength = <8>; /* 8 mA */
1439 bias-disable; /* NO PULL */
1440 };
1441 };
1442 };
Girish Mahadevan2e2fbe72017-03-28 13:28:18 -06001443
Xiaoyu Yee1bd1c62017-07-31 16:36:25 -07001444 quat_tdm {
1445 quat_tdm_sleep: quat_tdm_sleep {
1446 mux {
1447 pins = "gpio58", "gpio59";
1448 function = "qua_mi2s";
1449 };
1450
1451 config {
1452 pins = "gpio58", "gpio59";
1453 drive-strength = <2>; /* 2 mA */
1454 bias-pull-down; /* PULL DOWN */
1455 };
1456 };
1457
1458 quat_tdm_active: quat_tdm_active {
1459 mux {
1460 pins = "gpio58", "gpio59";
1461 function = "qua_mi2s";
1462 };
1463
1464 config {
1465 pins = "gpio58", "gpio59";
1466 drive-strength = <8>; /* 8 mA */
1467 bias-disable; /* NO PULL */
1468 };
1469 };
1470 };
1471
1472 quat_tdm_dout {
1473 quat_tdm_dout_sleep: quat_tdm_dout_sleep {
1474 mux {
1475 pins = "gpio61";
1476 function = "qua_mi2s";
1477 };
1478
1479 config {
1480 pins = "gpio61";
1481 drive-strength = <2>; /* 2 mA */
1482 bias-pull-down; /* PULL DOWN */
1483 };
1484 };
1485
1486 quat_tdm_dout_active: quat_tdm_dout_active {
1487 mux {
1488 pins = "gpio61";
1489 function = "qua_mi2s";
1490 };
1491
1492 config {
1493 pins = "gpio61";
1494 drive-strength = <2>; /* 2 mA */
1495 bias-disable; /* NO PULL */
1496 };
1497 };
1498 };
1499
1500 quat_tdm_din {
1501 quat_tdm_din_sleep: quat_tdm_din_sleep {
1502 mux {
1503 pins = "gpio60";
1504 function = "qua_mi2s";
1505 };
1506
1507 config {
1508 pins = "gpio60";
1509 drive-strength = <2>; /* 2 mA */
1510 bias-pull-down; /* PULL DOWN */
1511 };
1512 };
1513
1514 quat_tdm_din_active: quat_tdm_din_active {
1515 mux {
1516 pins = "gpio60";
1517 function = "qua_mi2s";
1518 };
1519
1520 config {
1521 pins = "gpio60";
1522 drive-strength = <2>; /* 2 mA */
1523 bias-disable; /* NO PULL */
1524 };
1525 };
1526 };
1527
Girish Mahadevan2e2fbe72017-03-28 13:28:18 -06001528 /* QUPv3 South SE mappings */
1529 /* SE 0 pin mappings */
1530 qupv3_se0_i2c_pins: qupv3_se0_i2c_pins {
1531 qupv3_se0_i2c_active: qupv3_se0_i2c_active {
1532 mux {
1533 pins = "gpio0", "gpio1";
1534 function = "qup0";
1535 };
1536
1537 config {
1538 pins = "gpio0", "gpio1";
1539 drive-strength = <2>;
1540 bias-disable;
1541 };
1542 };
1543
1544 qupv3_se0_i2c_sleep: qupv3_se0_i2c_sleep {
1545 mux {
1546 pins = "gpio0", "gpio1";
1547 function = "gpio";
1548 };
1549
1550 config {
1551 pins = "gpio0", "gpio1";
1552 drive-strength = <2>;
1553 bias-pull-up;
1554 };
1555 };
1556 };
1557
1558 qupv3_se0_spi_pins: qupv3_se0_spi_pins {
1559 qupv3_se0_spi_active: qupv3_se0_spi_active {
1560 mux {
1561 pins = "gpio0", "gpio1", "gpio2",
1562 "gpio3";
1563 function = "qup0";
1564 };
1565
1566 config {
1567 pins = "gpio0", "gpio1", "gpio2",
1568 "gpio3";
1569 drive-strength = <6>;
1570 bias-disable;
1571 };
1572 };
1573
1574 qupv3_se0_spi_sleep: qupv3_se0_spi_sleep {
1575 mux {
1576 pins = "gpio0", "gpio1", "gpio2",
1577 "gpio3";
1578 function = "gpio";
1579 };
1580
1581 config {
1582 pins = "gpio0", "gpio1", "gpio2",
1583 "gpio3";
1584 drive-strength = <6>;
1585 bias-disable;
1586 };
1587 };
1588 };
1589
1590 /* SE 1 pin mappings */
1591 qupv3_se1_i2c_pins: qupv3_se1_i2c_pins {
1592 qupv3_se1_i2c_active: qupv3_se1_i2c_active {
1593 mux {
1594 pins = "gpio17", "gpio18";
1595 function = "qup1";
1596 };
1597
1598 config {
1599 pins = "gpio17", "gpio18";
1600 drive-strength = <2>;
1601 bias-disable;
1602 };
1603 };
1604
1605 qupv3_se1_i2c_sleep: qupv3_se1_i2c_sleep {
1606 mux {
1607 pins = "gpio17", "gpio18";
1608 function = "gpio";
1609 };
1610
1611 config {
1612 pins = "gpio17", "gpio18";
1613 drive-strength = <2>;
1614 bias-pull-up;
1615 };
1616 };
1617 };
1618
1619 qupv3_se1_spi_pins: qupv3_se1_spi_pins {
1620 qupv3_se1_spi_active: qupv3_se1_spi_active {
1621 mux {
1622 pins = "gpio17", "gpio18", "gpio19",
1623 "gpio20";
1624 function = "qup1";
1625 };
1626
1627 config {
1628 pins = "gpio17", "gpio18", "gpio19",
1629 "gpio20";
1630 drive-strength = <6>;
1631 bias-disable;
1632 };
1633 };
1634
1635 qupv3_se1_spi_sleep: qupv3_se1_spi_sleep {
1636 mux {
1637 pins = "gpio17", "gpio18", "gpio19",
1638 "gpio20";
1639 function = "gpio";
1640 };
1641
1642 config {
1643 pins = "gpio17", "gpio18", "gpio19",
1644 "gpio20";
1645 drive-strength = <6>;
1646 bias-disable;
1647 };
1648 };
1649 };
1650
1651 /* SE 2 pin mappings */
1652 qupv3_se2_i2c_pins: qupv3_se2_i2c_pins {
1653 qupv3_se2_i2c_active: qupv3_se2_i2c_active {
1654 mux {
1655 pins = "gpio27", "gpio28";
1656 function = "qup2";
1657 };
1658
1659 config {
1660 pins = "gpio27", "gpio28";
1661 drive-strength = <2>;
1662 bias-disable;
1663 };
1664 };
1665
1666 qupv3_se2_i2c_sleep: qupv3_se2_i2c_sleep {
1667 mux {
1668 pins = "gpio27", "gpio28";
1669 function = "gpio";
1670 };
1671
1672 config {
1673 pins = "gpio27", "gpio28";
1674 drive-strength = <2>;
1675 bias-pull-up;
1676 };
1677 };
1678 };
1679
1680 qupv3_se2_spi_pins: qupv3_se2_spi_pins {
1681 qupv3_se2_spi_active: qupv3_se2_spi_active {
1682 mux {
1683 pins = "gpio27", "gpio28", "gpio29",
1684 "gpio30";
1685 function = "qup2";
1686 };
1687
1688 config {
1689 pins = "gpio27", "gpio28", "gpio29",
1690 "gpio30";
1691 drive-strength = <6>;
1692 bias-disable;
1693 };
1694 };
1695
1696 qupv3_se2_spi_sleep: qupv3_se2_spi_sleep {
1697 mux {
1698 pins = "gpio27", "gpio28", "gpio29",
1699 "gpio30";
1700 function = "gpio";
1701 };
1702
1703 config {
1704 pins = "gpio27", "gpio28", "gpio29",
1705 "gpio30";
1706 drive-strength = <6>;
1707 bias-disable;
1708 };
1709 };
1710 };
1711
1712 /* SE 3 pin mappings */
1713 qupv3_se3_i2c_pins: qupv3_se3_i2c_pins {
1714 qupv3_se3_i2c_active: qupv3_se3_i2c_active {
1715 mux {
1716 pins = "gpio41", "gpio42";
1717 function = "qup3";
1718 };
1719
1720 config {
1721 pins = "gpio41", "gpio42";
1722 drive-strength = <2>;
1723 bias-disable;
1724 };
1725 };
1726
1727 qupv3_se3_i2c_sleep: qupv3_se3_i2c_sleep {
1728 mux {
1729 pins = "gpio41", "gpio42";
1730 function = "gpio";
1731 };
1732
1733 config {
1734 pins = "gpio41", "gpio42";
1735 drive-strength = <2>;
1736 bias-pull-up;
1737 };
1738 };
1739 };
1740
Gaurav Singhalf6d253d2017-05-11 08:24:40 +05301741 nfc {
1742 nfc_int_active: nfc_int_active {
1743 /* active state */
1744 mux {
1745 /* GPIO 63 NFC Read Interrupt */
1746 pins = "gpio63";
1747 function = "gpio";
1748 };
1749
1750 config {
1751 pins = "gpio63";
1752 drive-strength = <2>; /* 2 MA */
1753 bias-pull-up;
1754 };
1755 };
1756
1757 nfc_int_suspend: nfc_int_suspend {
1758 /* sleep state */
1759 mux {
1760 /* GPIO 63 NFC Read Interrupt */
1761 pins = "gpio63";
1762 function = "gpio";
1763 };
1764
1765 config {
1766 pins = "gpio63";
1767 drive-strength = <2>; /* 2 MA */
1768 bias-pull-up;
1769 };
1770 };
1771
1772 nfc_enable_active: nfc_enable_active {
1773 /* active state */
1774 mux {
1775 /* 12: NFC ENABLE 116:ESE Enable */
1776 pins = "gpio12", "gpio62", "gpio116";
1777 function = "gpio";
1778 };
1779
1780 config {
1781 pins = "gpio12", "gpio62", "gpio116";
1782 drive-strength = <2>; /* 2 MA */
1783 bias-pull-up;
1784 };
1785 };
1786
1787 nfc_enable_suspend: nfc_enable_suspend {
1788 /* sleep state */
1789 mux {
1790 /* 12: NFC ENABLE 116:ESE Enable */
1791 pins = "gpio12", "gpio62", "gpio116";
1792 function = "gpio";
1793 };
1794
1795 config {
1796 pins = "gpio12", "gpio62", "gpio116";
1797 drive-strength = <2>; /* 2 MA */
1798 bias-disable;
1799 };
1800 };
1801 };
1802
Girish Mahadevan2e2fbe72017-03-28 13:28:18 -06001803 qupv3_se3_spi_pins: qupv3_se3_spi_pins {
1804 qupv3_se3_spi_active: qupv3_se3_spi_active {
1805 mux {
1806 pins = "gpio41", "gpio42", "gpio43",
1807 "gpio44";
1808 function = "qup3";
1809 };
1810
1811 config {
1812 pins = "gpio41", "gpio42", "gpio43",
1813 "gpio44";
1814 drive-strength = <6>;
1815 bias-disable;
1816 };
1817 };
1818
1819 qupv3_se3_spi_sleep: qupv3_se3_spi_sleep {
1820 mux {
1821 pins = "gpio41", "gpio42", "gpio43",
1822 "gpio44";
1823 function = "gpio";
1824 };
1825
1826 config {
1827 pins = "gpio41", "gpio42", "gpio43",
1828 "gpio44";
1829 drive-strength = <6>;
1830 bias-disable;
1831 };
1832 };
1833 };
1834
1835 /* SE 4 pin mappings */
1836 qupv3_se4_i2c_pins: qupv3_se4_i2c_pins {
1837 qupv3_se4_i2c_active: qupv3_se4_i2c_active {
1838 mux {
1839 pins = "gpio89", "gpio90";
1840 function = "qup4";
1841 };
1842
1843 config {
1844 pins = "gpio89", "gpio90";
1845 drive-strength = <2>;
1846 bias-disable;
1847 };
1848 };
1849
1850 qupv3_se4_i2c_sleep: qupv3_se4_i2c_sleep {
1851 mux {
1852 pins = "gpio89", "gpio90";
1853 function = "gpio";
1854 };
1855
1856 config {
1857 pins = "gpio89", "gpio90";
1858 drive-strength = <2>;
1859 bias-pull-up;
1860 };
1861 };
1862 };
1863
1864 qupv3_se4_spi_pins: qupv3_se4_spi_pins {
1865 qupv3_se4_spi_active: qupv3_se4_spi_active {
1866 mux {
1867 pins = "gpio89", "gpio90", "gpio91",
1868 "gpio92";
1869 function = "qup4";
1870 };
1871
1872 config {
1873 pins = "gpio89", "gpio90", "gpio91",
1874 "gpio92";
1875 drive-strength = <6>;
1876 bias-disable;
1877 };
1878 };
1879
1880 qupv3_se4_spi_sleep: qupv3_se4_spi_sleep {
1881 mux {
1882 pins = "gpio89", "gpio90", "gpio91",
1883 "gpio92";
1884 function = "gpio";
1885 };
1886
1887 config {
1888 pins = "gpio89", "gpio90", "gpio91",
1889 "gpio92";
1890 drive-strength = <6>;
1891 bias-disable;
1892 };
1893 };
1894 };
1895
1896 /* SE 5 pin mappings */
1897 qupv3_se5_i2c_pins: qupv3_se5_i2c_pins {
1898 qupv3_se5_i2c_active: qupv3_se5_i2c_active {
1899 mux {
1900 pins = "gpio85", "gpio86";
1901 function = "qup5";
1902 };
1903
1904 config {
1905 pins = "gpio85", "gpio86";
1906 drive-strength = <2>;
1907 bias-disable;
1908 };
1909 };
1910
1911 qupv3_se5_i2c_sleep: qupv3_se5_i2c_sleep {
1912 mux {
1913 pins = "gpio85", "gpio86";
1914 function = "gpio";
1915 };
1916
1917 config {
1918 pins = "gpio85", "gpio86";
1919 drive-strength = <2>;
1920 bias-pull-up;
1921 };
1922 };
1923 };
1924
1925 qupv3_se5_spi_pins: qupv3_se5_spi_pins {
1926 qupv3_se5_spi_active: qupv3_se5_spi_active {
1927 mux {
1928 pins = "gpio85", "gpio86", "gpio87",
1929 "gpio88";
1930 function = "qup5";
1931 };
1932
1933 config {
1934 pins = "gpio85", "gpio86", "gpio87",
1935 "gpio88";
1936 drive-strength = <6>;
1937 bias-disable;
1938 };
1939 };
1940
1941 qupv3_se5_spi_sleep: qupv3_se5_spi_sleep {
1942 mux {
1943 pins = "gpio85", "gpio86", "gpio87",
1944 "gpio88";
1945 function = "gpio";
1946 };
1947
1948 config {
1949 pins = "gpio85", "gpio86", "gpio87",
1950 "gpio88";
1951 drive-strength = <6>;
1952 bias-disable;
1953 };
1954 };
1955 };
1956
1957 /* SE 6 pin mappings */
1958 qupv3_se6_i2c_pins: qupv3_se6_i2c_pins {
1959 qupv3_se6_i2c_active: qupv3_se6_i2c_active {
1960 mux {
1961 pins = "gpio45", "gpio46";
1962 function = "qup6";
1963 };
1964
1965 config {
1966 pins = "gpio45", "gpio46";
1967 drive-strength = <2>;
1968 bias-disable;
1969 };
1970 };
1971
1972 qupv3_se6_i2c_sleep: qupv3_se6_i2c_sleep {
1973 mux {
1974 pins = "gpio45", "gpio46";
1975 function = "gpio";
1976 };
1977
1978 config {
1979 pins = "gpio45", "gpio46";
1980 drive-strength = <2>;
1981 bias-pull-up;
1982 };
1983 };
1984 };
1985
1986 qupv3_se6_4uart_pins: qupv3_se6_4uart_pins {
1987 qupv3_se6_4uart_active: qupv3_se6_4uart_active {
1988 mux {
1989 pins = "gpio45", "gpio46", "gpio47",
1990 "gpio48";
1991 function = "qup6";
1992 };
1993
1994 config {
1995 pins = "gpio45", "gpio46", "gpio47",
1996 "gpio48";
1997 drive-strength = <2>;
1998 bias-disable;
1999 };
2000 };
2001
2002 qupv3_se6_4uart_sleep: qupv3_se6_4uart_sleep {
2003 mux {
2004 pins = "gpio45", "gpio46", "gpio47",
2005 "gpio48";
2006 function = "gpio";
2007 };
2008
2009 config {
2010 pins = "gpio45", "gpio46", "gpio47",
2011 "gpio48";
2012 drive-strength = <2>;
2013 bias-disable;
2014 };
2015 };
2016 };
2017
2018 qupv3_se6_spi_pins: qupv3_se6_spi_pins {
2019 qupv3_se6_spi_active: qupv3_se6_spi_active {
2020 mux {
2021 pins = "gpio45", "gpio46", "gpio47",
2022 "gpio48";
2023 function = "qup6";
2024 };
2025
2026 config {
2027 pins = "gpio45", "gpio46", "gpio47",
2028 "gpio48";
2029 drive-strength = <6>;
2030 bias-disable;
2031 };
2032 };
2033
2034 qupv3_se6_spi_sleep: qupv3_se6_spi_sleep {
2035 mux {
2036 pins = "gpio45", "gpio46", "gpio47",
2037 "gpio48";
2038 function = "gpio";
2039 };
2040
2041 config {
2042 pins = "gpio45", "gpio46", "gpio47",
2043 "gpio48";
2044 drive-strength = <6>;
2045 bias-disable;
2046 };
2047 };
2048 };
2049
2050 /* SE 7 pin mappings */
2051 qupv3_se7_i2c_pins: qupv3_se7_i2c_pins {
2052 qupv3_se7_i2c_active: qupv3_se7_i2c_active {
2053 mux {
2054 pins = "gpio93", "gpio94";
2055 function = "qup7";
2056 };
2057
2058 config {
2059 pins = "gpio93", "gpio94";
2060 drive-strength = <2>;
2061 bias-disable;
2062 };
2063 };
2064
2065 qupv3_se7_i2c_sleep: qupv3_se7_i2c_sleep {
2066 mux {
2067 pins = "gpio93", "gpio94";
2068 function = "gpio";
2069 };
2070
2071 config {
2072 pins = "gpio93", "gpio94";
2073 drive-strength = <2>;
2074 bias-pull-up;
2075 };
2076 };
2077 };
2078
2079 qupv3_se7_4uart_pins: qupv3_se7_4uart_pins {
2080 qupv3_se7_4uart_active: qupv3_se7_4uart_active {
2081 mux {
2082 pins = "gpio93", "gpio94", "gpio95",
2083 "gpio96";
2084 function = "qup7";
2085 };
2086
2087 config {
2088 pins = "gpio93", "gpio94", "gpio95",
2089 "gpio96";
2090 drive-strength = <2>;
2091 bias-disable;
2092 };
2093 };
2094
2095 qupv3_se7_4uart_sleep: qupv3_se7_4uart_sleep {
2096 mux {
2097 pins = "gpio93", "gpio94", "gpio95",
2098 "gpio96";
2099 function = "gpio";
2100 };
2101
2102 config {
2103 pins = "gpio93", "gpio94", "gpio95",
2104 "gpio96";
2105 drive-strength = <2>;
2106 bias-disable;
2107 };
2108 };
2109 };
2110
2111 qupv3_se7_spi_pins: qupv3_se7_spi_pins {
2112 qupv3_se7_spi_active: qupv3_se7_spi_active {
2113 mux {
2114 pins = "gpio93", "gpio94", "gpio95",
2115 "gpio96";
2116 function = "qup7";
2117 };
2118
2119 config {
2120 pins = "gpio93", "gpio94", "gpio95",
2121 "gpio96";
2122 drive-strength = <6>;
2123 bias-disable;
2124 };
2125 };
2126
2127 qupv3_se7_spi_sleep: qupv3_se7_spi_sleep {
2128 mux {
2129 pins = "gpio93", "gpio94", "gpio95",
2130 "gpio96";
2131 function = "gpio";
2132 };
2133
2134 config {
2135 pins = "gpio93", "gpio94", "gpio95",
2136 "gpio96";
2137 drive-strength = <6>;
2138 bias-disable;
2139 };
2140 };
2141 };
2142
2143 /* QUPv3 North instances */
2144 /* SE 8 pin mappings */
2145 qupv3_se8_i2c_pins: qupv3_se8_i2c_pins {
2146 qupv3_se8_i2c_active: qupv3_se8_i2c_active {
2147 mux {
2148 pins = "gpio65", "gpio66";
2149 function = "qup8";
2150 };
2151
2152 config {
2153 pins = "gpio65", "gpio66";
2154 drive-strength = <2>;
2155 bias-disable;
2156 };
2157 };
2158
2159 qupv3_se8_i2c_sleep: qupv3_se8_i2c_sleep {
2160 mux {
2161 pins = "gpio65", "gpio66";
2162 function = "gpio";
2163 };
2164
2165 config {
2166 pins = "gpio65", "gpio66";
2167 drive-strength = <2>;
2168 bias-pull-up;
2169 };
2170 };
2171 };
2172
2173 qupv3_se8_spi_pins: qupv3_se8_spi_pins {
2174 qupv3_se8_spi_active: qupv3_se8_spi_active {
2175 mux {
2176 pins = "gpio65", "gpio66", "gpio67",
2177 "gpio68";
2178 function = "qup8";
2179 };
2180
2181 config {
2182 pins = "gpio65", "gpio66", "gpio67",
2183 "gpio68";
2184 drive-strength = <6>;
2185 bias-disable;
2186 };
2187 };
2188
2189 qupv3_se8_spi_sleep: qupv3_se8_spi_sleep {
2190 mux {
2191 pins = "gpio65", "gpio66", "gpio67",
2192 "gpio68";
2193 function = "gpio";
2194 };
2195
2196 config {
2197 pins = "gpio65", "gpio66", "gpio67",
2198 "gpio68";
2199 drive-strength = <6>;
2200 bias-disable;
2201 };
2202 };
2203 };
2204
2205 /* SE 9 pin mappings */
2206 qupv3_se9_i2c_pins: qupv3_se9_i2c_pins {
2207 qupv3_se9_i2c_active: qupv3_se9_i2c_active {
2208 mux {
2209 pins = "gpio6", "gpio7";
2210 function = "qup9";
2211 };
2212
2213 config {
2214 pins = "gpio6", "gpio7";
2215 drive-strength = <2>;
2216 bias-disable;
2217 };
2218 };
2219
2220 qupv3_se9_i2c_sleep: qupv3_se9_i2c_sleep {
2221 mux {
2222 pins = "gpio6", "gpio7";
2223 function = "gpio";
2224 };
2225
2226 config {
2227 pins = "gpio6", "gpio7";
2228 drive-strength = <2>;
2229 bias-pull-up;
2230 };
2231 };
2232 };
2233
2234 qupv3_se9_2uart_pins: qupv3_se9_2uart_pins {
2235 qupv3_se9_2uart_active: qupv3_se9_2uart_active {
2236 mux {
2237 pins = "gpio4", "gpio5";
2238 function = "qup9";
2239 };
2240
2241 config {
2242 pins = "gpio4", "gpio5";
2243 drive-strength = <2>;
2244 bias-disable;
2245 };
2246 };
2247
2248 qupv3_se9_2uart_sleep: qupv3_se9_2uart_sleep {
2249 mux {
2250 pins = "gpio4", "gpio5";
2251 function = "gpio";
2252 };
2253
2254 config {
2255 pins = "gpio4", "gpio5";
2256 drive-strength = <2>;
2257 bias-disable;
2258 };
2259 };
2260 };
2261
2262 qupv3_se9_spi_pins: qupv3_se9_spi_pins {
2263 qupv3_se9_spi_active: qupv3_se9_spi_active {
2264 mux {
2265 pins = "gpio4", "gpio5", "gpio6",
2266 "gpio7";
2267 function = "qup9";
2268 };
2269
2270 config {
2271 pins = "gpio4", "gpio5", "gpio6",
2272 "gpio7";
2273 drive-strength = <6>;
2274 bias-disable;
2275 };
2276 };
2277
2278 qupv3_se9_spi_sleep: qupv3_se9_spi_sleep {
2279 mux {
2280 pins = "gpio4", "gpio5", "gpio6",
2281 "gpio7";
2282 function = "gpio";
2283 };
2284
2285 config {
2286 pins = "gpio4", "gpio5", "gpio6",
2287 "gpio7";
2288 drive-strength = <6>;
2289 bias-disable;
2290 };
2291 };
2292 };
2293
2294 /* SE 10 pin mappings */
2295 qupv3_se10_i2c_pins: qupv3_se10_i2c_pins {
2296 qupv3_se10_i2c_active: qupv3_se10_i2c_active {
2297 mux {
2298 pins = "gpio55", "gpio56";
2299 function = "qup10";
2300 };
2301
2302 config {
2303 pins = "gpio55", "gpio56";
2304 drive-strength = <2>;
2305 bias-disable;
2306 };
2307 };
2308
2309 qupv3_se10_i2c_sleep: qupv3_se10_i2c_sleep {
2310 mux {
2311 pins = "gpio55", "gpio56";
2312 function = "gpio";
2313 };
2314
2315 config {
2316 pins = "gpio55", "gpio56";
2317 drive-strength = <2>;
2318 bias-pull-up;
2319 };
2320 };
2321 };
2322
2323 qupv3_se10_2uart_pins: qupv3_se10_2uart_pins {
2324 qupv3_se10_2uart_active: qupv3_se10_2uart_active {
2325 mux {
2326 pins = "gpio53", "gpio54";
2327 function = "qup10";
2328 };
2329
2330 config {
2331 pins = "gpio53", "gpio54";
2332 drive-strength = <2>;
2333 bias-disable;
2334 };
2335 };
2336
2337 qupv3_se10_2uart_sleep: qupv3_se10_2uart_sleep {
2338 mux {
2339 pins = "gpio53", "gpio54";
2340 function = "gpio";
2341 };
2342
2343 config {
2344 pins = "gpio53", "gpio54";
2345 drive-strength = <2>;
2346 bias-disable;
2347 };
2348 };
2349 };
2350
2351 qupv3_se10_spi_pins: qupv3_se10_spi_pins {
2352 qupv3_se10_spi_active: qupv3_se10_spi_active {
2353 mux {
2354 pins = "gpio53", "gpio54", "gpio55",
2355 "gpio56";
2356 function = "qup10";
2357 };
2358
2359 config {
2360 pins = "gpio53", "gpio54", "gpio55",
2361 "gpio56";
2362 drive-strength = <6>;
2363 bias-disable;
2364 };
2365 };
2366
2367 qupv3_se10_spi_sleep: qupv3_se10_spi_sleep {
2368 mux {
2369 pins = "gpio53", "gpio54", "gpio55",
2370 "gpio56";
2371 function = "gpio";
2372 };
2373
2374 config {
2375 pins = "gpio53", "gpio54", "gpio55",
2376 "gpio56";
2377 drive-strength = <6>;
2378 bias-disable;
2379 };
2380 };
2381 };
2382
2383 /* SE 11 pin mappings */
2384 qupv3_se11_i2c_pins: qupv3_se11_i2c_pins {
2385 qupv3_se11_i2c_active: qupv3_se11_i2c_active {
2386 mux {
2387 pins = "gpio31", "gpio32";
2388 function = "qup11";
2389 };
2390
2391 config {
2392 pins = "gpio31", "gpio32";
2393 drive-strength = <2>;
2394 bias-disable;
2395 };
2396 };
2397
2398 qupv3_se11_i2c_sleep: qupv3_se11_i2c_sleep {
2399 mux {
2400 pins = "gpio31", "gpio32";
2401 function = "gpio";
2402 };
2403
2404 config {
2405 pins = "gpio31", "gpio32";
2406 drive-strength = <2>;
2407 bias-pull-up;
2408 };
2409 };
2410 };
2411
2412 qupv3_se11_spi_pins: qupv3_se11_spi_pins {
2413 qupv3_se11_spi_active: qupv3_se11_spi_active {
2414 mux {
2415 pins = "gpio31", "gpio32", "gpio33",
2416 "gpio34";
2417 function = "qup11";
2418 };
2419
2420 config {
2421 pins = "gpio31", "gpio32", "gpio33",
2422 "gpio34";
2423 drive-strength = <6>;
2424 bias-disable;
2425 };
2426 };
2427
2428 qupv3_se11_spi_sleep: qupv3_se11_spi_sleep {
2429 mux {
2430 pins = "gpio31", "gpio32", "gpio33",
2431 "gpio34";
2432 function = "gpio";
2433 };
2434
2435 config {
2436 pins = "gpio31", "gpio32", "gpio33",
2437 "gpio34";
2438 drive-strength = <6>;
2439 bias-disable;
2440 };
2441 };
2442 };
2443
2444 /* SE 12 pin mappings */
2445 qupv3_se12_i2c_pins: qupv3_se12_i2c_pins {
2446 qupv3_se12_i2c_active: qupv3_se12_i2c_active {
2447 mux {
2448 pins = "gpio49", "gpio50";
2449 function = "qup12";
2450 };
2451
2452 config {
2453 pins = "gpio49", "gpio50";
2454 drive-strength = <2>;
2455 bias-disable;
2456 };
2457 };
2458
2459 qupv3_se12_i2c_sleep: qupv3_se12_i2c_sleep {
2460 mux {
2461 pins = "gpio49", "gpio50";
2462 function = "gpio";
2463 };
2464
2465 config {
2466 pins = "gpio49", "gpio50";
2467 drive-strength = <2>;
2468 bias-pull-up;
2469 };
2470 };
2471 };
2472
2473 qupv3_se12_spi_pins: qupv3_se12_spi_pins {
2474 qupv3_se12_spi_active: qupv3_se12_spi_active {
2475 mux {
2476 pins = "gpio49", "gpio50", "gpio51",
2477 "gpio52";
2478 function = "qup12";
2479 };
2480
2481 config {
2482 pins = "gpio49", "gpio50", "gpio51",
2483 "gpio52";
2484 drive-strength = <6>;
2485 bias-disable;
2486 };
2487 };
2488
2489 qupv3_se12_spi_sleep: qupv3_se12_spi_sleep {
2490 mux {
2491 pins = "gpio49", "gpio50", "gpio51",
2492 "gpio52";
2493 function = "gpio";
2494 };
2495
2496 config {
2497 pins = "gpio49", "gpio50", "gpio51",
2498 "gpio52";
2499 drive-strength = <6>;
2500 bias-disable;
2501 };
2502 };
2503 };
2504
2505 /* SE 13 pin mappings */
2506 qupv3_se13_i2c_pins: qupv3_se13_i2c_pins {
2507 qupv3_se13_i2c_active: qupv3_se13_i2c_active {
2508 mux {
2509 pins = "gpio105", "gpio106";
2510 function = "qup13";
2511 };
2512
2513 config {
2514 pins = "gpio105", "gpio106";
2515 drive-strength = <2>;
2516 bias-disable;
2517 };
2518 };
2519
2520 qupv3_se13_i2c_sleep: qupv3_se13_i2c_sleep {
2521 mux {
2522 pins = "gpio105", "gpio106";
2523 function = "gpio";
2524 };
2525
2526 config {
2527 pins = "gpio105", "gpio106";
2528 drive-strength = <2>;
2529 bias-pull-up;
2530 };
2531 };
2532 };
2533
2534 qupv3_se13_spi_pins: qupv3_se13_spi_pins {
2535 qupv3_se13_spi_active: qupv3_se13_spi_active {
2536 mux {
2537 pins = "gpio105", "gpio106", "gpio107",
2538 "gpio108";
2539 function = "qup13";
2540 };
2541
2542 config {
2543 pins = "gpio105", "gpio106", "gpio107",
2544 "gpio108";
2545 drive-strength = <6>;
2546 bias-disable;
2547 };
2548 };
2549
2550 qupv3_se13_spi_sleep: qupv3_se13_spi_sleep {
2551 mux {
2552 pins = "gpio105", "gpio106", "gpio107",
2553 "gpio108";
2554 function = "gpio";
2555 };
2556
2557 config {
2558 pins = "gpio105", "gpio106", "gpio107",
2559 "gpio108";
2560 drive-strength = <6>;
2561 bias-disable;
2562 };
2563 };
2564 };
2565
2566 /* SE 14 pin mappings */
2567 qupv3_se14_i2c_pins: qupv3_se14_i2c_pins {
2568 qupv3_se14_i2c_active: qupv3_se14_i2c_active {
2569 mux {
2570 pins = "gpio33", "gpio34";
2571 function = "qup14";
2572 };
2573
2574 config {
2575 pins = "gpio33", "gpio34";
2576 drive-strength = <2>;
2577 bias-disable;
2578 };
2579 };
2580
2581 qupv3_se14_i2c_sleep: qupv3_se14_i2c_sleep {
2582 mux {
2583 pins = "gpio33", "gpio34";
2584 function = "gpio";
2585 };
2586
2587 config {
2588 pins = "gpio33", "gpio34";
2589 drive-strength = <2>;
2590 bias-pull-up;
2591 };
2592 };
2593 };
2594
2595 qupv3_se14_spi_pins: qupv3_se14_spi_pins {
2596 qupv3_se14_spi_active: qupv3_se14_spi_active {
2597 mux {
2598 pins = "gpio31", "gpio32", "gpio33",
2599 "gpio34";
2600 function = "qup14";
2601 };
2602
2603 config {
2604 pins = "gpio31", "gpio32", "gpio33",
2605 "gpio34";
2606 drive-strength = <6>;
2607 bias-disable;
2608 };
2609 };
2610
2611 qupv3_se14_spi_sleep: qupv3_se14_spi_sleep {
2612 mux {
2613 pins = "gpio31", "gpio32", "gpio33",
2614 "gpio34";
2615 function = "gpio";
2616 };
2617
2618 config {
2619 pins = "gpio31", "gpio32", "gpio33",
2620 "gpio34";
2621 drive-strength = <6>;
2622 bias-disable;
2623 };
2624 };
2625 };
2626
2627 /* SE 15 pin mappings */
2628 qupv3_se15_i2c_pins: qupv3_se15_i2c_pins {
2629 qupv3_se15_i2c_active: qupv3_se15_i2c_active {
2630 mux {
2631 pins = "gpio81", "gpio82";
2632 function = "qup15";
2633 };
2634
2635 config {
2636 pins = "gpio81", "gpio82";
2637 drive-strength = <2>;
2638 bias-disable;
2639 };
2640 };
2641
2642 qupv3_se15_i2c_sleep: qupv3_se15_i2c_sleep {
2643 mux {
2644 pins = "gpio81", "gpio82";
2645 function = "gpio";
2646 };
2647
2648 config {
2649 pins = "gpio81", "gpio82";
2650 drive-strength = <2>;
2651 bias-pull-up;
2652 };
2653 };
2654 };
2655
2656 qupv3_se15_spi_pins: qupv3_se15_spi_pins {
2657 qupv3_se15_spi_active: qupv3_se15_spi_active {
2658 mux {
2659 pins = "gpio81", "gpio82", "gpio83",
2660 "gpio84";
2661 function = "qup15";
2662 };
2663
2664 config {
2665 pins = "gpio81", "gpio82", "gpio83",
2666 "gpio84";
2667 drive-strength = <6>;
2668 bias-disable;
2669 };
2670 };
2671
2672 qupv3_se15_spi_sleep: qupv3_se15_spi_sleep {
2673 mux {
2674 pins = "gpio81", "gpio82", "gpio83",
2675 "gpio84";
2676 function = "gpio";
2677 };
2678
2679 config {
2680 pins = "gpio81", "gpio82", "gpio83",
2681 "gpio84";
2682 drive-strength = <6>;
2683 bias-disable;
2684 };
2685 };
2686 };
Jigarkumar Zala861231152017-02-28 14:05:11 -08002687
2688 cci0_active: cci0_active {
2689 mux {
2690 /* CLK, DATA */
2691 pins = "gpio17","gpio18"; // Only 2
2692 function = "cci_i2c";
2693 };
2694
2695 config {
2696 pins = "gpio17","gpio18";
2697 bias-pull-up; /* PULL UP*/
2698 drive-strength = <2>; /* 2 MA */
2699 };
2700 };
2701
2702 cci0_suspend: cci0_suspend {
2703 mux {
2704 /* CLK, DATA */
2705 pins = "gpio17","gpio18";
2706 function = "cci_i2c";
2707 };
2708
2709 config {
2710 pins = "gpio17","gpio18";
2711 bias-pull-down; /* PULL DOWN */
2712 drive-strength = <2>; /* 2 MA */
2713 };
2714 };
2715
2716 cci1_active: cci1_active {
2717 mux {
2718 /* CLK, DATA */
2719 pins = "gpio19","gpio20";
2720 function = "cci_i2c";
2721 };
2722
2723 config {
2724 pins = "gpio19","gpio20";
2725 bias-pull-up; /* PULL UP*/
2726 drive-strength = <2>; /* 2 MA */
2727 };
2728 };
2729
2730 cci1_suspend: cci1_suspend {
2731 mux {
2732 /* CLK, DATA */
2733 pins = "gpio19","gpio20";
2734 function = "cci_i2c";
2735 };
2736
2737 config {
2738 pins = "gpio19","gpio20";
2739 bias-pull-down; /* PULL DOWN */
2740 drive-strength = <2>; /* 2 MA */
2741 };
2742 };
2743
2744 cam_sensor_mclk0_active: cam_sensor_mclk0_active {
2745 /* MCLK0 */
2746 mux {
2747 pins = "gpio13";
2748 function = "cam_mclk";
2749 };
2750
2751 config {
2752 pins = "gpio13";
2753 bias-disable; /* No PULL */
2754 drive-strength = <2>; /* 2 MA */
2755 };
2756 };
2757
2758 cam_sensor_mclk0_suspend: cam_sensor_mclk0_suspend {
2759 /* MCLK0 */
2760 mux {
2761 pins = "gpio13";
2762 function = "cam_mclk";
2763 };
2764
2765 config {
2766 pins = "gpio13";
2767 bias-pull-down; /* PULL DOWN */
2768 drive-strength = <2>; /* 2 MA */
2769 };
2770 };
2771
2772 cam_sensor_rear_active: cam_sensor_rear_active {
2773 /* RESET, AVDD LDO */
2774 mux {
2775 pins = "gpio80","gpio79";
2776 function = "gpio";
2777 };
2778
2779 config {
2780 pins = "gpio80","gpio79";
2781 bias-disable; /* No PULL */
2782 drive-strength = <2>; /* 2 MA */
2783 };
2784 };
2785
2786 cam_sensor_rear_suspend: cam_sensor_rear_suspend {
2787 /* RESET, AVDD LDO */
2788 mux {
2789 pins = "gpio80","gpio79";
2790 function = "gpio";
2791 };
2792
2793 config {
2794 pins = "gpio80","gpio79";
Jeyaprakash Soundrapandian902116a2017-07-20 18:17:59 -07002795 bias-pull-down; /* PULL DOWN */
Jigarkumar Zala861231152017-02-28 14:05:11 -08002796 drive-strength = <2>; /* 2 MA */
Karthik Anantha Rame87f1ee2017-08-24 14:05:36 -07002797 output-low;
Jigarkumar Zala861231152017-02-28 14:05:11 -08002798 };
2799 };
2800
2801 cam_sensor_mclk1_active: cam_sensor_mclk1_active {
2802 /* MCLK1 */
2803 mux {
2804 pins = "gpio14";
2805 function = "cam_mclk";
2806 };
2807
2808 config {
2809 pins = "gpio14";
2810 bias-disable; /* No PULL */
2811 drive-strength = <2>; /* 2 MA */
2812 };
2813 };
2814
2815 cam_sensor_mclk1_suspend: cam_sensor_mclk1_suspend {
2816 /* MCLK1 */
2817 mux {
2818 pins = "gpio14";
2819 function = "cam_mclk";
2820 };
2821
2822 config {
2823 pins = "gpio14";
2824 bias-pull-down; /* PULL DOWN */
2825 drive-strength = <2>; /* 2 MA */
2826 };
2827 };
2828
Jigarkumar Zala9e214912017-09-14 16:40:03 -07002829 cam_sensor_mclk3_active: cam_sensor_mclk3_active {
2830 /* MCLK3 */
2831 mux {
2832 pins = "gpio16";
2833 function = "cam_mclk";
2834 };
2835
2836 config {
2837 pins = "gpio16";
2838 bias-disable; /* No PULL */
2839 drive-strength = <2>; /* 2 MA */
2840 };
2841 };
2842
2843 cam_sensor_mclk3_suspend: cam_sensor_mclk3_suspend {
2844 /* MCLK3 */
2845 mux {
2846 pins = "gpio16";
2847 function = "cam_mclk";
2848 };
2849
2850 config {
2851 pins = "gpio16";
2852 bias-pull-down; /* PULL DOWN */
2853 drive-strength = <2>; /* 2 MA */
2854 };
2855 };
2856
2857
Jigarkumar Zala861231152017-02-28 14:05:11 -08002858 cam_sensor_front_active: cam_sensor_front_active {
2859 /* RESET AVDD_LDO*/
2860 mux {
2861 pins = "gpio28", "gpio8";
2862 function = "gpio";
2863 };
2864
2865 config {
2866 pins = "gpio28", "gpio8";
2867 bias-disable; /* No PULL */
2868 drive-strength = <2>; /* 2 MA */
2869 };
2870 };
2871
2872 cam_sensor_front_suspend: cam_sensor_front_suspend {
2873 /* RESET */
2874 mux {
2875 pins = "gpio28";
2876 function = "gpio";
2877 };
2878
2879 config {
2880 pins = "gpio28";
Jeyaprakash Soundrapandian902116a2017-07-20 18:17:59 -07002881 bias-pull-down; /* PULL DOWN */
Jigarkumar Zala861231152017-02-28 14:05:11 -08002882 drive-strength = <2>; /* 2 MA */
Karthik Anantha Rame87f1ee2017-08-24 14:05:36 -07002883 output-low;
Jigarkumar Zala861231152017-02-28 14:05:11 -08002884 };
2885 };
2886
Jigarkumar Zala9e214912017-09-14 16:40:03 -07002887 cam_sensor_iris_active: cam_sensor_iris_active {
2888 /* RESET AVDD_LDO*/
2889 mux {
2890 pins = "gpio9", "gpio8";
2891 function = "gpio";
2892 };
2893
2894 config {
2895 pins = "gpio9", "gpio8";
2896 bias-disable; /* No PULL */
2897 drive-strength = <2>; /* 2 MA */
2898 };
2899 };
2900
2901 cam_sensor_iris_suspend: cam_sensor_iris_suspend {
2902 /* RESET */
2903 mux {
2904 pins = "gpio9";
2905 function = "gpio";
2906 };
2907
2908 config {
2909 pins = "gpio9";
2910 bias-disable; /* No PULL */
2911 drive-strength = <2>; /* 2 MA */
2912 output-low;
2913 };
2914 };
2915
2916
Jigarkumar Zala861231152017-02-28 14:05:11 -08002917 cam_sensor_mclk2_active: cam_sensor_mclk2_active {
2918 /* MCLK1 */
2919 mux {
2920 /* CLK, DATA */
2921 pins = "gpio15";
2922 function = "cam_mclk";
2923 };
2924
2925 config {
2926 pins = "gpio15";
2927 bias-disable; /* No PULL */
2928 drive-strength = <2>; /* 2 MA */
2929 };
2930 };
2931
2932 cam_sensor_mclk2_suspend: cam_sensor_mclk2_suspend {
2933 /* MCLK1 */
2934 mux {
2935 /* CLK, DATA */
2936 pins = "gpio15";
2937 function = "cam_mclk";
2938 };
2939
2940 config {
2941 pins = "gpio15";
2942 bias-pull-down; /* PULL DOWN */
2943 drive-strength = <2>; /* 2 MA */
2944 };
2945 };
2946
2947 cam_sensor_rear2_active: cam_sensor_rear2_active {
2948 /* RESET, STANDBY */
2949 mux {
2950 pins = "gpio9","gpio8";
2951 function = "gpio";
2952 };
2953
2954 config {
2955 pins = "gpio9","gpio8";
2956 bias-disable; /* No PULL */
2957 drive-strength = <2>; /* 2 MA */
2958 };
2959 };
2960
2961 cam_sensor_rear2_suspend: cam_sensor_rear2_suspend {
2962 /* RESET, STANDBY */
2963 mux {
2964 pins = "gpio9","gpio8";
2965 function = "gpio";
2966 };
2967 config {
2968 pins = "gpio9","gpio8";
Jeyaprakash Soundrapandian902116a2017-07-20 18:17:59 -07002969 bias-pull-down; /* PULL DOWN */
Jigarkumar Zala861231152017-02-28 14:05:11 -08002970 drive-strength = <2>; /* 2 MA */
Karthik Anantha Rame87f1ee2017-08-24 14:05:36 -07002971 output-low;
Jigarkumar Zala861231152017-02-28 14:05:11 -08002972 };
2973 };
Satyajit Desaie4508132017-04-05 17:15:22 -07002974
2975 trigout_a: trigout_a {
2976 mux {
Satyajit Desai602a6712017-05-09 14:45:16 -07002977 pins = "gpio90";
Satyajit Desaie4508132017-04-05 17:15:22 -07002978 function = "qdss_cti";
2979 };
2980 config {
Satyajit Desai602a6712017-05-09 14:45:16 -07002981 pins = "gpio90";
Satyajit Desaie4508132017-04-05 17:15:22 -07002982 drive-strength = <2>;
2983 bias-disable;
2984 };
2985 };
Udaya Bhaskara Reddy Mallavarapu55ef0cb2017-06-12 14:45:28 +05302986
2987 tsif0_signals_active: tsif0_signals_active {
2988 tsif1_clk {
2989 pins = "gpio89"; /* TSIF0 CLK */
2990 function = "tsif1_clk";
2991 };
2992 tsif1_en {
2993 pins = "gpio90"; /* TSIF0 Enable */
2994 function = "tsif1_en";
2995 };
2996 tsif1_data {
2997 pins = "gpio91"; /* TSIF0 DATA */
2998 function = "tsif1_data";
2999 };
3000 signals_cfg {
3001 pins = "gpio89", "gpio90", "gpio91";
3002 drive_strength = <2>; /* 2 mA */
3003 bias-pull-down; /* pull down */
3004 };
3005 };
3006
3007 /* sync signal is only used if configured to mode-2 */
3008 tsif0_sync_active: tsif0_sync_active {
3009 tsif1_sync {
3010 pins = "gpio12"; /* TSIF0 SYNC */
3011 function = "tsif1_sync";
3012 drive_strength = <2>; /* 2 mA */
3013 bias-pull-down; /* pull down */
3014 };
3015 };
3016
3017 tsif1_signals_active: tsif1_signals_active {
3018 tsif2_clk {
3019 pins = "gpio93"; /* TSIF1 CLK */
3020 function = "tsif2_clk";
3021 };
3022 tsif2_en {
3023 pins = "gpio94"; /* TSIF1 Enable */
3024 function = "tsif2_en";
3025 };
3026 tsif2_data {
3027 pins = "gpio95"; /* TSIF1 DATA */
3028 function = "tsif2_data";
3029 };
3030 signals_cfg {
3031 pins = "gpio93", "gpio94", "gpio95";
3032 drive_strength = <2>; /* 2 mA */
3033 bias-pull-down; /* pull down */
3034 };
3035 };
3036
3037 /* sync signal is only used if configured to mode-2 */
3038 tsif1_sync_active: tsif1_sync_active {
3039 tsif2_sync {
3040 pins = "gpio96"; /* TSIF1 SYNC */
3041 function = "tsif2_sync";
3042 drive_strength = <2>; /* 2 mA */
3043 bias-pull-down; /* pull down */
3044 };
3045 };
Kyle Yan679cbee2016-07-27 16:55:20 -07003046 };
3047};
David Collinsc6686252017-03-31 14:23:09 -07003048
3049&pm8998_gpios {
3050 key_home {
3051 key_home_default: key_home_default {
3052 pins = "gpio5";
3053 function = "normal";
3054 input-enable;
3055 bias-pull-up;
3056 power-source = <0>;
3057 };
3058 };
3059
3060 key_vol_up {
3061 key_vol_up_default: key_vol_up_default {
3062 pins = "gpio6";
3063 function = "normal";
3064 input-enable;
3065 bias-pull-up;
3066 power-source = <0>;
3067 };
3068 };
3069
3070 key_cam_snapshot {
3071 key_cam_snapshot_default: key_cam_snapshot_default {
3072 pins = "gpio7";
3073 function = "normal";
3074 input-enable;
3075 bias-pull-up;
3076 power-source = <0>;
3077 };
3078 };
3079
3080 key_cam_focus {
3081 key_cam_focus_default: key_cam_focus_default {
3082 pins = "gpio8";
3083 function = "normal";
3084 input-enable;
3085 bias-pull-up;
3086 power-source = <0>;
3087 };
3088 };
Jigarkumar Zala861231152017-02-28 14:05:11 -08003089
3090 camera_dvdd_en {
3091 camera_dvdd_en_default: camera_dvdd_en_default {
3092 pins = "gpio9";
3093 function = "normal";
3094 power-source = <0>;
3095 output-low;
3096 };
3097 };
3098
3099 camera_rear_dvdd_en {
3100 camera_rear_dvdd_en_default: camera_rear_dvdd_en_default {
3101 pins = "gpio12";
3102 function = "normal";
3103 power-source = <0>;
3104 output-low;
3105 };
3106 };
Gaurav Singhal243b94b2017-06-20 14:16:59 +05303107
3108 nfc_clk {
3109 nfc_clk_default: nfc_clk_default {
3110 pins = "gpio21";
3111 function = "normal";
3112 input-enable;
3113 power-source = <1>;
3114 };
3115 };
David Collinsc6686252017-03-31 14:23:09 -07003116};