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Banajit Goswamib016de92017-02-15 21:02:30 -08001/* Copyright (c) 2016-2017, The Linux Foundation. All rights reserved.
Kyle Yan679cbee2016-07-27 16:55:20 -07002 *
3 * This program is free software; you can redistribute it and/or modify
4 * it under the terms of the GNU General Public License version 2 and
5 * only version 2 as published by the Free Software Foundation.
6 *
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
11 */
12
13&soc {
Channagoud Kadabieb7f0112017-04-03 20:39:27 -070014 tlmm: pinctrl@03400000 {
Kyle Yan6a20fae2017-02-14 13:34:41 -080015 compatible = "qcom,sdm845-pinctrl";
Channagoud Kadabieb7f0112017-04-03 20:39:27 -070016 reg = <0x03400000 0xc00000>;
Kyle Yan679cbee2016-07-27 16:55:20 -070017 interrupts = <0 208 0>;
18 gpio-controller;
19 #gpio-cells = <2>;
20 interrupt-controller;
21 #interrupt-cells = <2>;
Banajit Goswamib016de92017-02-15 21:02:30 -080022
Subhash Jadavaniafe2a792017-03-31 21:08:29 -070023 ufs_dev_reset_assert: ufs_dev_reset_assert {
24 config {
25 pins = "ufs_reset";
26 bias-pull-down; /* default: pull down */
27 /*
28 * UFS_RESET driver strengths are having
29 * different values/steps compared to typical
30 * GPIO drive strengths.
31 *
32 * Following table clarifies:
33 *
34 * HDRV value | UFS_RESET | Typical GPIO
35 * (dec) | (mA) | (mA)
36 * 0 | 0.8 | 2
37 * 1 | 1.55 | 4
38 * 2 | 2.35 | 6
39 * 3 | 3.1 | 8
40 * 4 | 3.9 | 10
41 * 5 | 4.65 | 12
42 * 6 | 5.4 | 14
43 * 7 | 6.15 | 16
44 *
45 * POR value for UFS_RESET HDRV is 3 which means
46 * 3.1mA and we want to use that. Hence just
47 * specify 8mA to "drive-strength" binding and
48 * that should result into writing 3 to HDRV
49 * field.
50 */
51 drive-strength = <8>; /* default: 3.1 mA */
52 output-low; /* active low reset */
53 };
54 };
55
56 ufs_dev_reset_deassert: ufs_dev_reset_deassert {
57 config {
58 pins = "ufs_reset";
59 bias-pull-down; /* default: pull down */
60 /*
61 * default: 3.1 mA
62 * check comments under ufs_dev_reset_assert
63 */
64 drive-strength = <8>;
65 output-high; /* active low reset */
66 };
67 };
68
Subbaraman Narayanamurthycd21c812017-03-30 18:36:49 -070069 flash_led3_front {
70 flash_led3_front_en: flash_led3_front_en {
71 mux {
72 pins = "gpio21";
Subbaraman Narayanamurthy58377f02017-03-21 20:38:43 -070073 function = "gpio";
74 };
75
76 config {
77 pins = "gpio21";
Subbaraman Narayanamurthycd21c812017-03-30 18:36:49 -070078 drive_strength = <2>;
79 output-high;
Subbaraman Narayanamurthy58377f02017-03-21 20:38:43 -070080 bias-disable;
Subbaraman Narayanamurthycd21c812017-03-30 18:36:49 -070081 };
82 };
83
84 flash_led3_front_dis: flash_led3_front_dis {
85 mux {
86 pins = "gpio21";
Subbaraman Narayanamurthy58377f02017-03-21 20:38:43 -070087 function = "gpio";
88 };
89
90 config {
91 pins = "gpio21";
Subbaraman Narayanamurthycd21c812017-03-30 18:36:49 -070092 drive_strength = <2>;
93 output-low;
Subbaraman Narayanamurthy58377f02017-03-21 20:38:43 -070094 bias-disable;
Subbaraman Narayanamurthycd21c812017-03-30 18:36:49 -070095 };
96 };
97 };
Subhash Jadavaniafe2a792017-03-31 21:08:29 -070098
Banajit Goswamib016de92017-02-15 21:02:30 -080099 wcd9xxx_intr {
100 wcd_intr_default: wcd_intr_default{
101 mux {
102 pins = "gpio54";
103 function = "gpio";
104 };
105
106 config {
107 pins = "gpio54";
108 drive-strength = <2>; /* 2 mA */
109 bias-pull-down; /* pull down */
110 input-enable;
111 };
112 };
113 };
114
Subhash Jadavanidd416c42017-05-15 11:54:10 -0700115 storage_cd: storage_cd {
116 mux {
117 pins = "gpio126";
118 function = "gpio";
119 };
120
121 config {
122 pins = "gpio126";
123 bias-pull-up; /* pull up */
124 drive-strength = <2>; /* 2 MA */
125 };
126 };
127
Xiaonian Wang898e0902017-04-08 06:46:29 +0800128 sdc2_clk_on: sdc2_clk_on {
129 config {
130 pins = "sdc2_clk";
131 bias-disable; /* NO pull */
132 drive-strength = <16>; /* 16 MA */
133 };
134 };
135
136 sdc2_clk_off: sdc2_clk_off {
137 config {
138 pins = "sdc2_clk";
139 bias-disable; /* NO pull */
140 drive-strength = <2>; /* 2 MA */
141 };
142 };
143
144 sdc2_cmd_on: sdc2_cmd_on {
145 config {
146 pins = "sdc2_cmd";
147 bias-pull-up; /* pull up */
148 drive-strength = <10>; /* 10 MA */
149 };
150 };
151
152 sdc2_cmd_off: sdc2_cmd_off {
153 config {
154 pins = "sdc2_cmd";
155 bias-pull-up; /* pull up */
156 drive-strength = <2>; /* 2 MA */
157 };
158 };
159
160 sdc2_data_on: sdc2_data_on {
161 config {
162 pins = "sdc2_data";
163 bias-pull-up; /* pull up */
164 drive-strength = <10>; /* 10 MA */
165 };
166 };
167
168 sdc2_data_off: sdc2_data_off {
169 config {
170 pins = "sdc2_data";
171 bias-pull-up; /* pull up */
172 drive-strength = <2>; /* 2 MA */
173 };
174 };
175
Tony Truongc0e0a5f02017-03-15 11:57:40 -0700176 pcie0 {
177 pcie0_clkreq_default: pcie0_clkreq_default {
178 mux {
179 pins = "gpio36";
180 function = "pci_e0";
181 };
182
183 config {
184 pins = "gpio36";
185 drive-strength = <2>;
186 bias-pull-up;
187 };
188 };
189
190 pcie0_perst_default: pcie0_perst_default {
191 mux {
192 pins = "gpio35";
193 function = "gpio";
194 };
195
196 config {
197 pins = "gpio35";
198 drive-strength = <2>;
199 bias-pull-down;
200 };
201 };
202
203 pcie0_wake_default: pcie0_wake_default {
204 mux {
205 pins = "gpio37";
206 function = "gpio";
207 };
208
209 config {
210 pins = "gpio37";
211 drive-strength = <2>;
212 bias-pull-down;
213 };
214 };
215 };
216
Banajit Goswamib016de92017-02-15 21:02:30 -0800217 cdc_reset_ctrl {
218 cdc_reset_sleep: cdc_reset_sleep {
219 mux {
220 pins = "gpio64";
221 function = "gpio";
222 };
223 config {
224 pins = "gpio64";
225 drive-strength = <2>;
226 bias-disable;
227 output-low;
228 };
229 };
230
231 cdc_reset_active:cdc_reset_active {
232 mux {
233 pins = "gpio64";
234 function = "gpio";
235 };
236 config {
237 pins = "gpio64";
238 drive-strength = <8>;
239 bias-pull-down;
240 output-high;
241 };
242 };
243 };
244
245 spkr_i2s_clk_pin {
246 spkr_i2s_clk_sleep: spkr_i2s_clk_sleep {
247 mux {
248 pins = "gpio69";
249 function = "spkr_i2s";
250 };
251
252 config {
253 pins = "gpio69";
254 drive-strength = <2>; /* 2 mA */
255 bias-pull-down; /* PULL DOWN */
256 };
257 };
258
259 spkr_i2s_clk_active: spkr_i2s_clk_active {
260 mux {
261 pins = "gpio69";
262 function = "spkr_i2s";
263 };
264
265 config {
266 pins = "gpio69";
267 drive-strength = <8>; /* 8 mA */
268 bias-disable; /* NO PULL */
269 };
270 };
271 };
272
273 wcd_gnd_mic_swap {
274 wcd_gnd_mic_swap_idle: wcd_gnd_mic_swap_idle {
275 mux {
276 pins = "gpio51";
277 function = "gpio";
278 };
279 config {
280 pins = "gpio51";
281 drive-strength = <2>;
282 bias-pull-down;
283 output-low;
284 };
285 };
286
287 wcd_gnd_mic_swap_active: wcd_gnd_mic_swap_active {
288 mux {
289 pins = "gpio51";
290 function = "gpio";
291 };
292 config {
293 pins = "gpio51";
294 drive-strength = <2>;
295 bias-disable;
296 output-high;
297 };
298 };
299 };
300
301 pri_aux_pcm_clk {
302 pri_aux_pcm_clk_sleep: pri_aux_pcm_clk_sleep {
303 mux {
304 pins = "gpio65";
305 function = "gpio";
306 };
307
308 config {
309 pins = "gpio65";
310 drive-strength = <2>; /* 2 mA */
311 bias-pull-down; /* PULL DOWN */
312 input-enable;
313 };
314 };
315
316 pri_aux_pcm_clk_active: pri_aux_pcm_clk_active {
317 mux {
318 pins = "gpio65";
319 function = "pri_mi2s";
320 };
321
322 config {
323 pins = "gpio65";
324 drive-strength = <8>; /* 8 mA */
325 bias-disable; /* NO PULL */
326 output-high;
327 };
328 };
329 };
330
331 pri_aux_pcm_sync {
332 pri_aux_pcm_sync_sleep: pri_aux_pcm_sync_sleep {
333 mux {
334 pins = "gpio66";
335 function = "gpio";
336 };
337
338 config {
339 pins = "gpio66";
340 drive-strength = <2>; /* 2 mA */
341 bias-pull-down; /* PULL DOWN */
342 input-enable;
343 };
344 };
345
346 pri_aux_pcm_sync_active: pri_aux_pcm_sync_active {
347 mux {
348 pins = "gpio66";
349 function = "pri_mi2s_ws";
350 };
351
352 config {
353 pins = "gpio66";
354 drive-strength = <8>; /* 8 mA */
355 bias-disable; /* NO PULL */
356 output-high;
357 };
358 };
359 };
360
361 pri_aux_pcm_din {
362 pri_aux_pcm_din_sleep: pri_aux_pcm_din_sleep {
363 mux {
364 pins = "gpio67";
365 function = "gpio";
366 };
367
368 config {
369 pins = "gpio67";
370 drive-strength = <2>; /* 2 mA */
371 bias-pull-down; /* PULL DOWN */
372 input-enable;
373 };
374 };
375
376 pri_aux_pcm_din_active: pri_aux_pcm_din_active {
377 mux {
378 pins = "gpio67";
379 function = "pri_mi2s";
380 };
381
382 config {
383 pins = "gpio67";
384 drive-strength = <8>; /* 8 mA */
385 bias-disable; /* NO PULL */
386 };
387 };
388 };
389
390 pri_aux_pcm_dout {
391 pri_aux_pcm_dout_sleep: pri_aux_pcm_dout_sleep {
392 mux {
393 pins = "gpio68";
394 function = "gpio";
395 };
396
397 config {
398 pins = "gpio68";
399 drive-strength = <2>; /* 2 mA */
400 bias-pull-down; /* PULL DOWN */
401 input-enable;
402 };
403 };
404
405 pri_aux_pcm_dout_active: pri_aux_pcm_dout_active {
406 mux {
407 pins = "gpio68";
408 function = "pri_mi2s";
409 };
410
411 config {
412 pins = "gpio68";
413 drive-strength = <8>; /* 8 mA */
414 bias-disable; /* NO PULL */
415 };
416 };
417 };
418
Shashank Babu Chinta Venkata2f40bc72017-03-21 15:31:38 -0700419 pmx_sde: pmx_sde {
420 sde_dsi_active: sde_dsi_active {
421 mux {
422 pins = "gpio6", "gpio52";
423 function = "gpio";
424 };
425
426 config {
427 pins = "gpio6", "gpio52";
428 drive-strength = <8>; /* 8 mA */
429 bias-disable = <0>; /* no pull */
430 };
431 };
432 sde_dsi_suspend: sde_dsi_suspend {
433 mux {
434 pins = "gpio6", "gpio52";
435 function = "gpio";
436 };
437
438 config {
439 pins = "gpio6", "gpio52";
440 drive-strength = <2>; /* 2 mA */
441 bias-pull-down; /* PULL DOWN */
442 };
443 };
444 };
445
446 pmx_sde_te {
447 sde_te_active: sde_te_active {
448 mux {
449 pins = "gpio10";
450 function = "mdp_vsync";
451 };
452
453 config {
454 pins = "gpio10";
455 drive-strength = <2>; /* 2 mA */
456 bias-pull-down; /* PULL DOWN */
457 };
458 };
459
460 sde_te_suspend: sde_te_suspend {
461 mux {
462 pins = "gpio10";
463 function = "mdp_vsync";
464 };
465
466 config {
467 pins = "gpio10";
468 drive-strength = <2>; /* 2 mA */
469 bias-pull-down; /* PULL DOWN */
470 };
471 };
472 };
473
Padmanabhan Komanduru887085e2017-05-02 14:57:12 -0700474 sde_dp_aux_active: sde_dp_aux_active {
475 mux {
476 pins = "gpio43", "gpio51";
477 function = "gpio";
478 };
479
480 config {
481 pins = "gpio43", "gpio51";
482 bias-disable = <0>; /* no pull */
483 drive-strength = <8>;
484 };
485 };
486
487 sde_dp_aux_suspend: sde_dp_aux_suspend {
488 mux {
489 pins = "gpio43", "gpio51";
490 function = "gpio";
491 };
492
493 config {
494 pins = "gpio43", "gpio51";
495 bias-pull-down;
496 drive-strength = <2>;
497 };
498 };
499
500 sde_dp_usbplug_cc_active: sde_dp_usbplug_cc_active {
501 mux {
502 pins = "gpio38";
503 function = "gpio";
504 };
505
506 config {
507 pins = "gpio38";
508 bias-disable;
509 drive-strength = <16>;
510 };
511 };
512
513 sde_dp_usbplug_cc_suspend: sde_dp_usbplug_cc_suspend {
514 mux {
515 pins = "gpio38";
516 function = "gpio";
517 };
518
519 config {
520 pins = "gpio38";
521 bias-pull-down;
522 drive-strength = <2>;
523 };
524 };
525
Banajit Goswamib016de92017-02-15 21:02:30 -0800526 sec_aux_pcm {
527 sec_aux_pcm_sleep: sec_aux_pcm_sleep {
528 mux {
529 pins = "gpio80", "gpio81";
530 function = "gpio";
531 };
532
533 config {
534 pins = "gpio80", "gpio81";
535 drive-strength = <2>; /* 2 mA */
536 bias-pull-down; /* PULL DOWN */
537 input-enable;
538 };
539 };
540
541 sec_aux_pcm_active: sec_aux_pcm_active {
542 mux {
543 pins = "gpio80", "gpio81";
544 function = "sec_mi2s";
545 };
546
547 config {
548 pins = "gpio80", "gpio81";
549 drive-strength = <8>; /* 8 mA */
550 bias-disable; /* NO PULL */
551 };
552 };
553 };
554
555 sec_aux_pcm_din {
556 sec_aux_pcm_din_sleep: sec_aux_pcm_din_sleep {
557 mux {
558 pins = "gpio82";
559 function = "gpio";
560 };
561
562 config {
563 pins = "gpio82";
564 drive-strength = <2>; /* 2 mA */
565 bias-pull-down; /* PULL DOWN */
566 input-enable;
567 };
568 };
569
570 sec_aux_pcm_din_active: sec_aux_pcm_din_active {
571 mux {
572 pins = "gpio82";
573 function = "sec_mi2s";
574 };
575
576 config {
577 pins = "gpio82";
578 drive-strength = <8>; /* 8 mA */
579 bias-disable; /* NO PULL */
580 };
581 };
582 };
583
584 sec_aux_pcm_dout {
585 sec_aux_pcm_dout_sleep: sec_aux_pcm_dout_sleep {
586 mux {
587 pins = "gpio83";
588 function = "gpio";
589 };
590
591 config {
592 pins = "gpio83";
593 drive-strength = <2>; /* 2 mA */
594 bias-pull-down; /* PULL DOWN */
595 input-enable;
596 };
597 };
598
599 sec_aux_pcm_dout_active: sec_aux_pcm_dout_active {
600 mux {
601 pins = "gpio83";
602 function = "sec_mi2s";
603 };
604
605 config {
606 pins = "gpio83";
607 drive-strength = <8>; /* 8 mA */
608 bias-disable; /* NO PULL */
609 };
610 };
611 };
612
613 tert_aux_pcm {
614 tert_aux_pcm_sleep: tert_aux_pcm_sleep {
615 mux {
616 pins = "gpio75", "gpio76";
617 function = "gpio";
618 };
619
620 config {
621 pins = "gpio75", "gpio76";
622 drive-strength = <2>; /* 2 mA */
623 bias-pull-down; /* PULL DOWN */
624 input-enable;
625 };
626 };
627
628 tert_aux_pcm_active: tert_aux_pcm_active {
629 mux {
630 pins = "gpio75", "gpio76";
631 function = "ter_mi2s";
632 };
633
634 config {
635 pins = "gpio75", "gpio76";
636 drive-strength = <8>; /* 8 mA */
637 bias-disable; /* NO PULL */
638 output-high;
639 };
640 };
641 };
642
643 tert_aux_pcm_din {
644 tert_aux_pcm_din_sleep: tert_aux_pcm_din_sleep {
645 mux {
646 pins = "gpio77";
647 function = "gpio";
648 };
649
650 config {
651 pins = "gpio77";
652 drive-strength = <2>; /* 2 mA */
653 bias-pull-down; /* PULL DOWN */
654 input-enable;
655 };
656 };
657
658 tert_aux_pcm_din_active: tert_aux_pcm_din_active {
659 mux {
660 pins = "gpio77";
661 function = "ter_mi2s";
662 };
663
664 config {
665 pins = "gpio77";
666 drive-strength = <8>; /* 8 mA */
667 bias-disable; /* NO PULL */
668 };
669 };
670 };
671
672 tert_aux_pcm_dout {
673 tert_aux_pcm_dout_sleep: tert_aux_pcm_dout_sleep {
674 mux {
675 pins = "gpio78";
676 function = "gpio";
677 };
678
679 config {
680 pins = "gpio78";
681 drive-strength = <2>; /* 2 mA */
682 bias-pull-down; /* PULL DOWN */
683 input-enable;
684 };
685 };
686
687 tert_aux_pcm_dout_active: tert_aux_pcm_dout_active {
688 mux {
689 pins = "gpio78";
690 function = "ter_mi2s";
691 };
692
693 config {
694 pins = "gpio78";
695 drive-strength = <8>; /* 8 mA */
696 bias-disable; /* NO PULL */
697 };
698 };
699 };
700
701 quat_aux_pcm {
702 quat_aux_pcm_sleep: quat_aux_pcm_sleep {
703 mux {
704 pins = "gpio58", "gpio59";
705 function = "gpio";
706 };
707
708 config {
709 pins = "gpio58", "gpio59";
710 drive-strength = <2>; /* 2 mA */
711 bias-pull-down; /* PULL DOWN */
712 input-enable;
713 };
714 };
715
716 quat_aux_pcm_active: quat_aux_pcm_active {
717 mux {
718 pins = "gpio58", "gpio59";
719 function = "qua_mi2s";
720 };
721
722 config {
723 pins = "gpio58", "gpio59";
724 drive-strength = <8>; /* 8 mA */
725 bias-disable; /* NO PULL */
726 output-high;
727 };
728 };
729 };
730
731 quat_aux_pcm_din {
732 quat_aux_pcm_din_sleep: quat_aux_pcm_din_sleep {
733 mux {
734 pins = "gpio60";
735 function = "gpio";
736 };
737
738 config {
739 pins = "gpio60";
740 drive-strength = <2>; /* 2 mA */
741 bias-pull-down; /* PULL DOWN */
742 input-enable;
743 };
744 };
745
746 quat_aux_pcm_din_active: quat_aux_pcm_din_active {
747 mux {
748 pins = "gpio60";
749 function = "qua_mi2s";
750 };
751
752 config {
753 pins = "gpio60";
754 drive-strength = <8>; /* 8 mA */
755 bias-disable; /* NO PULL */
756 };
757 };
758 };
759
760 quat_aux_pcm_dout {
761 quat_aux_pcm_dout_sleep: quat_aux_pcm_dout_sleep {
762 mux {
763 pins = "gpio61";
764 function = "gpio";
765 };
766
767 config {
768 pins = "gpio61";
769 drive-strength = <2>; /* 2 mA */
770 bias-pull-down; /* PULL DOWN */
771 input-enable;
772 };
773 };
774
775 quat_aux_pcm_dout_active: quat_aux_pcm_dout_active {
776 mux {
777 pins = "gpio61";
778 function = "qua_mi2s";
779 };
780
781 config {
782 pins = "gpio61";
783 drive-strength = <8>; /* 8 mA */
784 bias-disable; /* NO PULL */
785 };
786 };
787 };
788
789 pri_mi2s_mclk {
790 pri_mi2s_mclk_sleep: pri_mi2s_mclk_sleep {
791 mux {
792 pins = "gpio64";
793 function = "gpio";
794 };
795
796 config {
797 pins = "gpio64";
798 drive-strength = <2>; /* 2 mA */
799 bias-pull-down; /* PULL DOWN */
800 input-enable;
801 };
802 };
803
804 pri_mi2s_mclk_active: pri_mi2s_mclk_active {
805 mux {
806 pins = "gpio64";
807 function = "pri_mi2s";
808 };
809
810 config {
811 pins = "gpio64";
812 drive-strength = <8>; /* 8 mA */
813 bias-disable; /* NO PULL */
814 output-high;
815 };
816 };
817 };
818
819 pri_mi2s_sck {
820 pri_mi2s_sck_sleep: pri_mi2s_sck_sleep {
821 mux {
822 pins = "gpio65";
823 function = "gpio";
824 };
825
826 config {
827 pins = "gpio65";
828 drive-strength = <2>; /* 2 mA */
829 bias-pull-down; /* PULL DOWN */
830 input-enable;
831 };
832 };
833
834 pri_mi2s_sck_active: pri_mi2s_sck_active {
835 mux {
836 pins = "gpio65";
837 function = "pri_mi2s";
838 };
839
840 config {
841 pins = "gpio65";
842 drive-strength = <8>; /* 8 mA */
843 bias-disable; /* NO PULL */
844 output-high;
845 };
846 };
847 };
848
849 pri_mi2s_ws {
850 pri_mi2s_ws_sleep: pri_mi2s_ws_sleep {
851 mux {
852 pins = "gpio66";
853 function = "gpio";
854 };
855
856 config {
857 pins = "gpio66";
858 drive-strength = <2>; /* 2 mA */
859 bias-pull-down; /* PULL DOWN */
860 input-enable;
861 };
862 };
863
864 pri_mi2s_ws_active: pri_mi2s_ws_active {
865 mux {
866 pins = "gpio66";
867 function = "pri_mi2s_ws";
868 };
869
870 config {
871 pins = "gpio66";
872 drive-strength = <8>; /* 8 mA */
873 bias-disable; /* NO PULL */
874 output-high;
875 };
876 };
877 };
878
879 pri_mi2s_sd0 {
880 pri_mi2s_sd0_sleep: pri_mi2s_sd0_sleep {
881 mux {
882 pins = "gpio67";
883 function = "gpio";
884 };
885
886 config {
887 pins = "gpio67";
888 drive-strength = <2>; /* 2 mA */
889 bias-pull-down; /* PULL DOWN */
890 input-enable;
891 };
892 };
893
894 pri_mi2s_sd0_active: pri_mi2s_sd0_active {
895 mux {
896 pins = "gpio67";
897 function = "pri_mi2s";
898 };
899
900 config {
901 pins = "gpio67";
902 drive-strength = <8>; /* 8 mA */
903 bias-disable; /* NO PULL */
904 };
905 };
906 };
907
908 pri_mi2s_sd1 {
909 pri_mi2s_sd1_sleep: pri_mi2s_sd1_sleep {
910 mux {
911 pins = "gpio68";
912 function = "gpio";
913 };
914
915 config {
916 pins = "gpio68";
917 drive-strength = <2>; /* 2 mA */
918 bias-pull-down; /* PULL DOWN */
919 input-enable;
920 };
921 };
922
923 pri_mi2s_sd1_active: pri_mi2s_sd1_active {
924 mux {
925 pins = "gpio68";
926 function = "pri_mi2s";
927 };
928
929 config {
930 pins = "gpio68";
931 drive-strength = <8>; /* 8 mA */
932 bias-disable; /* NO PULL */
933 };
934 };
935 };
936
937 sec_mi2s_mclk {
938 sec_mi2s_mclk_sleep: sec_mi2s_mclk_sleep {
939 mux {
940 pins = "gpio79";
941 function = "gpio";
942 };
943
944 config {
945 pins = "gpio79";
946 drive-strength = <2>; /* 2 mA */
947 bias-pull-down; /* PULL DOWN */
948 input-enable;
949 };
950 };
951
952 sec_mi2s_mclk_active: sec_mi2s_mclk_active {
953 mux {
954 pins = "gpio79";
955 function = "sec_mi2s";
956 };
957
958 config {
959 pins = "gpio79";
960 drive-strength = <8>; /* 8 mA */
961 bias-disable; /* NO PULL */
962 };
963 };
964 };
965
966 sec_mi2s {
967 sec_mi2s_sleep: sec_mi2s_sleep {
968 mux {
969 pins = "gpio80", "gpio81";
970 function = "gpio";
971 };
972
973 config {
974 pins = "gpio80", "gpio81";
975 drive-strength = <2>; /* 2 mA */
976 bias-disable; /* NO PULL */
977 input-enable;
978 };
979 };
980
981 sec_mi2s_active: sec_mi2s_active {
982 mux {
983 pins = "gpio80", "gpio81";
984 function = "sec_mi2s";
985 };
986
987 config {
988 pins = "gpio80", "gpio81";
989 drive-strength = <8>; /* 8 mA */
990 bias-disable; /* NO PULL */
991 };
992 };
993 };
994
995 sec_mi2s_sd0 {
996 sec_mi2s_sd0_sleep: sec_mi2s_sd0_sleep {
997 mux {
998 pins = "gpio82";
999 function = "gpio";
1000 };
1001
1002 config {
1003 pins = "gpio82";
1004 drive-strength = <2>; /* 2 mA */
1005 bias-pull-down; /* PULL DOWN */
1006 input-enable;
1007 };
1008 };
1009
1010 sec_mi2s_sd0_active: sec_mi2s_sd0_active {
1011 mux {
1012 pins = "gpio82";
1013 function = "sec_mi2s";
1014 };
1015
1016 config {
1017 pins = "gpio82";
1018 drive-strength = <8>; /* 8 mA */
1019 bias-disable; /* NO PULL */
1020 };
1021 };
1022 };
1023
1024 sec_mi2s_sd1 {
1025 sec_mi2s_sd1_sleep: sec_mi2s_sd1_sleep {
1026 mux {
1027 pins = "gpio83";
1028 function = "gpio";
1029 };
1030
1031 config {
1032 pins = "gpio83";
1033 drive-strength = <2>; /* 2 mA */
1034 bias-pull-down; /* PULL DOWN */
1035 input-enable;
1036 };
1037 };
1038
1039 sec_mi2s_sd1_active: sec_mi2s_sd1_active {
1040 mux {
1041 pins = "gpio83";
1042 function = "sec_mi2s";
1043 };
1044
1045 config {
1046 pins = "gpio83";
1047 drive-strength = <8>; /* 8 mA */
1048 bias-disable; /* NO PULL */
1049 };
1050 };
1051 };
1052
1053 tert_mi2s_mclk {
1054 tert_mi2s_mclk_sleep: tert_mi2s_mclk_sleep {
1055 mux {
1056 pins = "gpio74";
1057 function = "gpio";
1058 };
1059
1060 config {
1061 pins = "gpio74";
1062 drive-strength = <2>; /* 2 mA */
1063 bias-pull-down; /* PULL DOWN */
1064 input-enable;
1065 };
1066 };
1067
1068 tert_mi2s_mclk_active: tert_mi2s_mclk_active {
1069 mux {
1070 pins = "gpio74";
1071 function = "ter_mi2s";
1072 };
1073
1074 config {
1075 pins = "gpio74";
1076 drive-strength = <8>; /* 8 mA */
1077 bias-disable; /* NO PULL */
1078 };
1079 };
1080 };
1081
1082 tert_mi2s {
1083 tert_mi2s_sleep: tert_mi2s_sleep {
1084 mux {
1085 pins = "gpio75", "gpio76";
1086 function = "gpio";
1087 };
1088
1089 config {
1090 pins = "gpio75", "gpio76";
1091 drive-strength = <2>; /* 2 mA */
1092 bias-pull-down; /* PULL DOWN */
1093 input-enable;
1094 };
1095 };
1096
1097 tert_mi2s_active: tert_mi2s_active {
1098 mux {
1099 pins = "gpio75", "gpio76";
1100 function = "ter_mi2s";
1101 };
1102
1103 config {
1104 pins = "gpio75", "gpio76";
1105 drive-strength = <8>; /* 8 mA */
1106 bias-disable; /* NO PULL */
1107 output-high;
1108 };
1109 };
1110 };
1111
1112 tert_mi2s_sd0 {
1113 tert_mi2s_sd0_sleep: tert_mi2s_sd0_sleep {
1114 mux {
1115 pins = "gpio77";
1116 function = "gpio";
1117 };
1118
1119 config {
1120 pins = "gpio77";
1121 drive-strength = <2>; /* 2 mA */
1122 bias-pull-down; /* PULL DOWN */
1123 input-enable;
1124 };
1125 };
1126
1127 tert_mi2s_sd0_active: tert_mi2s_sd0_active {
1128 mux {
1129 pins = "gpio77";
1130 function = "ter_mi2s";
1131 };
1132
1133 config {
1134 pins = "gpio77";
1135 drive-strength = <8>; /* 8 mA */
1136 bias-disable; /* NO PULL */
1137 };
1138 };
1139 };
1140
1141 tert_mi2s_sd1 {
1142 tert_mi2s_sd1_sleep: tert_mi2s_sd1_sleep {
1143 mux {
1144 pins = "gpio78";
1145 function = "gpio";
1146 };
1147
1148 config {
1149 pins = "gpio78";
1150 drive-strength = <2>; /* 2 mA */
1151 bias-pull-down; /* PULL DOWN */
1152 input-enable;
1153 };
1154 };
1155
1156 tert_mi2s_sd1_active: tert_mi2s_sd1_active {
1157 mux {
1158 pins = "gpio78";
1159 function = "ter_mi2s";
1160 };
1161
1162 config {
1163 pins = "gpio78";
1164 drive-strength = <8>; /* 8 mA */
1165 bias-disable; /* NO PULL */
1166 };
1167 };
1168 };
1169
1170 quat_mi2s_mclk {
1171 quat_mi2s_mclk_sleep: quat_mi2s_mclk_sleep {
1172 mux {
1173 pins = "gpio57";
1174 function = "gpio";
1175 };
1176
1177 config {
1178 pins = "gpio57";
1179 drive-strength = <2>; /* 2 mA */
1180 bias-pull-down; /* PULL DOWN */
1181 input-enable;
1182 };
1183 };
1184
1185 quat_mi2s_mclk_active: quat_mi2s_mclk_active {
1186 mux {
1187 pins = "gpio57";
1188 function = "qua_mi2s";
1189 };
1190
1191 config {
1192 pins = "gpio57";
1193 drive-strength = <8>; /* 8 mA */
1194 bias-disable; /* NO PULL */
1195 };
1196 };
1197 };
1198
1199 quat_mi2s {
1200 quat_mi2s_sleep: quat_mi2s_sleep {
1201 mux {
1202 pins = "gpio58", "gpio59";
1203 function = "gpio";
1204 };
1205
1206 config {
1207 pins = "gpio58", "gpio59";
1208 drive-strength = <2>; /* 2 mA */
1209 bias-pull-down; /* PULL DOWN */
1210 input-enable;
1211 };
1212 };
1213
1214 quat_mi2s_active: quat_mi2s_active {
1215 mux {
1216 pins = "gpio58", "gpio59";
1217 function = "qua_mi2s";
1218 };
1219
1220 config {
1221 pins = "gpio58", "gpio59";
1222 drive-strength = <8>; /* 8 mA */
1223 bias-disable; /* NO PULL */
1224 output-high;
1225 };
1226 };
1227 };
1228
1229 quat_mi2s_sd0 {
1230 quat_mi2s_sd0_sleep: quat_mi2s_sd0_sleep {
1231 mux {
1232 pins = "gpio60";
1233 function = "gpio";
1234 };
1235
1236 config {
1237 pins = "gpio60";
1238 drive-strength = <2>; /* 2 mA */
1239 bias-pull-down; /* PULL DOWN */
1240 input-enable;
1241 };
1242 };
1243
1244 quat_mi2s_sd0_active: quat_mi2s_sd0_active {
1245 mux {
1246 pins = "gpio60";
1247 function = "qua_mi2s";
1248 };
1249
1250 config {
1251 pins = "gpio60";
1252 drive-strength = <8>; /* 8 mA */
1253 bias-disable; /* NO PULL */
1254 };
1255 };
1256 };
1257
1258 quat_mi2s_sd1 {
1259 quat_mi2s_sd1_sleep: quat_mi2s_sd1_sleep {
1260 mux {
1261 pins = "gpio61";
1262 function = "gpio";
1263 };
1264
1265 config {
1266 pins = "gpio61";
1267 drive-strength = <2>; /* 2 mA */
1268 bias-pull-down; /* PULL DOWN */
1269 input-enable;
1270 };
1271 };
1272
1273 quat_mi2s_sd1_active: quat_mi2s_sd1_active {
1274 mux {
1275 pins = "gpio61";
1276 function = "qua_mi2s";
1277 };
1278
1279 config {
1280 pins = "gpio61";
1281 drive-strength = <8>; /* 8 mA */
1282 bias-disable; /* NO PULL */
1283 };
1284 };
1285 };
1286
1287 quat_mi2s_sd2 {
1288 quat_mi2s_sd2_sleep: quat_mi2s_sd2_sleep {
1289 mux {
1290 pins = "gpio62";
1291 function = "gpio";
1292 };
1293
1294 config {
1295 pins = "gpio62";
1296 drive-strength = <2>; /* 2 mA */
1297 bias-pull-down; /* PULL DOWN */
1298 input-enable;
1299 };
1300 };
1301
1302 quat_mi2s_sd2_active: quat_mi2s_sd2_active {
1303 mux {
1304 pins = "gpio62";
1305 function = "qua_mi2s";
1306 };
1307
1308 config {
1309 pins = "gpio62";
1310 drive-strength = <8>; /* 8 mA */
1311 bias-disable; /* NO PULL */
1312 };
1313 };
1314 };
1315
1316 quat_mi2s_sd3 {
1317 quat_mi2s_sd3_sleep: quat_mi2s_sd3_sleep {
1318 mux {
1319 pins = "gpio63";
1320 function = "gpio";
1321 };
1322
1323 config {
1324 pins = "gpio63";
1325 drive-strength = <2>; /* 2 mA */
1326 bias-pull-down; /* PULL DOWN */
1327 input-enable;
1328 };
1329 };
1330
1331 quat_mi2s_sd3_active: quat_mi2s_sd3_active {
1332 mux {
1333 pins = "gpio63";
1334 function = "qua_mi2s";
1335 };
1336
1337 config {
1338 pins = "gpio63";
1339 drive-strength = <8>; /* 8 mA */
1340 bias-disable; /* NO PULL */
1341 };
1342 };
1343 };
Girish Mahadevan2e2fbe72017-03-28 13:28:18 -06001344
1345 /* QUPv3 South SE mappings */
1346 /* SE 0 pin mappings */
1347 qupv3_se0_i2c_pins: qupv3_se0_i2c_pins {
1348 qupv3_se0_i2c_active: qupv3_se0_i2c_active {
1349 mux {
1350 pins = "gpio0", "gpio1";
1351 function = "qup0";
1352 };
1353
1354 config {
1355 pins = "gpio0", "gpio1";
1356 drive-strength = <2>;
1357 bias-disable;
1358 };
1359 };
1360
1361 qupv3_se0_i2c_sleep: qupv3_se0_i2c_sleep {
1362 mux {
1363 pins = "gpio0", "gpio1";
1364 function = "gpio";
1365 };
1366
1367 config {
1368 pins = "gpio0", "gpio1";
1369 drive-strength = <2>;
1370 bias-pull-up;
1371 };
1372 };
1373 };
1374
1375 qupv3_se0_spi_pins: qupv3_se0_spi_pins {
1376 qupv3_se0_spi_active: qupv3_se0_spi_active {
1377 mux {
1378 pins = "gpio0", "gpio1", "gpio2",
1379 "gpio3";
1380 function = "qup0";
1381 };
1382
1383 config {
1384 pins = "gpio0", "gpio1", "gpio2",
1385 "gpio3";
1386 drive-strength = <6>;
1387 bias-disable;
1388 };
1389 };
1390
1391 qupv3_se0_spi_sleep: qupv3_se0_spi_sleep {
1392 mux {
1393 pins = "gpio0", "gpio1", "gpio2",
1394 "gpio3";
1395 function = "gpio";
1396 };
1397
1398 config {
1399 pins = "gpio0", "gpio1", "gpio2",
1400 "gpio3";
1401 drive-strength = <6>;
1402 bias-disable;
1403 };
1404 };
1405 };
1406
1407 /* SE 1 pin mappings */
1408 qupv3_se1_i2c_pins: qupv3_se1_i2c_pins {
1409 qupv3_se1_i2c_active: qupv3_se1_i2c_active {
1410 mux {
1411 pins = "gpio17", "gpio18";
1412 function = "qup1";
1413 };
1414
1415 config {
1416 pins = "gpio17", "gpio18";
1417 drive-strength = <2>;
1418 bias-disable;
1419 };
1420 };
1421
1422 qupv3_se1_i2c_sleep: qupv3_se1_i2c_sleep {
1423 mux {
1424 pins = "gpio17", "gpio18";
1425 function = "gpio";
1426 };
1427
1428 config {
1429 pins = "gpio17", "gpio18";
1430 drive-strength = <2>;
1431 bias-pull-up;
1432 };
1433 };
1434 };
1435
1436 qupv3_se1_spi_pins: qupv3_se1_spi_pins {
1437 qupv3_se1_spi_active: qupv3_se1_spi_active {
1438 mux {
1439 pins = "gpio17", "gpio18", "gpio19",
1440 "gpio20";
1441 function = "qup1";
1442 };
1443
1444 config {
1445 pins = "gpio17", "gpio18", "gpio19",
1446 "gpio20";
1447 drive-strength = <6>;
1448 bias-disable;
1449 };
1450 };
1451
1452 qupv3_se1_spi_sleep: qupv3_se1_spi_sleep {
1453 mux {
1454 pins = "gpio17", "gpio18", "gpio19",
1455 "gpio20";
1456 function = "gpio";
1457 };
1458
1459 config {
1460 pins = "gpio17", "gpio18", "gpio19",
1461 "gpio20";
1462 drive-strength = <6>;
1463 bias-disable;
1464 };
1465 };
1466 };
1467
1468 /* SE 2 pin mappings */
1469 qupv3_se2_i2c_pins: qupv3_se2_i2c_pins {
1470 qupv3_se2_i2c_active: qupv3_se2_i2c_active {
1471 mux {
1472 pins = "gpio27", "gpio28";
1473 function = "qup2";
1474 };
1475
1476 config {
1477 pins = "gpio27", "gpio28";
1478 drive-strength = <2>;
1479 bias-disable;
1480 };
1481 };
1482
1483 qupv3_se2_i2c_sleep: qupv3_se2_i2c_sleep {
1484 mux {
1485 pins = "gpio27", "gpio28";
1486 function = "gpio";
1487 };
1488
1489 config {
1490 pins = "gpio27", "gpio28";
1491 drive-strength = <2>;
1492 bias-pull-up;
1493 };
1494 };
1495 };
1496
1497 qupv3_se2_spi_pins: qupv3_se2_spi_pins {
1498 qupv3_se2_spi_active: qupv3_se2_spi_active {
1499 mux {
1500 pins = "gpio27", "gpio28", "gpio29",
1501 "gpio30";
1502 function = "qup2";
1503 };
1504
1505 config {
1506 pins = "gpio27", "gpio28", "gpio29",
1507 "gpio30";
1508 drive-strength = <6>;
1509 bias-disable;
1510 };
1511 };
1512
1513 qupv3_se2_spi_sleep: qupv3_se2_spi_sleep {
1514 mux {
1515 pins = "gpio27", "gpio28", "gpio29",
1516 "gpio30";
1517 function = "gpio";
1518 };
1519
1520 config {
1521 pins = "gpio27", "gpio28", "gpio29",
1522 "gpio30";
1523 drive-strength = <6>;
1524 bias-disable;
1525 };
1526 };
1527 };
1528
1529 /* SE 3 pin mappings */
1530 qupv3_se3_i2c_pins: qupv3_se3_i2c_pins {
1531 qupv3_se3_i2c_active: qupv3_se3_i2c_active {
1532 mux {
1533 pins = "gpio41", "gpio42";
1534 function = "qup3";
1535 };
1536
1537 config {
1538 pins = "gpio41", "gpio42";
1539 drive-strength = <2>;
1540 bias-disable;
1541 };
1542 };
1543
1544 qupv3_se3_i2c_sleep: qupv3_se3_i2c_sleep {
1545 mux {
1546 pins = "gpio41", "gpio42";
1547 function = "gpio";
1548 };
1549
1550 config {
1551 pins = "gpio41", "gpio42";
1552 drive-strength = <2>;
1553 bias-pull-up;
1554 };
1555 };
1556 };
1557
1558 qupv3_se3_spi_pins: qupv3_se3_spi_pins {
1559 qupv3_se3_spi_active: qupv3_se3_spi_active {
1560 mux {
1561 pins = "gpio41", "gpio42", "gpio43",
1562 "gpio44";
1563 function = "qup3";
1564 };
1565
1566 config {
1567 pins = "gpio41", "gpio42", "gpio43",
1568 "gpio44";
1569 drive-strength = <6>;
1570 bias-disable;
1571 };
1572 };
1573
1574 qupv3_se3_spi_sleep: qupv3_se3_spi_sleep {
1575 mux {
1576 pins = "gpio41", "gpio42", "gpio43",
1577 "gpio44";
1578 function = "gpio";
1579 };
1580
1581 config {
1582 pins = "gpio41", "gpio42", "gpio43",
1583 "gpio44";
1584 drive-strength = <6>;
1585 bias-disable;
1586 };
1587 };
1588 };
1589
1590 /* SE 4 pin mappings */
1591 qupv3_se4_i2c_pins: qupv3_se4_i2c_pins {
1592 qupv3_se4_i2c_active: qupv3_se4_i2c_active {
1593 mux {
1594 pins = "gpio89", "gpio90";
1595 function = "qup4";
1596 };
1597
1598 config {
1599 pins = "gpio89", "gpio90";
1600 drive-strength = <2>;
1601 bias-disable;
1602 };
1603 };
1604
1605 qupv3_se4_i2c_sleep: qupv3_se4_i2c_sleep {
1606 mux {
1607 pins = "gpio89", "gpio90";
1608 function = "gpio";
1609 };
1610
1611 config {
1612 pins = "gpio89", "gpio90";
1613 drive-strength = <2>;
1614 bias-pull-up;
1615 };
1616 };
1617 };
1618
1619 qupv3_se4_spi_pins: qupv3_se4_spi_pins {
1620 qupv3_se4_spi_active: qupv3_se4_spi_active {
1621 mux {
1622 pins = "gpio89", "gpio90", "gpio91",
1623 "gpio92";
1624 function = "qup4";
1625 };
1626
1627 config {
1628 pins = "gpio89", "gpio90", "gpio91",
1629 "gpio92";
1630 drive-strength = <6>;
1631 bias-disable;
1632 };
1633 };
1634
1635 qupv3_se4_spi_sleep: qupv3_se4_spi_sleep {
1636 mux {
1637 pins = "gpio89", "gpio90", "gpio91",
1638 "gpio92";
1639 function = "gpio";
1640 };
1641
1642 config {
1643 pins = "gpio89", "gpio90", "gpio91",
1644 "gpio92";
1645 drive-strength = <6>;
1646 bias-disable;
1647 };
1648 };
1649 };
1650
1651 /* SE 5 pin mappings */
1652 qupv3_se5_i2c_pins: qupv3_se5_i2c_pins {
1653 qupv3_se5_i2c_active: qupv3_se5_i2c_active {
1654 mux {
1655 pins = "gpio85", "gpio86";
1656 function = "qup5";
1657 };
1658
1659 config {
1660 pins = "gpio85", "gpio86";
1661 drive-strength = <2>;
1662 bias-disable;
1663 };
1664 };
1665
1666 qupv3_se5_i2c_sleep: qupv3_se5_i2c_sleep {
1667 mux {
1668 pins = "gpio85", "gpio86";
1669 function = "gpio";
1670 };
1671
1672 config {
1673 pins = "gpio85", "gpio86";
1674 drive-strength = <2>;
1675 bias-pull-up;
1676 };
1677 };
1678 };
1679
1680 qupv3_se5_spi_pins: qupv3_se5_spi_pins {
1681 qupv3_se5_spi_active: qupv3_se5_spi_active {
1682 mux {
1683 pins = "gpio85", "gpio86", "gpio87",
1684 "gpio88";
1685 function = "qup5";
1686 };
1687
1688 config {
1689 pins = "gpio85", "gpio86", "gpio87",
1690 "gpio88";
1691 drive-strength = <6>;
1692 bias-disable;
1693 };
1694 };
1695
1696 qupv3_se5_spi_sleep: qupv3_se5_spi_sleep {
1697 mux {
1698 pins = "gpio85", "gpio86", "gpio87",
1699 "gpio88";
1700 function = "gpio";
1701 };
1702
1703 config {
1704 pins = "gpio85", "gpio86", "gpio87",
1705 "gpio88";
1706 drive-strength = <6>;
1707 bias-disable;
1708 };
1709 };
1710 };
1711
1712 /* SE 6 pin mappings */
1713 qupv3_se6_i2c_pins: qupv3_se6_i2c_pins {
1714 qupv3_se6_i2c_active: qupv3_se6_i2c_active {
1715 mux {
1716 pins = "gpio45", "gpio46";
1717 function = "qup6";
1718 };
1719
1720 config {
1721 pins = "gpio45", "gpio46";
1722 drive-strength = <2>;
1723 bias-disable;
1724 };
1725 };
1726
1727 qupv3_se6_i2c_sleep: qupv3_se6_i2c_sleep {
1728 mux {
1729 pins = "gpio45", "gpio46";
1730 function = "gpio";
1731 };
1732
1733 config {
1734 pins = "gpio45", "gpio46";
1735 drive-strength = <2>;
1736 bias-pull-up;
1737 };
1738 };
1739 };
1740
1741 qupv3_se6_4uart_pins: qupv3_se6_4uart_pins {
1742 qupv3_se6_4uart_active: qupv3_se6_4uart_active {
1743 mux {
1744 pins = "gpio45", "gpio46", "gpio47",
1745 "gpio48";
1746 function = "qup6";
1747 };
1748
1749 config {
1750 pins = "gpio45", "gpio46", "gpio47",
1751 "gpio48";
1752 drive-strength = <2>;
1753 bias-disable;
1754 };
1755 };
1756
1757 qupv3_se6_4uart_sleep: qupv3_se6_4uart_sleep {
1758 mux {
1759 pins = "gpio45", "gpio46", "gpio47",
1760 "gpio48";
1761 function = "gpio";
1762 };
1763
1764 config {
1765 pins = "gpio45", "gpio46", "gpio47",
1766 "gpio48";
1767 drive-strength = <2>;
1768 bias-disable;
1769 };
1770 };
1771 };
1772
1773 qupv3_se6_spi_pins: qupv3_se6_spi_pins {
1774 qupv3_se6_spi_active: qupv3_se6_spi_active {
1775 mux {
1776 pins = "gpio45", "gpio46", "gpio47",
1777 "gpio48";
1778 function = "qup6";
1779 };
1780
1781 config {
1782 pins = "gpio45", "gpio46", "gpio47",
1783 "gpio48";
1784 drive-strength = <6>;
1785 bias-disable;
1786 };
1787 };
1788
1789 qupv3_se6_spi_sleep: qupv3_se6_spi_sleep {
1790 mux {
1791 pins = "gpio45", "gpio46", "gpio47",
1792 "gpio48";
1793 function = "gpio";
1794 };
1795
1796 config {
1797 pins = "gpio45", "gpio46", "gpio47",
1798 "gpio48";
1799 drive-strength = <6>;
1800 bias-disable;
1801 };
1802 };
1803 };
1804
1805 /* SE 7 pin mappings */
1806 qupv3_se7_i2c_pins: qupv3_se7_i2c_pins {
1807 qupv3_se7_i2c_active: qupv3_se7_i2c_active {
1808 mux {
1809 pins = "gpio93", "gpio94";
1810 function = "qup7";
1811 };
1812
1813 config {
1814 pins = "gpio93", "gpio94";
1815 drive-strength = <2>;
1816 bias-disable;
1817 };
1818 };
1819
1820 qupv3_se7_i2c_sleep: qupv3_se7_i2c_sleep {
1821 mux {
1822 pins = "gpio93", "gpio94";
1823 function = "gpio";
1824 };
1825
1826 config {
1827 pins = "gpio93", "gpio94";
1828 drive-strength = <2>;
1829 bias-pull-up;
1830 };
1831 };
1832 };
1833
1834 qupv3_se7_4uart_pins: qupv3_se7_4uart_pins {
1835 qupv3_se7_4uart_active: qupv3_se7_4uart_active {
1836 mux {
1837 pins = "gpio93", "gpio94", "gpio95",
1838 "gpio96";
1839 function = "qup7";
1840 };
1841
1842 config {
1843 pins = "gpio93", "gpio94", "gpio95",
1844 "gpio96";
1845 drive-strength = <2>;
1846 bias-disable;
1847 };
1848 };
1849
1850 qupv3_se7_4uart_sleep: qupv3_se7_4uart_sleep {
1851 mux {
1852 pins = "gpio93", "gpio94", "gpio95",
1853 "gpio96";
1854 function = "gpio";
1855 };
1856
1857 config {
1858 pins = "gpio93", "gpio94", "gpio95",
1859 "gpio96";
1860 drive-strength = <2>;
1861 bias-disable;
1862 };
1863 };
1864 };
1865
1866 qupv3_se7_spi_pins: qupv3_se7_spi_pins {
1867 qupv3_se7_spi_active: qupv3_se7_spi_active {
1868 mux {
1869 pins = "gpio93", "gpio94", "gpio95",
1870 "gpio96";
1871 function = "qup7";
1872 };
1873
1874 config {
1875 pins = "gpio93", "gpio94", "gpio95",
1876 "gpio96";
1877 drive-strength = <6>;
1878 bias-disable;
1879 };
1880 };
1881
1882 qupv3_se7_spi_sleep: qupv3_se7_spi_sleep {
1883 mux {
1884 pins = "gpio93", "gpio94", "gpio95",
1885 "gpio96";
1886 function = "gpio";
1887 };
1888
1889 config {
1890 pins = "gpio93", "gpio94", "gpio95",
1891 "gpio96";
1892 drive-strength = <6>;
1893 bias-disable;
1894 };
1895 };
1896 };
1897
1898 /* QUPv3 North instances */
1899 /* SE 8 pin mappings */
1900 qupv3_se8_i2c_pins: qupv3_se8_i2c_pins {
1901 qupv3_se8_i2c_active: qupv3_se8_i2c_active {
1902 mux {
1903 pins = "gpio65", "gpio66";
1904 function = "qup8";
1905 };
1906
1907 config {
1908 pins = "gpio65", "gpio66";
1909 drive-strength = <2>;
1910 bias-disable;
1911 };
1912 };
1913
1914 qupv3_se8_i2c_sleep: qupv3_se8_i2c_sleep {
1915 mux {
1916 pins = "gpio65", "gpio66";
1917 function = "gpio";
1918 };
1919
1920 config {
1921 pins = "gpio65", "gpio66";
1922 drive-strength = <2>;
1923 bias-pull-up;
1924 };
1925 };
1926 };
1927
1928 qupv3_se8_spi_pins: qupv3_se8_spi_pins {
1929 qupv3_se8_spi_active: qupv3_se8_spi_active {
1930 mux {
1931 pins = "gpio65", "gpio66", "gpio67",
1932 "gpio68";
1933 function = "qup8";
1934 };
1935
1936 config {
1937 pins = "gpio65", "gpio66", "gpio67",
1938 "gpio68";
1939 drive-strength = <6>;
1940 bias-disable;
1941 };
1942 };
1943
1944 qupv3_se8_spi_sleep: qupv3_se8_spi_sleep {
1945 mux {
1946 pins = "gpio65", "gpio66", "gpio67",
1947 "gpio68";
1948 function = "gpio";
1949 };
1950
1951 config {
1952 pins = "gpio65", "gpio66", "gpio67",
1953 "gpio68";
1954 drive-strength = <6>;
1955 bias-disable;
1956 };
1957 };
1958 };
1959
1960 /* SE 9 pin mappings */
1961 qupv3_se9_i2c_pins: qupv3_se9_i2c_pins {
1962 qupv3_se9_i2c_active: qupv3_se9_i2c_active {
1963 mux {
1964 pins = "gpio6", "gpio7";
1965 function = "qup9";
1966 };
1967
1968 config {
1969 pins = "gpio6", "gpio7";
1970 drive-strength = <2>;
1971 bias-disable;
1972 };
1973 };
1974
1975 qupv3_se9_i2c_sleep: qupv3_se9_i2c_sleep {
1976 mux {
1977 pins = "gpio6", "gpio7";
1978 function = "gpio";
1979 };
1980
1981 config {
1982 pins = "gpio6", "gpio7";
1983 drive-strength = <2>;
1984 bias-pull-up;
1985 };
1986 };
1987 };
1988
1989 qupv3_se9_2uart_pins: qupv3_se9_2uart_pins {
1990 qupv3_se9_2uart_active: qupv3_se9_2uart_active {
1991 mux {
1992 pins = "gpio4", "gpio5";
1993 function = "qup9";
1994 };
1995
1996 config {
1997 pins = "gpio4", "gpio5";
1998 drive-strength = <2>;
1999 bias-disable;
2000 };
2001 };
2002
2003 qupv3_se9_2uart_sleep: qupv3_se9_2uart_sleep {
2004 mux {
2005 pins = "gpio4", "gpio5";
2006 function = "gpio";
2007 };
2008
2009 config {
2010 pins = "gpio4", "gpio5";
2011 drive-strength = <2>;
2012 bias-disable;
2013 };
2014 };
2015 };
2016
2017 qupv3_se9_spi_pins: qupv3_se9_spi_pins {
2018 qupv3_se9_spi_active: qupv3_se9_spi_active {
2019 mux {
2020 pins = "gpio4", "gpio5", "gpio6",
2021 "gpio7";
2022 function = "qup9";
2023 };
2024
2025 config {
2026 pins = "gpio4", "gpio5", "gpio6",
2027 "gpio7";
2028 drive-strength = <6>;
2029 bias-disable;
2030 };
2031 };
2032
2033 qupv3_se9_spi_sleep: qupv3_se9_spi_sleep {
2034 mux {
2035 pins = "gpio4", "gpio5", "gpio6",
2036 "gpio7";
2037 function = "gpio";
2038 };
2039
2040 config {
2041 pins = "gpio4", "gpio5", "gpio6",
2042 "gpio7";
2043 drive-strength = <6>;
2044 bias-disable;
2045 };
2046 };
2047 };
2048
2049 /* SE 10 pin mappings */
2050 qupv3_se10_i2c_pins: qupv3_se10_i2c_pins {
2051 qupv3_se10_i2c_active: qupv3_se10_i2c_active {
2052 mux {
2053 pins = "gpio55", "gpio56";
2054 function = "qup10";
2055 };
2056
2057 config {
2058 pins = "gpio55", "gpio56";
2059 drive-strength = <2>;
2060 bias-disable;
2061 };
2062 };
2063
2064 qupv3_se10_i2c_sleep: qupv3_se10_i2c_sleep {
2065 mux {
2066 pins = "gpio55", "gpio56";
2067 function = "gpio";
2068 };
2069
2070 config {
2071 pins = "gpio55", "gpio56";
2072 drive-strength = <2>;
2073 bias-pull-up;
2074 };
2075 };
2076 };
2077
2078 qupv3_se10_2uart_pins: qupv3_se10_2uart_pins {
2079 qupv3_se10_2uart_active: qupv3_se10_2uart_active {
2080 mux {
2081 pins = "gpio53", "gpio54";
2082 function = "qup10";
2083 };
2084
2085 config {
2086 pins = "gpio53", "gpio54";
2087 drive-strength = <2>;
2088 bias-disable;
2089 };
2090 };
2091
2092 qupv3_se10_2uart_sleep: qupv3_se10_2uart_sleep {
2093 mux {
2094 pins = "gpio53", "gpio54";
2095 function = "gpio";
2096 };
2097
2098 config {
2099 pins = "gpio53", "gpio54";
2100 drive-strength = <2>;
2101 bias-disable;
2102 };
2103 };
2104 };
2105
2106 qupv3_se10_spi_pins: qupv3_se10_spi_pins {
2107 qupv3_se10_spi_active: qupv3_se10_spi_active {
2108 mux {
2109 pins = "gpio53", "gpio54", "gpio55",
2110 "gpio56";
2111 function = "qup10";
2112 };
2113
2114 config {
2115 pins = "gpio53", "gpio54", "gpio55",
2116 "gpio56";
2117 drive-strength = <6>;
2118 bias-disable;
2119 };
2120 };
2121
2122 qupv3_se10_spi_sleep: qupv3_se10_spi_sleep {
2123 mux {
2124 pins = "gpio53", "gpio54", "gpio55",
2125 "gpio56";
2126 function = "gpio";
2127 };
2128
2129 config {
2130 pins = "gpio53", "gpio54", "gpio55",
2131 "gpio56";
2132 drive-strength = <6>;
2133 bias-disable;
2134 };
2135 };
2136 };
2137
2138 /* SE 11 pin mappings */
2139 qupv3_se11_i2c_pins: qupv3_se11_i2c_pins {
2140 qupv3_se11_i2c_active: qupv3_se11_i2c_active {
2141 mux {
2142 pins = "gpio31", "gpio32";
2143 function = "qup11";
2144 };
2145
2146 config {
2147 pins = "gpio31", "gpio32";
2148 drive-strength = <2>;
2149 bias-disable;
2150 };
2151 };
2152
2153 qupv3_se11_i2c_sleep: qupv3_se11_i2c_sleep {
2154 mux {
2155 pins = "gpio31", "gpio32";
2156 function = "gpio";
2157 };
2158
2159 config {
2160 pins = "gpio31", "gpio32";
2161 drive-strength = <2>;
2162 bias-pull-up;
2163 };
2164 };
2165 };
2166
2167 qupv3_se11_spi_pins: qupv3_se11_spi_pins {
2168 qupv3_se11_spi_active: qupv3_se11_spi_active {
2169 mux {
2170 pins = "gpio31", "gpio32", "gpio33",
2171 "gpio34";
2172 function = "qup11";
2173 };
2174
2175 config {
2176 pins = "gpio31", "gpio32", "gpio33",
2177 "gpio34";
2178 drive-strength = <6>;
2179 bias-disable;
2180 };
2181 };
2182
2183 qupv3_se11_spi_sleep: qupv3_se11_spi_sleep {
2184 mux {
2185 pins = "gpio31", "gpio32", "gpio33",
2186 "gpio34";
2187 function = "gpio";
2188 };
2189
2190 config {
2191 pins = "gpio31", "gpio32", "gpio33",
2192 "gpio34";
2193 drive-strength = <6>;
2194 bias-disable;
2195 };
2196 };
2197 };
2198
2199 /* SE 12 pin mappings */
2200 qupv3_se12_i2c_pins: qupv3_se12_i2c_pins {
2201 qupv3_se12_i2c_active: qupv3_se12_i2c_active {
2202 mux {
2203 pins = "gpio49", "gpio50";
2204 function = "qup12";
2205 };
2206
2207 config {
2208 pins = "gpio49", "gpio50";
2209 drive-strength = <2>;
2210 bias-disable;
2211 };
2212 };
2213
2214 qupv3_se12_i2c_sleep: qupv3_se12_i2c_sleep {
2215 mux {
2216 pins = "gpio49", "gpio50";
2217 function = "gpio";
2218 };
2219
2220 config {
2221 pins = "gpio49", "gpio50";
2222 drive-strength = <2>;
2223 bias-pull-up;
2224 };
2225 };
2226 };
2227
2228 qupv3_se12_spi_pins: qupv3_se12_spi_pins {
2229 qupv3_se12_spi_active: qupv3_se12_spi_active {
2230 mux {
2231 pins = "gpio49", "gpio50", "gpio51",
2232 "gpio52";
2233 function = "qup12";
2234 };
2235
2236 config {
2237 pins = "gpio49", "gpio50", "gpio51",
2238 "gpio52";
2239 drive-strength = <6>;
2240 bias-disable;
2241 };
2242 };
2243
2244 qupv3_se12_spi_sleep: qupv3_se12_spi_sleep {
2245 mux {
2246 pins = "gpio49", "gpio50", "gpio51",
2247 "gpio52";
2248 function = "gpio";
2249 };
2250
2251 config {
2252 pins = "gpio49", "gpio50", "gpio51",
2253 "gpio52";
2254 drive-strength = <6>;
2255 bias-disable;
2256 };
2257 };
2258 };
2259
2260 /* SE 13 pin mappings */
2261 qupv3_se13_i2c_pins: qupv3_se13_i2c_pins {
2262 qupv3_se13_i2c_active: qupv3_se13_i2c_active {
2263 mux {
2264 pins = "gpio105", "gpio106";
2265 function = "qup13";
2266 };
2267
2268 config {
2269 pins = "gpio105", "gpio106";
2270 drive-strength = <2>;
2271 bias-disable;
2272 };
2273 };
2274
2275 qupv3_se13_i2c_sleep: qupv3_se13_i2c_sleep {
2276 mux {
2277 pins = "gpio105", "gpio106";
2278 function = "gpio";
2279 };
2280
2281 config {
2282 pins = "gpio105", "gpio106";
2283 drive-strength = <2>;
2284 bias-pull-up;
2285 };
2286 };
2287 };
2288
2289 qupv3_se13_spi_pins: qupv3_se13_spi_pins {
2290 qupv3_se13_spi_active: qupv3_se13_spi_active {
2291 mux {
2292 pins = "gpio105", "gpio106", "gpio107",
2293 "gpio108";
2294 function = "qup13";
2295 };
2296
2297 config {
2298 pins = "gpio105", "gpio106", "gpio107",
2299 "gpio108";
2300 drive-strength = <6>;
2301 bias-disable;
2302 };
2303 };
2304
2305 qupv3_se13_spi_sleep: qupv3_se13_spi_sleep {
2306 mux {
2307 pins = "gpio105", "gpio106", "gpio107",
2308 "gpio108";
2309 function = "gpio";
2310 };
2311
2312 config {
2313 pins = "gpio105", "gpio106", "gpio107",
2314 "gpio108";
2315 drive-strength = <6>;
2316 bias-disable;
2317 };
2318 };
2319 };
2320
2321 /* SE 14 pin mappings */
2322 qupv3_se14_i2c_pins: qupv3_se14_i2c_pins {
2323 qupv3_se14_i2c_active: qupv3_se14_i2c_active {
2324 mux {
2325 pins = "gpio33", "gpio34";
2326 function = "qup14";
2327 };
2328
2329 config {
2330 pins = "gpio33", "gpio34";
2331 drive-strength = <2>;
2332 bias-disable;
2333 };
2334 };
2335
2336 qupv3_se14_i2c_sleep: qupv3_se14_i2c_sleep {
2337 mux {
2338 pins = "gpio33", "gpio34";
2339 function = "gpio";
2340 };
2341
2342 config {
2343 pins = "gpio33", "gpio34";
2344 drive-strength = <2>;
2345 bias-pull-up;
2346 };
2347 };
2348 };
2349
2350 qupv3_se14_spi_pins: qupv3_se14_spi_pins {
2351 qupv3_se14_spi_active: qupv3_se14_spi_active {
2352 mux {
2353 pins = "gpio31", "gpio32", "gpio33",
2354 "gpio34";
2355 function = "qup14";
2356 };
2357
2358 config {
2359 pins = "gpio31", "gpio32", "gpio33",
2360 "gpio34";
2361 drive-strength = <6>;
2362 bias-disable;
2363 };
2364 };
2365
2366 qupv3_se14_spi_sleep: qupv3_se14_spi_sleep {
2367 mux {
2368 pins = "gpio31", "gpio32", "gpio33",
2369 "gpio34";
2370 function = "gpio";
2371 };
2372
2373 config {
2374 pins = "gpio31", "gpio32", "gpio33",
2375 "gpio34";
2376 drive-strength = <6>;
2377 bias-disable;
2378 };
2379 };
2380 };
2381
2382 /* SE 15 pin mappings */
2383 qupv3_se15_i2c_pins: qupv3_se15_i2c_pins {
2384 qupv3_se15_i2c_active: qupv3_se15_i2c_active {
2385 mux {
2386 pins = "gpio81", "gpio82";
2387 function = "qup15";
2388 };
2389
2390 config {
2391 pins = "gpio81", "gpio82";
2392 drive-strength = <2>;
2393 bias-disable;
2394 };
2395 };
2396
2397 qupv3_se15_i2c_sleep: qupv3_se15_i2c_sleep {
2398 mux {
2399 pins = "gpio81", "gpio82";
2400 function = "gpio";
2401 };
2402
2403 config {
2404 pins = "gpio81", "gpio82";
2405 drive-strength = <2>;
2406 bias-pull-up;
2407 };
2408 };
2409 };
2410
2411 qupv3_se15_spi_pins: qupv3_se15_spi_pins {
2412 qupv3_se15_spi_active: qupv3_se15_spi_active {
2413 mux {
2414 pins = "gpio81", "gpio82", "gpio83",
2415 "gpio84";
2416 function = "qup15";
2417 };
2418
2419 config {
2420 pins = "gpio81", "gpio82", "gpio83",
2421 "gpio84";
2422 drive-strength = <6>;
2423 bias-disable;
2424 };
2425 };
2426
2427 qupv3_se15_spi_sleep: qupv3_se15_spi_sleep {
2428 mux {
2429 pins = "gpio81", "gpio82", "gpio83",
2430 "gpio84";
2431 function = "gpio";
2432 };
2433
2434 config {
2435 pins = "gpio81", "gpio82", "gpio83",
2436 "gpio84";
2437 drive-strength = <6>;
2438 bias-disable;
2439 };
2440 };
2441 };
Jigarkumar Zala861231152017-02-28 14:05:11 -08002442
2443 cci0_active: cci0_active {
2444 mux {
2445 /* CLK, DATA */
2446 pins = "gpio17","gpio18"; // Only 2
2447 function = "cci_i2c";
2448 };
2449
2450 config {
2451 pins = "gpio17","gpio18";
2452 bias-pull-up; /* PULL UP*/
2453 drive-strength = <2>; /* 2 MA */
2454 };
2455 };
2456
2457 cci0_suspend: cci0_suspend {
2458 mux {
2459 /* CLK, DATA */
2460 pins = "gpio17","gpio18";
2461 function = "cci_i2c";
2462 };
2463
2464 config {
2465 pins = "gpio17","gpio18";
2466 bias-pull-down; /* PULL DOWN */
2467 drive-strength = <2>; /* 2 MA */
2468 };
2469 };
2470
2471 cci1_active: cci1_active {
2472 mux {
2473 /* CLK, DATA */
2474 pins = "gpio19","gpio20";
2475 function = "cci_i2c";
2476 };
2477
2478 config {
2479 pins = "gpio19","gpio20";
2480 bias-pull-up; /* PULL UP*/
2481 drive-strength = <2>; /* 2 MA */
2482 };
2483 };
2484
2485 cci1_suspend: cci1_suspend {
2486 mux {
2487 /* CLK, DATA */
2488 pins = "gpio19","gpio20";
2489 function = "cci_i2c";
2490 };
2491
2492 config {
2493 pins = "gpio19","gpio20";
2494 bias-pull-down; /* PULL DOWN */
2495 drive-strength = <2>; /* 2 MA */
2496 };
2497 };
2498
2499 cam_sensor_mclk0_active: cam_sensor_mclk0_active {
2500 /* MCLK0 */
2501 mux {
2502 pins = "gpio13";
2503 function = "cam_mclk";
2504 };
2505
2506 config {
2507 pins = "gpio13";
2508 bias-disable; /* No PULL */
2509 drive-strength = <2>; /* 2 MA */
2510 };
2511 };
2512
2513 cam_sensor_mclk0_suspend: cam_sensor_mclk0_suspend {
2514 /* MCLK0 */
2515 mux {
2516 pins = "gpio13";
2517 function = "cam_mclk";
2518 };
2519
2520 config {
2521 pins = "gpio13";
2522 bias-pull-down; /* PULL DOWN */
2523 drive-strength = <2>; /* 2 MA */
2524 };
2525 };
2526
2527 cam_sensor_rear_active: cam_sensor_rear_active {
2528 /* RESET, AVDD LDO */
2529 mux {
2530 pins = "gpio80","gpio79";
2531 function = "gpio";
2532 };
2533
2534 config {
2535 pins = "gpio80","gpio79";
2536 bias-disable; /* No PULL */
2537 drive-strength = <2>; /* 2 MA */
2538 };
2539 };
2540
2541 cam_sensor_rear_suspend: cam_sensor_rear_suspend {
2542 /* RESET, AVDD LDO */
2543 mux {
2544 pins = "gpio80","gpio79";
2545 function = "gpio";
2546 };
2547
2548 config {
2549 pins = "gpio80","gpio79";
2550 bias-disable; /* No PULL */
2551 drive-strength = <2>; /* 2 MA */
2552 };
2553 };
2554
2555 cam_sensor_mclk1_active: cam_sensor_mclk1_active {
2556 /* MCLK1 */
2557 mux {
2558 pins = "gpio14";
2559 function = "cam_mclk";
2560 };
2561
2562 config {
2563 pins = "gpio14";
2564 bias-disable; /* No PULL */
2565 drive-strength = <2>; /* 2 MA */
2566 };
2567 };
2568
2569 cam_sensor_mclk1_suspend: cam_sensor_mclk1_suspend {
2570 /* MCLK1 */
2571 mux {
2572 pins = "gpio14";
2573 function = "cam_mclk";
2574 };
2575
2576 config {
2577 pins = "gpio14";
2578 bias-pull-down; /* PULL DOWN */
2579 drive-strength = <2>; /* 2 MA */
2580 };
2581 };
2582
2583 cam_sensor_front_active: cam_sensor_front_active {
2584 /* RESET AVDD_LDO*/
2585 mux {
2586 pins = "gpio28", "gpio8";
2587 function = "gpio";
2588 };
2589
2590 config {
2591 pins = "gpio28", "gpio8";
2592 bias-disable; /* No PULL */
2593 drive-strength = <2>; /* 2 MA */
2594 };
2595 };
2596
2597 cam_sensor_front_suspend: cam_sensor_front_suspend {
2598 /* RESET */
2599 mux {
2600 pins = "gpio28";
2601 function = "gpio";
2602 };
2603
2604 config {
2605 pins = "gpio28";
2606 bias-disable; /* No PULL */
2607 drive-strength = <2>; /* 2 MA */
2608 };
2609 };
2610
2611 cam_sensor_mclk2_active: cam_sensor_mclk2_active {
2612 /* MCLK1 */
2613 mux {
2614 /* CLK, DATA */
2615 pins = "gpio15";
2616 function = "cam_mclk";
2617 };
2618
2619 config {
2620 pins = "gpio15";
2621 bias-disable; /* No PULL */
2622 drive-strength = <2>; /* 2 MA */
2623 };
2624 };
2625
2626 cam_sensor_mclk2_suspend: cam_sensor_mclk2_suspend {
2627 /* MCLK1 */
2628 mux {
2629 /* CLK, DATA */
2630 pins = "gpio15";
2631 function = "cam_mclk";
2632 };
2633
2634 config {
2635 pins = "gpio15";
2636 bias-pull-down; /* PULL DOWN */
2637 drive-strength = <2>; /* 2 MA */
2638 };
2639 };
2640
2641 cam_sensor_rear2_active: cam_sensor_rear2_active {
2642 /* RESET, STANDBY */
2643 mux {
2644 pins = "gpio9","gpio8";
2645 function = "gpio";
2646 };
2647
2648 config {
2649 pins = "gpio9","gpio8";
2650 bias-disable; /* No PULL */
2651 drive-strength = <2>; /* 2 MA */
2652 };
2653 };
2654
2655 cam_sensor_rear2_suspend: cam_sensor_rear2_suspend {
2656 /* RESET, STANDBY */
2657 mux {
2658 pins = "gpio9","gpio8";
2659 function = "gpio";
2660 };
2661 config {
2662 pins = "gpio9","gpio8";
2663 bias-disable; /* No PULL */
2664 drive-strength = <2>; /* 2 MA */
2665 };
2666 };
Satyajit Desaie4508132017-04-05 17:15:22 -07002667
2668 trigout_a: trigout_a {
2669 mux {
2670 pins = "gpio62", "gpio51";
2671 function = "qdss_cti";
2672 };
2673 config {
2674 pins = "gpio62", "gpio51";
2675 drive-strength = <2>;
2676 bias-disable;
2677 };
2678 };
Kyle Yan679cbee2016-07-27 16:55:20 -07002679 };
2680};
David Collinsc6686252017-03-31 14:23:09 -07002681
2682&pm8998_gpios {
2683 key_home {
2684 key_home_default: key_home_default {
2685 pins = "gpio5";
2686 function = "normal";
2687 input-enable;
2688 bias-pull-up;
2689 power-source = <0>;
2690 };
2691 };
2692
2693 key_vol_up {
2694 key_vol_up_default: key_vol_up_default {
2695 pins = "gpio6";
2696 function = "normal";
2697 input-enable;
2698 bias-pull-up;
2699 power-source = <0>;
2700 };
2701 };
2702
2703 key_cam_snapshot {
2704 key_cam_snapshot_default: key_cam_snapshot_default {
2705 pins = "gpio7";
2706 function = "normal";
2707 input-enable;
2708 bias-pull-up;
2709 power-source = <0>;
2710 };
2711 };
2712
2713 key_cam_focus {
2714 key_cam_focus_default: key_cam_focus_default {
2715 pins = "gpio8";
2716 function = "normal";
2717 input-enable;
2718 bias-pull-up;
2719 power-source = <0>;
2720 };
2721 };
Jigarkumar Zala861231152017-02-28 14:05:11 -08002722
2723 camera_dvdd_en {
2724 camera_dvdd_en_default: camera_dvdd_en_default {
2725 pins = "gpio9";
2726 function = "normal";
2727 power-source = <0>;
2728 output-low;
2729 };
2730 };
2731
2732 camera_rear_dvdd_en {
2733 camera_rear_dvdd_en_default: camera_rear_dvdd_en_default {
2734 pins = "gpio12";
2735 function = "normal";
2736 power-source = <0>;
2737 output-low;
2738 };
2739 };
David Collinsc6686252017-03-31 14:23:09 -07002740};
Jack Phamc2160c842017-04-05 09:48:59 -07002741
2742&pmi8998_gpios {
2743 usb2_vbus_boost {
2744 usb2_vbus_boost_default: usb2_vbus_boost_default {
2745 pins = "gpio2";
2746 function = "normal";
2747 output-low;
2748 power-source = <0>;
2749 };
2750 };
2751
2752 usb2_vbus_det {
2753 usb2_vbus_det_default: usb2_vbus_det_default {
2754 pins = "gpio8";
2755 function = "normal";
2756 input-enable;
2757 bias-pull-down;
2758 power-source = <1>; /* VPH input supply */
2759 };
2760 };
2761
2762 usb2_id_det {
2763 usb2_id_det_default: usb2_id_det_default {
2764 pins = "gpio9";
2765 function = "normal";
2766 input-enable;
2767 bias-pull-up;
2768 power-source = <0>;
2769 };
2770 };
2771};