blob: 4f74a97f91c47f3448ff61abf12a5bd2bc74d107 [file] [log] [blame]
Banajit Goswamib016de92017-02-15 21:02:30 -08001/* Copyright (c) 2016-2017, The Linux Foundation. All rights reserved.
Kyle Yan679cbee2016-07-27 16:55:20 -07002 *
3 * This program is free software; you can redistribute it and/or modify
4 * it under the terms of the GNU General Public License version 2 and
5 * only version 2 as published by the Free Software Foundation.
6 *
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
11 */
12
13&soc {
Channagoud Kadabieb7f0112017-04-03 20:39:27 -070014 tlmm: pinctrl@03400000 {
Kyle Yan6a20fae2017-02-14 13:34:41 -080015 compatible = "qcom,sdm845-pinctrl";
Channagoud Kadabieb7f0112017-04-03 20:39:27 -070016 reg = <0x03400000 0xc00000>;
Kyle Yan679cbee2016-07-27 16:55:20 -070017 interrupts = <0 208 0>;
18 gpio-controller;
19 #gpio-cells = <2>;
20 interrupt-controller;
21 #interrupt-cells = <2>;
Archana Sathyakumar00a36ab2017-03-03 14:38:26 -070022 interrupt-parent = <&pdc>;
Banajit Goswamib016de92017-02-15 21:02:30 -080023
Subhash Jadavaniafe2a792017-03-31 21:08:29 -070024 ufs_dev_reset_assert: ufs_dev_reset_assert {
25 config {
26 pins = "ufs_reset";
27 bias-pull-down; /* default: pull down */
28 /*
29 * UFS_RESET driver strengths are having
30 * different values/steps compared to typical
31 * GPIO drive strengths.
32 *
33 * Following table clarifies:
34 *
35 * HDRV value | UFS_RESET | Typical GPIO
36 * (dec) | (mA) | (mA)
37 * 0 | 0.8 | 2
38 * 1 | 1.55 | 4
39 * 2 | 2.35 | 6
40 * 3 | 3.1 | 8
41 * 4 | 3.9 | 10
42 * 5 | 4.65 | 12
43 * 6 | 5.4 | 14
44 * 7 | 6.15 | 16
45 *
46 * POR value for UFS_RESET HDRV is 3 which means
47 * 3.1mA and we want to use that. Hence just
48 * specify 8mA to "drive-strength" binding and
49 * that should result into writing 3 to HDRV
50 * field.
51 */
52 drive-strength = <8>; /* default: 3.1 mA */
53 output-low; /* active low reset */
54 };
55 };
56
57 ufs_dev_reset_deassert: ufs_dev_reset_deassert {
58 config {
59 pins = "ufs_reset";
60 bias-pull-down; /* default: pull down */
61 /*
62 * default: 3.1 mA
63 * check comments under ufs_dev_reset_assert
64 */
65 drive-strength = <8>;
66 output-high; /* active low reset */
67 };
68 };
69
Subbaraman Narayanamurthycd21c812017-03-30 18:36:49 -070070 flash_led3_front {
71 flash_led3_front_en: flash_led3_front_en {
72 mux {
73 pins = "gpio21";
Subbaraman Narayanamurthy58377f02017-03-21 20:38:43 -070074 function = "gpio";
75 };
76
77 config {
78 pins = "gpio21";
Subbaraman Narayanamurthycd21c812017-03-30 18:36:49 -070079 drive_strength = <2>;
80 output-high;
Subbaraman Narayanamurthy58377f02017-03-21 20:38:43 -070081 bias-disable;
Subbaraman Narayanamurthycd21c812017-03-30 18:36:49 -070082 };
83 };
84
85 flash_led3_front_dis: flash_led3_front_dis {
86 mux {
87 pins = "gpio21";
Subbaraman Narayanamurthy58377f02017-03-21 20:38:43 -070088 function = "gpio";
89 };
90
91 config {
92 pins = "gpio21";
Subbaraman Narayanamurthycd21c812017-03-30 18:36:49 -070093 drive_strength = <2>;
94 output-low;
Subbaraman Narayanamurthy58377f02017-03-21 20:38:43 -070095 bias-disable;
Subbaraman Narayanamurthycd21c812017-03-30 18:36:49 -070096 };
97 };
98 };
Subhash Jadavaniafe2a792017-03-31 21:08:29 -070099
Banajit Goswamib016de92017-02-15 21:02:30 -0800100 wcd9xxx_intr {
101 wcd_intr_default: wcd_intr_default{
102 mux {
103 pins = "gpio54";
104 function = "gpio";
105 };
106
107 config {
108 pins = "gpio54";
109 drive-strength = <2>; /* 2 mA */
110 bias-pull-down; /* pull down */
111 input-enable;
112 };
113 };
114 };
115
Subhash Jadavanidd416c42017-05-15 11:54:10 -0700116 storage_cd: storage_cd {
117 mux {
118 pins = "gpio126";
119 function = "gpio";
120 };
121
122 config {
123 pins = "gpio126";
124 bias-pull-up; /* pull up */
125 drive-strength = <2>; /* 2 MA */
126 };
127 };
128
Xiaonian Wang898e0902017-04-08 06:46:29 +0800129 sdc2_clk_on: sdc2_clk_on {
130 config {
131 pins = "sdc2_clk";
132 bias-disable; /* NO pull */
133 drive-strength = <16>; /* 16 MA */
134 };
135 };
136
137 sdc2_clk_off: sdc2_clk_off {
138 config {
139 pins = "sdc2_clk";
140 bias-disable; /* NO pull */
141 drive-strength = <2>; /* 2 MA */
142 };
143 };
144
145 sdc2_cmd_on: sdc2_cmd_on {
146 config {
147 pins = "sdc2_cmd";
148 bias-pull-up; /* pull up */
149 drive-strength = <10>; /* 10 MA */
150 };
151 };
152
153 sdc2_cmd_off: sdc2_cmd_off {
154 config {
155 pins = "sdc2_cmd";
156 bias-pull-up; /* pull up */
157 drive-strength = <2>; /* 2 MA */
158 };
159 };
160
161 sdc2_data_on: sdc2_data_on {
162 config {
163 pins = "sdc2_data";
164 bias-pull-up; /* pull up */
165 drive-strength = <10>; /* 10 MA */
166 };
167 };
168
169 sdc2_data_off: sdc2_data_off {
170 config {
171 pins = "sdc2_data";
172 bias-pull-up; /* pull up */
173 drive-strength = <2>; /* 2 MA */
174 };
175 };
176
Tony Truongc0e0a5f02017-03-15 11:57:40 -0700177 pcie0 {
178 pcie0_clkreq_default: pcie0_clkreq_default {
179 mux {
180 pins = "gpio36";
181 function = "pci_e0";
182 };
183
184 config {
185 pins = "gpio36";
186 drive-strength = <2>;
187 bias-pull-up;
188 };
189 };
190
191 pcie0_perst_default: pcie0_perst_default {
192 mux {
193 pins = "gpio35";
194 function = "gpio";
195 };
196
197 config {
198 pins = "gpio35";
199 drive-strength = <2>;
200 bias-pull-down;
201 };
202 };
203
204 pcie0_wake_default: pcie0_wake_default {
205 mux {
206 pins = "gpio37";
207 function = "gpio";
208 };
209
210 config {
211 pins = "gpio37";
212 drive-strength = <2>;
213 bias-pull-down;
214 };
215 };
216 };
217
Banajit Goswamib016de92017-02-15 21:02:30 -0800218 cdc_reset_ctrl {
219 cdc_reset_sleep: cdc_reset_sleep {
220 mux {
221 pins = "gpio64";
222 function = "gpio";
223 };
224 config {
225 pins = "gpio64";
226 drive-strength = <2>;
227 bias-disable;
228 output-low;
229 };
230 };
231
232 cdc_reset_active:cdc_reset_active {
233 mux {
234 pins = "gpio64";
235 function = "gpio";
236 };
237 config {
238 pins = "gpio64";
239 drive-strength = <8>;
240 bias-pull-down;
241 output-high;
242 };
243 };
244 };
245
246 spkr_i2s_clk_pin {
247 spkr_i2s_clk_sleep: spkr_i2s_clk_sleep {
248 mux {
249 pins = "gpio69";
250 function = "spkr_i2s";
251 };
252
253 config {
254 pins = "gpio69";
255 drive-strength = <2>; /* 2 mA */
256 bias-pull-down; /* PULL DOWN */
257 };
258 };
259
260 spkr_i2s_clk_active: spkr_i2s_clk_active {
261 mux {
262 pins = "gpio69";
263 function = "spkr_i2s";
264 };
265
266 config {
267 pins = "gpio69";
268 drive-strength = <8>; /* 8 mA */
269 bias-disable; /* NO PULL */
270 };
271 };
272 };
273
274 wcd_gnd_mic_swap {
275 wcd_gnd_mic_swap_idle: wcd_gnd_mic_swap_idle {
276 mux {
277 pins = "gpio51";
278 function = "gpio";
279 };
280 config {
281 pins = "gpio51";
282 drive-strength = <2>;
283 bias-pull-down;
284 output-low;
285 };
286 };
287
288 wcd_gnd_mic_swap_active: wcd_gnd_mic_swap_active {
289 mux {
290 pins = "gpio51";
291 function = "gpio";
292 };
293 config {
294 pins = "gpio51";
295 drive-strength = <2>;
296 bias-disable;
297 output-high;
298 };
299 };
300 };
301
Karthikeyan Mani5bce47c2017-05-26 15:19:04 -0700302 /* USB C analog configuration */
303 wcd_usbc_analog_en1 {
304 wcd_usbc_analog_en1_idle: wcd_usbc_ana_en1_idle {
305 mux {
306 pins = "gpio49";
307 function = "gpio";
308 };
309 config {
310 pins = "gpio49";
311 drive-strength = <2>;
312 bias-pull-down;
313 output-low;
314 };
315 };
316
317 wcd_usbc_analog_en1_active: wcd_usbc_ana_en1_active {
318 mux {
319 pins = "gpio49";
320 function = "gpio";
321 };
322 config {
323 pins = "gpio49";
324 drive-strength = <2>;
325 bias-disable;
326 output-high;
327 };
328 };
329 };
330
331 wcd_usbc_analog_en2 {
332 wcd_usbc_analog_en2_idle: wcd_usbc_ana_en2_idle {
333 mux {
334 pins = "gpio51";
335 function = "gpio";
336 };
337 config {
338 pins = "gpio51";
339 drive-strength = <2>;
340 bias-pull-down;
341 output-low;
342 };
343 };
344
345 wcd_usbc_analog_en2_active: wcd_usbc_ana_en2_active {
346 mux {
347 pins = "gpio51";
348 function = "gpio";
349 };
350 config {
351 pins = "gpio51";
352 drive-strength = <2>;
353 bias-disable;
354 output-high;
355 };
356 };
357 };
358
Banajit Goswamib016de92017-02-15 21:02:30 -0800359 pri_aux_pcm_clk {
360 pri_aux_pcm_clk_sleep: pri_aux_pcm_clk_sleep {
361 mux {
362 pins = "gpio65";
363 function = "gpio";
364 };
365
366 config {
367 pins = "gpio65";
368 drive-strength = <2>; /* 2 mA */
369 bias-pull-down; /* PULL DOWN */
370 input-enable;
371 };
372 };
373
374 pri_aux_pcm_clk_active: pri_aux_pcm_clk_active {
375 mux {
376 pins = "gpio65";
377 function = "pri_mi2s";
378 };
379
380 config {
381 pins = "gpio65";
382 drive-strength = <8>; /* 8 mA */
383 bias-disable; /* NO PULL */
384 output-high;
385 };
386 };
387 };
388
389 pri_aux_pcm_sync {
390 pri_aux_pcm_sync_sleep: pri_aux_pcm_sync_sleep {
391 mux {
392 pins = "gpio66";
393 function = "gpio";
394 };
395
396 config {
397 pins = "gpio66";
398 drive-strength = <2>; /* 2 mA */
399 bias-pull-down; /* PULL DOWN */
400 input-enable;
401 };
402 };
403
404 pri_aux_pcm_sync_active: pri_aux_pcm_sync_active {
405 mux {
406 pins = "gpio66";
407 function = "pri_mi2s_ws";
408 };
409
410 config {
411 pins = "gpio66";
412 drive-strength = <8>; /* 8 mA */
413 bias-disable; /* NO PULL */
414 output-high;
415 };
416 };
417 };
418
419 pri_aux_pcm_din {
420 pri_aux_pcm_din_sleep: pri_aux_pcm_din_sleep {
421 mux {
422 pins = "gpio67";
423 function = "gpio";
424 };
425
426 config {
427 pins = "gpio67";
428 drive-strength = <2>; /* 2 mA */
429 bias-pull-down; /* PULL DOWN */
430 input-enable;
431 };
432 };
433
434 pri_aux_pcm_din_active: pri_aux_pcm_din_active {
435 mux {
436 pins = "gpio67";
437 function = "pri_mi2s";
438 };
439
440 config {
441 pins = "gpio67";
442 drive-strength = <8>; /* 8 mA */
443 bias-disable; /* NO PULL */
444 };
445 };
446 };
447
448 pri_aux_pcm_dout {
449 pri_aux_pcm_dout_sleep: pri_aux_pcm_dout_sleep {
450 mux {
451 pins = "gpio68";
452 function = "gpio";
453 };
454
455 config {
456 pins = "gpio68";
457 drive-strength = <2>; /* 2 mA */
458 bias-pull-down; /* PULL DOWN */
459 input-enable;
460 };
461 };
462
463 pri_aux_pcm_dout_active: pri_aux_pcm_dout_active {
464 mux {
465 pins = "gpio68";
466 function = "pri_mi2s";
467 };
468
469 config {
470 pins = "gpio68";
471 drive-strength = <8>; /* 8 mA */
472 bias-disable; /* NO PULL */
473 };
474 };
475 };
476
Shashank Babu Chinta Venkata2f40bc72017-03-21 15:31:38 -0700477 pmx_sde: pmx_sde {
478 sde_dsi_active: sde_dsi_active {
479 mux {
480 pins = "gpio6", "gpio52";
481 function = "gpio";
482 };
483
484 config {
485 pins = "gpio6", "gpio52";
486 drive-strength = <8>; /* 8 mA */
487 bias-disable = <0>; /* no pull */
488 };
489 };
490 sde_dsi_suspend: sde_dsi_suspend {
491 mux {
492 pins = "gpio6", "gpio52";
493 function = "gpio";
494 };
495
496 config {
497 pins = "gpio6", "gpio52";
498 drive-strength = <2>; /* 2 mA */
499 bias-pull-down; /* PULL DOWN */
500 };
501 };
502 };
503
504 pmx_sde_te {
505 sde_te_active: sde_te_active {
506 mux {
507 pins = "gpio10";
508 function = "mdp_vsync";
509 };
510
511 config {
512 pins = "gpio10";
513 drive-strength = <2>; /* 2 mA */
514 bias-pull-down; /* PULL DOWN */
515 };
516 };
517
518 sde_te_suspend: sde_te_suspend {
519 mux {
520 pins = "gpio10";
521 function = "mdp_vsync";
522 };
523
524 config {
525 pins = "gpio10";
526 drive-strength = <2>; /* 2 mA */
527 bias-pull-down; /* PULL DOWN */
528 };
529 };
530 };
531
Padmanabhan Komanduru887085e2017-05-02 14:57:12 -0700532 sde_dp_aux_active: sde_dp_aux_active {
533 mux {
534 pins = "gpio43", "gpio51";
535 function = "gpio";
536 };
537
538 config {
539 pins = "gpio43", "gpio51";
540 bias-disable = <0>; /* no pull */
541 drive-strength = <8>;
542 };
543 };
544
545 sde_dp_aux_suspend: sde_dp_aux_suspend {
546 mux {
547 pins = "gpio43", "gpio51";
548 function = "gpio";
549 };
550
551 config {
552 pins = "gpio43", "gpio51";
553 bias-pull-down;
554 drive-strength = <2>;
555 };
556 };
557
558 sde_dp_usbplug_cc_active: sde_dp_usbplug_cc_active {
559 mux {
560 pins = "gpio38";
561 function = "gpio";
562 };
563
564 config {
565 pins = "gpio38";
566 bias-disable;
567 drive-strength = <16>;
568 };
569 };
570
571 sde_dp_usbplug_cc_suspend: sde_dp_usbplug_cc_suspend {
572 mux {
573 pins = "gpio38";
574 function = "gpio";
575 };
576
577 config {
578 pins = "gpio38";
579 bias-pull-down;
580 drive-strength = <2>;
581 };
582 };
583
Banajit Goswamib016de92017-02-15 21:02:30 -0800584 sec_aux_pcm {
585 sec_aux_pcm_sleep: sec_aux_pcm_sleep {
586 mux {
587 pins = "gpio80", "gpio81";
588 function = "gpio";
589 };
590
591 config {
592 pins = "gpio80", "gpio81";
593 drive-strength = <2>; /* 2 mA */
594 bias-pull-down; /* PULL DOWN */
595 input-enable;
596 };
597 };
598
599 sec_aux_pcm_active: sec_aux_pcm_active {
600 mux {
601 pins = "gpio80", "gpio81";
602 function = "sec_mi2s";
603 };
604
605 config {
606 pins = "gpio80", "gpio81";
607 drive-strength = <8>; /* 8 mA */
608 bias-disable; /* NO PULL */
609 };
610 };
611 };
612
613 sec_aux_pcm_din {
614 sec_aux_pcm_din_sleep: sec_aux_pcm_din_sleep {
615 mux {
616 pins = "gpio82";
617 function = "gpio";
618 };
619
620 config {
621 pins = "gpio82";
622 drive-strength = <2>; /* 2 mA */
623 bias-pull-down; /* PULL DOWN */
624 input-enable;
625 };
626 };
627
628 sec_aux_pcm_din_active: sec_aux_pcm_din_active {
629 mux {
630 pins = "gpio82";
631 function = "sec_mi2s";
632 };
633
634 config {
635 pins = "gpio82";
636 drive-strength = <8>; /* 8 mA */
637 bias-disable; /* NO PULL */
638 };
639 };
640 };
641
642 sec_aux_pcm_dout {
643 sec_aux_pcm_dout_sleep: sec_aux_pcm_dout_sleep {
644 mux {
645 pins = "gpio83";
646 function = "gpio";
647 };
648
649 config {
650 pins = "gpio83";
651 drive-strength = <2>; /* 2 mA */
652 bias-pull-down; /* PULL DOWN */
653 input-enable;
654 };
655 };
656
657 sec_aux_pcm_dout_active: sec_aux_pcm_dout_active {
658 mux {
659 pins = "gpio83";
660 function = "sec_mi2s";
661 };
662
663 config {
664 pins = "gpio83";
665 drive-strength = <8>; /* 8 mA */
666 bias-disable; /* NO PULL */
667 };
668 };
669 };
670
671 tert_aux_pcm {
672 tert_aux_pcm_sleep: tert_aux_pcm_sleep {
673 mux {
674 pins = "gpio75", "gpio76";
675 function = "gpio";
676 };
677
678 config {
679 pins = "gpio75", "gpio76";
680 drive-strength = <2>; /* 2 mA */
681 bias-pull-down; /* PULL DOWN */
682 input-enable;
683 };
684 };
685
686 tert_aux_pcm_active: tert_aux_pcm_active {
687 mux {
688 pins = "gpio75", "gpio76";
689 function = "ter_mi2s";
690 };
691
692 config {
693 pins = "gpio75", "gpio76";
694 drive-strength = <8>; /* 8 mA */
695 bias-disable; /* NO PULL */
696 output-high;
697 };
698 };
699 };
700
701 tert_aux_pcm_din {
702 tert_aux_pcm_din_sleep: tert_aux_pcm_din_sleep {
703 mux {
704 pins = "gpio77";
705 function = "gpio";
706 };
707
708 config {
709 pins = "gpio77";
710 drive-strength = <2>; /* 2 mA */
711 bias-pull-down; /* PULL DOWN */
712 input-enable;
713 };
714 };
715
716 tert_aux_pcm_din_active: tert_aux_pcm_din_active {
717 mux {
718 pins = "gpio77";
719 function = "ter_mi2s";
720 };
721
722 config {
723 pins = "gpio77";
724 drive-strength = <8>; /* 8 mA */
725 bias-disable; /* NO PULL */
726 };
727 };
728 };
729
730 tert_aux_pcm_dout {
731 tert_aux_pcm_dout_sleep: tert_aux_pcm_dout_sleep {
732 mux {
733 pins = "gpio78";
734 function = "gpio";
735 };
736
737 config {
738 pins = "gpio78";
739 drive-strength = <2>; /* 2 mA */
740 bias-pull-down; /* PULL DOWN */
741 input-enable;
742 };
743 };
744
745 tert_aux_pcm_dout_active: tert_aux_pcm_dout_active {
746 mux {
747 pins = "gpio78";
748 function = "ter_mi2s";
749 };
750
751 config {
752 pins = "gpio78";
753 drive-strength = <8>; /* 8 mA */
754 bias-disable; /* NO PULL */
755 };
756 };
757 };
758
759 quat_aux_pcm {
760 quat_aux_pcm_sleep: quat_aux_pcm_sleep {
761 mux {
762 pins = "gpio58", "gpio59";
763 function = "gpio";
764 };
765
766 config {
767 pins = "gpio58", "gpio59";
768 drive-strength = <2>; /* 2 mA */
769 bias-pull-down; /* PULL DOWN */
770 input-enable;
771 };
772 };
773
774 quat_aux_pcm_active: quat_aux_pcm_active {
775 mux {
776 pins = "gpio58", "gpio59";
777 function = "qua_mi2s";
778 };
779
780 config {
781 pins = "gpio58", "gpio59";
782 drive-strength = <8>; /* 8 mA */
783 bias-disable; /* NO PULL */
784 output-high;
785 };
786 };
787 };
788
789 quat_aux_pcm_din {
790 quat_aux_pcm_din_sleep: quat_aux_pcm_din_sleep {
791 mux {
792 pins = "gpio60";
793 function = "gpio";
794 };
795
796 config {
797 pins = "gpio60";
798 drive-strength = <2>; /* 2 mA */
799 bias-pull-down; /* PULL DOWN */
800 input-enable;
801 };
802 };
803
804 quat_aux_pcm_din_active: quat_aux_pcm_din_active {
805 mux {
806 pins = "gpio60";
807 function = "qua_mi2s";
808 };
809
810 config {
811 pins = "gpio60";
812 drive-strength = <8>; /* 8 mA */
813 bias-disable; /* NO PULL */
814 };
815 };
816 };
817
818 quat_aux_pcm_dout {
819 quat_aux_pcm_dout_sleep: quat_aux_pcm_dout_sleep {
820 mux {
821 pins = "gpio61";
822 function = "gpio";
823 };
824
825 config {
826 pins = "gpio61";
827 drive-strength = <2>; /* 2 mA */
828 bias-pull-down; /* PULL DOWN */
829 input-enable;
830 };
831 };
832
833 quat_aux_pcm_dout_active: quat_aux_pcm_dout_active {
834 mux {
835 pins = "gpio61";
836 function = "qua_mi2s";
837 };
838
839 config {
840 pins = "gpio61";
841 drive-strength = <8>; /* 8 mA */
842 bias-disable; /* NO PULL */
843 };
844 };
845 };
846
847 pri_mi2s_mclk {
848 pri_mi2s_mclk_sleep: pri_mi2s_mclk_sleep {
849 mux {
850 pins = "gpio64";
851 function = "gpio";
852 };
853
854 config {
855 pins = "gpio64";
856 drive-strength = <2>; /* 2 mA */
857 bias-pull-down; /* PULL DOWN */
858 input-enable;
859 };
860 };
861
862 pri_mi2s_mclk_active: pri_mi2s_mclk_active {
863 mux {
864 pins = "gpio64";
865 function = "pri_mi2s";
866 };
867
868 config {
869 pins = "gpio64";
870 drive-strength = <8>; /* 8 mA */
871 bias-disable; /* NO PULL */
872 output-high;
873 };
874 };
875 };
876
877 pri_mi2s_sck {
878 pri_mi2s_sck_sleep: pri_mi2s_sck_sleep {
879 mux {
880 pins = "gpio65";
881 function = "gpio";
882 };
883
884 config {
885 pins = "gpio65";
886 drive-strength = <2>; /* 2 mA */
887 bias-pull-down; /* PULL DOWN */
888 input-enable;
889 };
890 };
891
892 pri_mi2s_sck_active: pri_mi2s_sck_active {
893 mux {
894 pins = "gpio65";
895 function = "pri_mi2s";
896 };
897
898 config {
899 pins = "gpio65";
900 drive-strength = <8>; /* 8 mA */
901 bias-disable; /* NO PULL */
902 output-high;
903 };
904 };
905 };
906
907 pri_mi2s_ws {
908 pri_mi2s_ws_sleep: pri_mi2s_ws_sleep {
909 mux {
910 pins = "gpio66";
911 function = "gpio";
912 };
913
914 config {
915 pins = "gpio66";
916 drive-strength = <2>; /* 2 mA */
917 bias-pull-down; /* PULL DOWN */
918 input-enable;
919 };
920 };
921
922 pri_mi2s_ws_active: pri_mi2s_ws_active {
923 mux {
924 pins = "gpio66";
925 function = "pri_mi2s_ws";
926 };
927
928 config {
929 pins = "gpio66";
930 drive-strength = <8>; /* 8 mA */
931 bias-disable; /* NO PULL */
932 output-high;
933 };
934 };
935 };
936
937 pri_mi2s_sd0 {
938 pri_mi2s_sd0_sleep: pri_mi2s_sd0_sleep {
939 mux {
940 pins = "gpio67";
941 function = "gpio";
942 };
943
944 config {
945 pins = "gpio67";
946 drive-strength = <2>; /* 2 mA */
947 bias-pull-down; /* PULL DOWN */
948 input-enable;
949 };
950 };
951
952 pri_mi2s_sd0_active: pri_mi2s_sd0_active {
953 mux {
954 pins = "gpio67";
955 function = "pri_mi2s";
956 };
957
958 config {
959 pins = "gpio67";
960 drive-strength = <8>; /* 8 mA */
961 bias-disable; /* NO PULL */
962 };
963 };
964 };
965
966 pri_mi2s_sd1 {
967 pri_mi2s_sd1_sleep: pri_mi2s_sd1_sleep {
968 mux {
969 pins = "gpio68";
970 function = "gpio";
971 };
972
973 config {
974 pins = "gpio68";
975 drive-strength = <2>; /* 2 mA */
976 bias-pull-down; /* PULL DOWN */
977 input-enable;
978 };
979 };
980
981 pri_mi2s_sd1_active: pri_mi2s_sd1_active {
982 mux {
983 pins = "gpio68";
984 function = "pri_mi2s";
985 };
986
987 config {
988 pins = "gpio68";
989 drive-strength = <8>; /* 8 mA */
990 bias-disable; /* NO PULL */
991 };
992 };
993 };
994
995 sec_mi2s_mclk {
996 sec_mi2s_mclk_sleep: sec_mi2s_mclk_sleep {
997 mux {
998 pins = "gpio79";
999 function = "gpio";
1000 };
1001
1002 config {
1003 pins = "gpio79";
1004 drive-strength = <2>; /* 2 mA */
1005 bias-pull-down; /* PULL DOWN */
1006 input-enable;
1007 };
1008 };
1009
1010 sec_mi2s_mclk_active: sec_mi2s_mclk_active {
1011 mux {
1012 pins = "gpio79";
1013 function = "sec_mi2s";
1014 };
1015
1016 config {
1017 pins = "gpio79";
1018 drive-strength = <8>; /* 8 mA */
1019 bias-disable; /* NO PULL */
1020 };
1021 };
1022 };
1023
1024 sec_mi2s {
1025 sec_mi2s_sleep: sec_mi2s_sleep {
1026 mux {
1027 pins = "gpio80", "gpio81";
1028 function = "gpio";
1029 };
1030
1031 config {
1032 pins = "gpio80", "gpio81";
1033 drive-strength = <2>; /* 2 mA */
1034 bias-disable; /* NO PULL */
1035 input-enable;
1036 };
1037 };
1038
1039 sec_mi2s_active: sec_mi2s_active {
1040 mux {
1041 pins = "gpio80", "gpio81";
1042 function = "sec_mi2s";
1043 };
1044
1045 config {
1046 pins = "gpio80", "gpio81";
1047 drive-strength = <8>; /* 8 mA */
1048 bias-disable; /* NO PULL */
1049 };
1050 };
1051 };
1052
1053 sec_mi2s_sd0 {
1054 sec_mi2s_sd0_sleep: sec_mi2s_sd0_sleep {
1055 mux {
1056 pins = "gpio82";
1057 function = "gpio";
1058 };
1059
1060 config {
1061 pins = "gpio82";
1062 drive-strength = <2>; /* 2 mA */
1063 bias-pull-down; /* PULL DOWN */
1064 input-enable;
1065 };
1066 };
1067
1068 sec_mi2s_sd0_active: sec_mi2s_sd0_active {
1069 mux {
1070 pins = "gpio82";
1071 function = "sec_mi2s";
1072 };
1073
1074 config {
1075 pins = "gpio82";
1076 drive-strength = <8>; /* 8 mA */
1077 bias-disable; /* NO PULL */
1078 };
1079 };
1080 };
1081
1082 sec_mi2s_sd1 {
1083 sec_mi2s_sd1_sleep: sec_mi2s_sd1_sleep {
1084 mux {
1085 pins = "gpio83";
1086 function = "gpio";
1087 };
1088
1089 config {
1090 pins = "gpio83";
1091 drive-strength = <2>; /* 2 mA */
1092 bias-pull-down; /* PULL DOWN */
1093 input-enable;
1094 };
1095 };
1096
1097 sec_mi2s_sd1_active: sec_mi2s_sd1_active {
1098 mux {
1099 pins = "gpio83";
1100 function = "sec_mi2s";
1101 };
1102
1103 config {
1104 pins = "gpio83";
1105 drive-strength = <8>; /* 8 mA */
1106 bias-disable; /* NO PULL */
1107 };
1108 };
1109 };
1110
1111 tert_mi2s_mclk {
1112 tert_mi2s_mclk_sleep: tert_mi2s_mclk_sleep {
1113 mux {
1114 pins = "gpio74";
1115 function = "gpio";
1116 };
1117
1118 config {
1119 pins = "gpio74";
1120 drive-strength = <2>; /* 2 mA */
1121 bias-pull-down; /* PULL DOWN */
1122 input-enable;
1123 };
1124 };
1125
1126 tert_mi2s_mclk_active: tert_mi2s_mclk_active {
1127 mux {
1128 pins = "gpio74";
1129 function = "ter_mi2s";
1130 };
1131
1132 config {
1133 pins = "gpio74";
1134 drive-strength = <8>; /* 8 mA */
1135 bias-disable; /* NO PULL */
1136 };
1137 };
1138 };
1139
1140 tert_mi2s {
1141 tert_mi2s_sleep: tert_mi2s_sleep {
1142 mux {
1143 pins = "gpio75", "gpio76";
1144 function = "gpio";
1145 };
1146
1147 config {
1148 pins = "gpio75", "gpio76";
1149 drive-strength = <2>; /* 2 mA */
1150 bias-pull-down; /* PULL DOWN */
1151 input-enable;
1152 };
1153 };
1154
1155 tert_mi2s_active: tert_mi2s_active {
1156 mux {
1157 pins = "gpio75", "gpio76";
1158 function = "ter_mi2s";
1159 };
1160
1161 config {
1162 pins = "gpio75", "gpio76";
1163 drive-strength = <8>; /* 8 mA */
1164 bias-disable; /* NO PULL */
1165 output-high;
1166 };
1167 };
1168 };
1169
1170 tert_mi2s_sd0 {
1171 tert_mi2s_sd0_sleep: tert_mi2s_sd0_sleep {
1172 mux {
1173 pins = "gpio77";
1174 function = "gpio";
1175 };
1176
1177 config {
1178 pins = "gpio77";
1179 drive-strength = <2>; /* 2 mA */
1180 bias-pull-down; /* PULL DOWN */
1181 input-enable;
1182 };
1183 };
1184
1185 tert_mi2s_sd0_active: tert_mi2s_sd0_active {
1186 mux {
1187 pins = "gpio77";
1188 function = "ter_mi2s";
1189 };
1190
1191 config {
1192 pins = "gpio77";
1193 drive-strength = <8>; /* 8 mA */
1194 bias-disable; /* NO PULL */
1195 };
1196 };
1197 };
1198
1199 tert_mi2s_sd1 {
1200 tert_mi2s_sd1_sleep: tert_mi2s_sd1_sleep {
1201 mux {
1202 pins = "gpio78";
1203 function = "gpio";
1204 };
1205
1206 config {
1207 pins = "gpio78";
1208 drive-strength = <2>; /* 2 mA */
1209 bias-pull-down; /* PULL DOWN */
1210 input-enable;
1211 };
1212 };
1213
1214 tert_mi2s_sd1_active: tert_mi2s_sd1_active {
1215 mux {
1216 pins = "gpio78";
1217 function = "ter_mi2s";
1218 };
1219
1220 config {
1221 pins = "gpio78";
1222 drive-strength = <8>; /* 8 mA */
1223 bias-disable; /* NO PULL */
1224 };
1225 };
1226 };
1227
1228 quat_mi2s_mclk {
1229 quat_mi2s_mclk_sleep: quat_mi2s_mclk_sleep {
1230 mux {
1231 pins = "gpio57";
1232 function = "gpio";
1233 };
1234
1235 config {
1236 pins = "gpio57";
1237 drive-strength = <2>; /* 2 mA */
1238 bias-pull-down; /* PULL DOWN */
1239 input-enable;
1240 };
1241 };
1242
1243 quat_mi2s_mclk_active: quat_mi2s_mclk_active {
1244 mux {
1245 pins = "gpio57";
1246 function = "qua_mi2s";
1247 };
1248
1249 config {
1250 pins = "gpio57";
1251 drive-strength = <8>; /* 8 mA */
1252 bias-disable; /* NO PULL */
1253 };
1254 };
1255 };
1256
1257 quat_mi2s {
1258 quat_mi2s_sleep: quat_mi2s_sleep {
1259 mux {
1260 pins = "gpio58", "gpio59";
1261 function = "gpio";
1262 };
1263
1264 config {
1265 pins = "gpio58", "gpio59";
1266 drive-strength = <2>; /* 2 mA */
1267 bias-pull-down; /* PULL DOWN */
1268 input-enable;
1269 };
1270 };
1271
1272 quat_mi2s_active: quat_mi2s_active {
1273 mux {
1274 pins = "gpio58", "gpio59";
1275 function = "qua_mi2s";
1276 };
1277
1278 config {
1279 pins = "gpio58", "gpio59";
1280 drive-strength = <8>; /* 8 mA */
1281 bias-disable; /* NO PULL */
1282 output-high;
1283 };
1284 };
1285 };
1286
1287 quat_mi2s_sd0 {
1288 quat_mi2s_sd0_sleep: quat_mi2s_sd0_sleep {
1289 mux {
1290 pins = "gpio60";
1291 function = "gpio";
1292 };
1293
1294 config {
1295 pins = "gpio60";
1296 drive-strength = <2>; /* 2 mA */
1297 bias-pull-down; /* PULL DOWN */
1298 input-enable;
1299 };
1300 };
1301
1302 quat_mi2s_sd0_active: quat_mi2s_sd0_active {
1303 mux {
1304 pins = "gpio60";
1305 function = "qua_mi2s";
1306 };
1307
1308 config {
1309 pins = "gpio60";
1310 drive-strength = <8>; /* 8 mA */
1311 bias-disable; /* NO PULL */
1312 };
1313 };
1314 };
1315
1316 quat_mi2s_sd1 {
1317 quat_mi2s_sd1_sleep: quat_mi2s_sd1_sleep {
1318 mux {
1319 pins = "gpio61";
1320 function = "gpio";
1321 };
1322
1323 config {
1324 pins = "gpio61";
1325 drive-strength = <2>; /* 2 mA */
1326 bias-pull-down; /* PULL DOWN */
1327 input-enable;
1328 };
1329 };
1330
1331 quat_mi2s_sd1_active: quat_mi2s_sd1_active {
1332 mux {
1333 pins = "gpio61";
1334 function = "qua_mi2s";
1335 };
1336
1337 config {
1338 pins = "gpio61";
1339 drive-strength = <8>; /* 8 mA */
1340 bias-disable; /* NO PULL */
1341 };
1342 };
1343 };
1344
1345 quat_mi2s_sd2 {
1346 quat_mi2s_sd2_sleep: quat_mi2s_sd2_sleep {
1347 mux {
1348 pins = "gpio62";
1349 function = "gpio";
1350 };
1351
1352 config {
1353 pins = "gpio62";
1354 drive-strength = <2>; /* 2 mA */
1355 bias-pull-down; /* PULL DOWN */
1356 input-enable;
1357 };
1358 };
1359
1360 quat_mi2s_sd2_active: quat_mi2s_sd2_active {
1361 mux {
1362 pins = "gpio62";
1363 function = "qua_mi2s";
1364 };
1365
1366 config {
1367 pins = "gpio62";
1368 drive-strength = <8>; /* 8 mA */
1369 bias-disable; /* NO PULL */
1370 };
1371 };
1372 };
1373
1374 quat_mi2s_sd3 {
1375 quat_mi2s_sd3_sleep: quat_mi2s_sd3_sleep {
1376 mux {
1377 pins = "gpio63";
1378 function = "gpio";
1379 };
1380
1381 config {
1382 pins = "gpio63";
1383 drive-strength = <2>; /* 2 mA */
1384 bias-pull-down; /* PULL DOWN */
1385 input-enable;
1386 };
1387 };
1388
1389 quat_mi2s_sd3_active: quat_mi2s_sd3_active {
1390 mux {
1391 pins = "gpio63";
1392 function = "qua_mi2s";
1393 };
1394
1395 config {
1396 pins = "gpio63";
1397 drive-strength = <8>; /* 8 mA */
1398 bias-disable; /* NO PULL */
1399 };
1400 };
1401 };
Girish Mahadevan2e2fbe72017-03-28 13:28:18 -06001402
1403 /* QUPv3 South SE mappings */
1404 /* SE 0 pin mappings */
1405 qupv3_se0_i2c_pins: qupv3_se0_i2c_pins {
1406 qupv3_se0_i2c_active: qupv3_se0_i2c_active {
1407 mux {
1408 pins = "gpio0", "gpio1";
1409 function = "qup0";
1410 };
1411
1412 config {
1413 pins = "gpio0", "gpio1";
1414 drive-strength = <2>;
1415 bias-disable;
1416 };
1417 };
1418
1419 qupv3_se0_i2c_sleep: qupv3_se0_i2c_sleep {
1420 mux {
1421 pins = "gpio0", "gpio1";
1422 function = "gpio";
1423 };
1424
1425 config {
1426 pins = "gpio0", "gpio1";
1427 drive-strength = <2>;
1428 bias-pull-up;
1429 };
1430 };
1431 };
1432
1433 qupv3_se0_spi_pins: qupv3_se0_spi_pins {
1434 qupv3_se0_spi_active: qupv3_se0_spi_active {
1435 mux {
1436 pins = "gpio0", "gpio1", "gpio2",
1437 "gpio3";
1438 function = "qup0";
1439 };
1440
1441 config {
1442 pins = "gpio0", "gpio1", "gpio2",
1443 "gpio3";
1444 drive-strength = <6>;
1445 bias-disable;
1446 };
1447 };
1448
1449 qupv3_se0_spi_sleep: qupv3_se0_spi_sleep {
1450 mux {
1451 pins = "gpio0", "gpio1", "gpio2",
1452 "gpio3";
1453 function = "gpio";
1454 };
1455
1456 config {
1457 pins = "gpio0", "gpio1", "gpio2",
1458 "gpio3";
1459 drive-strength = <6>;
1460 bias-disable;
1461 };
1462 };
1463 };
1464
1465 /* SE 1 pin mappings */
1466 qupv3_se1_i2c_pins: qupv3_se1_i2c_pins {
1467 qupv3_se1_i2c_active: qupv3_se1_i2c_active {
1468 mux {
1469 pins = "gpio17", "gpio18";
1470 function = "qup1";
1471 };
1472
1473 config {
1474 pins = "gpio17", "gpio18";
1475 drive-strength = <2>;
1476 bias-disable;
1477 };
1478 };
1479
1480 qupv3_se1_i2c_sleep: qupv3_se1_i2c_sleep {
1481 mux {
1482 pins = "gpio17", "gpio18";
1483 function = "gpio";
1484 };
1485
1486 config {
1487 pins = "gpio17", "gpio18";
1488 drive-strength = <2>;
1489 bias-pull-up;
1490 };
1491 };
1492 };
1493
1494 qupv3_se1_spi_pins: qupv3_se1_spi_pins {
1495 qupv3_se1_spi_active: qupv3_se1_spi_active {
1496 mux {
1497 pins = "gpio17", "gpio18", "gpio19",
1498 "gpio20";
1499 function = "qup1";
1500 };
1501
1502 config {
1503 pins = "gpio17", "gpio18", "gpio19",
1504 "gpio20";
1505 drive-strength = <6>;
1506 bias-disable;
1507 };
1508 };
1509
1510 qupv3_se1_spi_sleep: qupv3_se1_spi_sleep {
1511 mux {
1512 pins = "gpio17", "gpio18", "gpio19",
1513 "gpio20";
1514 function = "gpio";
1515 };
1516
1517 config {
1518 pins = "gpio17", "gpio18", "gpio19",
1519 "gpio20";
1520 drive-strength = <6>;
1521 bias-disable;
1522 };
1523 };
1524 };
1525
1526 /* SE 2 pin mappings */
1527 qupv3_se2_i2c_pins: qupv3_se2_i2c_pins {
1528 qupv3_se2_i2c_active: qupv3_se2_i2c_active {
1529 mux {
1530 pins = "gpio27", "gpio28";
1531 function = "qup2";
1532 };
1533
1534 config {
1535 pins = "gpio27", "gpio28";
1536 drive-strength = <2>;
1537 bias-disable;
1538 };
1539 };
1540
1541 qupv3_se2_i2c_sleep: qupv3_se2_i2c_sleep {
1542 mux {
1543 pins = "gpio27", "gpio28";
1544 function = "gpio";
1545 };
1546
1547 config {
1548 pins = "gpio27", "gpio28";
1549 drive-strength = <2>;
1550 bias-pull-up;
1551 };
1552 };
1553 };
1554
1555 qupv3_se2_spi_pins: qupv3_se2_spi_pins {
1556 qupv3_se2_spi_active: qupv3_se2_spi_active {
1557 mux {
1558 pins = "gpio27", "gpio28", "gpio29",
1559 "gpio30";
1560 function = "qup2";
1561 };
1562
1563 config {
1564 pins = "gpio27", "gpio28", "gpio29",
1565 "gpio30";
1566 drive-strength = <6>;
1567 bias-disable;
1568 };
1569 };
1570
1571 qupv3_se2_spi_sleep: qupv3_se2_spi_sleep {
1572 mux {
1573 pins = "gpio27", "gpio28", "gpio29",
1574 "gpio30";
1575 function = "gpio";
1576 };
1577
1578 config {
1579 pins = "gpio27", "gpio28", "gpio29",
1580 "gpio30";
1581 drive-strength = <6>;
1582 bias-disable;
1583 };
1584 };
1585 };
1586
1587 /* SE 3 pin mappings */
1588 qupv3_se3_i2c_pins: qupv3_se3_i2c_pins {
1589 qupv3_se3_i2c_active: qupv3_se3_i2c_active {
1590 mux {
1591 pins = "gpio41", "gpio42";
1592 function = "qup3";
1593 };
1594
1595 config {
1596 pins = "gpio41", "gpio42";
1597 drive-strength = <2>;
1598 bias-disable;
1599 };
1600 };
1601
1602 qupv3_se3_i2c_sleep: qupv3_se3_i2c_sleep {
1603 mux {
1604 pins = "gpio41", "gpio42";
1605 function = "gpio";
1606 };
1607
1608 config {
1609 pins = "gpio41", "gpio42";
1610 drive-strength = <2>;
1611 bias-pull-up;
1612 };
1613 };
1614 };
1615
Gaurav Singhalf6d253d2017-05-11 08:24:40 +05301616 nfc {
1617 nfc_int_active: nfc_int_active {
1618 /* active state */
1619 mux {
1620 /* GPIO 63 NFC Read Interrupt */
1621 pins = "gpio63";
1622 function = "gpio";
1623 };
1624
1625 config {
1626 pins = "gpio63";
1627 drive-strength = <2>; /* 2 MA */
1628 bias-pull-up;
1629 };
1630 };
1631
1632 nfc_int_suspend: nfc_int_suspend {
1633 /* sleep state */
1634 mux {
1635 /* GPIO 63 NFC Read Interrupt */
1636 pins = "gpio63";
1637 function = "gpio";
1638 };
1639
1640 config {
1641 pins = "gpio63";
1642 drive-strength = <2>; /* 2 MA */
1643 bias-pull-up;
1644 };
1645 };
1646
1647 nfc_enable_active: nfc_enable_active {
1648 /* active state */
1649 mux {
1650 /* 12: NFC ENABLE 116:ESE Enable */
1651 pins = "gpio12", "gpio62", "gpio116";
1652 function = "gpio";
1653 };
1654
1655 config {
1656 pins = "gpio12", "gpio62", "gpio116";
1657 drive-strength = <2>; /* 2 MA */
1658 bias-pull-up;
1659 };
1660 };
1661
1662 nfc_enable_suspend: nfc_enable_suspend {
1663 /* sleep state */
1664 mux {
1665 /* 12: NFC ENABLE 116:ESE Enable */
1666 pins = "gpio12", "gpio62", "gpio116";
1667 function = "gpio";
1668 };
1669
1670 config {
1671 pins = "gpio12", "gpio62", "gpio116";
1672 drive-strength = <2>; /* 2 MA */
1673 bias-disable;
1674 };
1675 };
1676 };
1677
Girish Mahadevan2e2fbe72017-03-28 13:28:18 -06001678 qupv3_se3_spi_pins: qupv3_se3_spi_pins {
1679 qupv3_se3_spi_active: qupv3_se3_spi_active {
1680 mux {
1681 pins = "gpio41", "gpio42", "gpio43",
1682 "gpio44";
1683 function = "qup3";
1684 };
1685
1686 config {
1687 pins = "gpio41", "gpio42", "gpio43",
1688 "gpio44";
1689 drive-strength = <6>;
1690 bias-disable;
1691 };
1692 };
1693
1694 qupv3_se3_spi_sleep: qupv3_se3_spi_sleep {
1695 mux {
1696 pins = "gpio41", "gpio42", "gpio43",
1697 "gpio44";
1698 function = "gpio";
1699 };
1700
1701 config {
1702 pins = "gpio41", "gpio42", "gpio43",
1703 "gpio44";
1704 drive-strength = <6>;
1705 bias-disable;
1706 };
1707 };
1708 };
1709
1710 /* SE 4 pin mappings */
1711 qupv3_se4_i2c_pins: qupv3_se4_i2c_pins {
1712 qupv3_se4_i2c_active: qupv3_se4_i2c_active {
1713 mux {
1714 pins = "gpio89", "gpio90";
1715 function = "qup4";
1716 };
1717
1718 config {
1719 pins = "gpio89", "gpio90";
1720 drive-strength = <2>;
1721 bias-disable;
1722 };
1723 };
1724
1725 qupv3_se4_i2c_sleep: qupv3_se4_i2c_sleep {
1726 mux {
1727 pins = "gpio89", "gpio90";
1728 function = "gpio";
1729 };
1730
1731 config {
1732 pins = "gpio89", "gpio90";
1733 drive-strength = <2>;
1734 bias-pull-up;
1735 };
1736 };
1737 };
1738
1739 qupv3_se4_spi_pins: qupv3_se4_spi_pins {
1740 qupv3_se4_spi_active: qupv3_se4_spi_active {
1741 mux {
1742 pins = "gpio89", "gpio90", "gpio91",
1743 "gpio92";
1744 function = "qup4";
1745 };
1746
1747 config {
1748 pins = "gpio89", "gpio90", "gpio91",
1749 "gpio92";
1750 drive-strength = <6>;
1751 bias-disable;
1752 };
1753 };
1754
1755 qupv3_se4_spi_sleep: qupv3_se4_spi_sleep {
1756 mux {
1757 pins = "gpio89", "gpio90", "gpio91",
1758 "gpio92";
1759 function = "gpio";
1760 };
1761
1762 config {
1763 pins = "gpio89", "gpio90", "gpio91",
1764 "gpio92";
1765 drive-strength = <6>;
1766 bias-disable;
1767 };
1768 };
1769 };
1770
1771 /* SE 5 pin mappings */
1772 qupv3_se5_i2c_pins: qupv3_se5_i2c_pins {
1773 qupv3_se5_i2c_active: qupv3_se5_i2c_active {
1774 mux {
1775 pins = "gpio85", "gpio86";
1776 function = "qup5";
1777 };
1778
1779 config {
1780 pins = "gpio85", "gpio86";
1781 drive-strength = <2>;
1782 bias-disable;
1783 };
1784 };
1785
1786 qupv3_se5_i2c_sleep: qupv3_se5_i2c_sleep {
1787 mux {
1788 pins = "gpio85", "gpio86";
1789 function = "gpio";
1790 };
1791
1792 config {
1793 pins = "gpio85", "gpio86";
1794 drive-strength = <2>;
1795 bias-pull-up;
1796 };
1797 };
1798 };
1799
1800 qupv3_se5_spi_pins: qupv3_se5_spi_pins {
1801 qupv3_se5_spi_active: qupv3_se5_spi_active {
1802 mux {
1803 pins = "gpio85", "gpio86", "gpio87",
1804 "gpio88";
1805 function = "qup5";
1806 };
1807
1808 config {
1809 pins = "gpio85", "gpio86", "gpio87",
1810 "gpio88";
1811 drive-strength = <6>;
1812 bias-disable;
1813 };
1814 };
1815
1816 qupv3_se5_spi_sleep: qupv3_se5_spi_sleep {
1817 mux {
1818 pins = "gpio85", "gpio86", "gpio87",
1819 "gpio88";
1820 function = "gpio";
1821 };
1822
1823 config {
1824 pins = "gpio85", "gpio86", "gpio87",
1825 "gpio88";
1826 drive-strength = <6>;
1827 bias-disable;
1828 };
1829 };
1830 };
1831
1832 /* SE 6 pin mappings */
1833 qupv3_se6_i2c_pins: qupv3_se6_i2c_pins {
1834 qupv3_se6_i2c_active: qupv3_se6_i2c_active {
1835 mux {
1836 pins = "gpio45", "gpio46";
1837 function = "qup6";
1838 };
1839
1840 config {
1841 pins = "gpio45", "gpio46";
1842 drive-strength = <2>;
1843 bias-disable;
1844 };
1845 };
1846
1847 qupv3_se6_i2c_sleep: qupv3_se6_i2c_sleep {
1848 mux {
1849 pins = "gpio45", "gpio46";
1850 function = "gpio";
1851 };
1852
1853 config {
1854 pins = "gpio45", "gpio46";
1855 drive-strength = <2>;
1856 bias-pull-up;
1857 };
1858 };
1859 };
1860
1861 qupv3_se6_4uart_pins: qupv3_se6_4uart_pins {
1862 qupv3_se6_4uart_active: qupv3_se6_4uart_active {
1863 mux {
1864 pins = "gpio45", "gpio46", "gpio47",
1865 "gpio48";
1866 function = "qup6";
1867 };
1868
1869 config {
1870 pins = "gpio45", "gpio46", "gpio47",
1871 "gpio48";
1872 drive-strength = <2>;
1873 bias-disable;
1874 };
1875 };
1876
1877 qupv3_se6_4uart_sleep: qupv3_se6_4uart_sleep {
1878 mux {
1879 pins = "gpio45", "gpio46", "gpio47",
1880 "gpio48";
1881 function = "gpio";
1882 };
1883
1884 config {
1885 pins = "gpio45", "gpio46", "gpio47",
1886 "gpio48";
1887 drive-strength = <2>;
1888 bias-disable;
1889 };
1890 };
1891 };
1892
1893 qupv3_se6_spi_pins: qupv3_se6_spi_pins {
1894 qupv3_se6_spi_active: qupv3_se6_spi_active {
1895 mux {
1896 pins = "gpio45", "gpio46", "gpio47",
1897 "gpio48";
1898 function = "qup6";
1899 };
1900
1901 config {
1902 pins = "gpio45", "gpio46", "gpio47",
1903 "gpio48";
1904 drive-strength = <6>;
1905 bias-disable;
1906 };
1907 };
1908
1909 qupv3_se6_spi_sleep: qupv3_se6_spi_sleep {
1910 mux {
1911 pins = "gpio45", "gpio46", "gpio47",
1912 "gpio48";
1913 function = "gpio";
1914 };
1915
1916 config {
1917 pins = "gpio45", "gpio46", "gpio47",
1918 "gpio48";
1919 drive-strength = <6>;
1920 bias-disable;
1921 };
1922 };
1923 };
1924
1925 /* SE 7 pin mappings */
1926 qupv3_se7_i2c_pins: qupv3_se7_i2c_pins {
1927 qupv3_se7_i2c_active: qupv3_se7_i2c_active {
1928 mux {
1929 pins = "gpio93", "gpio94";
1930 function = "qup7";
1931 };
1932
1933 config {
1934 pins = "gpio93", "gpio94";
1935 drive-strength = <2>;
1936 bias-disable;
1937 };
1938 };
1939
1940 qupv3_se7_i2c_sleep: qupv3_se7_i2c_sleep {
1941 mux {
1942 pins = "gpio93", "gpio94";
1943 function = "gpio";
1944 };
1945
1946 config {
1947 pins = "gpio93", "gpio94";
1948 drive-strength = <2>;
1949 bias-pull-up;
1950 };
1951 };
1952 };
1953
1954 qupv3_se7_4uart_pins: qupv3_se7_4uart_pins {
1955 qupv3_se7_4uart_active: qupv3_se7_4uart_active {
1956 mux {
1957 pins = "gpio93", "gpio94", "gpio95",
1958 "gpio96";
1959 function = "qup7";
1960 };
1961
1962 config {
1963 pins = "gpio93", "gpio94", "gpio95",
1964 "gpio96";
1965 drive-strength = <2>;
1966 bias-disable;
1967 };
1968 };
1969
1970 qupv3_se7_4uart_sleep: qupv3_se7_4uart_sleep {
1971 mux {
1972 pins = "gpio93", "gpio94", "gpio95",
1973 "gpio96";
1974 function = "gpio";
1975 };
1976
1977 config {
1978 pins = "gpio93", "gpio94", "gpio95",
1979 "gpio96";
1980 drive-strength = <2>;
1981 bias-disable;
1982 };
1983 };
1984 };
1985
1986 qupv3_se7_spi_pins: qupv3_se7_spi_pins {
1987 qupv3_se7_spi_active: qupv3_se7_spi_active {
1988 mux {
1989 pins = "gpio93", "gpio94", "gpio95",
1990 "gpio96";
1991 function = "qup7";
1992 };
1993
1994 config {
1995 pins = "gpio93", "gpio94", "gpio95",
1996 "gpio96";
1997 drive-strength = <6>;
1998 bias-disable;
1999 };
2000 };
2001
2002 qupv3_se7_spi_sleep: qupv3_se7_spi_sleep {
2003 mux {
2004 pins = "gpio93", "gpio94", "gpio95",
2005 "gpio96";
2006 function = "gpio";
2007 };
2008
2009 config {
2010 pins = "gpio93", "gpio94", "gpio95",
2011 "gpio96";
2012 drive-strength = <6>;
2013 bias-disable;
2014 };
2015 };
2016 };
2017
2018 /* QUPv3 North instances */
2019 /* SE 8 pin mappings */
2020 qupv3_se8_i2c_pins: qupv3_se8_i2c_pins {
2021 qupv3_se8_i2c_active: qupv3_se8_i2c_active {
2022 mux {
2023 pins = "gpio65", "gpio66";
2024 function = "qup8";
2025 };
2026
2027 config {
2028 pins = "gpio65", "gpio66";
2029 drive-strength = <2>;
2030 bias-disable;
2031 };
2032 };
2033
2034 qupv3_se8_i2c_sleep: qupv3_se8_i2c_sleep {
2035 mux {
2036 pins = "gpio65", "gpio66";
2037 function = "gpio";
2038 };
2039
2040 config {
2041 pins = "gpio65", "gpio66";
2042 drive-strength = <2>;
2043 bias-pull-up;
2044 };
2045 };
2046 };
2047
2048 qupv3_se8_spi_pins: qupv3_se8_spi_pins {
2049 qupv3_se8_spi_active: qupv3_se8_spi_active {
2050 mux {
2051 pins = "gpio65", "gpio66", "gpio67",
2052 "gpio68";
2053 function = "qup8";
2054 };
2055
2056 config {
2057 pins = "gpio65", "gpio66", "gpio67",
2058 "gpio68";
2059 drive-strength = <6>;
2060 bias-disable;
2061 };
2062 };
2063
2064 qupv3_se8_spi_sleep: qupv3_se8_spi_sleep {
2065 mux {
2066 pins = "gpio65", "gpio66", "gpio67",
2067 "gpio68";
2068 function = "gpio";
2069 };
2070
2071 config {
2072 pins = "gpio65", "gpio66", "gpio67",
2073 "gpio68";
2074 drive-strength = <6>;
2075 bias-disable;
2076 };
2077 };
2078 };
2079
2080 /* SE 9 pin mappings */
2081 qupv3_se9_i2c_pins: qupv3_se9_i2c_pins {
2082 qupv3_se9_i2c_active: qupv3_se9_i2c_active {
2083 mux {
2084 pins = "gpio6", "gpio7";
2085 function = "qup9";
2086 };
2087
2088 config {
2089 pins = "gpio6", "gpio7";
2090 drive-strength = <2>;
2091 bias-disable;
2092 };
2093 };
2094
2095 qupv3_se9_i2c_sleep: qupv3_se9_i2c_sleep {
2096 mux {
2097 pins = "gpio6", "gpio7";
2098 function = "gpio";
2099 };
2100
2101 config {
2102 pins = "gpio6", "gpio7";
2103 drive-strength = <2>;
2104 bias-pull-up;
2105 };
2106 };
2107 };
2108
2109 qupv3_se9_2uart_pins: qupv3_se9_2uart_pins {
2110 qupv3_se9_2uart_active: qupv3_se9_2uart_active {
2111 mux {
2112 pins = "gpio4", "gpio5";
2113 function = "qup9";
2114 };
2115
2116 config {
2117 pins = "gpio4", "gpio5";
2118 drive-strength = <2>;
2119 bias-disable;
2120 };
2121 };
2122
2123 qupv3_se9_2uart_sleep: qupv3_se9_2uart_sleep {
2124 mux {
2125 pins = "gpio4", "gpio5";
2126 function = "gpio";
2127 };
2128
2129 config {
2130 pins = "gpio4", "gpio5";
2131 drive-strength = <2>;
2132 bias-disable;
2133 };
2134 };
2135 };
2136
2137 qupv3_se9_spi_pins: qupv3_se9_spi_pins {
2138 qupv3_se9_spi_active: qupv3_se9_spi_active {
2139 mux {
2140 pins = "gpio4", "gpio5", "gpio6",
2141 "gpio7";
2142 function = "qup9";
2143 };
2144
2145 config {
2146 pins = "gpio4", "gpio5", "gpio6",
2147 "gpio7";
2148 drive-strength = <6>;
2149 bias-disable;
2150 };
2151 };
2152
2153 qupv3_se9_spi_sleep: qupv3_se9_spi_sleep {
2154 mux {
2155 pins = "gpio4", "gpio5", "gpio6",
2156 "gpio7";
2157 function = "gpio";
2158 };
2159
2160 config {
2161 pins = "gpio4", "gpio5", "gpio6",
2162 "gpio7";
2163 drive-strength = <6>;
2164 bias-disable;
2165 };
2166 };
2167 };
2168
2169 /* SE 10 pin mappings */
2170 qupv3_se10_i2c_pins: qupv3_se10_i2c_pins {
2171 qupv3_se10_i2c_active: qupv3_se10_i2c_active {
2172 mux {
2173 pins = "gpio55", "gpio56";
2174 function = "qup10";
2175 };
2176
2177 config {
2178 pins = "gpio55", "gpio56";
2179 drive-strength = <2>;
2180 bias-disable;
2181 };
2182 };
2183
2184 qupv3_se10_i2c_sleep: qupv3_se10_i2c_sleep {
2185 mux {
2186 pins = "gpio55", "gpio56";
2187 function = "gpio";
2188 };
2189
2190 config {
2191 pins = "gpio55", "gpio56";
2192 drive-strength = <2>;
2193 bias-pull-up;
2194 };
2195 };
2196 };
2197
2198 qupv3_se10_2uart_pins: qupv3_se10_2uart_pins {
2199 qupv3_se10_2uart_active: qupv3_se10_2uart_active {
2200 mux {
2201 pins = "gpio53", "gpio54";
2202 function = "qup10";
2203 };
2204
2205 config {
2206 pins = "gpio53", "gpio54";
2207 drive-strength = <2>;
2208 bias-disable;
2209 };
2210 };
2211
2212 qupv3_se10_2uart_sleep: qupv3_se10_2uart_sleep {
2213 mux {
2214 pins = "gpio53", "gpio54";
2215 function = "gpio";
2216 };
2217
2218 config {
2219 pins = "gpio53", "gpio54";
2220 drive-strength = <2>;
2221 bias-disable;
2222 };
2223 };
2224 };
2225
2226 qupv3_se10_spi_pins: qupv3_se10_spi_pins {
2227 qupv3_se10_spi_active: qupv3_se10_spi_active {
2228 mux {
2229 pins = "gpio53", "gpio54", "gpio55",
2230 "gpio56";
2231 function = "qup10";
2232 };
2233
2234 config {
2235 pins = "gpio53", "gpio54", "gpio55",
2236 "gpio56";
2237 drive-strength = <6>;
2238 bias-disable;
2239 };
2240 };
2241
2242 qupv3_se10_spi_sleep: qupv3_se10_spi_sleep {
2243 mux {
2244 pins = "gpio53", "gpio54", "gpio55",
2245 "gpio56";
2246 function = "gpio";
2247 };
2248
2249 config {
2250 pins = "gpio53", "gpio54", "gpio55",
2251 "gpio56";
2252 drive-strength = <6>;
2253 bias-disable;
2254 };
2255 };
2256 };
2257
2258 /* SE 11 pin mappings */
2259 qupv3_se11_i2c_pins: qupv3_se11_i2c_pins {
2260 qupv3_se11_i2c_active: qupv3_se11_i2c_active {
2261 mux {
2262 pins = "gpio31", "gpio32";
2263 function = "qup11";
2264 };
2265
2266 config {
2267 pins = "gpio31", "gpio32";
2268 drive-strength = <2>;
2269 bias-disable;
2270 };
2271 };
2272
2273 qupv3_se11_i2c_sleep: qupv3_se11_i2c_sleep {
2274 mux {
2275 pins = "gpio31", "gpio32";
2276 function = "gpio";
2277 };
2278
2279 config {
2280 pins = "gpio31", "gpio32";
2281 drive-strength = <2>;
2282 bias-pull-up;
2283 };
2284 };
2285 };
2286
2287 qupv3_se11_spi_pins: qupv3_se11_spi_pins {
2288 qupv3_se11_spi_active: qupv3_se11_spi_active {
2289 mux {
2290 pins = "gpio31", "gpio32", "gpio33",
2291 "gpio34";
2292 function = "qup11";
2293 };
2294
2295 config {
2296 pins = "gpio31", "gpio32", "gpio33",
2297 "gpio34";
2298 drive-strength = <6>;
2299 bias-disable;
2300 };
2301 };
2302
2303 qupv3_se11_spi_sleep: qupv3_se11_spi_sleep {
2304 mux {
2305 pins = "gpio31", "gpio32", "gpio33",
2306 "gpio34";
2307 function = "gpio";
2308 };
2309
2310 config {
2311 pins = "gpio31", "gpio32", "gpio33",
2312 "gpio34";
2313 drive-strength = <6>;
2314 bias-disable;
2315 };
2316 };
2317 };
2318
2319 /* SE 12 pin mappings */
2320 qupv3_se12_i2c_pins: qupv3_se12_i2c_pins {
2321 qupv3_se12_i2c_active: qupv3_se12_i2c_active {
2322 mux {
2323 pins = "gpio49", "gpio50";
2324 function = "qup12";
2325 };
2326
2327 config {
2328 pins = "gpio49", "gpio50";
2329 drive-strength = <2>;
2330 bias-disable;
2331 };
2332 };
2333
2334 qupv3_se12_i2c_sleep: qupv3_se12_i2c_sleep {
2335 mux {
2336 pins = "gpio49", "gpio50";
2337 function = "gpio";
2338 };
2339
2340 config {
2341 pins = "gpio49", "gpio50";
2342 drive-strength = <2>;
2343 bias-pull-up;
2344 };
2345 };
2346 };
2347
2348 qupv3_se12_spi_pins: qupv3_se12_spi_pins {
2349 qupv3_se12_spi_active: qupv3_se12_spi_active {
2350 mux {
2351 pins = "gpio49", "gpio50", "gpio51",
2352 "gpio52";
2353 function = "qup12";
2354 };
2355
2356 config {
2357 pins = "gpio49", "gpio50", "gpio51",
2358 "gpio52";
2359 drive-strength = <6>;
2360 bias-disable;
2361 };
2362 };
2363
2364 qupv3_se12_spi_sleep: qupv3_se12_spi_sleep {
2365 mux {
2366 pins = "gpio49", "gpio50", "gpio51",
2367 "gpio52";
2368 function = "gpio";
2369 };
2370
2371 config {
2372 pins = "gpio49", "gpio50", "gpio51",
2373 "gpio52";
2374 drive-strength = <6>;
2375 bias-disable;
2376 };
2377 };
2378 };
2379
2380 /* SE 13 pin mappings */
2381 qupv3_se13_i2c_pins: qupv3_se13_i2c_pins {
2382 qupv3_se13_i2c_active: qupv3_se13_i2c_active {
2383 mux {
2384 pins = "gpio105", "gpio106";
2385 function = "qup13";
2386 };
2387
2388 config {
2389 pins = "gpio105", "gpio106";
2390 drive-strength = <2>;
2391 bias-disable;
2392 };
2393 };
2394
2395 qupv3_se13_i2c_sleep: qupv3_se13_i2c_sleep {
2396 mux {
2397 pins = "gpio105", "gpio106";
2398 function = "gpio";
2399 };
2400
2401 config {
2402 pins = "gpio105", "gpio106";
2403 drive-strength = <2>;
2404 bias-pull-up;
2405 };
2406 };
2407 };
2408
2409 qupv3_se13_spi_pins: qupv3_se13_spi_pins {
2410 qupv3_se13_spi_active: qupv3_se13_spi_active {
2411 mux {
2412 pins = "gpio105", "gpio106", "gpio107",
2413 "gpio108";
2414 function = "qup13";
2415 };
2416
2417 config {
2418 pins = "gpio105", "gpio106", "gpio107",
2419 "gpio108";
2420 drive-strength = <6>;
2421 bias-disable;
2422 };
2423 };
2424
2425 qupv3_se13_spi_sleep: qupv3_se13_spi_sleep {
2426 mux {
2427 pins = "gpio105", "gpio106", "gpio107",
2428 "gpio108";
2429 function = "gpio";
2430 };
2431
2432 config {
2433 pins = "gpio105", "gpio106", "gpio107",
2434 "gpio108";
2435 drive-strength = <6>;
2436 bias-disable;
2437 };
2438 };
2439 };
2440
2441 /* SE 14 pin mappings */
2442 qupv3_se14_i2c_pins: qupv3_se14_i2c_pins {
2443 qupv3_se14_i2c_active: qupv3_se14_i2c_active {
2444 mux {
2445 pins = "gpio33", "gpio34";
2446 function = "qup14";
2447 };
2448
2449 config {
2450 pins = "gpio33", "gpio34";
2451 drive-strength = <2>;
2452 bias-disable;
2453 };
2454 };
2455
2456 qupv3_se14_i2c_sleep: qupv3_se14_i2c_sleep {
2457 mux {
2458 pins = "gpio33", "gpio34";
2459 function = "gpio";
2460 };
2461
2462 config {
2463 pins = "gpio33", "gpio34";
2464 drive-strength = <2>;
2465 bias-pull-up;
2466 };
2467 };
2468 };
2469
2470 qupv3_se14_spi_pins: qupv3_se14_spi_pins {
2471 qupv3_se14_spi_active: qupv3_se14_spi_active {
2472 mux {
2473 pins = "gpio31", "gpio32", "gpio33",
2474 "gpio34";
2475 function = "qup14";
2476 };
2477
2478 config {
2479 pins = "gpio31", "gpio32", "gpio33",
2480 "gpio34";
2481 drive-strength = <6>;
2482 bias-disable;
2483 };
2484 };
2485
2486 qupv3_se14_spi_sleep: qupv3_se14_spi_sleep {
2487 mux {
2488 pins = "gpio31", "gpio32", "gpio33",
2489 "gpio34";
2490 function = "gpio";
2491 };
2492
2493 config {
2494 pins = "gpio31", "gpio32", "gpio33",
2495 "gpio34";
2496 drive-strength = <6>;
2497 bias-disable;
2498 };
2499 };
2500 };
2501
2502 /* SE 15 pin mappings */
2503 qupv3_se15_i2c_pins: qupv3_se15_i2c_pins {
2504 qupv3_se15_i2c_active: qupv3_se15_i2c_active {
2505 mux {
2506 pins = "gpio81", "gpio82";
2507 function = "qup15";
2508 };
2509
2510 config {
2511 pins = "gpio81", "gpio82";
2512 drive-strength = <2>;
2513 bias-disable;
2514 };
2515 };
2516
2517 qupv3_se15_i2c_sleep: qupv3_se15_i2c_sleep {
2518 mux {
2519 pins = "gpio81", "gpio82";
2520 function = "gpio";
2521 };
2522
2523 config {
2524 pins = "gpio81", "gpio82";
2525 drive-strength = <2>;
2526 bias-pull-up;
2527 };
2528 };
2529 };
2530
2531 qupv3_se15_spi_pins: qupv3_se15_spi_pins {
2532 qupv3_se15_spi_active: qupv3_se15_spi_active {
2533 mux {
2534 pins = "gpio81", "gpio82", "gpio83",
2535 "gpio84";
2536 function = "qup15";
2537 };
2538
2539 config {
2540 pins = "gpio81", "gpio82", "gpio83",
2541 "gpio84";
2542 drive-strength = <6>;
2543 bias-disable;
2544 };
2545 };
2546
2547 qupv3_se15_spi_sleep: qupv3_se15_spi_sleep {
2548 mux {
2549 pins = "gpio81", "gpio82", "gpio83",
2550 "gpio84";
2551 function = "gpio";
2552 };
2553
2554 config {
2555 pins = "gpio81", "gpio82", "gpio83",
2556 "gpio84";
2557 drive-strength = <6>;
2558 bias-disable;
2559 };
2560 };
2561 };
Jigarkumar Zala861231152017-02-28 14:05:11 -08002562
2563 cci0_active: cci0_active {
2564 mux {
2565 /* CLK, DATA */
2566 pins = "gpio17","gpio18"; // Only 2
2567 function = "cci_i2c";
2568 };
2569
2570 config {
2571 pins = "gpio17","gpio18";
2572 bias-pull-up; /* PULL UP*/
2573 drive-strength = <2>; /* 2 MA */
2574 };
2575 };
2576
2577 cci0_suspend: cci0_suspend {
2578 mux {
2579 /* CLK, DATA */
2580 pins = "gpio17","gpio18";
2581 function = "cci_i2c";
2582 };
2583
2584 config {
2585 pins = "gpio17","gpio18";
2586 bias-pull-down; /* PULL DOWN */
2587 drive-strength = <2>; /* 2 MA */
2588 };
2589 };
2590
2591 cci1_active: cci1_active {
2592 mux {
2593 /* CLK, DATA */
2594 pins = "gpio19","gpio20";
2595 function = "cci_i2c";
2596 };
2597
2598 config {
2599 pins = "gpio19","gpio20";
2600 bias-pull-up; /* PULL UP*/
2601 drive-strength = <2>; /* 2 MA */
2602 };
2603 };
2604
2605 cci1_suspend: cci1_suspend {
2606 mux {
2607 /* CLK, DATA */
2608 pins = "gpio19","gpio20";
2609 function = "cci_i2c";
2610 };
2611
2612 config {
2613 pins = "gpio19","gpio20";
2614 bias-pull-down; /* PULL DOWN */
2615 drive-strength = <2>; /* 2 MA */
2616 };
2617 };
2618
2619 cam_sensor_mclk0_active: cam_sensor_mclk0_active {
2620 /* MCLK0 */
2621 mux {
2622 pins = "gpio13";
2623 function = "cam_mclk";
2624 };
2625
2626 config {
2627 pins = "gpio13";
2628 bias-disable; /* No PULL */
2629 drive-strength = <2>; /* 2 MA */
2630 };
2631 };
2632
2633 cam_sensor_mclk0_suspend: cam_sensor_mclk0_suspend {
2634 /* MCLK0 */
2635 mux {
2636 pins = "gpio13";
2637 function = "cam_mclk";
2638 };
2639
2640 config {
2641 pins = "gpio13";
2642 bias-pull-down; /* PULL DOWN */
2643 drive-strength = <2>; /* 2 MA */
2644 };
2645 };
2646
2647 cam_sensor_rear_active: cam_sensor_rear_active {
2648 /* RESET, AVDD LDO */
2649 mux {
2650 pins = "gpio80","gpio79";
2651 function = "gpio";
2652 };
2653
2654 config {
2655 pins = "gpio80","gpio79";
2656 bias-disable; /* No PULL */
2657 drive-strength = <2>; /* 2 MA */
2658 };
2659 };
2660
2661 cam_sensor_rear_suspend: cam_sensor_rear_suspend {
2662 /* RESET, AVDD LDO */
2663 mux {
2664 pins = "gpio80","gpio79";
2665 function = "gpio";
2666 };
2667
2668 config {
2669 pins = "gpio80","gpio79";
Jeyaprakash Soundrapandian902116a2017-07-20 18:17:59 -07002670 bias-pull-down; /* PULL DOWN */
Jigarkumar Zala861231152017-02-28 14:05:11 -08002671 drive-strength = <2>; /* 2 MA */
Karthik Anantha Rame87f1ee2017-08-24 14:05:36 -07002672 output-low;
Jigarkumar Zala861231152017-02-28 14:05:11 -08002673 };
2674 };
2675
2676 cam_sensor_mclk1_active: cam_sensor_mclk1_active {
2677 /* MCLK1 */
2678 mux {
2679 pins = "gpio14";
2680 function = "cam_mclk";
2681 };
2682
2683 config {
2684 pins = "gpio14";
2685 bias-disable; /* No PULL */
2686 drive-strength = <2>; /* 2 MA */
2687 };
2688 };
2689
2690 cam_sensor_mclk1_suspend: cam_sensor_mclk1_suspend {
2691 /* MCLK1 */
2692 mux {
2693 pins = "gpio14";
2694 function = "cam_mclk";
2695 };
2696
2697 config {
2698 pins = "gpio14";
2699 bias-pull-down; /* PULL DOWN */
2700 drive-strength = <2>; /* 2 MA */
2701 };
2702 };
2703
2704 cam_sensor_front_active: cam_sensor_front_active {
2705 /* RESET AVDD_LDO*/
2706 mux {
2707 pins = "gpio28", "gpio8";
2708 function = "gpio";
2709 };
2710
2711 config {
2712 pins = "gpio28", "gpio8";
2713 bias-disable; /* No PULL */
2714 drive-strength = <2>; /* 2 MA */
2715 };
2716 };
2717
2718 cam_sensor_front_suspend: cam_sensor_front_suspend {
2719 /* RESET */
2720 mux {
2721 pins = "gpio28";
2722 function = "gpio";
2723 };
2724
2725 config {
2726 pins = "gpio28";
Jeyaprakash Soundrapandian902116a2017-07-20 18:17:59 -07002727 bias-pull-down; /* PULL DOWN */
Jigarkumar Zala861231152017-02-28 14:05:11 -08002728 drive-strength = <2>; /* 2 MA */
Karthik Anantha Rame87f1ee2017-08-24 14:05:36 -07002729 output-low;
Jigarkumar Zala861231152017-02-28 14:05:11 -08002730 };
2731 };
2732
2733 cam_sensor_mclk2_active: cam_sensor_mclk2_active {
2734 /* MCLK1 */
2735 mux {
2736 /* CLK, DATA */
2737 pins = "gpio15";
2738 function = "cam_mclk";
2739 };
2740
2741 config {
2742 pins = "gpio15";
2743 bias-disable; /* No PULL */
2744 drive-strength = <2>; /* 2 MA */
2745 };
2746 };
2747
2748 cam_sensor_mclk2_suspend: cam_sensor_mclk2_suspend {
2749 /* MCLK1 */
2750 mux {
2751 /* CLK, DATA */
2752 pins = "gpio15";
2753 function = "cam_mclk";
2754 };
2755
2756 config {
2757 pins = "gpio15";
2758 bias-pull-down; /* PULL DOWN */
2759 drive-strength = <2>; /* 2 MA */
2760 };
2761 };
2762
2763 cam_sensor_rear2_active: cam_sensor_rear2_active {
2764 /* RESET, STANDBY */
2765 mux {
2766 pins = "gpio9","gpio8";
2767 function = "gpio";
2768 };
2769
2770 config {
2771 pins = "gpio9","gpio8";
2772 bias-disable; /* No PULL */
2773 drive-strength = <2>; /* 2 MA */
2774 };
2775 };
2776
2777 cam_sensor_rear2_suspend: cam_sensor_rear2_suspend {
2778 /* RESET, STANDBY */
2779 mux {
2780 pins = "gpio9","gpio8";
2781 function = "gpio";
2782 };
2783 config {
2784 pins = "gpio9","gpio8";
Jeyaprakash Soundrapandian902116a2017-07-20 18:17:59 -07002785 bias-pull-down; /* PULL DOWN */
Jigarkumar Zala861231152017-02-28 14:05:11 -08002786 drive-strength = <2>; /* 2 MA */
Karthik Anantha Rame87f1ee2017-08-24 14:05:36 -07002787 output-low;
Jigarkumar Zala861231152017-02-28 14:05:11 -08002788 };
2789 };
Satyajit Desaie4508132017-04-05 17:15:22 -07002790
2791 trigout_a: trigout_a {
2792 mux {
Satyajit Desai602a6712017-05-09 14:45:16 -07002793 pins = "gpio90";
Satyajit Desaie4508132017-04-05 17:15:22 -07002794 function = "qdss_cti";
2795 };
2796 config {
Satyajit Desai602a6712017-05-09 14:45:16 -07002797 pins = "gpio90";
Satyajit Desaie4508132017-04-05 17:15:22 -07002798 drive-strength = <2>;
2799 bias-disable;
2800 };
2801 };
Udaya Bhaskara Reddy Mallavarapu55ef0cb2017-06-12 14:45:28 +05302802
2803 tsif0_signals_active: tsif0_signals_active {
2804 tsif1_clk {
2805 pins = "gpio89"; /* TSIF0 CLK */
2806 function = "tsif1_clk";
2807 };
2808 tsif1_en {
2809 pins = "gpio90"; /* TSIF0 Enable */
2810 function = "tsif1_en";
2811 };
2812 tsif1_data {
2813 pins = "gpio91"; /* TSIF0 DATA */
2814 function = "tsif1_data";
2815 };
2816 signals_cfg {
2817 pins = "gpio89", "gpio90", "gpio91";
2818 drive_strength = <2>; /* 2 mA */
2819 bias-pull-down; /* pull down */
2820 };
2821 };
2822
2823 /* sync signal is only used if configured to mode-2 */
2824 tsif0_sync_active: tsif0_sync_active {
2825 tsif1_sync {
2826 pins = "gpio12"; /* TSIF0 SYNC */
2827 function = "tsif1_sync";
2828 drive_strength = <2>; /* 2 mA */
2829 bias-pull-down; /* pull down */
2830 };
2831 };
2832
2833 tsif1_signals_active: tsif1_signals_active {
2834 tsif2_clk {
2835 pins = "gpio93"; /* TSIF1 CLK */
2836 function = "tsif2_clk";
2837 };
2838 tsif2_en {
2839 pins = "gpio94"; /* TSIF1 Enable */
2840 function = "tsif2_en";
2841 };
2842 tsif2_data {
2843 pins = "gpio95"; /* TSIF1 DATA */
2844 function = "tsif2_data";
2845 };
2846 signals_cfg {
2847 pins = "gpio93", "gpio94", "gpio95";
2848 drive_strength = <2>; /* 2 mA */
2849 bias-pull-down; /* pull down */
2850 };
2851 };
2852
2853 /* sync signal is only used if configured to mode-2 */
2854 tsif1_sync_active: tsif1_sync_active {
2855 tsif2_sync {
2856 pins = "gpio96"; /* TSIF1 SYNC */
2857 function = "tsif2_sync";
2858 drive_strength = <2>; /* 2 mA */
2859 bias-pull-down; /* pull down */
2860 };
2861 };
Kyle Yan679cbee2016-07-27 16:55:20 -07002862 };
2863};
David Collinsc6686252017-03-31 14:23:09 -07002864
2865&pm8998_gpios {
2866 key_home {
2867 key_home_default: key_home_default {
2868 pins = "gpio5";
2869 function = "normal";
2870 input-enable;
2871 bias-pull-up;
2872 power-source = <0>;
2873 };
2874 };
2875
2876 key_vol_up {
2877 key_vol_up_default: key_vol_up_default {
2878 pins = "gpio6";
2879 function = "normal";
2880 input-enable;
2881 bias-pull-up;
2882 power-source = <0>;
2883 };
2884 };
2885
2886 key_cam_snapshot {
2887 key_cam_snapshot_default: key_cam_snapshot_default {
2888 pins = "gpio7";
2889 function = "normal";
2890 input-enable;
2891 bias-pull-up;
2892 power-source = <0>;
2893 };
2894 };
2895
2896 key_cam_focus {
2897 key_cam_focus_default: key_cam_focus_default {
2898 pins = "gpio8";
2899 function = "normal";
2900 input-enable;
2901 bias-pull-up;
2902 power-source = <0>;
2903 };
2904 };
Jigarkumar Zala861231152017-02-28 14:05:11 -08002905
2906 camera_dvdd_en {
2907 camera_dvdd_en_default: camera_dvdd_en_default {
2908 pins = "gpio9";
2909 function = "normal";
2910 power-source = <0>;
2911 output-low;
2912 };
2913 };
2914
2915 camera_rear_dvdd_en {
2916 camera_rear_dvdd_en_default: camera_rear_dvdd_en_default {
2917 pins = "gpio12";
2918 function = "normal";
2919 power-source = <0>;
2920 output-low;
2921 };
2922 };
Gaurav Singhal243b94b2017-06-20 14:16:59 +05302923
2924 nfc_clk {
2925 nfc_clk_default: nfc_clk_default {
2926 pins = "gpio21";
2927 function = "normal";
2928 input-enable;
2929 power-source = <1>;
2930 };
2931 };
David Collinsc6686252017-03-31 14:23:09 -07002932};
Jack Phamc2160c842017-04-05 09:48:59 -07002933
2934&pmi8998_gpios {
2935 usb2_vbus_boost {
2936 usb2_vbus_boost_default: usb2_vbus_boost_default {
2937 pins = "gpio2";
2938 function = "normal";
2939 output-low;
2940 power-source = <0>;
2941 };
2942 };
2943
2944 usb2_vbus_det {
2945 usb2_vbus_det_default: usb2_vbus_det_default {
2946 pins = "gpio8";
2947 function = "normal";
2948 input-enable;
2949 bias-pull-down;
2950 power-source = <1>; /* VPH input supply */
2951 };
2952 };
2953
2954 usb2_id_det {
2955 usb2_id_det_default: usb2_id_det_default {
2956 pins = "gpio9";
2957 function = "normal";
2958 input-enable;
2959 bias-pull-up;
2960 power-source = <0>;
2961 };
2962 };
Harry Yang4c05d3e42017-05-09 16:18:17 -07002963
2964 usb2_ext_5v_boost {
2965 usb2_ext_5v_boost_default: usb2_ext_5v_boost_default {
2966 pins = "gpio10";
2967 function = "normal";
2968 output-low;
2969 power-source = <0>;
2970 };
2971 };
Jack Phamc2160c842017-04-05 09:48:59 -07002972};