blob: 1f9e642c66adf8a6b0f620582dcb5598fca89f88 [file] [log] [blame]
Chris Leechc13c8262006-05-23 17:18:44 -07001/*
2 * Copyright(c) 2004 - 2006 Intel Corporation. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms of the GNU General Public License as published by the Free
6 * Software Foundation; either version 2 of the License, or (at your option)
7 * any later version.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc., 59
16 * Temple Place - Suite 330, Boston, MA 02111-1307, USA.
17 *
18 * The full GNU General Public License is included in this distribution in the
19 * file called COPYING.
20 */
Russell King - ARM Linuxd2ebfb32012-03-06 22:34:26 +000021#ifndef LINUX_DMAENGINE_H
22#define LINUX_DMAENGINE_H
David Woodhouse1c0f16e2006-06-27 02:53:56 -070023
Chris Leechc13c8262006-05-23 17:18:44 -070024#include <linux/device.h>
Stephen Warren0ad7c002013-11-26 10:04:22 -070025#include <linux/err.h>
Chris Leechc13c8262006-05-23 17:18:44 -070026#include <linux/uio.h>
Paul Gortmaker187f1882011-11-23 20:12:59 -050027#include <linux/bug.h>
Vinod Koul90b44f82011-07-25 19:57:52 +053028#include <linux/scatterlist.h>
Paul Gortmakera8efa9d2011-07-29 16:55:11 +100029#include <linux/bitmap.h>
Viresh Kumardcc043d2012-02-01 16:12:18 +053030#include <linux/types.h>
Paul Gortmakera8efa9d2011-07-29 16:55:11 +100031#include <asm/page.h>
Alexey Dobriyanb7f080c2011-06-16 11:01:34 +000032
Chris Leechc13c8262006-05-23 17:18:44 -070033/**
Randy Dunlapfe4ada22006-07-03 19:44:51 -070034 * typedef dma_cookie_t - an opaque DMA cookie
Chris Leechc13c8262006-05-23 17:18:44 -070035 *
36 * if dma_cookie_t is >0 it's a DMA request cookie, <0 it's an error code
37 */
38typedef s32 dma_cookie_t;
Steven J. Magnani76bd0612010-02-28 22:18:16 -070039#define DMA_MIN_COOKIE 1
Chris Leechc13c8262006-05-23 17:18:44 -070040
Dan Carpenter71ea1482013-08-10 10:46:50 +030041static inline int dma_submit_error(dma_cookie_t cookie)
42{
43 return cookie < 0 ? cookie : 0;
44}
Chris Leechc13c8262006-05-23 17:18:44 -070045
46/**
47 * enum dma_status - DMA transaction status
Vinod Kouladfedd92013-10-16 13:29:02 +053048 * @DMA_COMPLETE: transaction completed
Chris Leechc13c8262006-05-23 17:18:44 -070049 * @DMA_IN_PROGRESS: transaction not yet processed
Linus Walleij07934482010-03-26 16:50:49 -070050 * @DMA_PAUSED: transaction is paused
Chris Leechc13c8262006-05-23 17:18:44 -070051 * @DMA_ERROR: transaction failed
52 */
53enum dma_status {
Vinod Koul7db5f722013-10-17 07:29:57 +053054 DMA_COMPLETE,
Chris Leechc13c8262006-05-23 17:18:44 -070055 DMA_IN_PROGRESS,
Linus Walleij07934482010-03-26 16:50:49 -070056 DMA_PAUSED,
Chris Leechc13c8262006-05-23 17:18:44 -070057 DMA_ERROR,
58};
59
60/**
Dan Williams7405f742007-01-02 11:10:43 -070061 * enum dma_transaction_type - DMA transaction types/indexes
Dan Williams138f4c32009-09-08 17:42:51 -070062 *
63 * Note: The DMA_ASYNC_TX capability is not to be set by drivers. It is
64 * automatically set as dma devices are registered.
Dan Williams7405f742007-01-02 11:10:43 -070065 */
66enum dma_transaction_type {
67 DMA_MEMCPY,
68 DMA_XOR,
Dan Williamsb2f46fd2009-07-14 12:20:36 -070069 DMA_PQ,
Dan Williams099f53c2009-04-08 14:28:37 -070070 DMA_XOR_VAL,
71 DMA_PQ_VAL,
Dan Williams7405f742007-01-02 11:10:43 -070072 DMA_INTERRUPT,
Ira Snydera86ee032010-09-30 11:46:44 +000073 DMA_SG,
Dan Williams59b5ec22009-01-06 11:38:15 -070074 DMA_PRIVATE,
Dan Williams138f4c32009-09-08 17:42:51 -070075 DMA_ASYNC_TX,
Haavard Skinnemoendc0ee6432008-07-08 11:59:35 -070076 DMA_SLAVE,
Sascha Hauer782bc952010-09-30 13:56:32 +000077 DMA_CYCLIC,
Jassi Brarb14dab72011-10-13 12:33:30 +053078 DMA_INTERLEAVE,
Dan Williams7405f742007-01-02 11:10:43 -070079/* last transaction type for creation of the capabilities mask */
Jassi Brarb14dab72011-10-13 12:33:30 +053080 DMA_TX_TYPE_END,
81};
Haavard Skinnemoendc0ee6432008-07-08 11:59:35 -070082
Vinod Koul49920bc2011-10-13 15:15:27 +053083/**
84 * enum dma_transfer_direction - dma transfer mode and direction indicator
85 * @DMA_MEM_TO_MEM: Async/Memcpy mode
86 * @DMA_MEM_TO_DEV: Slave mode & From Memory to Device
87 * @DMA_DEV_TO_MEM: Slave mode & From Device to Memory
88 * @DMA_DEV_TO_DEV: Slave mode & From Device to Device
89 */
90enum dma_transfer_direction {
91 DMA_MEM_TO_MEM,
92 DMA_MEM_TO_DEV,
93 DMA_DEV_TO_MEM,
94 DMA_DEV_TO_DEV,
Shawn Guo62268ce2011-12-13 23:48:03 +080095 DMA_TRANS_NONE,
Vinod Koul49920bc2011-10-13 15:15:27 +053096};
Dan Williams7405f742007-01-02 11:10:43 -070097
98/**
Jassi Brarb14dab72011-10-13 12:33:30 +053099 * Interleaved Transfer Request
100 * ----------------------------
101 * A chunk is collection of contiguous bytes to be transfered.
102 * The gap(in bytes) between two chunks is called inter-chunk-gap(ICG).
103 * ICGs may or maynot change between chunks.
104 * A FRAME is the smallest series of contiguous {chunk,icg} pairs,
105 * that when repeated an integral number of times, specifies the transfer.
106 * A transfer template is specification of a Frame, the number of times
107 * it is to be repeated and other per-transfer attributes.
108 *
109 * Practically, a client driver would have ready a template for each
110 * type of transfer it is going to need during its lifetime and
111 * set only 'src_start' and 'dst_start' before submitting the requests.
112 *
113 *
114 * | Frame-1 | Frame-2 | ~ | Frame-'numf' |
115 * |====....==.===...=...|====....==.===...=...| ~ |====....==.===...=...|
116 *
117 * == Chunk size
118 * ... ICG
119 */
120
121/**
122 * struct data_chunk - Element of scatter-gather list that makes a frame.
123 * @size: Number of bytes to read from source.
124 * size_dst := fn(op, size_src), so doesn't mean much for destination.
125 * @icg: Number of bytes to jump after last src/dst address of this
126 * chunk and before first src/dst address for next chunk.
127 * Ignored for dst(assumed 0), if dst_inc is true and dst_sgl is false.
128 * Ignored for src(assumed 0), if src_inc is true and src_sgl is false.
129 */
130struct data_chunk {
131 size_t size;
132 size_t icg;
133};
134
135/**
136 * struct dma_interleaved_template - Template to convey DMAC the transfer pattern
137 * and attributes.
138 * @src_start: Bus address of source for the first chunk.
139 * @dst_start: Bus address of destination for the first chunk.
140 * @dir: Specifies the type of Source and Destination.
141 * @src_inc: If the source address increments after reading from it.
142 * @dst_inc: If the destination address increments after writing to it.
143 * @src_sgl: If the 'icg' of sgl[] applies to Source (scattered read).
144 * Otherwise, source is read contiguously (icg ignored).
145 * Ignored if src_inc is false.
146 * @dst_sgl: If the 'icg' of sgl[] applies to Destination (scattered write).
147 * Otherwise, destination is filled contiguously (icg ignored).
148 * Ignored if dst_inc is false.
149 * @numf: Number of frames in this template.
150 * @frame_size: Number of chunks in a frame i.e, size of sgl[].
151 * @sgl: Array of {chunk,icg} pairs that make up a frame.
152 */
153struct dma_interleaved_template {
154 dma_addr_t src_start;
155 dma_addr_t dst_start;
156 enum dma_transfer_direction dir;
157 bool src_inc;
158 bool dst_inc;
159 bool src_sgl;
160 bool dst_sgl;
161 size_t numf;
162 size_t frame_size;
163 struct data_chunk sgl[0];
164};
165
166/**
Dan Williams636bdea2008-04-17 20:17:26 -0700167 * enum dma_ctrl_flags - DMA flags to augment operation preparation,
Dan Williamsb2f46fd2009-07-14 12:20:36 -0700168 * control completion, and communicate status.
Dan Williamsd4c56f92008-02-02 19:49:58 -0700169 * @DMA_PREP_INTERRUPT - trigger an interrupt (callback) upon completion of
Dan Williamsb2f46fd2009-07-14 12:20:36 -0700170 * this transaction
Guennadi Liakhovetskia88f6662009-12-10 18:35:15 +0100171 * @DMA_CTRL_ACK - if clear, the descriptor cannot be reused until the client
Dan Williamsb2f46fd2009-07-14 12:20:36 -0700172 * acknowledges receipt, i.e. has has a chance to establish any dependency
173 * chains
Dan Williamsb2f46fd2009-07-14 12:20:36 -0700174 * @DMA_PREP_PQ_DISABLE_P - prevent generation of P while generating Q
175 * @DMA_PREP_PQ_DISABLE_Q - prevent generation of Q while generating P
176 * @DMA_PREP_CONTINUE - indicate to a driver that it is reusing buffers as
177 * sources that were the result of a previous operation, in the case of a PQ
178 * operation it continues the calculation with new sources
Dan Williams0403e382009-09-08 17:42:50 -0700179 * @DMA_PREP_FENCE - tell the driver that subsequent operations depend
180 * on the result of this operation
Dan Williamsd4c56f92008-02-02 19:49:58 -0700181 */
Dan Williams636bdea2008-04-17 20:17:26 -0700182enum dma_ctrl_flags {
Dan Williamsd4c56f92008-02-02 19:49:58 -0700183 DMA_PREP_INTERRUPT = (1 << 0),
Dan Williams636bdea2008-04-17 20:17:26 -0700184 DMA_CTRL_ACK = (1 << 1),
Bartlomiej Zolnierkiewicz0776ae72013-10-18 19:35:33 +0200185 DMA_PREP_PQ_DISABLE_P = (1 << 2),
186 DMA_PREP_PQ_DISABLE_Q = (1 << 3),
187 DMA_PREP_CONTINUE = (1 << 4),
188 DMA_PREP_FENCE = (1 << 5),
Dan Williamsd4c56f92008-02-02 19:49:58 -0700189};
190
191/**
Linus Walleijc3635c72010-03-26 16:44:01 -0700192 * enum dma_ctrl_cmd - DMA operations that can optionally be exercised
193 * on a running channel.
194 * @DMA_TERMINATE_ALL: terminate all ongoing transfers
195 * @DMA_PAUSE: pause ongoing transfers
196 * @DMA_RESUME: resume paused transfer
Linus Walleijc156d0a2010-08-04 13:37:33 +0200197 * @DMA_SLAVE_CONFIG: this command is only implemented by DMA controllers
198 * that need to runtime reconfigure the slave channels (as opposed to passing
199 * configuration data in statically from the platform). An additional
200 * argument of struct dma_slave_config must be passed in with this
201 * command.
Ira Snyder968f19a2010-09-30 11:46:46 +0000202 * @FSLDMA_EXTERNAL_START: this command will put the Freescale DMA controller
203 * into external start mode.
Linus Walleijc3635c72010-03-26 16:44:01 -0700204 */
205enum dma_ctrl_cmd {
206 DMA_TERMINATE_ALL,
207 DMA_PAUSE,
208 DMA_RESUME,
Linus Walleijc156d0a2010-08-04 13:37:33 +0200209 DMA_SLAVE_CONFIG,
Ira Snyder968f19a2010-09-30 11:46:46 +0000210 FSLDMA_EXTERNAL_START,
Linus Walleijc3635c72010-03-26 16:44:01 -0700211};
212
213/**
Dan Williamsad283ea2009-08-29 19:09:26 -0700214 * enum sum_check_bits - bit position of pq_check_flags
215 */
216enum sum_check_bits {
217 SUM_CHECK_P = 0,
218 SUM_CHECK_Q = 1,
219};
220
221/**
222 * enum pq_check_flags - result of async_{xor,pq}_zero_sum operations
223 * @SUM_CHECK_P_RESULT - 1 if xor zero sum error, 0 otherwise
224 * @SUM_CHECK_Q_RESULT - 1 if reed-solomon zero sum error, 0 otherwise
225 */
226enum sum_check_flags {
227 SUM_CHECK_P_RESULT = (1 << SUM_CHECK_P),
228 SUM_CHECK_Q_RESULT = (1 << SUM_CHECK_Q),
229};
230
231
232/**
Dan Williams7405f742007-01-02 11:10:43 -0700233 * dma_cap_mask_t - capabilities bitmap modeled after cpumask_t.
234 * See linux/cpumask.h
235 */
236typedef struct { DECLARE_BITMAP(bits, DMA_TX_TYPE_END); } dma_cap_mask_t;
237
238/**
Chris Leechc13c8262006-05-23 17:18:44 -0700239 * struct dma_chan_percpu - the per-CPU part of struct dma_chan
Chris Leechc13c8262006-05-23 17:18:44 -0700240 * @memcpy_count: transaction counter
241 * @bytes_transferred: byte counter
242 */
243
244struct dma_chan_percpu {
Chris Leechc13c8262006-05-23 17:18:44 -0700245 /* stats */
246 unsigned long memcpy_count;
247 unsigned long bytes_transferred;
248};
249
250/**
251 * struct dma_chan - devices supply DMA channels, clients use them
Randy Dunlapfe4ada22006-07-03 19:44:51 -0700252 * @device: ptr to the dma device who supplies this channel, always !%NULL
Chris Leechc13c8262006-05-23 17:18:44 -0700253 * @cookie: last cookie value returned to client
Russell King - ARM Linux4d4e58d2012-03-06 22:34:06 +0000254 * @completed_cookie: last completed cookie for this channel
Randy Dunlapfe4ada22006-07-03 19:44:51 -0700255 * @chan_id: channel ID for sysfs
Dan Williams41d5e592009-01-06 11:38:21 -0700256 * @dev: class device for sysfs
Chris Leechc13c8262006-05-23 17:18:44 -0700257 * @device_node: used to add this to the device chan list
258 * @local: per-cpu pointer to a struct dma_chan_percpu
Vinod Koul868d2ee2013-12-18 21:39:39 +0530259 * @client_count: how many clients are using this channel
Dan Williamsbec08512009-01-06 11:38:14 -0700260 * @table_count: number of appearances in the mem-to-mem allocation table
Dan Williams287d8592009-02-18 14:48:26 -0800261 * @private: private data for certain client-channel associations
Chris Leechc13c8262006-05-23 17:18:44 -0700262 */
263struct dma_chan {
Chris Leechc13c8262006-05-23 17:18:44 -0700264 struct dma_device *device;
265 dma_cookie_t cookie;
Russell King - ARM Linux4d4e58d2012-03-06 22:34:06 +0000266 dma_cookie_t completed_cookie;
Chris Leechc13c8262006-05-23 17:18:44 -0700267
268 /* sysfs */
269 int chan_id;
Dan Williams41d5e592009-01-06 11:38:21 -0700270 struct dma_chan_dev *dev;
Chris Leechc13c8262006-05-23 17:18:44 -0700271
Chris Leechc13c8262006-05-23 17:18:44 -0700272 struct list_head device_node;
Tejun Heoa29d8b82010-02-02 14:39:15 +0900273 struct dma_chan_percpu __percpu *local;
Dan Williams7cc5bf92008-07-08 11:58:21 -0700274 int client_count;
Dan Williamsbec08512009-01-06 11:38:14 -0700275 int table_count;
Dan Williams287d8592009-02-18 14:48:26 -0800276 void *private;
Chris Leechc13c8262006-05-23 17:18:44 -0700277};
278
Dan Williams41d5e592009-01-06 11:38:21 -0700279/**
280 * struct dma_chan_dev - relate sysfs device node to backing channel device
Vinod Koul868d2ee2013-12-18 21:39:39 +0530281 * @chan: driver channel device
282 * @device: sysfs device
283 * @dev_id: parent dma_device dev_id
284 * @idr_ref: reference count to gate release of dma_device dev_id
Dan Williams41d5e592009-01-06 11:38:21 -0700285 */
286struct dma_chan_dev {
287 struct dma_chan *chan;
288 struct device device;
Dan Williams864498a2009-01-06 11:38:21 -0700289 int dev_id;
290 atomic_t *idr_ref;
Dan Williams41d5e592009-01-06 11:38:21 -0700291};
292
Linus Walleijc156d0a2010-08-04 13:37:33 +0200293/**
Alexander Popovba730342014-05-15 18:15:31 +0400294 * enum dma_slave_buswidth - defines bus width of the DMA slave
Linus Walleijc156d0a2010-08-04 13:37:33 +0200295 * device, source or target buses
296 */
297enum dma_slave_buswidth {
298 DMA_SLAVE_BUSWIDTH_UNDEFINED = 0,
299 DMA_SLAVE_BUSWIDTH_1_BYTE = 1,
300 DMA_SLAVE_BUSWIDTH_2_BYTES = 2,
Peter Ujfalusi93c6ee92014-07-03 07:51:52 +0300301 DMA_SLAVE_BUSWIDTH_3_BYTES = 3,
Linus Walleijc156d0a2010-08-04 13:37:33 +0200302 DMA_SLAVE_BUSWIDTH_4_BYTES = 4,
303 DMA_SLAVE_BUSWIDTH_8_BYTES = 8,
304};
305
306/**
307 * struct dma_slave_config - dma slave channel runtime config
308 * @direction: whether the data shall go in or out on this slave
Alexander Popov397321f2013-12-16 12:12:17 +0400309 * channel, right now. DMA_MEM_TO_DEV and DMA_DEV_TO_MEM are
310 * legal values.
Linus Walleijc156d0a2010-08-04 13:37:33 +0200311 * @src_addr: this is the physical address where DMA slave data
312 * should be read (RX), if the source is memory this argument is
313 * ignored.
314 * @dst_addr: this is the physical address where DMA slave data
315 * should be written (TX), if the source is memory this argument
316 * is ignored.
317 * @src_addr_width: this is the width in bytes of the source (RX)
318 * register where DMA data shall be read. If the source
319 * is memory this may be ignored depending on architecture.
320 * Legal values: 1, 2, 4, 8.
321 * @dst_addr_width: same as src_addr_width but for destination
322 * target (TX) mutatis mutandis.
323 * @src_maxburst: the maximum number of words (note: words, as in
324 * units of the src_addr_width member, not bytes) that can be sent
325 * in one burst to the device. Typically something like half the
326 * FIFO depth on I/O peripherals so you don't overflow it. This
327 * may or may not be applicable on memory sources.
328 * @dst_maxburst: same as src_maxburst but for destination target
329 * mutatis mutandis.
Viresh Kumardcc043d2012-02-01 16:12:18 +0530330 * @device_fc: Flow Controller Settings. Only valid for slave channels. Fill
331 * with 'true' if peripheral should be flow controller. Direction will be
332 * selected at Runtime.
Laxman Dewangan4fd1e322012-06-06 10:55:26 +0530333 * @slave_id: Slave requester id. Only valid for slave channels. The dma
334 * slave peripheral will have unique id as dma requester which need to be
335 * pass as slave config.
Linus Walleijc156d0a2010-08-04 13:37:33 +0200336 *
337 * This struct is passed in as configuration data to a DMA engine
338 * in order to set up a certain channel for DMA transport at runtime.
339 * The DMA device/engine has to provide support for an additional
340 * command in the channel config interface, DMA_SLAVE_CONFIG
341 * and this struct will then be passed in as an argument to the
342 * DMA engine device_control() function.
343 *
Lars-Peter Clausen7cbccb52014-02-16 14:21:22 +0100344 * The rationale for adding configuration information to this struct is as
345 * follows: if it is likely that more than one DMA slave controllers in
346 * the world will support the configuration option, then make it generic.
347 * If not: if it is fixed so that it be sent in static from the platform
348 * data, then prefer to do that.
Linus Walleijc156d0a2010-08-04 13:37:33 +0200349 */
350struct dma_slave_config {
Vinod Koul49920bc2011-10-13 15:15:27 +0530351 enum dma_transfer_direction direction;
Linus Walleijc156d0a2010-08-04 13:37:33 +0200352 dma_addr_t src_addr;
353 dma_addr_t dst_addr;
354 enum dma_slave_buswidth src_addr_width;
355 enum dma_slave_buswidth dst_addr_width;
356 u32 src_maxburst;
357 u32 dst_maxburst;
Viresh Kumardcc043d2012-02-01 16:12:18 +0530358 bool device_fc;
Laxman Dewangan4fd1e322012-06-06 10:55:26 +0530359 unsigned int slave_id;
Linus Walleijc156d0a2010-08-04 13:37:33 +0200360};
361
Lars-Peter Clausen50720562014-01-11 14:02:16 +0100362/**
363 * enum dma_residue_granularity - Granularity of the reported transfer residue
364 * @DMA_RESIDUE_GRANULARITY_DESCRIPTOR: Residue reporting is not support. The
365 * DMA channel is only able to tell whether a descriptor has been completed or
366 * not, which means residue reporting is not supported by this channel. The
367 * residue field of the dma_tx_state field will always be 0.
368 * @DMA_RESIDUE_GRANULARITY_SEGMENT: Residue is updated after each successfully
369 * completed segment of the transfer (For cyclic transfers this is after each
370 * period). This is typically implemented by having the hardware generate an
371 * interrupt after each transferred segment and then the drivers updates the
372 * outstanding residue by the size of the segment. Another possibility is if
373 * the hardware supports scatter-gather and the segment descriptor has a field
374 * which gets set after the segment has been completed. The driver then counts
375 * the number of segments without the flag set to compute the residue.
376 * @DMA_RESIDUE_GRANULARITY_BURST: Residue is updated after each transferred
377 * burst. This is typically only supported if the hardware has a progress
378 * register of some sort (E.g. a register with the current read/write address
379 * or a register with the amount of bursts/beats/bytes that have been
380 * transferred or still need to be transferred).
381 */
382enum dma_residue_granularity {
383 DMA_RESIDUE_GRANULARITY_DESCRIPTOR = 0,
384 DMA_RESIDUE_GRANULARITY_SEGMENT = 1,
385 DMA_RESIDUE_GRANULARITY_BURST = 2,
386};
387
Vinod Koul221a27c72013-07-08 14:15:25 +0530388/* struct dma_slave_caps - expose capabilities of a slave channel only
389 *
390 * @src_addr_widths: bit mask of src addr widths the channel supports
391 * @dstn_addr_widths: bit mask of dstn addr widths the channel supports
392 * @directions: bit mask of slave direction the channel supported
393 * since the enum dma_transfer_direction is not defined as bits for each
394 * type of direction, the dma controller should fill (1 << <TYPE>) and same
395 * should be checked by controller as well
396 * @cmd_pause: true, if pause and thereby resume is supported
397 * @cmd_terminate: true, if terminate cmd is supported
Lars-Peter Clausen50720562014-01-11 14:02:16 +0100398 * @residue_granularity: granularity of the reported transfer residue
Vinod Koul221a27c72013-07-08 14:15:25 +0530399 */
400struct dma_slave_caps {
401 u32 src_addr_widths;
402 u32 dstn_addr_widths;
403 u32 directions;
404 bool cmd_pause;
405 bool cmd_terminate;
Lars-Peter Clausen50720562014-01-11 14:02:16 +0100406 enum dma_residue_granularity residue_granularity;
Vinod Koul221a27c72013-07-08 14:15:25 +0530407};
408
Dan Williams41d5e592009-01-06 11:38:21 -0700409static inline const char *dma_chan_name(struct dma_chan *chan)
410{
411 return dev_name(&chan->dev->device);
412}
Dan Williamsd379b012007-07-09 11:56:42 -0700413
Chris Leechc13c8262006-05-23 17:18:44 -0700414void dma_chan_cleanup(struct kref *kref);
415
Chris Leechc13c8262006-05-23 17:18:44 -0700416/**
Dan Williams59b5ec22009-01-06 11:38:15 -0700417 * typedef dma_filter_fn - callback filter for dma_request_channel
418 * @chan: channel to be reviewed
419 * @filter_param: opaque parameter passed through dma_request_channel
420 *
421 * When this optional parameter is specified in a call to dma_request_channel a
422 * suitable channel is passed to this routine for further dispositioning before
423 * being returned. Where 'suitable' indicates a non-busy channel that
Dan Williams7dd60252009-01-06 11:38:19 -0700424 * satisfies the given capability mask. It returns 'true' to indicate that the
425 * channel is suitable.
Dan Williams59b5ec22009-01-06 11:38:15 -0700426 */
Dan Williams7dd60252009-01-06 11:38:19 -0700427typedef bool (*dma_filter_fn)(struct dma_chan *chan, void *filter_param);
Dan Williams59b5ec22009-01-06 11:38:15 -0700428
Dan Williams7405f742007-01-02 11:10:43 -0700429typedef void (*dma_async_tx_callback)(void *dma_async_param);
Dan Williamsd38a8c62013-10-18 19:35:23 +0200430
431struct dmaengine_unmap_data {
Xuelin Shic1f43dd2014-05-21 14:02:37 -0700432 u8 map_cnt;
Dan Williamsd38a8c62013-10-18 19:35:23 +0200433 u8 to_cnt;
434 u8 from_cnt;
435 u8 bidi_cnt;
436 struct device *dev;
437 struct kref kref;
438 size_t len;
439 dma_addr_t addr[0];
440};
441
Dan Williams7405f742007-01-02 11:10:43 -0700442/**
443 * struct dma_async_tx_descriptor - async transaction descriptor
444 * ---dma generic offload fields---
445 * @cookie: tracking cookie for this transaction, set to -EBUSY if
446 * this tx is sitting on a dependency list
Dan Williams636bdea2008-04-17 20:17:26 -0700447 * @flags: flags to augment operation preparation, control completion, and
448 * communicate status
Dan Williams7405f742007-01-02 11:10:43 -0700449 * @phys: physical address of the descriptor
Dan Williams7405f742007-01-02 11:10:43 -0700450 * @chan: target channel for this operation
451 * @tx_submit: set the prepared descriptor(s) to be executed by the engine
Dan Williams7405f742007-01-02 11:10:43 -0700452 * @callback: routine to call after this operation is complete
453 * @callback_param: general parameter to pass to the callback routine
454 * ---async_tx api specific fields---
Dan Williams19242d72008-04-17 20:17:25 -0700455 * @next: at completion submit this descriptor
Dan Williams7405f742007-01-02 11:10:43 -0700456 * @parent: pointer to the next level up in the dependency chain
Dan Williams19242d72008-04-17 20:17:25 -0700457 * @lock: protect the parent and next pointers
Dan Williams7405f742007-01-02 11:10:43 -0700458 */
459struct dma_async_tx_descriptor {
460 dma_cookie_t cookie;
Dan Williams636bdea2008-04-17 20:17:26 -0700461 enum dma_ctrl_flags flags; /* not a 'long' to pack with cookie */
Dan Williams7405f742007-01-02 11:10:43 -0700462 dma_addr_t phys;
Dan Williams7405f742007-01-02 11:10:43 -0700463 struct dma_chan *chan;
464 dma_cookie_t (*tx_submit)(struct dma_async_tx_descriptor *tx);
Dan Williams7405f742007-01-02 11:10:43 -0700465 dma_async_tx_callback callback;
466 void *callback_param;
Dan Williamsd38a8c62013-10-18 19:35:23 +0200467 struct dmaengine_unmap_data *unmap;
Dan Williams5fc6d892010-10-07 16:44:50 -0700468#ifdef CONFIG_ASYNC_TX_ENABLE_CHANNEL_SWITCH
Dan Williams19242d72008-04-17 20:17:25 -0700469 struct dma_async_tx_descriptor *next;
Dan Williams7405f742007-01-02 11:10:43 -0700470 struct dma_async_tx_descriptor *parent;
471 spinlock_t lock;
Dan Williamscaa20d972010-05-17 16:24:16 -0700472#endif
Dan Williams7405f742007-01-02 11:10:43 -0700473};
474
Dan Williams89716462013-10-18 19:35:25 +0200475#ifdef CONFIG_DMA_ENGINE
Dan Williamsd38a8c62013-10-18 19:35:23 +0200476static inline void dma_set_unmap(struct dma_async_tx_descriptor *tx,
477 struct dmaengine_unmap_data *unmap)
478{
479 kref_get(&unmap->kref);
480 tx->unmap = unmap;
481}
482
Dan Williams89716462013-10-18 19:35:25 +0200483struct dmaengine_unmap_data *
484dmaengine_get_unmap_data(struct device *dev, int nr, gfp_t flags);
Dan Williams45c463a2013-10-18 19:35:24 +0200485void dmaengine_unmap_put(struct dmaengine_unmap_data *unmap);
Dan Williams89716462013-10-18 19:35:25 +0200486#else
487static inline void dma_set_unmap(struct dma_async_tx_descriptor *tx,
488 struct dmaengine_unmap_data *unmap)
489{
490}
491static inline struct dmaengine_unmap_data *
492dmaengine_get_unmap_data(struct device *dev, int nr, gfp_t flags)
493{
494 return NULL;
495}
496static inline void dmaengine_unmap_put(struct dmaengine_unmap_data *unmap)
497{
498}
499#endif
Dan Williams45c463a2013-10-18 19:35:24 +0200500
Dan Williamsd38a8c62013-10-18 19:35:23 +0200501static inline void dma_descriptor_unmap(struct dma_async_tx_descriptor *tx)
502{
503 if (tx->unmap) {
Dan Williams45c463a2013-10-18 19:35:24 +0200504 dmaengine_unmap_put(tx->unmap);
Dan Williamsd38a8c62013-10-18 19:35:23 +0200505 tx->unmap = NULL;
506 }
507}
508
Dan Williams5fc6d892010-10-07 16:44:50 -0700509#ifndef CONFIG_ASYNC_TX_ENABLE_CHANNEL_SWITCH
Dan Williamscaa20d972010-05-17 16:24:16 -0700510static inline void txd_lock(struct dma_async_tx_descriptor *txd)
511{
512}
513static inline void txd_unlock(struct dma_async_tx_descriptor *txd)
514{
515}
516static inline void txd_chain(struct dma_async_tx_descriptor *txd, struct dma_async_tx_descriptor *next)
517{
518 BUG();
519}
520static inline void txd_clear_parent(struct dma_async_tx_descriptor *txd)
521{
522}
523static inline void txd_clear_next(struct dma_async_tx_descriptor *txd)
524{
525}
526static inline struct dma_async_tx_descriptor *txd_next(struct dma_async_tx_descriptor *txd)
527{
528 return NULL;
529}
530static inline struct dma_async_tx_descriptor *txd_parent(struct dma_async_tx_descriptor *txd)
531{
532 return NULL;
533}
534
535#else
536static inline void txd_lock(struct dma_async_tx_descriptor *txd)
537{
538 spin_lock_bh(&txd->lock);
539}
540static inline void txd_unlock(struct dma_async_tx_descriptor *txd)
541{
542 spin_unlock_bh(&txd->lock);
543}
544static inline void txd_chain(struct dma_async_tx_descriptor *txd, struct dma_async_tx_descriptor *next)
545{
546 txd->next = next;
547 next->parent = txd;
548}
549static inline void txd_clear_parent(struct dma_async_tx_descriptor *txd)
550{
551 txd->parent = NULL;
552}
553static inline void txd_clear_next(struct dma_async_tx_descriptor *txd)
554{
555 txd->next = NULL;
556}
557static inline struct dma_async_tx_descriptor *txd_parent(struct dma_async_tx_descriptor *txd)
558{
559 return txd->parent;
560}
561static inline struct dma_async_tx_descriptor *txd_next(struct dma_async_tx_descriptor *txd)
562{
563 return txd->next;
564}
565#endif
566
Chris Leechc13c8262006-05-23 17:18:44 -0700567/**
Linus Walleij07934482010-03-26 16:50:49 -0700568 * struct dma_tx_state - filled in to report the status of
569 * a transfer.
570 * @last: last completed DMA cookie
571 * @used: last issued DMA cookie (i.e. the one in progress)
572 * @residue: the remaining number of bytes left to transmit
573 * on the selected transfer for states DMA_IN_PROGRESS and
574 * DMA_PAUSED if this is implemented in the driver, else 0
575 */
576struct dma_tx_state {
577 dma_cookie_t last;
578 dma_cookie_t used;
579 u32 residue;
580};
581
582/**
Chris Leechc13c8262006-05-23 17:18:44 -0700583 * struct dma_device - info on the entity supplying DMA services
584 * @chancnt: how many DMA channels are supported
Atsushi Nemoto0f571512009-03-06 20:07:14 +0900585 * @privatecnt: how many DMA channels are requested by dma_request_channel
Chris Leechc13c8262006-05-23 17:18:44 -0700586 * @channels: the list of struct dma_chan
587 * @global_node: list_head for global dma_device_list
Dan Williams7405f742007-01-02 11:10:43 -0700588 * @cap_mask: one or more dma_capability flags
589 * @max_xor: maximum number of xor sources, 0 if no capability
Dan Williamsb2f46fd2009-07-14 12:20:36 -0700590 * @max_pq: maximum number of PQ sources and PQ-continue capability
Dan Williams83544ae2009-09-08 17:42:53 -0700591 * @copy_align: alignment shift for memcpy operations
592 * @xor_align: alignment shift for xor operations
593 * @pq_align: alignment shift for pq operations
594 * @fill_align: alignment shift for memset operations
Randy Dunlapfe4ada22006-07-03 19:44:51 -0700595 * @dev_id: unique device ID
Dan Williams7405f742007-01-02 11:10:43 -0700596 * @dev: struct device reference for dma mapping api
Randy Dunlapfe4ada22006-07-03 19:44:51 -0700597 * @device_alloc_chan_resources: allocate resources and return the
598 * number of allocated descriptors
599 * @device_free_chan_resources: release DMA channel's resources
Dan Williams7405f742007-01-02 11:10:43 -0700600 * @device_prep_dma_memcpy: prepares a memcpy operation
601 * @device_prep_dma_xor: prepares a xor operation
Dan Williams099f53c2009-04-08 14:28:37 -0700602 * @device_prep_dma_xor_val: prepares a xor validation operation
Dan Williamsb2f46fd2009-07-14 12:20:36 -0700603 * @device_prep_dma_pq: prepares a pq operation
604 * @device_prep_dma_pq_val: prepares a pqzero_sum operation
Dan Williams7405f742007-01-02 11:10:43 -0700605 * @device_prep_dma_interrupt: prepares an end of chain interrupt operation
Haavard Skinnemoendc0ee6432008-07-08 11:59:35 -0700606 * @device_prep_slave_sg: prepares a slave dma operation
Sascha Hauer782bc952010-09-30 13:56:32 +0000607 * @device_prep_dma_cyclic: prepare a cyclic dma operation suitable for audio.
608 * The function takes a buffer of size buf_len. The callback function will
609 * be called after period_len bytes have been transferred.
Jassi Brarb14dab72011-10-13 12:33:30 +0530610 * @device_prep_interleaved_dma: Transfer expression in a generic way.
Linus Walleijc3635c72010-03-26 16:44:01 -0700611 * @device_control: manipulate all pending operations on a channel, returns
612 * zero or error code
Linus Walleij07934482010-03-26 16:50:49 -0700613 * @device_tx_status: poll for transaction completion, the optional
614 * txstate parameter can be supplied with a pointer to get a
Lucas De Marchi25985ed2011-03-30 22:57:33 -0300615 * struct with auxiliary transfer status information, otherwise the call
Linus Walleij07934482010-03-26 16:50:49 -0700616 * will just return a simple status code
Dan Williams7405f742007-01-02 11:10:43 -0700617 * @device_issue_pending: push pending transactions to hardware
Vinod Koul221a27c72013-07-08 14:15:25 +0530618 * @device_slave_caps: return the slave channel capabilities
Chris Leechc13c8262006-05-23 17:18:44 -0700619 */
620struct dma_device {
621
622 unsigned int chancnt;
Atsushi Nemoto0f571512009-03-06 20:07:14 +0900623 unsigned int privatecnt;
Chris Leechc13c8262006-05-23 17:18:44 -0700624 struct list_head channels;
625 struct list_head global_node;
Dan Williams7405f742007-01-02 11:10:43 -0700626 dma_cap_mask_t cap_mask;
Dan Williamsb2f46fd2009-07-14 12:20:36 -0700627 unsigned short max_xor;
628 unsigned short max_pq;
Dan Williams83544ae2009-09-08 17:42:53 -0700629 u8 copy_align;
630 u8 xor_align;
631 u8 pq_align;
632 u8 fill_align;
Dan Williamsb2f46fd2009-07-14 12:20:36 -0700633 #define DMA_HAS_PQ_CONTINUE (1 << 15)
Chris Leechc13c8262006-05-23 17:18:44 -0700634
Chris Leechc13c8262006-05-23 17:18:44 -0700635 int dev_id;
Dan Williams7405f742007-01-02 11:10:43 -0700636 struct device *dev;
Chris Leechc13c8262006-05-23 17:18:44 -0700637
Dan Williamsaa1e6f12009-01-06 11:38:17 -0700638 int (*device_alloc_chan_resources)(struct dma_chan *chan);
Chris Leechc13c8262006-05-23 17:18:44 -0700639 void (*device_free_chan_resources)(struct dma_chan *chan);
Dan Williams7405f742007-01-02 11:10:43 -0700640
641 struct dma_async_tx_descriptor *(*device_prep_dma_memcpy)(
Dan Williams00367312008-02-02 19:49:57 -0700642 struct dma_chan *chan, dma_addr_t dest, dma_addr_t src,
Dan Williamsd4c56f92008-02-02 19:49:58 -0700643 size_t len, unsigned long flags);
Dan Williams7405f742007-01-02 11:10:43 -0700644 struct dma_async_tx_descriptor *(*device_prep_dma_xor)(
Dan Williams00367312008-02-02 19:49:57 -0700645 struct dma_chan *chan, dma_addr_t dest, dma_addr_t *src,
Dan Williamsd4c56f92008-02-02 19:49:58 -0700646 unsigned int src_cnt, size_t len, unsigned long flags);
Dan Williams099f53c2009-04-08 14:28:37 -0700647 struct dma_async_tx_descriptor *(*device_prep_dma_xor_val)(
Dan Williams00367312008-02-02 19:49:57 -0700648 struct dma_chan *chan, dma_addr_t *src, unsigned int src_cnt,
Dan Williamsad283ea2009-08-29 19:09:26 -0700649 size_t len, enum sum_check_flags *result, unsigned long flags);
Dan Williamsb2f46fd2009-07-14 12:20:36 -0700650 struct dma_async_tx_descriptor *(*device_prep_dma_pq)(
651 struct dma_chan *chan, dma_addr_t *dst, dma_addr_t *src,
652 unsigned int src_cnt, const unsigned char *scf,
653 size_t len, unsigned long flags);
654 struct dma_async_tx_descriptor *(*device_prep_dma_pq_val)(
655 struct dma_chan *chan, dma_addr_t *pq, dma_addr_t *src,
656 unsigned int src_cnt, const unsigned char *scf, size_t len,
657 enum sum_check_flags *pqres, unsigned long flags);
Dan Williams7405f742007-01-02 11:10:43 -0700658 struct dma_async_tx_descriptor *(*device_prep_dma_interrupt)(
Dan Williams636bdea2008-04-17 20:17:26 -0700659 struct dma_chan *chan, unsigned long flags);
Ira Snydera86ee032010-09-30 11:46:44 +0000660 struct dma_async_tx_descriptor *(*device_prep_dma_sg)(
661 struct dma_chan *chan,
662 struct scatterlist *dst_sg, unsigned int dst_nents,
663 struct scatterlist *src_sg, unsigned int src_nents,
664 unsigned long flags);
Dan Williams7405f742007-01-02 11:10:43 -0700665
Haavard Skinnemoendc0ee6432008-07-08 11:59:35 -0700666 struct dma_async_tx_descriptor *(*device_prep_slave_sg)(
667 struct dma_chan *chan, struct scatterlist *sgl,
Vinod Koul49920bc2011-10-13 15:15:27 +0530668 unsigned int sg_len, enum dma_transfer_direction direction,
Alexandre Bounine185ecb52012-03-08 15:35:13 -0500669 unsigned long flags, void *context);
Sascha Hauer782bc952010-09-30 13:56:32 +0000670 struct dma_async_tx_descriptor *(*device_prep_dma_cyclic)(
671 struct dma_chan *chan, dma_addr_t buf_addr, size_t buf_len,
Alexandre Bounine185ecb52012-03-08 15:35:13 -0500672 size_t period_len, enum dma_transfer_direction direction,
Laurent Pinchart31c1e5a2014-08-01 12:20:10 +0200673 unsigned long flags);
Jassi Brarb14dab72011-10-13 12:33:30 +0530674 struct dma_async_tx_descriptor *(*device_prep_interleaved_dma)(
675 struct dma_chan *chan, struct dma_interleaved_template *xt,
676 unsigned long flags);
Linus Walleij05827632010-05-17 16:30:42 -0700677 int (*device_control)(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
678 unsigned long arg);
Haavard Skinnemoendc0ee6432008-07-08 11:59:35 -0700679
Linus Walleij07934482010-03-26 16:50:49 -0700680 enum dma_status (*device_tx_status)(struct dma_chan *chan,
681 dma_cookie_t cookie,
682 struct dma_tx_state *txstate);
Dan Williams7405f742007-01-02 11:10:43 -0700683 void (*device_issue_pending)(struct dma_chan *chan);
Vinod Koul221a27c72013-07-08 14:15:25 +0530684 int (*device_slave_caps)(struct dma_chan *chan, struct dma_slave_caps *caps);
Chris Leechc13c8262006-05-23 17:18:44 -0700685};
686
Sascha Hauer6e3ecaf2010-09-30 13:56:33 +0000687static inline int dmaengine_device_control(struct dma_chan *chan,
688 enum dma_ctrl_cmd cmd,
689 unsigned long arg)
690{
Jon Mason944ea4d2012-11-11 23:03:20 +0000691 if (chan->device->device_control)
692 return chan->device->device_control(chan, cmd, arg);
Andy Shevchenko978c4172013-02-14 11:00:16 +0200693
694 return -ENOSYS;
Sascha Hauer6e3ecaf2010-09-30 13:56:33 +0000695}
696
697static inline int dmaengine_slave_config(struct dma_chan *chan,
698 struct dma_slave_config *config)
699{
700 return dmaengine_device_control(chan, DMA_SLAVE_CONFIG,
701 (unsigned long)config);
702}
703
Andy Shevchenko61cc13a2013-01-10 10:52:56 +0200704static inline bool is_slave_direction(enum dma_transfer_direction direction)
705{
706 return (direction == DMA_MEM_TO_DEV) || (direction == DMA_DEV_TO_MEM);
707}
708
Vinod Koul90b44f82011-07-25 19:57:52 +0530709static inline struct dma_async_tx_descriptor *dmaengine_prep_slave_single(
Kuninori Morimoto922ee082012-04-25 20:50:53 +0200710 struct dma_chan *chan, dma_addr_t buf, size_t len,
Vinod Koul49920bc2011-10-13 15:15:27 +0530711 enum dma_transfer_direction dir, unsigned long flags)
Vinod Koul90b44f82011-07-25 19:57:52 +0530712{
713 struct scatterlist sg;
Kuninori Morimoto922ee082012-04-25 20:50:53 +0200714 sg_init_table(&sg, 1);
715 sg_dma_address(&sg) = buf;
716 sg_dma_len(&sg) = len;
Vinod Koul90b44f82011-07-25 19:57:52 +0530717
Alexandre Bounine185ecb52012-03-08 15:35:13 -0500718 return chan->device->device_prep_slave_sg(chan, &sg, 1,
719 dir, flags, NULL);
Vinod Koul90b44f82011-07-25 19:57:52 +0530720}
721
Alexandre Bounine16052822012-03-08 16:11:18 -0500722static inline struct dma_async_tx_descriptor *dmaengine_prep_slave_sg(
723 struct dma_chan *chan, struct scatterlist *sgl, unsigned int sg_len,
724 enum dma_transfer_direction dir, unsigned long flags)
725{
726 return chan->device->device_prep_slave_sg(chan, sgl, sg_len,
Alexandre Bounine185ecb52012-03-08 15:35:13 -0500727 dir, flags, NULL);
Alexandre Bounine16052822012-03-08 16:11:18 -0500728}
729
Alexandre Bouninee42d98e2012-05-31 16:26:38 -0700730#ifdef CONFIG_RAPIDIO_DMA_ENGINE
731struct rio_dma_ext;
732static inline struct dma_async_tx_descriptor *dmaengine_prep_rio_sg(
733 struct dma_chan *chan, struct scatterlist *sgl, unsigned int sg_len,
734 enum dma_transfer_direction dir, unsigned long flags,
735 struct rio_dma_ext *rio_ext)
736{
737 return chan->device->device_prep_slave_sg(chan, sgl, sg_len,
738 dir, flags, rio_ext);
739}
740#endif
741
Alexandre Bounine16052822012-03-08 16:11:18 -0500742static inline struct dma_async_tx_descriptor *dmaengine_prep_dma_cyclic(
743 struct dma_chan *chan, dma_addr_t buf_addr, size_t buf_len,
Peter Ujfalusie7736cd2012-09-24 10:58:04 +0300744 size_t period_len, enum dma_transfer_direction dir,
745 unsigned long flags)
Alexandre Bounine16052822012-03-08 16:11:18 -0500746{
747 return chan->device->device_prep_dma_cyclic(chan, buf_addr, buf_len,
Laurent Pinchart31c1e5a2014-08-01 12:20:10 +0200748 period_len, dir, flags);
Sascha Hauer6e3ecaf2010-09-30 13:56:33 +0000749}
750
Barry Songa14acb42012-11-06 21:32:39 +0800751static inline struct dma_async_tx_descriptor *dmaengine_prep_interleaved_dma(
752 struct dma_chan *chan, struct dma_interleaved_template *xt,
753 unsigned long flags)
754{
755 return chan->device->device_prep_interleaved_dma(chan, xt, flags);
756}
757
Vinod Koul221a27c72013-07-08 14:15:25 +0530758static inline int dma_get_slave_caps(struct dma_chan *chan, struct dma_slave_caps *caps)
759{
760 if (!chan || !caps)
761 return -EINVAL;
762
763 /* check if the channel supports slave transactions */
764 if (!test_bit(DMA_SLAVE, chan->device->cap_mask.bits))
765 return -ENXIO;
766
767 if (chan->device->device_slave_caps)
768 return chan->device->device_slave_caps(chan, caps);
769
770 return -ENXIO;
771}
772
Sascha Hauer6e3ecaf2010-09-30 13:56:33 +0000773static inline int dmaengine_terminate_all(struct dma_chan *chan)
774{
775 return dmaengine_device_control(chan, DMA_TERMINATE_ALL, 0);
776}
777
778static inline int dmaengine_pause(struct dma_chan *chan)
779{
780 return dmaengine_device_control(chan, DMA_PAUSE, 0);
781}
782
783static inline int dmaengine_resume(struct dma_chan *chan)
784{
785 return dmaengine_device_control(chan, DMA_RESUME, 0);
786}
787
Lars-Peter Clausen3052cc22012-06-11 20:11:40 +0200788static inline enum dma_status dmaengine_tx_status(struct dma_chan *chan,
789 dma_cookie_t cookie, struct dma_tx_state *state)
790{
791 return chan->device->device_tx_status(chan, cookie, state);
792}
793
Russell King - ARM Linux98d530f2011-01-01 23:00:23 +0000794static inline dma_cookie_t dmaengine_submit(struct dma_async_tx_descriptor *desc)
Sascha Hauer6e3ecaf2010-09-30 13:56:33 +0000795{
796 return desc->tx_submit(desc);
797}
798
Dan Williams83544ae2009-09-08 17:42:53 -0700799static inline bool dmaengine_check_align(u8 align, size_t off1, size_t off2, size_t len)
800{
801 size_t mask;
802
803 if (!align)
804 return true;
805 mask = (1 << align) - 1;
806 if (mask & (off1 | off2 | len))
807 return false;
808 return true;
809}
810
811static inline bool is_dma_copy_aligned(struct dma_device *dev, size_t off1,
812 size_t off2, size_t len)
813{
814 return dmaengine_check_align(dev->copy_align, off1, off2, len);
815}
816
817static inline bool is_dma_xor_aligned(struct dma_device *dev, size_t off1,
818 size_t off2, size_t len)
819{
820 return dmaengine_check_align(dev->xor_align, off1, off2, len);
821}
822
823static inline bool is_dma_pq_aligned(struct dma_device *dev, size_t off1,
824 size_t off2, size_t len)
825{
826 return dmaengine_check_align(dev->pq_align, off1, off2, len);
827}
828
829static inline bool is_dma_fill_aligned(struct dma_device *dev, size_t off1,
830 size_t off2, size_t len)
831{
832 return dmaengine_check_align(dev->fill_align, off1, off2, len);
833}
834
Dan Williamsb2f46fd2009-07-14 12:20:36 -0700835static inline void
836dma_set_maxpq(struct dma_device *dma, int maxpq, int has_pq_continue)
837{
838 dma->max_pq = maxpq;
839 if (has_pq_continue)
840 dma->max_pq |= DMA_HAS_PQ_CONTINUE;
841}
842
843static inline bool dmaf_continue(enum dma_ctrl_flags flags)
844{
845 return (flags & DMA_PREP_CONTINUE) == DMA_PREP_CONTINUE;
846}
847
848static inline bool dmaf_p_disabled_continue(enum dma_ctrl_flags flags)
849{
850 enum dma_ctrl_flags mask = DMA_PREP_CONTINUE | DMA_PREP_PQ_DISABLE_P;
851
852 return (flags & mask) == mask;
853}
854
855static inline bool dma_dev_has_pq_continue(struct dma_device *dma)
856{
857 return (dma->max_pq & DMA_HAS_PQ_CONTINUE) == DMA_HAS_PQ_CONTINUE;
858}
859
Mathieu Lacaged3f3cf82010-08-14 15:02:44 +0200860static inline unsigned short dma_dev_to_maxpq(struct dma_device *dma)
Dan Williamsb2f46fd2009-07-14 12:20:36 -0700861{
862 return dma->max_pq & ~DMA_HAS_PQ_CONTINUE;
863}
864
865/* dma_maxpq - reduce maxpq in the face of continued operations
866 * @dma - dma device with PQ capability
867 * @flags - to check if DMA_PREP_CONTINUE and DMA_PREP_PQ_DISABLE_P are set
868 *
869 * When an engine does not support native continuation we need 3 extra
870 * source slots to reuse P and Q with the following coefficients:
871 * 1/ {00} * P : remove P from Q', but use it as a source for P'
872 * 2/ {01} * Q : use Q to continue Q' calculation
873 * 3/ {00} * Q : subtract Q from P' to cancel (2)
874 *
875 * In the case where P is disabled we only need 1 extra source:
876 * 1/ {01} * Q : use Q to continue Q' calculation
877 */
878static inline int dma_maxpq(struct dma_device *dma, enum dma_ctrl_flags flags)
879{
880 if (dma_dev_has_pq_continue(dma) || !dmaf_continue(flags))
881 return dma_dev_to_maxpq(dma);
882 else if (dmaf_p_disabled_continue(flags))
883 return dma_dev_to_maxpq(dma) - 1;
884 else if (dmaf_continue(flags))
885 return dma_dev_to_maxpq(dma) - 3;
886 BUG();
887}
888
Chris Leechc13c8262006-05-23 17:18:44 -0700889/* --- public DMA engine API --- */
890
Dan Williams649274d2009-01-11 00:20:39 -0800891#ifdef CONFIG_DMA_ENGINE
Dan Williams209b84a2009-01-06 11:38:17 -0700892void dmaengine_get(void);
893void dmaengine_put(void);
Dan Williams649274d2009-01-11 00:20:39 -0800894#else
895static inline void dmaengine_get(void)
896{
897}
898static inline void dmaengine_put(void)
899{
900}
901#endif
902
David S. Millerb4bd07c2009-02-06 22:06:43 -0800903#ifdef CONFIG_NET_DMA
904#define net_dmaengine_get() dmaengine_get()
905#define net_dmaengine_put() dmaengine_put()
906#else
907static inline void net_dmaengine_get(void)
908{
909}
910static inline void net_dmaengine_put(void)
911{
912}
913#endif
914
Dan Williams729b5d12009-03-25 09:13:25 -0700915#ifdef CONFIG_ASYNC_TX_DMA
916#define async_dmaengine_get() dmaengine_get()
917#define async_dmaengine_put() dmaengine_put()
Dan Williams5fc6d892010-10-07 16:44:50 -0700918#ifndef CONFIG_ASYNC_TX_ENABLE_CHANNEL_SWITCH
Dan Williams138f4c32009-09-08 17:42:51 -0700919#define async_dma_find_channel(type) dma_find_channel(DMA_ASYNC_TX)
920#else
Dan Williams729b5d12009-03-25 09:13:25 -0700921#define async_dma_find_channel(type) dma_find_channel(type)
Dan Williams5fc6d892010-10-07 16:44:50 -0700922#endif /* CONFIG_ASYNC_TX_ENABLE_CHANNEL_SWITCH */
Dan Williams729b5d12009-03-25 09:13:25 -0700923#else
924static inline void async_dmaengine_get(void)
925{
926}
927static inline void async_dmaengine_put(void)
928{
929}
930static inline struct dma_chan *
931async_dma_find_channel(enum dma_transaction_type type)
932{
933 return NULL;
934}
Dan Williams138f4c32009-09-08 17:42:51 -0700935#endif /* CONFIG_ASYNC_TX_DMA */
Dan Williams729b5d12009-03-25 09:13:25 -0700936
Dan Williams7405f742007-01-02 11:10:43 -0700937dma_cookie_t dma_async_memcpy_buf_to_buf(struct dma_chan *chan,
938 void *dest, void *src, size_t len);
939dma_cookie_t dma_async_memcpy_buf_to_pg(struct dma_chan *chan,
940 struct page *page, unsigned int offset, void *kdata, size_t len);
941dma_cookie_t dma_async_memcpy_pg_to_pg(struct dma_chan *chan,
Chris Leechc13c8262006-05-23 17:18:44 -0700942 struct page *dest_pg, unsigned int dest_off, struct page *src_pg,
Dan Williams7405f742007-01-02 11:10:43 -0700943 unsigned int src_off, size_t len);
944void dma_async_tx_descriptor_init(struct dma_async_tx_descriptor *tx,
945 struct dma_chan *chan);
Chris Leechc13c8262006-05-23 17:18:44 -0700946
Dan Williams08398752008-07-17 17:59:56 -0700947static inline void async_tx_ack(struct dma_async_tx_descriptor *tx)
Dan Williams7405f742007-01-02 11:10:43 -0700948{
Dan Williams636bdea2008-04-17 20:17:26 -0700949 tx->flags |= DMA_CTRL_ACK;
950}
951
Guennadi Liakhovetskief560682009-01-19 15:36:21 -0700952static inline void async_tx_clear_ack(struct dma_async_tx_descriptor *tx)
953{
954 tx->flags &= ~DMA_CTRL_ACK;
955}
956
Dan Williams08398752008-07-17 17:59:56 -0700957static inline bool async_tx_test_ack(struct dma_async_tx_descriptor *tx)
Dan Williams636bdea2008-04-17 20:17:26 -0700958{
Dan Williams08398752008-07-17 17:59:56 -0700959 return (tx->flags & DMA_CTRL_ACK) == DMA_CTRL_ACK;
Chris Leechc13c8262006-05-23 17:18:44 -0700960}
961
Dan Williams7405f742007-01-02 11:10:43 -0700962#define dma_cap_set(tx, mask) __dma_cap_set((tx), &(mask))
963static inline void
964__dma_cap_set(enum dma_transaction_type tx_type, dma_cap_mask_t *dstp)
965{
966 set_bit(tx_type, dstp->bits);
967}
968
Atsushi Nemoto0f571512009-03-06 20:07:14 +0900969#define dma_cap_clear(tx, mask) __dma_cap_clear((tx), &(mask))
970static inline void
971__dma_cap_clear(enum dma_transaction_type tx_type, dma_cap_mask_t *dstp)
972{
973 clear_bit(tx_type, dstp->bits);
974}
975
Dan Williams33df8ca2009-01-06 11:38:15 -0700976#define dma_cap_zero(mask) __dma_cap_zero(&(mask))
977static inline void __dma_cap_zero(dma_cap_mask_t *dstp)
978{
979 bitmap_zero(dstp->bits, DMA_TX_TYPE_END);
980}
981
Dan Williams7405f742007-01-02 11:10:43 -0700982#define dma_has_cap(tx, mask) __dma_has_cap((tx), &(mask))
983static inline int
984__dma_has_cap(enum dma_transaction_type tx_type, dma_cap_mask_t *srcp)
985{
986 return test_bit(tx_type, srcp->bits);
987}
988
989#define for_each_dma_cap_mask(cap, mask) \
Akinobu Mitae5a087f2012-10-26 23:35:15 +0900990 for_each_set_bit(cap, mask.bits, DMA_TX_TYPE_END)
Dan Williams7405f742007-01-02 11:10:43 -0700991
Chris Leechc13c8262006-05-23 17:18:44 -0700992/**
Dan Williams7405f742007-01-02 11:10:43 -0700993 * dma_async_issue_pending - flush pending transactions to HW
Randy Dunlapfe4ada22006-07-03 19:44:51 -0700994 * @chan: target DMA channel
Chris Leechc13c8262006-05-23 17:18:44 -0700995 *
996 * This allows drivers to push copies to HW in batches,
997 * reducing MMIO writes where possible.
998 */
Dan Williams7405f742007-01-02 11:10:43 -0700999static inline void dma_async_issue_pending(struct dma_chan *chan)
Chris Leechc13c8262006-05-23 17:18:44 -07001000{
Dan Williamsec8670f2008-03-01 07:51:29 -07001001 chan->device->device_issue_pending(chan);
Chris Leechc13c8262006-05-23 17:18:44 -07001002}
1003
1004/**
Dan Williams7405f742007-01-02 11:10:43 -07001005 * dma_async_is_tx_complete - poll for transaction completion
Chris Leechc13c8262006-05-23 17:18:44 -07001006 * @chan: DMA channel
1007 * @cookie: transaction identifier to check status of
1008 * @last: returns last completed cookie, can be NULL
1009 * @used: returns last issued cookie, can be NULL
1010 *
1011 * If @last and @used are passed in, upon return they reflect the driver
1012 * internal state and can be used with dma_async_is_complete() to check
1013 * the status of multiple cookies without re-checking hardware state.
1014 */
Dan Williams7405f742007-01-02 11:10:43 -07001015static inline enum dma_status dma_async_is_tx_complete(struct dma_chan *chan,
Chris Leechc13c8262006-05-23 17:18:44 -07001016 dma_cookie_t cookie, dma_cookie_t *last, dma_cookie_t *used)
1017{
Linus Walleij07934482010-03-26 16:50:49 -07001018 struct dma_tx_state state;
1019 enum dma_status status;
1020
1021 status = chan->device->device_tx_status(chan, cookie, &state);
1022 if (last)
1023 *last = state.last;
1024 if (used)
1025 *used = state.used;
1026 return status;
Chris Leechc13c8262006-05-23 17:18:44 -07001027}
1028
1029/**
1030 * dma_async_is_complete - test a cookie against chan state
1031 * @cookie: transaction identifier to test status of
1032 * @last_complete: last know completed transaction
1033 * @last_used: last cookie value handed out
1034 *
Bartlomiej Zolnierkiewicze239345f2012-11-08 10:01:01 +00001035 * dma_async_is_complete() is used in dma_async_is_tx_complete()
Sebastian Siewior8a5703f2008-04-21 22:38:45 +00001036 * the test logic is separated for lightweight testing of multiple cookies
Chris Leechc13c8262006-05-23 17:18:44 -07001037 */
1038static inline enum dma_status dma_async_is_complete(dma_cookie_t cookie,
1039 dma_cookie_t last_complete, dma_cookie_t last_used)
1040{
1041 if (last_complete <= last_used) {
1042 if ((cookie <= last_complete) || (cookie > last_used))
Vinod Kouladfedd92013-10-16 13:29:02 +05301043 return DMA_COMPLETE;
Chris Leechc13c8262006-05-23 17:18:44 -07001044 } else {
1045 if ((cookie <= last_complete) && (cookie > last_used))
Vinod Kouladfedd92013-10-16 13:29:02 +05301046 return DMA_COMPLETE;
Chris Leechc13c8262006-05-23 17:18:44 -07001047 }
1048 return DMA_IN_PROGRESS;
1049}
1050
Dan Williamsbca34692010-03-26 16:52:10 -07001051static inline void
1052dma_set_tx_state(struct dma_tx_state *st, dma_cookie_t last, dma_cookie_t used, u32 residue)
1053{
1054 if (st) {
1055 st->last = last;
1056 st->used = used;
1057 st->residue = residue;
1058 }
1059}
1060
Dan Williams07f22112009-01-05 17:14:31 -07001061#ifdef CONFIG_DMA_ENGINE
Jon Mason4a43f392013-09-09 16:51:59 -07001062struct dma_chan *dma_find_channel(enum dma_transaction_type tx_type);
1063enum dma_status dma_sync_wait(struct dma_chan *chan, dma_cookie_t cookie);
Dan Williams07f22112009-01-05 17:14:31 -07001064enum dma_status dma_wait_for_async_tx(struct dma_async_tx_descriptor *tx);
Dan Williamsc50331e2009-01-19 15:33:14 -07001065void dma_issue_pending_all(void);
Lars-Peter Clausena53e28d2013-03-25 13:23:52 +01001066struct dma_chan *__dma_request_channel(const dma_cap_mask_t *mask,
1067 dma_filter_fn fn, void *fn_param);
Stephen Warren0ad7c002013-11-26 10:04:22 -07001068struct dma_chan *dma_request_slave_channel_reason(struct device *dev,
1069 const char *name);
Markus Pargmannbef29ec2013-02-24 16:36:09 +01001070struct dma_chan *dma_request_slave_channel(struct device *dev, const char *name);
Guennadi Liakhovetski8f33d522010-12-22 14:46:46 +01001071void dma_release_channel(struct dma_chan *chan);
Dan Williams07f22112009-01-05 17:14:31 -07001072#else
Jon Mason4a43f392013-09-09 16:51:59 -07001073static inline struct dma_chan *dma_find_channel(enum dma_transaction_type tx_type)
1074{
1075 return NULL;
1076}
1077static inline enum dma_status dma_sync_wait(struct dma_chan *chan, dma_cookie_t cookie)
1078{
Vinod Kouladfedd92013-10-16 13:29:02 +05301079 return DMA_COMPLETE;
Jon Mason4a43f392013-09-09 16:51:59 -07001080}
Dan Williams07f22112009-01-05 17:14:31 -07001081static inline enum dma_status dma_wait_for_async_tx(struct dma_async_tx_descriptor *tx)
1082{
Vinod Kouladfedd92013-10-16 13:29:02 +05301083 return DMA_COMPLETE;
Dan Williams07f22112009-01-05 17:14:31 -07001084}
Dan Williamsc50331e2009-01-19 15:33:14 -07001085static inline void dma_issue_pending_all(void)
1086{
Guennadi Liakhovetski8f33d522010-12-22 14:46:46 +01001087}
Lars-Peter Clausena53e28d2013-03-25 13:23:52 +01001088static inline struct dma_chan *__dma_request_channel(const dma_cap_mask_t *mask,
Guennadi Liakhovetski8f33d522010-12-22 14:46:46 +01001089 dma_filter_fn fn, void *fn_param)
1090{
1091 return NULL;
1092}
Stephen Warren0ad7c002013-11-26 10:04:22 -07001093static inline struct dma_chan *dma_request_slave_channel_reason(
1094 struct device *dev, const char *name)
1095{
1096 return ERR_PTR(-ENODEV);
1097}
Jon Hunter9a6cecc2012-09-14 17:41:57 -05001098static inline struct dma_chan *dma_request_slave_channel(struct device *dev,
Markus Pargmannbef29ec2013-02-24 16:36:09 +01001099 const char *name)
Jon Hunter9a6cecc2012-09-14 17:41:57 -05001100{
Vinod Kould18d5f52012-09-25 16:18:55 +05301101 return NULL;
Jon Hunter9a6cecc2012-09-14 17:41:57 -05001102}
Guennadi Liakhovetski8f33d522010-12-22 14:46:46 +01001103static inline void dma_release_channel(struct dma_chan *chan)
1104{
Dan Williamsc50331e2009-01-19 15:33:14 -07001105}
Dan Williams07f22112009-01-05 17:14:31 -07001106#endif
Chris Leechc13c8262006-05-23 17:18:44 -07001107
1108/* --- DMA device --- */
1109
1110int dma_async_device_register(struct dma_device *device);
1111void dma_async_device_unregister(struct dma_device *device);
Dan Williams07f22112009-01-05 17:14:31 -07001112void dma_run_dependencies(struct dma_async_tx_descriptor *tx);
Zhangfei Gao7bb587f2013-06-28 20:39:12 +08001113struct dma_chan *dma_get_slave_channel(struct dma_chan *chan);
Stephen Warren8010dad2013-11-26 12:40:51 -07001114struct dma_chan *dma_get_any_slave_channel(struct dma_device *device);
Dave Jianga2bd1142012-04-04 16:10:46 -07001115struct dma_chan *net_dma_find_channel(void);
Dan Williams59b5ec22009-01-06 11:38:15 -07001116#define dma_request_channel(mask, x, y) __dma_request_channel(&(mask), x, y)
Matt Porter864ef692013-02-01 18:22:52 +00001117#define dma_request_slave_channel_compat(mask, x, y, dev, name) \
1118 __dma_request_slave_channel_compat(&(mask), x, y, dev, name)
1119
1120static inline struct dma_chan
Lars-Peter Clausena53e28d2013-03-25 13:23:52 +01001121*__dma_request_slave_channel_compat(const dma_cap_mask_t *mask,
1122 dma_filter_fn fn, void *fn_param,
1123 struct device *dev, char *name)
Matt Porter864ef692013-02-01 18:22:52 +00001124{
1125 struct dma_chan *chan;
1126
1127 chan = dma_request_slave_channel(dev, name);
1128 if (chan)
1129 return chan;
1130
1131 return __dma_request_channel(mask, fn, fn_param);
1132}
Chris Leechc13c8262006-05-23 17:18:44 -07001133
Chris Leechde5506e2006-05-23 17:50:37 -07001134/* --- Helper iov-locking functions --- */
1135
1136struct dma_page_list {
Al Virob2ddb902008-03-29 03:09:38 +00001137 char __user *base_address;
Chris Leechde5506e2006-05-23 17:50:37 -07001138 int nr_pages;
1139 struct page **pages;
1140};
1141
1142struct dma_pinned_list {
1143 int nr_iovecs;
1144 struct dma_page_list page_list[0];
1145};
1146
1147struct dma_pinned_list *dma_pin_iovec_pages(struct iovec *iov, size_t len);
1148void dma_unpin_iovec_pages(struct dma_pinned_list* pinned_list);
1149
1150dma_cookie_t dma_memcpy_to_iovec(struct dma_chan *chan, struct iovec *iov,
1151 struct dma_pinned_list *pinned_list, unsigned char *kdata, size_t len);
1152dma_cookie_t dma_memcpy_pg_to_iovec(struct dma_chan *chan, struct iovec *iov,
1153 struct dma_pinned_list *pinned_list, struct page *page,
1154 unsigned int offset, size_t len);
1155
Chris Leechc13c8262006-05-23 17:18:44 -07001156#endif /* DMAENGINE_H */