Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1 | /* |
| 2 | * linux/drivers/video/omap2/dss/dsi.c |
| 3 | * |
| 4 | * Copyright (C) 2009 Nokia Corporation |
| 5 | * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com> |
| 6 | * |
| 7 | * This program is free software; you can redistribute it and/or modify it |
| 8 | * under the terms of the GNU General Public License version 2 as published by |
| 9 | * the Free Software Foundation. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, but WITHOUT |
| 12 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
| 13 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for |
| 14 | * more details. |
| 15 | * |
| 16 | * You should have received a copy of the GNU General Public License along with |
| 17 | * this program. If not, see <http://www.gnu.org/licenses/>. |
| 18 | */ |
| 19 | |
| 20 | #define DSS_SUBSYS_NAME "DSI" |
| 21 | |
| 22 | #include <linux/kernel.h> |
| 23 | #include <linux/io.h> |
| 24 | #include <linux/clk.h> |
| 25 | #include <linux/device.h> |
| 26 | #include <linux/err.h> |
| 27 | #include <linux/interrupt.h> |
| 28 | #include <linux/delay.h> |
| 29 | #include <linux/mutex.h> |
Tomi Valkeinen | b9eb5d7 | 2010-01-11 16:33:56 +0200 | [diff] [blame] | 30 | #include <linux/semaphore.h> |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 31 | #include <linux/seq_file.h> |
| 32 | #include <linux/platform_device.h> |
| 33 | #include <linux/regulator/consumer.h> |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 34 | #include <linux/wait.h> |
Tomi Valkeinen | 18946f6 | 2010-01-12 14:16:41 +0200 | [diff] [blame] | 35 | #include <linux/workqueue.h> |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 36 | |
| 37 | #include <plat/display.h> |
| 38 | #include <plat/clock.h> |
| 39 | |
| 40 | #include "dss.h" |
Archit Taneja | 819d807 | 2011-03-01 11:54:00 +0530 | [diff] [blame] | 41 | #include "dss_features.h" |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 42 | |
| 43 | /*#define VERBOSE_IRQ*/ |
| 44 | #define DSI_CATCH_MISSING_TE |
| 45 | |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 46 | struct dsi_reg { u16 idx; }; |
| 47 | |
| 48 | #define DSI_REG(idx) ((const struct dsi_reg) { idx }) |
| 49 | |
| 50 | #define DSI_SZ_REGS SZ_1K |
| 51 | /* DSI Protocol Engine */ |
| 52 | |
| 53 | #define DSI_REVISION DSI_REG(0x0000) |
| 54 | #define DSI_SYSCONFIG DSI_REG(0x0010) |
| 55 | #define DSI_SYSSTATUS DSI_REG(0x0014) |
| 56 | #define DSI_IRQSTATUS DSI_REG(0x0018) |
| 57 | #define DSI_IRQENABLE DSI_REG(0x001C) |
| 58 | #define DSI_CTRL DSI_REG(0x0040) |
| 59 | #define DSI_COMPLEXIO_CFG1 DSI_REG(0x0048) |
| 60 | #define DSI_COMPLEXIO_IRQ_STATUS DSI_REG(0x004C) |
| 61 | #define DSI_COMPLEXIO_IRQ_ENABLE DSI_REG(0x0050) |
| 62 | #define DSI_CLK_CTRL DSI_REG(0x0054) |
| 63 | #define DSI_TIMING1 DSI_REG(0x0058) |
| 64 | #define DSI_TIMING2 DSI_REG(0x005C) |
| 65 | #define DSI_VM_TIMING1 DSI_REG(0x0060) |
| 66 | #define DSI_VM_TIMING2 DSI_REG(0x0064) |
| 67 | #define DSI_VM_TIMING3 DSI_REG(0x0068) |
| 68 | #define DSI_CLK_TIMING DSI_REG(0x006C) |
| 69 | #define DSI_TX_FIFO_VC_SIZE DSI_REG(0x0070) |
| 70 | #define DSI_RX_FIFO_VC_SIZE DSI_REG(0x0074) |
| 71 | #define DSI_COMPLEXIO_CFG2 DSI_REG(0x0078) |
| 72 | #define DSI_RX_FIFO_VC_FULLNESS DSI_REG(0x007C) |
| 73 | #define DSI_VM_TIMING4 DSI_REG(0x0080) |
| 74 | #define DSI_TX_FIFO_VC_EMPTINESS DSI_REG(0x0084) |
| 75 | #define DSI_VM_TIMING5 DSI_REG(0x0088) |
| 76 | #define DSI_VM_TIMING6 DSI_REG(0x008C) |
| 77 | #define DSI_VM_TIMING7 DSI_REG(0x0090) |
| 78 | #define DSI_STOPCLK_TIMING DSI_REG(0x0094) |
| 79 | #define DSI_VC_CTRL(n) DSI_REG(0x0100 + (n * 0x20)) |
| 80 | #define DSI_VC_TE(n) DSI_REG(0x0104 + (n * 0x20)) |
| 81 | #define DSI_VC_LONG_PACKET_HEADER(n) DSI_REG(0x0108 + (n * 0x20)) |
| 82 | #define DSI_VC_LONG_PACKET_PAYLOAD(n) DSI_REG(0x010C + (n * 0x20)) |
| 83 | #define DSI_VC_SHORT_PACKET_HEADER(n) DSI_REG(0x0110 + (n * 0x20)) |
| 84 | #define DSI_VC_IRQSTATUS(n) DSI_REG(0x0118 + (n * 0x20)) |
| 85 | #define DSI_VC_IRQENABLE(n) DSI_REG(0x011C + (n * 0x20)) |
| 86 | |
| 87 | /* DSIPHY_SCP */ |
| 88 | |
| 89 | #define DSI_DSIPHY_CFG0 DSI_REG(0x200 + 0x0000) |
| 90 | #define DSI_DSIPHY_CFG1 DSI_REG(0x200 + 0x0004) |
| 91 | #define DSI_DSIPHY_CFG2 DSI_REG(0x200 + 0x0008) |
| 92 | #define DSI_DSIPHY_CFG5 DSI_REG(0x200 + 0x0014) |
| 93 | |
| 94 | /* DSI_PLL_CTRL_SCP */ |
| 95 | |
| 96 | #define DSI_PLL_CONTROL DSI_REG(0x300 + 0x0000) |
| 97 | #define DSI_PLL_STATUS DSI_REG(0x300 + 0x0004) |
| 98 | #define DSI_PLL_GO DSI_REG(0x300 + 0x0008) |
| 99 | #define DSI_PLL_CONFIGURATION1 DSI_REG(0x300 + 0x000C) |
| 100 | #define DSI_PLL_CONFIGURATION2 DSI_REG(0x300 + 0x0010) |
| 101 | |
| 102 | #define REG_GET(idx, start, end) \ |
| 103 | FLD_GET(dsi_read_reg(idx), start, end) |
| 104 | |
| 105 | #define REG_FLD_MOD(idx, val, start, end) \ |
| 106 | dsi_write_reg(idx, FLD_MOD(dsi_read_reg(idx), val, start, end)) |
| 107 | |
| 108 | /* Global interrupts */ |
| 109 | #define DSI_IRQ_VC0 (1 << 0) |
| 110 | #define DSI_IRQ_VC1 (1 << 1) |
| 111 | #define DSI_IRQ_VC2 (1 << 2) |
| 112 | #define DSI_IRQ_VC3 (1 << 3) |
| 113 | #define DSI_IRQ_WAKEUP (1 << 4) |
| 114 | #define DSI_IRQ_RESYNC (1 << 5) |
| 115 | #define DSI_IRQ_PLL_LOCK (1 << 7) |
| 116 | #define DSI_IRQ_PLL_UNLOCK (1 << 8) |
| 117 | #define DSI_IRQ_PLL_RECALL (1 << 9) |
| 118 | #define DSI_IRQ_COMPLEXIO_ERR (1 << 10) |
| 119 | #define DSI_IRQ_HS_TX_TIMEOUT (1 << 14) |
| 120 | #define DSI_IRQ_LP_RX_TIMEOUT (1 << 15) |
| 121 | #define DSI_IRQ_TE_TRIGGER (1 << 16) |
| 122 | #define DSI_IRQ_ACK_TRIGGER (1 << 17) |
| 123 | #define DSI_IRQ_SYNC_LOST (1 << 18) |
| 124 | #define DSI_IRQ_LDO_POWER_GOOD (1 << 19) |
| 125 | #define DSI_IRQ_TA_TIMEOUT (1 << 20) |
| 126 | #define DSI_IRQ_ERROR_MASK \ |
| 127 | (DSI_IRQ_HS_TX_TIMEOUT | DSI_IRQ_LP_RX_TIMEOUT | DSI_IRQ_SYNC_LOST | \ |
| 128 | DSI_IRQ_TA_TIMEOUT) |
| 129 | #define DSI_IRQ_CHANNEL_MASK 0xf |
| 130 | |
| 131 | /* Virtual channel interrupts */ |
| 132 | #define DSI_VC_IRQ_CS (1 << 0) |
| 133 | #define DSI_VC_IRQ_ECC_CORR (1 << 1) |
| 134 | #define DSI_VC_IRQ_PACKET_SENT (1 << 2) |
| 135 | #define DSI_VC_IRQ_FIFO_TX_OVF (1 << 3) |
| 136 | #define DSI_VC_IRQ_FIFO_RX_OVF (1 << 4) |
| 137 | #define DSI_VC_IRQ_BTA (1 << 5) |
| 138 | #define DSI_VC_IRQ_ECC_NO_CORR (1 << 6) |
| 139 | #define DSI_VC_IRQ_FIFO_TX_UDF (1 << 7) |
| 140 | #define DSI_VC_IRQ_PP_BUSY_CHANGE (1 << 8) |
| 141 | #define DSI_VC_IRQ_ERROR_MASK \ |
| 142 | (DSI_VC_IRQ_CS | DSI_VC_IRQ_ECC_CORR | DSI_VC_IRQ_FIFO_TX_OVF | \ |
| 143 | DSI_VC_IRQ_FIFO_RX_OVF | DSI_VC_IRQ_ECC_NO_CORR | \ |
| 144 | DSI_VC_IRQ_FIFO_TX_UDF) |
| 145 | |
| 146 | /* ComplexIO interrupts */ |
| 147 | #define DSI_CIO_IRQ_ERRSYNCESC1 (1 << 0) |
| 148 | #define DSI_CIO_IRQ_ERRSYNCESC2 (1 << 1) |
| 149 | #define DSI_CIO_IRQ_ERRSYNCESC3 (1 << 2) |
| 150 | #define DSI_CIO_IRQ_ERRESC1 (1 << 5) |
| 151 | #define DSI_CIO_IRQ_ERRESC2 (1 << 6) |
| 152 | #define DSI_CIO_IRQ_ERRESC3 (1 << 7) |
| 153 | #define DSI_CIO_IRQ_ERRCONTROL1 (1 << 10) |
| 154 | #define DSI_CIO_IRQ_ERRCONTROL2 (1 << 11) |
| 155 | #define DSI_CIO_IRQ_ERRCONTROL3 (1 << 12) |
| 156 | #define DSI_CIO_IRQ_STATEULPS1 (1 << 15) |
| 157 | #define DSI_CIO_IRQ_STATEULPS2 (1 << 16) |
| 158 | #define DSI_CIO_IRQ_STATEULPS3 (1 << 17) |
| 159 | #define DSI_CIO_IRQ_ERRCONTENTIONLP0_1 (1 << 20) |
| 160 | #define DSI_CIO_IRQ_ERRCONTENTIONLP1_1 (1 << 21) |
| 161 | #define DSI_CIO_IRQ_ERRCONTENTIONLP0_2 (1 << 22) |
| 162 | #define DSI_CIO_IRQ_ERRCONTENTIONLP1_2 (1 << 23) |
| 163 | #define DSI_CIO_IRQ_ERRCONTENTIONLP0_3 (1 << 24) |
| 164 | #define DSI_CIO_IRQ_ERRCONTENTIONLP1_3 (1 << 25) |
| 165 | #define DSI_CIO_IRQ_ULPSACTIVENOT_ALL0 (1 << 30) |
| 166 | #define DSI_CIO_IRQ_ULPSACTIVENOT_ALL1 (1 << 31) |
Tomi Valkeinen | bbecb50 | 2010-05-10 14:35:33 +0300 | [diff] [blame] | 167 | #define DSI_CIO_IRQ_ERROR_MASK \ |
| 168 | (DSI_CIO_IRQ_ERRSYNCESC1 | DSI_CIO_IRQ_ERRSYNCESC2 | \ |
| 169 | DSI_CIO_IRQ_ERRSYNCESC3 | DSI_CIO_IRQ_ERRESC1 | DSI_CIO_IRQ_ERRESC2 | \ |
| 170 | DSI_CIO_IRQ_ERRESC3 | DSI_CIO_IRQ_ERRCONTROL1 | \ |
| 171 | DSI_CIO_IRQ_ERRCONTROL2 | DSI_CIO_IRQ_ERRCONTROL3 | \ |
| 172 | DSI_CIO_IRQ_ERRCONTENTIONLP0_1 | DSI_CIO_IRQ_ERRCONTENTIONLP1_1 | \ |
| 173 | DSI_CIO_IRQ_ERRCONTENTIONLP0_2 | DSI_CIO_IRQ_ERRCONTENTIONLP1_2 | \ |
| 174 | DSI_CIO_IRQ_ERRCONTENTIONLP0_3 | DSI_CIO_IRQ_ERRCONTENTIONLP1_3) |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 175 | |
| 176 | #define DSI_DT_DCS_SHORT_WRITE_0 0x05 |
| 177 | #define DSI_DT_DCS_SHORT_WRITE_1 0x15 |
| 178 | #define DSI_DT_DCS_READ 0x06 |
| 179 | #define DSI_DT_SET_MAX_RET_PKG_SIZE 0x37 |
| 180 | #define DSI_DT_NULL_PACKET 0x09 |
| 181 | #define DSI_DT_DCS_LONG_WRITE 0x39 |
| 182 | |
| 183 | #define DSI_DT_RX_ACK_WITH_ERR 0x02 |
| 184 | #define DSI_DT_RX_DCS_LONG_READ 0x1c |
| 185 | #define DSI_DT_RX_SHORT_READ_1 0x21 |
| 186 | #define DSI_DT_RX_SHORT_READ_2 0x22 |
| 187 | |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 188 | enum fifo_size { |
| 189 | DSI_FIFO_SIZE_0 = 0, |
| 190 | DSI_FIFO_SIZE_32 = 1, |
| 191 | DSI_FIFO_SIZE_64 = 2, |
| 192 | DSI_FIFO_SIZE_96 = 3, |
| 193 | DSI_FIFO_SIZE_128 = 4, |
| 194 | }; |
| 195 | |
| 196 | enum dsi_vc_mode { |
| 197 | DSI_VC_MODE_L4 = 0, |
| 198 | DSI_VC_MODE_VP, |
| 199 | }; |
| 200 | |
| 201 | struct dsi_update_region { |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 202 | u16 x, y, w, h; |
| 203 | struct omap_dss_device *device; |
| 204 | }; |
| 205 | |
Tomi Valkeinen | dfc0fd8 | 2009-12-17 14:35:21 +0200 | [diff] [blame] | 206 | struct dsi_irq_stats { |
| 207 | unsigned long last_reset; |
| 208 | unsigned irq_count; |
| 209 | unsigned dsi_irqs[32]; |
| 210 | unsigned vc_irqs[4][32]; |
| 211 | unsigned cio_irqs[32]; |
| 212 | }; |
| 213 | |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 214 | static struct |
| 215 | { |
Senthilvadivu Guruswamy | c8aac01 | 2011-01-24 06:22:02 +0000 | [diff] [blame] | 216 | struct platform_device *pdev; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 217 | void __iomem *base; |
archit taneja | affe360 | 2011-02-23 08:41:03 +0000 | [diff] [blame] | 218 | int irq; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 219 | |
| 220 | struct dsi_clock_info current_cinfo; |
| 221 | |
| 222 | struct regulator *vdds_dsi_reg; |
| 223 | |
| 224 | struct { |
| 225 | enum dsi_vc_mode mode; |
| 226 | struct omap_dss_device *dssdev; |
| 227 | enum fifo_size fifo_size; |
Archit Taneja | 5ee3c14 | 2011-03-02 12:35:53 +0530 | [diff] [blame] | 228 | int vc_id; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 229 | } vc[4]; |
| 230 | |
| 231 | struct mutex lock; |
Tomi Valkeinen | b9eb5d7 | 2010-01-11 16:33:56 +0200 | [diff] [blame] | 232 | struct semaphore bus_lock; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 233 | |
| 234 | unsigned pll_locked; |
| 235 | |
| 236 | struct completion bta_completion; |
Tomi Valkeinen | ab83b14 | 2010-06-09 15:31:01 +0300 | [diff] [blame] | 237 | void (*bta_callback)(void); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 238 | |
Tomi Valkeinen | 18946f6 | 2010-01-12 14:16:41 +0200 | [diff] [blame] | 239 | int update_channel; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 240 | struct dsi_update_region update_region; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 241 | |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 242 | bool te_enabled; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 243 | |
Tomi Valkeinen | 0f16aa0 | 2010-04-12 09:57:19 +0300 | [diff] [blame] | 244 | struct workqueue_struct *workqueue; |
| 245 | |
Tomi Valkeinen | 18946f6 | 2010-01-12 14:16:41 +0200 | [diff] [blame] | 246 | void (*framedone_callback)(int, void *); |
| 247 | void *framedone_data; |
| 248 | |
| 249 | struct delayed_work framedone_timeout_work; |
| 250 | |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 251 | #ifdef DSI_CATCH_MISSING_TE |
| 252 | struct timer_list te_timer; |
| 253 | #endif |
| 254 | |
| 255 | unsigned long cache_req_pck; |
| 256 | unsigned long cache_clk_freq; |
| 257 | struct dsi_clock_info cache_cinfo; |
| 258 | |
| 259 | u32 errors; |
| 260 | spinlock_t errors_lock; |
| 261 | #ifdef DEBUG |
| 262 | ktime_t perf_setup_time; |
| 263 | ktime_t perf_start_time; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 264 | #endif |
| 265 | int debug_read; |
| 266 | int debug_write; |
Tomi Valkeinen | dfc0fd8 | 2009-12-17 14:35:21 +0200 | [diff] [blame] | 267 | |
| 268 | #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS |
| 269 | spinlock_t irq_stats_lock; |
| 270 | struct dsi_irq_stats irq_stats; |
| 271 | #endif |
Taneja, Archit | 4964111 | 2011-03-14 23:28:23 -0500 | [diff] [blame^] | 272 | /* DSI PLL Parameter Ranges */ |
| 273 | unsigned long regm_max, regn_max; |
| 274 | unsigned long regm_dispc_max, regm_dsi_max; |
| 275 | unsigned long fint_min, fint_max; |
| 276 | unsigned long lpdiv_max; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 277 | } dsi; |
| 278 | |
| 279 | #ifdef DEBUG |
| 280 | static unsigned int dsi_perf; |
| 281 | module_param_named(dsi_perf, dsi_perf, bool, 0644); |
| 282 | #endif |
| 283 | |
| 284 | static inline void dsi_write_reg(const struct dsi_reg idx, u32 val) |
| 285 | { |
| 286 | __raw_writel(val, dsi.base + idx.idx); |
| 287 | } |
| 288 | |
| 289 | static inline u32 dsi_read_reg(const struct dsi_reg idx) |
| 290 | { |
| 291 | return __raw_readl(dsi.base + idx.idx); |
| 292 | } |
| 293 | |
| 294 | |
| 295 | void dsi_save_context(void) |
| 296 | { |
| 297 | } |
| 298 | |
| 299 | void dsi_restore_context(void) |
| 300 | { |
| 301 | } |
| 302 | |
| 303 | void dsi_bus_lock(void) |
| 304 | { |
Tomi Valkeinen | b9eb5d7 | 2010-01-11 16:33:56 +0200 | [diff] [blame] | 305 | down(&dsi.bus_lock); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 306 | } |
| 307 | EXPORT_SYMBOL(dsi_bus_lock); |
| 308 | |
| 309 | void dsi_bus_unlock(void) |
| 310 | { |
Tomi Valkeinen | b9eb5d7 | 2010-01-11 16:33:56 +0200 | [diff] [blame] | 311 | up(&dsi.bus_lock); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 312 | } |
| 313 | EXPORT_SYMBOL(dsi_bus_unlock); |
| 314 | |
Tomi Valkeinen | 4f76502 | 2010-01-18 16:27:52 +0200 | [diff] [blame] | 315 | static bool dsi_bus_is_locked(void) |
| 316 | { |
Tomi Valkeinen | b9eb5d7 | 2010-01-11 16:33:56 +0200 | [diff] [blame] | 317 | return dsi.bus_lock.count == 0; |
Tomi Valkeinen | 4f76502 | 2010-01-18 16:27:52 +0200 | [diff] [blame] | 318 | } |
| 319 | |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 320 | static inline int wait_for_bit_change(const struct dsi_reg idx, int bitnum, |
| 321 | int value) |
| 322 | { |
| 323 | int t = 100000; |
| 324 | |
| 325 | while (REG_GET(idx, bitnum, bitnum) != value) { |
| 326 | if (--t == 0) |
| 327 | return !value; |
| 328 | } |
| 329 | |
| 330 | return value; |
| 331 | } |
| 332 | |
| 333 | #ifdef DEBUG |
| 334 | static void dsi_perf_mark_setup(void) |
| 335 | { |
| 336 | dsi.perf_setup_time = ktime_get(); |
| 337 | } |
| 338 | |
| 339 | static void dsi_perf_mark_start(void) |
| 340 | { |
| 341 | dsi.perf_start_time = ktime_get(); |
| 342 | } |
| 343 | |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 344 | static void dsi_perf_show(const char *name) |
| 345 | { |
| 346 | ktime_t t, setup_time, trans_time; |
| 347 | u32 total_bytes; |
| 348 | u32 setup_us, trans_us, total_us; |
| 349 | |
| 350 | if (!dsi_perf) |
| 351 | return; |
| 352 | |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 353 | t = ktime_get(); |
| 354 | |
| 355 | setup_time = ktime_sub(dsi.perf_start_time, dsi.perf_setup_time); |
| 356 | setup_us = (u32)ktime_to_us(setup_time); |
| 357 | if (setup_us == 0) |
| 358 | setup_us = 1; |
| 359 | |
| 360 | trans_time = ktime_sub(t, dsi.perf_start_time); |
| 361 | trans_us = (u32)ktime_to_us(trans_time); |
| 362 | if (trans_us == 0) |
| 363 | trans_us = 1; |
| 364 | |
| 365 | total_us = setup_us + trans_us; |
| 366 | |
Tomi Valkeinen | 18946f6 | 2010-01-12 14:16:41 +0200 | [diff] [blame] | 367 | total_bytes = dsi.update_region.w * |
| 368 | dsi.update_region.h * |
| 369 | dsi.update_region.device->ctrl.pixel_size / 8; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 370 | |
Tomi Valkeinen | 1bbb275 | 2010-01-11 16:41:10 +0200 | [diff] [blame] | 371 | printk(KERN_INFO "DSI(%s): %u us + %u us = %u us (%uHz), " |
| 372 | "%u bytes, %u kbytes/sec\n", |
| 373 | name, |
| 374 | setup_us, |
| 375 | trans_us, |
| 376 | total_us, |
| 377 | 1000*1000 / total_us, |
| 378 | total_bytes, |
| 379 | total_bytes * 1000 / total_us); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 380 | } |
| 381 | #else |
| 382 | #define dsi_perf_mark_setup() |
| 383 | #define dsi_perf_mark_start() |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 384 | #define dsi_perf_show(x) |
| 385 | #endif |
| 386 | |
| 387 | static void print_irq_status(u32 status) |
| 388 | { |
| 389 | #ifndef VERBOSE_IRQ |
| 390 | if ((status & ~DSI_IRQ_CHANNEL_MASK) == 0) |
| 391 | return; |
| 392 | #endif |
| 393 | printk(KERN_DEBUG "DSI IRQ: 0x%x: ", status); |
| 394 | |
| 395 | #define PIS(x) \ |
| 396 | if (status & DSI_IRQ_##x) \ |
| 397 | printk(#x " "); |
| 398 | #ifdef VERBOSE_IRQ |
| 399 | PIS(VC0); |
| 400 | PIS(VC1); |
| 401 | PIS(VC2); |
| 402 | PIS(VC3); |
| 403 | #endif |
| 404 | PIS(WAKEUP); |
| 405 | PIS(RESYNC); |
| 406 | PIS(PLL_LOCK); |
| 407 | PIS(PLL_UNLOCK); |
| 408 | PIS(PLL_RECALL); |
| 409 | PIS(COMPLEXIO_ERR); |
| 410 | PIS(HS_TX_TIMEOUT); |
| 411 | PIS(LP_RX_TIMEOUT); |
| 412 | PIS(TE_TRIGGER); |
| 413 | PIS(ACK_TRIGGER); |
| 414 | PIS(SYNC_LOST); |
| 415 | PIS(LDO_POWER_GOOD); |
| 416 | PIS(TA_TIMEOUT); |
| 417 | #undef PIS |
| 418 | |
| 419 | printk("\n"); |
| 420 | } |
| 421 | |
| 422 | static void print_irq_status_vc(int channel, u32 status) |
| 423 | { |
| 424 | #ifndef VERBOSE_IRQ |
| 425 | if ((status & ~DSI_VC_IRQ_PACKET_SENT) == 0) |
| 426 | return; |
| 427 | #endif |
| 428 | printk(KERN_DEBUG "DSI VC(%d) IRQ 0x%x: ", channel, status); |
| 429 | |
| 430 | #define PIS(x) \ |
| 431 | if (status & DSI_VC_IRQ_##x) \ |
| 432 | printk(#x " "); |
| 433 | PIS(CS); |
| 434 | PIS(ECC_CORR); |
| 435 | #ifdef VERBOSE_IRQ |
| 436 | PIS(PACKET_SENT); |
| 437 | #endif |
| 438 | PIS(FIFO_TX_OVF); |
| 439 | PIS(FIFO_RX_OVF); |
| 440 | PIS(BTA); |
| 441 | PIS(ECC_NO_CORR); |
| 442 | PIS(FIFO_TX_UDF); |
| 443 | PIS(PP_BUSY_CHANGE); |
| 444 | #undef PIS |
| 445 | printk("\n"); |
| 446 | } |
| 447 | |
| 448 | static void print_irq_status_cio(u32 status) |
| 449 | { |
| 450 | printk(KERN_DEBUG "DSI CIO IRQ 0x%x: ", status); |
| 451 | |
| 452 | #define PIS(x) \ |
| 453 | if (status & DSI_CIO_IRQ_##x) \ |
| 454 | printk(#x " "); |
| 455 | PIS(ERRSYNCESC1); |
| 456 | PIS(ERRSYNCESC2); |
| 457 | PIS(ERRSYNCESC3); |
| 458 | PIS(ERRESC1); |
| 459 | PIS(ERRESC2); |
| 460 | PIS(ERRESC3); |
| 461 | PIS(ERRCONTROL1); |
| 462 | PIS(ERRCONTROL2); |
| 463 | PIS(ERRCONTROL3); |
| 464 | PIS(STATEULPS1); |
| 465 | PIS(STATEULPS2); |
| 466 | PIS(STATEULPS3); |
| 467 | PIS(ERRCONTENTIONLP0_1); |
| 468 | PIS(ERRCONTENTIONLP1_1); |
| 469 | PIS(ERRCONTENTIONLP0_2); |
| 470 | PIS(ERRCONTENTIONLP1_2); |
| 471 | PIS(ERRCONTENTIONLP0_3); |
| 472 | PIS(ERRCONTENTIONLP1_3); |
| 473 | PIS(ULPSACTIVENOT_ALL0); |
| 474 | PIS(ULPSACTIVENOT_ALL1); |
| 475 | #undef PIS |
| 476 | |
| 477 | printk("\n"); |
| 478 | } |
| 479 | |
| 480 | static int debug_irq; |
| 481 | |
| 482 | /* called from dss */ |
archit taneja | affe360 | 2011-02-23 08:41:03 +0000 | [diff] [blame] | 483 | static irqreturn_t omap_dsi_irq_handler(int irq, void *arg) |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 484 | { |
| 485 | u32 irqstatus, vcstatus, ciostatus; |
| 486 | int i; |
| 487 | |
| 488 | irqstatus = dsi_read_reg(DSI_IRQSTATUS); |
| 489 | |
archit taneja | affe360 | 2011-02-23 08:41:03 +0000 | [diff] [blame] | 490 | /* IRQ is not for us */ |
| 491 | if (!irqstatus) |
| 492 | return IRQ_NONE; |
| 493 | |
Tomi Valkeinen | dfc0fd8 | 2009-12-17 14:35:21 +0200 | [diff] [blame] | 494 | #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS |
| 495 | spin_lock(&dsi.irq_stats_lock); |
| 496 | dsi.irq_stats.irq_count++; |
| 497 | dss_collect_irq_stats(irqstatus, dsi.irq_stats.dsi_irqs); |
| 498 | #endif |
| 499 | |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 500 | if (irqstatus & DSI_IRQ_ERROR_MASK) { |
| 501 | DSSERR("DSI error, irqstatus %x\n", irqstatus); |
| 502 | print_irq_status(irqstatus); |
| 503 | spin_lock(&dsi.errors_lock); |
| 504 | dsi.errors |= irqstatus & DSI_IRQ_ERROR_MASK; |
| 505 | spin_unlock(&dsi.errors_lock); |
| 506 | } else if (debug_irq) { |
| 507 | print_irq_status(irqstatus); |
| 508 | } |
| 509 | |
| 510 | #ifdef DSI_CATCH_MISSING_TE |
| 511 | if (irqstatus & DSI_IRQ_TE_TRIGGER) |
| 512 | del_timer(&dsi.te_timer); |
| 513 | #endif |
| 514 | |
| 515 | for (i = 0; i < 4; ++i) { |
| 516 | if ((irqstatus & (1<<i)) == 0) |
| 517 | continue; |
| 518 | |
| 519 | vcstatus = dsi_read_reg(DSI_VC_IRQSTATUS(i)); |
| 520 | |
Tomi Valkeinen | dfc0fd8 | 2009-12-17 14:35:21 +0200 | [diff] [blame] | 521 | #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS |
| 522 | dss_collect_irq_stats(vcstatus, dsi.irq_stats.vc_irqs[i]); |
| 523 | #endif |
| 524 | |
Tomi Valkeinen | ab83b14 | 2010-06-09 15:31:01 +0300 | [diff] [blame] | 525 | if (vcstatus & DSI_VC_IRQ_BTA) { |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 526 | complete(&dsi.bta_completion); |
| 527 | |
Tomi Valkeinen | ab83b14 | 2010-06-09 15:31:01 +0300 | [diff] [blame] | 528 | if (dsi.bta_callback) |
| 529 | dsi.bta_callback(); |
| 530 | } |
| 531 | |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 532 | if (vcstatus & DSI_VC_IRQ_ERROR_MASK) { |
| 533 | DSSERR("DSI VC(%d) error, vc irqstatus %x\n", |
| 534 | i, vcstatus); |
| 535 | print_irq_status_vc(i, vcstatus); |
| 536 | } else if (debug_irq) { |
| 537 | print_irq_status_vc(i, vcstatus); |
| 538 | } |
| 539 | |
| 540 | dsi_write_reg(DSI_VC_IRQSTATUS(i), vcstatus); |
| 541 | /* flush posted write */ |
| 542 | dsi_read_reg(DSI_VC_IRQSTATUS(i)); |
| 543 | } |
| 544 | |
| 545 | if (irqstatus & DSI_IRQ_COMPLEXIO_ERR) { |
| 546 | ciostatus = dsi_read_reg(DSI_COMPLEXIO_IRQ_STATUS); |
| 547 | |
Tomi Valkeinen | dfc0fd8 | 2009-12-17 14:35:21 +0200 | [diff] [blame] | 548 | #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS |
| 549 | dss_collect_irq_stats(ciostatus, dsi.irq_stats.cio_irqs); |
| 550 | #endif |
| 551 | |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 552 | dsi_write_reg(DSI_COMPLEXIO_IRQ_STATUS, ciostatus); |
| 553 | /* flush posted write */ |
| 554 | dsi_read_reg(DSI_COMPLEXIO_IRQ_STATUS); |
| 555 | |
Tomi Valkeinen | bbecb50 | 2010-05-10 14:35:33 +0300 | [diff] [blame] | 556 | if (ciostatus & DSI_CIO_IRQ_ERROR_MASK) { |
| 557 | DSSERR("DSI CIO error, cio irqstatus %x\n", ciostatus); |
| 558 | print_irq_status_cio(ciostatus); |
| 559 | } else if (debug_irq) { |
| 560 | print_irq_status_cio(ciostatus); |
| 561 | } |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 562 | } |
| 563 | |
| 564 | dsi_write_reg(DSI_IRQSTATUS, irqstatus & ~DSI_IRQ_CHANNEL_MASK); |
| 565 | /* flush posted write */ |
| 566 | dsi_read_reg(DSI_IRQSTATUS); |
Tomi Valkeinen | dfc0fd8 | 2009-12-17 14:35:21 +0200 | [diff] [blame] | 567 | |
| 568 | #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS |
| 569 | spin_unlock(&dsi.irq_stats_lock); |
| 570 | #endif |
archit taneja | affe360 | 2011-02-23 08:41:03 +0000 | [diff] [blame] | 571 | return IRQ_HANDLED; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 572 | } |
| 573 | |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 574 | static void _dsi_initialize_irq(void) |
| 575 | { |
| 576 | u32 l; |
| 577 | int i; |
| 578 | |
| 579 | /* disable all interrupts */ |
| 580 | dsi_write_reg(DSI_IRQENABLE, 0); |
| 581 | for (i = 0; i < 4; ++i) |
| 582 | dsi_write_reg(DSI_VC_IRQENABLE(i), 0); |
| 583 | dsi_write_reg(DSI_COMPLEXIO_IRQ_ENABLE, 0); |
| 584 | |
| 585 | /* clear interrupt status */ |
| 586 | l = dsi_read_reg(DSI_IRQSTATUS); |
| 587 | dsi_write_reg(DSI_IRQSTATUS, l & ~DSI_IRQ_CHANNEL_MASK); |
| 588 | |
| 589 | for (i = 0; i < 4; ++i) { |
| 590 | l = dsi_read_reg(DSI_VC_IRQSTATUS(i)); |
| 591 | dsi_write_reg(DSI_VC_IRQSTATUS(i), l); |
| 592 | } |
| 593 | |
| 594 | l = dsi_read_reg(DSI_COMPLEXIO_IRQ_STATUS); |
| 595 | dsi_write_reg(DSI_COMPLEXIO_IRQ_STATUS, l); |
| 596 | |
| 597 | /* enable error irqs */ |
| 598 | l = DSI_IRQ_ERROR_MASK; |
| 599 | #ifdef DSI_CATCH_MISSING_TE |
| 600 | l |= DSI_IRQ_TE_TRIGGER; |
| 601 | #endif |
| 602 | dsi_write_reg(DSI_IRQENABLE, l); |
| 603 | |
| 604 | l = DSI_VC_IRQ_ERROR_MASK; |
| 605 | for (i = 0; i < 4; ++i) |
| 606 | dsi_write_reg(DSI_VC_IRQENABLE(i), l); |
| 607 | |
Tomi Valkeinen | bbecb50 | 2010-05-10 14:35:33 +0300 | [diff] [blame] | 608 | l = DSI_CIO_IRQ_ERROR_MASK; |
| 609 | dsi_write_reg(DSI_COMPLEXIO_IRQ_ENABLE, l); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 610 | } |
| 611 | |
| 612 | static u32 dsi_get_errors(void) |
| 613 | { |
| 614 | unsigned long flags; |
| 615 | u32 e; |
| 616 | spin_lock_irqsave(&dsi.errors_lock, flags); |
| 617 | e = dsi.errors; |
| 618 | dsi.errors = 0; |
| 619 | spin_unlock_irqrestore(&dsi.errors_lock, flags); |
| 620 | return e; |
| 621 | } |
| 622 | |
| 623 | static void dsi_vc_enable_bta_irq(int channel) |
| 624 | { |
| 625 | u32 l; |
| 626 | |
| 627 | dsi_write_reg(DSI_VC_IRQSTATUS(channel), DSI_VC_IRQ_BTA); |
| 628 | |
| 629 | l = dsi_read_reg(DSI_VC_IRQENABLE(channel)); |
| 630 | l |= DSI_VC_IRQ_BTA; |
| 631 | dsi_write_reg(DSI_VC_IRQENABLE(channel), l); |
| 632 | } |
| 633 | |
| 634 | static void dsi_vc_disable_bta_irq(int channel) |
| 635 | { |
| 636 | u32 l; |
| 637 | |
| 638 | l = dsi_read_reg(DSI_VC_IRQENABLE(channel)); |
| 639 | l &= ~DSI_VC_IRQ_BTA; |
| 640 | dsi_write_reg(DSI_VC_IRQENABLE(channel), l); |
| 641 | } |
| 642 | |
Archit Taneja | 1bb4783 | 2011-02-24 14:17:30 +0530 | [diff] [blame] | 643 | /* DSI func clock. this could also be dsi_pll_hsdiv_dsi_clk */ |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 644 | static inline void enable_clocks(bool enable) |
| 645 | { |
| 646 | if (enable) |
Archit Taneja | 6af9cd1 | 2011-01-31 16:27:44 +0000 | [diff] [blame] | 647 | dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 648 | else |
Archit Taneja | 6af9cd1 | 2011-01-31 16:27:44 +0000 | [diff] [blame] | 649 | dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 650 | } |
| 651 | |
| 652 | /* source clock for DSI PLL. this could also be PCLKFREE */ |
| 653 | static inline void dsi_enable_pll_clock(bool enable) |
| 654 | { |
| 655 | if (enable) |
Archit Taneja | 6af9cd1 | 2011-01-31 16:27:44 +0000 | [diff] [blame] | 656 | dss_clk_enable(DSS_CLK_SYSCK); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 657 | else |
Archit Taneja | 6af9cd1 | 2011-01-31 16:27:44 +0000 | [diff] [blame] | 658 | dss_clk_disable(DSS_CLK_SYSCK); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 659 | |
| 660 | if (enable && dsi.pll_locked) { |
| 661 | if (wait_for_bit_change(DSI_PLL_STATUS, 1, 1) != 1) |
| 662 | DSSERR("cannot lock PLL when enabling clocks\n"); |
| 663 | } |
| 664 | } |
| 665 | |
| 666 | #ifdef DEBUG |
| 667 | static void _dsi_print_reset_status(void) |
| 668 | { |
| 669 | u32 l; |
| 670 | |
| 671 | if (!dss_debug) |
| 672 | return; |
| 673 | |
| 674 | /* A dummy read using the SCP interface to any DSIPHY register is |
| 675 | * required after DSIPHY reset to complete the reset of the DSI complex |
| 676 | * I/O. */ |
| 677 | l = dsi_read_reg(DSI_DSIPHY_CFG5); |
| 678 | |
| 679 | printk(KERN_DEBUG "DSI resets: "); |
| 680 | |
| 681 | l = dsi_read_reg(DSI_PLL_STATUS); |
| 682 | printk("PLL (%d) ", FLD_GET(l, 0, 0)); |
| 683 | |
| 684 | l = dsi_read_reg(DSI_COMPLEXIO_CFG1); |
| 685 | printk("CIO (%d) ", FLD_GET(l, 29, 29)); |
| 686 | |
| 687 | l = dsi_read_reg(DSI_DSIPHY_CFG5); |
| 688 | printk("PHY (%x, %d, %d, %d)\n", |
| 689 | FLD_GET(l, 28, 26), |
| 690 | FLD_GET(l, 29, 29), |
| 691 | FLD_GET(l, 30, 30), |
| 692 | FLD_GET(l, 31, 31)); |
| 693 | } |
| 694 | #else |
| 695 | #define _dsi_print_reset_status() |
| 696 | #endif |
| 697 | |
| 698 | static inline int dsi_if_enable(bool enable) |
| 699 | { |
| 700 | DSSDBG("dsi_if_enable(%d)\n", enable); |
| 701 | |
| 702 | enable = enable ? 1 : 0; |
| 703 | REG_FLD_MOD(DSI_CTRL, enable, 0, 0); /* IF_EN */ |
| 704 | |
| 705 | if (wait_for_bit_change(DSI_CTRL, 0, enable) != enable) { |
| 706 | DSSERR("Failed to set dsi_if_enable to %d\n", enable); |
| 707 | return -EIO; |
| 708 | } |
| 709 | |
| 710 | return 0; |
| 711 | } |
| 712 | |
Archit Taneja | 1bb4783 | 2011-02-24 14:17:30 +0530 | [diff] [blame] | 713 | unsigned long dsi_get_pll_hsdiv_dispc_rate(void) |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 714 | { |
Archit Taneja | 1bb4783 | 2011-02-24 14:17:30 +0530 | [diff] [blame] | 715 | return dsi.current_cinfo.dsi_pll_hsdiv_dispc_clk; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 716 | } |
| 717 | |
Archit Taneja | 1bb4783 | 2011-02-24 14:17:30 +0530 | [diff] [blame] | 718 | static unsigned long dsi_get_pll_hsdiv_dsi_rate(void) |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 719 | { |
Archit Taneja | 1bb4783 | 2011-02-24 14:17:30 +0530 | [diff] [blame] | 720 | return dsi.current_cinfo.dsi_pll_hsdiv_dsi_clk; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 721 | } |
| 722 | |
| 723 | static unsigned long dsi_get_txbyteclkhs(void) |
| 724 | { |
| 725 | return dsi.current_cinfo.clkin4ddr / 16; |
| 726 | } |
| 727 | |
| 728 | static unsigned long dsi_fclk_rate(void) |
| 729 | { |
| 730 | unsigned long r; |
| 731 | |
Archit Taneja | 88134fa | 2011-01-06 10:44:10 +0530 | [diff] [blame] | 732 | if (dss_get_dsi_clk_source() == DSS_CLK_SRC_FCK) { |
Archit Taneja | 1bb4783 | 2011-02-24 14:17:30 +0530 | [diff] [blame] | 733 | /* DSI FCLK source is DSS_CLK_FCK */ |
Archit Taneja | 6af9cd1 | 2011-01-31 16:27:44 +0000 | [diff] [blame] | 734 | r = dss_clk_get_rate(DSS_CLK_FCK); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 735 | } else { |
Archit Taneja | 1bb4783 | 2011-02-24 14:17:30 +0530 | [diff] [blame] | 736 | /* DSI FCLK source is dsi_pll_hsdiv_dsi_clk */ |
| 737 | r = dsi_get_pll_hsdiv_dsi_rate(); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 738 | } |
| 739 | |
| 740 | return r; |
| 741 | } |
| 742 | |
| 743 | static int dsi_set_lp_clk_divisor(struct omap_dss_device *dssdev) |
| 744 | { |
| 745 | unsigned long dsi_fclk; |
| 746 | unsigned lp_clk_div; |
| 747 | unsigned long lp_clk; |
| 748 | |
| 749 | lp_clk_div = dssdev->phy.dsi.div.lp_clk_div; |
| 750 | |
Taneja, Archit | 4964111 | 2011-03-14 23:28:23 -0500 | [diff] [blame^] | 751 | if (lp_clk_div == 0 || lp_clk_div > dsi.lpdiv_max) |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 752 | return -EINVAL; |
| 753 | |
| 754 | dsi_fclk = dsi_fclk_rate(); |
| 755 | |
| 756 | lp_clk = dsi_fclk / 2 / lp_clk_div; |
| 757 | |
| 758 | DSSDBG("LP_CLK_DIV %u, LP_CLK %lu\n", lp_clk_div, lp_clk); |
| 759 | dsi.current_cinfo.lp_clk = lp_clk; |
| 760 | dsi.current_cinfo.lp_clk_div = lp_clk_div; |
| 761 | |
| 762 | REG_FLD_MOD(DSI_CLK_CTRL, lp_clk_div, 12, 0); /* LP_CLK_DIVISOR */ |
| 763 | |
| 764 | REG_FLD_MOD(DSI_CLK_CTRL, dsi_fclk > 30000000 ? 1 : 0, |
| 765 | 21, 21); /* LP_RX_SYNCHRO_ENABLE */ |
| 766 | |
| 767 | return 0; |
| 768 | } |
| 769 | |
| 770 | |
| 771 | enum dsi_pll_power_state { |
| 772 | DSI_PLL_POWER_OFF = 0x0, |
| 773 | DSI_PLL_POWER_ON_HSCLK = 0x1, |
| 774 | DSI_PLL_POWER_ON_ALL = 0x2, |
| 775 | DSI_PLL_POWER_ON_DIV = 0x3, |
| 776 | }; |
| 777 | |
| 778 | static int dsi_pll_power(enum dsi_pll_power_state state) |
| 779 | { |
| 780 | int t = 0; |
| 781 | |
| 782 | REG_FLD_MOD(DSI_CLK_CTRL, state, 31, 30); /* PLL_PWR_CMD */ |
| 783 | |
| 784 | /* PLL_PWR_STATUS */ |
| 785 | while (FLD_GET(dsi_read_reg(DSI_CLK_CTRL), 29, 28) != state) { |
Tomi Valkeinen | 24be78b | 2010-01-07 14:19:48 +0200 | [diff] [blame] | 786 | if (++t > 1000) { |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 787 | DSSERR("Failed to set DSI PLL power mode to %d\n", |
| 788 | state); |
| 789 | return -ENODEV; |
| 790 | } |
Tomi Valkeinen | 24be78b | 2010-01-07 14:19:48 +0200 | [diff] [blame] | 791 | udelay(1); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 792 | } |
| 793 | |
| 794 | return 0; |
| 795 | } |
| 796 | |
| 797 | /* calculate clock rates using dividers in cinfo */ |
Sumit Semwal | ff1b2cd | 2010-12-02 11:27:11 +0000 | [diff] [blame] | 798 | static int dsi_calc_clock_rates(struct omap_dss_device *dssdev, |
| 799 | struct dsi_clock_info *cinfo) |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 800 | { |
Taneja, Archit | 4964111 | 2011-03-14 23:28:23 -0500 | [diff] [blame^] | 801 | if (cinfo->regn == 0 || cinfo->regn > dsi.regn_max) |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 802 | return -EINVAL; |
| 803 | |
Taneja, Archit | 4964111 | 2011-03-14 23:28:23 -0500 | [diff] [blame^] | 804 | if (cinfo->regm == 0 || cinfo->regm > dsi.regm_max) |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 805 | return -EINVAL; |
| 806 | |
Taneja, Archit | 4964111 | 2011-03-14 23:28:23 -0500 | [diff] [blame^] | 807 | if (cinfo->regm_dispc > dsi.regm_dispc_max) |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 808 | return -EINVAL; |
| 809 | |
Taneja, Archit | 4964111 | 2011-03-14 23:28:23 -0500 | [diff] [blame^] | 810 | if (cinfo->regm_dsi > dsi.regm_dsi_max) |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 811 | return -EINVAL; |
| 812 | |
Archit Taneja | 1bb4783 | 2011-02-24 14:17:30 +0530 | [diff] [blame] | 813 | if (cinfo->use_sys_clk) { |
Archit Taneja | 6af9cd1 | 2011-01-31 16:27:44 +0000 | [diff] [blame] | 814 | cinfo->clkin = dss_clk_get_rate(DSS_CLK_SYSCK); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 815 | /* XXX it is unclear if highfreq should be used |
Archit Taneja | 1bb4783 | 2011-02-24 14:17:30 +0530 | [diff] [blame] | 816 | * with DSS_SYS_CLK source also */ |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 817 | cinfo->highfreq = 0; |
| 818 | } else { |
Sumit Semwal | ff1b2cd | 2010-12-02 11:27:11 +0000 | [diff] [blame] | 819 | cinfo->clkin = dispc_pclk_rate(dssdev->manager->id); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 820 | |
| 821 | if (cinfo->clkin < 32000000) |
| 822 | cinfo->highfreq = 0; |
| 823 | else |
| 824 | cinfo->highfreq = 1; |
| 825 | } |
| 826 | |
| 827 | cinfo->fint = cinfo->clkin / (cinfo->regn * (cinfo->highfreq ? 2 : 1)); |
| 828 | |
Taneja, Archit | 4964111 | 2011-03-14 23:28:23 -0500 | [diff] [blame^] | 829 | if (cinfo->fint > dsi.fint_max || cinfo->fint < dsi.fint_min) |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 830 | return -EINVAL; |
| 831 | |
| 832 | cinfo->clkin4ddr = 2 * cinfo->regm * cinfo->fint; |
| 833 | |
| 834 | if (cinfo->clkin4ddr > 1800 * 1000 * 1000) |
| 835 | return -EINVAL; |
| 836 | |
Archit Taneja | 1bb4783 | 2011-02-24 14:17:30 +0530 | [diff] [blame] | 837 | if (cinfo->regm_dispc > 0) |
| 838 | cinfo->dsi_pll_hsdiv_dispc_clk = |
| 839 | cinfo->clkin4ddr / cinfo->regm_dispc; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 840 | else |
Archit Taneja | 1bb4783 | 2011-02-24 14:17:30 +0530 | [diff] [blame] | 841 | cinfo->dsi_pll_hsdiv_dispc_clk = 0; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 842 | |
Archit Taneja | 1bb4783 | 2011-02-24 14:17:30 +0530 | [diff] [blame] | 843 | if (cinfo->regm_dsi > 0) |
| 844 | cinfo->dsi_pll_hsdiv_dsi_clk = |
| 845 | cinfo->clkin4ddr / cinfo->regm_dsi; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 846 | else |
Archit Taneja | 1bb4783 | 2011-02-24 14:17:30 +0530 | [diff] [blame] | 847 | cinfo->dsi_pll_hsdiv_dsi_clk = 0; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 848 | |
| 849 | return 0; |
| 850 | } |
| 851 | |
| 852 | int dsi_pll_calc_clock_div_pck(bool is_tft, unsigned long req_pck, |
| 853 | struct dsi_clock_info *dsi_cinfo, |
| 854 | struct dispc_clock_info *dispc_cinfo) |
| 855 | { |
| 856 | struct dsi_clock_info cur, best; |
| 857 | struct dispc_clock_info best_dispc; |
| 858 | int min_fck_per_pck; |
| 859 | int match = 0; |
Archit Taneja | 1bb4783 | 2011-02-24 14:17:30 +0530 | [diff] [blame] | 860 | unsigned long dss_sys_clk, max_dss_fck; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 861 | |
Archit Taneja | 1bb4783 | 2011-02-24 14:17:30 +0530 | [diff] [blame] | 862 | dss_sys_clk = dss_clk_get_rate(DSS_CLK_SYSCK); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 863 | |
Taneja, Archit | 31ef823 | 2011-03-14 23:28:22 -0500 | [diff] [blame] | 864 | max_dss_fck = dss_feat_get_param_max(FEAT_PARAM_DSS_FCK); |
Archit Taneja | 819d807 | 2011-03-01 11:54:00 +0530 | [diff] [blame] | 865 | |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 866 | if (req_pck == dsi.cache_req_pck && |
Archit Taneja | 1bb4783 | 2011-02-24 14:17:30 +0530 | [diff] [blame] | 867 | dsi.cache_cinfo.clkin == dss_sys_clk) { |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 868 | DSSDBG("DSI clock info found from cache\n"); |
| 869 | *dsi_cinfo = dsi.cache_cinfo; |
Archit Taneja | 1bb4783 | 2011-02-24 14:17:30 +0530 | [diff] [blame] | 870 | dispc_find_clk_divs(is_tft, req_pck, |
| 871 | dsi_cinfo->dsi_pll_hsdiv_dispc_clk, dispc_cinfo); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 872 | return 0; |
| 873 | } |
| 874 | |
| 875 | min_fck_per_pck = CONFIG_OMAP2_DSS_MIN_FCK_PER_PCK; |
| 876 | |
| 877 | if (min_fck_per_pck && |
Archit Taneja | 819d807 | 2011-03-01 11:54:00 +0530 | [diff] [blame] | 878 | req_pck * min_fck_per_pck > max_dss_fck) { |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 879 | DSSERR("Requested pixel clock not possible with the current " |
| 880 | "OMAP2_DSS_MIN_FCK_PER_PCK setting. Turning " |
| 881 | "the constraint off.\n"); |
| 882 | min_fck_per_pck = 0; |
| 883 | } |
| 884 | |
| 885 | DSSDBG("dsi_pll_calc\n"); |
| 886 | |
| 887 | retry: |
| 888 | memset(&best, 0, sizeof(best)); |
| 889 | memset(&best_dispc, 0, sizeof(best_dispc)); |
| 890 | |
| 891 | memset(&cur, 0, sizeof(cur)); |
Archit Taneja | 1bb4783 | 2011-02-24 14:17:30 +0530 | [diff] [blame] | 892 | cur.clkin = dss_sys_clk; |
| 893 | cur.use_sys_clk = 1; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 894 | cur.highfreq = 0; |
| 895 | |
| 896 | /* no highfreq: 0.75MHz < Fint = clkin / regn < 2.1MHz */ |
| 897 | /* highfreq: 0.75MHz < Fint = clkin / (2*regn) < 2.1MHz */ |
| 898 | /* To reduce PLL lock time, keep Fint high (around 2 MHz) */ |
Taneja, Archit | 4964111 | 2011-03-14 23:28:23 -0500 | [diff] [blame^] | 899 | for (cur.regn = 1; cur.regn < dsi.regn_max; ++cur.regn) { |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 900 | if (cur.highfreq == 0) |
| 901 | cur.fint = cur.clkin / cur.regn; |
| 902 | else |
| 903 | cur.fint = cur.clkin / (2 * cur.regn); |
| 904 | |
Taneja, Archit | 4964111 | 2011-03-14 23:28:23 -0500 | [diff] [blame^] | 905 | if (cur.fint > dsi.fint_max || cur.fint < dsi.fint_min) |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 906 | continue; |
| 907 | |
| 908 | /* DSIPHY(MHz) = (2 * regm / regn) * (clkin / (highfreq + 1)) */ |
Taneja, Archit | 4964111 | 2011-03-14 23:28:23 -0500 | [diff] [blame^] | 909 | for (cur.regm = 1; cur.regm < dsi.regm_max; ++cur.regm) { |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 910 | unsigned long a, b; |
| 911 | |
| 912 | a = 2 * cur.regm * (cur.clkin/1000); |
| 913 | b = cur.regn * (cur.highfreq + 1); |
| 914 | cur.clkin4ddr = a / b * 1000; |
| 915 | |
| 916 | if (cur.clkin4ddr > 1800 * 1000 * 1000) |
| 917 | break; |
| 918 | |
Archit Taneja | 1bb4783 | 2011-02-24 14:17:30 +0530 | [diff] [blame] | 919 | /* dsi_pll_hsdiv_dispc_clk(MHz) = |
| 920 | * DSIPHY(MHz) / regm_dispc < 173MHz/186Mhz */ |
Taneja, Archit | 4964111 | 2011-03-14 23:28:23 -0500 | [diff] [blame^] | 921 | for (cur.regm_dispc = 1; cur.regm_dispc < dsi.regm_dispc_max; |
Archit Taneja | 1bb4783 | 2011-02-24 14:17:30 +0530 | [diff] [blame] | 922 | ++cur.regm_dispc) { |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 923 | struct dispc_clock_info cur_dispc; |
Archit Taneja | 1bb4783 | 2011-02-24 14:17:30 +0530 | [diff] [blame] | 924 | cur.dsi_pll_hsdiv_dispc_clk = |
| 925 | cur.clkin4ddr / cur.regm_dispc; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 926 | |
| 927 | /* this will narrow down the search a bit, |
| 928 | * but still give pixclocks below what was |
| 929 | * requested */ |
Archit Taneja | 1bb4783 | 2011-02-24 14:17:30 +0530 | [diff] [blame] | 930 | if (cur.dsi_pll_hsdiv_dispc_clk < req_pck) |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 931 | break; |
| 932 | |
Archit Taneja | 1bb4783 | 2011-02-24 14:17:30 +0530 | [diff] [blame] | 933 | if (cur.dsi_pll_hsdiv_dispc_clk > max_dss_fck) |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 934 | continue; |
| 935 | |
| 936 | if (min_fck_per_pck && |
Archit Taneja | 1bb4783 | 2011-02-24 14:17:30 +0530 | [diff] [blame] | 937 | cur.dsi_pll_hsdiv_dispc_clk < |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 938 | req_pck * min_fck_per_pck) |
| 939 | continue; |
| 940 | |
| 941 | match = 1; |
| 942 | |
| 943 | dispc_find_clk_divs(is_tft, req_pck, |
Archit Taneja | 1bb4783 | 2011-02-24 14:17:30 +0530 | [diff] [blame] | 944 | cur.dsi_pll_hsdiv_dispc_clk, |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 945 | &cur_dispc); |
| 946 | |
| 947 | if (abs(cur_dispc.pck - req_pck) < |
| 948 | abs(best_dispc.pck - req_pck)) { |
| 949 | best = cur; |
| 950 | best_dispc = cur_dispc; |
| 951 | |
| 952 | if (cur_dispc.pck == req_pck) |
| 953 | goto found; |
| 954 | } |
| 955 | } |
| 956 | } |
| 957 | } |
| 958 | found: |
| 959 | if (!match) { |
| 960 | if (min_fck_per_pck) { |
| 961 | DSSERR("Could not find suitable clock settings.\n" |
| 962 | "Turning FCK/PCK constraint off and" |
| 963 | "trying again.\n"); |
| 964 | min_fck_per_pck = 0; |
| 965 | goto retry; |
| 966 | } |
| 967 | |
| 968 | DSSERR("Could not find suitable clock settings.\n"); |
| 969 | |
| 970 | return -EINVAL; |
| 971 | } |
| 972 | |
Archit Taneja | 1bb4783 | 2011-02-24 14:17:30 +0530 | [diff] [blame] | 973 | /* dsi_pll_hsdiv_dsi_clk (regm_dsi) is not used */ |
| 974 | best.regm_dsi = 0; |
| 975 | best.dsi_pll_hsdiv_dsi_clk = 0; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 976 | |
| 977 | if (dsi_cinfo) |
| 978 | *dsi_cinfo = best; |
| 979 | if (dispc_cinfo) |
| 980 | *dispc_cinfo = best_dispc; |
| 981 | |
| 982 | dsi.cache_req_pck = req_pck; |
| 983 | dsi.cache_clk_freq = 0; |
| 984 | dsi.cache_cinfo = best; |
| 985 | |
| 986 | return 0; |
| 987 | } |
| 988 | |
| 989 | int dsi_pll_set_clock_div(struct dsi_clock_info *cinfo) |
| 990 | { |
| 991 | int r = 0; |
| 992 | u32 l; |
| 993 | int f; |
Taneja, Archit | 4964111 | 2011-03-14 23:28:23 -0500 | [diff] [blame^] | 994 | u8 regn_start, regn_end, regm_start, regm_end; |
| 995 | u8 regm_dispc_start, regm_dispc_end, regm_dsi_start, regm_dsi_end; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 996 | |
| 997 | DSSDBGF(); |
| 998 | |
| 999 | dsi.current_cinfo.fint = cinfo->fint; |
| 1000 | dsi.current_cinfo.clkin4ddr = cinfo->clkin4ddr; |
Archit Taneja | 1bb4783 | 2011-02-24 14:17:30 +0530 | [diff] [blame] | 1001 | dsi.current_cinfo.dsi_pll_hsdiv_dispc_clk = |
| 1002 | cinfo->dsi_pll_hsdiv_dispc_clk; |
| 1003 | dsi.current_cinfo.dsi_pll_hsdiv_dsi_clk = |
| 1004 | cinfo->dsi_pll_hsdiv_dsi_clk; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1005 | |
| 1006 | dsi.current_cinfo.regn = cinfo->regn; |
| 1007 | dsi.current_cinfo.regm = cinfo->regm; |
Archit Taneja | 1bb4783 | 2011-02-24 14:17:30 +0530 | [diff] [blame] | 1008 | dsi.current_cinfo.regm_dispc = cinfo->regm_dispc; |
| 1009 | dsi.current_cinfo.regm_dsi = cinfo->regm_dsi; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1010 | |
| 1011 | DSSDBG("DSI Fint %ld\n", cinfo->fint); |
| 1012 | |
| 1013 | DSSDBG("clkin (%s) rate %ld, highfreq %d\n", |
Archit Taneja | 1bb4783 | 2011-02-24 14:17:30 +0530 | [diff] [blame] | 1014 | cinfo->use_sys_clk ? "dss_sys_clk" : "pclkfree", |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1015 | cinfo->clkin, |
| 1016 | cinfo->highfreq); |
| 1017 | |
| 1018 | /* DSIPHY == CLKIN4DDR */ |
| 1019 | DSSDBG("CLKIN4DDR = 2 * %d / %d * %lu / %d = %lu\n", |
| 1020 | cinfo->regm, |
| 1021 | cinfo->regn, |
| 1022 | cinfo->clkin, |
| 1023 | cinfo->highfreq + 1, |
| 1024 | cinfo->clkin4ddr); |
| 1025 | |
| 1026 | DSSDBG("Data rate on 1 DSI lane %ld Mbps\n", |
| 1027 | cinfo->clkin4ddr / 1000 / 1000 / 2); |
| 1028 | |
| 1029 | DSSDBG("Clock lane freq %ld Hz\n", cinfo->clkin4ddr / 4); |
| 1030 | |
Archit Taneja | 1bb4783 | 2011-02-24 14:17:30 +0530 | [diff] [blame] | 1031 | DSSDBG("regm_dispc = %d, %s (%s) = %lu\n", cinfo->regm_dispc, |
Archit Taneja | 067a57e | 2011-03-02 11:57:25 +0530 | [diff] [blame] | 1032 | dss_get_generic_clk_source_name(DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC), |
| 1033 | dss_feat_get_clk_source_name(DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC), |
Archit Taneja | 1bb4783 | 2011-02-24 14:17:30 +0530 | [diff] [blame] | 1034 | cinfo->dsi_pll_hsdiv_dispc_clk); |
| 1035 | DSSDBG("regm_dsi = %d, %s (%s) = %lu\n", cinfo->regm_dsi, |
Archit Taneja | 067a57e | 2011-03-02 11:57:25 +0530 | [diff] [blame] | 1036 | dss_get_generic_clk_source_name(DSS_CLK_SRC_DSI_PLL_HSDIV_DSI), |
| 1037 | dss_feat_get_clk_source_name(DSS_CLK_SRC_DSI_PLL_HSDIV_DSI), |
Archit Taneja | 1bb4783 | 2011-02-24 14:17:30 +0530 | [diff] [blame] | 1038 | cinfo->dsi_pll_hsdiv_dsi_clk); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1039 | |
Taneja, Archit | 4964111 | 2011-03-14 23:28:23 -0500 | [diff] [blame^] | 1040 | dss_feat_get_reg_field(FEAT_REG_DSIPLL_REGN, ®n_start, ®n_end); |
| 1041 | dss_feat_get_reg_field(FEAT_REG_DSIPLL_REGM, ®m_start, ®m_end); |
| 1042 | dss_feat_get_reg_field(FEAT_REG_DSIPLL_REGM_DISPC, ®m_dispc_start, |
| 1043 | ®m_dispc_end); |
| 1044 | dss_feat_get_reg_field(FEAT_REG_DSIPLL_REGM_DSI, ®m_dsi_start, |
| 1045 | ®m_dsi_end); |
| 1046 | |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1047 | REG_FLD_MOD(DSI_PLL_CONTROL, 0, 0, 0); /* DSI_PLL_AUTOMODE = manual */ |
| 1048 | |
| 1049 | l = dsi_read_reg(DSI_PLL_CONFIGURATION1); |
| 1050 | l = FLD_MOD(l, 1, 0, 0); /* DSI_PLL_STOPMODE */ |
Taneja, Archit | 4964111 | 2011-03-14 23:28:23 -0500 | [diff] [blame^] | 1051 | /* DSI_PLL_REGN */ |
| 1052 | l = FLD_MOD(l, cinfo->regn - 1, regn_start, regn_end); |
| 1053 | /* DSI_PLL_REGM */ |
| 1054 | l = FLD_MOD(l, cinfo->regm, regm_start, regm_end); |
| 1055 | /* DSI_CLOCK_DIV */ |
Archit Taneja | 1bb4783 | 2011-02-24 14:17:30 +0530 | [diff] [blame] | 1056 | l = FLD_MOD(l, cinfo->regm_dispc > 0 ? cinfo->regm_dispc - 1 : 0, |
Taneja, Archit | 4964111 | 2011-03-14 23:28:23 -0500 | [diff] [blame^] | 1057 | regm_dispc_start, regm_dispc_end); |
| 1058 | /* DSIPROTO_CLOCK_DIV */ |
Archit Taneja | 1bb4783 | 2011-02-24 14:17:30 +0530 | [diff] [blame] | 1059 | l = FLD_MOD(l, cinfo->regm_dsi > 0 ? cinfo->regm_dsi - 1 : 0, |
Taneja, Archit | 4964111 | 2011-03-14 23:28:23 -0500 | [diff] [blame^] | 1060 | regm_dsi_start, regm_dsi_end); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1061 | dsi_write_reg(DSI_PLL_CONFIGURATION1, l); |
| 1062 | |
Taneja, Archit | 4964111 | 2011-03-14 23:28:23 -0500 | [diff] [blame^] | 1063 | BUG_ON(cinfo->fint < dsi.fint_min || cinfo->fint > dsi.fint_max); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1064 | if (cinfo->fint < 1000000) |
| 1065 | f = 0x3; |
| 1066 | else if (cinfo->fint < 1250000) |
| 1067 | f = 0x4; |
| 1068 | else if (cinfo->fint < 1500000) |
| 1069 | f = 0x5; |
| 1070 | else if (cinfo->fint < 1750000) |
| 1071 | f = 0x6; |
| 1072 | else |
| 1073 | f = 0x7; |
| 1074 | |
| 1075 | l = dsi_read_reg(DSI_PLL_CONFIGURATION2); |
| 1076 | l = FLD_MOD(l, f, 4, 1); /* DSI_PLL_FREQSEL */ |
Archit Taneja | 1bb4783 | 2011-02-24 14:17:30 +0530 | [diff] [blame] | 1077 | l = FLD_MOD(l, cinfo->use_sys_clk ? 0 : 1, |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1078 | 11, 11); /* DSI_PLL_CLKSEL */ |
| 1079 | l = FLD_MOD(l, cinfo->highfreq, |
| 1080 | 12, 12); /* DSI_PLL_HIGHFREQ */ |
| 1081 | l = FLD_MOD(l, 1, 13, 13); /* DSI_PLL_REFEN */ |
| 1082 | l = FLD_MOD(l, 0, 14, 14); /* DSIPHY_CLKINEN */ |
| 1083 | l = FLD_MOD(l, 1, 20, 20); /* DSI_HSDIVBYPASS */ |
| 1084 | dsi_write_reg(DSI_PLL_CONFIGURATION2, l); |
| 1085 | |
| 1086 | REG_FLD_MOD(DSI_PLL_GO, 1, 0, 0); /* DSI_PLL_GO */ |
| 1087 | |
| 1088 | if (wait_for_bit_change(DSI_PLL_GO, 0, 0) != 0) { |
| 1089 | DSSERR("dsi pll go bit not going down.\n"); |
| 1090 | r = -EIO; |
| 1091 | goto err; |
| 1092 | } |
| 1093 | |
| 1094 | if (wait_for_bit_change(DSI_PLL_STATUS, 1, 1) != 1) { |
| 1095 | DSSERR("cannot lock PLL\n"); |
| 1096 | r = -EIO; |
| 1097 | goto err; |
| 1098 | } |
| 1099 | |
| 1100 | dsi.pll_locked = 1; |
| 1101 | |
| 1102 | l = dsi_read_reg(DSI_PLL_CONFIGURATION2); |
| 1103 | l = FLD_MOD(l, 0, 0, 0); /* DSI_PLL_IDLE */ |
| 1104 | l = FLD_MOD(l, 0, 5, 5); /* DSI_PLL_PLLLPMODE */ |
| 1105 | l = FLD_MOD(l, 0, 6, 6); /* DSI_PLL_LOWCURRSTBY */ |
| 1106 | l = FLD_MOD(l, 0, 7, 7); /* DSI_PLL_TIGHTPHASELOCK */ |
| 1107 | l = FLD_MOD(l, 0, 8, 8); /* DSI_PLL_DRIFTGUARDEN */ |
| 1108 | l = FLD_MOD(l, 0, 10, 9); /* DSI_PLL_LOCKSEL */ |
| 1109 | l = FLD_MOD(l, 1, 13, 13); /* DSI_PLL_REFEN */ |
| 1110 | l = FLD_MOD(l, 1, 14, 14); /* DSIPHY_CLKINEN */ |
| 1111 | l = FLD_MOD(l, 0, 15, 15); /* DSI_BYPASSEN */ |
| 1112 | l = FLD_MOD(l, 1, 16, 16); /* DSS_CLOCK_EN */ |
| 1113 | l = FLD_MOD(l, 0, 17, 17); /* DSS_CLOCK_PWDN */ |
| 1114 | l = FLD_MOD(l, 1, 18, 18); /* DSI_PROTO_CLOCK_EN */ |
| 1115 | l = FLD_MOD(l, 0, 19, 19); /* DSI_PROTO_CLOCK_PWDN */ |
| 1116 | l = FLD_MOD(l, 0, 20, 20); /* DSI_HSDIVBYPASS */ |
| 1117 | dsi_write_reg(DSI_PLL_CONFIGURATION2, l); |
| 1118 | |
| 1119 | DSSDBG("PLL config done\n"); |
| 1120 | err: |
| 1121 | return r; |
| 1122 | } |
| 1123 | |
| 1124 | int dsi_pll_init(struct omap_dss_device *dssdev, bool enable_hsclk, |
| 1125 | bool enable_hsdiv) |
| 1126 | { |
| 1127 | int r = 0; |
| 1128 | enum dsi_pll_power_state pwstate; |
| 1129 | |
| 1130 | DSSDBG("PLL init\n"); |
| 1131 | |
Tomi Valkeinen | f2988ab | 2011-03-02 10:06:48 +0200 | [diff] [blame] | 1132 | #ifdef CONFIG_OMAP2_DSS_USE_DSI_PLL |
| 1133 | /* |
| 1134 | * HACK: this is just a quick hack to get the USE_DSI_PLL |
| 1135 | * option working. USE_DSI_PLL is itself a big hack, and |
| 1136 | * should be removed. |
| 1137 | */ |
| 1138 | if (dsi.vdds_dsi_reg == NULL) { |
| 1139 | struct regulator *vdds_dsi; |
| 1140 | |
| 1141 | vdds_dsi = regulator_get(&dsi.pdev->dev, "vdds_dsi"); |
| 1142 | |
| 1143 | if (IS_ERR(vdds_dsi)) { |
| 1144 | DSSERR("can't get VDDS_DSI regulator\n"); |
| 1145 | return PTR_ERR(vdds_dsi); |
| 1146 | } |
| 1147 | |
| 1148 | dsi.vdds_dsi_reg = vdds_dsi; |
| 1149 | } |
| 1150 | #endif |
| 1151 | |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1152 | enable_clocks(1); |
| 1153 | dsi_enable_pll_clock(1); |
| 1154 | |
| 1155 | r = regulator_enable(dsi.vdds_dsi_reg); |
| 1156 | if (r) |
| 1157 | goto err0; |
| 1158 | |
| 1159 | /* XXX PLL does not come out of reset without this... */ |
| 1160 | dispc_pck_free_enable(1); |
| 1161 | |
| 1162 | if (wait_for_bit_change(DSI_PLL_STATUS, 0, 1) != 1) { |
| 1163 | DSSERR("PLL not coming out of reset.\n"); |
| 1164 | r = -ENODEV; |
Ville Syrjälä | 481dfa0 | 2010-04-22 22:50:04 +0200 | [diff] [blame] | 1165 | dispc_pck_free_enable(0); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1166 | goto err1; |
| 1167 | } |
| 1168 | |
| 1169 | /* XXX ... but if left on, we get problems when planes do not |
| 1170 | * fill the whole display. No idea about this */ |
| 1171 | dispc_pck_free_enable(0); |
| 1172 | |
| 1173 | if (enable_hsclk && enable_hsdiv) |
| 1174 | pwstate = DSI_PLL_POWER_ON_ALL; |
| 1175 | else if (enable_hsclk) |
| 1176 | pwstate = DSI_PLL_POWER_ON_HSCLK; |
| 1177 | else if (enable_hsdiv) |
| 1178 | pwstate = DSI_PLL_POWER_ON_DIV; |
| 1179 | else |
| 1180 | pwstate = DSI_PLL_POWER_OFF; |
| 1181 | |
| 1182 | r = dsi_pll_power(pwstate); |
| 1183 | |
| 1184 | if (r) |
| 1185 | goto err1; |
| 1186 | |
| 1187 | DSSDBG("PLL init done\n"); |
| 1188 | |
| 1189 | return 0; |
| 1190 | err1: |
| 1191 | regulator_disable(dsi.vdds_dsi_reg); |
| 1192 | err0: |
| 1193 | enable_clocks(0); |
| 1194 | dsi_enable_pll_clock(0); |
| 1195 | return r; |
| 1196 | } |
| 1197 | |
| 1198 | void dsi_pll_uninit(void) |
| 1199 | { |
| 1200 | enable_clocks(0); |
| 1201 | dsi_enable_pll_clock(0); |
| 1202 | |
| 1203 | dsi.pll_locked = 0; |
| 1204 | dsi_pll_power(DSI_PLL_POWER_OFF); |
| 1205 | regulator_disable(dsi.vdds_dsi_reg); |
| 1206 | DSSDBG("PLL uninit done\n"); |
| 1207 | } |
| 1208 | |
| 1209 | void dsi_dump_clocks(struct seq_file *s) |
| 1210 | { |
| 1211 | int clksel; |
| 1212 | struct dsi_clock_info *cinfo = &dsi.current_cinfo; |
Archit Taneja | 067a57e | 2011-03-02 11:57:25 +0530 | [diff] [blame] | 1213 | enum dss_clk_source dispc_clk_src, dsi_clk_src; |
| 1214 | |
| 1215 | dispc_clk_src = dss_get_dispc_clk_source(); |
| 1216 | dsi_clk_src = dss_get_dsi_clk_source(); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1217 | |
| 1218 | enable_clocks(1); |
| 1219 | |
| 1220 | clksel = REG_GET(DSI_PLL_CONFIGURATION2, 11, 11); |
| 1221 | |
| 1222 | seq_printf(s, "- DSI PLL -\n"); |
| 1223 | |
| 1224 | seq_printf(s, "dsi pll source = %s\n", |
| 1225 | clksel == 0 ? |
Archit Taneja | 1bb4783 | 2011-02-24 14:17:30 +0530 | [diff] [blame] | 1226 | "dss_sys_clk" : "pclkfree"); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1227 | |
| 1228 | seq_printf(s, "Fint\t\t%-16luregn %u\n", cinfo->fint, cinfo->regn); |
| 1229 | |
| 1230 | seq_printf(s, "CLKIN4DDR\t%-16luregm %u\n", |
| 1231 | cinfo->clkin4ddr, cinfo->regm); |
| 1232 | |
Archit Taneja | 1bb4783 | 2011-02-24 14:17:30 +0530 | [diff] [blame] | 1233 | seq_printf(s, "%s (%s)\t%-16luregm_dispc %u\t(%s)\n", |
Archit Taneja | 067a57e | 2011-03-02 11:57:25 +0530 | [diff] [blame] | 1234 | dss_get_generic_clk_source_name(dispc_clk_src), |
| 1235 | dss_feat_get_clk_source_name(dispc_clk_src), |
Archit Taneja | 1bb4783 | 2011-02-24 14:17:30 +0530 | [diff] [blame] | 1236 | cinfo->dsi_pll_hsdiv_dispc_clk, |
| 1237 | cinfo->regm_dispc, |
Archit Taneja | 067a57e | 2011-03-02 11:57:25 +0530 | [diff] [blame] | 1238 | dispc_clk_src == DSS_CLK_SRC_FCK ? |
Tomi Valkeinen | 63cf28a | 2010-02-23 17:40:00 +0200 | [diff] [blame] | 1239 | "off" : "on"); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1240 | |
Archit Taneja | 1bb4783 | 2011-02-24 14:17:30 +0530 | [diff] [blame] | 1241 | seq_printf(s, "%s (%s)\t%-16luregm_dsi %u\t(%s)\n", |
Archit Taneja | 067a57e | 2011-03-02 11:57:25 +0530 | [diff] [blame] | 1242 | dss_get_generic_clk_source_name(dsi_clk_src), |
| 1243 | dss_feat_get_clk_source_name(dsi_clk_src), |
Archit Taneja | 1bb4783 | 2011-02-24 14:17:30 +0530 | [diff] [blame] | 1244 | cinfo->dsi_pll_hsdiv_dsi_clk, |
| 1245 | cinfo->regm_dsi, |
Archit Taneja | 067a57e | 2011-03-02 11:57:25 +0530 | [diff] [blame] | 1246 | dsi_clk_src == DSS_CLK_SRC_FCK ? |
Tomi Valkeinen | 63cf28a | 2010-02-23 17:40:00 +0200 | [diff] [blame] | 1247 | "off" : "on"); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1248 | |
| 1249 | seq_printf(s, "- DSI -\n"); |
| 1250 | |
Archit Taneja | 067a57e | 2011-03-02 11:57:25 +0530 | [diff] [blame] | 1251 | seq_printf(s, "dsi fclk source = %s (%s)\n", |
| 1252 | dss_get_generic_clk_source_name(dsi_clk_src), |
| 1253 | dss_feat_get_clk_source_name(dsi_clk_src)); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1254 | |
| 1255 | seq_printf(s, "DSI_FCLK\t%lu\n", dsi_fclk_rate()); |
| 1256 | |
| 1257 | seq_printf(s, "DDR_CLK\t\t%lu\n", |
| 1258 | cinfo->clkin4ddr / 4); |
| 1259 | |
| 1260 | seq_printf(s, "TxByteClkHS\t%lu\n", dsi_get_txbyteclkhs()); |
| 1261 | |
| 1262 | seq_printf(s, "LP_CLK\t\t%lu\n", cinfo->lp_clk); |
| 1263 | |
| 1264 | seq_printf(s, "VP_CLK\t\t%lu\n" |
| 1265 | "VP_PCLK\t\t%lu\n", |
Sumit Semwal | ff1b2cd | 2010-12-02 11:27:11 +0000 | [diff] [blame] | 1266 | dispc_lclk_rate(OMAP_DSS_CHANNEL_LCD), |
| 1267 | dispc_pclk_rate(OMAP_DSS_CHANNEL_LCD)); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1268 | |
| 1269 | enable_clocks(0); |
| 1270 | } |
| 1271 | |
Tomi Valkeinen | dfc0fd8 | 2009-12-17 14:35:21 +0200 | [diff] [blame] | 1272 | #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS |
| 1273 | void dsi_dump_irqs(struct seq_file *s) |
| 1274 | { |
| 1275 | unsigned long flags; |
| 1276 | struct dsi_irq_stats stats; |
| 1277 | |
| 1278 | spin_lock_irqsave(&dsi.irq_stats_lock, flags); |
| 1279 | |
| 1280 | stats = dsi.irq_stats; |
| 1281 | memset(&dsi.irq_stats, 0, sizeof(dsi.irq_stats)); |
| 1282 | dsi.irq_stats.last_reset = jiffies; |
| 1283 | |
| 1284 | spin_unlock_irqrestore(&dsi.irq_stats_lock, flags); |
| 1285 | |
| 1286 | seq_printf(s, "period %u ms\n", |
| 1287 | jiffies_to_msecs(jiffies - stats.last_reset)); |
| 1288 | |
| 1289 | seq_printf(s, "irqs %d\n", stats.irq_count); |
| 1290 | #define PIS(x) \ |
| 1291 | seq_printf(s, "%-20s %10d\n", #x, stats.dsi_irqs[ffs(DSI_IRQ_##x)-1]); |
| 1292 | |
| 1293 | seq_printf(s, "-- DSI interrupts --\n"); |
| 1294 | PIS(VC0); |
| 1295 | PIS(VC1); |
| 1296 | PIS(VC2); |
| 1297 | PIS(VC3); |
| 1298 | PIS(WAKEUP); |
| 1299 | PIS(RESYNC); |
| 1300 | PIS(PLL_LOCK); |
| 1301 | PIS(PLL_UNLOCK); |
| 1302 | PIS(PLL_RECALL); |
| 1303 | PIS(COMPLEXIO_ERR); |
| 1304 | PIS(HS_TX_TIMEOUT); |
| 1305 | PIS(LP_RX_TIMEOUT); |
| 1306 | PIS(TE_TRIGGER); |
| 1307 | PIS(ACK_TRIGGER); |
| 1308 | PIS(SYNC_LOST); |
| 1309 | PIS(LDO_POWER_GOOD); |
| 1310 | PIS(TA_TIMEOUT); |
| 1311 | #undef PIS |
| 1312 | |
| 1313 | #define PIS(x) \ |
| 1314 | seq_printf(s, "%-20s %10d %10d %10d %10d\n", #x, \ |
| 1315 | stats.vc_irqs[0][ffs(DSI_VC_IRQ_##x)-1], \ |
| 1316 | stats.vc_irqs[1][ffs(DSI_VC_IRQ_##x)-1], \ |
| 1317 | stats.vc_irqs[2][ffs(DSI_VC_IRQ_##x)-1], \ |
| 1318 | stats.vc_irqs[3][ffs(DSI_VC_IRQ_##x)-1]); |
| 1319 | |
| 1320 | seq_printf(s, "-- VC interrupts --\n"); |
| 1321 | PIS(CS); |
| 1322 | PIS(ECC_CORR); |
| 1323 | PIS(PACKET_SENT); |
| 1324 | PIS(FIFO_TX_OVF); |
| 1325 | PIS(FIFO_RX_OVF); |
| 1326 | PIS(BTA); |
| 1327 | PIS(ECC_NO_CORR); |
| 1328 | PIS(FIFO_TX_UDF); |
| 1329 | PIS(PP_BUSY_CHANGE); |
| 1330 | #undef PIS |
| 1331 | |
| 1332 | #define PIS(x) \ |
| 1333 | seq_printf(s, "%-20s %10d\n", #x, \ |
| 1334 | stats.cio_irqs[ffs(DSI_CIO_IRQ_##x)-1]); |
| 1335 | |
| 1336 | seq_printf(s, "-- CIO interrupts --\n"); |
| 1337 | PIS(ERRSYNCESC1); |
| 1338 | PIS(ERRSYNCESC2); |
| 1339 | PIS(ERRSYNCESC3); |
| 1340 | PIS(ERRESC1); |
| 1341 | PIS(ERRESC2); |
| 1342 | PIS(ERRESC3); |
| 1343 | PIS(ERRCONTROL1); |
| 1344 | PIS(ERRCONTROL2); |
| 1345 | PIS(ERRCONTROL3); |
| 1346 | PIS(STATEULPS1); |
| 1347 | PIS(STATEULPS2); |
| 1348 | PIS(STATEULPS3); |
| 1349 | PIS(ERRCONTENTIONLP0_1); |
| 1350 | PIS(ERRCONTENTIONLP1_1); |
| 1351 | PIS(ERRCONTENTIONLP0_2); |
| 1352 | PIS(ERRCONTENTIONLP1_2); |
| 1353 | PIS(ERRCONTENTIONLP0_3); |
| 1354 | PIS(ERRCONTENTIONLP1_3); |
| 1355 | PIS(ULPSACTIVENOT_ALL0); |
| 1356 | PIS(ULPSACTIVENOT_ALL1); |
| 1357 | #undef PIS |
| 1358 | } |
| 1359 | #endif |
| 1360 | |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1361 | void dsi_dump_regs(struct seq_file *s) |
| 1362 | { |
| 1363 | #define DUMPREG(r) seq_printf(s, "%-35s %08x\n", #r, dsi_read_reg(r)) |
| 1364 | |
Archit Taneja | 6af9cd1 | 2011-01-31 16:27:44 +0000 | [diff] [blame] | 1365 | dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1366 | |
| 1367 | DUMPREG(DSI_REVISION); |
| 1368 | DUMPREG(DSI_SYSCONFIG); |
| 1369 | DUMPREG(DSI_SYSSTATUS); |
| 1370 | DUMPREG(DSI_IRQSTATUS); |
| 1371 | DUMPREG(DSI_IRQENABLE); |
| 1372 | DUMPREG(DSI_CTRL); |
| 1373 | DUMPREG(DSI_COMPLEXIO_CFG1); |
| 1374 | DUMPREG(DSI_COMPLEXIO_IRQ_STATUS); |
| 1375 | DUMPREG(DSI_COMPLEXIO_IRQ_ENABLE); |
| 1376 | DUMPREG(DSI_CLK_CTRL); |
| 1377 | DUMPREG(DSI_TIMING1); |
| 1378 | DUMPREG(DSI_TIMING2); |
| 1379 | DUMPREG(DSI_VM_TIMING1); |
| 1380 | DUMPREG(DSI_VM_TIMING2); |
| 1381 | DUMPREG(DSI_VM_TIMING3); |
| 1382 | DUMPREG(DSI_CLK_TIMING); |
| 1383 | DUMPREG(DSI_TX_FIFO_VC_SIZE); |
| 1384 | DUMPREG(DSI_RX_FIFO_VC_SIZE); |
| 1385 | DUMPREG(DSI_COMPLEXIO_CFG2); |
| 1386 | DUMPREG(DSI_RX_FIFO_VC_FULLNESS); |
| 1387 | DUMPREG(DSI_VM_TIMING4); |
| 1388 | DUMPREG(DSI_TX_FIFO_VC_EMPTINESS); |
| 1389 | DUMPREG(DSI_VM_TIMING5); |
| 1390 | DUMPREG(DSI_VM_TIMING6); |
| 1391 | DUMPREG(DSI_VM_TIMING7); |
| 1392 | DUMPREG(DSI_STOPCLK_TIMING); |
| 1393 | |
| 1394 | DUMPREG(DSI_VC_CTRL(0)); |
| 1395 | DUMPREG(DSI_VC_TE(0)); |
| 1396 | DUMPREG(DSI_VC_LONG_PACKET_HEADER(0)); |
| 1397 | DUMPREG(DSI_VC_LONG_PACKET_PAYLOAD(0)); |
| 1398 | DUMPREG(DSI_VC_SHORT_PACKET_HEADER(0)); |
| 1399 | DUMPREG(DSI_VC_IRQSTATUS(0)); |
| 1400 | DUMPREG(DSI_VC_IRQENABLE(0)); |
| 1401 | |
| 1402 | DUMPREG(DSI_VC_CTRL(1)); |
| 1403 | DUMPREG(DSI_VC_TE(1)); |
| 1404 | DUMPREG(DSI_VC_LONG_PACKET_HEADER(1)); |
| 1405 | DUMPREG(DSI_VC_LONG_PACKET_PAYLOAD(1)); |
| 1406 | DUMPREG(DSI_VC_SHORT_PACKET_HEADER(1)); |
| 1407 | DUMPREG(DSI_VC_IRQSTATUS(1)); |
| 1408 | DUMPREG(DSI_VC_IRQENABLE(1)); |
| 1409 | |
| 1410 | DUMPREG(DSI_VC_CTRL(2)); |
| 1411 | DUMPREG(DSI_VC_TE(2)); |
| 1412 | DUMPREG(DSI_VC_LONG_PACKET_HEADER(2)); |
| 1413 | DUMPREG(DSI_VC_LONG_PACKET_PAYLOAD(2)); |
| 1414 | DUMPREG(DSI_VC_SHORT_PACKET_HEADER(2)); |
| 1415 | DUMPREG(DSI_VC_IRQSTATUS(2)); |
| 1416 | DUMPREG(DSI_VC_IRQENABLE(2)); |
| 1417 | |
| 1418 | DUMPREG(DSI_VC_CTRL(3)); |
| 1419 | DUMPREG(DSI_VC_TE(3)); |
| 1420 | DUMPREG(DSI_VC_LONG_PACKET_HEADER(3)); |
| 1421 | DUMPREG(DSI_VC_LONG_PACKET_PAYLOAD(3)); |
| 1422 | DUMPREG(DSI_VC_SHORT_PACKET_HEADER(3)); |
| 1423 | DUMPREG(DSI_VC_IRQSTATUS(3)); |
| 1424 | DUMPREG(DSI_VC_IRQENABLE(3)); |
| 1425 | |
| 1426 | DUMPREG(DSI_DSIPHY_CFG0); |
| 1427 | DUMPREG(DSI_DSIPHY_CFG1); |
| 1428 | DUMPREG(DSI_DSIPHY_CFG2); |
| 1429 | DUMPREG(DSI_DSIPHY_CFG5); |
| 1430 | |
| 1431 | DUMPREG(DSI_PLL_CONTROL); |
| 1432 | DUMPREG(DSI_PLL_STATUS); |
| 1433 | DUMPREG(DSI_PLL_GO); |
| 1434 | DUMPREG(DSI_PLL_CONFIGURATION1); |
| 1435 | DUMPREG(DSI_PLL_CONFIGURATION2); |
| 1436 | |
Archit Taneja | 6af9cd1 | 2011-01-31 16:27:44 +0000 | [diff] [blame] | 1437 | dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1438 | #undef DUMPREG |
| 1439 | } |
| 1440 | |
| 1441 | enum dsi_complexio_power_state { |
| 1442 | DSI_COMPLEXIO_POWER_OFF = 0x0, |
| 1443 | DSI_COMPLEXIO_POWER_ON = 0x1, |
| 1444 | DSI_COMPLEXIO_POWER_ULPS = 0x2, |
| 1445 | }; |
| 1446 | |
| 1447 | static int dsi_complexio_power(enum dsi_complexio_power_state state) |
| 1448 | { |
| 1449 | int t = 0; |
| 1450 | |
| 1451 | /* PWR_CMD */ |
| 1452 | REG_FLD_MOD(DSI_COMPLEXIO_CFG1, state, 28, 27); |
| 1453 | |
| 1454 | /* PWR_STATUS */ |
| 1455 | while (FLD_GET(dsi_read_reg(DSI_COMPLEXIO_CFG1), 26, 25) != state) { |
Tomi Valkeinen | 24be78b | 2010-01-07 14:19:48 +0200 | [diff] [blame] | 1456 | if (++t > 1000) { |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1457 | DSSERR("failed to set complexio power state to " |
| 1458 | "%d\n", state); |
| 1459 | return -ENODEV; |
| 1460 | } |
Tomi Valkeinen | 24be78b | 2010-01-07 14:19:48 +0200 | [diff] [blame] | 1461 | udelay(1); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1462 | } |
| 1463 | |
| 1464 | return 0; |
| 1465 | } |
| 1466 | |
| 1467 | static void dsi_complexio_config(struct omap_dss_device *dssdev) |
| 1468 | { |
| 1469 | u32 r; |
| 1470 | |
| 1471 | int clk_lane = dssdev->phy.dsi.clk_lane; |
| 1472 | int data1_lane = dssdev->phy.dsi.data1_lane; |
| 1473 | int data2_lane = dssdev->phy.dsi.data2_lane; |
| 1474 | int clk_pol = dssdev->phy.dsi.clk_pol; |
| 1475 | int data1_pol = dssdev->phy.dsi.data1_pol; |
| 1476 | int data2_pol = dssdev->phy.dsi.data2_pol; |
| 1477 | |
| 1478 | r = dsi_read_reg(DSI_COMPLEXIO_CFG1); |
| 1479 | r = FLD_MOD(r, clk_lane, 2, 0); |
| 1480 | r = FLD_MOD(r, clk_pol, 3, 3); |
| 1481 | r = FLD_MOD(r, data1_lane, 6, 4); |
| 1482 | r = FLD_MOD(r, data1_pol, 7, 7); |
| 1483 | r = FLD_MOD(r, data2_lane, 10, 8); |
| 1484 | r = FLD_MOD(r, data2_pol, 11, 11); |
| 1485 | dsi_write_reg(DSI_COMPLEXIO_CFG1, r); |
| 1486 | |
| 1487 | /* The configuration of the DSI complex I/O (number of data lanes, |
| 1488 | position, differential order) should not be changed while |
| 1489 | DSS.DSI_CLK_CRTRL[20] LP_CLK_ENABLE bit is set to 1. In order for |
| 1490 | the hardware to take into account a new configuration of the complex |
| 1491 | I/O (done in DSS.DSI_COMPLEXIO_CFG1 register), it is recommended to |
| 1492 | follow this sequence: First set the DSS.DSI_CTRL[0] IF_EN bit to 1, |
| 1493 | then reset the DSS.DSI_CTRL[0] IF_EN to 0, then set |
| 1494 | DSS.DSI_CLK_CTRL[20] LP_CLK_ENABLE to 1 and finally set again the |
| 1495 | DSS.DSI_CTRL[0] IF_EN bit to 1. If the sequence is not followed, the |
| 1496 | DSI complex I/O configuration is unknown. */ |
| 1497 | |
| 1498 | /* |
| 1499 | REG_FLD_MOD(DSI_CTRL, 1, 0, 0); |
| 1500 | REG_FLD_MOD(DSI_CTRL, 0, 0, 0); |
| 1501 | REG_FLD_MOD(DSI_CLK_CTRL, 1, 20, 20); |
| 1502 | REG_FLD_MOD(DSI_CTRL, 1, 0, 0); |
| 1503 | */ |
| 1504 | } |
| 1505 | |
| 1506 | static inline unsigned ns2ddr(unsigned ns) |
| 1507 | { |
| 1508 | /* convert time in ns to ddr ticks, rounding up */ |
| 1509 | unsigned long ddr_clk = dsi.current_cinfo.clkin4ddr / 4; |
| 1510 | return (ns * (ddr_clk / 1000 / 1000) + 999) / 1000; |
| 1511 | } |
| 1512 | |
| 1513 | static inline unsigned ddr2ns(unsigned ddr) |
| 1514 | { |
| 1515 | unsigned long ddr_clk = dsi.current_cinfo.clkin4ddr / 4; |
| 1516 | return ddr * 1000 * 1000 / (ddr_clk / 1000); |
| 1517 | } |
| 1518 | |
| 1519 | static void dsi_complexio_timings(void) |
| 1520 | { |
| 1521 | u32 r; |
| 1522 | u32 ths_prepare, ths_prepare_ths_zero, ths_trail, ths_exit; |
| 1523 | u32 tlpx_half, tclk_trail, tclk_zero; |
| 1524 | u32 tclk_prepare; |
| 1525 | |
| 1526 | /* calculate timings */ |
| 1527 | |
| 1528 | /* 1 * DDR_CLK = 2 * UI */ |
| 1529 | |
| 1530 | /* min 40ns + 4*UI max 85ns + 6*UI */ |
| 1531 | ths_prepare = ns2ddr(70) + 2; |
| 1532 | |
| 1533 | /* min 145ns + 10*UI */ |
| 1534 | ths_prepare_ths_zero = ns2ddr(175) + 2; |
| 1535 | |
| 1536 | /* min max(8*UI, 60ns+4*UI) */ |
| 1537 | ths_trail = ns2ddr(60) + 5; |
| 1538 | |
| 1539 | /* min 100ns */ |
| 1540 | ths_exit = ns2ddr(145); |
| 1541 | |
| 1542 | /* tlpx min 50n */ |
| 1543 | tlpx_half = ns2ddr(25); |
| 1544 | |
| 1545 | /* min 60ns */ |
| 1546 | tclk_trail = ns2ddr(60) + 2; |
| 1547 | |
| 1548 | /* min 38ns, max 95ns */ |
| 1549 | tclk_prepare = ns2ddr(65); |
| 1550 | |
| 1551 | /* min tclk-prepare + tclk-zero = 300ns */ |
| 1552 | tclk_zero = ns2ddr(260); |
| 1553 | |
| 1554 | DSSDBG("ths_prepare %u (%uns), ths_prepare_ths_zero %u (%uns)\n", |
| 1555 | ths_prepare, ddr2ns(ths_prepare), |
| 1556 | ths_prepare_ths_zero, ddr2ns(ths_prepare_ths_zero)); |
| 1557 | DSSDBG("ths_trail %u (%uns), ths_exit %u (%uns)\n", |
| 1558 | ths_trail, ddr2ns(ths_trail), |
| 1559 | ths_exit, ddr2ns(ths_exit)); |
| 1560 | |
| 1561 | DSSDBG("tlpx_half %u (%uns), tclk_trail %u (%uns), " |
| 1562 | "tclk_zero %u (%uns)\n", |
| 1563 | tlpx_half, ddr2ns(tlpx_half), |
| 1564 | tclk_trail, ddr2ns(tclk_trail), |
| 1565 | tclk_zero, ddr2ns(tclk_zero)); |
| 1566 | DSSDBG("tclk_prepare %u (%uns)\n", |
| 1567 | tclk_prepare, ddr2ns(tclk_prepare)); |
| 1568 | |
| 1569 | /* program timings */ |
| 1570 | |
| 1571 | r = dsi_read_reg(DSI_DSIPHY_CFG0); |
| 1572 | r = FLD_MOD(r, ths_prepare, 31, 24); |
| 1573 | r = FLD_MOD(r, ths_prepare_ths_zero, 23, 16); |
| 1574 | r = FLD_MOD(r, ths_trail, 15, 8); |
| 1575 | r = FLD_MOD(r, ths_exit, 7, 0); |
| 1576 | dsi_write_reg(DSI_DSIPHY_CFG0, r); |
| 1577 | |
| 1578 | r = dsi_read_reg(DSI_DSIPHY_CFG1); |
| 1579 | r = FLD_MOD(r, tlpx_half, 22, 16); |
| 1580 | r = FLD_MOD(r, tclk_trail, 15, 8); |
| 1581 | r = FLD_MOD(r, tclk_zero, 7, 0); |
| 1582 | dsi_write_reg(DSI_DSIPHY_CFG1, r); |
| 1583 | |
| 1584 | r = dsi_read_reg(DSI_DSIPHY_CFG2); |
| 1585 | r = FLD_MOD(r, tclk_prepare, 7, 0); |
| 1586 | dsi_write_reg(DSI_DSIPHY_CFG2, r); |
| 1587 | } |
| 1588 | |
| 1589 | |
| 1590 | static int dsi_complexio_init(struct omap_dss_device *dssdev) |
| 1591 | { |
| 1592 | int r = 0; |
| 1593 | |
| 1594 | DSSDBG("dsi_complexio_init\n"); |
| 1595 | |
| 1596 | /* CIO_CLK_ICG, enable L3 clk to CIO */ |
| 1597 | REG_FLD_MOD(DSI_CLK_CTRL, 1, 14, 14); |
| 1598 | |
| 1599 | /* A dummy read using the SCP interface to any DSIPHY register is |
| 1600 | * required after DSIPHY reset to complete the reset of the DSI complex |
| 1601 | * I/O. */ |
| 1602 | dsi_read_reg(DSI_DSIPHY_CFG5); |
| 1603 | |
| 1604 | if (wait_for_bit_change(DSI_DSIPHY_CFG5, 30, 1) != 1) { |
| 1605 | DSSERR("ComplexIO PHY not coming out of reset.\n"); |
| 1606 | r = -ENODEV; |
| 1607 | goto err; |
| 1608 | } |
| 1609 | |
| 1610 | dsi_complexio_config(dssdev); |
| 1611 | |
| 1612 | r = dsi_complexio_power(DSI_COMPLEXIO_POWER_ON); |
| 1613 | |
| 1614 | if (r) |
| 1615 | goto err; |
| 1616 | |
| 1617 | if (wait_for_bit_change(DSI_COMPLEXIO_CFG1, 29, 1) != 1) { |
| 1618 | DSSERR("ComplexIO not coming out of reset.\n"); |
| 1619 | r = -ENODEV; |
| 1620 | goto err; |
| 1621 | } |
| 1622 | |
| 1623 | if (wait_for_bit_change(DSI_COMPLEXIO_CFG1, 21, 1) != 1) { |
| 1624 | DSSERR("ComplexIO LDO power down.\n"); |
| 1625 | r = -ENODEV; |
| 1626 | goto err; |
| 1627 | } |
| 1628 | |
| 1629 | dsi_complexio_timings(); |
| 1630 | |
| 1631 | /* |
| 1632 | The configuration of the DSI complex I/O (number of data lanes, |
| 1633 | position, differential order) should not be changed while |
| 1634 | DSS.DSI_CLK_CRTRL[20] LP_CLK_ENABLE bit is set to 1. For the |
| 1635 | hardware to recognize a new configuration of the complex I/O (done |
| 1636 | in DSS.DSI_COMPLEXIO_CFG1 register), it is recommended to follow |
| 1637 | this sequence: First set the DSS.DSI_CTRL[0] IF_EN bit to 1, next |
| 1638 | reset the DSS.DSI_CTRL[0] IF_EN to 0, then set DSS.DSI_CLK_CTRL[20] |
| 1639 | LP_CLK_ENABLE to 1, and finally, set again the DSS.DSI_CTRL[0] IF_EN |
| 1640 | bit to 1. If the sequence is not followed, the DSi complex I/O |
| 1641 | configuration is undetermined. |
| 1642 | */ |
| 1643 | dsi_if_enable(1); |
| 1644 | dsi_if_enable(0); |
| 1645 | REG_FLD_MOD(DSI_CLK_CTRL, 1, 20, 20); /* LP_CLK_ENABLE */ |
| 1646 | dsi_if_enable(1); |
| 1647 | dsi_if_enable(0); |
| 1648 | |
| 1649 | DSSDBG("CIO init done\n"); |
| 1650 | err: |
| 1651 | return r; |
| 1652 | } |
| 1653 | |
| 1654 | static void dsi_complexio_uninit(void) |
| 1655 | { |
| 1656 | dsi_complexio_power(DSI_COMPLEXIO_POWER_OFF); |
| 1657 | } |
| 1658 | |
| 1659 | static int _dsi_wait_reset(void) |
| 1660 | { |
Tomi Valkeinen | 24be78b | 2010-01-07 14:19:48 +0200 | [diff] [blame] | 1661 | int t = 0; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1662 | |
| 1663 | while (REG_GET(DSI_SYSSTATUS, 0, 0) == 0) { |
Tomi Valkeinen | 24be78b | 2010-01-07 14:19:48 +0200 | [diff] [blame] | 1664 | if (++t > 5) { |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1665 | DSSERR("soft reset failed\n"); |
| 1666 | return -ENODEV; |
| 1667 | } |
| 1668 | udelay(1); |
| 1669 | } |
| 1670 | |
| 1671 | return 0; |
| 1672 | } |
| 1673 | |
| 1674 | static int _dsi_reset(void) |
| 1675 | { |
| 1676 | /* Soft reset */ |
| 1677 | REG_FLD_MOD(DSI_SYSCONFIG, 1, 1, 1); |
| 1678 | return _dsi_wait_reset(); |
| 1679 | } |
| 1680 | |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1681 | static void dsi_config_tx_fifo(enum fifo_size size1, enum fifo_size size2, |
| 1682 | enum fifo_size size3, enum fifo_size size4) |
| 1683 | { |
| 1684 | u32 r = 0; |
| 1685 | int add = 0; |
| 1686 | int i; |
| 1687 | |
| 1688 | dsi.vc[0].fifo_size = size1; |
| 1689 | dsi.vc[1].fifo_size = size2; |
| 1690 | dsi.vc[2].fifo_size = size3; |
| 1691 | dsi.vc[3].fifo_size = size4; |
| 1692 | |
| 1693 | for (i = 0; i < 4; i++) { |
| 1694 | u8 v; |
| 1695 | int size = dsi.vc[i].fifo_size; |
| 1696 | |
| 1697 | if (add + size > 4) { |
| 1698 | DSSERR("Illegal FIFO configuration\n"); |
| 1699 | BUG(); |
| 1700 | } |
| 1701 | |
| 1702 | v = FLD_VAL(add, 2, 0) | FLD_VAL(size, 7, 4); |
| 1703 | r |= v << (8 * i); |
| 1704 | /*DSSDBG("TX FIFO vc %d: size %d, add %d\n", i, size, add); */ |
| 1705 | add += size; |
| 1706 | } |
| 1707 | |
| 1708 | dsi_write_reg(DSI_TX_FIFO_VC_SIZE, r); |
| 1709 | } |
| 1710 | |
| 1711 | static void dsi_config_rx_fifo(enum fifo_size size1, enum fifo_size size2, |
| 1712 | enum fifo_size size3, enum fifo_size size4) |
| 1713 | { |
| 1714 | u32 r = 0; |
| 1715 | int add = 0; |
| 1716 | int i; |
| 1717 | |
| 1718 | dsi.vc[0].fifo_size = size1; |
| 1719 | dsi.vc[1].fifo_size = size2; |
| 1720 | dsi.vc[2].fifo_size = size3; |
| 1721 | dsi.vc[3].fifo_size = size4; |
| 1722 | |
| 1723 | for (i = 0; i < 4; i++) { |
| 1724 | u8 v; |
| 1725 | int size = dsi.vc[i].fifo_size; |
| 1726 | |
| 1727 | if (add + size > 4) { |
| 1728 | DSSERR("Illegal FIFO configuration\n"); |
| 1729 | BUG(); |
| 1730 | } |
| 1731 | |
| 1732 | v = FLD_VAL(add, 2, 0) | FLD_VAL(size, 7, 4); |
| 1733 | r |= v << (8 * i); |
| 1734 | /*DSSDBG("RX FIFO vc %d: size %d, add %d\n", i, size, add); */ |
| 1735 | add += size; |
| 1736 | } |
| 1737 | |
| 1738 | dsi_write_reg(DSI_RX_FIFO_VC_SIZE, r); |
| 1739 | } |
| 1740 | |
| 1741 | static int dsi_force_tx_stop_mode_io(void) |
| 1742 | { |
| 1743 | u32 r; |
| 1744 | |
| 1745 | r = dsi_read_reg(DSI_TIMING1); |
| 1746 | r = FLD_MOD(r, 1, 15, 15); /* FORCE_TX_STOP_MODE_IO */ |
| 1747 | dsi_write_reg(DSI_TIMING1, r); |
| 1748 | |
| 1749 | if (wait_for_bit_change(DSI_TIMING1, 15, 0) != 0) { |
| 1750 | DSSERR("TX_STOP bit not going down\n"); |
| 1751 | return -EIO; |
| 1752 | } |
| 1753 | |
| 1754 | return 0; |
| 1755 | } |
| 1756 | |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1757 | static int dsi_vc_enable(int channel, bool enable) |
| 1758 | { |
Tomi Valkeinen | 446f7bf | 2010-01-11 16:12:31 +0200 | [diff] [blame] | 1759 | DSSDBG("dsi_vc_enable channel %d, enable %d\n", |
| 1760 | channel, enable); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1761 | |
| 1762 | enable = enable ? 1 : 0; |
| 1763 | |
| 1764 | REG_FLD_MOD(DSI_VC_CTRL(channel), enable, 0, 0); |
| 1765 | |
| 1766 | if (wait_for_bit_change(DSI_VC_CTRL(channel), 0, enable) != enable) { |
| 1767 | DSSERR("Failed to set dsi_vc_enable to %d\n", enable); |
| 1768 | return -EIO; |
| 1769 | } |
| 1770 | |
| 1771 | return 0; |
| 1772 | } |
| 1773 | |
| 1774 | static void dsi_vc_initial_config(int channel) |
| 1775 | { |
| 1776 | u32 r; |
| 1777 | |
| 1778 | DSSDBGF("%d", channel); |
| 1779 | |
| 1780 | r = dsi_read_reg(DSI_VC_CTRL(channel)); |
| 1781 | |
| 1782 | if (FLD_GET(r, 15, 15)) /* VC_BUSY */ |
| 1783 | DSSERR("VC(%d) busy when trying to configure it!\n", |
| 1784 | channel); |
| 1785 | |
| 1786 | r = FLD_MOD(r, 0, 1, 1); /* SOURCE, 0 = L4 */ |
| 1787 | r = FLD_MOD(r, 0, 2, 2); /* BTA_SHORT_EN */ |
| 1788 | r = FLD_MOD(r, 0, 3, 3); /* BTA_LONG_EN */ |
| 1789 | r = FLD_MOD(r, 0, 4, 4); /* MODE, 0 = command */ |
| 1790 | r = FLD_MOD(r, 1, 7, 7); /* CS_TX_EN */ |
| 1791 | r = FLD_MOD(r, 1, 8, 8); /* ECC_TX_EN */ |
| 1792 | r = FLD_MOD(r, 0, 9, 9); /* MODE_SPEED, high speed on/off */ |
| 1793 | |
| 1794 | r = FLD_MOD(r, 4, 29, 27); /* DMA_RX_REQ_NB = no dma */ |
| 1795 | r = FLD_MOD(r, 4, 23, 21); /* DMA_TX_REQ_NB = no dma */ |
| 1796 | |
| 1797 | dsi_write_reg(DSI_VC_CTRL(channel), r); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1798 | } |
| 1799 | |
Tomi Valkeinen | 9ecd968 | 2010-04-30 11:24:33 +0300 | [diff] [blame] | 1800 | static int dsi_vc_config_l4(int channel) |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1801 | { |
| 1802 | if (dsi.vc[channel].mode == DSI_VC_MODE_L4) |
Tomi Valkeinen | 9ecd968 | 2010-04-30 11:24:33 +0300 | [diff] [blame] | 1803 | return 0; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1804 | |
| 1805 | DSSDBGF("%d", channel); |
| 1806 | |
| 1807 | dsi_vc_enable(channel, 0); |
| 1808 | |
Tomi Valkeinen | 9ecd968 | 2010-04-30 11:24:33 +0300 | [diff] [blame] | 1809 | /* VC_BUSY */ |
| 1810 | if (wait_for_bit_change(DSI_VC_CTRL(channel), 15, 0) != 0) { |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1811 | DSSERR("vc(%d) busy when trying to config for L4\n", channel); |
Tomi Valkeinen | 9ecd968 | 2010-04-30 11:24:33 +0300 | [diff] [blame] | 1812 | return -EIO; |
| 1813 | } |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1814 | |
| 1815 | REG_FLD_MOD(DSI_VC_CTRL(channel), 0, 1, 1); /* SOURCE, 0 = L4 */ |
| 1816 | |
| 1817 | dsi_vc_enable(channel, 1); |
| 1818 | |
| 1819 | dsi.vc[channel].mode = DSI_VC_MODE_L4; |
Tomi Valkeinen | 9ecd968 | 2010-04-30 11:24:33 +0300 | [diff] [blame] | 1820 | |
| 1821 | return 0; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1822 | } |
| 1823 | |
Tomi Valkeinen | 9ecd968 | 2010-04-30 11:24:33 +0300 | [diff] [blame] | 1824 | static int dsi_vc_config_vp(int channel) |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1825 | { |
| 1826 | if (dsi.vc[channel].mode == DSI_VC_MODE_VP) |
Tomi Valkeinen | 9ecd968 | 2010-04-30 11:24:33 +0300 | [diff] [blame] | 1827 | return 0; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1828 | |
| 1829 | DSSDBGF("%d", channel); |
| 1830 | |
| 1831 | dsi_vc_enable(channel, 0); |
| 1832 | |
Tomi Valkeinen | 9ecd968 | 2010-04-30 11:24:33 +0300 | [diff] [blame] | 1833 | /* VC_BUSY */ |
| 1834 | if (wait_for_bit_change(DSI_VC_CTRL(channel), 15, 0) != 0) { |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1835 | DSSERR("vc(%d) busy when trying to config for VP\n", channel); |
Tomi Valkeinen | 9ecd968 | 2010-04-30 11:24:33 +0300 | [diff] [blame] | 1836 | return -EIO; |
| 1837 | } |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1838 | |
| 1839 | REG_FLD_MOD(DSI_VC_CTRL(channel), 1, 1, 1); /* SOURCE, 1 = video port */ |
| 1840 | |
| 1841 | dsi_vc_enable(channel, 1); |
| 1842 | |
| 1843 | dsi.vc[channel].mode = DSI_VC_MODE_VP; |
Tomi Valkeinen | 9ecd968 | 2010-04-30 11:24:33 +0300 | [diff] [blame] | 1844 | |
| 1845 | return 0; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1846 | } |
| 1847 | |
| 1848 | |
Tomi Valkeinen | 61140c9 | 2010-01-12 16:00:30 +0200 | [diff] [blame] | 1849 | void omapdss_dsi_vc_enable_hs(int channel, bool enable) |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1850 | { |
| 1851 | DSSDBG("dsi_vc_enable_hs(%d, %d)\n", channel, enable); |
| 1852 | |
Tomi Valkeinen | 61140c9 | 2010-01-12 16:00:30 +0200 | [diff] [blame] | 1853 | WARN_ON(!dsi_bus_is_locked()); |
| 1854 | |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1855 | dsi_vc_enable(channel, 0); |
| 1856 | dsi_if_enable(0); |
| 1857 | |
| 1858 | REG_FLD_MOD(DSI_VC_CTRL(channel), enable, 9, 9); |
| 1859 | |
| 1860 | dsi_vc_enable(channel, 1); |
| 1861 | dsi_if_enable(1); |
| 1862 | |
| 1863 | dsi_force_tx_stop_mode_io(); |
| 1864 | } |
Tomi Valkeinen | 61140c9 | 2010-01-12 16:00:30 +0200 | [diff] [blame] | 1865 | EXPORT_SYMBOL(omapdss_dsi_vc_enable_hs); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1866 | |
| 1867 | static void dsi_vc_flush_long_data(int channel) |
| 1868 | { |
| 1869 | while (REG_GET(DSI_VC_CTRL(channel), 20, 20)) { |
| 1870 | u32 val; |
| 1871 | val = dsi_read_reg(DSI_VC_SHORT_PACKET_HEADER(channel)); |
| 1872 | DSSDBG("\t\tb1 %#02x b2 %#02x b3 %#02x b4 %#02x\n", |
| 1873 | (val >> 0) & 0xff, |
| 1874 | (val >> 8) & 0xff, |
| 1875 | (val >> 16) & 0xff, |
| 1876 | (val >> 24) & 0xff); |
| 1877 | } |
| 1878 | } |
| 1879 | |
| 1880 | static void dsi_show_rx_ack_with_err(u16 err) |
| 1881 | { |
| 1882 | DSSERR("\tACK with ERROR (%#x):\n", err); |
| 1883 | if (err & (1 << 0)) |
| 1884 | DSSERR("\t\tSoT Error\n"); |
| 1885 | if (err & (1 << 1)) |
| 1886 | DSSERR("\t\tSoT Sync Error\n"); |
| 1887 | if (err & (1 << 2)) |
| 1888 | DSSERR("\t\tEoT Sync Error\n"); |
| 1889 | if (err & (1 << 3)) |
| 1890 | DSSERR("\t\tEscape Mode Entry Command Error\n"); |
| 1891 | if (err & (1 << 4)) |
| 1892 | DSSERR("\t\tLP Transmit Sync Error\n"); |
| 1893 | if (err & (1 << 5)) |
| 1894 | DSSERR("\t\tHS Receive Timeout Error\n"); |
| 1895 | if (err & (1 << 6)) |
| 1896 | DSSERR("\t\tFalse Control Error\n"); |
| 1897 | if (err & (1 << 7)) |
| 1898 | DSSERR("\t\t(reserved7)\n"); |
| 1899 | if (err & (1 << 8)) |
| 1900 | DSSERR("\t\tECC Error, single-bit (corrected)\n"); |
| 1901 | if (err & (1 << 9)) |
| 1902 | DSSERR("\t\tECC Error, multi-bit (not corrected)\n"); |
| 1903 | if (err & (1 << 10)) |
| 1904 | DSSERR("\t\tChecksum Error\n"); |
| 1905 | if (err & (1 << 11)) |
| 1906 | DSSERR("\t\tData type not recognized\n"); |
| 1907 | if (err & (1 << 12)) |
| 1908 | DSSERR("\t\tInvalid VC ID\n"); |
| 1909 | if (err & (1 << 13)) |
| 1910 | DSSERR("\t\tInvalid Transmission Length\n"); |
| 1911 | if (err & (1 << 14)) |
| 1912 | DSSERR("\t\t(reserved14)\n"); |
| 1913 | if (err & (1 << 15)) |
| 1914 | DSSERR("\t\tDSI Protocol Violation\n"); |
| 1915 | } |
| 1916 | |
| 1917 | static u16 dsi_vc_flush_receive_data(int channel) |
| 1918 | { |
| 1919 | /* RX_FIFO_NOT_EMPTY */ |
| 1920 | while (REG_GET(DSI_VC_CTRL(channel), 20, 20)) { |
| 1921 | u32 val; |
| 1922 | u8 dt; |
| 1923 | val = dsi_read_reg(DSI_VC_SHORT_PACKET_HEADER(channel)); |
Tomi Valkeinen | 86a7867 | 2010-03-16 16:19:06 +0200 | [diff] [blame] | 1924 | DSSERR("\trawval %#08x\n", val); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1925 | dt = FLD_GET(val, 5, 0); |
| 1926 | if (dt == DSI_DT_RX_ACK_WITH_ERR) { |
| 1927 | u16 err = FLD_GET(val, 23, 8); |
| 1928 | dsi_show_rx_ack_with_err(err); |
| 1929 | } else if (dt == DSI_DT_RX_SHORT_READ_1) { |
Tomi Valkeinen | 86a7867 | 2010-03-16 16:19:06 +0200 | [diff] [blame] | 1930 | DSSERR("\tDCS short response, 1 byte: %#x\n", |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1931 | FLD_GET(val, 23, 8)); |
| 1932 | } else if (dt == DSI_DT_RX_SHORT_READ_2) { |
Tomi Valkeinen | 86a7867 | 2010-03-16 16:19:06 +0200 | [diff] [blame] | 1933 | DSSERR("\tDCS short response, 2 byte: %#x\n", |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1934 | FLD_GET(val, 23, 8)); |
| 1935 | } else if (dt == DSI_DT_RX_DCS_LONG_READ) { |
Tomi Valkeinen | 86a7867 | 2010-03-16 16:19:06 +0200 | [diff] [blame] | 1936 | DSSERR("\tDCS long response, len %d\n", |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1937 | FLD_GET(val, 23, 8)); |
| 1938 | dsi_vc_flush_long_data(channel); |
| 1939 | } else { |
| 1940 | DSSERR("\tunknown datatype 0x%02x\n", dt); |
| 1941 | } |
| 1942 | } |
| 1943 | return 0; |
| 1944 | } |
| 1945 | |
| 1946 | static int dsi_vc_send_bta(int channel) |
| 1947 | { |
Tomi Valkeinen | 446f7bf | 2010-01-11 16:12:31 +0200 | [diff] [blame] | 1948 | if (dsi.debug_write || dsi.debug_read) |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1949 | DSSDBG("dsi_vc_send_bta %d\n", channel); |
| 1950 | |
Tomi Valkeinen | 4f76502 | 2010-01-18 16:27:52 +0200 | [diff] [blame] | 1951 | WARN_ON(!dsi_bus_is_locked()); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1952 | |
| 1953 | if (REG_GET(DSI_VC_CTRL(channel), 20, 20)) { /* RX_FIFO_NOT_EMPTY */ |
| 1954 | DSSERR("rx fifo not empty when sending BTA, dumping data:\n"); |
| 1955 | dsi_vc_flush_receive_data(channel); |
| 1956 | } |
| 1957 | |
| 1958 | REG_FLD_MOD(DSI_VC_CTRL(channel), 1, 6, 6); /* BTA_EN */ |
| 1959 | |
| 1960 | return 0; |
| 1961 | } |
| 1962 | |
| 1963 | int dsi_vc_send_bta_sync(int channel) |
| 1964 | { |
| 1965 | int r = 0; |
| 1966 | u32 err; |
| 1967 | |
| 1968 | INIT_COMPLETION(dsi.bta_completion); |
| 1969 | |
| 1970 | dsi_vc_enable_bta_irq(channel); |
| 1971 | |
| 1972 | r = dsi_vc_send_bta(channel); |
| 1973 | if (r) |
| 1974 | goto err; |
| 1975 | |
| 1976 | if (wait_for_completion_timeout(&dsi.bta_completion, |
| 1977 | msecs_to_jiffies(500)) == 0) { |
| 1978 | DSSERR("Failed to receive BTA\n"); |
| 1979 | r = -EIO; |
| 1980 | goto err; |
| 1981 | } |
| 1982 | |
| 1983 | err = dsi_get_errors(); |
| 1984 | if (err) { |
| 1985 | DSSERR("Error while sending BTA: %x\n", err); |
| 1986 | r = -EIO; |
| 1987 | goto err; |
| 1988 | } |
| 1989 | err: |
| 1990 | dsi_vc_disable_bta_irq(channel); |
| 1991 | |
| 1992 | return r; |
| 1993 | } |
| 1994 | EXPORT_SYMBOL(dsi_vc_send_bta_sync); |
| 1995 | |
| 1996 | static inline void dsi_vc_write_long_header(int channel, u8 data_type, |
| 1997 | u16 len, u8 ecc) |
| 1998 | { |
| 1999 | u32 val; |
| 2000 | u8 data_id; |
| 2001 | |
Tomi Valkeinen | 4f76502 | 2010-01-18 16:27:52 +0200 | [diff] [blame] | 2002 | WARN_ON(!dsi_bus_is_locked()); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2003 | |
Archit Taneja | 5ee3c14 | 2011-03-02 12:35:53 +0530 | [diff] [blame] | 2004 | data_id = data_type | dsi.vc[channel].vc_id << 6; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2005 | |
| 2006 | val = FLD_VAL(data_id, 7, 0) | FLD_VAL(len, 23, 8) | |
| 2007 | FLD_VAL(ecc, 31, 24); |
| 2008 | |
| 2009 | dsi_write_reg(DSI_VC_LONG_PACKET_HEADER(channel), val); |
| 2010 | } |
| 2011 | |
| 2012 | static inline void dsi_vc_write_long_payload(int channel, |
| 2013 | u8 b1, u8 b2, u8 b3, u8 b4) |
| 2014 | { |
| 2015 | u32 val; |
| 2016 | |
| 2017 | val = b4 << 24 | b3 << 16 | b2 << 8 | b1 << 0; |
| 2018 | |
| 2019 | /* DSSDBG("\twriting %02x, %02x, %02x, %02x (%#010x)\n", |
| 2020 | b1, b2, b3, b4, val); */ |
| 2021 | |
| 2022 | dsi_write_reg(DSI_VC_LONG_PACKET_PAYLOAD(channel), val); |
| 2023 | } |
| 2024 | |
| 2025 | static int dsi_vc_send_long(int channel, u8 data_type, u8 *data, u16 len, |
| 2026 | u8 ecc) |
| 2027 | { |
| 2028 | /*u32 val; */ |
| 2029 | int i; |
| 2030 | u8 *p; |
| 2031 | int r = 0; |
| 2032 | u8 b1, b2, b3, b4; |
| 2033 | |
| 2034 | if (dsi.debug_write) |
| 2035 | DSSDBG("dsi_vc_send_long, %d bytes\n", len); |
| 2036 | |
| 2037 | /* len + header */ |
| 2038 | if (dsi.vc[channel].fifo_size * 32 * 4 < len + 4) { |
| 2039 | DSSERR("unable to send long packet: packet too long.\n"); |
| 2040 | return -EINVAL; |
| 2041 | } |
| 2042 | |
| 2043 | dsi_vc_config_l4(channel); |
| 2044 | |
| 2045 | dsi_vc_write_long_header(channel, data_type, len, ecc); |
| 2046 | |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2047 | p = data; |
| 2048 | for (i = 0; i < len >> 2; i++) { |
| 2049 | if (dsi.debug_write) |
| 2050 | DSSDBG("\tsending full packet %d\n", i); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2051 | |
| 2052 | b1 = *p++; |
| 2053 | b2 = *p++; |
| 2054 | b3 = *p++; |
| 2055 | b4 = *p++; |
| 2056 | |
| 2057 | dsi_vc_write_long_payload(channel, b1, b2, b3, b4); |
| 2058 | } |
| 2059 | |
| 2060 | i = len % 4; |
| 2061 | if (i) { |
| 2062 | b1 = 0; b2 = 0; b3 = 0; |
| 2063 | |
| 2064 | if (dsi.debug_write) |
| 2065 | DSSDBG("\tsending remainder bytes %d\n", i); |
| 2066 | |
| 2067 | switch (i) { |
| 2068 | case 3: |
| 2069 | b1 = *p++; |
| 2070 | b2 = *p++; |
| 2071 | b3 = *p++; |
| 2072 | break; |
| 2073 | case 2: |
| 2074 | b1 = *p++; |
| 2075 | b2 = *p++; |
| 2076 | break; |
| 2077 | case 1: |
| 2078 | b1 = *p++; |
| 2079 | break; |
| 2080 | } |
| 2081 | |
| 2082 | dsi_vc_write_long_payload(channel, b1, b2, b3, 0); |
| 2083 | } |
| 2084 | |
| 2085 | return r; |
| 2086 | } |
| 2087 | |
| 2088 | static int dsi_vc_send_short(int channel, u8 data_type, u16 data, u8 ecc) |
| 2089 | { |
| 2090 | u32 r; |
| 2091 | u8 data_id; |
| 2092 | |
Tomi Valkeinen | 4f76502 | 2010-01-18 16:27:52 +0200 | [diff] [blame] | 2093 | WARN_ON(!dsi_bus_is_locked()); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2094 | |
| 2095 | if (dsi.debug_write) |
| 2096 | DSSDBG("dsi_vc_send_short(ch%d, dt %#x, b1 %#x, b2 %#x)\n", |
| 2097 | channel, |
| 2098 | data_type, data & 0xff, (data >> 8) & 0xff); |
| 2099 | |
| 2100 | dsi_vc_config_l4(channel); |
| 2101 | |
| 2102 | if (FLD_GET(dsi_read_reg(DSI_VC_CTRL(channel)), 16, 16)) { |
| 2103 | DSSERR("ERROR FIFO FULL, aborting transfer\n"); |
| 2104 | return -EINVAL; |
| 2105 | } |
| 2106 | |
Archit Taneja | 5ee3c14 | 2011-03-02 12:35:53 +0530 | [diff] [blame] | 2107 | data_id = data_type | dsi.vc[channel].vc_id << 6; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2108 | |
| 2109 | r = (data_id << 0) | (data << 8) | (ecc << 24); |
| 2110 | |
| 2111 | dsi_write_reg(DSI_VC_SHORT_PACKET_HEADER(channel), r); |
| 2112 | |
| 2113 | return 0; |
| 2114 | } |
| 2115 | |
| 2116 | int dsi_vc_send_null(int channel) |
| 2117 | { |
| 2118 | u8 nullpkg[] = {0, 0, 0, 0}; |
Tomi Valkeinen | 397bb3c | 2009-12-03 13:37:31 +0200 | [diff] [blame] | 2119 | return dsi_vc_send_long(channel, DSI_DT_NULL_PACKET, nullpkg, 4, 0); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2120 | } |
| 2121 | EXPORT_SYMBOL(dsi_vc_send_null); |
| 2122 | |
| 2123 | int dsi_vc_dcs_write_nosync(int channel, u8 *data, int len) |
| 2124 | { |
| 2125 | int r; |
| 2126 | |
| 2127 | BUG_ON(len == 0); |
| 2128 | |
| 2129 | if (len == 1) { |
| 2130 | r = dsi_vc_send_short(channel, DSI_DT_DCS_SHORT_WRITE_0, |
| 2131 | data[0], 0); |
| 2132 | } else if (len == 2) { |
| 2133 | r = dsi_vc_send_short(channel, DSI_DT_DCS_SHORT_WRITE_1, |
| 2134 | data[0] | (data[1] << 8), 0); |
| 2135 | } else { |
| 2136 | /* 0x39 = DCS Long Write */ |
| 2137 | r = dsi_vc_send_long(channel, DSI_DT_DCS_LONG_WRITE, |
| 2138 | data, len, 0); |
| 2139 | } |
| 2140 | |
| 2141 | return r; |
| 2142 | } |
| 2143 | EXPORT_SYMBOL(dsi_vc_dcs_write_nosync); |
| 2144 | |
| 2145 | int dsi_vc_dcs_write(int channel, u8 *data, int len) |
| 2146 | { |
| 2147 | int r; |
| 2148 | |
| 2149 | r = dsi_vc_dcs_write_nosync(channel, data, len); |
| 2150 | if (r) |
Tomi Valkeinen | 5d68e03 | 2010-02-26 11:32:56 +0200 | [diff] [blame] | 2151 | goto err; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2152 | |
| 2153 | r = dsi_vc_send_bta_sync(channel); |
Tomi Valkeinen | 5d68e03 | 2010-02-26 11:32:56 +0200 | [diff] [blame] | 2154 | if (r) |
| 2155 | goto err; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2156 | |
Tomi Valkeinen | b63ac1e | 2010-04-09 13:20:57 +0300 | [diff] [blame] | 2157 | if (REG_GET(DSI_VC_CTRL(channel), 20, 20)) { /* RX_FIFO_NOT_EMPTY */ |
| 2158 | DSSERR("rx fifo not empty after write, dumping data:\n"); |
| 2159 | dsi_vc_flush_receive_data(channel); |
| 2160 | r = -EIO; |
| 2161 | goto err; |
| 2162 | } |
| 2163 | |
Tomi Valkeinen | 5d68e03 | 2010-02-26 11:32:56 +0200 | [diff] [blame] | 2164 | return 0; |
| 2165 | err: |
| 2166 | DSSERR("dsi_vc_dcs_write(ch %d, cmd 0x%02x, len %d) failed\n", |
| 2167 | channel, data[0], len); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2168 | return r; |
| 2169 | } |
| 2170 | EXPORT_SYMBOL(dsi_vc_dcs_write); |
| 2171 | |
Tomi Valkeinen | 828c48f | 2009-12-16 14:53:15 +0200 | [diff] [blame] | 2172 | int dsi_vc_dcs_write_0(int channel, u8 dcs_cmd) |
| 2173 | { |
| 2174 | return dsi_vc_dcs_write(channel, &dcs_cmd, 1); |
| 2175 | } |
| 2176 | EXPORT_SYMBOL(dsi_vc_dcs_write_0); |
| 2177 | |
| 2178 | int dsi_vc_dcs_write_1(int channel, u8 dcs_cmd, u8 param) |
| 2179 | { |
| 2180 | u8 buf[2]; |
| 2181 | buf[0] = dcs_cmd; |
| 2182 | buf[1] = param; |
| 2183 | return dsi_vc_dcs_write(channel, buf, 2); |
| 2184 | } |
| 2185 | EXPORT_SYMBOL(dsi_vc_dcs_write_1); |
| 2186 | |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2187 | int dsi_vc_dcs_read(int channel, u8 dcs_cmd, u8 *buf, int buflen) |
| 2188 | { |
| 2189 | u32 val; |
| 2190 | u8 dt; |
| 2191 | int r; |
| 2192 | |
| 2193 | if (dsi.debug_read) |
Tomi Valkeinen | ff90a34 | 2009-12-03 13:38:04 +0200 | [diff] [blame] | 2194 | DSSDBG("dsi_vc_dcs_read(ch%d, dcs_cmd %x)\n", channel, dcs_cmd); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2195 | |
| 2196 | r = dsi_vc_send_short(channel, DSI_DT_DCS_READ, dcs_cmd, 0); |
| 2197 | if (r) |
Tomi Valkeinen | 5d68e03 | 2010-02-26 11:32:56 +0200 | [diff] [blame] | 2198 | goto err; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2199 | |
| 2200 | r = dsi_vc_send_bta_sync(channel); |
| 2201 | if (r) |
Tomi Valkeinen | 5d68e03 | 2010-02-26 11:32:56 +0200 | [diff] [blame] | 2202 | goto err; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2203 | |
| 2204 | /* RX_FIFO_NOT_EMPTY */ |
| 2205 | if (REG_GET(DSI_VC_CTRL(channel), 20, 20) == 0) { |
| 2206 | DSSERR("RX fifo empty when trying to read.\n"); |
Tomi Valkeinen | 5d68e03 | 2010-02-26 11:32:56 +0200 | [diff] [blame] | 2207 | r = -EIO; |
| 2208 | goto err; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2209 | } |
| 2210 | |
| 2211 | val = dsi_read_reg(DSI_VC_SHORT_PACKET_HEADER(channel)); |
| 2212 | if (dsi.debug_read) |
| 2213 | DSSDBG("\theader: %08x\n", val); |
| 2214 | dt = FLD_GET(val, 5, 0); |
| 2215 | if (dt == DSI_DT_RX_ACK_WITH_ERR) { |
| 2216 | u16 err = FLD_GET(val, 23, 8); |
| 2217 | dsi_show_rx_ack_with_err(err); |
Tomi Valkeinen | 5d68e03 | 2010-02-26 11:32:56 +0200 | [diff] [blame] | 2218 | r = -EIO; |
| 2219 | goto err; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2220 | |
| 2221 | } else if (dt == DSI_DT_RX_SHORT_READ_1) { |
| 2222 | u8 data = FLD_GET(val, 15, 8); |
| 2223 | if (dsi.debug_read) |
| 2224 | DSSDBG("\tDCS short response, 1 byte: %02x\n", data); |
| 2225 | |
Tomi Valkeinen | 5d68e03 | 2010-02-26 11:32:56 +0200 | [diff] [blame] | 2226 | if (buflen < 1) { |
| 2227 | r = -EIO; |
| 2228 | goto err; |
| 2229 | } |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2230 | |
| 2231 | buf[0] = data; |
| 2232 | |
| 2233 | return 1; |
| 2234 | } else if (dt == DSI_DT_RX_SHORT_READ_2) { |
| 2235 | u16 data = FLD_GET(val, 23, 8); |
| 2236 | if (dsi.debug_read) |
| 2237 | DSSDBG("\tDCS short response, 2 byte: %04x\n", data); |
| 2238 | |
Tomi Valkeinen | 5d68e03 | 2010-02-26 11:32:56 +0200 | [diff] [blame] | 2239 | if (buflen < 2) { |
| 2240 | r = -EIO; |
| 2241 | goto err; |
| 2242 | } |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2243 | |
| 2244 | buf[0] = data & 0xff; |
| 2245 | buf[1] = (data >> 8) & 0xff; |
| 2246 | |
| 2247 | return 2; |
| 2248 | } else if (dt == DSI_DT_RX_DCS_LONG_READ) { |
| 2249 | int w; |
| 2250 | int len = FLD_GET(val, 23, 8); |
| 2251 | if (dsi.debug_read) |
| 2252 | DSSDBG("\tDCS long response, len %d\n", len); |
| 2253 | |
Tomi Valkeinen | 5d68e03 | 2010-02-26 11:32:56 +0200 | [diff] [blame] | 2254 | if (len > buflen) { |
| 2255 | r = -EIO; |
| 2256 | goto err; |
| 2257 | } |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2258 | |
| 2259 | /* two byte checksum ends the packet, not included in len */ |
| 2260 | for (w = 0; w < len + 2;) { |
| 2261 | int b; |
| 2262 | val = dsi_read_reg(DSI_VC_SHORT_PACKET_HEADER(channel)); |
| 2263 | if (dsi.debug_read) |
| 2264 | DSSDBG("\t\t%02x %02x %02x %02x\n", |
| 2265 | (val >> 0) & 0xff, |
| 2266 | (val >> 8) & 0xff, |
| 2267 | (val >> 16) & 0xff, |
| 2268 | (val >> 24) & 0xff); |
| 2269 | |
| 2270 | for (b = 0; b < 4; ++b) { |
| 2271 | if (w < len) |
| 2272 | buf[w] = (val >> (b * 8)) & 0xff; |
| 2273 | /* we discard the 2 byte checksum */ |
| 2274 | ++w; |
| 2275 | } |
| 2276 | } |
| 2277 | |
| 2278 | return len; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2279 | } else { |
| 2280 | DSSERR("\tunknown datatype 0x%02x\n", dt); |
Tomi Valkeinen | 5d68e03 | 2010-02-26 11:32:56 +0200 | [diff] [blame] | 2281 | r = -EIO; |
| 2282 | goto err; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2283 | } |
Tomi Valkeinen | 5d68e03 | 2010-02-26 11:32:56 +0200 | [diff] [blame] | 2284 | |
| 2285 | BUG(); |
| 2286 | err: |
| 2287 | DSSERR("dsi_vc_dcs_read(ch %d, cmd 0x%02x) failed\n", |
| 2288 | channel, dcs_cmd); |
| 2289 | return r; |
| 2290 | |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2291 | } |
| 2292 | EXPORT_SYMBOL(dsi_vc_dcs_read); |
| 2293 | |
Tomi Valkeinen | 828c48f | 2009-12-16 14:53:15 +0200 | [diff] [blame] | 2294 | int dsi_vc_dcs_read_1(int channel, u8 dcs_cmd, u8 *data) |
| 2295 | { |
| 2296 | int r; |
| 2297 | |
| 2298 | r = dsi_vc_dcs_read(channel, dcs_cmd, data, 1); |
| 2299 | |
| 2300 | if (r < 0) |
| 2301 | return r; |
| 2302 | |
| 2303 | if (r != 1) |
| 2304 | return -EIO; |
| 2305 | |
| 2306 | return 0; |
| 2307 | } |
| 2308 | EXPORT_SYMBOL(dsi_vc_dcs_read_1); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2309 | |
Tomi Valkeinen | 0c244f7 | 2010-06-09 15:19:29 +0300 | [diff] [blame] | 2310 | int dsi_vc_dcs_read_2(int channel, u8 dcs_cmd, u8 *data1, u8 *data2) |
Tomi Valkeinen | 53055aa | 2010-02-25 11:38:13 +0200 | [diff] [blame] | 2311 | { |
Tomi Valkeinen | 0c244f7 | 2010-06-09 15:19:29 +0300 | [diff] [blame] | 2312 | u8 buf[2]; |
Tomi Valkeinen | 53055aa | 2010-02-25 11:38:13 +0200 | [diff] [blame] | 2313 | int r; |
| 2314 | |
Tomi Valkeinen | 0c244f7 | 2010-06-09 15:19:29 +0300 | [diff] [blame] | 2315 | r = dsi_vc_dcs_read(channel, dcs_cmd, buf, 2); |
Tomi Valkeinen | 53055aa | 2010-02-25 11:38:13 +0200 | [diff] [blame] | 2316 | |
| 2317 | if (r < 0) |
| 2318 | return r; |
| 2319 | |
| 2320 | if (r != 2) |
| 2321 | return -EIO; |
| 2322 | |
Tomi Valkeinen | 0c244f7 | 2010-06-09 15:19:29 +0300 | [diff] [blame] | 2323 | *data1 = buf[0]; |
| 2324 | *data2 = buf[1]; |
| 2325 | |
Tomi Valkeinen | 53055aa | 2010-02-25 11:38:13 +0200 | [diff] [blame] | 2326 | return 0; |
| 2327 | } |
| 2328 | EXPORT_SYMBOL(dsi_vc_dcs_read_2); |
| 2329 | |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2330 | int dsi_vc_set_max_rx_packet_size(int channel, u16 len) |
| 2331 | { |
Tomi Valkeinen | fa15c79 | 2010-05-14 17:42:07 +0300 | [diff] [blame] | 2332 | return dsi_vc_send_short(channel, DSI_DT_SET_MAX_RET_PKG_SIZE, |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2333 | len, 0); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2334 | } |
| 2335 | EXPORT_SYMBOL(dsi_vc_set_max_rx_packet_size); |
| 2336 | |
Tomi Valkeinen | 4ffa357 | 2010-04-12 10:40:12 +0300 | [diff] [blame] | 2337 | static void dsi_set_lp_rx_timeout(unsigned ticks, bool x4, bool x16) |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2338 | { |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2339 | unsigned long fck; |
Tomi Valkeinen | 4ffa357 | 2010-04-12 10:40:12 +0300 | [diff] [blame] | 2340 | unsigned long total_ticks; |
| 2341 | u32 r; |
| 2342 | |
| 2343 | BUG_ON(ticks > 0x1fff); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2344 | |
| 2345 | /* ticks in DSI_FCK */ |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2346 | fck = dsi_fclk_rate(); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2347 | |
| 2348 | r = dsi_read_reg(DSI_TIMING2); |
| 2349 | r = FLD_MOD(r, 1, 15, 15); /* LP_RX_TO */ |
Tomi Valkeinen | 4ffa357 | 2010-04-12 10:40:12 +0300 | [diff] [blame] | 2350 | r = FLD_MOD(r, x16 ? 1 : 0, 14, 14); /* LP_RX_TO_X16 */ |
| 2351 | r = FLD_MOD(r, x4 ? 1 : 0, 13, 13); /* LP_RX_TO_X4 */ |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2352 | r = FLD_MOD(r, ticks, 12, 0); /* LP_RX_COUNTER */ |
| 2353 | dsi_write_reg(DSI_TIMING2, r); |
| 2354 | |
Tomi Valkeinen | 4ffa357 | 2010-04-12 10:40:12 +0300 | [diff] [blame] | 2355 | total_ticks = ticks * (x16 ? 16 : 1) * (x4 ? 4 : 1); |
| 2356 | |
| 2357 | DSSDBG("LP_RX_TO %lu ticks (%#x%s%s) = %lu ns\n", |
| 2358 | total_ticks, |
| 2359 | ticks, x4 ? " x4" : "", x16 ? " x16" : "", |
| 2360 | (total_ticks * 1000) / (fck / 1000 / 1000)); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2361 | } |
| 2362 | |
Tomi Valkeinen | 4ffa357 | 2010-04-12 10:40:12 +0300 | [diff] [blame] | 2363 | static void dsi_set_ta_timeout(unsigned ticks, bool x8, bool x16) |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2364 | { |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2365 | unsigned long fck; |
Tomi Valkeinen | 4ffa357 | 2010-04-12 10:40:12 +0300 | [diff] [blame] | 2366 | unsigned long total_ticks; |
| 2367 | u32 r; |
| 2368 | |
| 2369 | BUG_ON(ticks > 0x1fff); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2370 | |
| 2371 | /* ticks in DSI_FCK */ |
| 2372 | fck = dsi_fclk_rate(); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2373 | |
| 2374 | r = dsi_read_reg(DSI_TIMING1); |
| 2375 | r = FLD_MOD(r, 1, 31, 31); /* TA_TO */ |
Tomi Valkeinen | 4ffa357 | 2010-04-12 10:40:12 +0300 | [diff] [blame] | 2376 | r = FLD_MOD(r, x16 ? 1 : 0, 30, 30); /* TA_TO_X16 */ |
| 2377 | r = FLD_MOD(r, x8 ? 1 : 0, 29, 29); /* TA_TO_X8 */ |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2378 | r = FLD_MOD(r, ticks, 28, 16); /* TA_TO_COUNTER */ |
| 2379 | dsi_write_reg(DSI_TIMING1, r); |
| 2380 | |
Tomi Valkeinen | 4ffa357 | 2010-04-12 10:40:12 +0300 | [diff] [blame] | 2381 | total_ticks = ticks * (x16 ? 16 : 1) * (x8 ? 8 : 1); |
| 2382 | |
| 2383 | DSSDBG("TA_TO %lu ticks (%#x%s%s) = %lu ns\n", |
| 2384 | total_ticks, |
| 2385 | ticks, x8 ? " x8" : "", x16 ? " x16" : "", |
| 2386 | (total_ticks * 1000) / (fck / 1000 / 1000)); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2387 | } |
| 2388 | |
Tomi Valkeinen | 4ffa357 | 2010-04-12 10:40:12 +0300 | [diff] [blame] | 2389 | static void dsi_set_stop_state_counter(unsigned ticks, bool x4, bool x16) |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2390 | { |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2391 | unsigned long fck; |
Tomi Valkeinen | 4ffa357 | 2010-04-12 10:40:12 +0300 | [diff] [blame] | 2392 | unsigned long total_ticks; |
| 2393 | u32 r; |
| 2394 | |
| 2395 | BUG_ON(ticks > 0x1fff); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2396 | |
| 2397 | /* ticks in DSI_FCK */ |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2398 | fck = dsi_fclk_rate(); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2399 | |
| 2400 | r = dsi_read_reg(DSI_TIMING1); |
| 2401 | r = FLD_MOD(r, 1, 15, 15); /* FORCE_TX_STOP_MODE_IO */ |
Tomi Valkeinen | 4ffa357 | 2010-04-12 10:40:12 +0300 | [diff] [blame] | 2402 | r = FLD_MOD(r, x16 ? 1 : 0, 14, 14); /* STOP_STATE_X16_IO */ |
| 2403 | r = FLD_MOD(r, x4 ? 1 : 0, 13, 13); /* STOP_STATE_X4_IO */ |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2404 | r = FLD_MOD(r, ticks, 12, 0); /* STOP_STATE_COUNTER_IO */ |
| 2405 | dsi_write_reg(DSI_TIMING1, r); |
| 2406 | |
Tomi Valkeinen | 4ffa357 | 2010-04-12 10:40:12 +0300 | [diff] [blame] | 2407 | total_ticks = ticks * (x16 ? 16 : 1) * (x4 ? 4 : 1); |
| 2408 | |
| 2409 | DSSDBG("STOP_STATE_COUNTER %lu ticks (%#x%s%s) = %lu ns\n", |
| 2410 | total_ticks, |
| 2411 | ticks, x4 ? " x4" : "", x16 ? " x16" : "", |
| 2412 | (total_ticks * 1000) / (fck / 1000 / 1000)); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2413 | } |
| 2414 | |
Tomi Valkeinen | 4ffa357 | 2010-04-12 10:40:12 +0300 | [diff] [blame] | 2415 | static void dsi_set_hs_tx_timeout(unsigned ticks, bool x4, bool x16) |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2416 | { |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2417 | unsigned long fck; |
Tomi Valkeinen | 4ffa357 | 2010-04-12 10:40:12 +0300 | [diff] [blame] | 2418 | unsigned long total_ticks; |
| 2419 | u32 r; |
| 2420 | |
| 2421 | BUG_ON(ticks > 0x1fff); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2422 | |
| 2423 | /* ticks in TxByteClkHS */ |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2424 | fck = dsi_get_txbyteclkhs(); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2425 | |
| 2426 | r = dsi_read_reg(DSI_TIMING2); |
| 2427 | r = FLD_MOD(r, 1, 31, 31); /* HS_TX_TO */ |
Tomi Valkeinen | 4ffa357 | 2010-04-12 10:40:12 +0300 | [diff] [blame] | 2428 | r = FLD_MOD(r, x16 ? 1 : 0, 30, 30); /* HS_TX_TO_X16 */ |
| 2429 | r = FLD_MOD(r, x4 ? 1 : 0, 29, 29); /* HS_TX_TO_X8 (4 really) */ |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2430 | r = FLD_MOD(r, ticks, 28, 16); /* HS_TX_TO_COUNTER */ |
| 2431 | dsi_write_reg(DSI_TIMING2, r); |
| 2432 | |
Tomi Valkeinen | 4ffa357 | 2010-04-12 10:40:12 +0300 | [diff] [blame] | 2433 | total_ticks = ticks * (x16 ? 16 : 1) * (x4 ? 4 : 1); |
| 2434 | |
| 2435 | DSSDBG("HS_TX_TO %lu ticks (%#x%s%s) = %lu ns\n", |
| 2436 | total_ticks, |
| 2437 | ticks, x4 ? " x4" : "", x16 ? " x16" : "", |
| 2438 | (total_ticks * 1000) / (fck / 1000 / 1000)); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2439 | } |
| 2440 | static int dsi_proto_config(struct omap_dss_device *dssdev) |
| 2441 | { |
| 2442 | u32 r; |
| 2443 | int buswidth = 0; |
| 2444 | |
Tomi Valkeinen | dd8079d | 2009-12-16 16:49:03 +0200 | [diff] [blame] | 2445 | dsi_config_tx_fifo(DSI_FIFO_SIZE_32, |
| 2446 | DSI_FIFO_SIZE_32, |
| 2447 | DSI_FIFO_SIZE_32, |
| 2448 | DSI_FIFO_SIZE_32); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2449 | |
Tomi Valkeinen | dd8079d | 2009-12-16 16:49:03 +0200 | [diff] [blame] | 2450 | dsi_config_rx_fifo(DSI_FIFO_SIZE_32, |
| 2451 | DSI_FIFO_SIZE_32, |
| 2452 | DSI_FIFO_SIZE_32, |
| 2453 | DSI_FIFO_SIZE_32); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2454 | |
| 2455 | /* XXX what values for the timeouts? */ |
Tomi Valkeinen | 4ffa357 | 2010-04-12 10:40:12 +0300 | [diff] [blame] | 2456 | dsi_set_stop_state_counter(0x1000, false, false); |
| 2457 | dsi_set_ta_timeout(0x1fff, true, true); |
| 2458 | dsi_set_lp_rx_timeout(0x1fff, true, true); |
| 2459 | dsi_set_hs_tx_timeout(0x1fff, true, true); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2460 | |
| 2461 | switch (dssdev->ctrl.pixel_size) { |
| 2462 | case 16: |
| 2463 | buswidth = 0; |
| 2464 | break; |
| 2465 | case 18: |
| 2466 | buswidth = 1; |
| 2467 | break; |
| 2468 | case 24: |
| 2469 | buswidth = 2; |
| 2470 | break; |
| 2471 | default: |
| 2472 | BUG(); |
| 2473 | } |
| 2474 | |
| 2475 | r = dsi_read_reg(DSI_CTRL); |
| 2476 | r = FLD_MOD(r, 1, 1, 1); /* CS_RX_EN */ |
| 2477 | r = FLD_MOD(r, 1, 2, 2); /* ECC_RX_EN */ |
| 2478 | r = FLD_MOD(r, 1, 3, 3); /* TX_FIFO_ARBITRATION */ |
| 2479 | r = FLD_MOD(r, 1, 4, 4); /* VP_CLK_RATIO, always 1, see errata*/ |
| 2480 | r = FLD_MOD(r, buswidth, 7, 6); /* VP_DATA_BUS_WIDTH */ |
| 2481 | r = FLD_MOD(r, 0, 8, 8); /* VP_CLK_POL */ |
| 2482 | r = FLD_MOD(r, 2, 13, 12); /* LINE_BUFFER, 2 lines */ |
| 2483 | r = FLD_MOD(r, 1, 14, 14); /* TRIGGER_RESET_MODE */ |
| 2484 | r = FLD_MOD(r, 1, 19, 19); /* EOT_ENABLE */ |
| 2485 | r = FLD_MOD(r, 1, 24, 24); /* DCS_CMD_ENABLE */ |
| 2486 | r = FLD_MOD(r, 0, 25, 25); /* DCS_CMD_CODE, 1=start, 0=continue */ |
| 2487 | |
| 2488 | dsi_write_reg(DSI_CTRL, r); |
| 2489 | |
| 2490 | dsi_vc_initial_config(0); |
Tomi Valkeinen | dd8079d | 2009-12-16 16:49:03 +0200 | [diff] [blame] | 2491 | dsi_vc_initial_config(1); |
| 2492 | dsi_vc_initial_config(2); |
| 2493 | dsi_vc_initial_config(3); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2494 | |
| 2495 | return 0; |
| 2496 | } |
| 2497 | |
| 2498 | static void dsi_proto_timings(struct omap_dss_device *dssdev) |
| 2499 | { |
| 2500 | unsigned tlpx, tclk_zero, tclk_prepare, tclk_trail; |
| 2501 | unsigned tclk_pre, tclk_post; |
| 2502 | unsigned ths_prepare, ths_prepare_ths_zero, ths_zero; |
| 2503 | unsigned ths_trail, ths_exit; |
| 2504 | unsigned ddr_clk_pre, ddr_clk_post; |
| 2505 | unsigned enter_hs_mode_lat, exit_hs_mode_lat; |
| 2506 | unsigned ths_eot; |
| 2507 | u32 r; |
| 2508 | |
| 2509 | r = dsi_read_reg(DSI_DSIPHY_CFG0); |
| 2510 | ths_prepare = FLD_GET(r, 31, 24); |
| 2511 | ths_prepare_ths_zero = FLD_GET(r, 23, 16); |
| 2512 | ths_zero = ths_prepare_ths_zero - ths_prepare; |
| 2513 | ths_trail = FLD_GET(r, 15, 8); |
| 2514 | ths_exit = FLD_GET(r, 7, 0); |
| 2515 | |
| 2516 | r = dsi_read_reg(DSI_DSIPHY_CFG1); |
| 2517 | tlpx = FLD_GET(r, 22, 16) * 2; |
| 2518 | tclk_trail = FLD_GET(r, 15, 8); |
| 2519 | tclk_zero = FLD_GET(r, 7, 0); |
| 2520 | |
| 2521 | r = dsi_read_reg(DSI_DSIPHY_CFG2); |
| 2522 | tclk_prepare = FLD_GET(r, 7, 0); |
| 2523 | |
| 2524 | /* min 8*UI */ |
| 2525 | tclk_pre = 20; |
| 2526 | /* min 60ns + 52*UI */ |
| 2527 | tclk_post = ns2ddr(60) + 26; |
| 2528 | |
| 2529 | /* ths_eot is 2 for 2 datalanes and 4 for 1 datalane */ |
| 2530 | if (dssdev->phy.dsi.data1_lane != 0 && |
| 2531 | dssdev->phy.dsi.data2_lane != 0) |
| 2532 | ths_eot = 2; |
| 2533 | else |
| 2534 | ths_eot = 4; |
| 2535 | |
| 2536 | ddr_clk_pre = DIV_ROUND_UP(tclk_pre + tlpx + tclk_zero + tclk_prepare, |
| 2537 | 4); |
| 2538 | ddr_clk_post = DIV_ROUND_UP(tclk_post + ths_trail, 4) + ths_eot; |
| 2539 | |
| 2540 | BUG_ON(ddr_clk_pre == 0 || ddr_clk_pre > 255); |
| 2541 | BUG_ON(ddr_clk_post == 0 || ddr_clk_post > 255); |
| 2542 | |
| 2543 | r = dsi_read_reg(DSI_CLK_TIMING); |
| 2544 | r = FLD_MOD(r, ddr_clk_pre, 15, 8); |
| 2545 | r = FLD_MOD(r, ddr_clk_post, 7, 0); |
| 2546 | dsi_write_reg(DSI_CLK_TIMING, r); |
| 2547 | |
| 2548 | DSSDBG("ddr_clk_pre %u, ddr_clk_post %u\n", |
| 2549 | ddr_clk_pre, |
| 2550 | ddr_clk_post); |
| 2551 | |
| 2552 | enter_hs_mode_lat = 1 + DIV_ROUND_UP(tlpx, 4) + |
| 2553 | DIV_ROUND_UP(ths_prepare, 4) + |
| 2554 | DIV_ROUND_UP(ths_zero + 3, 4); |
| 2555 | |
| 2556 | exit_hs_mode_lat = DIV_ROUND_UP(ths_trail + ths_exit, 4) + 1 + ths_eot; |
| 2557 | |
| 2558 | r = FLD_VAL(enter_hs_mode_lat, 31, 16) | |
| 2559 | FLD_VAL(exit_hs_mode_lat, 15, 0); |
| 2560 | dsi_write_reg(DSI_VM_TIMING7, r); |
| 2561 | |
| 2562 | DSSDBG("enter_hs_mode_lat %u, exit_hs_mode_lat %u\n", |
| 2563 | enter_hs_mode_lat, exit_hs_mode_lat); |
| 2564 | } |
| 2565 | |
| 2566 | |
| 2567 | #define DSI_DECL_VARS \ |
| 2568 | int __dsi_cb = 0; u32 __dsi_cv = 0; |
| 2569 | |
| 2570 | #define DSI_FLUSH(ch) \ |
| 2571 | if (__dsi_cb > 0) { \ |
| 2572 | /*DSSDBG("sending long packet %#010x\n", __dsi_cv);*/ \ |
| 2573 | dsi_write_reg(DSI_VC_LONG_PACKET_PAYLOAD(ch), __dsi_cv); \ |
| 2574 | __dsi_cb = __dsi_cv = 0; \ |
| 2575 | } |
| 2576 | |
| 2577 | #define DSI_PUSH(ch, data) \ |
| 2578 | do { \ |
| 2579 | __dsi_cv |= (data) << (__dsi_cb * 8); \ |
| 2580 | /*DSSDBG("cv = %#010x, cb = %d\n", __dsi_cv, __dsi_cb);*/ \ |
| 2581 | if (++__dsi_cb > 3) \ |
| 2582 | DSI_FLUSH(ch); \ |
| 2583 | } while (0) |
| 2584 | |
| 2585 | static int dsi_update_screen_l4(struct omap_dss_device *dssdev, |
| 2586 | int x, int y, int w, int h) |
| 2587 | { |
| 2588 | /* Note: supports only 24bit colors in 32bit container */ |
| 2589 | int first = 1; |
| 2590 | int fifo_stalls = 0; |
| 2591 | int max_dsi_packet_size; |
| 2592 | int max_data_per_packet; |
| 2593 | int max_pixels_per_packet; |
| 2594 | int pixels_left; |
| 2595 | int bytespp = dssdev->ctrl.pixel_size / 8; |
| 2596 | int scr_width; |
| 2597 | u32 __iomem *data; |
| 2598 | int start_offset; |
| 2599 | int horiz_inc; |
| 2600 | int current_x; |
| 2601 | struct omap_overlay *ovl; |
| 2602 | |
| 2603 | debug_irq = 0; |
| 2604 | |
| 2605 | DSSDBG("dsi_update_screen_l4 (%d,%d %dx%d)\n", |
| 2606 | x, y, w, h); |
| 2607 | |
| 2608 | ovl = dssdev->manager->overlays[0]; |
| 2609 | |
| 2610 | if (ovl->info.color_mode != OMAP_DSS_COLOR_RGB24U) |
| 2611 | return -EINVAL; |
| 2612 | |
| 2613 | if (dssdev->ctrl.pixel_size != 24) |
| 2614 | return -EINVAL; |
| 2615 | |
| 2616 | scr_width = ovl->info.screen_width; |
| 2617 | data = ovl->info.vaddr; |
| 2618 | |
| 2619 | start_offset = scr_width * y + x; |
| 2620 | horiz_inc = scr_width - w; |
| 2621 | current_x = x; |
| 2622 | |
| 2623 | /* We need header(4) + DCSCMD(1) + pixels(numpix*bytespp) bytes |
| 2624 | * in fifo */ |
| 2625 | |
| 2626 | /* When using CPU, max long packet size is TX buffer size */ |
| 2627 | max_dsi_packet_size = dsi.vc[0].fifo_size * 32 * 4; |
| 2628 | |
| 2629 | /* we seem to get better perf if we divide the tx fifo to half, |
| 2630 | and while the other half is being sent, we fill the other half |
| 2631 | max_dsi_packet_size /= 2; */ |
| 2632 | |
| 2633 | max_data_per_packet = max_dsi_packet_size - 4 - 1; |
| 2634 | |
| 2635 | max_pixels_per_packet = max_data_per_packet / bytespp; |
| 2636 | |
| 2637 | DSSDBG("max_pixels_per_packet %d\n", max_pixels_per_packet); |
| 2638 | |
| 2639 | pixels_left = w * h; |
| 2640 | |
| 2641 | DSSDBG("total pixels %d\n", pixels_left); |
| 2642 | |
| 2643 | data += start_offset; |
| 2644 | |
| 2645 | while (pixels_left > 0) { |
| 2646 | /* 0x2c = write_memory_start */ |
| 2647 | /* 0x3c = write_memory_continue */ |
| 2648 | u8 dcs_cmd = first ? 0x2c : 0x3c; |
| 2649 | int pixels; |
| 2650 | DSI_DECL_VARS; |
| 2651 | first = 0; |
| 2652 | |
| 2653 | #if 1 |
| 2654 | /* using fifo not empty */ |
| 2655 | /* TX_FIFO_NOT_EMPTY */ |
| 2656 | while (FLD_GET(dsi_read_reg(DSI_VC_CTRL(0)), 5, 5)) { |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2657 | fifo_stalls++; |
| 2658 | if (fifo_stalls > 0xfffff) { |
| 2659 | DSSERR("fifo stalls overflow, pixels left %d\n", |
| 2660 | pixels_left); |
| 2661 | dsi_if_enable(0); |
| 2662 | return -EIO; |
| 2663 | } |
Tomi Valkeinen | 24be78b | 2010-01-07 14:19:48 +0200 | [diff] [blame] | 2664 | udelay(1); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2665 | } |
| 2666 | #elif 1 |
| 2667 | /* using fifo emptiness */ |
| 2668 | while ((REG_GET(DSI_TX_FIFO_VC_EMPTINESS, 7, 0)+1)*4 < |
| 2669 | max_dsi_packet_size) { |
| 2670 | fifo_stalls++; |
| 2671 | if (fifo_stalls > 0xfffff) { |
| 2672 | DSSERR("fifo stalls overflow, pixels left %d\n", |
| 2673 | pixels_left); |
| 2674 | dsi_if_enable(0); |
| 2675 | return -EIO; |
| 2676 | } |
| 2677 | } |
| 2678 | #else |
| 2679 | while ((REG_GET(DSI_TX_FIFO_VC_EMPTINESS, 7, 0)+1)*4 == 0) { |
| 2680 | fifo_stalls++; |
| 2681 | if (fifo_stalls > 0xfffff) { |
| 2682 | DSSERR("fifo stalls overflow, pixels left %d\n", |
| 2683 | pixels_left); |
| 2684 | dsi_if_enable(0); |
| 2685 | return -EIO; |
| 2686 | } |
| 2687 | } |
| 2688 | #endif |
| 2689 | pixels = min(max_pixels_per_packet, pixels_left); |
| 2690 | |
| 2691 | pixels_left -= pixels; |
| 2692 | |
| 2693 | dsi_vc_write_long_header(0, DSI_DT_DCS_LONG_WRITE, |
| 2694 | 1 + pixels * bytespp, 0); |
| 2695 | |
| 2696 | DSI_PUSH(0, dcs_cmd); |
| 2697 | |
| 2698 | while (pixels-- > 0) { |
| 2699 | u32 pix = __raw_readl(data++); |
| 2700 | |
| 2701 | DSI_PUSH(0, (pix >> 16) & 0xff); |
| 2702 | DSI_PUSH(0, (pix >> 8) & 0xff); |
| 2703 | DSI_PUSH(0, (pix >> 0) & 0xff); |
| 2704 | |
| 2705 | current_x++; |
| 2706 | if (current_x == x+w) { |
| 2707 | current_x = x; |
| 2708 | data += horiz_inc; |
| 2709 | } |
| 2710 | } |
| 2711 | |
| 2712 | DSI_FLUSH(0); |
| 2713 | } |
| 2714 | |
| 2715 | return 0; |
| 2716 | } |
| 2717 | |
| 2718 | static void dsi_update_screen_dispc(struct omap_dss_device *dssdev, |
| 2719 | u16 x, u16 y, u16 w, u16 h) |
| 2720 | { |
| 2721 | unsigned bytespp; |
| 2722 | unsigned bytespl; |
| 2723 | unsigned bytespf; |
| 2724 | unsigned total_len; |
| 2725 | unsigned packet_payload; |
| 2726 | unsigned packet_len; |
| 2727 | u32 l; |
Tomi Valkeinen | 0f16aa0 | 2010-04-12 09:57:19 +0300 | [diff] [blame] | 2728 | int r; |
Tomi Valkeinen | 18946f6 | 2010-01-12 14:16:41 +0200 | [diff] [blame] | 2729 | const unsigned channel = dsi.update_channel; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2730 | /* line buffer is 1024 x 24bits */ |
| 2731 | /* XXX: for some reason using full buffer size causes considerable TX |
| 2732 | * slowdown with update sizes that fill the whole buffer */ |
| 2733 | const unsigned line_buf_size = 1023 * 3; |
| 2734 | |
Tomi Valkeinen | 446f7bf | 2010-01-11 16:12:31 +0200 | [diff] [blame] | 2735 | DSSDBG("dsi_update_screen_dispc(%d,%d %dx%d)\n", |
| 2736 | x, y, w, h); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2737 | |
Tomi Valkeinen | 18946f6 | 2010-01-12 14:16:41 +0200 | [diff] [blame] | 2738 | dsi_vc_config_vp(channel); |
| 2739 | |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2740 | bytespp = dssdev->ctrl.pixel_size / 8; |
| 2741 | bytespl = w * bytespp; |
| 2742 | bytespf = bytespl * h; |
| 2743 | |
| 2744 | /* NOTE: packet_payload has to be equal to N * bytespl, where N is |
| 2745 | * number of lines in a packet. See errata about VP_CLK_RATIO */ |
| 2746 | |
| 2747 | if (bytespf < line_buf_size) |
| 2748 | packet_payload = bytespf; |
| 2749 | else |
| 2750 | packet_payload = (line_buf_size) / bytespl * bytespl; |
| 2751 | |
| 2752 | packet_len = packet_payload + 1; /* 1 byte for DCS cmd */ |
| 2753 | total_len = (bytespf / packet_payload) * packet_len; |
| 2754 | |
| 2755 | if (bytespf % packet_payload) |
| 2756 | total_len += (bytespf % packet_payload) + 1; |
| 2757 | |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2758 | l = FLD_VAL(total_len, 23, 0); /* TE_SIZE */ |
| 2759 | dsi_write_reg(DSI_VC_TE(channel), l); |
| 2760 | |
| 2761 | dsi_vc_write_long_header(channel, DSI_DT_DCS_LONG_WRITE, packet_len, 0); |
| 2762 | |
Tomi Valkeinen | 942a91a | 2010-02-10 17:27:39 +0200 | [diff] [blame] | 2763 | if (dsi.te_enabled) |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2764 | l = FLD_MOD(l, 1, 30, 30); /* TE_EN */ |
| 2765 | else |
| 2766 | l = FLD_MOD(l, 1, 31, 31); /* TE_START */ |
| 2767 | dsi_write_reg(DSI_VC_TE(channel), l); |
| 2768 | |
| 2769 | /* We put SIDLEMODE to no-idle for the duration of the transfer, |
| 2770 | * because DSS interrupts are not capable of waking up the CPU and the |
| 2771 | * framedone interrupt could be delayed for quite a long time. I think |
| 2772 | * the same goes for any DSS interrupts, but for some reason I have not |
| 2773 | * seen the problem anywhere else than here. |
| 2774 | */ |
| 2775 | dispc_disable_sidle(); |
| 2776 | |
Tomi Valkeinen | 18946f6 | 2010-01-12 14:16:41 +0200 | [diff] [blame] | 2777 | dsi_perf_mark_start(); |
| 2778 | |
Tomi Valkeinen | 0f16aa0 | 2010-04-12 09:57:19 +0300 | [diff] [blame] | 2779 | r = queue_delayed_work(dsi.workqueue, &dsi.framedone_timeout_work, |
Tomi Valkeinen | 18946f6 | 2010-01-12 14:16:41 +0200 | [diff] [blame] | 2780 | msecs_to_jiffies(250)); |
Tomi Valkeinen | 0f16aa0 | 2010-04-12 09:57:19 +0300 | [diff] [blame] | 2781 | BUG_ON(r == 0); |
Tomi Valkeinen | 18946f6 | 2010-01-12 14:16:41 +0200 | [diff] [blame] | 2782 | |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2783 | dss_start_update(dssdev); |
| 2784 | |
Tomi Valkeinen | 942a91a | 2010-02-10 17:27:39 +0200 | [diff] [blame] | 2785 | if (dsi.te_enabled) { |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2786 | /* disable LP_RX_TO, so that we can receive TE. Time to wait |
| 2787 | * for TE is longer than the timer allows */ |
| 2788 | REG_FLD_MOD(DSI_TIMING2, 0, 15, 15); /* LP_RX_TO */ |
| 2789 | |
| 2790 | dsi_vc_send_bta(channel); |
| 2791 | |
| 2792 | #ifdef DSI_CATCH_MISSING_TE |
| 2793 | mod_timer(&dsi.te_timer, jiffies + msecs_to_jiffies(250)); |
| 2794 | #endif |
| 2795 | } |
| 2796 | } |
| 2797 | |
| 2798 | #ifdef DSI_CATCH_MISSING_TE |
| 2799 | static void dsi_te_timeout(unsigned long arg) |
| 2800 | { |
| 2801 | DSSERR("TE not received for 250ms!\n"); |
| 2802 | } |
| 2803 | #endif |
| 2804 | |
Tomi Valkeinen | ab83b14 | 2010-06-09 15:31:01 +0300 | [diff] [blame] | 2805 | static void dsi_handle_framedone(int error) |
Tomi Valkeinen | 18946f6 | 2010-01-12 14:16:41 +0200 | [diff] [blame] | 2806 | { |
Tomi Valkeinen | 18946f6 | 2010-01-12 14:16:41 +0200 | [diff] [blame] | 2807 | const int channel = dsi.update_channel; |
Tomi Valkeinen | 18946f6 | 2010-01-12 14:16:41 +0200 | [diff] [blame] | 2808 | |
Tomi Valkeinen | ab83b14 | 2010-06-09 15:31:01 +0300 | [diff] [blame] | 2809 | cancel_delayed_work(&dsi.framedone_timeout_work); |
Tomi Valkeinen | 18946f6 | 2010-01-12 14:16:41 +0200 | [diff] [blame] | 2810 | |
Tomi Valkeinen | ab83b14 | 2010-06-09 15:31:01 +0300 | [diff] [blame] | 2811 | dsi_vc_disable_bta_irq(channel); |
| 2812 | |
| 2813 | /* SIDLEMODE back to smart-idle */ |
| 2814 | dispc_enable_sidle(); |
| 2815 | |
| 2816 | dsi.bta_callback = NULL; |
| 2817 | |
| 2818 | if (dsi.te_enabled) { |
| 2819 | /* enable LP_RX_TO again after the TE */ |
| 2820 | REG_FLD_MOD(DSI_TIMING2, 1, 15, 15); /* LP_RX_TO */ |
| 2821 | } |
| 2822 | |
| 2823 | /* RX_FIFO_NOT_EMPTY */ |
| 2824 | if (REG_GET(DSI_VC_CTRL(channel), 20, 20)) { |
| 2825 | DSSERR("Received error during frame transfer:\n"); |
| 2826 | dsi_vc_flush_receive_data(channel); |
| 2827 | if (!error) |
| 2828 | error = -EIO; |
| 2829 | } |
| 2830 | |
| 2831 | dsi.framedone_callback(error, dsi.framedone_data); |
| 2832 | |
| 2833 | if (!error) |
| 2834 | dsi_perf_show("DISPC"); |
| 2835 | } |
| 2836 | |
| 2837 | static void dsi_framedone_timeout_work_callback(struct work_struct *work) |
| 2838 | { |
Tomi Valkeinen | 0f16aa0 | 2010-04-12 09:57:19 +0300 | [diff] [blame] | 2839 | /* XXX While extremely unlikely, we could get FRAMEDONE interrupt after |
| 2840 | * 250ms which would conflict with this timeout work. What should be |
| 2841 | * done is first cancel the transfer on the HW, and then cancel the |
Tomi Valkeinen | ab83b14 | 2010-06-09 15:31:01 +0300 | [diff] [blame] | 2842 | * possibly scheduled framedone work. However, cancelling the transfer |
| 2843 | * on the HW is buggy, and would probably require resetting the whole |
| 2844 | * DSI */ |
Tomi Valkeinen | 0f16aa0 | 2010-04-12 09:57:19 +0300 | [diff] [blame] | 2845 | |
Tomi Valkeinen | ab83b14 | 2010-06-09 15:31:01 +0300 | [diff] [blame] | 2846 | DSSERR("Framedone not received for 250ms!\n"); |
Tomi Valkeinen | 18946f6 | 2010-01-12 14:16:41 +0200 | [diff] [blame] | 2847 | |
Tomi Valkeinen | ab83b14 | 2010-06-09 15:31:01 +0300 | [diff] [blame] | 2848 | dsi_handle_framedone(-ETIMEDOUT); |
Tomi Valkeinen | 18946f6 | 2010-01-12 14:16:41 +0200 | [diff] [blame] | 2849 | } |
| 2850 | |
Tomi Valkeinen | ab83b14 | 2010-06-09 15:31:01 +0300 | [diff] [blame] | 2851 | static void dsi_framedone_bta_callback(void) |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2852 | { |
Tomi Valkeinen | ab83b14 | 2010-06-09 15:31:01 +0300 | [diff] [blame] | 2853 | dsi_handle_framedone(0); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2854 | |
| 2855 | #ifdef CONFIG_OMAP2_DSS_FAKE_VSYNC |
| 2856 | dispc_fake_vsync_irq(); |
| 2857 | #endif |
| 2858 | } |
| 2859 | |
Tomi Valkeinen | ab83b14 | 2010-06-09 15:31:01 +0300 | [diff] [blame] | 2860 | static void dsi_framedone_irq_callback(void *data, u32 mask) |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2861 | { |
Tomi Valkeinen | ab83b14 | 2010-06-09 15:31:01 +0300 | [diff] [blame] | 2862 | const int channel = dsi.update_channel; |
| 2863 | int r; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2864 | |
Tomi Valkeinen | ab83b14 | 2010-06-09 15:31:01 +0300 | [diff] [blame] | 2865 | /* Note: We get FRAMEDONE when DISPC has finished sending pixels and |
| 2866 | * turns itself off. However, DSI still has the pixels in its buffers, |
| 2867 | * and is sending the data. |
| 2868 | */ |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2869 | |
Tomi Valkeinen | ab83b14 | 2010-06-09 15:31:01 +0300 | [diff] [blame] | 2870 | if (dsi.te_enabled) { |
| 2871 | /* enable LP_RX_TO again after the TE */ |
| 2872 | REG_FLD_MOD(DSI_TIMING2, 1, 15, 15); /* LP_RX_TO */ |
| 2873 | } |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2874 | |
Tomi Valkeinen | ab83b14 | 2010-06-09 15:31:01 +0300 | [diff] [blame] | 2875 | /* Send BTA after the frame. We need this for the TE to work, as TE |
| 2876 | * trigger is only sent for BTAs without preceding packet. Thus we need |
| 2877 | * to BTA after the pixel packets so that next BTA will cause TE |
| 2878 | * trigger. |
| 2879 | * |
| 2880 | * This is not needed when TE is not in use, but we do it anyway to |
| 2881 | * make sure that the transfer has been completed. It would be more |
| 2882 | * optimal, but more complex, to wait only just before starting next |
| 2883 | * transfer. |
| 2884 | * |
| 2885 | * Also, as there's no interrupt telling when the transfer has been |
| 2886 | * done and the channel could be reconfigured, the only way is to |
| 2887 | * busyloop until TE_SIZE is zero. With BTA we can do this |
| 2888 | * asynchronously. |
| 2889 | * */ |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2890 | |
Tomi Valkeinen | ab83b14 | 2010-06-09 15:31:01 +0300 | [diff] [blame] | 2891 | dsi.bta_callback = dsi_framedone_bta_callback; |
| 2892 | |
| 2893 | barrier(); |
| 2894 | |
| 2895 | dsi_vc_enable_bta_irq(channel); |
| 2896 | |
| 2897 | r = dsi_vc_send_bta(channel); |
| 2898 | if (r) { |
| 2899 | DSSERR("BTA after framedone failed\n"); |
| 2900 | dsi_handle_framedone(-EIO); |
| 2901 | } |
Tomi Valkeinen | 18946f6 | 2010-01-12 14:16:41 +0200 | [diff] [blame] | 2902 | } |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2903 | |
Tomi Valkeinen | 18946f6 | 2010-01-12 14:16:41 +0200 | [diff] [blame] | 2904 | int omap_dsi_prepare_update(struct omap_dss_device *dssdev, |
Tomi Valkeinen | 26a8c25 | 2010-06-09 15:31:34 +0300 | [diff] [blame] | 2905 | u16 *x, u16 *y, u16 *w, u16 *h, |
| 2906 | bool enlarge_update_area) |
Tomi Valkeinen | 18946f6 | 2010-01-12 14:16:41 +0200 | [diff] [blame] | 2907 | { |
| 2908 | u16 dw, dh; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2909 | |
Tomi Valkeinen | 18946f6 | 2010-01-12 14:16:41 +0200 | [diff] [blame] | 2910 | dssdev->driver->get_resolution(dssdev, &dw, &dh); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2911 | |
Tomi Valkeinen | 18946f6 | 2010-01-12 14:16:41 +0200 | [diff] [blame] | 2912 | if (*x > dw || *y > dh) |
| 2913 | return -EINVAL; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2914 | |
Tomi Valkeinen | 18946f6 | 2010-01-12 14:16:41 +0200 | [diff] [blame] | 2915 | if (*x + *w > dw) |
| 2916 | return -EINVAL; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2917 | |
Tomi Valkeinen | 18946f6 | 2010-01-12 14:16:41 +0200 | [diff] [blame] | 2918 | if (*y + *h > dh) |
| 2919 | return -EINVAL; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2920 | |
Tomi Valkeinen | 18946f6 | 2010-01-12 14:16:41 +0200 | [diff] [blame] | 2921 | if (*w == 1) |
| 2922 | return -EINVAL; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2923 | |
Tomi Valkeinen | 18946f6 | 2010-01-12 14:16:41 +0200 | [diff] [blame] | 2924 | if (*w == 0 || *h == 0) |
| 2925 | return -EINVAL; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2926 | |
Tomi Valkeinen | 18946f6 | 2010-01-12 14:16:41 +0200 | [diff] [blame] | 2927 | dsi_perf_mark_setup(); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2928 | |
Tomi Valkeinen | 18946f6 | 2010-01-12 14:16:41 +0200 | [diff] [blame] | 2929 | if (dssdev->manager->caps & OMAP_DSS_OVL_MGR_CAP_DISPC) { |
Tomi Valkeinen | 26a8c25 | 2010-06-09 15:31:34 +0300 | [diff] [blame] | 2930 | dss_setup_partial_planes(dssdev, x, y, w, h, |
| 2931 | enlarge_update_area); |
Sumit Semwal | 64ba4f7 | 2010-12-02 11:27:10 +0000 | [diff] [blame] | 2932 | dispc_set_lcd_size(dssdev->manager->id, *w, *h); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2933 | } |
| 2934 | |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2935 | return 0; |
| 2936 | } |
Tomi Valkeinen | 18946f6 | 2010-01-12 14:16:41 +0200 | [diff] [blame] | 2937 | EXPORT_SYMBOL(omap_dsi_prepare_update); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2938 | |
Tomi Valkeinen | 18946f6 | 2010-01-12 14:16:41 +0200 | [diff] [blame] | 2939 | int omap_dsi_update(struct omap_dss_device *dssdev, |
| 2940 | int channel, |
| 2941 | u16 x, u16 y, u16 w, u16 h, |
| 2942 | void (*callback)(int, void *), void *data) |
| 2943 | { |
| 2944 | dsi.update_channel = channel; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2945 | |
Tomi Valkeinen | a602771 | 2010-05-25 17:01:28 +0300 | [diff] [blame] | 2946 | /* OMAP DSS cannot send updates of odd widths. |
| 2947 | * omap_dsi_prepare_update() makes the widths even, but add a BUG_ON |
| 2948 | * here to make sure we catch erroneous updates. Otherwise we'll only |
| 2949 | * see rather obscure HW error happening, as DSS halts. */ |
| 2950 | BUG_ON(x % 2 == 1); |
| 2951 | |
Tomi Valkeinen | 18946f6 | 2010-01-12 14:16:41 +0200 | [diff] [blame] | 2952 | if (dssdev->manager->caps & OMAP_DSS_OVL_MGR_CAP_DISPC) { |
| 2953 | dsi.framedone_callback = callback; |
| 2954 | dsi.framedone_data = data; |
| 2955 | |
| 2956 | dsi.update_region.x = x; |
| 2957 | dsi.update_region.y = y; |
| 2958 | dsi.update_region.w = w; |
| 2959 | dsi.update_region.h = h; |
| 2960 | dsi.update_region.device = dssdev; |
| 2961 | |
| 2962 | dsi_update_screen_dispc(dssdev, x, y, w, h); |
| 2963 | } else { |
Archit Taneja | e9c31af | 2010-07-14 14:11:50 +0200 | [diff] [blame] | 2964 | int r; |
| 2965 | |
| 2966 | r = dsi_update_screen_l4(dssdev, x, y, w, h); |
| 2967 | if (r) |
| 2968 | return r; |
| 2969 | |
Tomi Valkeinen | 18946f6 | 2010-01-12 14:16:41 +0200 | [diff] [blame] | 2970 | dsi_perf_show("L4"); |
| 2971 | callback(0, data); |
| 2972 | } |
| 2973 | |
| 2974 | return 0; |
| 2975 | } |
| 2976 | EXPORT_SYMBOL(omap_dsi_update); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2977 | |
| 2978 | /* Display funcs */ |
| 2979 | |
| 2980 | static int dsi_display_init_dispc(struct omap_dss_device *dssdev) |
| 2981 | { |
| 2982 | int r; |
| 2983 | |
| 2984 | r = omap_dispc_register_isr(dsi_framedone_irq_callback, NULL, |
| 2985 | DISPC_IRQ_FRAMEDONE); |
| 2986 | if (r) { |
| 2987 | DSSERR("can't get FRAMEDONE irq\n"); |
| 2988 | return r; |
| 2989 | } |
| 2990 | |
Sumit Semwal | 64ba4f7 | 2010-12-02 11:27:10 +0000 | [diff] [blame] | 2991 | dispc_set_lcd_display_type(dssdev->manager->id, |
| 2992 | OMAP_DSS_LCD_DISPLAY_TFT); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2993 | |
Sumit Semwal | 64ba4f7 | 2010-12-02 11:27:10 +0000 | [diff] [blame] | 2994 | dispc_set_parallel_interface_mode(dssdev->manager->id, |
| 2995 | OMAP_DSS_PARALLELMODE_DSI); |
| 2996 | dispc_enable_fifohandcheck(dssdev->manager->id, 1); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2997 | |
Sumit Semwal | 64ba4f7 | 2010-12-02 11:27:10 +0000 | [diff] [blame] | 2998 | dispc_set_tft_data_lines(dssdev->manager->id, dssdev->ctrl.pixel_size); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2999 | |
| 3000 | { |
| 3001 | struct omap_video_timings timings = { |
| 3002 | .hsw = 1, |
| 3003 | .hfp = 1, |
| 3004 | .hbp = 1, |
| 3005 | .vsw = 1, |
| 3006 | .vfp = 0, |
| 3007 | .vbp = 0, |
| 3008 | }; |
| 3009 | |
Sumit Semwal | 64ba4f7 | 2010-12-02 11:27:10 +0000 | [diff] [blame] | 3010 | dispc_set_lcd_timings(dssdev->manager->id, &timings); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3011 | } |
| 3012 | |
| 3013 | return 0; |
| 3014 | } |
| 3015 | |
| 3016 | static void dsi_display_uninit_dispc(struct omap_dss_device *dssdev) |
| 3017 | { |
| 3018 | omap_dispc_unregister_isr(dsi_framedone_irq_callback, NULL, |
| 3019 | DISPC_IRQ_FRAMEDONE); |
| 3020 | } |
| 3021 | |
| 3022 | static int dsi_configure_dsi_clocks(struct omap_dss_device *dssdev) |
| 3023 | { |
| 3024 | struct dsi_clock_info cinfo; |
| 3025 | int r; |
| 3026 | |
Archit Taneja | 1bb4783 | 2011-02-24 14:17:30 +0530 | [diff] [blame] | 3027 | /* we always use DSS_CLK_SYSCK as input clock */ |
| 3028 | cinfo.use_sys_clk = true; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3029 | cinfo.regn = dssdev->phy.dsi.div.regn; |
| 3030 | cinfo.regm = dssdev->phy.dsi.div.regm; |
Archit Taneja | 1bb4783 | 2011-02-24 14:17:30 +0530 | [diff] [blame] | 3031 | cinfo.regm_dispc = dssdev->phy.dsi.div.regm_dispc; |
| 3032 | cinfo.regm_dsi = dssdev->phy.dsi.div.regm_dsi; |
Sumit Semwal | ff1b2cd | 2010-12-02 11:27:11 +0000 | [diff] [blame] | 3033 | r = dsi_calc_clock_rates(dssdev, &cinfo); |
Ville Syrjälä | ebf0a3f | 2010-04-22 22:50:05 +0200 | [diff] [blame] | 3034 | if (r) { |
| 3035 | DSSERR("Failed to calc dsi clocks\n"); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3036 | return r; |
Ville Syrjälä | ebf0a3f | 2010-04-22 22:50:05 +0200 | [diff] [blame] | 3037 | } |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3038 | |
| 3039 | r = dsi_pll_set_clock_div(&cinfo); |
| 3040 | if (r) { |
| 3041 | DSSERR("Failed to set dsi clocks\n"); |
| 3042 | return r; |
| 3043 | } |
| 3044 | |
| 3045 | return 0; |
| 3046 | } |
| 3047 | |
| 3048 | static int dsi_configure_dispc_clocks(struct omap_dss_device *dssdev) |
| 3049 | { |
| 3050 | struct dispc_clock_info dispc_cinfo; |
| 3051 | int r; |
| 3052 | unsigned long long fck; |
| 3053 | |
Archit Taneja | 1bb4783 | 2011-02-24 14:17:30 +0530 | [diff] [blame] | 3054 | fck = dsi_get_pll_hsdiv_dispc_rate(); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3055 | |
| 3056 | dispc_cinfo.lck_div = dssdev->phy.dsi.div.lck_div; |
| 3057 | dispc_cinfo.pck_div = dssdev->phy.dsi.div.pck_div; |
| 3058 | |
| 3059 | r = dispc_calc_clock_rates(fck, &dispc_cinfo); |
| 3060 | if (r) { |
| 3061 | DSSERR("Failed to calc dispc clocks\n"); |
| 3062 | return r; |
| 3063 | } |
| 3064 | |
Sumit Semwal | ff1b2cd | 2010-12-02 11:27:11 +0000 | [diff] [blame] | 3065 | r = dispc_set_clock_div(dssdev->manager->id, &dispc_cinfo); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3066 | if (r) { |
| 3067 | DSSERR("Failed to set dispc clocks\n"); |
| 3068 | return r; |
| 3069 | } |
| 3070 | |
| 3071 | return 0; |
| 3072 | } |
| 3073 | |
| 3074 | static int dsi_display_init_dsi(struct omap_dss_device *dssdev) |
| 3075 | { |
| 3076 | int r; |
| 3077 | |
| 3078 | _dsi_print_reset_status(); |
| 3079 | |
| 3080 | r = dsi_pll_init(dssdev, true, true); |
| 3081 | if (r) |
| 3082 | goto err0; |
| 3083 | |
| 3084 | r = dsi_configure_dsi_clocks(dssdev); |
| 3085 | if (r) |
| 3086 | goto err1; |
| 3087 | |
Archit Taneja | 88134fa | 2011-01-06 10:44:10 +0530 | [diff] [blame] | 3088 | dss_select_dispc_clk_source(DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC); |
| 3089 | dss_select_dsi_clk_source(DSS_CLK_SRC_DSI_PLL_HSDIV_DSI); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3090 | |
| 3091 | DSSDBG("PLL OK\n"); |
| 3092 | |
| 3093 | r = dsi_configure_dispc_clocks(dssdev); |
| 3094 | if (r) |
| 3095 | goto err2; |
| 3096 | |
| 3097 | r = dsi_complexio_init(dssdev); |
| 3098 | if (r) |
| 3099 | goto err2; |
| 3100 | |
| 3101 | _dsi_print_reset_status(); |
| 3102 | |
| 3103 | dsi_proto_timings(dssdev); |
| 3104 | dsi_set_lp_clk_divisor(dssdev); |
| 3105 | |
| 3106 | if (1) |
| 3107 | _dsi_print_reset_status(); |
| 3108 | |
| 3109 | r = dsi_proto_config(dssdev); |
| 3110 | if (r) |
| 3111 | goto err3; |
| 3112 | |
| 3113 | /* enable interface */ |
| 3114 | dsi_vc_enable(0, 1); |
Tomi Valkeinen | dd8079d | 2009-12-16 16:49:03 +0200 | [diff] [blame] | 3115 | dsi_vc_enable(1, 1); |
| 3116 | dsi_vc_enable(2, 1); |
| 3117 | dsi_vc_enable(3, 1); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3118 | dsi_if_enable(1); |
| 3119 | dsi_force_tx_stop_mode_io(); |
| 3120 | |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3121 | return 0; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3122 | err3: |
| 3123 | dsi_complexio_uninit(); |
| 3124 | err2: |
Archit Taneja | 88134fa | 2011-01-06 10:44:10 +0530 | [diff] [blame] | 3125 | dss_select_dispc_clk_source(DSS_CLK_SRC_FCK); |
| 3126 | dss_select_dsi_clk_source(DSS_CLK_SRC_FCK); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3127 | err1: |
| 3128 | dsi_pll_uninit(); |
| 3129 | err0: |
| 3130 | return r; |
| 3131 | } |
| 3132 | |
| 3133 | static void dsi_display_uninit_dsi(struct omap_dss_device *dssdev) |
| 3134 | { |
Ville Syrjälä | d737010 | 2010-04-22 22:50:09 +0200 | [diff] [blame] | 3135 | /* disable interface */ |
| 3136 | dsi_if_enable(0); |
| 3137 | dsi_vc_enable(0, 0); |
| 3138 | dsi_vc_enable(1, 0); |
| 3139 | dsi_vc_enable(2, 0); |
| 3140 | dsi_vc_enable(3, 0); |
| 3141 | |
Archit Taneja | 88134fa | 2011-01-06 10:44:10 +0530 | [diff] [blame] | 3142 | dss_select_dispc_clk_source(DSS_CLK_SRC_FCK); |
| 3143 | dss_select_dsi_clk_source(DSS_CLK_SRC_FCK); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3144 | dsi_complexio_uninit(); |
| 3145 | dsi_pll_uninit(); |
| 3146 | } |
| 3147 | |
| 3148 | static int dsi_core_init(void) |
| 3149 | { |
| 3150 | /* Autoidle */ |
| 3151 | REG_FLD_MOD(DSI_SYSCONFIG, 1, 0, 0); |
| 3152 | |
| 3153 | /* ENWAKEUP */ |
| 3154 | REG_FLD_MOD(DSI_SYSCONFIG, 1, 2, 2); |
| 3155 | |
| 3156 | /* SIDLEMODE smart-idle */ |
| 3157 | REG_FLD_MOD(DSI_SYSCONFIG, 2, 4, 3); |
| 3158 | |
| 3159 | _dsi_initialize_irq(); |
| 3160 | |
| 3161 | return 0; |
| 3162 | } |
| 3163 | |
Tomi Valkeinen | 37ac60e | 2010-01-12 15:12:07 +0200 | [diff] [blame] | 3164 | int omapdss_dsi_display_enable(struct omap_dss_device *dssdev) |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3165 | { |
| 3166 | int r = 0; |
| 3167 | |
| 3168 | DSSDBG("dsi_display_enable\n"); |
| 3169 | |
Tomi Valkeinen | 37ac60e | 2010-01-12 15:12:07 +0200 | [diff] [blame] | 3170 | WARN_ON(!dsi_bus_is_locked()); |
| 3171 | |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3172 | mutex_lock(&dsi.lock); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3173 | |
| 3174 | r = omap_dss_start_device(dssdev); |
| 3175 | if (r) { |
| 3176 | DSSERR("failed to start device\n"); |
| 3177 | goto err0; |
| 3178 | } |
| 3179 | |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3180 | enable_clocks(1); |
| 3181 | dsi_enable_pll_clock(1); |
| 3182 | |
| 3183 | r = _dsi_reset(); |
| 3184 | if (r) |
Tomi Valkeinen | 37ac60e | 2010-01-12 15:12:07 +0200 | [diff] [blame] | 3185 | goto err1; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3186 | |
| 3187 | dsi_core_init(); |
| 3188 | |
| 3189 | r = dsi_display_init_dispc(dssdev); |
| 3190 | if (r) |
Tomi Valkeinen | 37ac60e | 2010-01-12 15:12:07 +0200 | [diff] [blame] | 3191 | goto err1; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3192 | |
| 3193 | r = dsi_display_init_dsi(dssdev); |
| 3194 | if (r) |
Tomi Valkeinen | 37ac60e | 2010-01-12 15:12:07 +0200 | [diff] [blame] | 3195 | goto err2; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3196 | |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3197 | mutex_unlock(&dsi.lock); |
| 3198 | |
| 3199 | return 0; |
| 3200 | |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3201 | err2: |
Tomi Valkeinen | 37ac60e | 2010-01-12 15:12:07 +0200 | [diff] [blame] | 3202 | dsi_display_uninit_dispc(dssdev); |
| 3203 | err1: |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3204 | enable_clocks(0); |
| 3205 | dsi_enable_pll_clock(0); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3206 | omap_dss_stop_device(dssdev); |
| 3207 | err0: |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3208 | mutex_unlock(&dsi.lock); |
| 3209 | DSSDBG("dsi_display_enable FAILED\n"); |
| 3210 | return r; |
| 3211 | } |
Tomi Valkeinen | 37ac60e | 2010-01-12 15:12:07 +0200 | [diff] [blame] | 3212 | EXPORT_SYMBOL(omapdss_dsi_display_enable); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3213 | |
Tomi Valkeinen | 37ac60e | 2010-01-12 15:12:07 +0200 | [diff] [blame] | 3214 | void omapdss_dsi_display_disable(struct omap_dss_device *dssdev) |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3215 | { |
| 3216 | DSSDBG("dsi_display_disable\n"); |
| 3217 | |
Tomi Valkeinen | 37ac60e | 2010-01-12 15:12:07 +0200 | [diff] [blame] | 3218 | WARN_ON(!dsi_bus_is_locked()); |
| 3219 | |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3220 | mutex_lock(&dsi.lock); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3221 | |
| 3222 | dsi_display_uninit_dispc(dssdev); |
| 3223 | |
| 3224 | dsi_display_uninit_dsi(dssdev); |
| 3225 | |
| 3226 | enable_clocks(0); |
| 3227 | dsi_enable_pll_clock(0); |
| 3228 | |
| 3229 | omap_dss_stop_device(dssdev); |
Tomi Valkeinen | 37ac60e | 2010-01-12 15:12:07 +0200 | [diff] [blame] | 3230 | |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3231 | mutex_unlock(&dsi.lock); |
| 3232 | } |
Tomi Valkeinen | 37ac60e | 2010-01-12 15:12:07 +0200 | [diff] [blame] | 3233 | EXPORT_SYMBOL(omapdss_dsi_display_disable); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3234 | |
Tomi Valkeinen | 225b650 | 2010-01-11 15:11:01 +0200 | [diff] [blame] | 3235 | int omapdss_dsi_enable_te(struct omap_dss_device *dssdev, bool enable) |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3236 | { |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3237 | dsi.te_enabled = enable; |
Tomi Valkeinen | 225b650 | 2010-01-11 15:11:01 +0200 | [diff] [blame] | 3238 | return 0; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3239 | } |
Tomi Valkeinen | 225b650 | 2010-01-11 15:11:01 +0200 | [diff] [blame] | 3240 | EXPORT_SYMBOL(omapdss_dsi_enable_te); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3241 | |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3242 | void dsi_get_overlay_fifo_thresholds(enum omap_plane plane, |
| 3243 | u32 fifo_size, enum omap_burst_size *burst_size, |
| 3244 | u32 *fifo_low, u32 *fifo_high) |
| 3245 | { |
| 3246 | unsigned burst_size_bytes; |
| 3247 | |
| 3248 | *burst_size = OMAP_DSS_BURST_16x32; |
| 3249 | burst_size_bytes = 16 * 32 / 8; |
| 3250 | |
| 3251 | *fifo_high = fifo_size - burst_size_bytes; |
Tomi Valkeinen | 36194b4 | 2010-05-18 13:35:37 +0300 | [diff] [blame] | 3252 | *fifo_low = fifo_size - burst_size_bytes * 2; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3253 | } |
| 3254 | |
| 3255 | int dsi_init_display(struct omap_dss_device *dssdev) |
| 3256 | { |
| 3257 | DSSDBG("DSI init\n"); |
| 3258 | |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3259 | /* XXX these should be figured out dynamically */ |
| 3260 | dssdev->caps = OMAP_DSS_DISPLAY_CAP_MANUAL_UPDATE | |
| 3261 | OMAP_DSS_DISPLAY_CAP_TEAR_ELIM; |
| 3262 | |
Tomi Valkeinen | 5f42f2c | 2011-02-22 15:53:46 +0200 | [diff] [blame] | 3263 | if (dsi.vdds_dsi_reg == NULL) { |
| 3264 | struct regulator *vdds_dsi; |
| 3265 | |
| 3266 | vdds_dsi = regulator_get(&dsi.pdev->dev, "vdds_dsi"); |
| 3267 | |
| 3268 | if (IS_ERR(vdds_dsi)) { |
| 3269 | DSSERR("can't get VDDS_DSI regulator\n"); |
| 3270 | return PTR_ERR(vdds_dsi); |
| 3271 | } |
| 3272 | |
| 3273 | dsi.vdds_dsi_reg = vdds_dsi; |
| 3274 | } |
| 3275 | |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3276 | return 0; |
| 3277 | } |
| 3278 | |
Archit Taneja | 5ee3c14 | 2011-03-02 12:35:53 +0530 | [diff] [blame] | 3279 | int omap_dsi_request_vc(struct omap_dss_device *dssdev, int *channel) |
| 3280 | { |
| 3281 | int i; |
| 3282 | |
| 3283 | for (i = 0; i < ARRAY_SIZE(dsi.vc); i++) { |
| 3284 | if (!dsi.vc[i].dssdev) { |
| 3285 | dsi.vc[i].dssdev = dssdev; |
| 3286 | *channel = i; |
| 3287 | return 0; |
| 3288 | } |
| 3289 | } |
| 3290 | |
| 3291 | DSSERR("cannot get VC for display %s", dssdev->name); |
| 3292 | return -ENOSPC; |
| 3293 | } |
| 3294 | EXPORT_SYMBOL(omap_dsi_request_vc); |
| 3295 | |
| 3296 | int omap_dsi_set_vc_id(struct omap_dss_device *dssdev, int channel, int vc_id) |
| 3297 | { |
| 3298 | if (vc_id < 0 || vc_id > 3) { |
| 3299 | DSSERR("VC ID out of range\n"); |
| 3300 | return -EINVAL; |
| 3301 | } |
| 3302 | |
| 3303 | if (channel < 0 || channel > 3) { |
| 3304 | DSSERR("Virtual Channel out of range\n"); |
| 3305 | return -EINVAL; |
| 3306 | } |
| 3307 | |
| 3308 | if (dsi.vc[channel].dssdev != dssdev) { |
| 3309 | DSSERR("Virtual Channel not allocated to display %s\n", |
| 3310 | dssdev->name); |
| 3311 | return -EINVAL; |
| 3312 | } |
| 3313 | |
| 3314 | dsi.vc[channel].vc_id = vc_id; |
| 3315 | |
| 3316 | return 0; |
| 3317 | } |
| 3318 | EXPORT_SYMBOL(omap_dsi_set_vc_id); |
| 3319 | |
| 3320 | void omap_dsi_release_vc(struct omap_dss_device *dssdev, int channel) |
| 3321 | { |
| 3322 | if ((channel >= 0 && channel <= 3) && |
| 3323 | dsi.vc[channel].dssdev == dssdev) { |
| 3324 | dsi.vc[channel].dssdev = NULL; |
| 3325 | dsi.vc[channel].vc_id = 0; |
| 3326 | } |
| 3327 | } |
| 3328 | EXPORT_SYMBOL(omap_dsi_release_vc); |
| 3329 | |
Archit Taneja | 1bb4783 | 2011-02-24 14:17:30 +0530 | [diff] [blame] | 3330 | void dsi_wait_pll_hsdiv_dispc_active(void) |
Tomi Valkeinen | e406f90 | 2010-06-09 15:28:12 +0300 | [diff] [blame] | 3331 | { |
| 3332 | if (wait_for_bit_change(DSI_PLL_STATUS, 7, 1) != 1) |
Archit Taneja | 067a57e | 2011-03-02 11:57:25 +0530 | [diff] [blame] | 3333 | DSSERR("%s (%s) not active\n", |
| 3334 | dss_get_generic_clk_source_name(DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC), |
| 3335 | dss_feat_get_clk_source_name(DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC)); |
Tomi Valkeinen | e406f90 | 2010-06-09 15:28:12 +0300 | [diff] [blame] | 3336 | } |
| 3337 | |
Archit Taneja | 1bb4783 | 2011-02-24 14:17:30 +0530 | [diff] [blame] | 3338 | void dsi_wait_pll_hsdiv_dsi_active(void) |
Tomi Valkeinen | e406f90 | 2010-06-09 15:28:12 +0300 | [diff] [blame] | 3339 | { |
| 3340 | if (wait_for_bit_change(DSI_PLL_STATUS, 8, 1) != 1) |
Archit Taneja | 067a57e | 2011-03-02 11:57:25 +0530 | [diff] [blame] | 3341 | DSSERR("%s (%s) not active\n", |
| 3342 | dss_get_generic_clk_source_name(DSS_CLK_SRC_DSI_PLL_HSDIV_DSI), |
| 3343 | dss_feat_get_clk_source_name(DSS_CLK_SRC_DSI_PLL_HSDIV_DSI)); |
Tomi Valkeinen | e406f90 | 2010-06-09 15:28:12 +0300 | [diff] [blame] | 3344 | } |
| 3345 | |
Taneja, Archit | 4964111 | 2011-03-14 23:28:23 -0500 | [diff] [blame^] | 3346 | static void dsi_calc_clock_param_ranges(void) |
| 3347 | { |
| 3348 | dsi.regn_max = dss_feat_get_param_max(FEAT_PARAM_DSIPLL_REGN); |
| 3349 | dsi.regm_max = dss_feat_get_param_max(FEAT_PARAM_DSIPLL_REGM); |
| 3350 | dsi.regm_dispc_max = dss_feat_get_param_max(FEAT_PARAM_DSIPLL_REGM_DISPC); |
| 3351 | dsi.regm_dsi_max = dss_feat_get_param_max(FEAT_PARAM_DSIPLL_REGM_DSI); |
| 3352 | dsi.fint_min = dss_feat_get_param_min(FEAT_PARAM_DSIPLL_FINT); |
| 3353 | dsi.fint_max = dss_feat_get_param_max(FEAT_PARAM_DSIPLL_FINT); |
| 3354 | dsi.lpdiv_max = dss_feat_get_param_max(FEAT_PARAM_DSIPLL_LPDIV); |
| 3355 | } |
| 3356 | |
Senthilvadivu Guruswamy | c8aac01 | 2011-01-24 06:22:02 +0000 | [diff] [blame] | 3357 | static int dsi_init(struct platform_device *pdev) |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3358 | { |
| 3359 | u32 rev; |
Archit Taneja | 5ee3c14 | 2011-03-02 12:35:53 +0530 | [diff] [blame] | 3360 | int r, i; |
Senthilvadivu Guruswamy | ea9da36 | 2011-01-24 06:22:04 +0000 | [diff] [blame] | 3361 | struct resource *dsi_mem; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3362 | |
| 3363 | spin_lock_init(&dsi.errors_lock); |
| 3364 | dsi.errors = 0; |
| 3365 | |
Tomi Valkeinen | dfc0fd8 | 2009-12-17 14:35:21 +0200 | [diff] [blame] | 3366 | #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS |
| 3367 | spin_lock_init(&dsi.irq_stats_lock); |
| 3368 | dsi.irq_stats.last_reset = jiffies; |
| 3369 | #endif |
| 3370 | |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3371 | init_completion(&dsi.bta_completion); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3372 | |
| 3373 | mutex_init(&dsi.lock); |
Tomi Valkeinen | b9eb5d7 | 2010-01-11 16:33:56 +0200 | [diff] [blame] | 3374 | sema_init(&dsi.bus_lock, 1); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3375 | |
Tomi Valkeinen | 0f16aa0 | 2010-04-12 09:57:19 +0300 | [diff] [blame] | 3376 | dsi.workqueue = create_singlethread_workqueue("dsi"); |
| 3377 | if (dsi.workqueue == NULL) |
| 3378 | return -ENOMEM; |
| 3379 | |
Tomi Valkeinen | 18946f6 | 2010-01-12 14:16:41 +0200 | [diff] [blame] | 3380 | INIT_DELAYED_WORK_DEFERRABLE(&dsi.framedone_timeout_work, |
| 3381 | dsi_framedone_timeout_work_callback); |
| 3382 | |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3383 | #ifdef DSI_CATCH_MISSING_TE |
| 3384 | init_timer(&dsi.te_timer); |
| 3385 | dsi.te_timer.function = dsi_te_timeout; |
| 3386 | dsi.te_timer.data = 0; |
| 3387 | #endif |
Senthilvadivu Guruswamy | ea9da36 | 2011-01-24 06:22:04 +0000 | [diff] [blame] | 3388 | dsi_mem = platform_get_resource(dsi.pdev, IORESOURCE_MEM, 0); |
| 3389 | if (!dsi_mem) { |
| 3390 | DSSERR("can't get IORESOURCE_MEM DSI\n"); |
| 3391 | r = -EINVAL; |
| 3392 | goto err1; |
| 3393 | } |
| 3394 | dsi.base = ioremap(dsi_mem->start, resource_size(dsi_mem)); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3395 | if (!dsi.base) { |
| 3396 | DSSERR("can't ioremap DSI\n"); |
| 3397 | r = -ENOMEM; |
| 3398 | goto err1; |
| 3399 | } |
archit taneja | affe360 | 2011-02-23 08:41:03 +0000 | [diff] [blame] | 3400 | dsi.irq = platform_get_irq(dsi.pdev, 0); |
| 3401 | if (dsi.irq < 0) { |
| 3402 | DSSERR("platform_get_irq failed\n"); |
| 3403 | r = -ENODEV; |
| 3404 | goto err2; |
| 3405 | } |
| 3406 | |
| 3407 | r = request_irq(dsi.irq, omap_dsi_irq_handler, IRQF_SHARED, |
| 3408 | "OMAP DSI1", dsi.pdev); |
| 3409 | if (r < 0) { |
| 3410 | DSSERR("request_irq failed\n"); |
| 3411 | goto err2; |
| 3412 | } |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3413 | |
Archit Taneja | 5ee3c14 | 2011-03-02 12:35:53 +0530 | [diff] [blame] | 3414 | /* DSI VCs initialization */ |
| 3415 | for (i = 0; i < ARRAY_SIZE(dsi.vc); i++) { |
| 3416 | dsi.vc[i].mode = DSI_VC_MODE_L4; |
| 3417 | dsi.vc[i].dssdev = NULL; |
| 3418 | dsi.vc[i].vc_id = 0; |
| 3419 | } |
| 3420 | |
Taneja, Archit | 4964111 | 2011-03-14 23:28:23 -0500 | [diff] [blame^] | 3421 | dsi_calc_clock_param_ranges(); |
| 3422 | |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3423 | enable_clocks(1); |
| 3424 | |
| 3425 | rev = dsi_read_reg(DSI_REVISION); |
Sumit Semwal | a06b62f | 2011-01-24 06:22:03 +0000 | [diff] [blame] | 3426 | dev_dbg(&pdev->dev, "OMAP DSI rev %d.%d\n", |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3427 | FLD_GET(rev, 7, 4), FLD_GET(rev, 3, 0)); |
| 3428 | |
| 3429 | enable_clocks(0); |
| 3430 | |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3431 | return 0; |
archit taneja | affe360 | 2011-02-23 08:41:03 +0000 | [diff] [blame] | 3432 | err2: |
| 3433 | iounmap(dsi.base); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3434 | err1: |
Tomi Valkeinen | 0f16aa0 | 2010-04-12 09:57:19 +0300 | [diff] [blame] | 3435 | destroy_workqueue(dsi.workqueue); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3436 | return r; |
| 3437 | } |
| 3438 | |
Senthilvadivu Guruswamy | c8aac01 | 2011-01-24 06:22:02 +0000 | [diff] [blame] | 3439 | static void dsi_exit(void) |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3440 | { |
Senthilvadivu Guruswamy | c8aac01 | 2011-01-24 06:22:02 +0000 | [diff] [blame] | 3441 | if (dsi.vdds_dsi_reg != NULL) { |
| 3442 | regulator_put(dsi.vdds_dsi_reg); |
| 3443 | dsi.vdds_dsi_reg = NULL; |
| 3444 | } |
| 3445 | |
archit taneja | affe360 | 2011-02-23 08:41:03 +0000 | [diff] [blame] | 3446 | free_irq(dsi.irq, dsi.pdev); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3447 | iounmap(dsi.base); |
| 3448 | |
Tomi Valkeinen | 0f16aa0 | 2010-04-12 09:57:19 +0300 | [diff] [blame] | 3449 | destroy_workqueue(dsi.workqueue); |
| 3450 | |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3451 | DSSDBG("omap_dsi_exit\n"); |
| 3452 | } |
| 3453 | |
Senthilvadivu Guruswamy | c8aac01 | 2011-01-24 06:22:02 +0000 | [diff] [blame] | 3454 | /* DSI1 HW IP initialisation */ |
| 3455 | static int omap_dsi1hw_probe(struct platform_device *pdev) |
| 3456 | { |
| 3457 | int r; |
| 3458 | dsi.pdev = pdev; |
| 3459 | r = dsi_init(pdev); |
| 3460 | if (r) { |
| 3461 | DSSERR("Failed to initialize DSI\n"); |
| 3462 | goto err_dsi; |
| 3463 | } |
| 3464 | err_dsi: |
| 3465 | return r; |
| 3466 | } |
| 3467 | |
| 3468 | static int omap_dsi1hw_remove(struct platform_device *pdev) |
| 3469 | { |
| 3470 | dsi_exit(); |
| 3471 | return 0; |
| 3472 | } |
| 3473 | |
| 3474 | static struct platform_driver omap_dsi1hw_driver = { |
| 3475 | .probe = omap_dsi1hw_probe, |
| 3476 | .remove = omap_dsi1hw_remove, |
| 3477 | .driver = { |
| 3478 | .name = "omapdss_dsi1", |
| 3479 | .owner = THIS_MODULE, |
| 3480 | }, |
| 3481 | }; |
| 3482 | |
| 3483 | int dsi_init_platform_driver(void) |
| 3484 | { |
| 3485 | return platform_driver_register(&omap_dsi1hw_driver); |
| 3486 | } |
| 3487 | |
| 3488 | void dsi_uninit_platform_driver(void) |
| 3489 | { |
| 3490 | return platform_driver_unregister(&omap_dsi1hw_driver); |
| 3491 | } |