Mike Marciniszyn | 7724105 | 2015-07-30 15:17:43 -0400 | [diff] [blame] | 1 | #ifndef _HFI1_KERNEL_H |
| 2 | #define _HFI1_KERNEL_H |
| 3 | /* |
| 4 | * |
| 5 | * This file is provided under a dual BSD/GPLv2 license. When using or |
| 6 | * redistributing this file, you may do so under either license. |
| 7 | * |
| 8 | * GPL LICENSE SUMMARY |
| 9 | * |
Easwar Hariharan | 91ab4ed | 2016-02-03 14:35:57 -0800 | [diff] [blame] | 10 | * Copyright(c) 2015, 2016 Intel Corporation. |
Mike Marciniszyn | 7724105 | 2015-07-30 15:17:43 -0400 | [diff] [blame] | 11 | * |
| 12 | * This program is free software; you can redistribute it and/or modify |
| 13 | * it under the terms of version 2 of the GNU General Public License as |
| 14 | * published by the Free Software Foundation. |
| 15 | * |
| 16 | * This program is distributed in the hope that it will be useful, but |
| 17 | * WITHOUT ANY WARRANTY; without even the implied warranty of |
| 18 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
| 19 | * General Public License for more details. |
| 20 | * |
| 21 | * BSD LICENSE |
| 22 | * |
Easwar Hariharan | 91ab4ed | 2016-02-03 14:35:57 -0800 | [diff] [blame] | 23 | * Copyright(c) 2015, 2016 Intel Corporation. |
Mike Marciniszyn | 7724105 | 2015-07-30 15:17:43 -0400 | [diff] [blame] | 24 | * |
| 25 | * Redistribution and use in source and binary forms, with or without |
| 26 | * modification, are permitted provided that the following conditions |
| 27 | * are met: |
| 28 | * |
| 29 | * - Redistributions of source code must retain the above copyright |
| 30 | * notice, this list of conditions and the following disclaimer. |
| 31 | * - Redistributions in binary form must reproduce the above copyright |
| 32 | * notice, this list of conditions and the following disclaimer in |
| 33 | * the documentation and/or other materials provided with the |
| 34 | * distribution. |
| 35 | * - Neither the name of Intel Corporation nor the names of its |
| 36 | * contributors may be used to endorse or promote products derived |
| 37 | * from this software without specific prior written permission. |
| 38 | * |
| 39 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS |
| 40 | * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT |
| 41 | * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR |
| 42 | * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT |
| 43 | * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, |
| 44 | * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT |
| 45 | * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
| 46 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
| 47 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
| 48 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
| 49 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| 50 | * |
| 51 | */ |
| 52 | |
| 53 | #include <linux/interrupt.h> |
| 54 | #include <linux/pci.h> |
| 55 | #include <linux/dma-mapping.h> |
| 56 | #include <linux/mutex.h> |
| 57 | #include <linux/list.h> |
| 58 | #include <linux/scatterlist.h> |
| 59 | #include <linux/slab.h> |
| 60 | #include <linux/io.h> |
| 61 | #include <linux/fs.h> |
| 62 | #include <linux/completion.h> |
| 63 | #include <linux/kref.h> |
| 64 | #include <linux/sched.h> |
| 65 | #include <linux/cdev.h> |
| 66 | #include <linux/delay.h> |
| 67 | #include <linux/kthread.h> |
Dennis Dalessandro | ec3f2c1 | 2016-01-19 14:41:33 -0800 | [diff] [blame] | 68 | #include <rdma/rdma_vt.h> |
Mike Marciniszyn | 7724105 | 2015-07-30 15:17:43 -0400 | [diff] [blame] | 69 | |
| 70 | #include "chip_registers.h" |
| 71 | #include "common.h" |
| 72 | #include "verbs.h" |
| 73 | #include "pio.h" |
| 74 | #include "chip.h" |
| 75 | #include "mad.h" |
| 76 | #include "qsfp.h" |
Easwar Hariharan | 8ebd4cf | 2016-02-03 14:31:14 -0800 | [diff] [blame] | 77 | #include "platform.h" |
Mitko Haralanov | 957558c | 2016-02-03 14:33:40 -0800 | [diff] [blame] | 78 | #include "affinity.h" |
Mike Marciniszyn | 7724105 | 2015-07-30 15:17:43 -0400 | [diff] [blame] | 79 | |
| 80 | /* bumped 1 from s/w major version of TrueScale */ |
| 81 | #define HFI1_CHIP_VERS_MAJ 3U |
| 82 | |
| 83 | /* don't care about this except printing */ |
| 84 | #define HFI1_CHIP_VERS_MIN 0U |
| 85 | |
| 86 | /* The Organization Unique Identifier (Mfg code), and its position in GUID */ |
| 87 | #define HFI1_OUI 0x001175 |
| 88 | #define HFI1_OUI_LSB 40 |
| 89 | |
| 90 | #define DROP_PACKET_OFF 0 |
| 91 | #define DROP_PACKET_ON 1 |
| 92 | |
| 93 | extern unsigned long hfi1_cap_mask; |
| 94 | #define HFI1_CAP_KGET_MASK(mask, cap) ((mask) & HFI1_CAP_##cap) |
| 95 | #define HFI1_CAP_UGET_MASK(mask, cap) \ |
| 96 | (((mask) >> HFI1_CAP_USER_SHIFT) & HFI1_CAP_##cap) |
| 97 | #define HFI1_CAP_KGET(cap) (HFI1_CAP_KGET_MASK(hfi1_cap_mask, cap)) |
| 98 | #define HFI1_CAP_UGET(cap) (HFI1_CAP_UGET_MASK(hfi1_cap_mask, cap)) |
| 99 | #define HFI1_CAP_IS_KSET(cap) (!!HFI1_CAP_KGET(cap)) |
| 100 | #define HFI1_CAP_IS_USET(cap) (!!HFI1_CAP_UGET(cap)) |
| 101 | #define HFI1_MISC_GET() ((hfi1_cap_mask >> HFI1_CAP_MISC_SHIFT) & \ |
| 102 | HFI1_CAP_MISC_MASK) |
Bryan Morgan | a9c05e3 | 2016-02-03 14:30:49 -0800 | [diff] [blame] | 103 | /* Offline Disabled Reason is 4-bits */ |
| 104 | #define HFI1_ODR_MASK(rsn) ((rsn) & OPA_PI_MASK_OFFLINE_REASON) |
Mike Marciniszyn | 7724105 | 2015-07-30 15:17:43 -0400 | [diff] [blame] | 105 | |
| 106 | /* |
Niranjana Vishwanathapura | 82c2611 | 2015-11-11 00:35:19 -0500 | [diff] [blame] | 107 | * Control context is always 0 and handles the error packets. |
| 108 | * It also handles the VL15 and multicast packets. |
| 109 | */ |
| 110 | #define HFI1_CTRL_CTXT 0 |
| 111 | |
| 112 | /* |
Joel Rosenzweig | 2c5b521 | 2015-12-01 15:38:19 -0500 | [diff] [blame] | 113 | * Driver context will store software counters for each of the events |
| 114 | * associated with these status registers |
| 115 | */ |
| 116 | #define NUM_CCE_ERR_STATUS_COUNTERS 41 |
| 117 | #define NUM_RCV_ERR_STATUS_COUNTERS 64 |
| 118 | #define NUM_MISC_ERR_STATUS_COUNTERS 13 |
| 119 | #define NUM_SEND_PIO_ERR_STATUS_COUNTERS 36 |
| 120 | #define NUM_SEND_DMA_ERR_STATUS_COUNTERS 4 |
| 121 | #define NUM_SEND_EGRESS_ERR_STATUS_COUNTERS 64 |
| 122 | #define NUM_SEND_ERR_STATUS_COUNTERS 3 |
| 123 | #define NUM_SEND_CTXT_ERR_STATUS_COUNTERS 5 |
| 124 | #define NUM_SEND_DMA_ENG_ERR_STATUS_COUNTERS 24 |
| 125 | |
| 126 | /* |
Mike Marciniszyn | 7724105 | 2015-07-30 15:17:43 -0400 | [diff] [blame] | 127 | * per driver stats, either not device nor port-specific, or |
| 128 | * summed over all of the devices and ports. |
| 129 | * They are described by name via ipathfs filesystem, so layout |
| 130 | * and number of elements can change without breaking compatibility. |
| 131 | * If members are added or deleted hfi1_statnames[] in debugfs.c must |
| 132 | * change to match. |
| 133 | */ |
| 134 | struct hfi1_ib_stats { |
| 135 | __u64 sps_ints; /* number of interrupts handled */ |
| 136 | __u64 sps_errints; /* number of error interrupts */ |
| 137 | __u64 sps_txerrs; /* tx-related packet errors */ |
| 138 | __u64 sps_rcverrs; /* non-crc rcv packet errors */ |
| 139 | __u64 sps_hwerrs; /* hardware errors reported (parity, etc.) */ |
| 140 | __u64 sps_nopiobufs; /* no pio bufs avail from kernel */ |
| 141 | __u64 sps_ctxts; /* number of contexts currently open */ |
| 142 | __u64 sps_lenerrs; /* number of kernel packets where RHF != LRH len */ |
| 143 | __u64 sps_buffull; |
| 144 | __u64 sps_hdrfull; |
| 145 | }; |
| 146 | |
| 147 | extern struct hfi1_ib_stats hfi1_stats; |
| 148 | extern const struct pci_error_handlers hfi1_pci_err_handler; |
| 149 | |
| 150 | /* |
| 151 | * First-cut criterion for "device is active" is |
| 152 | * two thousand dwords combined Tx, Rx traffic per |
| 153 | * 5-second interval. SMA packets are 64 dwords, |
| 154 | * and occur "a few per second", presumably each way. |
| 155 | */ |
| 156 | #define HFI1_TRAFFIC_ACTIVE_THRESHOLD (2000) |
| 157 | |
| 158 | /* |
| 159 | * Below contains all data related to a single context (formerly called port). |
| 160 | */ |
| 161 | |
| 162 | #ifdef CONFIG_DEBUG_FS |
| 163 | struct hfi1_opcode_stats_perctx; |
| 164 | #endif |
| 165 | |
Mike Marciniszyn | 7724105 | 2015-07-30 15:17:43 -0400 | [diff] [blame] | 166 | struct ctxt_eager_bufs { |
| 167 | ssize_t size; /* total size of eager buffers */ |
| 168 | u32 count; /* size of buffers array */ |
| 169 | u32 numbufs; /* number of buffers allocated */ |
| 170 | u32 alloced; /* number of rcvarray entries used */ |
| 171 | u32 rcvtid_size; /* size of each eager rcv tid */ |
| 172 | u32 threshold; /* head update threshold */ |
| 173 | struct eager_buffer { |
| 174 | void *addr; |
| 175 | dma_addr_t phys; |
| 176 | ssize_t len; |
| 177 | } *buffers; |
| 178 | struct { |
| 179 | void *addr; |
| 180 | dma_addr_t phys; |
| 181 | } *rcvtids; |
| 182 | }; |
| 183 | |
Mitko Haralanov | a86cd35 | 2016-02-05 11:57:49 -0500 | [diff] [blame] | 184 | struct exp_tid_set { |
| 185 | struct list_head list; |
| 186 | u32 count; |
| 187 | }; |
| 188 | |
Mike Marciniszyn | 7724105 | 2015-07-30 15:17:43 -0400 | [diff] [blame] | 189 | struct hfi1_ctxtdata { |
| 190 | /* shadow the ctxt's RcvCtrl register */ |
| 191 | u64 rcvctrl; |
| 192 | /* rcvhdrq base, needs mmap before useful */ |
| 193 | void *rcvhdrq; |
| 194 | /* kernel virtual address where hdrqtail is updated */ |
| 195 | volatile __le64 *rcvhdrtail_kvaddr; |
| 196 | /* |
| 197 | * Shared page for kernel to signal user processes that send buffers |
| 198 | * need disarming. The process should call HFI1_CMD_DISARM_BUFS |
| 199 | * or HFI1_CMD_ACK_EVENT with IPATH_EVENT_DISARM_BUFS set. |
| 200 | */ |
| 201 | unsigned long *user_event_mask; |
| 202 | /* when waiting for rcv or pioavail */ |
| 203 | wait_queue_head_t wait; |
| 204 | /* rcvhdrq size (for freeing) */ |
| 205 | size_t rcvhdrq_size; |
| 206 | /* number of rcvhdrq entries */ |
| 207 | u16 rcvhdrq_cnt; |
| 208 | /* size of each of the rcvhdrq entries */ |
| 209 | u16 rcvhdrqentsize; |
| 210 | /* mmap of hdrq, must fit in 44 bits */ |
| 211 | dma_addr_t rcvhdrq_phys; |
| 212 | dma_addr_t rcvhdrqtailaddr_phys; |
| 213 | struct ctxt_eager_bufs egrbufs; |
| 214 | /* this receive context's assigned PIO ACK send context */ |
| 215 | struct send_context *sc; |
| 216 | |
| 217 | /* dynamic receive available interrupt timeout */ |
| 218 | u32 rcvavail_timeout; |
| 219 | /* |
| 220 | * number of opens (including slave sub-contexts) on this instance |
| 221 | * (ignoring forks, dup, etc. for now) |
| 222 | */ |
| 223 | int cnt; |
| 224 | /* |
| 225 | * how much space to leave at start of eager TID entries for |
| 226 | * protocol use, on each TID |
| 227 | */ |
| 228 | /* instead of calculating it */ |
| 229 | unsigned ctxt; |
| 230 | /* non-zero if ctxt is being shared. */ |
| 231 | u16 subctxt_cnt; |
| 232 | /* non-zero if ctxt is being shared. */ |
| 233 | u16 subctxt_id; |
| 234 | u8 uuid[16]; |
| 235 | /* job key */ |
| 236 | u16 jkey; |
| 237 | /* number of RcvArray groups for this context. */ |
| 238 | u32 rcv_array_groups; |
| 239 | /* index of first eager TID entry. */ |
| 240 | u32 eager_base; |
| 241 | /* number of expected TID entries */ |
| 242 | u32 expected_count; |
| 243 | /* index of first expected TID entry. */ |
| 244 | u32 expected_base; |
Mitko Haralanov | a86cd35 | 2016-02-05 11:57:49 -0500 | [diff] [blame] | 245 | |
| 246 | struct exp_tid_set tid_group_list; |
| 247 | struct exp_tid_set tid_used_list; |
| 248 | struct exp_tid_set tid_full_list; |
| 249 | |
Mike Marciniszyn | 7724105 | 2015-07-30 15:17:43 -0400 | [diff] [blame] | 250 | /* lock protecting all Expected TID data */ |
Mitko Haralanov | 463e6eb | 2016-02-05 11:57:53 -0500 | [diff] [blame] | 251 | struct mutex exp_lock; |
Mike Marciniszyn | 7724105 | 2015-07-30 15:17:43 -0400 | [diff] [blame] | 252 | /* number of pio bufs for this ctxt (all procs, if shared) */ |
| 253 | u32 piocnt; |
| 254 | /* first pio buffer for this ctxt */ |
| 255 | u32 pio_base; |
| 256 | /* chip offset of PIO buffers for this ctxt */ |
| 257 | u32 piobufs; |
| 258 | /* per-context configuration flags */ |
Niranjana Vishwanathapura | 82c2611 | 2015-11-11 00:35:19 -0500 | [diff] [blame] | 259 | u32 flags; |
Mike Marciniszyn | 7724105 | 2015-07-30 15:17:43 -0400 | [diff] [blame] | 260 | /* per-context event flags for fileops/intr communication */ |
| 261 | unsigned long event_flags; |
| 262 | /* WAIT_RCV that timed out, no interrupt */ |
| 263 | u32 rcvwait_to; |
| 264 | /* WAIT_PIO that timed out, no interrupt */ |
| 265 | u32 piowait_to; |
| 266 | /* WAIT_RCV already happened, no wait */ |
| 267 | u32 rcvnowait; |
| 268 | /* WAIT_PIO already happened, no wait */ |
| 269 | u32 pionowait; |
| 270 | /* total number of polled urgent packets */ |
| 271 | u32 urgent; |
| 272 | /* saved total number of polled urgent packets for poll edge trigger */ |
| 273 | u32 urgent_poll; |
| 274 | /* pid of process using this ctxt */ |
| 275 | pid_t pid; |
| 276 | pid_t subpid[HFI1_MAX_SHARED_CTXTS]; |
| 277 | /* same size as task_struct .comm[], command that opened context */ |
Geliang Tang | c3af8a2 | 2015-10-08 22:04:26 -0700 | [diff] [blame] | 278 | char comm[TASK_COMM_LEN]; |
Mike Marciniszyn | 7724105 | 2015-07-30 15:17:43 -0400 | [diff] [blame] | 279 | /* so file ops can get at unit */ |
| 280 | struct hfi1_devdata *dd; |
| 281 | /* so functions that need physical port can get it easily */ |
| 282 | struct hfi1_pportdata *ppd; |
| 283 | /* A page of memory for rcvhdrhead, rcvegrhead, rcvegrtail * N */ |
| 284 | void *subctxt_uregbase; |
| 285 | /* An array of pages for the eager receive buffers * N */ |
| 286 | void *subctxt_rcvegrbuf; |
| 287 | /* An array of pages for the eager header queue entries * N */ |
| 288 | void *subctxt_rcvhdr_base; |
| 289 | /* The version of the library which opened this ctxt */ |
| 290 | u32 userversion; |
| 291 | /* Bitmask of active slaves */ |
| 292 | u32 active_slaves; |
| 293 | /* Type of packets or conditions we want to poll for */ |
| 294 | u16 poll_type; |
| 295 | /* receive packet sequence counter */ |
| 296 | u8 seq_cnt; |
| 297 | u8 redirect_seq_cnt; |
| 298 | /* ctxt rcvhdrq head offset */ |
| 299 | u32 head; |
| 300 | u32 pkt_count; |
| 301 | /* QPs waiting for context processing */ |
| 302 | struct list_head qp_wait_list; |
| 303 | /* interrupt handling */ |
| 304 | u64 imask; /* clear interrupt mask */ |
| 305 | int ireg; /* clear interrupt register */ |
| 306 | unsigned numa_id; /* numa node of this context */ |
| 307 | /* verbs stats per CTX */ |
| 308 | struct hfi1_opcode_stats_perctx *opstats; |
| 309 | /* |
| 310 | * This is the kernel thread that will keep making |
| 311 | * progress on the user sdma requests behind the scenes. |
| 312 | * There is one per context (shared contexts use the master's). |
| 313 | */ |
| 314 | struct task_struct *progress; |
| 315 | struct list_head sdma_queues; |
| 316 | spinlock_t sdma_qlock; |
| 317 | |
Ashutosh Dixit | affa48d | 2016-02-03 14:33:06 -0800 | [diff] [blame] | 318 | /* Is ASPM interrupt supported for this context */ |
| 319 | bool aspm_intr_supported; |
| 320 | /* ASPM state (enabled/disabled) for this context */ |
| 321 | bool aspm_enabled; |
| 322 | /* Timer for re-enabling ASPM if interrupt activity quietens down */ |
| 323 | struct timer_list aspm_timer; |
| 324 | /* Lock to serialize between intr, timer intr and user threads */ |
| 325 | spinlock_t aspm_lock; |
| 326 | /* Is ASPM processing enabled for this context (in intr context) */ |
| 327 | bool aspm_intr_enable; |
| 328 | /* Last interrupt timestamp */ |
| 329 | ktime_t aspm_ts_last_intr; |
| 330 | /* Last timestamp at which we scheduled a timer for this context */ |
| 331 | ktime_t aspm_ts_timer_sched; |
| 332 | |
Mike Marciniszyn | 7724105 | 2015-07-30 15:17:43 -0400 | [diff] [blame] | 333 | /* |
| 334 | * The interrupt handler for a particular receive context can vary |
| 335 | * throughout it's lifetime. This is not a lock protected data member so |
| 336 | * it must be updated atomically and the prev and new value must always |
| 337 | * be valid. Worst case is we process an extra interrupt and up to 64 |
| 338 | * packets with the wrong interrupt handler. |
| 339 | */ |
Dean Luick | f4f30031c | 2015-10-26 10:28:44 -0400 | [diff] [blame] | 340 | int (*do_interrupt)(struct hfi1_ctxtdata *rcd, int threaded); |
Mike Marciniszyn | 7724105 | 2015-07-30 15:17:43 -0400 | [diff] [blame] | 341 | }; |
| 342 | |
| 343 | /* |
| 344 | * Represents a single packet at a high level. Put commonly computed things in |
| 345 | * here so we do not have to keep doing them over and over. The rule of thumb is |
| 346 | * if something is used one time to derive some value, store that something in |
| 347 | * here. If it is used multiple times, then store the result of that derivation |
| 348 | * in here. |
| 349 | */ |
| 350 | struct hfi1_packet { |
| 351 | void *ebuf; |
| 352 | void *hdr; |
| 353 | struct hfi1_ctxtdata *rcd; |
| 354 | __le32 *rhf_addr; |
Dennis Dalessandro | 895420d | 2016-01-19 14:42:28 -0800 | [diff] [blame] | 355 | struct rvt_qp *qp; |
Mike Marciniszyn | 7724105 | 2015-07-30 15:17:43 -0400 | [diff] [blame] | 356 | struct hfi1_other_headers *ohdr; |
| 357 | u64 rhf; |
| 358 | u32 maxcnt; |
| 359 | u32 rhqoff; |
| 360 | u32 hdrqtail; |
| 361 | int numpkt; |
| 362 | u16 tlen; |
| 363 | u16 hlen; |
| 364 | s16 etail; |
| 365 | u16 rsize; |
| 366 | u8 updegr; |
| 367 | u8 rcv_flags; |
| 368 | u8 etype; |
| 369 | }; |
| 370 | |
| 371 | static inline bool has_sc4_bit(struct hfi1_packet *p) |
| 372 | { |
| 373 | return !!rhf_dc_info(p->rhf); |
| 374 | } |
| 375 | |
| 376 | /* |
| 377 | * Private data for snoop/capture support. |
| 378 | */ |
| 379 | struct hfi1_snoop_data { |
| 380 | int mode_flag; |
| 381 | struct cdev cdev; |
| 382 | struct device *class_dev; |
| 383 | spinlock_t snoop_lock; |
| 384 | struct list_head queue; |
| 385 | wait_queue_head_t waitq; |
| 386 | void *filter_value; |
| 387 | int (*filter_callback)(void *hdr, void *data, void *value); |
| 388 | u64 dcc_cfg; /* saved value of DCC Cfg register */ |
| 389 | }; |
| 390 | |
| 391 | /* snoop mode_flag values */ |
| 392 | #define HFI1_PORT_SNOOP_MODE 1U |
| 393 | #define HFI1_PORT_CAPTURE_MODE 2U |
| 394 | |
Dennis Dalessandro | 895420d | 2016-01-19 14:42:28 -0800 | [diff] [blame] | 395 | struct rvt_sge_state; |
Mike Marciniszyn | 7724105 | 2015-07-30 15:17:43 -0400 | [diff] [blame] | 396 | |
| 397 | /* |
| 398 | * Get/Set IB link-level config parameters for f_get/set_ib_cfg() |
| 399 | * Mostly for MADs that set or query link parameters, also ipath |
| 400 | * config interfaces |
| 401 | */ |
| 402 | #define HFI1_IB_CFG_LIDLMC 0 /* LID (LS16b) and Mask (MS16b) */ |
| 403 | #define HFI1_IB_CFG_LWID_DG_ENB 1 /* allowed Link-width downgrade */ |
| 404 | #define HFI1_IB_CFG_LWID_ENB 2 /* allowed Link-width */ |
| 405 | #define HFI1_IB_CFG_LWID 3 /* currently active Link-width */ |
| 406 | #define HFI1_IB_CFG_SPD_ENB 4 /* allowed Link speeds */ |
| 407 | #define HFI1_IB_CFG_SPD 5 /* current Link spd */ |
| 408 | #define HFI1_IB_CFG_RXPOL_ENB 6 /* Auto-RX-polarity enable */ |
| 409 | #define HFI1_IB_CFG_LREV_ENB 7 /* Auto-Lane-reversal enable */ |
| 410 | #define HFI1_IB_CFG_LINKLATENCY 8 /* Link Latency (IB1.2 only) */ |
| 411 | #define HFI1_IB_CFG_HRTBT 9 /* IB heartbeat off/enable/auto; DDR/QDR only */ |
| 412 | #define HFI1_IB_CFG_OP_VLS 10 /* operational VLs */ |
| 413 | #define HFI1_IB_CFG_VL_HIGH_CAP 11 /* num of VL high priority weights */ |
| 414 | #define HFI1_IB_CFG_VL_LOW_CAP 12 /* num of VL low priority weights */ |
| 415 | #define HFI1_IB_CFG_OVERRUN_THRESH 13 /* IB overrun threshold */ |
| 416 | #define HFI1_IB_CFG_PHYERR_THRESH 14 /* IB PHY error threshold */ |
| 417 | #define HFI1_IB_CFG_LINKDEFAULT 15 /* IB link default (sleep/poll) */ |
| 418 | #define HFI1_IB_CFG_PKEYS 16 /* update partition keys */ |
| 419 | #define HFI1_IB_CFG_MTU 17 /* update MTU in IBC */ |
| 420 | #define HFI1_IB_CFG_VL_HIGH_LIMIT 19 |
| 421 | #define HFI1_IB_CFG_PMA_TICKS 20 /* PMA sample tick resolution */ |
| 422 | #define HFI1_IB_CFG_PORT 21 /* switch port we are connected to */ |
| 423 | |
| 424 | /* |
| 425 | * HFI or Host Link States |
| 426 | * |
| 427 | * These describe the states the driver thinks the logical and physical |
| 428 | * states are in. Used as an argument to set_link_state(). Implemented |
| 429 | * as bits for easy multi-state checking. The actual state can only be |
| 430 | * one. |
| 431 | */ |
| 432 | #define __HLS_UP_INIT_BP 0 |
| 433 | #define __HLS_UP_ARMED_BP 1 |
| 434 | #define __HLS_UP_ACTIVE_BP 2 |
| 435 | #define __HLS_DN_DOWNDEF_BP 3 /* link down default */ |
| 436 | #define __HLS_DN_POLL_BP 4 |
| 437 | #define __HLS_DN_DISABLE_BP 5 |
| 438 | #define __HLS_DN_OFFLINE_BP 6 |
| 439 | #define __HLS_VERIFY_CAP_BP 7 |
| 440 | #define __HLS_GOING_UP_BP 8 |
| 441 | #define __HLS_GOING_OFFLINE_BP 9 |
| 442 | #define __HLS_LINK_COOLDOWN_BP 10 |
| 443 | |
jubin.john@intel.com | 349ac71 | 2016-01-11 18:30:52 -0500 | [diff] [blame] | 444 | #define HLS_UP_INIT BIT(__HLS_UP_INIT_BP) |
| 445 | #define HLS_UP_ARMED BIT(__HLS_UP_ARMED_BP) |
| 446 | #define HLS_UP_ACTIVE BIT(__HLS_UP_ACTIVE_BP) |
| 447 | #define HLS_DN_DOWNDEF BIT(__HLS_DN_DOWNDEF_BP) /* link down default */ |
| 448 | #define HLS_DN_POLL BIT(__HLS_DN_POLL_BP) |
| 449 | #define HLS_DN_DISABLE BIT(__HLS_DN_DISABLE_BP) |
| 450 | #define HLS_DN_OFFLINE BIT(__HLS_DN_OFFLINE_BP) |
| 451 | #define HLS_VERIFY_CAP BIT(__HLS_VERIFY_CAP_BP) |
| 452 | #define HLS_GOING_UP BIT(__HLS_GOING_UP_BP) |
| 453 | #define HLS_GOING_OFFLINE BIT(__HLS_GOING_OFFLINE_BP) |
| 454 | #define HLS_LINK_COOLDOWN BIT(__HLS_LINK_COOLDOWN_BP) |
Mike Marciniszyn | 7724105 | 2015-07-30 15:17:43 -0400 | [diff] [blame] | 455 | |
| 456 | #define HLS_UP (HLS_UP_INIT | HLS_UP_ARMED | HLS_UP_ACTIVE) |
| 457 | |
| 458 | /* use this MTU size if none other is given */ |
| 459 | #define HFI1_DEFAULT_ACTIVE_MTU 8192 |
| 460 | /* use this MTU size as the default maximum */ |
| 461 | #define HFI1_DEFAULT_MAX_MTU 8192 |
| 462 | /* default partition key */ |
| 463 | #define DEFAULT_PKEY 0xffff |
| 464 | |
| 465 | /* |
| 466 | * Possible fabric manager config parameters for fm_{get,set}_table() |
| 467 | */ |
| 468 | #define FM_TBL_VL_HIGH_ARB 1 /* Get/set VL high prio weights */ |
| 469 | #define FM_TBL_VL_LOW_ARB 2 /* Get/set VL low prio weights */ |
| 470 | #define FM_TBL_BUFFER_CONTROL 3 /* Get/set Buffer Control */ |
| 471 | #define FM_TBL_SC2VLNT 4 /* Get/set SC->VLnt */ |
| 472 | #define FM_TBL_VL_PREEMPT_ELEMS 5 /* Get (no set) VL preempt elems */ |
| 473 | #define FM_TBL_VL_PREEMPT_MATRIX 6 /* Get (no set) VL preempt matrix */ |
| 474 | |
| 475 | /* |
| 476 | * Possible "operations" for f_rcvctrl(ppd, op, ctxt) |
| 477 | * these are bits so they can be combined, e.g. |
| 478 | * HFI1_RCVCTRL_INTRAVAIL_ENB | HFI1_RCVCTRL_CTXT_ENB |
| 479 | */ |
| 480 | #define HFI1_RCVCTRL_TAILUPD_ENB 0x01 |
| 481 | #define HFI1_RCVCTRL_TAILUPD_DIS 0x02 |
| 482 | #define HFI1_RCVCTRL_CTXT_ENB 0x04 |
| 483 | #define HFI1_RCVCTRL_CTXT_DIS 0x08 |
| 484 | #define HFI1_RCVCTRL_INTRAVAIL_ENB 0x10 |
| 485 | #define HFI1_RCVCTRL_INTRAVAIL_DIS 0x20 |
| 486 | #define HFI1_RCVCTRL_PKEY_ENB 0x40 /* Note, default is enabled */ |
| 487 | #define HFI1_RCVCTRL_PKEY_DIS 0x80 |
| 488 | #define HFI1_RCVCTRL_TIDFLOW_ENB 0x0400 |
| 489 | #define HFI1_RCVCTRL_TIDFLOW_DIS 0x0800 |
| 490 | #define HFI1_RCVCTRL_ONE_PKT_EGR_ENB 0x1000 |
| 491 | #define HFI1_RCVCTRL_ONE_PKT_EGR_DIS 0x2000 |
| 492 | #define HFI1_RCVCTRL_NO_RHQ_DROP_ENB 0x4000 |
| 493 | #define HFI1_RCVCTRL_NO_RHQ_DROP_DIS 0x8000 |
| 494 | #define HFI1_RCVCTRL_NO_EGR_DROP_ENB 0x10000 |
| 495 | #define HFI1_RCVCTRL_NO_EGR_DROP_DIS 0x20000 |
| 496 | |
| 497 | /* partition enforcement flags */ |
| 498 | #define HFI1_PART_ENFORCE_IN 0x1 |
| 499 | #define HFI1_PART_ENFORCE_OUT 0x2 |
| 500 | |
| 501 | /* how often we check for synthetic counter wrap around */ |
| 502 | #define SYNTH_CNT_TIME 2 |
| 503 | |
| 504 | /* Counter flags */ |
| 505 | #define CNTR_NORMAL 0x0 /* Normal counters, just read register */ |
| 506 | #define CNTR_SYNTH 0x1 /* Synthetic counters, saturate at all 1s */ |
| 507 | #define CNTR_DISABLED 0x2 /* Disable this counter */ |
| 508 | #define CNTR_32BIT 0x4 /* Simulate 64 bits for this counter */ |
| 509 | #define CNTR_VL 0x8 /* Per VL counter */ |
Vennila Megavannan | a699c6c | 2016-01-11 18:30:56 -0500 | [diff] [blame] | 510 | #define CNTR_SDMA 0x10 |
Mike Marciniszyn | 7724105 | 2015-07-30 15:17:43 -0400 | [diff] [blame] | 511 | #define CNTR_INVALID_VL -1 /* Specifies invalid VL */ |
| 512 | #define CNTR_MODE_W 0x0 |
| 513 | #define CNTR_MODE_R 0x1 |
| 514 | |
| 515 | /* VLs Supported/Operational */ |
| 516 | #define HFI1_MIN_VLS_SUPPORTED 1 |
| 517 | #define HFI1_MAX_VLS_SUPPORTED 8 |
| 518 | |
| 519 | static inline void incr_cntr64(u64 *cntr) |
| 520 | { |
| 521 | if (*cntr < (u64)-1LL) |
| 522 | (*cntr)++; |
| 523 | } |
| 524 | |
| 525 | static inline void incr_cntr32(u32 *cntr) |
| 526 | { |
| 527 | if (*cntr < (u32)-1LL) |
| 528 | (*cntr)++; |
| 529 | } |
| 530 | |
| 531 | #define MAX_NAME_SIZE 64 |
| 532 | struct hfi1_msix_entry { |
Mitko Haralanov | 957558c | 2016-02-03 14:33:40 -0800 | [diff] [blame] | 533 | enum irq_type type; |
Mike Marciniszyn | 7724105 | 2015-07-30 15:17:43 -0400 | [diff] [blame] | 534 | struct msix_entry msix; |
| 535 | void *arg; |
| 536 | char name[MAX_NAME_SIZE]; |
Mitko Haralanov | 957558c | 2016-02-03 14:33:40 -0800 | [diff] [blame] | 537 | cpumask_t mask; |
Mike Marciniszyn | 7724105 | 2015-07-30 15:17:43 -0400 | [diff] [blame] | 538 | }; |
| 539 | |
| 540 | /* per-SL CCA information */ |
| 541 | struct cca_timer { |
| 542 | struct hrtimer hrtimer; |
| 543 | struct hfi1_pportdata *ppd; /* read-only */ |
| 544 | int sl; /* read-only */ |
| 545 | u16 ccti; /* read/write - current value of CCTI */ |
| 546 | }; |
| 547 | |
| 548 | struct link_down_reason { |
| 549 | /* |
| 550 | * SMA-facing value. Should be set from .latest when |
| 551 | * HLS_UP_* -> HLS_DN_* transition actually occurs. |
| 552 | */ |
| 553 | u8 sma; |
| 554 | u8 latest; |
| 555 | }; |
| 556 | |
| 557 | enum { |
| 558 | LO_PRIO_TABLE, |
| 559 | HI_PRIO_TABLE, |
| 560 | MAX_PRIO_TABLE |
| 561 | }; |
| 562 | |
| 563 | struct vl_arb_cache { |
| 564 | spinlock_t lock; |
| 565 | struct ib_vl_weight_elem table[VL_ARB_TABLE_SIZE]; |
| 566 | }; |
| 567 | |
| 568 | /* |
| 569 | * The structure below encapsulates data relevant to a physical IB Port. |
| 570 | * Current chips support only one such port, but the separation |
| 571 | * clarifies things a bit. Note that to conform to IB conventions, |
| 572 | * port-numbers are one-based. The first or only port is port1. |
| 573 | */ |
| 574 | struct hfi1_pportdata { |
| 575 | struct hfi1_ibport ibport_data; |
| 576 | |
| 577 | struct hfi1_devdata *dd; |
| 578 | struct kobject pport_cc_kobj; |
| 579 | struct kobject sc2vl_kobj; |
| 580 | struct kobject sl2sc_kobj; |
| 581 | struct kobject vl2mtu_kobj; |
| 582 | |
Easwar Hariharan | 8ebd4cf | 2016-02-03 14:31:14 -0800 | [diff] [blame] | 583 | /* PHY support */ |
| 584 | u32 port_type; |
Mike Marciniszyn | 7724105 | 2015-07-30 15:17:43 -0400 | [diff] [blame] | 585 | struct qsfp_data qsfp_info; |
| 586 | |
| 587 | /* GUID for this interface, in host order */ |
| 588 | u64 guid; |
| 589 | /* GUID for peer interface, in host order */ |
| 590 | u64 neighbor_guid; |
| 591 | |
| 592 | /* up or down physical link state */ |
| 593 | u32 linkup; |
| 594 | |
| 595 | /* |
| 596 | * this address is mapped read-only into user processes so they can |
| 597 | * get status cheaply, whenever they want. One qword of status per port |
| 598 | */ |
| 599 | u64 *statusp; |
| 600 | |
| 601 | /* SendDMA related entries */ |
| 602 | |
| 603 | struct workqueue_struct *hfi1_wq; |
| 604 | |
| 605 | /* move out of interrupt context */ |
| 606 | struct work_struct link_vc_work; |
| 607 | struct work_struct link_up_work; |
| 608 | struct work_struct link_down_work; |
Easwar Hariharan | cbac386 | 2016-02-03 14:31:31 -0800 | [diff] [blame] | 609 | struct work_struct dc_host_req_work; |
Mike Marciniszyn | 7724105 | 2015-07-30 15:17:43 -0400 | [diff] [blame] | 610 | struct work_struct sma_message_work; |
| 611 | struct work_struct freeze_work; |
| 612 | struct work_struct link_downgrade_work; |
| 613 | struct work_struct link_bounce_work; |
| 614 | /* host link state variables */ |
| 615 | struct mutex hls_lock; |
| 616 | u32 host_link_state; |
| 617 | |
| 618 | spinlock_t sdma_alllock ____cacheline_aligned_in_smp; |
| 619 | |
| 620 | u32 lstate; /* logical link state */ |
| 621 | |
| 622 | /* these are the "32 bit" regs */ |
| 623 | |
| 624 | u32 ibmtu; /* The MTU programmed for this unit */ |
| 625 | /* |
| 626 | * Current max size IB packet (in bytes) including IB headers, that |
| 627 | * we can send. Changes when ibmtu changes. |
| 628 | */ |
| 629 | u32 ibmaxlen; |
| 630 | u32 current_egress_rate; /* units [10^6 bits/sec] */ |
| 631 | /* LID programmed for this instance */ |
| 632 | u16 lid; |
| 633 | /* list of pkeys programmed; 0 if not set */ |
| 634 | u16 pkeys[MAX_PKEY_VALUES]; |
| 635 | u16 link_width_supported; |
| 636 | u16 link_width_downgrade_supported; |
| 637 | u16 link_speed_supported; |
| 638 | u16 link_width_enabled; |
| 639 | u16 link_width_downgrade_enabled; |
| 640 | u16 link_speed_enabled; |
| 641 | u16 link_width_active; |
| 642 | u16 link_width_downgrade_tx_active; |
| 643 | u16 link_width_downgrade_rx_active; |
| 644 | u16 link_speed_active; |
| 645 | u8 vls_supported; |
| 646 | u8 vls_operational; |
Mike Marciniszyn | 8a4d344 | 2016-02-14 12:46:01 -0800 | [diff] [blame] | 647 | u8 actual_vls_operational; |
Mike Marciniszyn | 7724105 | 2015-07-30 15:17:43 -0400 | [diff] [blame] | 648 | /* LID mask control */ |
| 649 | u8 lmc; |
| 650 | /* Rx Polarity inversion (compensate for ~tx on partner) */ |
| 651 | u8 rx_pol_inv; |
| 652 | |
| 653 | u8 hw_pidx; /* physical port index */ |
| 654 | u8 port; /* IB port number and index into dd->pports - 1 */ |
| 655 | /* type of neighbor node */ |
| 656 | u8 neighbor_type; |
| 657 | u8 neighbor_normal; |
| 658 | u8 neighbor_fm_security; /* 1 if firmware checking is disabled */ |
| 659 | u8 neighbor_port_number; |
| 660 | u8 is_sm_config_started; |
| 661 | u8 offline_disabled_reason; |
| 662 | u8 is_active_optimize_enabled; |
| 663 | u8 driver_link_ready; /* driver ready for active link */ |
| 664 | u8 link_enabled; /* link enabled? */ |
| 665 | u8 linkinit_reason; |
| 666 | u8 local_tx_rate; /* rate given to 8051 firmware */ |
Dean Luick | f45c8dc | 2016-02-03 14:35:31 -0800 | [diff] [blame] | 667 | u8 last_pstate; /* info only */ |
Mike Marciniszyn | 7724105 | 2015-07-30 15:17:43 -0400 | [diff] [blame] | 668 | |
| 669 | /* placeholders for IB MAD packet settings */ |
| 670 | u8 overrun_threshold; |
| 671 | u8 phy_error_threshold; |
| 672 | |
Easwar Hariharan | 91ab4ed | 2016-02-03 14:35:57 -0800 | [diff] [blame] | 673 | /* Used to override LED behavior for things like maintenance beaconing*/ |
| 674 | /* |
| 675 | * Alternates per phase of blink |
| 676 | * [0] holds LED off duration, [1] holds LED on duration |
| 677 | */ |
| 678 | unsigned long led_override_vals[2]; |
| 679 | u8 led_override_phase; /* LSB picks from vals[] */ |
Mike Marciniszyn | 7724105 | 2015-07-30 15:17:43 -0400 | [diff] [blame] | 680 | atomic_t led_override_timer_active; |
| 681 | /* Used to flash LEDs in override mode */ |
| 682 | struct timer_list led_override_timer; |
Easwar Hariharan | 91ab4ed | 2016-02-03 14:35:57 -0800 | [diff] [blame] | 683 | |
Mike Marciniszyn | 7724105 | 2015-07-30 15:17:43 -0400 | [diff] [blame] | 684 | u32 sm_trap_qp; |
| 685 | u32 sa_qp; |
| 686 | |
| 687 | /* |
| 688 | * cca_timer_lock protects access to the per-SL cca_timer |
| 689 | * structures (specifically the ccti member). |
| 690 | */ |
| 691 | spinlock_t cca_timer_lock ____cacheline_aligned_in_smp; |
| 692 | struct cca_timer cca_timer[OPA_MAX_SLS]; |
| 693 | |
| 694 | /* List of congestion control table entries */ |
| 695 | struct ib_cc_table_entry_shadow ccti_entries[CC_TABLE_SHADOW_MAX]; |
| 696 | |
| 697 | /* congestion entries, each entry corresponding to a SL */ |
| 698 | struct opa_congestion_setting_entry_shadow |
| 699 | congestion_entries[OPA_MAX_SLS]; |
| 700 | |
| 701 | /* |
| 702 | * cc_state_lock protects (write) access to the per-port |
| 703 | * struct cc_state. |
| 704 | */ |
| 705 | spinlock_t cc_state_lock ____cacheline_aligned_in_smp; |
| 706 | |
| 707 | struct cc_state __rcu *cc_state; |
| 708 | |
| 709 | /* Total number of congestion control table entries */ |
| 710 | u16 total_cct_entry; |
| 711 | |
| 712 | /* Bit map identifying service level */ |
| 713 | u32 cc_sl_control_map; |
| 714 | |
| 715 | /* CA's max number of 64 entry units in the congestion control table */ |
| 716 | u8 cc_max_table_entries; |
| 717 | |
| 718 | /* begin congestion log related entries |
| 719 | * cc_log_lock protects all congestion log related data */ |
| 720 | spinlock_t cc_log_lock ____cacheline_aligned_in_smp; |
Jubin John | 8638b77 | 2016-02-14 20:19:24 -0800 | [diff] [blame] | 721 | u8 threshold_cong_event_map[OPA_MAX_SLS / 8]; |
Mike Marciniszyn | 7724105 | 2015-07-30 15:17:43 -0400 | [diff] [blame] | 722 | u16 threshold_event_counter; |
| 723 | struct opa_hfi1_cong_log_event_internal cc_events[OPA_CONG_LOG_ELEMS]; |
| 724 | int cc_log_idx; /* index for logging events */ |
| 725 | int cc_mad_idx; /* index for reporting events */ |
| 726 | /* end congestion log related entries */ |
| 727 | |
| 728 | struct vl_arb_cache vl_arb_cache[MAX_PRIO_TABLE]; |
| 729 | |
| 730 | /* port relative counter buffer */ |
| 731 | u64 *cntrs; |
| 732 | /* port relative synthetic counter buffer */ |
| 733 | u64 *scntrs; |
Mike Marciniszyn | 69a00b8 | 2016-02-03 14:31:49 -0800 | [diff] [blame] | 734 | /* port_xmit_discards are synthesized from different egress errors */ |
Mike Marciniszyn | 7724105 | 2015-07-30 15:17:43 -0400 | [diff] [blame] | 735 | u64 port_xmit_discards; |
Mike Marciniszyn | 69a00b8 | 2016-02-03 14:31:49 -0800 | [diff] [blame] | 736 | u64 port_xmit_discards_vl[C_VL_COUNT]; |
Mike Marciniszyn | 7724105 | 2015-07-30 15:17:43 -0400 | [diff] [blame] | 737 | u64 port_xmit_constraint_errors; |
| 738 | u64 port_rcv_constraint_errors; |
| 739 | /* count of 'link_err' interrupts from DC */ |
| 740 | u64 link_downed; |
| 741 | /* number of times link retrained successfully */ |
| 742 | u64 link_up; |
Dean Luick | 6d01453 | 2015-12-01 15:38:23 -0500 | [diff] [blame] | 743 | /* number of times a link unknown frame was reported */ |
| 744 | u64 unknown_frame_count; |
Mike Marciniszyn | 7724105 | 2015-07-30 15:17:43 -0400 | [diff] [blame] | 745 | /* port_ltp_crc_mode is returned in 'portinfo' MADs */ |
| 746 | u16 port_ltp_crc_mode; |
| 747 | /* port_crc_mode_enabled is the crc we support */ |
| 748 | u8 port_crc_mode_enabled; |
| 749 | /* mgmt_allowed is also returned in 'portinfo' MADs */ |
| 750 | u8 mgmt_allowed; |
| 751 | u8 part_enforce; /* partition enforcement flags */ |
| 752 | struct link_down_reason local_link_down_reason; |
| 753 | struct link_down_reason neigh_link_down_reason; |
| 754 | /* Value to be sent to link peer on LinkDown .*/ |
| 755 | u8 remote_link_down_reason; |
| 756 | /* Error events that will cause a port bounce. */ |
| 757 | u32 port_error_action; |
Jim Snow | fb9036d | 2016-01-11 18:32:21 -0500 | [diff] [blame] | 758 | struct work_struct linkstate_active_work; |
Vennila Megavannan | 6c9e50f | 2016-02-03 14:32:57 -0800 | [diff] [blame] | 759 | /* Does this port need to prescan for FECNs */ |
| 760 | bool cc_prescan; |
Mike Marciniszyn | 7724105 | 2015-07-30 15:17:43 -0400 | [diff] [blame] | 761 | }; |
| 762 | |
| 763 | typedef int (*rhf_rcv_function_ptr)(struct hfi1_packet *packet); |
| 764 | |
| 765 | typedef void (*opcode_handler)(struct hfi1_packet *packet); |
| 766 | |
| 767 | /* return values for the RHF receive functions */ |
| 768 | #define RHF_RCV_CONTINUE 0 /* keep going */ |
| 769 | #define RHF_RCV_DONE 1 /* stop, this packet processed */ |
| 770 | #define RHF_RCV_REPROCESS 2 /* stop. retain this packet */ |
| 771 | |
| 772 | struct rcv_array_data { |
| 773 | u8 group_size; |
| 774 | u16 ngroups; |
| 775 | u16 nctxt_extra; |
| 776 | }; |
| 777 | |
| 778 | struct per_vl_data { |
| 779 | u16 mtu; |
| 780 | struct send_context *sc; |
| 781 | }; |
| 782 | |
| 783 | /* 16 to directly index */ |
| 784 | #define PER_VL_SEND_CONTEXTS 16 |
| 785 | |
| 786 | struct err_info_rcvport { |
| 787 | u8 status_and_code; |
| 788 | u64 packet_flit1; |
| 789 | u64 packet_flit2; |
| 790 | }; |
| 791 | |
| 792 | struct err_info_constraint { |
| 793 | u8 status; |
| 794 | u16 pkey; |
| 795 | u32 slid; |
| 796 | }; |
| 797 | |
| 798 | struct hfi1_temp { |
| 799 | unsigned int curr; /* current temperature */ |
| 800 | unsigned int lo_lim; /* low temperature limit */ |
| 801 | unsigned int hi_lim; /* high temperature limit */ |
| 802 | unsigned int crit_lim; /* critical temperature limit */ |
| 803 | u8 triggers; /* temperature triggers */ |
| 804 | }; |
| 805 | |
| 806 | /* device data struct now contains only "general per-device" info. |
| 807 | * fields related to a physical IB port are in a hfi1_pportdata struct. |
| 808 | */ |
| 809 | struct sdma_engine; |
| 810 | struct sdma_vl_map; |
| 811 | |
| 812 | #define BOARD_VERS_MAX 96 /* how long the version string can be */ |
| 813 | #define SERIAL_MAX 16 /* length of the serial number */ |
| 814 | |
Mike Marciniszyn | 14553ca | 2016-02-14 12:45:36 -0800 | [diff] [blame] | 815 | typedef int (*send_routine)(struct rvt_qp *, struct hfi1_pkt_state *, u64); |
Mike Marciniszyn | 7724105 | 2015-07-30 15:17:43 -0400 | [diff] [blame] | 816 | struct hfi1_devdata { |
| 817 | struct hfi1_ibdev verbs_dev; /* must be first */ |
| 818 | struct list_head list; |
| 819 | /* pointers to related structs for this device */ |
| 820 | /* pci access data structure */ |
| 821 | struct pci_dev *pcidev; |
| 822 | struct cdev user_cdev; |
| 823 | struct cdev diag_cdev; |
| 824 | struct cdev ui_cdev; |
| 825 | struct device *user_device; |
| 826 | struct device *diag_device; |
| 827 | struct device *ui_device; |
| 828 | |
| 829 | /* mem-mapped pointer to base of chip regs */ |
| 830 | u8 __iomem *kregbase; |
| 831 | /* end of mem-mapped chip space excluding sendbuf and user regs */ |
| 832 | u8 __iomem *kregend; |
| 833 | /* physical address of chip for io_remap, etc. */ |
| 834 | resource_size_t physaddr; |
| 835 | /* receive context data */ |
| 836 | struct hfi1_ctxtdata **rcd; |
| 837 | /* send context data */ |
| 838 | struct send_context_info *send_contexts; |
| 839 | /* map hardware send contexts to software index */ |
| 840 | u8 *hw_to_sw; |
| 841 | /* spinlock for allocating and releasing send context resources */ |
| 842 | spinlock_t sc_lock; |
| 843 | /* Per VL data. Enough for all VLs but not all elements are set/used. */ |
| 844 | struct per_vl_data vld[PER_VL_SEND_CONTEXTS]; |
Jubin John | 35f6bef | 2016-02-14 12:46:10 -0800 | [diff] [blame] | 845 | /* lock for pio_map */ |
| 846 | spinlock_t pio_map_lock; |
| 847 | /* array of kernel send contexts */ |
| 848 | struct send_context **kernel_send_context; |
| 849 | /* array of vl maps */ |
| 850 | struct pio_vl_map __rcu *pio_map; |
Mike Marciniszyn | 7724105 | 2015-07-30 15:17:43 -0400 | [diff] [blame] | 851 | /* seqlock for sc2vl */ |
| 852 | seqlock_t sc2vl_lock; |
| 853 | u64 sc2vl[4]; |
| 854 | /* Send Context initialization lock. */ |
| 855 | spinlock_t sc_init_lock; |
| 856 | |
| 857 | /* fields common to all SDMA engines */ |
| 858 | |
| 859 | /* default flags to last descriptor */ |
| 860 | u64 default_desc1; |
| 861 | volatile __le64 *sdma_heads_dma; /* DMA'ed by chip */ |
| 862 | dma_addr_t sdma_heads_phys; |
| 863 | void *sdma_pad_dma; /* DMA'ed by chip */ |
| 864 | dma_addr_t sdma_pad_phys; |
| 865 | /* for deallocation */ |
| 866 | size_t sdma_heads_size; |
| 867 | /* number from the chip */ |
| 868 | u32 chip_sdma_engines; |
| 869 | /* num used */ |
| 870 | u32 num_sdma; |
| 871 | /* lock for sdma_map */ |
| 872 | spinlock_t sde_map_lock; |
| 873 | /* array of engines sized by num_sdma */ |
| 874 | struct sdma_engine *per_sdma; |
| 875 | /* array of vl maps */ |
| 876 | struct sdma_vl_map __rcu *sdma_map; |
| 877 | /* SPC freeze waitqueue and variable */ |
| 878 | wait_queue_head_t sdma_unfreeze_wq; |
| 879 | atomic_t sdma_unfreeze_count; |
| 880 | |
Mike Marciniszyn | 7724105 | 2015-07-30 15:17:43 -0400 | [diff] [blame] | 881 | /* hfi1_pportdata, points to array of (physical) port-specific |
| 882 | * data structs, indexed by pidx (0..n-1) |
| 883 | */ |
| 884 | struct hfi1_pportdata *pport; |
| 885 | |
| 886 | /* mem-mapped pointer to base of PIO buffers */ |
| 887 | void __iomem *piobase; |
| 888 | /* |
| 889 | * write-combining mem-mapped pointer to base of RcvArray |
| 890 | * memory. |
| 891 | */ |
| 892 | void __iomem *rcvarray_wc; |
| 893 | /* |
| 894 | * credit return base - a per-NUMA range of DMA address that |
| 895 | * the chip will use to update the per-context free counter |
| 896 | */ |
| 897 | struct credit_return_base *cr_base; |
| 898 | |
| 899 | /* send context numbers and sizes for each type */ |
| 900 | struct sc_config_sizes sc_sizes[SC_MAX]; |
| 901 | |
| 902 | u32 lcb_access_count; /* count of LCB users */ |
| 903 | |
| 904 | char *boardname; /* human readable board info */ |
| 905 | |
| 906 | /* device (not port) flags, basically device capabilities */ |
| 907 | u32 flags; |
| 908 | |
| 909 | /* reset value */ |
| 910 | u64 z_int_counter; |
| 911 | u64 z_rcv_limit; |
Vennila Megavannan | 89abfc8 | 2016-02-03 14:34:07 -0800 | [diff] [blame] | 912 | u64 z_send_schedule; |
Mike Marciniszyn | 7724105 | 2015-07-30 15:17:43 -0400 | [diff] [blame] | 913 | /* percpu int_counter */ |
| 914 | u64 __percpu *int_counter; |
| 915 | u64 __percpu *rcv_limit; |
Vennila Megavannan | 89abfc8 | 2016-02-03 14:34:07 -0800 | [diff] [blame] | 916 | u64 __percpu *send_schedule; |
Mike Marciniszyn | 7724105 | 2015-07-30 15:17:43 -0400 | [diff] [blame] | 917 | /* number of receive contexts in use by the driver */ |
| 918 | u32 num_rcv_contexts; |
| 919 | /* number of pio send contexts in use by the driver */ |
| 920 | u32 num_send_contexts; |
| 921 | /* |
| 922 | * number of ctxts available for PSM open |
| 923 | */ |
| 924 | u32 freectxts; |
Ashutosh Dixit | affa48d | 2016-02-03 14:33:06 -0800 | [diff] [blame] | 925 | /* total number of available user/PSM contexts */ |
| 926 | u32 num_user_contexts; |
Mike Marciniszyn | 7724105 | 2015-07-30 15:17:43 -0400 | [diff] [blame] | 927 | /* base receive interrupt timeout, in CSR units */ |
| 928 | u32 rcv_intr_timeout_csr; |
| 929 | |
| 930 | u64 __iomem *egrtidbase; |
| 931 | spinlock_t sendctrl_lock; /* protect changes to SendCtrl */ |
| 932 | spinlock_t rcvctrl_lock; /* protect changes to RcvCtrl */ |
| 933 | /* around rcd and (user ctxts) ctxt_cnt use (intr vs free) */ |
| 934 | spinlock_t uctxt_lock; /* rcd and user context changes */ |
| 935 | /* exclusive access to 8051 */ |
| 936 | spinlock_t dc8051_lock; |
| 937 | /* exclusive access to 8051 memory */ |
| 938 | spinlock_t dc8051_memlock; |
| 939 | int dc8051_timed_out; /* remember if the 8051 timed out */ |
| 940 | /* |
| 941 | * A page that will hold event notification bitmaps for all |
| 942 | * contexts. This page will be mapped into all processes. |
| 943 | */ |
| 944 | unsigned long *events; |
| 945 | /* |
| 946 | * per unit status, see also portdata statusp |
| 947 | * mapped read-only into user processes so they can get unit and |
| 948 | * IB link status cheaply |
| 949 | */ |
| 950 | struct hfi1_status *status; |
| 951 | u32 freezelen; /* max length of freezemsg */ |
| 952 | |
| 953 | /* revision register shadow */ |
| 954 | u64 revision; |
| 955 | /* Base GUID for device (network order) */ |
| 956 | u64 base_guid; |
| 957 | |
| 958 | /* these are the "32 bit" regs */ |
| 959 | |
| 960 | /* value we put in kr_rcvhdrsize */ |
| 961 | u32 rcvhdrsize; |
| 962 | /* number of receive contexts the chip supports */ |
| 963 | u32 chip_rcv_contexts; |
| 964 | /* number of receive array entries */ |
| 965 | u32 chip_rcv_array_count; |
| 966 | /* number of PIO send contexts the chip supports */ |
| 967 | u32 chip_send_contexts; |
| 968 | /* number of bytes in the PIO memory buffer */ |
| 969 | u32 chip_pio_mem_size; |
| 970 | /* number of bytes in the SDMA memory buffer */ |
| 971 | u32 chip_sdma_mem_size; |
| 972 | |
| 973 | /* size of each rcvegrbuffer */ |
| 974 | u32 rcvegrbufsize; |
| 975 | /* log2 of above */ |
| 976 | u16 rcvegrbufsize_shift; |
| 977 | /* both sides of the PCIe link are gen3 capable */ |
| 978 | u8 link_gen3_capable; |
| 979 | /* localbus width (1, 2,4,8,16,32) from config space */ |
| 980 | u32 lbus_width; |
| 981 | /* localbus speed in MHz */ |
| 982 | u32 lbus_speed; |
| 983 | int unit; /* unit # of this chip */ |
| 984 | int node; /* home node of this chip */ |
| 985 | |
| 986 | /* save these PCI fields to restore after a reset */ |
| 987 | u32 pcibar0; |
| 988 | u32 pcibar1; |
| 989 | u32 pci_rom; |
| 990 | u16 pci_command; |
| 991 | u16 pcie_devctl; |
| 992 | u16 pcie_lnkctl; |
| 993 | u16 pcie_devctl2; |
| 994 | u32 pci_msix0; |
| 995 | u32 pci_lnkctl3; |
| 996 | u32 pci_tph2; |
| 997 | |
| 998 | /* |
| 999 | * ASCII serial number, from flash, large enough for original |
| 1000 | * all digit strings, and longer serial number format |
| 1001 | */ |
| 1002 | u8 serial[SERIAL_MAX]; |
| 1003 | /* human readable board version */ |
| 1004 | u8 boardversion[BOARD_VERS_MAX]; |
| 1005 | u8 lbus_info[32]; /* human readable localbus info */ |
| 1006 | /* chip major rev, from CceRevision */ |
| 1007 | u8 majrev; |
| 1008 | /* chip minor rev, from CceRevision */ |
| 1009 | u8 minrev; |
| 1010 | /* hardware ID */ |
| 1011 | u8 hfi1_id; |
| 1012 | /* implementation code */ |
| 1013 | u8 icode; |
| 1014 | /* default link down value (poll/sleep) */ |
| 1015 | u8 link_default; |
| 1016 | /* vAU of this device */ |
| 1017 | u8 vau; |
| 1018 | /* vCU of this device */ |
| 1019 | u8 vcu; |
| 1020 | /* link credits of this device */ |
| 1021 | u16 link_credits; |
| 1022 | /* initial vl15 credits to use */ |
| 1023 | u16 vl15_init; |
| 1024 | |
| 1025 | /* Misc small ints */ |
| 1026 | /* Number of physical ports available */ |
| 1027 | u8 num_pports; |
| 1028 | /* Lowest context number which can be used by user processes */ |
| 1029 | u8 first_user_ctxt; |
| 1030 | u8 n_krcv_queues; |
| 1031 | u8 qos_shift; |
| 1032 | u8 qpn_mask; |
| 1033 | |
| 1034 | u16 rhf_offset; /* offset of RHF within receive header entry */ |
| 1035 | u16 irev; /* implementation revision */ |
| 1036 | u16 dc8051_ver; /* 8051 firmware version */ |
| 1037 | |
Easwar Hariharan | c3838b3 | 2016-02-09 14:29:13 -0800 | [diff] [blame] | 1038 | struct platform_config platform_config; |
Mike Marciniszyn | 7724105 | 2015-07-30 15:17:43 -0400 | [diff] [blame] | 1039 | struct platform_config_cache pcfg_cache; |
| 1040 | /* control high-level access to qsfp */ |
| 1041 | struct mutex qsfp_i2c_mutex; |
| 1042 | |
| 1043 | struct diag_client *diag_client; |
| 1044 | spinlock_t hfi1_diag_trans_lock; /* protect diag observer ops */ |
| 1045 | |
| 1046 | u8 psxmitwait_supported; |
| 1047 | /* cycle length of PS* counters in HW (in picoseconds) */ |
| 1048 | u16 psxmitwait_check_rate; |
| 1049 | /* high volume overflow errors deferred to tasklet */ |
| 1050 | struct tasklet_struct error_tasklet; |
Mike Marciniszyn | 7724105 | 2015-07-30 15:17:43 -0400 | [diff] [blame] | 1051 | |
| 1052 | /* MSI-X information */ |
| 1053 | struct hfi1_msix_entry *msix_entries; |
| 1054 | u32 num_msix_entries; |
| 1055 | |
| 1056 | /* INTx information */ |
| 1057 | u32 requested_intx_irq; /* did we request one? */ |
| 1058 | char intx_name[MAX_NAME_SIZE]; /* INTx name */ |
| 1059 | |
| 1060 | /* general interrupt: mask of handled interrupts */ |
| 1061 | u64 gi_mask[CCE_NUM_INT_CSRS]; |
| 1062 | |
| 1063 | struct rcv_array_data rcv_entries; |
| 1064 | |
| 1065 | /* |
| 1066 | * 64 bit synthetic counters |
| 1067 | */ |
| 1068 | struct timer_list synth_stats_timer; |
| 1069 | |
| 1070 | /* |
| 1071 | * device counters |
| 1072 | */ |
| 1073 | char *cntrnames; |
| 1074 | size_t cntrnameslen; |
| 1075 | size_t ndevcntrs; |
| 1076 | u64 *cntrs; |
| 1077 | u64 *scntrs; |
| 1078 | |
| 1079 | /* |
| 1080 | * remembered values for synthetic counters |
| 1081 | */ |
| 1082 | u64 last_tx; |
| 1083 | u64 last_rx; |
| 1084 | |
| 1085 | /* |
| 1086 | * per-port counters |
| 1087 | */ |
| 1088 | size_t nportcntrs; |
| 1089 | char *portcntrnames; |
| 1090 | size_t portcntrnameslen; |
| 1091 | |
| 1092 | struct hfi1_snoop_data hfi1_snoop; |
| 1093 | |
| 1094 | struct err_info_rcvport err_info_rcvport; |
| 1095 | struct err_info_constraint err_info_rcv_constraint; |
| 1096 | struct err_info_constraint err_info_xmit_constraint; |
| 1097 | u8 err_info_uncorrectable; |
| 1098 | u8 err_info_fmconfig; |
| 1099 | |
| 1100 | atomic_t drop_packet; |
| 1101 | u8 do_drop; |
| 1102 | |
Joel Rosenzweig | 2c5b521 | 2015-12-01 15:38:19 -0500 | [diff] [blame] | 1103 | /* |
| 1104 | * Software counters for the status bits defined by the |
| 1105 | * associated error status registers |
| 1106 | */ |
| 1107 | u64 cce_err_status_cnt[NUM_CCE_ERR_STATUS_COUNTERS]; |
| 1108 | u64 rcv_err_status_cnt[NUM_RCV_ERR_STATUS_COUNTERS]; |
| 1109 | u64 misc_err_status_cnt[NUM_MISC_ERR_STATUS_COUNTERS]; |
| 1110 | u64 send_pio_err_status_cnt[NUM_SEND_PIO_ERR_STATUS_COUNTERS]; |
| 1111 | u64 send_dma_err_status_cnt[NUM_SEND_DMA_ERR_STATUS_COUNTERS]; |
| 1112 | u64 send_egress_err_status_cnt[NUM_SEND_EGRESS_ERR_STATUS_COUNTERS]; |
| 1113 | u64 send_err_status_cnt[NUM_SEND_ERR_STATUS_COUNTERS]; |
| 1114 | |
| 1115 | /* Software counter that spans all contexts */ |
| 1116 | u64 sw_ctxt_err_status_cnt[NUM_SEND_CTXT_ERR_STATUS_COUNTERS]; |
| 1117 | /* Software counter that spans all DMA engines */ |
| 1118 | u64 sw_send_dma_eng_err_status_cnt[ |
| 1119 | NUM_SEND_DMA_ENG_ERR_STATUS_COUNTERS]; |
| 1120 | /* Software counter that aggregates all cce_err_status errors */ |
| 1121 | u64 sw_cce_err_status_aggregate; |
| 1122 | |
Mike Marciniszyn | 7724105 | 2015-07-30 15:17:43 -0400 | [diff] [blame] | 1123 | /* receive interrupt functions */ |
| 1124 | rhf_rcv_function_ptr *rhf_rcv_function_map; |
| 1125 | rhf_rcv_function_ptr normal_rhf_rcv_functions[8]; |
| 1126 | |
| 1127 | /* |
| 1128 | * Handlers for outgoing data so that snoop/capture does not |
| 1129 | * have to have its hooks in the send path |
| 1130 | */ |
Mike Marciniszyn | 14553ca | 2016-02-14 12:45:36 -0800 | [diff] [blame] | 1131 | send_routine process_pio_send; |
| 1132 | send_routine process_dma_send; |
Mike Marciniszyn | 7724105 | 2015-07-30 15:17:43 -0400 | [diff] [blame] | 1133 | void (*pio_inline_send)(struct hfi1_devdata *dd, struct pio_buf *pbuf, |
| 1134 | u64 pbc, const void *from, size_t count); |
| 1135 | |
| 1136 | /* OUI comes from the HW. Used everywhere as 3 separate bytes. */ |
| 1137 | u8 oui1; |
| 1138 | u8 oui2; |
| 1139 | u8 oui3; |
| 1140 | /* Timer and counter used to detect RcvBufOvflCnt changes */ |
| 1141 | struct timer_list rcverr_timer; |
| 1142 | u32 rcv_ovfl_cnt; |
| 1143 | |
Mike Marciniszyn | 7724105 | 2015-07-30 15:17:43 -0400 | [diff] [blame] | 1144 | wait_queue_head_t event_queue; |
| 1145 | |
| 1146 | /* Save the enabled LCB error bits */ |
| 1147 | u64 lcb_err_en; |
| 1148 | u8 dc_shutdown; |
Mark F. Brown | 46b010d | 2015-11-09 19:18:20 -0500 | [diff] [blame] | 1149 | |
| 1150 | /* receive context tail dummy address */ |
| 1151 | __le64 *rcvhdrtail_dummy_kvaddr; |
| 1152 | dma_addr_t rcvhdrtail_dummy_physaddr; |
Ashutosh Dixit | affa48d | 2016-02-03 14:33:06 -0800 | [diff] [blame] | 1153 | |
Dean Luick | e154f12 | 2016-02-03 14:37:24 -0800 | [diff] [blame] | 1154 | bool eprom_available; /* true if EPROM is available for this device */ |
Ashutosh Dixit | affa48d | 2016-02-03 14:33:06 -0800 | [diff] [blame] | 1155 | bool aspm_supported; /* Does HW support ASPM */ |
| 1156 | bool aspm_enabled; /* ASPM state: enabled/disabled */ |
| 1157 | /* Serialize ASPM enable/disable between multiple verbs contexts */ |
| 1158 | spinlock_t aspm_lock; |
| 1159 | /* Number of verbs contexts which have disabled ASPM */ |
| 1160 | atomic_t aspm_disabled_cnt; |
Mitko Haralanov | 957558c | 2016-02-03 14:33:40 -0800 | [diff] [blame] | 1161 | |
| 1162 | struct hfi1_affinity *affinity; |
Mike Marciniszyn | 7724105 | 2015-07-30 15:17:43 -0400 | [diff] [blame] | 1163 | }; |
| 1164 | |
| 1165 | /* 8051 firmware version helper */ |
| 1166 | #define dc8051_ver(a, b) ((a) << 8 | (b)) |
| 1167 | |
| 1168 | /* f_put_tid types */ |
| 1169 | #define PT_EXPECTED 0 |
| 1170 | #define PT_EAGER 1 |
| 1171 | #define PT_INVALID 2 |
| 1172 | |
Mitko Haralanov | f727a0c | 2016-02-05 11:57:46 -0500 | [diff] [blame] | 1173 | struct mmu_rb_node; |
| 1174 | |
Mike Marciniszyn | 7724105 | 2015-07-30 15:17:43 -0400 | [diff] [blame] | 1175 | /* Private data for file operations */ |
| 1176 | struct hfi1_filedata { |
| 1177 | struct hfi1_ctxtdata *uctxt; |
| 1178 | unsigned subctxt; |
| 1179 | struct hfi1_user_sdma_comp_q *cq; |
| 1180 | struct hfi1_user_sdma_pkt_q *pq; |
| 1181 | /* for cpu affinity; -1 if none */ |
| 1182 | int rec_cpu_num; |
Mitko Haralanov | a86cd35 | 2016-02-05 11:57:49 -0500 | [diff] [blame] | 1183 | struct mmu_notifier mn; |
| 1184 | struct rb_root tid_rb_root; |
Mitko Haralanov | a92ba6d | 2016-02-03 14:34:41 -0800 | [diff] [blame] | 1185 | struct mmu_rb_node **entry_to_rb; |
Mitko Haralanov | a86cd35 | 2016-02-05 11:57:49 -0500 | [diff] [blame] | 1186 | spinlock_t tid_lock; /* protect tid_[limit,used] counters */ |
| 1187 | u32 tid_limit; |
| 1188 | u32 tid_used; |
| 1189 | spinlock_t rb_lock; /* protect tid_rb_root RB tree */ |
| 1190 | u32 *invalid_tids; |
| 1191 | u32 invalid_tid_idx; |
| 1192 | spinlock_t invalid_lock; /* protect the invalid_tids array */ |
Mitko Haralanov | a92ba6d | 2016-02-03 14:34:41 -0800 | [diff] [blame] | 1193 | int (*mmu_rb_insert)(struct hfi1_filedata *, struct rb_root *, |
| 1194 | struct mmu_rb_node *); |
| 1195 | void (*mmu_rb_remove)(struct hfi1_filedata *, struct rb_root *, |
| 1196 | struct mmu_rb_node *); |
Mike Marciniszyn | 7724105 | 2015-07-30 15:17:43 -0400 | [diff] [blame] | 1197 | }; |
| 1198 | |
| 1199 | extern struct list_head hfi1_dev_list; |
| 1200 | extern spinlock_t hfi1_devs_lock; |
| 1201 | struct hfi1_devdata *hfi1_lookup(int unit); |
| 1202 | extern u32 hfi1_cpulist_count; |
| 1203 | extern unsigned long *hfi1_cpulist; |
| 1204 | |
| 1205 | extern unsigned int snoop_drop_send; |
| 1206 | extern unsigned int snoop_force_capture; |
| 1207 | int hfi1_init(struct hfi1_devdata *, int); |
| 1208 | int hfi1_count_units(int *npresentp, int *nupp); |
| 1209 | int hfi1_count_active_units(void); |
| 1210 | |
| 1211 | int hfi1_diag_add(struct hfi1_devdata *); |
| 1212 | void hfi1_diag_remove(struct hfi1_devdata *); |
| 1213 | void handle_linkup_change(struct hfi1_devdata *dd, u32 linkup); |
| 1214 | |
| 1215 | void handle_user_interrupt(struct hfi1_ctxtdata *rcd); |
| 1216 | |
| 1217 | int hfi1_create_rcvhdrq(struct hfi1_devdata *, struct hfi1_ctxtdata *); |
| 1218 | int hfi1_setup_eagerbufs(struct hfi1_ctxtdata *); |
| 1219 | int hfi1_create_ctxts(struct hfi1_devdata *dd); |
Mitko Haralanov | 957558c | 2016-02-03 14:33:40 -0800 | [diff] [blame] | 1220 | struct hfi1_ctxtdata *hfi1_create_ctxtdata(struct hfi1_pportdata *, u32, int); |
Mike Marciniszyn | 7724105 | 2015-07-30 15:17:43 -0400 | [diff] [blame] | 1221 | void hfi1_init_pportdata(struct pci_dev *, struct hfi1_pportdata *, |
| 1222 | struct hfi1_devdata *, u8, u8); |
| 1223 | void hfi1_free_ctxtdata(struct hfi1_devdata *, struct hfi1_ctxtdata *); |
| 1224 | |
Dean Luick | f4f30031c | 2015-10-26 10:28:44 -0400 | [diff] [blame] | 1225 | int handle_receive_interrupt(struct hfi1_ctxtdata *, int); |
| 1226 | int handle_receive_interrupt_nodma_rtail(struct hfi1_ctxtdata *, int); |
| 1227 | int handle_receive_interrupt_dma_rtail(struct hfi1_ctxtdata *, int); |
Jim Snow | fb9036d | 2016-01-11 18:32:21 -0500 | [diff] [blame] | 1228 | void set_all_slowpath(struct hfi1_devdata *dd); |
Dean Luick | f4f30031c | 2015-10-26 10:28:44 -0400 | [diff] [blame] | 1229 | |
| 1230 | /* receive packet handler dispositions */ |
| 1231 | #define RCV_PKT_OK 0x0 /* keep going */ |
| 1232 | #define RCV_PKT_LIMIT 0x1 /* stop, hit limit, start thread */ |
| 1233 | #define RCV_PKT_DONE 0x2 /* stop, no more packets detected */ |
| 1234 | |
| 1235 | /* calculate the current RHF address */ |
| 1236 | static inline __le32 *get_rhf_addr(struct hfi1_ctxtdata *rcd) |
| 1237 | { |
| 1238 | return (__le32 *)rcd->rcvhdrq + rcd->head + rcd->dd->rhf_offset; |
| 1239 | } |
| 1240 | |
Mike Marciniszyn | 7724105 | 2015-07-30 15:17:43 -0400 | [diff] [blame] | 1241 | int hfi1_reset_device(int); |
| 1242 | |
| 1243 | /* return the driver's idea of the logical OPA port state */ |
| 1244 | static inline u32 driver_lstate(struct hfi1_pportdata *ppd) |
| 1245 | { |
| 1246 | return ppd->lstate; /* use the cached value */ |
| 1247 | } |
| 1248 | |
Jim Snow | fb9036d | 2016-01-11 18:32:21 -0500 | [diff] [blame] | 1249 | void receive_interrupt_work(struct work_struct *work); |
| 1250 | |
| 1251 | /* extract service channel from header and rhf */ |
| 1252 | static inline int hdr2sc(struct hfi1_message_header *hdr, u64 rhf) |
| 1253 | { |
| 1254 | return ((be16_to_cpu(hdr->lrh[0]) >> 12) & 0xf) | |
| 1255 | ((!!(rhf & RHF_DC_INFO_MASK)) << 4); |
| 1256 | } |
| 1257 | |
Mike Marciniszyn | 7724105 | 2015-07-30 15:17:43 -0400 | [diff] [blame] | 1258 | static inline u16 generate_jkey(kuid_t uid) |
| 1259 | { |
| 1260 | return from_kuid(current_user_ns(), uid) & 0xffff; |
| 1261 | } |
| 1262 | |
| 1263 | /* |
| 1264 | * active_egress_rate |
| 1265 | * |
| 1266 | * returns the active egress rate in units of [10^6 bits/sec] |
| 1267 | */ |
| 1268 | static inline u32 active_egress_rate(struct hfi1_pportdata *ppd) |
| 1269 | { |
| 1270 | u16 link_speed = ppd->link_speed_active; |
| 1271 | u16 link_width = ppd->link_width_active; |
| 1272 | u32 egress_rate; |
| 1273 | |
| 1274 | if (link_speed == OPA_LINK_SPEED_25G) |
| 1275 | egress_rate = 25000; |
| 1276 | else /* assume OPA_LINK_SPEED_12_5G */ |
| 1277 | egress_rate = 12500; |
| 1278 | |
| 1279 | switch (link_width) { |
| 1280 | case OPA_LINK_WIDTH_4X: |
| 1281 | egress_rate *= 4; |
| 1282 | break; |
| 1283 | case OPA_LINK_WIDTH_3X: |
| 1284 | egress_rate *= 3; |
| 1285 | break; |
| 1286 | case OPA_LINK_WIDTH_2X: |
| 1287 | egress_rate *= 2; |
| 1288 | break; |
| 1289 | default: |
| 1290 | /* assume IB_WIDTH_1X */ |
| 1291 | break; |
| 1292 | } |
| 1293 | |
| 1294 | return egress_rate; |
| 1295 | } |
| 1296 | |
| 1297 | /* |
| 1298 | * egress_cycles |
| 1299 | * |
| 1300 | * Returns the number of 'fabric clock cycles' to egress a packet |
| 1301 | * of length 'len' bytes, at 'rate' Mbit/s. Since the fabric clock |
| 1302 | * rate is (approximately) 805 MHz, the units of the returned value |
| 1303 | * are (1/805 MHz). |
| 1304 | */ |
| 1305 | static inline u32 egress_cycles(u32 len, u32 rate) |
| 1306 | { |
| 1307 | u32 cycles; |
| 1308 | |
| 1309 | /* |
| 1310 | * cycles is: |
| 1311 | * |
| 1312 | * (length) [bits] / (rate) [bits/sec] |
| 1313 | * --------------------------------------------------- |
| 1314 | * fabric_clock_period == 1 /(805 * 10^6) [cycles/sec] |
| 1315 | */ |
| 1316 | |
| 1317 | cycles = len * 8; /* bits */ |
| 1318 | cycles *= 805; |
| 1319 | cycles /= rate; |
| 1320 | |
| 1321 | return cycles; |
| 1322 | } |
| 1323 | |
| 1324 | void set_link_ipg(struct hfi1_pportdata *ppd); |
| 1325 | void process_becn(struct hfi1_pportdata *ppd, u8 sl, u16 rlid, u32 lqpn, |
| 1326 | u32 rqpn, u8 svc_type); |
Dennis Dalessandro | 895420d | 2016-01-19 14:42:28 -0800 | [diff] [blame] | 1327 | void return_cnp(struct hfi1_ibport *ibp, struct rvt_qp *qp, u32 remote_qpn, |
Mike Marciniszyn | 7724105 | 2015-07-30 15:17:43 -0400 | [diff] [blame] | 1328 | u32 pkey, u32 slid, u32 dlid, u8 sc5, |
| 1329 | const struct ib_grh *old_grh); |
| 1330 | |
| 1331 | #define PACKET_EGRESS_TIMEOUT 350 |
| 1332 | static inline void pause_for_credit_return(struct hfi1_devdata *dd) |
| 1333 | { |
| 1334 | /* Pause at least 1us, to ensure chip returns all credits */ |
| 1335 | u32 usec = cclock_to_ns(dd, PACKET_EGRESS_TIMEOUT) / 1000; |
| 1336 | |
| 1337 | udelay(usec ? usec : 1); |
| 1338 | } |
| 1339 | |
| 1340 | /** |
| 1341 | * sc_to_vlt() reverse lookup sc to vl |
| 1342 | * @dd - devdata |
| 1343 | * @sc5 - 5 bit sc |
| 1344 | */ |
| 1345 | static inline u8 sc_to_vlt(struct hfi1_devdata *dd, u8 sc5) |
| 1346 | { |
| 1347 | unsigned seq; |
| 1348 | u8 rval; |
| 1349 | |
| 1350 | if (sc5 >= OPA_MAX_SCS) |
| 1351 | return (u8)(0xff); |
| 1352 | |
| 1353 | do { |
| 1354 | seq = read_seqbegin(&dd->sc2vl_lock); |
| 1355 | rval = *(((u8 *)dd->sc2vl) + sc5); |
| 1356 | } while (read_seqretry(&dd->sc2vl_lock, seq)); |
| 1357 | |
| 1358 | return rval; |
| 1359 | } |
| 1360 | |
| 1361 | #define PKEY_MEMBER_MASK 0x8000 |
| 1362 | #define PKEY_LOW_15_MASK 0x7fff |
| 1363 | |
| 1364 | /* |
| 1365 | * ingress_pkey_matches_entry - return 1 if the pkey matches ent (ent |
| 1366 | * being an entry from the ingress partition key table), return 0 |
| 1367 | * otherwise. Use the matching criteria for ingress partition keys |
| 1368 | * specified in the OPAv1 spec., section 9.10.14. |
| 1369 | */ |
| 1370 | static inline int ingress_pkey_matches_entry(u16 pkey, u16 ent) |
| 1371 | { |
| 1372 | u16 mkey = pkey & PKEY_LOW_15_MASK; |
| 1373 | u16 ment = ent & PKEY_LOW_15_MASK; |
| 1374 | |
| 1375 | if (mkey == ment) { |
| 1376 | /* |
| 1377 | * If pkey[15] is clear (limited partition member), |
| 1378 | * is bit 15 in the corresponding table element |
| 1379 | * clear (limited member)? |
| 1380 | */ |
| 1381 | if (!(pkey & PKEY_MEMBER_MASK)) |
| 1382 | return !!(ent & PKEY_MEMBER_MASK); |
| 1383 | return 1; |
| 1384 | } |
| 1385 | return 0; |
| 1386 | } |
| 1387 | |
| 1388 | /* |
| 1389 | * ingress_pkey_table_search - search the entire pkey table for |
| 1390 | * an entry which matches 'pkey'. return 0 if a match is found, |
| 1391 | * and 1 otherwise. |
| 1392 | */ |
| 1393 | static int ingress_pkey_table_search(struct hfi1_pportdata *ppd, u16 pkey) |
| 1394 | { |
| 1395 | int i; |
| 1396 | |
| 1397 | for (i = 0; i < MAX_PKEY_VALUES; i++) { |
| 1398 | if (ingress_pkey_matches_entry(pkey, ppd->pkeys[i])) |
| 1399 | return 0; |
| 1400 | } |
| 1401 | return 1; |
| 1402 | } |
| 1403 | |
| 1404 | /* |
| 1405 | * ingress_pkey_table_fail - record a failure of ingress pkey validation, |
| 1406 | * i.e., increment port_rcv_constraint_errors for the port, and record |
| 1407 | * the 'error info' for this failure. |
| 1408 | */ |
| 1409 | static void ingress_pkey_table_fail(struct hfi1_pportdata *ppd, u16 pkey, |
| 1410 | u16 slid) |
| 1411 | { |
| 1412 | struct hfi1_devdata *dd = ppd->dd; |
| 1413 | |
| 1414 | incr_cntr64(&ppd->port_rcv_constraint_errors); |
| 1415 | if (!(dd->err_info_rcv_constraint.status & OPA_EI_STATUS_SMASK)) { |
| 1416 | dd->err_info_rcv_constraint.status |= OPA_EI_STATUS_SMASK; |
| 1417 | dd->err_info_rcv_constraint.slid = slid; |
| 1418 | dd->err_info_rcv_constraint.pkey = pkey; |
| 1419 | } |
| 1420 | } |
| 1421 | |
| 1422 | /* |
| 1423 | * ingress_pkey_check - Return 0 if the ingress pkey is valid, return 1 |
| 1424 | * otherwise. Use the criteria in the OPAv1 spec, section 9.10.14. idx |
| 1425 | * is a hint as to the best place in the partition key table to begin |
| 1426 | * searching. This function should not be called on the data path because |
| 1427 | * of performance reasons. On datapath pkey check is expected to be done |
| 1428 | * by HW and rcv_pkey_check function should be called instead. |
| 1429 | */ |
| 1430 | static inline int ingress_pkey_check(struct hfi1_pportdata *ppd, u16 pkey, |
| 1431 | u8 sc5, u8 idx, u16 slid) |
| 1432 | { |
| 1433 | if (!(ppd->part_enforce & HFI1_PART_ENFORCE_IN)) |
| 1434 | return 0; |
| 1435 | |
| 1436 | /* If SC15, pkey[0:14] must be 0x7fff */ |
| 1437 | if ((sc5 == 0xf) && ((pkey & PKEY_LOW_15_MASK) != PKEY_LOW_15_MASK)) |
| 1438 | goto bad; |
| 1439 | |
| 1440 | /* Is the pkey = 0x0, or 0x8000? */ |
| 1441 | if ((pkey & PKEY_LOW_15_MASK) == 0) |
| 1442 | goto bad; |
| 1443 | |
| 1444 | /* The most likely matching pkey has index 'idx' */ |
| 1445 | if (ingress_pkey_matches_entry(pkey, ppd->pkeys[idx])) |
| 1446 | return 0; |
| 1447 | |
| 1448 | /* no match - try the whole table */ |
| 1449 | if (!ingress_pkey_table_search(ppd, pkey)) |
| 1450 | return 0; |
| 1451 | |
| 1452 | bad: |
| 1453 | ingress_pkey_table_fail(ppd, pkey, slid); |
| 1454 | return 1; |
| 1455 | } |
| 1456 | |
| 1457 | /* |
| 1458 | * rcv_pkey_check - Return 0 if the ingress pkey is valid, return 1 |
| 1459 | * otherwise. It only ensures pkey is vlid for QP0. This function |
| 1460 | * should be called on the data path instead of ingress_pkey_check |
| 1461 | * as on data path, pkey check is done by HW (except for QP0). |
| 1462 | */ |
| 1463 | static inline int rcv_pkey_check(struct hfi1_pportdata *ppd, u16 pkey, |
| 1464 | u8 sc5, u16 slid) |
| 1465 | { |
| 1466 | if (!(ppd->part_enforce & HFI1_PART_ENFORCE_IN)) |
| 1467 | return 0; |
| 1468 | |
| 1469 | /* If SC15, pkey[0:14] must be 0x7fff */ |
| 1470 | if ((sc5 == 0xf) && ((pkey & PKEY_LOW_15_MASK) != PKEY_LOW_15_MASK)) |
| 1471 | goto bad; |
| 1472 | |
| 1473 | return 0; |
| 1474 | bad: |
| 1475 | ingress_pkey_table_fail(ppd, pkey, slid); |
| 1476 | return 1; |
| 1477 | } |
| 1478 | |
| 1479 | /* MTU handling */ |
| 1480 | |
| 1481 | /* MTU enumeration, 256-4k match IB */ |
| 1482 | #define OPA_MTU_0 0 |
| 1483 | #define OPA_MTU_256 1 |
| 1484 | #define OPA_MTU_512 2 |
| 1485 | #define OPA_MTU_1024 3 |
| 1486 | #define OPA_MTU_2048 4 |
| 1487 | #define OPA_MTU_4096 5 |
| 1488 | |
| 1489 | u32 lrh_max_header_bytes(struct hfi1_devdata *dd); |
| 1490 | int mtu_to_enum(u32 mtu, int default_if_bad); |
| 1491 | u16 enum_to_mtu(int); |
| 1492 | static inline int valid_ib_mtu(unsigned int mtu) |
| 1493 | { |
| 1494 | return mtu == 256 || mtu == 512 || |
| 1495 | mtu == 1024 || mtu == 2048 || |
| 1496 | mtu == 4096; |
| 1497 | } |
| 1498 | static inline int valid_opa_max_mtu(unsigned int mtu) |
| 1499 | { |
| 1500 | return mtu >= 2048 && |
| 1501 | (valid_ib_mtu(mtu) || mtu == 8192 || mtu == 10240); |
| 1502 | } |
| 1503 | |
| 1504 | int set_mtu(struct hfi1_pportdata *); |
| 1505 | |
| 1506 | int hfi1_set_lid(struct hfi1_pportdata *, u32, u8); |
| 1507 | void hfi1_disable_after_error(struct hfi1_devdata *); |
| 1508 | int hfi1_set_uevent_bits(struct hfi1_pportdata *, const int); |
| 1509 | int hfi1_rcvbuf_validate(u32, u8, u16 *); |
| 1510 | |
| 1511 | int fm_get_table(struct hfi1_pportdata *, int, void *); |
| 1512 | int fm_set_table(struct hfi1_pportdata *, int, void *); |
| 1513 | |
| 1514 | void set_up_vl15(struct hfi1_devdata *dd, u8 vau, u16 vl15buf); |
| 1515 | void reset_link_credits(struct hfi1_devdata *dd); |
| 1516 | void assign_remote_cm_au_table(struct hfi1_devdata *dd, u8 vcu); |
| 1517 | |
| 1518 | int snoop_recv_handler(struct hfi1_packet *packet); |
Dennis Dalessandro | 895420d | 2016-01-19 14:42:28 -0800 | [diff] [blame] | 1519 | int snoop_send_dma_handler(struct rvt_qp *qp, struct hfi1_pkt_state *ps, |
Dennis Dalessandro | d46e514 | 2015-11-11 00:34:37 -0500 | [diff] [blame] | 1520 | u64 pbc); |
Dennis Dalessandro | 895420d | 2016-01-19 14:42:28 -0800 | [diff] [blame] | 1521 | int snoop_send_pio_handler(struct rvt_qp *qp, struct hfi1_pkt_state *ps, |
Dennis Dalessandro | d46e514 | 2015-11-11 00:34:37 -0500 | [diff] [blame] | 1522 | u64 pbc); |
Mike Marciniszyn | 7724105 | 2015-07-30 15:17:43 -0400 | [diff] [blame] | 1523 | void snoop_inline_pio_send(struct hfi1_devdata *dd, struct pio_buf *pbuf, |
| 1524 | u64 pbc, const void *from, size_t count); |
Mike Marciniszyn | 8a4d344 | 2016-02-14 12:46:01 -0800 | [diff] [blame] | 1525 | int set_buffer_control(struct hfi1_pportdata *ppd, struct buffer_control *bc); |
Mike Marciniszyn | 7724105 | 2015-07-30 15:17:43 -0400 | [diff] [blame] | 1526 | |
Mike Marciniszyn | 7724105 | 2015-07-30 15:17:43 -0400 | [diff] [blame] | 1527 | static inline struct hfi1_devdata *dd_from_ppd(struct hfi1_pportdata *ppd) |
| 1528 | { |
| 1529 | return ppd->dd; |
| 1530 | } |
| 1531 | |
| 1532 | static inline struct hfi1_devdata *dd_from_dev(struct hfi1_ibdev *dev) |
| 1533 | { |
| 1534 | return container_of(dev, struct hfi1_devdata, verbs_dev); |
| 1535 | } |
| 1536 | |
| 1537 | static inline struct hfi1_devdata *dd_from_ibdev(struct ib_device *ibdev) |
| 1538 | { |
| 1539 | return dd_from_dev(to_idev(ibdev)); |
| 1540 | } |
| 1541 | |
| 1542 | static inline struct hfi1_pportdata *ppd_from_ibp(struct hfi1_ibport *ibp) |
| 1543 | { |
| 1544 | return container_of(ibp, struct hfi1_pportdata, ibport_data); |
| 1545 | } |
| 1546 | |
Harish Chegondi | 45b59ee | 2016-02-03 14:36:49 -0800 | [diff] [blame] | 1547 | static inline struct hfi1_ibdev *dev_from_rdi(struct rvt_dev_info *rdi) |
| 1548 | { |
| 1549 | return container_of(rdi, struct hfi1_ibdev, rdi); |
| 1550 | } |
| 1551 | |
Mike Marciniszyn | 7724105 | 2015-07-30 15:17:43 -0400 | [diff] [blame] | 1552 | static inline struct hfi1_ibport *to_iport(struct ib_device *ibdev, u8 port) |
| 1553 | { |
| 1554 | struct hfi1_devdata *dd = dd_from_ibdev(ibdev); |
| 1555 | unsigned pidx = port - 1; /* IB number port from 1, hdw from 0 */ |
| 1556 | |
| 1557 | WARN_ON(pidx >= dd->num_pports); |
| 1558 | return &dd->pport[pidx].ibport_data; |
| 1559 | } |
| 1560 | |
| 1561 | /* |
| 1562 | * Return the indexed PKEY from the port PKEY table. |
| 1563 | */ |
| 1564 | static inline u16 hfi1_get_pkey(struct hfi1_ibport *ibp, unsigned index) |
| 1565 | { |
| 1566 | struct hfi1_pportdata *ppd = ppd_from_ibp(ibp); |
| 1567 | u16 ret; |
| 1568 | |
| 1569 | if (index >= ARRAY_SIZE(ppd->pkeys)) |
| 1570 | ret = 0; |
| 1571 | else |
| 1572 | ret = ppd->pkeys[index]; |
| 1573 | |
| 1574 | return ret; |
| 1575 | } |
| 1576 | |
| 1577 | /* |
| 1578 | * Readers of cc_state must call get_cc_state() under rcu_read_lock(). |
| 1579 | * Writers of cc_state must call get_cc_state() under cc_state_lock. |
| 1580 | */ |
| 1581 | static inline struct cc_state *get_cc_state(struct hfi1_pportdata *ppd) |
| 1582 | { |
| 1583 | return rcu_dereference(ppd->cc_state); |
| 1584 | } |
| 1585 | |
| 1586 | /* |
| 1587 | * values for dd->flags (_device_ related flags) |
| 1588 | */ |
| 1589 | #define HFI1_INITTED 0x1 /* chip and driver up and initted */ |
| 1590 | #define HFI1_PRESENT 0x2 /* chip accesses can be done */ |
| 1591 | #define HFI1_FROZEN 0x4 /* chip in SPC freeze */ |
| 1592 | #define HFI1_HAS_SDMA_TIMEOUT 0x8 |
| 1593 | #define HFI1_HAS_SEND_DMA 0x10 /* Supports Send DMA */ |
| 1594 | #define HFI1_FORCED_FREEZE 0x80 /* driver forced freeze mode */ |
| 1595 | #define HFI1_DO_INIT_ASIC 0x100 /* This device will init the ASIC */ |
| 1596 | |
| 1597 | /* IB dword length mask in PBC (lower 11 bits); same for all chips */ |
| 1598 | #define HFI1_PBC_LENGTH_MASK ((1 << 11) - 1) |
| 1599 | |
Mike Marciniszyn | 7724105 | 2015-07-30 15:17:43 -0400 | [diff] [blame] | 1600 | /* ctxt_flag bit offsets */ |
| 1601 | /* context has been setup */ |
| 1602 | #define HFI1_CTXT_SETUP_DONE 1 |
| 1603 | /* waiting for a packet to arrive */ |
| 1604 | #define HFI1_CTXT_WAITING_RCV 2 |
| 1605 | /* master has not finished initializing */ |
| 1606 | #define HFI1_CTXT_MASTER_UNINIT 4 |
| 1607 | /* waiting for an urgent packet to arrive */ |
| 1608 | #define HFI1_CTXT_WAITING_URG 5 |
| 1609 | |
| 1610 | /* free up any allocated data at closes */ |
| 1611 | struct hfi1_devdata *hfi1_init_dd(struct pci_dev *, |
| 1612 | const struct pci_device_id *); |
| 1613 | void hfi1_free_devdata(struct hfi1_devdata *); |
| 1614 | void cc_state_reclaim(struct rcu_head *rcu); |
| 1615 | struct hfi1_devdata *hfi1_alloc_devdata(struct pci_dev *pdev, size_t extra); |
| 1616 | |
Easwar Hariharan | 91ab4ed | 2016-02-03 14:35:57 -0800 | [diff] [blame] | 1617 | void hfi1_set_led_override(struct hfi1_pportdata *ppd, unsigned int timeon, |
| 1618 | unsigned int timeoff); |
Mike Marciniszyn | 7724105 | 2015-07-30 15:17:43 -0400 | [diff] [blame] | 1619 | /* |
Easwar Hariharan | 91ab4ed | 2016-02-03 14:35:57 -0800 | [diff] [blame] | 1620 | * Only to be used for driver unload or device reset where we cannot allow |
| 1621 | * the timer to fire even the one extra time, else use hfi1_set_led_override |
| 1622 | * with timeon = timeoff = 0 |
Mike Marciniszyn | 7724105 | 2015-07-30 15:17:43 -0400 | [diff] [blame] | 1623 | */ |
Easwar Hariharan | 91ab4ed | 2016-02-03 14:35:57 -0800 | [diff] [blame] | 1624 | void shutdown_led_override(struct hfi1_pportdata *ppd); |
Mike Marciniszyn | 7724105 | 2015-07-30 15:17:43 -0400 | [diff] [blame] | 1625 | |
| 1626 | #define HFI1_CREDIT_RETURN_RATE (100) |
| 1627 | |
| 1628 | /* |
| 1629 | * The number of words for the KDETH protocol field. If this is |
| 1630 | * larger then the actual field used, then part of the payload |
| 1631 | * will be in the header. |
| 1632 | * |
| 1633 | * Optimally, we want this sized so that a typical case will |
| 1634 | * use full cache lines. The typical local KDETH header would |
| 1635 | * be: |
| 1636 | * |
| 1637 | * Bytes Field |
| 1638 | * 8 LRH |
| 1639 | * 12 BHT |
| 1640 | * ?? KDETH |
| 1641 | * 8 RHF |
| 1642 | * --- |
| 1643 | * 28 + KDETH |
| 1644 | * |
| 1645 | * For a 64-byte cache line, KDETH would need to be 36 bytes or 9 DWORDS |
| 1646 | */ |
| 1647 | #define DEFAULT_RCVHDRSIZE 9 |
| 1648 | |
| 1649 | /* |
| 1650 | * Maximal header byte count: |
| 1651 | * |
| 1652 | * Bytes Field |
| 1653 | * 8 LRH |
| 1654 | * 40 GRH (optional) |
| 1655 | * 12 BTH |
| 1656 | * ?? KDETH |
| 1657 | * 8 RHF |
| 1658 | * --- |
| 1659 | * 68 + KDETH |
| 1660 | * |
| 1661 | * We also want to maintain a cache line alignment to assist DMA'ing |
| 1662 | * of the header bytes. Round up to a good size. |
| 1663 | */ |
| 1664 | #define DEFAULT_RCVHDR_ENTSIZE 32 |
| 1665 | |
Mitko Haralanov | def8228 | 2015-12-08 17:10:09 -0500 | [diff] [blame] | 1666 | int hfi1_acquire_user_pages(unsigned long, size_t, bool, struct page **); |
| 1667 | void hfi1_release_user_pages(struct page **, size_t, bool); |
Mike Marciniszyn | 7724105 | 2015-07-30 15:17:43 -0400 | [diff] [blame] | 1668 | |
| 1669 | static inline void clear_rcvhdrtail(const struct hfi1_ctxtdata *rcd) |
| 1670 | { |
Jubin John | 50e5dcb | 2016-02-14 20:19:41 -0800 | [diff] [blame^] | 1671 | *((u64 *)rcd->rcvhdrtail_kvaddr) = 0ULL; |
Mike Marciniszyn | 7724105 | 2015-07-30 15:17:43 -0400 | [diff] [blame] | 1672 | } |
| 1673 | |
| 1674 | static inline u32 get_rcvhdrtail(const struct hfi1_ctxtdata *rcd) |
| 1675 | { |
| 1676 | /* |
| 1677 | * volatile because it's a DMA target from the chip, routine is |
| 1678 | * inlined, and don't want register caching or reordering. |
| 1679 | */ |
Jubin John | 50e5dcb | 2016-02-14 20:19:41 -0800 | [diff] [blame^] | 1680 | return (u32)le64_to_cpu(*rcd->rcvhdrtail_kvaddr); |
Mike Marciniszyn | 7724105 | 2015-07-30 15:17:43 -0400 | [diff] [blame] | 1681 | } |
| 1682 | |
| 1683 | /* |
| 1684 | * sysfs interface. |
| 1685 | */ |
| 1686 | |
| 1687 | extern const char ib_hfi1_version[]; |
| 1688 | |
| 1689 | int hfi1_device_create(struct hfi1_devdata *); |
| 1690 | void hfi1_device_remove(struct hfi1_devdata *); |
| 1691 | |
| 1692 | int hfi1_create_port_files(struct ib_device *ibdev, u8 port_num, |
| 1693 | struct kobject *kobj); |
| 1694 | int hfi1_verbs_register_sysfs(struct hfi1_devdata *); |
| 1695 | void hfi1_verbs_unregister_sysfs(struct hfi1_devdata *); |
| 1696 | /* Hook for sysfs read of QSFP */ |
| 1697 | int qsfp_dump(struct hfi1_pportdata *ppd, char *buf, int len); |
| 1698 | |
| 1699 | int hfi1_pcie_init(struct pci_dev *, const struct pci_device_id *); |
| 1700 | void hfi1_pcie_cleanup(struct pci_dev *); |
| 1701 | int hfi1_pcie_ddinit(struct hfi1_devdata *, struct pci_dev *, |
| 1702 | const struct pci_device_id *); |
| 1703 | void hfi1_pcie_ddcleanup(struct hfi1_devdata *); |
| 1704 | void hfi1_pcie_flr(struct hfi1_devdata *); |
| 1705 | int pcie_speeds(struct hfi1_devdata *); |
| 1706 | void request_msix(struct hfi1_devdata *, u32 *, struct hfi1_msix_entry *); |
| 1707 | void hfi1_enable_intx(struct pci_dev *); |
Mike Marciniszyn | 7724105 | 2015-07-30 15:17:43 -0400 | [diff] [blame] | 1708 | void restore_pci_variables(struct hfi1_devdata *dd); |
| 1709 | int do_pcie_gen3_transition(struct hfi1_devdata *dd); |
| 1710 | int parse_platform_config(struct hfi1_devdata *dd); |
| 1711 | int get_platform_config_field(struct hfi1_devdata *dd, |
| 1712 | enum platform_config_table_type_encoding table_type, |
| 1713 | int table_index, int field_index, u32 *data, u32 len); |
| 1714 | |
Mike Marciniszyn | 7724105 | 2015-07-30 15:17:43 -0400 | [diff] [blame] | 1715 | const char *get_unit_name(int unit); |
Dennis Dalessandro | 49dbb6c | 2016-01-19 14:42:06 -0800 | [diff] [blame] | 1716 | const char *get_card_name(struct rvt_dev_info *rdi); |
| 1717 | struct pci_dev *get_pci_dev(struct rvt_dev_info *rdi); |
Mike Marciniszyn | 7724105 | 2015-07-30 15:17:43 -0400 | [diff] [blame] | 1718 | |
| 1719 | /* |
| 1720 | * Flush write combining store buffers (if present) and perform a write |
| 1721 | * barrier. |
| 1722 | */ |
| 1723 | static inline void flush_wc(void) |
| 1724 | { |
| 1725 | asm volatile("sfence" : : : "memory"); |
| 1726 | } |
| 1727 | |
| 1728 | void handle_eflags(struct hfi1_packet *packet); |
| 1729 | int process_receive_ib(struct hfi1_packet *packet); |
| 1730 | int process_receive_bypass(struct hfi1_packet *packet); |
| 1731 | int process_receive_error(struct hfi1_packet *packet); |
| 1732 | int kdeth_process_expected(struct hfi1_packet *packet); |
| 1733 | int kdeth_process_eager(struct hfi1_packet *packet); |
| 1734 | int process_receive_invalid(struct hfi1_packet *packet); |
| 1735 | |
| 1736 | extern rhf_rcv_function_ptr snoop_rhf_rcv_functions[8]; |
| 1737 | |
Dennis Dalessandro | 895420d | 2016-01-19 14:42:28 -0800 | [diff] [blame] | 1738 | void update_sge(struct rvt_sge_state *ss, u32 length); |
Mike Marciniszyn | 7724105 | 2015-07-30 15:17:43 -0400 | [diff] [blame] | 1739 | |
| 1740 | /* global module parameter variables */ |
| 1741 | extern unsigned int hfi1_max_mtu; |
| 1742 | extern unsigned int hfi1_cu; |
| 1743 | extern unsigned int user_credit_return_threshold; |
Sebastian Sanchez | 2ce6bf2 | 2015-12-11 08:44:48 -0500 | [diff] [blame] | 1744 | extern int num_user_contexts; |
Mike Marciniszyn | 7724105 | 2015-07-30 15:17:43 -0400 | [diff] [blame] | 1745 | extern unsigned n_krcvqs; |
Mark F. Brown | 5b55ea3 | 2016-01-11 18:30:54 -0500 | [diff] [blame] | 1746 | extern uint krcvqs[]; |
Mike Marciniszyn | 7724105 | 2015-07-30 15:17:43 -0400 | [diff] [blame] | 1747 | extern int krcvqsset; |
| 1748 | extern uint kdeth_qp; |
| 1749 | extern uint loopback; |
| 1750 | extern uint quick_linkup; |
| 1751 | extern uint rcv_intr_timeout; |
| 1752 | extern uint rcv_intr_count; |
| 1753 | extern uint rcv_intr_dynamic; |
| 1754 | extern ushort link_crc_mask; |
| 1755 | |
| 1756 | extern struct mutex hfi1_mutex; |
| 1757 | |
| 1758 | /* Number of seconds before our card status check... */ |
| 1759 | #define STATUS_TIMEOUT 60 |
| 1760 | |
| 1761 | #define DRIVER_NAME "hfi1" |
| 1762 | #define HFI1_USER_MINOR_BASE 0 |
| 1763 | #define HFI1_TRACE_MINOR 127 |
| 1764 | #define HFI1_DIAGPKT_MINOR 128 |
| 1765 | #define HFI1_DIAG_MINOR_BASE 129 |
| 1766 | #define HFI1_SNOOP_CAPTURE_BASE 200 |
| 1767 | #define HFI1_NMINORS 255 |
| 1768 | |
| 1769 | #define PCI_VENDOR_ID_INTEL 0x8086 |
| 1770 | #define PCI_DEVICE_ID_INTEL0 0x24f0 |
| 1771 | #define PCI_DEVICE_ID_INTEL1 0x24f1 |
| 1772 | |
| 1773 | #define HFI1_PKT_USER_SC_INTEGRITY \ |
| 1774 | (SEND_CTXT_CHECK_ENABLE_DISALLOW_NON_KDETH_PACKETS_SMASK \ |
| 1775 | | SEND_CTXT_CHECK_ENABLE_DISALLOW_BYPASS_SMASK \ |
| 1776 | | SEND_CTXT_CHECK_ENABLE_DISALLOW_GRH_SMASK) |
| 1777 | |
| 1778 | #define HFI1_PKT_KERNEL_SC_INTEGRITY \ |
| 1779 | (SEND_CTXT_CHECK_ENABLE_DISALLOW_KDETH_PACKETS_SMASK) |
| 1780 | |
| 1781 | static inline u64 hfi1_pkt_default_send_ctxt_mask(struct hfi1_devdata *dd, |
| 1782 | u16 ctxt_type) |
| 1783 | { |
| 1784 | u64 base_sc_integrity = |
| 1785 | SEND_CTXT_CHECK_ENABLE_DISALLOW_BYPASS_BAD_PKT_LEN_SMASK |
| 1786 | | SEND_CTXT_CHECK_ENABLE_DISALLOW_PBC_STATIC_RATE_CONTROL_SMASK |
| 1787 | | SEND_CTXT_CHECK_ENABLE_DISALLOW_TOO_LONG_BYPASS_PACKETS_SMASK |
| 1788 | | SEND_CTXT_CHECK_ENABLE_DISALLOW_TOO_LONG_IB_PACKETS_SMASK |
| 1789 | | SEND_CTXT_CHECK_ENABLE_DISALLOW_BAD_PKT_LEN_SMASK |
| 1790 | | SEND_CTXT_CHECK_ENABLE_DISALLOW_PBC_TEST_SMASK |
| 1791 | | SEND_CTXT_CHECK_ENABLE_DISALLOW_TOO_SMALL_BYPASS_PACKETS_SMASK |
| 1792 | | SEND_CTXT_CHECK_ENABLE_DISALLOW_TOO_SMALL_IB_PACKETS_SMASK |
| 1793 | | SEND_CTXT_CHECK_ENABLE_DISALLOW_RAW_IPV6_SMASK |
| 1794 | | SEND_CTXT_CHECK_ENABLE_DISALLOW_RAW_SMASK |
| 1795 | | SEND_CTXT_CHECK_ENABLE_CHECK_BYPASS_VL_MAPPING_SMASK |
| 1796 | | SEND_CTXT_CHECK_ENABLE_CHECK_VL_MAPPING_SMASK |
| 1797 | | SEND_CTXT_CHECK_ENABLE_CHECK_OPCODE_SMASK |
| 1798 | | SEND_CTXT_CHECK_ENABLE_CHECK_SLID_SMASK |
| 1799 | | SEND_CTXT_CHECK_ENABLE_CHECK_JOB_KEY_SMASK |
| 1800 | | SEND_CTXT_CHECK_ENABLE_CHECK_VL_SMASK |
| 1801 | | SEND_CTXT_CHECK_ENABLE_CHECK_ENABLE_SMASK; |
| 1802 | |
| 1803 | if (ctxt_type == SC_USER) |
| 1804 | base_sc_integrity |= HFI1_PKT_USER_SC_INTEGRITY; |
| 1805 | else |
| 1806 | base_sc_integrity |= HFI1_PKT_KERNEL_SC_INTEGRITY; |
| 1807 | |
Mike Marciniszyn | 995deaf | 2015-11-16 21:59:29 -0500 | [diff] [blame] | 1808 | if (is_ax(dd)) |
Edward Mascarenhas | 624be1d | 2016-01-11 18:31:43 -0500 | [diff] [blame] | 1809 | /* turn off send-side job key checks - A0 */ |
Mike Marciniszyn | 7724105 | 2015-07-30 15:17:43 -0400 | [diff] [blame] | 1810 | return base_sc_integrity & |
| 1811 | ~SEND_CTXT_CHECK_ENABLE_CHECK_JOB_KEY_SMASK; |
| 1812 | return base_sc_integrity; |
| 1813 | } |
| 1814 | |
| 1815 | static inline u64 hfi1_pkt_base_sdma_integrity(struct hfi1_devdata *dd) |
| 1816 | { |
| 1817 | u64 base_sdma_integrity = |
| 1818 | SEND_DMA_CHECK_ENABLE_DISALLOW_BYPASS_BAD_PKT_LEN_SMASK |
| 1819 | | SEND_DMA_CHECK_ENABLE_DISALLOW_PBC_STATIC_RATE_CONTROL_SMASK |
| 1820 | | SEND_DMA_CHECK_ENABLE_DISALLOW_TOO_LONG_BYPASS_PACKETS_SMASK |
| 1821 | | SEND_DMA_CHECK_ENABLE_DISALLOW_TOO_LONG_IB_PACKETS_SMASK |
| 1822 | | SEND_DMA_CHECK_ENABLE_DISALLOW_BAD_PKT_LEN_SMASK |
| 1823 | | SEND_DMA_CHECK_ENABLE_DISALLOW_TOO_SMALL_BYPASS_PACKETS_SMASK |
| 1824 | | SEND_DMA_CHECK_ENABLE_DISALLOW_TOO_SMALL_IB_PACKETS_SMASK |
| 1825 | | SEND_DMA_CHECK_ENABLE_DISALLOW_RAW_IPV6_SMASK |
| 1826 | | SEND_DMA_CHECK_ENABLE_DISALLOW_RAW_SMASK |
| 1827 | | SEND_DMA_CHECK_ENABLE_CHECK_BYPASS_VL_MAPPING_SMASK |
| 1828 | | SEND_DMA_CHECK_ENABLE_CHECK_VL_MAPPING_SMASK |
| 1829 | | SEND_DMA_CHECK_ENABLE_CHECK_OPCODE_SMASK |
| 1830 | | SEND_DMA_CHECK_ENABLE_CHECK_SLID_SMASK |
| 1831 | | SEND_DMA_CHECK_ENABLE_CHECK_JOB_KEY_SMASK |
| 1832 | | SEND_DMA_CHECK_ENABLE_CHECK_VL_SMASK |
| 1833 | | SEND_DMA_CHECK_ENABLE_CHECK_ENABLE_SMASK; |
| 1834 | |
Mike Marciniszyn | 995deaf | 2015-11-16 21:59:29 -0500 | [diff] [blame] | 1835 | if (is_ax(dd)) |
Edward Mascarenhas | 624be1d | 2016-01-11 18:31:43 -0500 | [diff] [blame] | 1836 | /* turn off send-side job key checks - A0 */ |
Mike Marciniszyn | 7724105 | 2015-07-30 15:17:43 -0400 | [diff] [blame] | 1837 | return base_sdma_integrity & |
| 1838 | ~SEND_DMA_CHECK_ENABLE_CHECK_JOB_KEY_SMASK; |
| 1839 | return base_sdma_integrity; |
| 1840 | } |
| 1841 | |
| 1842 | /* |
| 1843 | * hfi1_early_err is used (only!) to print early errors before devdata is |
| 1844 | * allocated, or when dd->pcidev may not be valid, and at the tail end of |
| 1845 | * cleanup when devdata may have been freed, etc. hfi1_dev_porterr is |
| 1846 | * the same as dd_dev_err, but is used when the message really needs |
| 1847 | * the IB port# to be definitive as to what's happening.. |
| 1848 | */ |
| 1849 | #define hfi1_early_err(dev, fmt, ...) \ |
| 1850 | dev_err(dev, fmt, ##__VA_ARGS__) |
| 1851 | |
| 1852 | #define hfi1_early_info(dev, fmt, ...) \ |
| 1853 | dev_info(dev, fmt, ##__VA_ARGS__) |
| 1854 | |
| 1855 | #define dd_dev_emerg(dd, fmt, ...) \ |
| 1856 | dev_emerg(&(dd)->pcidev->dev, "%s: " fmt, \ |
| 1857 | get_unit_name((dd)->unit), ##__VA_ARGS__) |
| 1858 | #define dd_dev_err(dd, fmt, ...) \ |
| 1859 | dev_err(&(dd)->pcidev->dev, "%s: " fmt, \ |
| 1860 | get_unit_name((dd)->unit), ##__VA_ARGS__) |
| 1861 | #define dd_dev_warn(dd, fmt, ...) \ |
| 1862 | dev_warn(&(dd)->pcidev->dev, "%s: " fmt, \ |
| 1863 | get_unit_name((dd)->unit), ##__VA_ARGS__) |
| 1864 | |
| 1865 | #define dd_dev_warn_ratelimited(dd, fmt, ...) \ |
| 1866 | dev_warn_ratelimited(&(dd)->pcidev->dev, "%s: " fmt, \ |
| 1867 | get_unit_name((dd)->unit), ##__VA_ARGS__) |
| 1868 | |
| 1869 | #define dd_dev_info(dd, fmt, ...) \ |
| 1870 | dev_info(&(dd)->pcidev->dev, "%s: " fmt, \ |
| 1871 | get_unit_name((dd)->unit), ##__VA_ARGS__) |
| 1872 | |
Ira Weiny | a1edc18 | 2016-01-11 13:04:32 -0500 | [diff] [blame] | 1873 | #define dd_dev_dbg(dd, fmt, ...) \ |
| 1874 | dev_dbg(&(dd)->pcidev->dev, "%s: " fmt, \ |
| 1875 | get_unit_name((dd)->unit), ##__VA_ARGS__) |
| 1876 | |
Mike Marciniszyn | 7724105 | 2015-07-30 15:17:43 -0400 | [diff] [blame] | 1877 | #define hfi1_dev_porterr(dd, port, fmt, ...) \ |
| 1878 | dev_err(&(dd)->pcidev->dev, "%s: IB%u:%u " fmt, \ |
| 1879 | get_unit_name((dd)->unit), (dd)->unit, (port), \ |
| 1880 | ##__VA_ARGS__) |
| 1881 | |
| 1882 | /* |
| 1883 | * this is used for formatting hw error messages... |
| 1884 | */ |
| 1885 | struct hfi1_hwerror_msgs { |
| 1886 | u64 mask; |
| 1887 | const char *msg; |
| 1888 | size_t sz; |
| 1889 | }; |
| 1890 | |
| 1891 | /* in intr.c... */ |
| 1892 | void hfi1_format_hwerrors(u64 hwerrs, |
| 1893 | const struct hfi1_hwerror_msgs *hwerrmsgs, |
| 1894 | size_t nhwerrmsgs, char *msg, size_t lmsg); |
| 1895 | |
| 1896 | #define USER_OPCODE_CHECK_VAL 0xC0 |
| 1897 | #define USER_OPCODE_CHECK_MASK 0xC0 |
| 1898 | #define OPCODE_CHECK_VAL_DISABLED 0x0 |
| 1899 | #define OPCODE_CHECK_MASK_DISABLED 0x0 |
| 1900 | |
| 1901 | static inline void hfi1_reset_cpu_counters(struct hfi1_devdata *dd) |
| 1902 | { |
| 1903 | struct hfi1_pportdata *ppd; |
| 1904 | int i; |
| 1905 | |
| 1906 | dd->z_int_counter = get_all_cpu_total(dd->int_counter); |
| 1907 | dd->z_rcv_limit = get_all_cpu_total(dd->rcv_limit); |
Vennila Megavannan | 89abfc8 | 2016-02-03 14:34:07 -0800 | [diff] [blame] | 1908 | dd->z_send_schedule = get_all_cpu_total(dd->send_schedule); |
Mike Marciniszyn | 7724105 | 2015-07-30 15:17:43 -0400 | [diff] [blame] | 1909 | |
| 1910 | ppd = (struct hfi1_pportdata *)(dd + 1); |
| 1911 | for (i = 0; i < dd->num_pports; i++, ppd++) { |
Dennis Dalessandro | 4eb0688 | 2016-01-19 14:42:39 -0800 | [diff] [blame] | 1912 | ppd->ibport_data.rvp.z_rc_acks = |
| 1913 | get_all_cpu_total(ppd->ibport_data.rvp.rc_acks); |
| 1914 | ppd->ibport_data.rvp.z_rc_qacks = |
| 1915 | get_all_cpu_total(ppd->ibport_data.rvp.rc_qacks); |
Mike Marciniszyn | 7724105 | 2015-07-30 15:17:43 -0400 | [diff] [blame] | 1916 | } |
| 1917 | } |
| 1918 | |
| 1919 | /* Control LED state */ |
| 1920 | static inline void setextled(struct hfi1_devdata *dd, u32 on) |
| 1921 | { |
| 1922 | if (on) |
| 1923 | write_csr(dd, DCC_CFG_LED_CNTRL, 0x1F); |
| 1924 | else |
| 1925 | write_csr(dd, DCC_CFG_LED_CNTRL, 0x10); |
| 1926 | } |
| 1927 | |
| 1928 | int hfi1_tempsense_rd(struct hfi1_devdata *dd, struct hfi1_temp *temp); |
| 1929 | |
| 1930 | #endif /* _HFI1_KERNEL_H */ |