blob: 5cc71e2abf959d7aba4d1c5631b194209e72e41d [file] [log] [blame]
Catalin Marinas8c2c3df2012-04-20 14:45:54 +01001config ARM64
2 def_bool y
Arun Chandran92980402014-10-10 12:31:24 +01003 select ARCH_BINFMT_ELF_RANDOMIZE_PIE
Catalin Marinas8c2c3df2012-04-20 14:45:54 +01004 select ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE
Riku Voipio957e3fa2014-12-12 16:57:44 -08005 select ARCH_HAS_GCOV_PROFILE_ALL
Laura Abbott308c09f2014-08-08 14:23:25 -07006 select ARCH_HAS_SG_CHAIN
Lorenzo Pieralisi1f850082013-09-04 10:55:17 +01007 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
Sudeep Hollac63c8702014-05-09 10:33:01 +01008 select ARCH_USE_CMPXCHG_LOCKREF
Peter Zijlstra4badad32014-06-06 19:53:16 +02009 select ARCH_SUPPORTS_ATOMIC_RMW
Arnd Bergmann91701002013-02-21 11:42:57 +010010 select ARCH_WANT_OPTIONAL_GPIOLIB
Will Deacon6212a512012-11-07 14:16:28 +000011 select ARCH_WANT_COMPAT_IPC_PARSE_VERSION
Catalin Marinasb6f35982013-01-29 18:25:41 +000012 select ARCH_WANT_FRAME_POINTERS
Catalin Marinas25c92a32012-12-18 15:26:13 +000013 select ARM_AMBA
Mark Rutland1aee5d72012-11-20 10:06:00 +000014 select ARM_ARCH_TIMER
Catalin Marinasc4188ed2013-01-14 12:39:31 +000015 select ARM_GIC
AKASHI Takahiro875cbf32014-07-04 08:28:30 +010016 select AUDIT_ARCH_COMPAT_GENERIC
Suravee Suthikulpanit853a33c2014-11-25 18:47:22 +000017 select ARM_GIC_V2M if PCI_MSI
Marc Zyngier021f6532014-06-30 16:01:31 +010018 select ARM_GIC_V3
Marc Zyngier19812722014-11-24 14:35:19 +000019 select ARM_GIC_V3_ITS if PCI_MSI
Will Deaconadace892013-05-08 17:29:24 +010020 select BUILDTIME_EXTABLE_SORT
Catalin Marinasdb2789b2012-12-18 15:27:25 +000021 select CLONE_BACKWARDS
Deepak Saxena7ca2ef32012-09-22 10:33:36 -070022 select COMMON_CLK
Lorenzo Pieralisi166936b2013-11-07 18:37:14 +000023 select CPU_PM if (SUSPEND || CPU_IDLE)
Will Deacon7bc13fd2013-11-06 19:32:13 +000024 select DCACHE_WORD_ACCESS
Laura Abbottd4932f92014-10-09 15:26:44 -070025 select GENERIC_ALLOCATOR
Catalin Marinas8c2c3df2012-04-20 14:45:54 +010026 select GENERIC_CLOCKEVENTS
Lorenzo Pieralisi1f850082013-09-04 10:55:17 +010027 select GENERIC_CLOCKEVENTS_BROADCAST if SMP
Ard Biesheuvel3be1a5c2014-03-04 01:10:04 +000028 select GENERIC_CPU_AUTOPROBE
Mark Salterbf4b5582014-04-07 15:39:52 -070029 select GENERIC_EARLY_IOREMAP
Catalin Marinas8c2c3df2012-04-20 14:45:54 +010030 select GENERIC_IRQ_PROBE
31 select GENERIC_IRQ_SHOW
Arnd Bergmanncb61f672014-11-19 14:09:07 +010032 select GENERIC_PCI_IOMAP
Stephen Boyd65cd4f62013-07-18 16:21:18 -070033 select GENERIC_SCHED_CLOCK
Catalin Marinas8c2c3df2012-04-20 14:45:54 +010034 select GENERIC_SMP_IDLE_THREAD
Will Deacon12a0ef72013-11-06 17:20:22 +000035 select GENERIC_STRNCPY_FROM_USER
36 select GENERIC_STRNLEN_USER
Catalin Marinas8c2c3df2012-04-20 14:45:54 +010037 select GENERIC_TIME_VSYSCALL
Marc Zyngiera1ddc742014-08-26 11:03:17 +010038 select HANDLE_DOMAIN_IRQ
Catalin Marinas8c2c3df2012-04-20 14:45:54 +010039 select HARDIRQS_SW_RESEND
Steve Capper5284e1b2014-10-24 13:22:20 +010040 select HAVE_ALIGNED_STRUCT_PAGE if SLUB
AKASHI Takahiro875cbf32014-07-04 08:28:30 +010041 select HAVE_ARCH_AUDITSYSCALL
Jiang Liu9732caf2014-01-07 22:17:13 +080042 select HAVE_ARCH_JUMP_LABEL
Vijaya Kumar K95292472014-01-28 11:20:22 +000043 select HAVE_ARCH_KGDB
AKASHI Takahiroa1ae65b2014-11-28 05:26:39 +000044 select HAVE_ARCH_SECCOMP_FILTER
Catalin Marinas8c2c3df2012-04-20 14:45:54 +010045 select HAVE_ARCH_TRACEHOOK
Zi Shen Lime54bcde2014-08-26 21:15:30 -070046 select HAVE_BPF_JIT
AKASHI Takahiroaf64d2a2014-04-30 10:54:32 +010047 select HAVE_C_RECORDMCOUNT
Laura Abbottc0c264a2014-06-25 23:55:03 +010048 select HAVE_CC_STACKPROTECTOR
Steve Capper5284e1b2014-10-24 13:22:20 +010049 select HAVE_CMPXCHG_DOUBLE
Catalin Marinas9b2a60c2012-10-08 16:28:13 -070050 select HAVE_DEBUG_BUGVERBOSE
Catalin Marinasb69ec422012-10-08 16:28:11 -070051 select HAVE_DEBUG_KMEMLEAK
Catalin Marinas8c2c3df2012-04-20 14:45:54 +010052 select HAVE_DMA_API_DEBUG
53 select HAVE_DMA_ATTRS
Laura Abbott6ac21042013-12-12 19:28:33 +000054 select HAVE_DMA_CONTIGUOUS
AKASHI Takahirobd7d38d2014-04-30 10:54:34 +010055 select HAVE_DYNAMIC_FTRACE
Will Deacon50afc332013-12-16 17:50:08 +000056 select HAVE_EFFICIENT_UNALIGNED_ACCESS
AKASHI Takahiroaf64d2a2014-04-30 10:54:32 +010057 select HAVE_FTRACE_MCOUNT_RECORD
AKASHI Takahiro819e50e2014-04-30 18:54:33 +090058 select HAVE_FUNCTION_TRACER
59 select HAVE_FUNCTION_GRAPH_TRACER
Catalin Marinas8c2c3df2012-04-20 14:45:54 +010060 select HAVE_GENERIC_DMA_COHERENT
Catalin Marinas8c2c3df2012-04-20 14:45:54 +010061 select HAVE_HW_BREAKPOINT if PERF_EVENTS
Catalin Marinas8c2c3df2012-04-20 14:45:54 +010062 select HAVE_MEMBLOCK
Mark Rutland55834a72014-02-07 17:12:45 +000063 select HAVE_PATA_PLATFORM
Catalin Marinas8c2c3df2012-04-20 14:45:54 +010064 select HAVE_PERF_EVENTS
Jean Pihet2ee0d7f2014-02-03 19:18:27 +010065 select HAVE_PERF_REGS
66 select HAVE_PERF_USER_STACK_DUMP
Steve Capper5e5f6dc2014-10-09 15:29:23 -070067 select HAVE_RCU_TABLE_FREE
AKASHI Takahiro055b1212014-04-30 10:54:36 +010068 select HAVE_SYSCALL_TRACEPOINTS
Catalin Marinas8c2c3df2012-04-20 14:45:54 +010069 select IRQ_DOMAIN
Catalin Marinasfea2aca2012-10-16 11:26:57 +010070 select MODULES_USE_ELF_RELA
Catalin Marinas8c2c3df2012-04-20 14:45:54 +010071 select NO_BOOTMEM
72 select OF
73 select OF_EARLY_FLATTREE
Marek Szyprowski9bf14b72014-02-28 14:42:55 +010074 select OF_RESERVED_MEM
Catalin Marinas8c2c3df2012-04-20 14:45:54 +010075 select PERF_USE_VMALLOC
Catalin Marinasaa1e8ec2013-02-28 18:14:37 +000076 select POWER_RESET
77 select POWER_SUPPLY
Catalin Marinas8c2c3df2012-04-20 14:45:54 +010078 select RTC_LIB
79 select SPARSE_IRQ
Catalin Marinas7ac57a82012-10-08 16:28:16 -070080 select SYSCTL_EXCEPTION_TRACE
Larry Bassel6c81fe72014-05-30 12:34:15 -070081 select HAVE_CONTEXT_TRACKING
Catalin Marinas8c2c3df2012-04-20 14:45:54 +010082 help
83 ARM 64-bit (AArch64) Linux support.
84
85config 64BIT
86 def_bool y
87
88config ARCH_PHYS_ADDR_T_64BIT
89 def_bool y
90
91config MMU
92 def_bool y
93
Uwe Kleine-Königce816fa2014-04-07 15:39:19 -070094config NO_IOPORT_MAP
Liviu Dudaud1e6dc92014-09-29 15:29:31 +010095 def_bool y if !PCI
Catalin Marinas8c2c3df2012-04-20 14:45:54 +010096
97config STACKTRACE_SUPPORT
98 def_bool y
99
100config LOCKDEP_SUPPORT
101 def_bool y
102
103config TRACE_IRQFLAGS_SUPPORT
104 def_bool y
105
Will Deaconc209f792014-03-14 17:47:05 +0000106config RWSEM_XCHGADD_ALGORITHM
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100107 def_bool y
108
109config GENERIC_HWEIGHT
110 def_bool y
111
112config GENERIC_CSUM
113 def_bool y
114
115config GENERIC_CALIBRATE_DELAY
116 def_bool y
117
Catalin Marinas19e76402014-02-27 12:09:22 +0000118config ZONE_DMA
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100119 def_bool y
120
Steve Capper29e56942014-10-09 15:29:25 -0700121config HAVE_GENERIC_RCU_GUP
122 def_bool y
123
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100124config ARCH_DMA_ADDR_T_64BIT
125 def_bool y
126
127config NEED_DMA_MAP_STATE
128 def_bool y
129
130config NEED_SG_DMA_LENGTH
131 def_bool y
132
133config SWIOTLB
134 def_bool y
135
136config IOMMU_HELPER
137 def_bool SWIOTLB
138
Ard Biesheuvel4cfb3612013-07-09 14:18:12 +0100139config KERNEL_MODE_NEON
140 def_bool y
141
Rob Herring92cc15f2014-04-18 17:19:59 -0500142config FIX_EARLYCON_MEM
143 def_bool y
144
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100145source "init/Kconfig"
146
147source "kernel/Kconfig.freezer"
148
Catalin Marinas1ae90e72012-09-05 17:47:44 +0100149menu "Platform selection"
150
Alim Akhtar6f56eef2014-11-22 22:41:52 +0900151config ARCH_EXYNOS
152 bool
153 help
154 This enables support for Samsung Exynos SoC family
155
156config ARCH_EXYNOS7
157 bool "ARMv8 based Samsung Exynos7"
158 select ARCH_EXYNOS
159 select COMMON_CLK_SAMSUNG
160 select HAVE_S3C2410_WATCHDOG if WATCHDOG
161 select HAVE_S3C_RTC if RTC_CLASS
162 select PINCTRL
163 select PINCTRL_EXYNOS
164
165 help
166 This enables support for Samsung Exynos7 SoC family
167
Olof Johansson5118a6a2015-01-27 16:19:11 -0800168config ARCH_FSL_LS2085A
169 bool "Freescale LS2085A SOC"
170 help
171 This enables support for Freescale LS2085A SOC.
172
Eddie Huang4727a6f2015-12-01 10:14:00 +0100173config ARCH_MEDIATEK
174 bool "Mediatek MT65xx & MT81xx ARMv8 SoC"
175 select ARM_GIC
176 help
177 Support for Mediatek MT65xx & MT81xx ARMv8 SoCs
178
Suravee Suthikulpanit41904362014-11-26 11:51:09 +0700179config ARCH_SEATTLE
180 bool "AMD Seattle SoC Family"
181 help
182 This enables support for AMD Seattle SOC Family
183
Paul Walmsleyd035fdf2015-01-07 01:17:33 -0700184config ARCH_TEGRA
185 bool "NVIDIA Tegra SoC Family"
186 select ARCH_HAS_RESET_CONTROLLER
187 select ARCH_REQUIRE_GPIOLIB
188 select CLKDEV_LOOKUP
189 select CLKSRC_MMIO
190 select CLKSRC_OF
191 select GENERIC_CLOCKEVENTS
192 select HAVE_CLK
193 select HAVE_SMP
194 select PINCTRL
195 select RESET_CONTROLLER
196 help
197 This enables support for the NVIDIA Tegra SoC family.
198
199config ARCH_TEGRA_132_SOC
200 bool "NVIDIA Tegra132 SoC"
201 depends on ARCH_TEGRA
202 select PINCTRL_TEGRA124
203 select USB_ARCH_HAS_EHCI if USB_SUPPORT
204 select USB_ULPI if USB_PHY
205 select USB_ULPI_VIEWPORT if USB_PHY
206 help
207 Enable support for NVIDIA Tegra132 SoC, based on the Denver
208 ARMv8 CPU. The Tegra132 SoC is similar to the Tegra124 SoC,
209 but contains an NVIDIA Denver CPU complex in place of
210 Tegra124's "4+1" Cortex-A15 CPU complex.
211
Radha Mohan Chintakuntla28f74202014-04-08 18:47:51 +0530212config ARCH_THUNDER
213 bool "Cavium Inc. Thunder SoC Family"
214 help
215 This enables support for Cavium's Thunder Family of SoCs.
216
Catalin Marinas1ae90e72012-09-05 17:47:44 +0100217config ARCH_VEXPRESS
218 bool "ARMv8 software model (Versatile Express)"
219 select ARCH_REQUIRE_GPIOLIB
220 select COMMON_CLK_VERSATILE
Catalin Marinasaa1e8ec2013-02-28 18:14:37 +0000221 select POWER_RESET_VEXPRESS
Catalin Marinas1ae90e72012-09-05 17:47:44 +0100222 select VEXPRESS_CONFIG
223 help
224 This enables support for the ARMv8 software model (Versatile
225 Express).
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100226
Vinayak Kale15942852013-04-24 10:06:57 +0100227config ARCH_XGENE
228 bool "AppliedMicro X-Gene SOC Family"
229 help
230 This enables support for AppliedMicro X-Gene SOC Family
231
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100232endmenu
233
234menu "Bus support"
235
Liviu Dudaud1e6dc92014-09-29 15:29:31 +0100236config PCI
237 bool "PCI support"
238 help
239 This feature enables support for PCI bus system. If you say Y
240 here, the kernel will include drivers and infrastructure code
241 to support PCI bus devices.
242
243config PCI_DOMAINS
244 def_bool PCI
245
246config PCI_DOMAINS_GENERIC
247 def_bool PCI
248
249config PCI_SYSCALL
250 def_bool PCI
251
252source "drivers/pci/Kconfig"
253source "drivers/pci/pcie/Kconfig"
254source "drivers/pci/hotplug/Kconfig"
255
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100256endmenu
257
258menu "Kernel Features"
259
Andre Przywarac0a01b82014-11-14 15:54:12 +0000260menu "ARM errata workarounds via the alternatives framework"
261
262config ARM64_ERRATUM_826319
263 bool "Cortex-A53: 826319: System might deadlock if a write cannot complete until read data is accepted"
264 default y
265 help
266 This option adds an alternative code sequence to work around ARM
267 erratum 826319 on Cortex-A53 parts up to r0p2 with an AMBA 4 ACE or
268 AXI master interface and an L2 cache.
269
270 If a Cortex-A53 uses an AMBA AXI4 ACE interface to other processors
271 and is unable to accept a certain write via this interface, it will
272 not progress on read data presented on the read data channel and the
273 system can deadlock.
274
275 The workaround promotes data cache clean instructions to
276 data cache clean-and-invalidate.
277 Please note that this does not necessarily enable the workaround,
278 as it depends on the alternative framework, which will only patch
279 the kernel if an affected CPU is detected.
280
281 If unsure, say Y.
282
283config ARM64_ERRATUM_827319
284 bool "Cortex-A53: 827319: Data cache clean instructions might cause overlapping transactions to the interconnect"
285 default y
286 help
287 This option adds an alternative code sequence to work around ARM
288 erratum 827319 on Cortex-A53 parts up to r0p2 with an AMBA 5 CHI
289 master interface and an L2 cache.
290
291 Under certain conditions this erratum can cause a clean line eviction
292 to occur at the same time as another transaction to the same address
293 on the AMBA 5 CHI interface, which can cause data corruption if the
294 interconnect reorders the two transactions.
295
296 The workaround promotes data cache clean instructions to
297 data cache clean-and-invalidate.
298 Please note that this does not necessarily enable the workaround,
299 as it depends on the alternative framework, which will only patch
300 the kernel if an affected CPU is detected.
301
302 If unsure, say Y.
303
304config ARM64_ERRATUM_824069
305 bool "Cortex-A53: 824069: Cache line might not be marked as clean after a CleanShared snoop"
306 default y
307 help
308 This option adds an alternative code sequence to work around ARM
309 erratum 824069 on Cortex-A53 parts up to r0p2 when it is connected
310 to a coherent interconnect.
311
312 If a Cortex-A53 processor is executing a store or prefetch for
313 write instruction at the same time as a processor in another
314 cluster is executing a cache maintenance operation to the same
315 address, then this erratum might cause a clean cache line to be
316 incorrectly marked as dirty.
317
318 The workaround promotes data cache clean instructions to
319 data cache clean-and-invalidate.
320 Please note that this option does not necessarily enable the
321 workaround, as it depends on the alternative framework, which will
322 only patch the kernel if an affected CPU is detected.
323
324 If unsure, say Y.
325
326config ARM64_ERRATUM_819472
327 bool "Cortex-A53: 819472: Store exclusive instructions might cause data corruption"
328 default y
329 help
330 This option adds an alternative code sequence to work around ARM
331 erratum 819472 on Cortex-A53 parts up to r0p1 with an L2 cache
332 present when it is connected to a coherent interconnect.
333
334 If the processor is executing a load and store exclusive sequence at
335 the same time as a processor in another cluster is executing a cache
336 maintenance operation to the same address, then this erratum might
337 cause data corruption.
338
339 The workaround promotes data cache clean instructions to
340 data cache clean-and-invalidate.
341 Please note that this does not necessarily enable the workaround,
342 as it depends on the alternative framework, which will only patch
343 the kernel if an affected CPU is detected.
344
345 If unsure, say Y.
346
347config ARM64_ERRATUM_832075
348 bool "Cortex-A57: 832075: possible deadlock on mixing exclusive memory accesses with device loads"
349 default y
350 help
351 This option adds an alternative code sequence to work around ARM
352 erratum 832075 on Cortex-A57 parts up to r1p2.
353
354 Affected Cortex-A57 parts might deadlock when exclusive load/store
355 instructions to Write-Back memory are mixed with Device loads.
356
357 The workaround is to promote device loads to use Load-Acquire
358 semantics.
359 Please note that this does not necessarily enable the workaround,
360 as it depends on the alternative framework, which will only patch
361 the kernel if an affected CPU is detected.
362
363 If unsure, say Y.
364
365endmenu
366
367
Jungseok Leee41ceed2014-05-12 10:40:38 +0100368choice
369 prompt "Page size"
370 default ARM64_4K_PAGES
371 help
372 Page size (translation granule) configuration.
373
374config ARM64_4K_PAGES
375 bool "4KB"
376 help
377 This feature enables 4KB pages support.
378
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100379config ARM64_64K_PAGES
Jungseok Leee41ceed2014-05-12 10:40:38 +0100380 bool "64KB"
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100381 help
382 This feature enables 64KB pages support (4KB by default)
383 allowing only two levels of page tables and faster TLB
384 look-up. AArch32 emulation is not available when this feature
385 is enabled.
386
Jungseok Leee41ceed2014-05-12 10:40:38 +0100387endchoice
388
389choice
390 prompt "Virtual address space size"
391 default ARM64_VA_BITS_39 if ARM64_4K_PAGES
392 default ARM64_VA_BITS_42 if ARM64_64K_PAGES
393 help
394 Allows choosing one of multiple possible virtual address
395 space sizes. The level of translation table is determined by
396 a combination of page size and virtual address space size.
397
398config ARM64_VA_BITS_39
399 bool "39-bit"
400 depends on ARM64_4K_PAGES
401
402config ARM64_VA_BITS_42
403 bool "42-bit"
404 depends on ARM64_64K_PAGES
405
Jungseok Leec79b9542014-05-12 18:40:51 +0900406config ARM64_VA_BITS_48
407 bool "48-bit"
Christoffer Dall04f905a2014-10-10 11:14:30 +0100408 depends on !ARM_SMMU
Jungseok Leec79b9542014-05-12 18:40:51 +0900409
Jungseok Leee41ceed2014-05-12 10:40:38 +0100410endchoice
411
412config ARM64_VA_BITS
413 int
414 default 39 if ARM64_VA_BITS_39
415 default 42 if ARM64_VA_BITS_42
Jungseok Leec79b9542014-05-12 18:40:51 +0900416 default 48 if ARM64_VA_BITS_48
Jungseok Leee41ceed2014-05-12 10:40:38 +0100417
Catalin Marinasabe669d2014-07-15 15:37:21 +0100418config ARM64_PGTABLE_LEVELS
419 int
420 default 2 if ARM64_64K_PAGES && ARM64_VA_BITS_42
Catalin Marinas383c2792014-07-21 15:54:50 +0100421 default 3 if ARM64_64K_PAGES && ARM64_VA_BITS_48
Catalin Marinasabe669d2014-07-15 15:37:21 +0100422 default 3 if ARM64_4K_PAGES && ARM64_VA_BITS_39
423 default 4 if ARM64_4K_PAGES && ARM64_VA_BITS_48
Jungseok Leec79b9542014-05-12 18:40:51 +0900424
Will Deacona8720132013-10-11 14:52:19 +0100425config CPU_BIG_ENDIAN
426 bool "Build big-endian kernel"
427 help
428 Say Y if you plan on running a kernel in big-endian mode.
429
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100430config SMP
431 bool "Symmetric Multi-Processing"
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100432 help
433 This enables support for systems with more than one CPU. If
434 you say N here, the kernel will run on single and
435 multiprocessor machines, but will use only one CPU of a
436 multiprocessor machine. If you say Y here, the kernel will run
437 on many, but not all, single processor machines. On a single
438 processor machine, the kernel will run faster if you say N
439 here.
440
441 If you don't know what to do here, say N.
442
Mark Brownf6e763b2014-03-04 07:51:17 +0000443config SCHED_MC
444 bool "Multi-core scheduler support"
445 depends on SMP
446 help
447 Multi-core scheduler support improves the CPU scheduler's decision
448 making when dealing with multi-core CPU chips at a cost of slightly
449 increased overhead in some places. If unsure say N here.
450
451config SCHED_SMT
452 bool "SMT scheduler support"
453 depends on SMP
454 help
455 Improves the CPU scheduler's decision making when dealing with
456 MultiThreading at a cost of slightly increased overhead in some
457 places. If unsure say N here.
458
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100459config NR_CPUS
Robert Richtere3672642014-09-08 12:44:48 +0100460 int "Maximum number of CPUs (2-64)"
461 range 2 64
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100462 depends on SMP
Vinayak Kale15942852013-04-24 10:06:57 +0100463 # These have to remain sorted largest to smallest
Robert Richtere3672642014-09-08 12:44:48 +0100464 default "64"
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100465
Mark Rutland9327e2c2013-10-24 20:30:18 +0100466config HOTPLUG_CPU
467 bool "Support for hot-pluggable CPUs"
468 depends on SMP
469 help
470 Say Y here to experiment with turning CPUs off and on. CPUs
471 can be controlled through /sys/devices/system/cpu.
472
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100473source kernel/Kconfig.preempt
474
475config HZ
476 int
477 default 100
478
479config ARCH_HAS_HOLES_MEMORYMODEL
480 def_bool y if SPARSEMEM
481
482config ARCH_SPARSEMEM_ENABLE
483 def_bool y
484 select SPARSEMEM_VMEMMAP_ENABLE
485
486config ARCH_SPARSEMEM_DEFAULT
487 def_bool ARCH_SPARSEMEM_ENABLE
488
489config ARCH_SELECT_MEMORY_MODEL
490 def_bool ARCH_SPARSEMEM_ENABLE
491
492config HAVE_ARCH_PFN_VALID
493 def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
494
495config HW_PERF_EVENTS
496 bool "Enable hardware performance counter support for perf events"
497 depends on PERF_EVENTS
498 default y
499 help
500 Enable hardware performance counter support for perf events. If
501 disabled, perf events will use software events only.
502
Steve Capper084bd292013-04-10 13:48:00 +0100503config SYS_SUPPORTS_HUGETLBFS
504 def_bool y
505
506config ARCH_WANT_GENERAL_HUGETLB
507 def_bool y
508
509config ARCH_WANT_HUGE_PMD_SHARE
510 def_bool y if !ARM64_64K_PAGES
511
Steve Capperaf074842013-04-19 16:23:57 +0100512config HAVE_ARCH_TRANSPARENT_HUGEPAGE
513 def_bool y
514
Catalin Marinasa41dc0e2014-04-03 17:48:54 +0100515config ARCH_HAS_CACHE_LINE_SIZE
516 def_bool y
517
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100518source "mm/Kconfig"
519
AKASHI Takahiroa1ae65b2014-11-28 05:26:39 +0000520config SECCOMP
521 bool "Enable seccomp to safely compute untrusted bytecode"
522 ---help---
523 This kernel feature is useful for number crunching applications
524 that may need to compute untrusted bytecode during their
525 execution. By using pipes or other transports made available to
526 the process as file descriptors supporting the read/write
527 syscalls, it's possible to isolate those applications in
528 their own address space using seccomp. Once seccomp is
529 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
530 and the task is only allowed to execute a few safe syscalls
531 defined by each seccomp mode.
532
Stefano Stabelliniaa42aa12013-06-03 17:05:43 +0000533config XEN_DOM0
534 def_bool y
535 depends on XEN
536
537config XEN
Julien Grallc2ba1f72014-09-17 14:07:06 -0700538 bool "Xen guest support on ARM64"
Stefano Stabelliniaa42aa12013-06-03 17:05:43 +0000539 depends on ARM64 && OF
Stefano Stabellini83862cc2013-10-10 13:40:44 +0000540 select SWIOTLB_XEN
Stefano Stabelliniaa42aa12013-06-03 17:05:43 +0000541 help
542 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM64.
543
Steve Capperd03bb142013-04-25 15:19:21 +0100544config FORCE_MAX_ZONEORDER
545 int
546 default "14" if (ARM64_64K_PAGES && TRANSPARENT_HUGEPAGE)
547 default "11"
548
Will Deacon1b907f42014-11-20 16:51:10 +0000549menuconfig ARMV8_DEPRECATED
550 bool "Emulate deprecated/obsolete ARMv8 instructions"
551 depends on COMPAT
552 help
553 Legacy software support may require certain instructions
554 that have been deprecated or obsoleted in the architecture.
555
556 Enable this config to enable selective emulation of these
557 features.
558
559 If unsure, say Y
560
561if ARMV8_DEPRECATED
562
563config SWP_EMULATION
564 bool "Emulate SWP/SWPB instructions"
565 help
566 ARMv8 obsoletes the use of A32 SWP/SWPB instructions such that
567 they are always undefined. Say Y here to enable software
568 emulation of these instructions for userspace using LDXR/STXR.
569
570 In some older versions of glibc [<=2.8] SWP is used during futex
571 trylock() operations with the assumption that the code will not
572 be preempted. This invalid assumption may be more likely to fail
573 with SWP emulation enabled, leading to deadlock of the user
574 application.
575
576 NOTE: when accessing uncached shared regions, LDXR/STXR rely
577 on an external transaction monitoring block called a global
578 monitor to maintain update atomicity. If your system does not
579 implement a global monitor, this option can cause programs that
580 perform SWP operations to uncached memory to deadlock.
581
582 If unsure, say Y
583
584config CP15_BARRIER_EMULATION
585 bool "Emulate CP15 Barrier instructions"
586 help
587 The CP15 barrier instructions - CP15ISB, CP15DSB, and
588 CP15DMB - are deprecated in ARMv8 (and ARMv7). It is
589 strongly recommended to use the ISB, DSB, and DMB
590 instructions instead.
591
592 Say Y here to enable software emulation of these
593 instructions for AArch32 userspace code. When this option is
594 enabled, CP15 barrier usage is traced which can help
595 identify software that needs updating.
596
597 If unsure, say Y
598
599endif
600
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100601endmenu
602
603menu "Boot options"
604
605config CMDLINE
606 string "Default kernel command string"
607 default ""
608 help
609 Provide a set of default command-line options at build time by
610 entering them here. As a minimum, you should specify the the
611 root device (e.g. root=/dev/nfs).
612
613config CMDLINE_FORCE
614 bool "Always use the default kernel command string"
615 help
616 Always use the default kernel command string, even if the boot
617 loader passes other arguments to the kernel.
618 This is useful if you cannot or don't want to change the
619 command-line options your boot loader passes to the kernel.
620
Ard Biesheuvelf4f75ad52014-07-02 14:54:43 +0200621config EFI_STUB
622 bool
623
Mark Salterf84d0272014-04-15 21:59:30 -0400624config EFI
625 bool "UEFI runtime support"
626 depends on OF && !CPU_BIG_ENDIAN
627 select LIBFDT
628 select UCS2_STRING
629 select EFI_PARAMS_FROM_FDT
Ard Biesheuvele15dd492014-07-04 19:41:53 +0200630 select EFI_RUNTIME_WRAPPERS
Ard Biesheuvelf4f75ad52014-07-02 14:54:43 +0200631 select EFI_STUB
632 select EFI_ARMSTUB
Mark Salterf84d0272014-04-15 21:59:30 -0400633 default y
634 help
635 This option provides support for runtime services provided
636 by UEFI firmware (such as non-volatile variables, realtime
Mark Salter3c7f2552014-04-15 22:47:52 -0400637 clock, and platform reset). A UEFI stub is also provided to
638 allow the kernel to be booted as an EFI application. This
639 is only useful on systems that have UEFI firmware.
Mark Salterf84d0272014-04-15 21:59:30 -0400640
Yi Lid1ae8c02014-10-04 23:46:43 +0800641config DMI
642 bool "Enable support for SMBIOS (DMI) tables"
643 depends on EFI
644 default y
645 help
646 This enables SMBIOS/DMI feature for systems.
647
648 This option is only useful on systems that have UEFI firmware.
649 However, even with this option, the resultant kernel should
650 continue to boot on existing non-UEFI platforms.
651
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100652endmenu
653
654menu "Userspace binary formats"
655
656source "fs/Kconfig.binfmt"
657
658config COMPAT
659 bool "Kernel support for 32-bit EL0"
660 depends on !ARM64_64K_PAGES
661 select COMPAT_BINFMT_ELF
Catalin Marinasaf1839e2012-10-08 16:28:08 -0700662 select HAVE_UID16
Al Viro84b9e9b2012-12-25 16:29:11 -0500663 select OLD_SIGSUSPEND3
Al Viro51682032012-12-25 19:31:29 -0500664 select COMPAT_OLD_SIGACTION
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100665 help
666 This option enables support for a 32-bit EL0 running under a 64-bit
667 kernel at EL1. AArch32-specific components such as system calls,
668 the user helper functions, VFP support and the ptrace interface are
669 handled appropriately by the kernel.
670
671 If you want to execute 32-bit userspace applications, say Y.
672
673config SYSVIPC_COMPAT
674 def_bool y
675 depends on COMPAT && SYSVIPC
676
677endmenu
678
Lorenzo Pieralisi166936b2013-11-07 18:37:14 +0000679menu "Power management options"
680
681source "kernel/power/Kconfig"
682
683config ARCH_SUSPEND_POSSIBLE
684 def_bool y
685
686config ARM64_CPU_SUSPEND
687 def_bool PM_SLEEP
688
689endmenu
690
Lorenzo Pieralisi13072202013-07-17 14:54:21 +0100691menu "CPU Power Management"
692
693source "drivers/cpuidle/Kconfig"
694
Rob Herring52e7e812014-02-24 11:27:57 +0900695source "drivers/cpufreq/Kconfig"
696
697endmenu
698
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100699source "net/Kconfig"
700
701source "drivers/Kconfig"
702
Mark Salterf84d0272014-04-15 21:59:30 -0400703source "drivers/firmware/Kconfig"
704
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100705source "fs/Kconfig"
706
Marc Zyngierc3eb5b12013-07-04 13:34:32 +0100707source "arch/arm64/kvm/Kconfig"
708
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100709source "arch/arm64/Kconfig.debug"
710
711source "security/Kconfig"
712
713source "crypto/Kconfig"
Ard Biesheuvel2c988332014-03-06 16:23:33 +0800714if CRYPTO
715source "arch/arm64/crypto/Kconfig"
716endif
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100717
718source "lib/Kconfig"