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gerrit-public.fairphone.software / kernel / msm-4.9 / 5f52ee48751e63ed555b56a82db446745f60bc82 / . / sound / soc / codecs / wm8962.c
blob: cc4049e9174b6f8a51c2a3647b85297c32976fac [file] [log] [blame]
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]1/*
2 * wm8962.c -- WM8962 ALSA SoC Audio driver
3 *
4 * Copyright 2010 Wolfson Microelectronics plc
5 *
6 * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
7 *
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 */
13
14#include <linux/module.h>
15#include <linux/moduleparam.h>
16#include <linux/init.h>
17#include <linux/delay.h>
18#include <linux/pm.h>
19#include <linux/gcd.h>
Mark Brown3367b8d2010-09-20 17:34:58 +0100[diff] [blame]20#include <linux/gpio.h>
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]21#include <linux/i2c.h>
22#include <linux/input.h>
Mark Brown7b16f562011-11-01 19:32:25 +0000[diff] [blame]23#include <linux/regmap.h>
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]24#include <linux/regulator/consumer.h>
25#include <linux/slab.h>
26#include <linux/workqueue.h>
27#include <sound/core.h>
Mark Brown77113082010-09-30 15:37:53 -0700[diff] [blame]28#include <sound/jack.h>
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]29#include <sound/pcm.h>
30#include <sound/pcm_params.h>
31#include <sound/soc.h>
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]32#include <sound/initval.h>
33#include <sound/tlv.h>
34#include <sound/wm8962.h>
Mark Brown2bbb5d62010-12-05 12:50:12 +0000[diff] [blame]35#include <trace/events/asoc.h>
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]36
37#include "wm8962.h"
38
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]39#define WM8962_NUM_SUPPLIES 8
40static const char *wm8962_supply_names[WM8962_NUM_SUPPLIES] = {
41 "DCVDD",
42 "DBVDD",
43 "AVDD",
44 "CPVDD",
45 "MICVDD",
46 "PLLVDD",
47 "SPKVDD1",
48 "SPKVDD2",
49};
50
51/* codec private data */
52struct wm8962_priv {
Mark Brown7b16f562011-11-01 19:32:25 +0000[diff] [blame]53 struct regmap *regmap;
Mark Brown54d8d0a2010-08-12 15:02:11 +0100[diff] [blame]54 struct snd_soc_codec *codec;
55
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]56 int sysclk;
57 int sysclk_rate;
58
59 int bclk; /* Desired BCLK */
60 int lrclk;
61
Mark Brown3b8a6d82011-04-25 17:53:43 +0100[diff] [blame]62 struct completion fll_lock;
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]63 int fll_src;
64 int fll_fref;
65 int fll_fout;
66
Mark Brown6f88a4e2011-08-17 10:03:51 +0900[diff] [blame]67 u16 dsp2_ena;
68
Mark Brown77113082010-09-30 15:37:53 -0700[diff] [blame]69 struct delayed_work mic_work;
70 struct snd_soc_jack *jack;
71
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]72 struct regulator_bulk_data supplies[WM8962_NUM_SUPPLIES];
73 struct notifier_block disable_nb[WM8962_NUM_SUPPLIES];
74
75#if defined(CONFIG_INPUT) || defined(CONFIG_INPUT_MODULE)
76 struct input_dev *beep;
77 struct work_struct beep_work;
78 int beep_rate;
79#endif
Mark Brown3367b8d2010-09-20 17:34:58 +0100[diff] [blame]80
81#ifdef CONFIG_GPIOLIB
82 struct gpio_chip gpio_chip;
83#endif
Mark Brownc7356da2011-06-07 23:13:53 +0100[diff] [blame]84
85 int irq;
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]86};
87
88/* We can't use the same notifier block for more than one supply and
89 * there's no way I can see to get from a callback to the caller
90 * except container_of().
91 */
92#define WM8962_REGULATOR_EVENT(n) \
93static int wm8962_regulator_event_##n(struct notifier_block *nb, \
94 unsigned long event, void *data) \
95{ \
96 struct wm8962_priv *wm8962 = container_of(nb, struct wm8962_priv, \
97 disable_nb[n]); \
98 if (event & REGULATOR_EVENT_DISABLE) { \
Mark Brown7b16f562011-11-01 19:32:25 +0000[diff] [blame]99 regcache_cache_only(wm8962->regmap, true); \
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]100 } \
101 return 0; \
102}
103
104WM8962_REGULATOR_EVENT(0)
105WM8962_REGULATOR_EVENT(1)
106WM8962_REGULATOR_EVENT(2)
107WM8962_REGULATOR_EVENT(3)
108WM8962_REGULATOR_EVENT(4)
109WM8962_REGULATOR_EVENT(5)
110WM8962_REGULATOR_EVENT(6)
111WM8962_REGULATOR_EVENT(7)
112
Mark Brown7b16f562011-11-01 19:32:25 +0000[diff] [blame]113static struct reg_default wm8962_reg[] = {
114 { 0, 0x009F }, /* R0 - Left Input volume */
115 { 1, 0x049F }, /* R1 - Right Input volume */
116 { 2, 0x0000 }, /* R2 - HPOUTL volume */
117 { 3, 0x0000 }, /* R3 - HPOUTR volume */
118 { 4, 0x0020 }, /* R4 - Clocking1 */
119 { 5, 0x0018 }, /* R5 - ADC & DAC Control 1 */
120 { 6, 0x2008 }, /* R6 - ADC & DAC Control 2 */
121 { 7, 0x000A }, /* R7 - Audio Interface 0 */
122 { 8, 0x01E4 }, /* R8 - Clocking2 */
123 { 9, 0x0300 }, /* R9 - Audio Interface 1 */
124 { 10, 0x00C0 }, /* R10 - Left DAC volume */
125 { 11, 0x00C0 }, /* R11 - Right DAC volume */
Mark Brownf57f6c042010-10-07 17:41:04 -0700[diff] [blame]126
Mark Brown7b16f562011-11-01 19:32:25 +0000[diff] [blame]127 { 14, 0x0040 }, /* R14 - Audio Interface 2 */
128 { 15, 0x6243 }, /* R15 - Software Reset */
Mark Brownf57f6c042010-10-07 17:41:04 -0700[diff] [blame]129
Mark Brown7b16f562011-11-01 19:32:25 +0000[diff] [blame]130 { 17, 0x007B }, /* R17 - ALC1 */
131 { 18, 0x0000 }, /* R18 - ALC2 */
132 { 19, 0x1C32 }, /* R19 - ALC3 */
133 { 20, 0x3200 }, /* R20 - Noise Gate */
134 { 21, 0x00C0 }, /* R21 - Left ADC volume */
135 { 22, 0x00C0 }, /* R22 - Right ADC volume */
136 { 23, 0x0160 }, /* R23 - Additional control(1) */
137 { 24, 0x0000 }, /* R24 - Additional control(2) */
138 { 25, 0x0000 }, /* R25 - Pwr Mgmt (1) */
139 { 26, 0x0000 }, /* R26 - Pwr Mgmt (2) */
140 { 27, 0x0010 }, /* R27 - Additional Control (3) */
141 { 28, 0x0000 }, /* R28 - Anti-pop */
Mark Brownf57f6c042010-10-07 17:41:04 -0700[diff] [blame]142
Mark Brown7b16f562011-11-01 19:32:25 +0000[diff] [blame]143 { 30, 0x005E }, /* R30 - Clocking 3 */
144 { 31, 0x0000 }, /* R31 - Input mixer control (1) */
145 { 32, 0x0145 }, /* R32 - Left input mixer volume */
146 { 33, 0x0145 }, /* R33 - Right input mixer volume */
147 { 34, 0x0009 }, /* R34 - Input mixer control (2) */
148 { 35, 0x0003 }, /* R35 - Input bias control */
149 { 37, 0x0008 }, /* R37 - Left input PGA control */
150 { 38, 0x0008 }, /* R38 - Right input PGA control */
Mark Brownf57f6c042010-10-07 17:41:04 -0700[diff] [blame]151
Mark Brown7b16f562011-11-01 19:32:25 +0000[diff] [blame]152 { 40, 0x0000 }, /* R40 - SPKOUTL volume */
153 { 41, 0x0000 }, /* R41 - SPKOUTR volume */
Mark Brownf57f6c042010-10-07 17:41:04 -0700[diff] [blame]154
Mark Brown7b16f562011-11-01 19:32:25 +0000[diff] [blame]155 { 47, 0x0000 }, /* R47 - Thermal Shutdown Status */
156 { 48, 0x8027 }, /* R48 - Additional Control (4) */
157 { 49, 0x0010 }, /* R49 - Class D Control 1 */
Mark Brownf57f6c042010-10-07 17:41:04 -0700[diff] [blame]158
Mark Brown7b16f562011-11-01 19:32:25 +0000[diff] [blame]159 { 51, 0x0003 }, /* R51 - Class D Control 2 */
Mark Brownf57f6c042010-10-07 17:41:04 -0700[diff] [blame]160
Mark Brown7b16f562011-11-01 19:32:25 +0000[diff] [blame]161 { 56, 0x0506 }, /* R56 - Clocking 4 */
162 { 57, 0x0000 }, /* R57 - DAC DSP Mixing (1) */
163 { 58, 0x0000 }, /* R58 - DAC DSP Mixing (2) */
Mark Brownf57f6c042010-10-07 17:41:04 -0700[diff] [blame]164
Mark Brown7b16f562011-11-01 19:32:25 +0000[diff] [blame]165 { 60, 0x0300 }, /* R60 - DC Servo 0 */
166 { 61, 0x0300 }, /* R61 - DC Servo 1 */
Mark Brownf57f6c042010-10-07 17:41:04 -0700[diff] [blame]167
Mark Brown7b16f562011-11-01 19:32:25 +0000[diff] [blame]168 { 64, 0x0810 }, /* R64 - DC Servo 4 */
Mark Brownf57f6c042010-10-07 17:41:04 -0700[diff] [blame]169
Mark Brown7b16f562011-11-01 19:32:25 +0000[diff] [blame]170 { 66, 0x0000 }, /* R66 - DC Servo 6 */
Mark Brownf57f6c042010-10-07 17:41:04 -0700[diff] [blame]171
Mark Brown7b16f562011-11-01 19:32:25 +0000[diff] [blame]172 { 68, 0x001B }, /* R68 - Analogue PGA Bias */
173 { 69, 0x0000 }, /* R69 - Analogue HP 0 */
Mark Brownf57f6c042010-10-07 17:41:04 -0700[diff] [blame]174
Mark Brown7b16f562011-11-01 19:32:25 +0000[diff] [blame]175 { 71, 0x01FB }, /* R71 - Analogue HP 2 */
176 { 72, 0x0000 }, /* R72 - Charge Pump 1 */
Mark Brownf57f6c042010-10-07 17:41:04 -0700[diff] [blame]177
Mark Brown7b16f562011-11-01 19:32:25 +0000[diff] [blame]178 { 82, 0x0004 }, /* R82 - Charge Pump B */
Mark Brownf57f6c042010-10-07 17:41:04 -0700[diff] [blame]179
Mark Brown7b16f562011-11-01 19:32:25 +0000[diff] [blame]180 { 87, 0x0000 }, /* R87 - Write Sequencer Control 1 */
Mark Brownf57f6c042010-10-07 17:41:04 -0700[diff] [blame]181
Mark Brown7b16f562011-11-01 19:32:25 +0000[diff] [blame]182 { 90, 0x0000 }, /* R90 - Write Sequencer Control 2 */
Mark Brownf57f6c042010-10-07 17:41:04 -0700[diff] [blame]183
Mark Brown7b16f562011-11-01 19:32:25 +0000[diff] [blame]184 { 93, 0x0000 }, /* R93 - Write Sequencer Control 3 */
185 { 94, 0x0000 }, /* R94 - Control Interface */
Mark Brownf57f6c042010-10-07 17:41:04 -0700[diff] [blame]186
Mark Brown7b16f562011-11-01 19:32:25 +0000[diff] [blame]187 { 99, 0x0000 }, /* R99 - Mixer Enables */
188 { 100, 0x0000 }, /* R100 - Headphone Mixer (1) */
189 { 101, 0x0000 }, /* R101 - Headphone Mixer (2) */
190 { 102, 0x013F }, /* R102 - Headphone Mixer (3) */
191 { 103, 0x013F }, /* R103 - Headphone Mixer (4) */
Mark Brownf57f6c042010-10-07 17:41:04 -0700[diff] [blame]192
Mark Brown7b16f562011-11-01 19:32:25 +0000[diff] [blame]193 { 105, 0x0000 }, /* R105 - Speaker Mixer (1) */
194 { 106, 0x0000 }, /* R106 - Speaker Mixer (2) */
195 { 107, 0x013F }, /* R107 - Speaker Mixer (3) */
196 { 108, 0x013F }, /* R108 - Speaker Mixer (4) */
197 { 109, 0x0003 }, /* R109 - Speaker Mixer (5) */
198 { 110, 0x0002 }, /* R110 - Beep Generator (1) */
Mark Brownf57f6c042010-10-07 17:41:04 -0700[diff] [blame]199
Mark Brown7b16f562011-11-01 19:32:25 +0000[diff] [blame]200 { 115, 0x0006 }, /* R115 - Oscillator Trim (3) */
201 { 116, 0x0026 }, /* R116 - Oscillator Trim (4) */
Mark Brownf57f6c042010-10-07 17:41:04 -0700[diff] [blame]202
Mark Brown7b16f562011-11-01 19:32:25 +0000[diff] [blame]203 { 119, 0x0000 }, /* R119 - Oscillator Trim (7) */
Mark Brownf57f6c042010-10-07 17:41:04 -0700[diff] [blame]204
Mark Brown7b16f562011-11-01 19:32:25 +0000[diff] [blame]205 { 124, 0x0011 }, /* R124 - Analogue Clocking1 */
206 { 125, 0x004B }, /* R125 - Analogue Clocking2 */
207 { 126, 0x000D }, /* R126 - Analogue Clocking3 */
208 { 127, 0x0000 }, /* R127 - PLL Software Reset */
Mark Brownf57f6c042010-10-07 17:41:04 -0700[diff] [blame]209
Mark Brown7b16f562011-11-01 19:32:25 +0000[diff] [blame]210 { 129, 0x0000 }, /* R129 - PLL2 */
Mark Brownf57f6c042010-10-07 17:41:04 -0700[diff] [blame]211
Mark Brown7b16f562011-11-01 19:32:25 +0000[diff] [blame]212 { 131, 0x0000 }, /* R131 - PLL 4 */
Mark Brownf57f6c042010-10-07 17:41:04 -0700[diff] [blame]213
Mark Brown7b16f562011-11-01 19:32:25 +0000[diff] [blame]214 { 136, 0x0067 }, /* R136 - PLL 9 */
215 { 137, 0x001C }, /* R137 - PLL 10 */
216 { 138, 0x0071 }, /* R138 - PLL 11 */
217 { 139, 0x00C7 }, /* R139 - PLL 12 */
218 { 140, 0x0067 }, /* R140 - PLL 13 */
219 { 141, 0x0048 }, /* R141 - PLL 14 */
220 { 142, 0x0022 }, /* R142 - PLL 15 */
221 { 143, 0x0097 }, /* R143 - PLL 16 */
Mark Brownf57f6c042010-10-07 17:41:04 -0700[diff] [blame]222
Mark Brown7b16f562011-11-01 19:32:25 +0000[diff] [blame]223 { 155, 0x000C }, /* R155 - FLL Control (1) */
224 { 156, 0x0039 }, /* R156 - FLL Control (2) */
225 { 157, 0x0180 }, /* R157 - FLL Control (3) */
Mark Brownf57f6c042010-10-07 17:41:04 -0700[diff] [blame]226
Mark Brown7b16f562011-11-01 19:32:25 +0000[diff] [blame]227 { 159, 0x0032 }, /* R159 - FLL Control (5) */
228 { 160, 0x0018 }, /* R160 - FLL Control (6) */
229 { 161, 0x007D }, /* R161 - FLL Control (7) */
230 { 162, 0x0008 }, /* R162 - FLL Control (8) */
Mark Brownf57f6c042010-10-07 17:41:04 -0700[diff] [blame]231
Mark Brown7b16f562011-11-01 19:32:25 +0000[diff] [blame]232 { 252, 0x0005 }, /* R252 - General test 1 */
Mark Brownf57f6c042010-10-07 17:41:04 -0700[diff] [blame]233
Mark Brown7b16f562011-11-01 19:32:25 +0000[diff] [blame]234 { 256, 0x0000 }, /* R256 - DF1 */
235 { 257, 0x0000 }, /* R257 - DF2 */
236 { 258, 0x0000 }, /* R258 - DF3 */
237 { 259, 0x0000 }, /* R259 - DF4 */
238 { 260, 0x0000 }, /* R260 - DF5 */
239 { 261, 0x0000 }, /* R261 - DF6 */
240 { 262, 0x0000 }, /* R262 - DF7 */
Mark Brownf57f6c042010-10-07 17:41:04 -0700[diff] [blame]241
Mark Brown7b16f562011-11-01 19:32:25 +0000[diff] [blame]242 { 264, 0x0000 }, /* R264 - LHPF1 */
243 { 265, 0x0000 }, /* R265 - LHPF2 */
Mark Brownf57f6c042010-10-07 17:41:04 -0700[diff] [blame]244
Mark Brown7b16f562011-11-01 19:32:25 +0000[diff] [blame]245 { 268, 0x0000 }, /* R268 - THREED1 */
246 { 269, 0x0000 }, /* R269 - THREED2 */
247 { 270, 0x0000 }, /* R270 - THREED3 */
248 { 271, 0x0000 }, /* R271 - THREED4 */
Mark Brownf57f6c042010-10-07 17:41:04 -0700[diff] [blame]249
Mark Brown7b16f562011-11-01 19:32:25 +0000[diff] [blame]250 { 276, 0x000C }, /* R276 - DRC 1 */
251 { 277, 0x0925 }, /* R277 - DRC 2 */
252 { 278, 0x0000 }, /* R278 - DRC 3 */
253 { 279, 0x0000 }, /* R279 - DRC 4 */
254 { 280, 0x0000 }, /* R280 - DRC 5 */
Mark Brownf57f6c042010-10-07 17:41:04 -0700[diff] [blame]255
Mark Brown7b16f562011-11-01 19:32:25 +0000[diff] [blame]256 { 285, 0x0000 }, /* R285 - Tloopback */
Mark Brownf57f6c042010-10-07 17:41:04 -0700[diff] [blame]257
Mark Brown7b16f562011-11-01 19:32:25 +0000[diff] [blame]258 { 335, 0x0004 }, /* R335 - EQ1 */
259 { 336, 0x6318 }, /* R336 - EQ2 */
260 { 337, 0x6300 }, /* R337 - EQ3 */
261 { 338, 0x0FCA }, /* R338 - EQ4 */
262 { 339, 0x0400 }, /* R339 - EQ5 */
263 { 340, 0x00D8 }, /* R340 - EQ6 */
264 { 341, 0x1EB5 }, /* R341 - EQ7 */
265 { 342, 0xF145 }, /* R342 - EQ8 */
266 { 343, 0x0B75 }, /* R343 - EQ9 */
267 { 344, 0x01C5 }, /* R344 - EQ10 */
268 { 345, 0x1C58 }, /* R345 - EQ11 */
269 { 346, 0xF373 }, /* R346 - EQ12 */
270 { 347, 0x0A54 }, /* R347 - EQ13 */
271 { 348, 0x0558 }, /* R348 - EQ14 */
272 { 349, 0x168E }, /* R349 - EQ15 */
273 { 350, 0xF829 }, /* R350 - EQ16 */
274 { 351, 0x07AD }, /* R351 - EQ17 */
275 { 352, 0x1103 }, /* R352 - EQ18 */
276 { 353, 0x0564 }, /* R353 - EQ19 */
277 { 354, 0x0559 }, /* R354 - EQ20 */
278 { 355, 0x4000 }, /* R355 - EQ21 */
279 { 356, 0x6318 }, /* R356 - EQ22 */
280 { 357, 0x6300 }, /* R357 - EQ23 */
281 { 358, 0x0FCA }, /* R358 - EQ24 */
282 { 359, 0x0400 }, /* R359 - EQ25 */
283 { 360, 0x00D8 }, /* R360 - EQ26 */
284 { 361, 0x1EB5 }, /* R361 - EQ27 */
285 { 362, 0xF145 }, /* R362 - EQ28 */
286 { 363, 0x0B75 }, /* R363 - EQ29 */
287 { 364, 0x01C5 }, /* R364 - EQ30 */
288 { 365, 0x1C58 }, /* R365 - EQ31 */
289 { 366, 0xF373 }, /* R366 - EQ32 */
290 { 367, 0x0A54 }, /* R367 - EQ33 */
291 { 368, 0x0558 }, /* R368 - EQ34 */
292 { 369, 0x168E }, /* R369 - EQ35 */
293 { 370, 0xF829 }, /* R370 - EQ36 */
294 { 371, 0x07AD }, /* R371 - EQ37 */
295 { 372, 0x1103 }, /* R372 - EQ38 */
296 { 373, 0x0564 }, /* R373 - EQ39 */
297 { 374, 0x0559 }, /* R374 - EQ40 */
298 { 375, 0x4000 }, /* R375 - EQ41 */
Mark Brownf57f6c042010-10-07 17:41:04 -0700[diff] [blame]299
Mark Brown7b16f562011-11-01 19:32:25 +0000[diff] [blame]300 { 513, 0x0000 }, /* R513 - GPIO 2 */
301 { 514, 0x0000 }, /* R514 - GPIO 3 */
Mark Brownf57f6c042010-10-07 17:41:04 -0700[diff] [blame]302
Mark Brown7b16f562011-11-01 19:32:25 +0000[diff] [blame]303 { 516, 0x8100 }, /* R516 - GPIO 5 */
304 { 517, 0x8100 }, /* R517 - GPIO 6 */
Mark Brownf57f6c042010-10-07 17:41:04 -0700[diff] [blame]305
Mark Brown7b16f562011-11-01 19:32:25 +0000[diff] [blame]306 { 560, 0x0000 }, /* R560 - Interrupt Status 1 */
307 { 561, 0x0000 }, /* R561 - Interrupt Status 2 */
Mark Brownf57f6c042010-10-07 17:41:04 -0700[diff] [blame]308
Mark Brown7b16f562011-11-01 19:32:25 +0000[diff] [blame]309 { 568, 0x0030 }, /* R568 - Interrupt Status 1 Mask */
310 { 569, 0xFFED }, /* R569 - Interrupt Status 2 Mask */
Mark Brownf57f6c042010-10-07 17:41:04 -0700[diff] [blame]311
Mark Brown7b16f562011-11-01 19:32:25 +0000[diff] [blame]312 { 576, 0x0000 }, /* R576 - Interrupt Control */
Mark Brownf57f6c042010-10-07 17:41:04 -0700[diff] [blame]313
Mark Brown7b16f562011-11-01 19:32:25 +0000[diff] [blame]314 { 584, 0x002D }, /* R584 - IRQ Debounce */
Mark Brownf57f6c042010-10-07 17:41:04 -0700[diff] [blame]315
Mark Brown7b16f562011-11-01 19:32:25 +0000[diff] [blame]316 { 586, 0x0000 }, /* R586 - MICINT Source Pol */
Mark Brownf57f6c042010-10-07 17:41:04 -0700[diff] [blame]317
Mark Brown7b16f562011-11-01 19:32:25 +0000[diff] [blame]318 { 768, 0x1C00 }, /* R768 - DSP2 Power Management */
Mark Brownf57f6c042010-10-07 17:41:04 -0700[diff] [blame]319
Mark Brown7b16f562011-11-01 19:32:25 +0000[diff] [blame]320 { 1037, 0x0000 }, /* R1037 - DSP2_ExecControl */
Mark Brownf57f6c042010-10-07 17:41:04 -0700[diff] [blame]321
Mark Brown7b16f562011-11-01 19:32:25 +0000[diff] [blame]322 { 8192, 0x0000 }, /* R8192 - DSP2 Instruction RAM 0 */
Mark Brownf57f6c042010-10-07 17:41:04 -0700[diff] [blame]323
Mark Brown7b16f562011-11-01 19:32:25 +0000[diff] [blame]324 { 9216, 0x0030 }, /* R9216 - DSP2 Address RAM 2 */
325 { 9217, 0x0000 }, /* R9217 - DSP2 Address RAM 1 */
326 { 9218, 0x0000 }, /* R9218 - DSP2 Address RAM 0 */
Mark Brownf57f6c042010-10-07 17:41:04 -0700[diff] [blame]327
Mark Brown7b16f562011-11-01 19:32:25 +0000[diff] [blame]328 { 12288, 0x0000 }, /* R12288 - DSP2 Data1 RAM 1 */
329 { 12289, 0x0000 }, /* R12289 - DSP2 Data1 RAM 0 */
Mark Brownf57f6c042010-10-07 17:41:04 -0700[diff] [blame]330
Mark Brown7b16f562011-11-01 19:32:25 +0000[diff] [blame]331 { 13312, 0x0000 }, /* R13312 - DSP2 Data2 RAM 1 */
332 { 13313, 0x0000 }, /* R13313 - DSP2 Data2 RAM 0 */
Mark Brownf57f6c042010-10-07 17:41:04 -0700[diff] [blame]333
Mark Brown7b16f562011-11-01 19:32:25 +0000[diff] [blame]334 { 14336, 0x0000 }, /* R14336 - DSP2 Data3 RAM 1 */
335 { 14337, 0x0000 }, /* R14337 - DSP2 Data3 RAM 0 */
Mark Brownf57f6c042010-10-07 17:41:04 -0700[diff] [blame]336
Mark Brown7b16f562011-11-01 19:32:25 +0000[diff] [blame]337 { 15360, 0x000A }, /* R15360 - DSP2 Coeff RAM 0 */
Mark Brownf57f6c042010-10-07 17:41:04 -0700[diff] [blame]338
Mark Brown7b16f562011-11-01 19:32:25 +0000[diff] [blame]339 { 16384, 0x0000 }, /* R16384 - RETUNEADC_SHARED_COEFF_1 */
340 { 16385, 0x0000 }, /* R16385 - RETUNEADC_SHARED_COEFF_0 */
341 { 16386, 0x0000 }, /* R16386 - RETUNEDAC_SHARED_COEFF_1 */
342 { 16387, 0x0000 }, /* R16387 - RETUNEDAC_SHARED_COEFF_0 */
343 { 16388, 0x0000 }, /* R16388 - SOUNDSTAGE_ENABLES_1 */
344 { 16389, 0x0000 }, /* R16389 - SOUNDSTAGE_ENABLES_0 */
Mark Brownf57f6c042010-10-07 17:41:04 -0700[diff] [blame]345
Mark Brown7b16f562011-11-01 19:32:25 +0000[diff] [blame]346 { 16896, 0x0002 }, /* R16896 - HDBASS_AI_1 */
347 { 16897, 0xBD12 }, /* R16897 - HDBASS_AI_0 */
348 { 16898, 0x007C }, /* R16898 - HDBASS_AR_1 */
349 { 16899, 0x586C }, /* R16899 - HDBASS_AR_0 */
350 { 16900, 0x0053 }, /* R16900 - HDBASS_B_1 */
351 { 16901, 0x8121 }, /* R16901 - HDBASS_B_0 */
352 { 16902, 0x003F }, /* R16902 - HDBASS_K_1 */
353 { 16903, 0x8BD8 }, /* R16903 - HDBASS_K_0 */
354 { 16904, 0x0032 }, /* R16904 - HDBASS_N1_1 */
355 { 16905, 0xF52D }, /* R16905 - HDBASS_N1_0 */
356 { 16906, 0x0065 }, /* R16906 - HDBASS_N2_1 */
357 { 16907, 0xAC8C }, /* R16907 - HDBASS_N2_0 */
358 { 16908, 0x006B }, /* R16908 - HDBASS_N3_1 */
359 { 16909, 0xE087 }, /* R16909 - HDBASS_N3_0 */
360 { 16910, 0x0072 }, /* R16910 - HDBASS_N4_1 */
361 { 16911, 0x1483 }, /* R16911 - HDBASS_N4_0 */
362 { 16912, 0x0072 }, /* R16912 - HDBASS_N5_1 */
363 { 16913, 0x1483 }, /* R16913 - HDBASS_N5_0 */
364 { 16914, 0x0043 }, /* R16914 - HDBASS_X1_1 */
365 { 16915, 0x3525 }, /* R16915 - HDBASS_X1_0 */
366 { 16916, 0x0006 }, /* R16916 - HDBASS_X2_1 */
367 { 16917, 0x6A4A }, /* R16917 - HDBASS_X2_0 */
368 { 16918, 0x0043 }, /* R16918 - HDBASS_X3_1 */
369 { 16919, 0x6079 }, /* R16919 - HDBASS_X3_0 */
370 { 16920, 0x0008 }, /* R16920 - HDBASS_ATK_1 */
371 { 16921, 0x0000 }, /* R16921 - HDBASS_ATK_0 */
372 { 16922, 0x0001 }, /* R16922 - HDBASS_DCY_1 */
373 { 16923, 0x0000 }, /* R16923 - HDBASS_DCY_0 */
374 { 16924, 0x0059 }, /* R16924 - HDBASS_PG_1 */
375 { 16925, 0x999A }, /* R16925 - HDBASS_PG_0 */
Mark Brownf57f6c042010-10-07 17:41:04 -0700[diff] [blame]376
Mark Brown7b16f562011-11-01 19:32:25 +0000[diff] [blame]377 { 17048, 0x0083 }, /* R17408 - HPF_C_1 */
378 { 17049, 0x98AD }, /* R17409 - HPF_C_0 */
Mark Brownf57f6c042010-10-07 17:41:04 -0700[diff] [blame]379
Mark Brown7b16f562011-11-01 19:32:25 +0000[diff] [blame]380 { 17920, 0x007F }, /* R17920 - ADCL_RETUNE_C1_1 */
381 { 17921, 0xFFFF }, /* R17921 - ADCL_RETUNE_C1_0 */
382 { 17922, 0x0000 }, /* R17922 - ADCL_RETUNE_C2_1 */
383 { 17923, 0x0000 }, /* R17923 - ADCL_RETUNE_C2_0 */
384 { 17924, 0x0000 }, /* R17924 - ADCL_RETUNE_C3_1 */
385 { 17925, 0x0000 }, /* R17925 - ADCL_RETUNE_C3_0 */
386 { 17926, 0x0000 }, /* R17926 - ADCL_RETUNE_C4_1 */
387 { 17927, 0x0000 }, /* R17927 - ADCL_RETUNE_C4_0 */
388 { 17928, 0x0000 }, /* R17928 - ADCL_RETUNE_C5_1 */
389 { 17929, 0x0000 }, /* R17929 - ADCL_RETUNE_C5_0 */
390 { 17930, 0x0000 }, /* R17930 - ADCL_RETUNE_C6_1 */
391 { 17931, 0x0000 }, /* R17931 - ADCL_RETUNE_C6_0 */
392 { 17932, 0x0000 }, /* R17932 - ADCL_RETUNE_C7_1 */
393 { 17933, 0x0000 }, /* R17933 - ADCL_RETUNE_C7_0 */
394 { 17934, 0x0000 }, /* R17934 - ADCL_RETUNE_C8_1 */
395 { 17935, 0x0000 }, /* R17935 - ADCL_RETUNE_C8_0 */
396 { 17936, 0x0000 }, /* R17936 - ADCL_RETUNE_C9_1 */
397 { 17937, 0x0000 }, /* R17937 - ADCL_RETUNE_C9_0 */
398 { 17938, 0x0000 }, /* R17938 - ADCL_RETUNE_C10_1 */
399 { 17939, 0x0000 }, /* R17939 - ADCL_RETUNE_C10_0 */
400 { 17940, 0x0000 }, /* R17940 - ADCL_RETUNE_C11_1 */
401 { 17941, 0x0000 }, /* R17941 - ADCL_RETUNE_C11_0 */
402 { 17942, 0x0000 }, /* R17942 - ADCL_RETUNE_C12_1 */
403 { 17943, 0x0000 }, /* R17943 - ADCL_RETUNE_C12_0 */
404 { 17944, 0x0000 }, /* R17944 - ADCL_RETUNE_C13_1 */
405 { 17945, 0x0000 }, /* R17945 - ADCL_RETUNE_C13_0 */
406 { 17946, 0x0000 }, /* R17946 - ADCL_RETUNE_C14_1 */
407 { 17947, 0x0000 }, /* R17947 - ADCL_RETUNE_C14_0 */
408 { 17948, 0x0000 }, /* R17948 - ADCL_RETUNE_C15_1 */
409 { 17949, 0x0000 }, /* R17949 - ADCL_RETUNE_C15_0 */
410 { 17950, 0x0000 }, /* R17950 - ADCL_RETUNE_C16_1 */
411 { 17951, 0x0000 }, /* R17951 - ADCL_RETUNE_C16_0 */
412 { 17952, 0x0000 }, /* R17952 - ADCL_RETUNE_C17_1 */
413 { 17953, 0x0000 }, /* R17953 - ADCL_RETUNE_C17_0 */
414 { 17954, 0x0000 }, /* R17954 - ADCL_RETUNE_C18_1 */
415 { 17955, 0x0000 }, /* R17955 - ADCL_RETUNE_C18_0 */
416 { 17956, 0x0000 }, /* R17956 - ADCL_RETUNE_C19_1 */
417 { 17957, 0x0000 }, /* R17957 - ADCL_RETUNE_C19_0 */
418 { 17958, 0x0000 }, /* R17958 - ADCL_RETUNE_C20_1 */
419 { 17959, 0x0000 }, /* R17959 - ADCL_RETUNE_C20_0 */
420 { 17960, 0x0000 }, /* R17960 - ADCL_RETUNE_C21_1 */
421 { 17961, 0x0000 }, /* R17961 - ADCL_RETUNE_C21_0 */
422 { 17962, 0x0000 }, /* R17962 - ADCL_RETUNE_C22_1 */
423 { 17963, 0x0000 }, /* R17963 - ADCL_RETUNE_C22_0 */
424 { 17964, 0x0000 }, /* R17964 - ADCL_RETUNE_C23_1 */
425 { 17965, 0x0000 }, /* R17965 - ADCL_RETUNE_C23_0 */
426 { 17966, 0x0000 }, /* R17966 - ADCL_RETUNE_C24_1 */
427 { 17967, 0x0000 }, /* R17967 - ADCL_RETUNE_C24_0 */
428 { 17968, 0x0000 }, /* R17968 - ADCL_RETUNE_C25_1 */
429 { 17969, 0x0000 }, /* R17969 - ADCL_RETUNE_C25_0 */
430 { 17970, 0x0000 }, /* R17970 - ADCL_RETUNE_C26_1 */
431 { 17971, 0x0000 }, /* R17971 - ADCL_RETUNE_C26_0 */
432 { 17972, 0x0000 }, /* R17972 - ADCL_RETUNE_C27_1 */
433 { 17973, 0x0000 }, /* R17973 - ADCL_RETUNE_C27_0 */
434 { 17974, 0x0000 }, /* R17974 - ADCL_RETUNE_C28_1 */
435 { 17975, 0x0000 }, /* R17975 - ADCL_RETUNE_C28_0 */
436 { 17976, 0x0000 }, /* R17976 - ADCL_RETUNE_C29_1 */
437 { 17977, 0x0000 }, /* R17977 - ADCL_RETUNE_C29_0 */
438 { 17978, 0x0000 }, /* R17978 - ADCL_RETUNE_C30_1 */
439 { 17979, 0x0000 }, /* R17979 - ADCL_RETUNE_C30_0 */
440 { 17980, 0x0000 }, /* R17980 - ADCL_RETUNE_C31_1 */
441 { 17981, 0x0000 }, /* R17981 - ADCL_RETUNE_C31_0 */
442 { 17982, 0x0000 }, /* R17982 - ADCL_RETUNE_C32_1 */
443 { 17983, 0x0000 }, /* R17983 - ADCL_RETUNE_C32_0 */
Mark Brownf57f6c042010-10-07 17:41:04 -0700[diff] [blame]444
Mark Brown7b16f562011-11-01 19:32:25 +0000[diff] [blame]445 { 18432, 0x0020 }, /* R18432 - RETUNEADC_PG2_1 */
446 { 18433, 0x0000 }, /* R18433 - RETUNEADC_PG2_0 */
447 { 18434, 0x0040 }, /* R18434 - RETUNEADC_PG_1 */
448 { 18435, 0x0000 }, /* R18435 - RETUNEADC_PG_0 */
Mark Brownf57f6c042010-10-07 17:41:04 -0700[diff] [blame]449
Mark Brown7b16f562011-11-01 19:32:25 +0000[diff] [blame]450 { 18944, 0x007F }, /* R18944 - ADCR_RETUNE_C1_1 */
451 { 18945, 0xFFFF }, /* R18945 - ADCR_RETUNE_C1_0 */
452 { 18946, 0x0000 }, /* R18946 - ADCR_RETUNE_C2_1 */
453 { 18947, 0x0000 }, /* R18947 - ADCR_RETUNE_C2_0 */
454 { 18948, 0x0000 }, /* R18948 - ADCR_RETUNE_C3_1 */
455 { 18949, 0x0000 }, /* R18949 - ADCR_RETUNE_C3_0 */
456 { 18950, 0x0000 }, /* R18950 - ADCR_RETUNE_C4_1 */
457 { 18951, 0x0000 }, /* R18951 - ADCR_RETUNE_C4_0 */
458 { 18952, 0x0000 }, /* R18952 - ADCR_RETUNE_C5_1 */
459 { 18953, 0x0000 }, /* R18953 - ADCR_RETUNE_C5_0 */
460 { 18954, 0x0000 }, /* R18954 - ADCR_RETUNE_C6_1 */
461 { 18955, 0x0000 }, /* R18955 - ADCR_RETUNE_C6_0 */
462 { 18956, 0x0000 }, /* R18956 - ADCR_RETUNE_C7_1 */
463 { 18957, 0x0000 }, /* R18957 - ADCR_RETUNE_C7_0 */
464 { 18958, 0x0000 }, /* R18958 - ADCR_RETUNE_C8_1 */
465 { 18959, 0x0000 }, /* R18959 - ADCR_RETUNE_C8_0 */
466 { 18960, 0x0000 }, /* R18960 - ADCR_RETUNE_C9_1 */
467 { 18961, 0x0000 }, /* R18961 - ADCR_RETUNE_C9_0 */
468 { 18962, 0x0000 }, /* R18962 - ADCR_RETUNE_C10_1 */
469 { 18963, 0x0000 }, /* R18963 - ADCR_RETUNE_C10_0 */
470 { 18964, 0x0000 }, /* R18964 - ADCR_RETUNE_C11_1 */
471 { 18965, 0x0000 }, /* R18965 - ADCR_RETUNE_C11_0 */
472 { 18966, 0x0000 }, /* R18966 - ADCR_RETUNE_C12_1 */
473 { 18967, 0x0000 }, /* R18967 - ADCR_RETUNE_C12_0 */
474 { 18968, 0x0000 }, /* R18968 - ADCR_RETUNE_C13_1 */
475 { 18969, 0x0000 }, /* R18969 - ADCR_RETUNE_C13_0 */
476 { 18970, 0x0000 }, /* R18970 - ADCR_RETUNE_C14_1 */
477 { 18971, 0x0000 }, /* R18971 - ADCR_RETUNE_C14_0 */
478 { 18972, 0x0000 }, /* R18972 - ADCR_RETUNE_C15_1 */
479 { 18973, 0x0000 }, /* R18973 - ADCR_RETUNE_C15_0 */
480 { 18974, 0x0000 }, /* R18974 - ADCR_RETUNE_C16_1 */
481 { 18975, 0x0000 }, /* R18975 - ADCR_RETUNE_C16_0 */
482 { 18976, 0x0000 }, /* R18976 - ADCR_RETUNE_C17_1 */
483 { 18977, 0x0000 }, /* R18977 - ADCR_RETUNE_C17_0 */
484 { 18978, 0x0000 }, /* R18978 - ADCR_RETUNE_C18_1 */
485 { 18979, 0x0000 }, /* R18979 - ADCR_RETUNE_C18_0 */
486 { 18980, 0x0000 }, /* R18980 - ADCR_RETUNE_C19_1 */
487 { 18981, 0x0000 }, /* R18981 - ADCR_RETUNE_C19_0 */
488 { 18982, 0x0000 }, /* R18982 - ADCR_RETUNE_C20_1 */
489 { 18983, 0x0000 }, /* R18983 - ADCR_RETUNE_C20_0 */
490 { 18984, 0x0000 }, /* R18984 - ADCR_RETUNE_C21_1 */
491 { 18985, 0x0000 }, /* R18985 - ADCR_RETUNE_C21_0 */
492 { 18986, 0x0000 }, /* R18986 - ADCR_RETUNE_C22_1 */
493 { 18987, 0x0000 }, /* R18987 - ADCR_RETUNE_C22_0 */
494 { 18988, 0x0000 }, /* R18988 - ADCR_RETUNE_C23_1 */
495 { 18989, 0x0000 }, /* R18989 - ADCR_RETUNE_C23_0 */
496 { 18990, 0x0000 }, /* R18990 - ADCR_RETUNE_C24_1 */
497 { 18991, 0x0000 }, /* R18991 - ADCR_RETUNE_C24_0 */
498 { 18992, 0x0000 }, /* R18992 - ADCR_RETUNE_C25_1 */
499 { 18993, 0x0000 }, /* R18993 - ADCR_RETUNE_C25_0 */
500 { 18994, 0x0000 }, /* R18994 - ADCR_RETUNE_C26_1 */
501 { 18995, 0x0000 }, /* R18995 - ADCR_RETUNE_C26_0 */
502 { 18996, 0x0000 }, /* R18996 - ADCR_RETUNE_C27_1 */
503 { 18997, 0x0000 }, /* R18997 - ADCR_RETUNE_C27_0 */
504 { 18998, 0x0000 }, /* R18998 - ADCR_RETUNE_C28_1 */
505 { 18999, 0x0000 }, /* R18999 - ADCR_RETUNE_C28_0 */
506 { 19000, 0x0000 }, /* R19000 - ADCR_RETUNE_C29_1 */
507 { 19001, 0x0000 }, /* R19001 - ADCR_RETUNE_C29_0 */
508 { 19002, 0x0000 }, /* R19002 - ADCR_RETUNE_C30_1 */
509 { 19003, 0x0000 }, /* R19003 - ADCR_RETUNE_C30_0 */
510 { 19004, 0x0000 }, /* R19004 - ADCR_RETUNE_C31_1 */
511 { 19005, 0x0000 }, /* R19005 - ADCR_RETUNE_C31_0 */
512 { 19006, 0x0000 }, /* R19006 - ADCR_RETUNE_C32_1 */
513 { 19007, 0x0000 }, /* R19007 - ADCR_RETUNE_C32_0 */
Mark Brownf57f6c042010-10-07 17:41:04 -0700[diff] [blame]514
Mark Brown7b16f562011-11-01 19:32:25 +0000[diff] [blame]515 { 19456, 0x007F }, /* R19456 - DACL_RETUNE_C1_1 */
516 { 19457, 0xFFFF }, /* R19457 - DACL_RETUNE_C1_0 */
517 { 19458, 0x0000 }, /* R19458 - DACL_RETUNE_C2_1 */
518 { 19459, 0x0000 }, /* R19459 - DACL_RETUNE_C2_0 */
519 { 19460, 0x0000 }, /* R19460 - DACL_RETUNE_C3_1 */
520 { 19461, 0x0000 }, /* R19461 - DACL_RETUNE_C3_0 */
521 { 19462, 0x0000 }, /* R19462 - DACL_RETUNE_C4_1 */
522 { 19463, 0x0000 }, /* R19463 - DACL_RETUNE_C4_0 */
523 { 19464, 0x0000 }, /* R19464 - DACL_RETUNE_C5_1 */
524 { 19465, 0x0000 }, /* R19465 - DACL_RETUNE_C5_0 */
525 { 19466, 0x0000 }, /* R19466 - DACL_RETUNE_C6_1 */
526 { 19467, 0x0000 }, /* R19467 - DACL_RETUNE_C6_0 */
527 { 19468, 0x0000 }, /* R19468 - DACL_RETUNE_C7_1 */
528 { 19469, 0x0000 }, /* R19469 - DACL_RETUNE_C7_0 */
529 { 19470, 0x0000 }, /* R19470 - DACL_RETUNE_C8_1 */
530 { 19471, 0x0000 }, /* R19471 - DACL_RETUNE_C8_0 */
531 { 19472, 0x0000 }, /* R19472 - DACL_RETUNE_C9_1 */
532 { 19473, 0x0000 }, /* R19473 - DACL_RETUNE_C9_0 */
533 { 19474, 0x0000 }, /* R19474 - DACL_RETUNE_C10_1 */
534 { 19475, 0x0000 }, /* R19475 - DACL_RETUNE_C10_0 */
535 { 19476, 0x0000 }, /* R19476 - DACL_RETUNE_C11_1 */
536 { 19477, 0x0000 }, /* R19477 - DACL_RETUNE_C11_0 */
537 { 19478, 0x0000 }, /* R19478 - DACL_RETUNE_C12_1 */
538 { 19479, 0x0000 }, /* R19479 - DACL_RETUNE_C12_0 */
539 { 19480, 0x0000 }, /* R19480 - DACL_RETUNE_C13_1 */
540 { 19481, 0x0000 }, /* R19481 - DACL_RETUNE_C13_0 */
541 { 19482, 0x0000 }, /* R19482 - DACL_RETUNE_C14_1 */
542 { 19483, 0x0000 }, /* R19483 - DACL_RETUNE_C14_0 */
543 { 19484, 0x0000 }, /* R19484 - DACL_RETUNE_C15_1 */
544 { 19485, 0x0000 }, /* R19485 - DACL_RETUNE_C15_0 */
545 { 19486, 0x0000 }, /* R19486 - DACL_RETUNE_C16_1 */
546 { 19487, 0x0000 }, /* R19487 - DACL_RETUNE_C16_0 */
547 { 19488, 0x0000 }, /* R19488 - DACL_RETUNE_C17_1 */
548 { 19489, 0x0000 }, /* R19489 - DACL_RETUNE_C17_0 */
549 { 19490, 0x0000 }, /* R19490 - DACL_RETUNE_C18_1 */
550 { 19491, 0x0000 }, /* R19491 - DACL_RETUNE_C18_0 */
551 { 19492, 0x0000 }, /* R19492 - DACL_RETUNE_C19_1 */
552 { 19493, 0x0000 }, /* R19493 - DACL_RETUNE_C19_0 */
553 { 19494, 0x0000 }, /* R19494 - DACL_RETUNE_C20_1 */
554 { 19495, 0x0000 }, /* R19495 - DACL_RETUNE_C20_0 */
555 { 19496, 0x0000 }, /* R19496 - DACL_RETUNE_C21_1 */
556 { 19497, 0x0000 }, /* R19497 - DACL_RETUNE_C21_0 */
557 { 19498, 0x0000 }, /* R19498 - DACL_RETUNE_C22_1 */
558 { 19499, 0x0000 }, /* R19499 - DACL_RETUNE_C22_0 */
559 { 19500, 0x0000 }, /* R19500 - DACL_RETUNE_C23_1 */
560 { 19501, 0x0000 }, /* R19501 - DACL_RETUNE_C23_0 */
561 { 19502, 0x0000 }, /* R19502 - DACL_RETUNE_C24_1 */
562 { 19503, 0x0000 }, /* R19503 - DACL_RETUNE_C24_0 */
563 { 19504, 0x0000 }, /* R19504 - DACL_RETUNE_C25_1 */
564 { 19505, 0x0000 }, /* R19505 - DACL_RETUNE_C25_0 */
565 { 19506, 0x0000 }, /* R19506 - DACL_RETUNE_C26_1 */
566 { 19507, 0x0000 }, /* R19507 - DACL_RETUNE_C26_0 */
567 { 19508, 0x0000 }, /* R19508 - DACL_RETUNE_C27_1 */
568 { 19509, 0x0000 }, /* R19509 - DACL_RETUNE_C27_0 */
569 { 19510, 0x0000 }, /* R19510 - DACL_RETUNE_C28_1 */
570 { 19511, 0x0000 }, /* R19511 - DACL_RETUNE_C28_0 */
571 { 19512, 0x0000 }, /* R19512 - DACL_RETUNE_C29_1 */
572 { 19513, 0x0000 }, /* R19513 - DACL_RETUNE_C29_0 */
573 { 19514, 0x0000 }, /* R19514 - DACL_RETUNE_C30_1 */
574 { 19515, 0x0000 }, /* R19515 - DACL_RETUNE_C30_0 */
575 { 19516, 0x0000 }, /* R19516 - DACL_RETUNE_C31_1 */
576 { 19517, 0x0000 }, /* R19517 - DACL_RETUNE_C31_0 */
577 { 19518, 0x0000 }, /* R19518 - DACL_RETUNE_C32_1 */
578 { 19519, 0x0000 }, /* R19519 - DACL_RETUNE_C32_0 */
Mark Brownf57f6c042010-10-07 17:41:04 -0700[diff] [blame]579
Mark Brown7b16f562011-11-01 19:32:25 +0000[diff] [blame]580 { 19968, 0x0020 }, /* R19968 - RETUNEDAC_PG2_1 */
581 { 19969, 0x0000 }, /* R19969 - RETUNEDAC_PG2_0 */
582 { 19970, 0x0040 }, /* R19970 - RETUNEDAC_PG_1 */
583 { 19971, 0x0000 }, /* R19971 - RETUNEDAC_PG_0 */
Mark Brownf57f6c042010-10-07 17:41:04 -0700[diff] [blame]584
Mark Brown7b16f562011-11-01 19:32:25 +0000[diff] [blame]585 { 20480, 0x007F }, /* R20480 - DACR_RETUNE_C1_1 */
586 { 20481, 0xFFFF }, /* R20481 - DACR_RETUNE_C1_0 */
587 { 20482, 0x0000 }, /* R20482 - DACR_RETUNE_C2_1 */
588 { 20483, 0x0000 }, /* R20483 - DACR_RETUNE_C2_0 */
589 { 20484, 0x0000 }, /* R20484 - DACR_RETUNE_C3_1 */
590 { 20485, 0x0000 }, /* R20485 - DACR_RETUNE_C3_0 */
591 { 20486, 0x0000 }, /* R20486 - DACR_RETUNE_C4_1 */
592 { 20487, 0x0000 }, /* R20487 - DACR_RETUNE_C4_0 */
593 { 20488, 0x0000 }, /* R20488 - DACR_RETUNE_C5_1 */
594 { 20489, 0x0000 }, /* R20489 - DACR_RETUNE_C5_0 */
595 { 20490, 0x0000 }, /* R20490 - DACR_RETUNE_C6_1 */
596 { 20491, 0x0000 }, /* R20491 - DACR_RETUNE_C6_0 */
597 { 20492, 0x0000 }, /* R20492 - DACR_RETUNE_C7_1 */
598 { 20493, 0x0000 }, /* R20493 - DACR_RETUNE_C7_0 */
599 { 20494, 0x0000 }, /* R20494 - DACR_RETUNE_C8_1 */
600 { 20495, 0x0000 }, /* R20495 - DACR_RETUNE_C8_0 */
601 { 20496, 0x0000 }, /* R20496 - DACR_RETUNE_C9_1 */
602 { 20497, 0x0000 }, /* R20497 - DACR_RETUNE_C9_0 */
603 { 20498, 0x0000 }, /* R20498 - DACR_RETUNE_C10_1 */
604 { 20499, 0x0000 }, /* R20499 - DACR_RETUNE_C10_0 */
605 { 20500, 0x0000 }, /* R20500 - DACR_RETUNE_C11_1 */
606 { 20501, 0x0000 }, /* R20501 - DACR_RETUNE_C11_0 */
607 { 20502, 0x0000 }, /* R20502 - DACR_RETUNE_C12_1 */
608 { 20503, 0x0000 }, /* R20503 - DACR_RETUNE_C12_0 */
609 { 20504, 0x0000 }, /* R20504 - DACR_RETUNE_C13_1 */
610 { 20505, 0x0000 }, /* R20505 - DACR_RETUNE_C13_0 */
611 { 20506, 0x0000 }, /* R20506 - DACR_RETUNE_C14_1 */
612 { 20507, 0x0000 }, /* R20507 - DACR_RETUNE_C14_0 */
613 { 20508, 0x0000 }, /* R20508 - DACR_RETUNE_C15_1 */
614 { 20509, 0x0000 }, /* R20509 - DACR_RETUNE_C15_0 */
615 { 20510, 0x0000 }, /* R20510 - DACR_RETUNE_C16_1 */
616 { 20511, 0x0000 }, /* R20511 - DACR_RETUNE_C16_0 */
617 { 20512, 0x0000 }, /* R20512 - DACR_RETUNE_C17_1 */
618 { 20513, 0x0000 }, /* R20513 - DACR_RETUNE_C17_0 */
619 { 20514, 0x0000 }, /* R20514 - DACR_RETUNE_C18_1 */
620 { 20515, 0x0000 }, /* R20515 - DACR_RETUNE_C18_0 */
621 { 20516, 0x0000 }, /* R20516 - DACR_RETUNE_C19_1 */
622 { 20517, 0x0000 }, /* R20517 - DACR_RETUNE_C19_0 */
623 { 20518, 0x0000 }, /* R20518 - DACR_RETUNE_C20_1 */
624 { 20519, 0x0000 }, /* R20519 - DACR_RETUNE_C20_0 */
625 { 20520, 0x0000 }, /* R20520 - DACR_RETUNE_C21_1 */
626 { 20521, 0x0000 }, /* R20521 - DACR_RETUNE_C21_0 */
627 { 20522, 0x0000 }, /* R20522 - DACR_RETUNE_C22_1 */
628 { 20523, 0x0000 }, /* R20523 - DACR_RETUNE_C22_0 */
629 { 20524, 0x0000 }, /* R20524 - DACR_RETUNE_C23_1 */
630 { 20525, 0x0000 }, /* R20525 - DACR_RETUNE_C23_0 */
631 { 20526, 0x0000 }, /* R20526 - DACR_RETUNE_C24_1 */
632 { 20527, 0x0000 }, /* R20527 - DACR_RETUNE_C24_0 */
633 { 20528, 0x0000 }, /* R20528 - DACR_RETUNE_C25_1 */
634 { 20529, 0x0000 }, /* R20529 - DACR_RETUNE_C25_0 */
635 { 20530, 0x0000 }, /* R20530 - DACR_RETUNE_C26_1 */
636 { 20531, 0x0000 }, /* R20531 - DACR_RETUNE_C26_0 */
637 { 20532, 0x0000 }, /* R20532 - DACR_RETUNE_C27_1 */
638 { 20533, 0x0000 }, /* R20533 - DACR_RETUNE_C27_0 */
639 { 20534, 0x0000 }, /* R20534 - DACR_RETUNE_C28_1 */
640 { 20535, 0x0000 }, /* R20535 - DACR_RETUNE_C28_0 */
641 { 20536, 0x0000 }, /* R20536 - DACR_RETUNE_C29_1 */
642 { 20537, 0x0000 }, /* R20537 - DACR_RETUNE_C29_0 */
643 { 20538, 0x0000 }, /* R20538 - DACR_RETUNE_C30_1 */
644 { 20539, 0x0000 }, /* R20539 - DACR_RETUNE_C30_0 */
645 { 20540, 0x0000 }, /* R20540 - DACR_RETUNE_C31_1 */
646 { 20541, 0x0000 }, /* R20541 - DACR_RETUNE_C31_0 */
647 { 20542, 0x0000 }, /* R20542 - DACR_RETUNE_C32_1 */
648 { 20543, 0x0000 }, /* R20543 - DACR_RETUNE_C32_0 */
Mark Brownf57f6c042010-10-07 17:41:04 -0700[diff] [blame]649
Mark Brown7b16f562011-11-01 19:32:25 +0000[diff] [blame]650 { 20992, 0x008C }, /* R20992 - VSS_XHD2_1 */
651 { 20993, 0x0200 }, /* R20993 - VSS_XHD2_0 */
652 { 20994, 0x0035 }, /* R20994 - VSS_XHD3_1 */
653 { 20995, 0x0700 }, /* R20995 - VSS_XHD3_0 */
654 { 20996, 0x003A }, /* R20996 - VSS_XHN1_1 */
655 { 20997, 0x4100 }, /* R20997 - VSS_XHN1_0 */
656 { 20998, 0x008B }, /* R20998 - VSS_XHN2_1 */
657 { 20999, 0x7D00 }, /* R20999 - VSS_XHN2_0 */
658 { 21000, 0x003A }, /* R21000 - VSS_XHN3_1 */
659 { 21001, 0x4100 }, /* R21001 - VSS_XHN3_0 */
660 { 21002, 0x008C }, /* R21002 - VSS_XLA_1 */
661 { 21003, 0xFEE8 }, /* R21003 - VSS_XLA_0 */
662 { 21004, 0x0078 }, /* R21004 - VSS_XLB_1 */
663 { 21005, 0x0000 }, /* R21005 - VSS_XLB_0 */
664 { 21006, 0x003F }, /* R21006 - VSS_XLG_1 */
665 { 21007, 0xB260 }, /* R21007 - VSS_XLG_0 */
666 { 21008, 0x002D }, /* R21008 - VSS_PG2_1 */
667 { 21009, 0x1818 }, /* R21009 - VSS_PG2_0 */
668 { 21010, 0x0020 }, /* R21010 - VSS_PG_1 */
669 { 21011, 0x0000 }, /* R21011 - VSS_PG_0 */
670 { 21012, 0x00F1 }, /* R21012 - VSS_XTD1_1 */
671 { 21013, 0x8340 }, /* R21013 - VSS_XTD1_0 */
672 { 21014, 0x00FB }, /* R21014 - VSS_XTD2_1 */
673 { 21015, 0x8300 }, /* R21015 - VSS_XTD2_0 */
674 { 21016, 0x00EE }, /* R21016 - VSS_XTD3_1 */
675 { 21017, 0xAEC0 }, /* R21017 - VSS_XTD3_0 */
676 { 21018, 0x00FB }, /* R21018 - VSS_XTD4_1 */
677 { 21019, 0xAC40 }, /* R21019 - VSS_XTD4_0 */
678 { 21020, 0x00F1 }, /* R21020 - VSS_XTD5_1 */
679 { 21021, 0x7F80 }, /* R21021 - VSS_XTD5_0 */
680 { 21022, 0x00F4 }, /* R21022 - VSS_XTD6_1 */
681 { 21023, 0x3B40 }, /* R21023 - VSS_XTD6_0 */
682 { 21024, 0x00F5 }, /* R21024 - VSS_XTD7_1 */
683 { 21025, 0xFB00 }, /* R21025 - VSS_XTD7_0 */
684 { 21026, 0x00EA }, /* R21026 - VSS_XTD8_1 */
685 { 21027, 0x10C0 }, /* R21027 - VSS_XTD8_0 */
686 { 21028, 0x00FC }, /* R21028 - VSS_XTD9_1 */
687 { 21029, 0xC580 }, /* R21029 - VSS_XTD9_0 */
688 { 21030, 0x00E2 }, /* R21030 - VSS_XTD10_1 */
689 { 21031, 0x75C0 }, /* R21031 - VSS_XTD10_0 */
690 { 21032, 0x0004 }, /* R21032 - VSS_XTD11_1 */
691 { 21033, 0xB480 }, /* R21033 - VSS_XTD11_0 */
692 { 21034, 0x00D4 }, /* R21034 - VSS_XTD12_1 */
693 { 21035, 0xF980 }, /* R21035 - VSS_XTD12_0 */
694 { 21036, 0x0004 }, /* R21036 - VSS_XTD13_1 */
695 { 21037, 0x9140 }, /* R21037 - VSS_XTD13_0 */
696 { 21038, 0x00D8 }, /* R21038 - VSS_XTD14_1 */
697 { 21039, 0xA480 }, /* R21039 - VSS_XTD14_0 */
698 { 21040, 0x0002 }, /* R21040 - VSS_XTD15_1 */
699 { 21041, 0x3DC0 }, /* R21041 - VSS_XTD15_0 */
700 { 21042, 0x00CF }, /* R21042 - VSS_XTD16_1 */
701 { 21043, 0x7A80 }, /* R21043 - VSS_XTD16_0 */
702 { 21044, 0x00DC }, /* R21044 - VSS_XTD17_1 */
703 { 21045, 0x0600 }, /* R21045 - VSS_XTD17_0 */
704 { 21046, 0x00F2 }, /* R21046 - VSS_XTD18_1 */
705 { 21047, 0xDAC0 }, /* R21047 - VSS_XTD18_0 */
706 { 21048, 0x00BA }, /* R21048 - VSS_XTD19_1 */
707 { 21049, 0xF340 }, /* R21049 - VSS_XTD19_0 */
708 { 21050, 0x000A }, /* R21050 - VSS_XTD20_1 */
709 { 21051, 0x7940 }, /* R21051 - VSS_XTD20_0 */
710 { 21052, 0x001C }, /* R21052 - VSS_XTD21_1 */
711 { 21053, 0x0680 }, /* R21053 - VSS_XTD21_0 */
712 { 21054, 0x00FD }, /* R21054 - VSS_XTD22_1 */
713 { 21055, 0x2D00 }, /* R21055 - VSS_XTD22_0 */
714 { 21056, 0x001C }, /* R21056 - VSS_XTD23_1 */
715 { 21057, 0xE840 }, /* R21057 - VSS_XTD23_0 */
716 { 21058, 0x000D }, /* R21058 - VSS_XTD24_1 */
717 { 21059, 0xDC40 }, /* R21059 - VSS_XTD24_0 */
718 { 21060, 0x00FC }, /* R21060 - VSS_XTD25_1 */
719 { 21061, 0x9D00 }, /* R21061 - VSS_XTD25_0 */
720 { 21062, 0x0009 }, /* R21062 - VSS_XTD26_1 */
721 { 21063, 0x5580 }, /* R21063 - VSS_XTD26_0 */
722 { 21064, 0x00FE }, /* R21064 - VSS_XTD27_1 */
723 { 21065, 0x7E80 }, /* R21065 - VSS_XTD27_0 */
724 { 21066, 0x000E }, /* R21066 - VSS_XTD28_1 */
725 { 21067, 0xAB40 }, /* R21067 - VSS_XTD28_0 */
726 { 21068, 0x00F9 }, /* R21068 - VSS_XTD29_1 */
727 { 21069, 0x9880 }, /* R21069 - VSS_XTD29_0 */
728 { 21070, 0x0009 }, /* R21070 - VSS_XTD30_1 */
729 { 21071, 0x87C0 }, /* R21071 - VSS_XTD30_0 */
730 { 21072, 0x00FD }, /* R21072 - VSS_XTD31_1 */
731 { 21073, 0x2C40 }, /* R21073 - VSS_XTD31_0 */
732 { 21074, 0x0009 }, /* R21074 - VSS_XTD32_1 */
733 { 21075, 0x4800 }, /* R21075 - VSS_XTD32_0 */
734 { 21076, 0x0003 }, /* R21076 - VSS_XTS1_1 */
735 { 21077, 0x5F40 }, /* R21077 - VSS_XTS1_0 */
736 { 21078, 0x0000 }, /* R21078 - VSS_XTS2_1 */
737 { 21079, 0x8700 }, /* R21079 - VSS_XTS2_0 */
738 { 21080, 0x00FA }, /* R21080 - VSS_XTS3_1 */
739 { 21081, 0xE4C0 }, /* R21081 - VSS_XTS3_0 */
740 { 21082, 0x0000 }, /* R21082 - VSS_XTS4_1 */
741 { 21083, 0x0B40 }, /* R21083 - VSS_XTS4_0 */
742 { 21084, 0x0004 }, /* R21084 - VSS_XTS5_1 */
743 { 21085, 0xE180 }, /* R21085 - VSS_XTS5_0 */
744 { 21086, 0x0001 }, /* R21086 - VSS_XTS6_1 */
745 { 21087, 0x1F40 }, /* R21087 - VSS_XTS6_0 */
746 { 21088, 0x00F8 }, /* R21088 - VSS_XTS7_1 */
747 { 21089, 0xB000 }, /* R21089 - VSS_XTS7_0 */
748 { 21090, 0x00FB }, /* R21090 - VSS_XTS8_1 */
749 { 21091, 0xCBC0 }, /* R21091 - VSS_XTS8_0 */
750 { 21092, 0x0004 }, /* R21092 - VSS_XTS9_1 */
751 { 21093, 0xF380 }, /* R21093 - VSS_XTS9_0 */
752 { 21094, 0x0007 }, /* R21094 - VSS_XTS10_1 */
753 { 21095, 0xDF40 }, /* R21095 - VSS_XTS10_0 */
754 { 21096, 0x00FF }, /* R21096 - VSS_XTS11_1 */
755 { 21097, 0x0700 }, /* R21097 - VSS_XTS11_0 */
756 { 21098, 0x00EF }, /* R21098 - VSS_XTS12_1 */
757 { 21099, 0xD700 }, /* R21099 - VSS_XTS12_0 */
758 { 21100, 0x00FB }, /* R21100 - VSS_XTS13_1 */
759 { 21101, 0xAF40 }, /* R21101 - VSS_XTS13_0 */
760 { 21102, 0x0010 }, /* R21102 - VSS_XTS14_1 */
761 { 21103, 0x8A80 }, /* R21103 - VSS_XTS14_0 */
762 { 21104, 0x0011 }, /* R21104 - VSS_XTS15_1 */
763 { 21105, 0x07C0 }, /* R21105 - VSS_XTS15_0 */
764 { 21106, 0x00E0 }, /* R21106 - VSS_XTS16_1 */
765 { 21107, 0x0800 }, /* R21107 - VSS_XTS16_0 */
766 { 21108, 0x00D2 }, /* R21108 - VSS_XTS17_1 */
767 { 21109, 0x7600 }, /* R21109 - VSS_XTS17_0 */
768 { 21110, 0x0020 }, /* R21110 - VSS_XTS18_1 */
769 { 21111, 0xCF40 }, /* R21111 - VSS_XTS18_0 */
770 { 21112, 0x0030 }, /* R21112 - VSS_XTS19_1 */
771 { 21113, 0x2340 }, /* R21113 - VSS_XTS19_0 */
772 { 21114, 0x00FD }, /* R21114 - VSS_XTS20_1 */
773 { 21115, 0x69C0 }, /* R21115 - VSS_XTS20_0 */
774 { 21116, 0x0028 }, /* R21116 - VSS_XTS21_1 */
775 { 21117, 0x3500 }, /* R21117 - VSS_XTS21_0 */
776 { 21118, 0x0006 }, /* R21118 - VSS_XTS22_1 */
777 { 21119, 0x3300 }, /* R21119 - VSS_XTS22_0 */
778 { 21120, 0x00D9 }, /* R21120 - VSS_XTS23_1 */
779 { 21121, 0xF6C0 }, /* R21121 - VSS_XTS23_0 */
780 { 21122, 0x00F3 }, /* R21122 - VSS_XTS24_1 */
781 { 21123, 0x3340 }, /* R21123 - VSS_XTS24_0 */
782 { 21124, 0x000F }, /* R21124 - VSS_XTS25_1 */
783 { 21125, 0x4200 }, /* R21125 - VSS_XTS25_0 */
784 { 21126, 0x0004 }, /* R21126 - VSS_XTS26_1 */
785 { 21127, 0x0C80 }, /* R21127 - VSS_XTS26_0 */
786 { 21128, 0x00FB }, /* R21128 - VSS_XTS27_1 */
787 { 21129, 0x3F80 }, /* R21129 - VSS_XTS27_0 */
788 { 21130, 0x00F7 }, /* R21130 - VSS_XTS28_1 */
789 { 21131, 0x57C0 }, /* R21131 - VSS_XTS28_0 */
790 { 21132, 0x0003 }, /* R21132 - VSS_XTS29_1 */
791 { 21133, 0x5400 }, /* R21133 - VSS_XTS29_0 */
792 { 21134, 0x0000 }, /* R21134 - VSS_XTS30_1 */
793 { 21135, 0xC6C0 }, /* R21135 - VSS_XTS30_0 */
794 { 21136, 0x0003 }, /* R21136 - VSS_XTS31_1 */
795 { 21137, 0x12C0 }, /* R21137 - VSS_XTS31_0 */
796 { 21138, 0x00FD }, /* R21138 - VSS_XTS32_1 */
797 { 21139, 0x8580 }, /* R21139 - VSS_XTS32_0 */
Mark Brownf57f6c042010-10-07 17:41:04 -0700[diff] [blame]798};
799
Mark Brown7b16f562011-11-01 19:32:25 +0000[diff] [blame]800static bool wm8962_volatile_register(struct device *dev, unsigned int reg)
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]801{
Mark Browncef6d1d2012-01-11 20:13:19 -0800[diff] [blame]802 switch (reg) {
803 case WM8962_CLOCKING1:
804 case WM8962_CLOCKING2:
805 case WM8962_SOFTWARE_RESET:
806 case WM8962_ALC2:
807 case WM8962_THERMAL_SHUTDOWN_STATUS:
808 case WM8962_ADDITIONAL_CONTROL_4:
809 case WM8962_CLASS_D_CONTROL_1:
810 case WM8962_DC_SERVO_6:
811 case WM8962_INTERRUPT_STATUS_1:
812 case WM8962_INTERRUPT_STATUS_2:
813 case WM8962_DSP2_EXECCONTROL:
814 return true;
815 default:
816 return false;
817 }
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]818}
819
Mark Brown7b16f562011-11-01 19:32:25 +0000[diff] [blame]820static bool wm8962_readable_register(struct device *dev, unsigned int reg)
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]821{
Mark Browncef6d1d2012-01-11 20:13:19 -0800[diff] [blame]822 switch (reg) {
823 case WM8962_LEFT_INPUT_VOLUME:
824 case WM8962_RIGHT_INPUT_VOLUME:
825 case WM8962_HPOUTL_VOLUME:
826 case WM8962_HPOUTR_VOLUME:
827 case WM8962_CLOCKING1:
828 case WM8962_ADC_DAC_CONTROL_1:
829 case WM8962_ADC_DAC_CONTROL_2:
830 case WM8962_AUDIO_INTERFACE_0:
831 case WM8962_CLOCKING2:
832 case WM8962_AUDIO_INTERFACE_1:
833 case WM8962_LEFT_DAC_VOLUME:
834 case WM8962_RIGHT_DAC_VOLUME:
835 case WM8962_AUDIO_INTERFACE_2:
836 case WM8962_SOFTWARE_RESET:
837 case WM8962_ALC1:
838 case WM8962_ALC2:
839 case WM8962_ALC3:
840 case WM8962_NOISE_GATE:
841 case WM8962_LEFT_ADC_VOLUME:
842 case WM8962_RIGHT_ADC_VOLUME:
843 case WM8962_ADDITIONAL_CONTROL_1:
844 case WM8962_ADDITIONAL_CONTROL_2:
845 case WM8962_PWR_MGMT_1:
846 case WM8962_PWR_MGMT_2:
847 case WM8962_ADDITIONAL_CONTROL_3:
848 case WM8962_ANTI_POP:
849 case WM8962_CLOCKING_3:
850 case WM8962_INPUT_MIXER_CONTROL_1:
851 case WM8962_LEFT_INPUT_MIXER_VOLUME:
852 case WM8962_RIGHT_INPUT_MIXER_VOLUME:
853 case WM8962_INPUT_MIXER_CONTROL_2:
854 case WM8962_INPUT_BIAS_CONTROL:
855 case WM8962_LEFT_INPUT_PGA_CONTROL:
856 case WM8962_RIGHT_INPUT_PGA_CONTROL:
857 case WM8962_SPKOUTL_VOLUME:
858 case WM8962_SPKOUTR_VOLUME:
859 case WM8962_THERMAL_SHUTDOWN_STATUS:
860 case WM8962_ADDITIONAL_CONTROL_4:
861 case WM8962_CLASS_D_CONTROL_1:
862 case WM8962_CLASS_D_CONTROL_2:
863 case WM8962_CLOCKING_4:
864 case WM8962_DAC_DSP_MIXING_1:
865 case WM8962_DAC_DSP_MIXING_2:
866 case WM8962_DC_SERVO_0:
867 case WM8962_DC_SERVO_1:
868 case WM8962_DC_SERVO_4:
869 case WM8962_DC_SERVO_6:
870 case WM8962_ANALOGUE_PGA_BIAS:
871 case WM8962_ANALOGUE_HP_0:
872 case WM8962_ANALOGUE_HP_2:
873 case WM8962_CHARGE_PUMP_1:
874 case WM8962_CHARGE_PUMP_B:
875 case WM8962_WRITE_SEQUENCER_CONTROL_1:
876 case WM8962_WRITE_SEQUENCER_CONTROL_2:
877 case WM8962_WRITE_SEQUENCER_CONTROL_3:
878 case WM8962_CONTROL_INTERFACE:
879 case WM8962_MIXER_ENABLES:
880 case WM8962_HEADPHONE_MIXER_1:
881 case WM8962_HEADPHONE_MIXER_2:
882 case WM8962_HEADPHONE_MIXER_3:
883 case WM8962_HEADPHONE_MIXER_4:
884 case WM8962_SPEAKER_MIXER_1:
885 case WM8962_SPEAKER_MIXER_2:
886 case WM8962_SPEAKER_MIXER_3:
887 case WM8962_SPEAKER_MIXER_4:
888 case WM8962_SPEAKER_MIXER_5:
889 case WM8962_BEEP_GENERATOR_1:
890 case WM8962_OSCILLATOR_TRIM_3:
891 case WM8962_OSCILLATOR_TRIM_4:
892 case WM8962_OSCILLATOR_TRIM_7:
893 case WM8962_ANALOGUE_CLOCKING1:
894 case WM8962_ANALOGUE_CLOCKING2:
895 case WM8962_ANALOGUE_CLOCKING3:
896 case WM8962_PLL_SOFTWARE_RESET:
897 case WM8962_PLL2:
898 case WM8962_PLL_4:
899 case WM8962_PLL_9:
900 case WM8962_PLL_10:
901 case WM8962_PLL_11:
902 case WM8962_PLL_12:
903 case WM8962_PLL_13:
904 case WM8962_PLL_14:
905 case WM8962_PLL_15:
906 case WM8962_PLL_16:
907 case WM8962_FLL_CONTROL_1:
908 case WM8962_FLL_CONTROL_2:
909 case WM8962_FLL_CONTROL_3:
910 case WM8962_FLL_CONTROL_5:
911 case WM8962_FLL_CONTROL_6:
912 case WM8962_FLL_CONTROL_7:
913 case WM8962_FLL_CONTROL_8:
914 case WM8962_GENERAL_TEST_1:
915 case WM8962_DF1:
916 case WM8962_DF2:
917 case WM8962_DF3:
918 case WM8962_DF4:
919 case WM8962_DF5:
920 case WM8962_DF6:
921 case WM8962_DF7:
922 case WM8962_LHPF1:
923 case WM8962_LHPF2:
924 case WM8962_THREED1:
925 case WM8962_THREED2:
926 case WM8962_THREED3:
927 case WM8962_THREED4:
928 case WM8962_DRC_1:
929 case WM8962_DRC_2:
930 case WM8962_DRC_3:
931 case WM8962_DRC_4:
932 case WM8962_DRC_5:
933 case WM8962_TLOOPBACK:
934 case WM8962_EQ1:
935 case WM8962_EQ2:
936 case WM8962_EQ3:
937 case WM8962_EQ4:
938 case WM8962_EQ5:
939 case WM8962_EQ6:
940 case WM8962_EQ7:
941 case WM8962_EQ8:
942 case WM8962_EQ9:
943 case WM8962_EQ10:
944 case WM8962_EQ11:
945 case WM8962_EQ12:
946 case WM8962_EQ13:
947 case WM8962_EQ14:
948 case WM8962_EQ15:
949 case WM8962_EQ16:
950 case WM8962_EQ17:
951 case WM8962_EQ18:
952 case WM8962_EQ19:
953 case WM8962_EQ20:
954 case WM8962_EQ21:
955 case WM8962_EQ22:
956 case WM8962_EQ23:
957 case WM8962_EQ24:
958 case WM8962_EQ25:
959 case WM8962_EQ26:
960 case WM8962_EQ27:
961 case WM8962_EQ28:
962 case WM8962_EQ29:
963 case WM8962_EQ30:
964 case WM8962_EQ31:
965 case WM8962_EQ32:
966 case WM8962_EQ33:
967 case WM8962_EQ34:
968 case WM8962_EQ35:
969 case WM8962_EQ36:
970 case WM8962_EQ37:
971 case WM8962_EQ38:
972 case WM8962_EQ39:
973 case WM8962_EQ40:
974 case WM8962_EQ41:
975 case WM8962_GPIO_BASE:
976 case WM8962_GPIO_2:
977 case WM8962_GPIO_3:
978 case WM8962_GPIO_5:
979 case WM8962_GPIO_6:
980 case WM8962_INTERRUPT_STATUS_1:
981 case WM8962_INTERRUPT_STATUS_2:
982 case WM8962_INTERRUPT_STATUS_1_MASK:
983 case WM8962_INTERRUPT_STATUS_2_MASK:
984 case WM8962_INTERRUPT_CONTROL:
985 case WM8962_IRQ_DEBOUNCE:
986 case WM8962_MICINT_SOURCE_POL:
987 case WM8962_DSP2_POWER_MANAGEMENT:
988 case WM8962_DSP2_EXECCONTROL:
989 case WM8962_DSP2_INSTRUCTION_RAM_0:
990 case WM8962_DSP2_ADDRESS_RAM_2:
991 case WM8962_DSP2_ADDRESS_RAM_1:
992 case WM8962_DSP2_ADDRESS_RAM_0:
993 case WM8962_DSP2_DATA1_RAM_1:
994 case WM8962_DSP2_DATA1_RAM_0:
995 case WM8962_DSP2_DATA2_RAM_1:
996 case WM8962_DSP2_DATA2_RAM_0:
997 case WM8962_DSP2_DATA3_RAM_1:
998 case WM8962_DSP2_DATA3_RAM_0:
999 case WM8962_DSP2_COEFF_RAM_0:
1000 case WM8962_RETUNEADC_SHARED_COEFF_1:
1001 case WM8962_RETUNEADC_SHARED_COEFF_0:
1002 case WM8962_RETUNEDAC_SHARED_COEFF_1:
1003 case WM8962_RETUNEDAC_SHARED_COEFF_0:
1004 case WM8962_SOUNDSTAGE_ENABLES_1:
1005 case WM8962_SOUNDSTAGE_ENABLES_0:
1006 case WM8962_HDBASS_AI_1:
1007 case WM8962_HDBASS_AI_0:
1008 case WM8962_HDBASS_AR_1:
1009 case WM8962_HDBASS_AR_0:
1010 case WM8962_HDBASS_B_1:
1011 case WM8962_HDBASS_B_0:
1012 case WM8962_HDBASS_K_1:
1013 case WM8962_HDBASS_K_0:
1014 case WM8962_HDBASS_N1_1:
1015 case WM8962_HDBASS_N1_0:
1016 case WM8962_HDBASS_N2_1:
1017 case WM8962_HDBASS_N2_0:
1018 case WM8962_HDBASS_N3_1:
1019 case WM8962_HDBASS_N3_0:
1020 case WM8962_HDBASS_N4_1:
1021 case WM8962_HDBASS_N4_0:
1022 case WM8962_HDBASS_N5_1:
1023 case WM8962_HDBASS_N5_0:
1024 case WM8962_HDBASS_X1_1:
1025 case WM8962_HDBASS_X1_0:
1026 case WM8962_HDBASS_X2_1:
1027 case WM8962_HDBASS_X2_0:
1028 case WM8962_HDBASS_X3_1:
1029 case WM8962_HDBASS_X3_0:
1030 case WM8962_HDBASS_ATK_1:
1031 case WM8962_HDBASS_ATK_0:
1032 case WM8962_HDBASS_DCY_1:
1033 case WM8962_HDBASS_DCY_0:
1034 case WM8962_HDBASS_PG_1:
1035 case WM8962_HDBASS_PG_0:
1036 case WM8962_HPF_C_1:
1037 case WM8962_HPF_C_0:
1038 case WM8962_ADCL_RETUNE_C1_1:
1039 case WM8962_ADCL_RETUNE_C1_0:
1040 case WM8962_ADCL_RETUNE_C2_1:
1041 case WM8962_ADCL_RETUNE_C2_0:
1042 case WM8962_ADCL_RETUNE_C3_1:
1043 case WM8962_ADCL_RETUNE_C3_0:
1044 case WM8962_ADCL_RETUNE_C4_1:
1045 case WM8962_ADCL_RETUNE_C4_0:
1046 case WM8962_ADCL_RETUNE_C5_1:
1047 case WM8962_ADCL_RETUNE_C5_0:
1048 case WM8962_ADCL_RETUNE_C6_1:
1049 case WM8962_ADCL_RETUNE_C6_0:
1050 case WM8962_ADCL_RETUNE_C7_1:
1051 case WM8962_ADCL_RETUNE_C7_0:
1052 case WM8962_ADCL_RETUNE_C8_1:
1053 case WM8962_ADCL_RETUNE_C8_0:
1054 case WM8962_ADCL_RETUNE_C9_1:
1055 case WM8962_ADCL_RETUNE_C9_0:
1056 case WM8962_ADCL_RETUNE_C10_1:
1057 case WM8962_ADCL_RETUNE_C10_0:
1058 case WM8962_ADCL_RETUNE_C11_1:
1059 case WM8962_ADCL_RETUNE_C11_0:
1060 case WM8962_ADCL_RETUNE_C12_1:
1061 case WM8962_ADCL_RETUNE_C12_0:
1062 case WM8962_ADCL_RETUNE_C13_1:
1063 case WM8962_ADCL_RETUNE_C13_0:
1064 case WM8962_ADCL_RETUNE_C14_1:
1065 case WM8962_ADCL_RETUNE_C14_0:
1066 case WM8962_ADCL_RETUNE_C15_1:
1067 case WM8962_ADCL_RETUNE_C15_0:
1068 case WM8962_ADCL_RETUNE_C16_1:
1069 case WM8962_ADCL_RETUNE_C16_0:
1070 case WM8962_ADCL_RETUNE_C17_1:
1071 case WM8962_ADCL_RETUNE_C17_0:
1072 case WM8962_ADCL_RETUNE_C18_1:
1073 case WM8962_ADCL_RETUNE_C18_0:
1074 case WM8962_ADCL_RETUNE_C19_1:
1075 case WM8962_ADCL_RETUNE_C19_0:
1076 case WM8962_ADCL_RETUNE_C20_1:
1077 case WM8962_ADCL_RETUNE_C20_0:
1078 case WM8962_ADCL_RETUNE_C21_1:
1079 case WM8962_ADCL_RETUNE_C21_0:
1080 case WM8962_ADCL_RETUNE_C22_1:
1081 case WM8962_ADCL_RETUNE_C22_0:
1082 case WM8962_ADCL_RETUNE_C23_1:
1083 case WM8962_ADCL_RETUNE_C23_0:
1084 case WM8962_ADCL_RETUNE_C24_1:
1085 case WM8962_ADCL_RETUNE_C24_0:
1086 case WM8962_ADCL_RETUNE_C25_1:
1087 case WM8962_ADCL_RETUNE_C25_0:
1088 case WM8962_ADCL_RETUNE_C26_1:
1089 case WM8962_ADCL_RETUNE_C26_0:
1090 case WM8962_ADCL_RETUNE_C27_1:
1091 case WM8962_ADCL_RETUNE_C27_0:
1092 case WM8962_ADCL_RETUNE_C28_1:
1093 case WM8962_ADCL_RETUNE_C28_0:
1094 case WM8962_ADCL_RETUNE_C29_1:
1095 case WM8962_ADCL_RETUNE_C29_0:
1096 case WM8962_ADCL_RETUNE_C30_1:
1097 case WM8962_ADCL_RETUNE_C30_0:
1098 case WM8962_ADCL_RETUNE_C31_1:
1099 case WM8962_ADCL_RETUNE_C31_0:
1100 case WM8962_ADCL_RETUNE_C32_1:
1101 case WM8962_ADCL_RETUNE_C32_0:
1102 case WM8962_RETUNEADC_PG2_1:
1103 case WM8962_RETUNEADC_PG2_0:
1104 case WM8962_RETUNEADC_PG_1:
1105 case WM8962_RETUNEADC_PG_0:
1106 case WM8962_ADCR_RETUNE_C1_1:
1107 case WM8962_ADCR_RETUNE_C1_0:
1108 case WM8962_ADCR_RETUNE_C2_1:
1109 case WM8962_ADCR_RETUNE_C2_0:
1110 case WM8962_ADCR_RETUNE_C3_1:
1111 case WM8962_ADCR_RETUNE_C3_0:
1112 case WM8962_ADCR_RETUNE_C4_1:
1113 case WM8962_ADCR_RETUNE_C4_0:
1114 case WM8962_ADCR_RETUNE_C5_1:
1115 case WM8962_ADCR_RETUNE_C5_0:
1116 case WM8962_ADCR_RETUNE_C6_1:
1117 case WM8962_ADCR_RETUNE_C6_0:
1118 case WM8962_ADCR_RETUNE_C7_1:
1119 case WM8962_ADCR_RETUNE_C7_0:
1120 case WM8962_ADCR_RETUNE_C8_1:
1121 case WM8962_ADCR_RETUNE_C8_0:
1122 case WM8962_ADCR_RETUNE_C9_1:
1123 case WM8962_ADCR_RETUNE_C9_0:
1124 case WM8962_ADCR_RETUNE_C10_1:
1125 case WM8962_ADCR_RETUNE_C10_0:
1126 case WM8962_ADCR_RETUNE_C11_1:
1127 case WM8962_ADCR_RETUNE_C11_0:
1128 case WM8962_ADCR_RETUNE_C12_1:
1129 case WM8962_ADCR_RETUNE_C12_0:
1130 case WM8962_ADCR_RETUNE_C13_1:
1131 case WM8962_ADCR_RETUNE_C13_0:
1132 case WM8962_ADCR_RETUNE_C14_1:
1133 case WM8962_ADCR_RETUNE_C14_0:
1134 case WM8962_ADCR_RETUNE_C15_1:
1135 case WM8962_ADCR_RETUNE_C15_0:
1136 case WM8962_ADCR_RETUNE_C16_1:
1137 case WM8962_ADCR_RETUNE_C16_0:
1138 case WM8962_ADCR_RETUNE_C17_1:
1139 case WM8962_ADCR_RETUNE_C17_0:
1140 case WM8962_ADCR_RETUNE_C18_1:
1141 case WM8962_ADCR_RETUNE_C18_0:
1142 case WM8962_ADCR_RETUNE_C19_1:
1143 case WM8962_ADCR_RETUNE_C19_0:
1144 case WM8962_ADCR_RETUNE_C20_1:
1145 case WM8962_ADCR_RETUNE_C20_0:
1146 case WM8962_ADCR_RETUNE_C21_1:
1147 case WM8962_ADCR_RETUNE_C21_0:
1148 case WM8962_ADCR_RETUNE_C22_1:
1149 case WM8962_ADCR_RETUNE_C22_0:
1150 case WM8962_ADCR_RETUNE_C23_1:
1151 case WM8962_ADCR_RETUNE_C23_0:
1152 case WM8962_ADCR_RETUNE_C24_1:
1153 case WM8962_ADCR_RETUNE_C24_0:
1154 case WM8962_ADCR_RETUNE_C25_1:
1155 case WM8962_ADCR_RETUNE_C25_0:
1156 case WM8962_ADCR_RETUNE_C26_1:
1157 case WM8962_ADCR_RETUNE_C26_0:
1158 case WM8962_ADCR_RETUNE_C27_1:
1159 case WM8962_ADCR_RETUNE_C27_0:
1160 case WM8962_ADCR_RETUNE_C28_1:
1161 case WM8962_ADCR_RETUNE_C28_0:
1162 case WM8962_ADCR_RETUNE_C29_1:
1163 case WM8962_ADCR_RETUNE_C29_0:
1164 case WM8962_ADCR_RETUNE_C30_1:
1165 case WM8962_ADCR_RETUNE_C30_0:
1166 case WM8962_ADCR_RETUNE_C31_1:
1167 case WM8962_ADCR_RETUNE_C31_0:
1168 case WM8962_ADCR_RETUNE_C32_1:
1169 case WM8962_ADCR_RETUNE_C32_0:
1170 case WM8962_DACL_RETUNE_C1_1:
1171 case WM8962_DACL_RETUNE_C1_0:
1172 case WM8962_DACL_RETUNE_C2_1:
1173 case WM8962_DACL_RETUNE_C2_0:
1174 case WM8962_DACL_RETUNE_C3_1:
1175 case WM8962_DACL_RETUNE_C3_0:
1176 case WM8962_DACL_RETUNE_C4_1:
1177 case WM8962_DACL_RETUNE_C4_0:
1178 case WM8962_DACL_RETUNE_C5_1:
1179 case WM8962_DACL_RETUNE_C5_0:
1180 case WM8962_DACL_RETUNE_C6_1:
1181 case WM8962_DACL_RETUNE_C6_0:
1182 case WM8962_DACL_RETUNE_C7_1:
1183 case WM8962_DACL_RETUNE_C7_0:
1184 case WM8962_DACL_RETUNE_C8_1:
1185 case WM8962_DACL_RETUNE_C8_0:
1186 case WM8962_DACL_RETUNE_C9_1:
1187 case WM8962_DACL_RETUNE_C9_0:
1188 case WM8962_DACL_RETUNE_C10_1:
1189 case WM8962_DACL_RETUNE_C10_0:
1190 case WM8962_DACL_RETUNE_C11_1:
1191 case WM8962_DACL_RETUNE_C11_0:
1192 case WM8962_DACL_RETUNE_C12_1:
1193 case WM8962_DACL_RETUNE_C12_0:
1194 case WM8962_DACL_RETUNE_C13_1:
1195 case WM8962_DACL_RETUNE_C13_0:
1196 case WM8962_DACL_RETUNE_C14_1:
1197 case WM8962_DACL_RETUNE_C14_0:
1198 case WM8962_DACL_RETUNE_C15_1:
1199 case WM8962_DACL_RETUNE_C15_0:
1200 case WM8962_DACL_RETUNE_C16_1:
1201 case WM8962_DACL_RETUNE_C16_0:
1202 case WM8962_DACL_RETUNE_C17_1:
1203 case WM8962_DACL_RETUNE_C17_0:
1204 case WM8962_DACL_RETUNE_C18_1:
1205 case WM8962_DACL_RETUNE_C18_0:
1206 case WM8962_DACL_RETUNE_C19_1:
1207 case WM8962_DACL_RETUNE_C19_0:
1208 case WM8962_DACL_RETUNE_C20_1:
1209 case WM8962_DACL_RETUNE_C20_0:
1210 case WM8962_DACL_RETUNE_C21_1:
1211 case WM8962_DACL_RETUNE_C21_0:
1212 case WM8962_DACL_RETUNE_C22_1:
1213 case WM8962_DACL_RETUNE_C22_0:
1214 case WM8962_DACL_RETUNE_C23_1:
1215 case WM8962_DACL_RETUNE_C23_0:
1216 case WM8962_DACL_RETUNE_C24_1:
1217 case WM8962_DACL_RETUNE_C24_0:
1218 case WM8962_DACL_RETUNE_C25_1:
1219 case WM8962_DACL_RETUNE_C25_0:
1220 case WM8962_DACL_RETUNE_C26_1:
1221 case WM8962_DACL_RETUNE_C26_0:
1222 case WM8962_DACL_RETUNE_C27_1:
1223 case WM8962_DACL_RETUNE_C27_0:
1224 case WM8962_DACL_RETUNE_C28_1:
1225 case WM8962_DACL_RETUNE_C28_0:
1226 case WM8962_DACL_RETUNE_C29_1:
1227 case WM8962_DACL_RETUNE_C29_0:
1228 case WM8962_DACL_RETUNE_C30_1:
1229 case WM8962_DACL_RETUNE_C30_0:
1230 case WM8962_DACL_RETUNE_C31_1:
1231 case WM8962_DACL_RETUNE_C31_0:
1232 case WM8962_DACL_RETUNE_C32_1:
1233 case WM8962_DACL_RETUNE_C32_0:
1234 case WM8962_RETUNEDAC_PG2_1:
1235 case WM8962_RETUNEDAC_PG2_0:
1236 case WM8962_RETUNEDAC_PG_1:
1237 case WM8962_RETUNEDAC_PG_0:
1238 case WM8962_DACR_RETUNE_C1_1:
1239 case WM8962_DACR_RETUNE_C1_0:
1240 case WM8962_DACR_RETUNE_C2_1:
1241 case WM8962_DACR_RETUNE_C2_0:
1242 case WM8962_DACR_RETUNE_C3_1:
1243 case WM8962_DACR_RETUNE_C3_0:
1244 case WM8962_DACR_RETUNE_C4_1:
1245 case WM8962_DACR_RETUNE_C4_0:
1246 case WM8962_DACR_RETUNE_C5_1:
1247 case WM8962_DACR_RETUNE_C5_0:
1248 case WM8962_DACR_RETUNE_C6_1:
1249 case WM8962_DACR_RETUNE_C6_0:
1250 case WM8962_DACR_RETUNE_C7_1:
1251 case WM8962_DACR_RETUNE_C7_0:
1252 case WM8962_DACR_RETUNE_C8_1:
1253 case WM8962_DACR_RETUNE_C8_0:
1254 case WM8962_DACR_RETUNE_C9_1:
1255 case WM8962_DACR_RETUNE_C9_0:
1256 case WM8962_DACR_RETUNE_C10_1:
1257 case WM8962_DACR_RETUNE_C10_0:
1258 case WM8962_DACR_RETUNE_C11_1:
1259 case WM8962_DACR_RETUNE_C11_0:
1260 case WM8962_DACR_RETUNE_C12_1:
1261 case WM8962_DACR_RETUNE_C12_0:
1262 case WM8962_DACR_RETUNE_C13_1:
1263 case WM8962_DACR_RETUNE_C13_0:
1264 case WM8962_DACR_RETUNE_C14_1:
1265 case WM8962_DACR_RETUNE_C14_0:
1266 case WM8962_DACR_RETUNE_C15_1:
1267 case WM8962_DACR_RETUNE_C15_0:
1268 case WM8962_DACR_RETUNE_C16_1:
1269 case WM8962_DACR_RETUNE_C16_0:
1270 case WM8962_DACR_RETUNE_C17_1:
1271 case WM8962_DACR_RETUNE_C17_0:
1272 case WM8962_DACR_RETUNE_C18_1:
1273 case WM8962_DACR_RETUNE_C18_0:
1274 case WM8962_DACR_RETUNE_C19_1:
1275 case WM8962_DACR_RETUNE_C19_0:
1276 case WM8962_DACR_RETUNE_C20_1:
1277 case WM8962_DACR_RETUNE_C20_0:
1278 case WM8962_DACR_RETUNE_C21_1:
1279 case WM8962_DACR_RETUNE_C21_0:
1280 case WM8962_DACR_RETUNE_C22_1:
1281 case WM8962_DACR_RETUNE_C22_0:
1282 case WM8962_DACR_RETUNE_C23_1:
1283 case WM8962_DACR_RETUNE_C23_0:
1284 case WM8962_DACR_RETUNE_C24_1:
1285 case WM8962_DACR_RETUNE_C24_0:
1286 case WM8962_DACR_RETUNE_C25_1:
1287 case WM8962_DACR_RETUNE_C25_0:
1288 case WM8962_DACR_RETUNE_C26_1:
1289 case WM8962_DACR_RETUNE_C26_0:
1290 case WM8962_DACR_RETUNE_C27_1:
1291 case WM8962_DACR_RETUNE_C27_0:
1292 case WM8962_DACR_RETUNE_C28_1:
1293 case WM8962_DACR_RETUNE_C28_0:
1294 case WM8962_DACR_RETUNE_C29_1:
1295 case WM8962_DACR_RETUNE_C29_0:
1296 case WM8962_DACR_RETUNE_C30_1:
1297 case WM8962_DACR_RETUNE_C30_0:
1298 case WM8962_DACR_RETUNE_C31_1:
1299 case WM8962_DACR_RETUNE_C31_0:
1300 case WM8962_DACR_RETUNE_C32_1:
1301 case WM8962_DACR_RETUNE_C32_0:
1302 case WM8962_VSS_XHD2_1:
1303 case WM8962_VSS_XHD2_0:
1304 case WM8962_VSS_XHD3_1:
1305 case WM8962_VSS_XHD3_0:
1306 case WM8962_VSS_XHN1_1:
1307 case WM8962_VSS_XHN1_0:
1308 case WM8962_VSS_XHN2_1:
1309 case WM8962_VSS_XHN2_0:
1310 case WM8962_VSS_XHN3_1:
1311 case WM8962_VSS_XHN3_0:
1312 case WM8962_VSS_XLA_1:
1313 case WM8962_VSS_XLA_0:
1314 case WM8962_VSS_XLB_1:
1315 case WM8962_VSS_XLB_0:
1316 case WM8962_VSS_XLG_1:
1317 case WM8962_VSS_XLG_0:
1318 case WM8962_VSS_PG2_1:
1319 case WM8962_VSS_PG2_0:
1320 case WM8962_VSS_PG_1:
1321 case WM8962_VSS_PG_0:
1322 case WM8962_VSS_XTD1_1:
1323 case WM8962_VSS_XTD1_0:
1324 case WM8962_VSS_XTD2_1:
1325 case WM8962_VSS_XTD2_0:
1326 case WM8962_VSS_XTD3_1:
1327 case WM8962_VSS_XTD3_0:
1328 case WM8962_VSS_XTD4_1:
1329 case WM8962_VSS_XTD4_0:
1330 case WM8962_VSS_XTD5_1:
1331 case WM8962_VSS_XTD5_0:
1332 case WM8962_VSS_XTD6_1:
1333 case WM8962_VSS_XTD6_0:
1334 case WM8962_VSS_XTD7_1:
1335 case WM8962_VSS_XTD7_0:
1336 case WM8962_VSS_XTD8_1:
1337 case WM8962_VSS_XTD8_0:
1338 case WM8962_VSS_XTD9_1:
1339 case WM8962_VSS_XTD9_0:
1340 case WM8962_VSS_XTD10_1:
1341 case WM8962_VSS_XTD10_0:
1342 case WM8962_VSS_XTD11_1:
1343 case WM8962_VSS_XTD11_0:
1344 case WM8962_VSS_XTD12_1:
1345 case WM8962_VSS_XTD12_0:
1346 case WM8962_VSS_XTD13_1:
1347 case WM8962_VSS_XTD13_0:
1348 case WM8962_VSS_XTD14_1:
1349 case WM8962_VSS_XTD14_0:
1350 case WM8962_VSS_XTD15_1:
1351 case WM8962_VSS_XTD15_0:
1352 case WM8962_VSS_XTD16_1:
1353 case WM8962_VSS_XTD16_0:
1354 case WM8962_VSS_XTD17_1:
1355 case WM8962_VSS_XTD17_0:
1356 case WM8962_VSS_XTD18_1:
1357 case WM8962_VSS_XTD18_0:
1358 case WM8962_VSS_XTD19_1:
1359 case WM8962_VSS_XTD19_0:
1360 case WM8962_VSS_XTD20_1:
1361 case WM8962_VSS_XTD20_0:
1362 case WM8962_VSS_XTD21_1:
1363 case WM8962_VSS_XTD21_0:
1364 case WM8962_VSS_XTD22_1:
1365 case WM8962_VSS_XTD22_0:
1366 case WM8962_VSS_XTD23_1:
1367 case WM8962_VSS_XTD23_0:
1368 case WM8962_VSS_XTD24_1:
1369 case WM8962_VSS_XTD24_0:
1370 case WM8962_VSS_XTD25_1:
1371 case WM8962_VSS_XTD25_0:
1372 case WM8962_VSS_XTD26_1:
1373 case WM8962_VSS_XTD26_0:
1374 case WM8962_VSS_XTD27_1:
1375 case WM8962_VSS_XTD27_0:
1376 case WM8962_VSS_XTD28_1:
1377 case WM8962_VSS_XTD28_0:
1378 case WM8962_VSS_XTD29_1:
1379 case WM8962_VSS_XTD29_0:
1380 case WM8962_VSS_XTD30_1:
1381 case WM8962_VSS_XTD30_0:
1382 case WM8962_VSS_XTD31_1:
1383 case WM8962_VSS_XTD31_0:
1384 case WM8962_VSS_XTD32_1:
1385 case WM8962_VSS_XTD32_0:
1386 case WM8962_VSS_XTS1_1:
1387 case WM8962_VSS_XTS1_0:
1388 case WM8962_VSS_XTS2_1:
1389 case WM8962_VSS_XTS2_0:
1390 case WM8962_VSS_XTS3_1:
1391 case WM8962_VSS_XTS3_0:
1392 case WM8962_VSS_XTS4_1:
1393 case WM8962_VSS_XTS4_0:
1394 case WM8962_VSS_XTS5_1:
1395 case WM8962_VSS_XTS5_0:
1396 case WM8962_VSS_XTS6_1:
1397 case WM8962_VSS_XTS6_0:
1398 case WM8962_VSS_XTS7_1:
1399 case WM8962_VSS_XTS7_0:
1400 case WM8962_VSS_XTS8_1:
1401 case WM8962_VSS_XTS8_0:
1402 case WM8962_VSS_XTS9_1:
1403 case WM8962_VSS_XTS9_0:
1404 case WM8962_VSS_XTS10_1:
1405 case WM8962_VSS_XTS10_0:
1406 case WM8962_VSS_XTS11_1:
1407 case WM8962_VSS_XTS11_0:
1408 case WM8962_VSS_XTS12_1:
1409 case WM8962_VSS_XTS12_0:
1410 case WM8962_VSS_XTS13_1:
1411 case WM8962_VSS_XTS13_0:
1412 case WM8962_VSS_XTS14_1:
1413 case WM8962_VSS_XTS14_0:
1414 case WM8962_VSS_XTS15_1:
1415 case WM8962_VSS_XTS15_0:
1416 case WM8962_VSS_XTS16_1:
1417 case WM8962_VSS_XTS16_0:
1418 case WM8962_VSS_XTS17_1:
1419 case WM8962_VSS_XTS17_0:
1420 case WM8962_VSS_XTS18_1:
1421 case WM8962_VSS_XTS18_0:
1422 case WM8962_VSS_XTS19_1:
1423 case WM8962_VSS_XTS19_0:
1424 case WM8962_VSS_XTS20_1:
1425 case WM8962_VSS_XTS20_0:
1426 case WM8962_VSS_XTS21_1:
1427 case WM8962_VSS_XTS21_0:
1428 case WM8962_VSS_XTS22_1:
1429 case WM8962_VSS_XTS22_0:
1430 case WM8962_VSS_XTS23_1:
1431 case WM8962_VSS_XTS23_0:
1432 case WM8962_VSS_XTS24_1:
1433 case WM8962_VSS_XTS24_0:
1434 case WM8962_VSS_XTS25_1:
1435 case WM8962_VSS_XTS25_0:
1436 case WM8962_VSS_XTS26_1:
1437 case WM8962_VSS_XTS26_0:
1438 case WM8962_VSS_XTS27_1:
1439 case WM8962_VSS_XTS27_0:
1440 case WM8962_VSS_XTS28_1:
1441 case WM8962_VSS_XTS28_0:
1442 case WM8962_VSS_XTS29_1:
1443 case WM8962_VSS_XTS29_0:
1444 case WM8962_VSS_XTS30_1:
1445 case WM8962_VSS_XTS30_0:
1446 case WM8962_VSS_XTS31_1:
1447 case WM8962_VSS_XTS31_0:
1448 case WM8962_VSS_XTS32_1:
1449 case WM8962_VSS_XTS32_0:
1450 return true;
1451 default:
1452 return false;
1453 }
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]1454}
1455
Mark Brown7b16f562011-11-01 19:32:25 +0000[diff] [blame]1456static int wm8962_reset(struct wm8962_priv *wm8962)
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]1457{
Mark Brown4f4488a2011-11-01 13:36:10 +0000[diff] [blame]1458 int ret;
1459
Mark Brown7b16f562011-11-01 19:32:25 +0000[diff] [blame]1460 ret = regmap_write(wm8962->regmap, WM8962_SOFTWARE_RESET, 0x6243);
Mark Brown4f4488a2011-11-01 13:36:10 +0000[diff] [blame]1461 if (ret != 0)
1462 return ret;
1463
Mark Brown7b16f562011-11-01 19:32:25 +0000[diff] [blame]1464 return regmap_write(wm8962->regmap, WM8962_PLL_SOFTWARE_RESET, 0);
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]1465}
1466
1467static const DECLARE_TLV_DB_SCALE(inpga_tlv, -2325, 75, 0);
1468static const DECLARE_TLV_DB_SCALE(mixin_tlv, -1500, 300, 0);
1469static const unsigned int mixinpga_tlv[] = {
Clemens Ladisch43e9dc72011-11-20 15:13:27 +0100[diff] [blame]1470 TLV_DB_RANGE_HEAD(5),
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]1471 0, 1, TLV_DB_SCALE_ITEM(0, 600, 0),
1472 2, 2, TLV_DB_SCALE_ITEM(1300, 1300, 0),
1473 3, 4, TLV_DB_SCALE_ITEM(1800, 200, 0),
1474 5, 5, TLV_DB_SCALE_ITEM(2400, 0, 0),
1475 6, 7, TLV_DB_SCALE_ITEM(2700, 300, 0),
1476};
1477static const DECLARE_TLV_DB_SCALE(beep_tlv, -9600, 600, 1);
1478static const DECLARE_TLV_DB_SCALE(digital_tlv, -7200, 75, 1);
1479static const DECLARE_TLV_DB_SCALE(st_tlv, -3600, 300, 0);
1480static const DECLARE_TLV_DB_SCALE(inmix_tlv, -600, 600, 0);
1481static const DECLARE_TLV_DB_SCALE(bypass_tlv, -1500, 300, 0);
1482static const DECLARE_TLV_DB_SCALE(out_tlv, -12100, 100, 1);
1483static const DECLARE_TLV_DB_SCALE(hp_tlv, -700, 100, 0);
1484static const unsigned int classd_tlv[] = {
Clemens Ladisch43e9dc72011-11-20 15:13:27 +0100[diff] [blame]1485 TLV_DB_RANGE_HEAD(2),
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]1486 0, 6, TLV_DB_SCALE_ITEM(0, 150, 0),
1487 7, 7, TLV_DB_SCALE_ITEM(1200, 0, 0),
1488};
Mark Brown8f63aaa882011-06-07 23:14:37 +0100[diff] [blame]1489static const DECLARE_TLV_DB_SCALE(eq_tlv, -1200, 100, 0);
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]1490
Mark Brown6f88a4e2011-08-17 10:03:51 +0900[diff] [blame]1491static int wm8962_dsp2_write_config(struct snd_soc_codec *codec)
1492{
1493 return 0;
1494}
1495
1496static int wm8962_dsp2_set_enable(struct snd_soc_codec *codec, u16 val)
1497{
1498 u16 adcl = snd_soc_read(codec, WM8962_LEFT_ADC_VOLUME);
1499 u16 adcr = snd_soc_read(codec, WM8962_RIGHT_ADC_VOLUME);
1500 u16 dac = snd_soc_read(codec, WM8962_ADC_DAC_CONTROL_1);
1501
1502 /* Mute the ADCs and DACs */
1503 snd_soc_write(codec, WM8962_LEFT_ADC_VOLUME, 0);
1504 snd_soc_write(codec, WM8962_RIGHT_ADC_VOLUME, WM8962_ADC_VU);
1505 snd_soc_update_bits(codec, WM8962_ADC_DAC_CONTROL_1,
1506 WM8962_DAC_MUTE, WM8962_DAC_MUTE);
1507
1508 snd_soc_write(codec, WM8962_SOUNDSTAGE_ENABLES_0, val);
1509
1510 /* Restore the ADCs and DACs */
1511 snd_soc_write(codec, WM8962_LEFT_ADC_VOLUME, adcl);
1512 snd_soc_write(codec, WM8962_RIGHT_ADC_VOLUME, adcr);
1513 snd_soc_update_bits(codec, WM8962_ADC_DAC_CONTROL_1,
1514 WM8962_DAC_MUTE, dac);
1515
1516 return 0;
1517}
1518
1519static int wm8962_dsp2_start(struct snd_soc_codec *codec)
1520{
1521 struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec);
1522
1523 wm8962_dsp2_write_config(codec);
1524
1525 snd_soc_write(codec, WM8962_DSP2_EXECCONTROL, WM8962_DSP2_RUNR);
1526
1527 wm8962_dsp2_set_enable(codec, wm8962->dsp2_ena);
1528
1529 return 0;
1530}
1531
1532static int wm8962_dsp2_stop(struct snd_soc_codec *codec)
1533{
1534 wm8962_dsp2_set_enable(codec, 0);
1535
1536 snd_soc_write(codec, WM8962_DSP2_EXECCONTROL, WM8962_DSP2_STOP);
1537
1538 return 0;
1539}
1540
1541#define WM8962_DSP2_ENABLE(xname, xshift) \
1542{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
1543 .info = wm8962_dsp2_ena_info, \
1544 .get = wm8962_dsp2_ena_get, .put = wm8962_dsp2_ena_put, \
1545 .private_value = xshift }
1546
1547static int wm8962_dsp2_ena_info(struct snd_kcontrol *kcontrol,
1548 struct snd_ctl_elem_info *uinfo)
1549{
1550 uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
1551
1552 uinfo->count = 1;
1553 uinfo->value.integer.min = 0;
1554 uinfo->value.integer.max = 1;
1555
1556 return 0;
1557}
1558
1559static int wm8962_dsp2_ena_get(struct snd_kcontrol *kcontrol,
1560 struct snd_ctl_elem_value *ucontrol)
1561{
1562 int shift = kcontrol->private_value;
1563 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
1564 struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec);
1565
1566 ucontrol->value.integer.value[0] = !!(wm8962->dsp2_ena & 1 << shift);
1567
1568 return 0;
1569}
1570
1571static int wm8962_dsp2_ena_put(struct snd_kcontrol *kcontrol,
1572 struct snd_ctl_elem_value *ucontrol)
1573{
1574 int shift = kcontrol->private_value;
1575 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
1576 struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec);
1577 int old = wm8962->dsp2_ena;
1578 int ret = 0;
1579 int dsp2_running = snd_soc_read(codec, WM8962_DSP2_POWER_MANAGEMENT) &
1580 WM8962_DSP2_ENA;
1581
1582 mutex_lock(&codec->mutex);
1583
1584 if (ucontrol->value.integer.value[0])
1585 wm8962->dsp2_ena |= 1 << shift;
1586 else
1587 wm8962->dsp2_ena &= ~(1 << shift);
1588
1589 if (wm8962->dsp2_ena == old)
1590 goto out;
1591
1592 ret = 1;
1593
1594 if (dsp2_running) {
1595 if (wm8962->dsp2_ena)
1596 wm8962_dsp2_set_enable(codec, wm8962->dsp2_ena);
1597 else
1598 wm8962_dsp2_stop(codec);
1599 }
1600
1601out:
1602 mutex_unlock(&codec->mutex);
1603
1604 return ret;
1605}
1606
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]1607/* The VU bits for the headphones are in a different register to the mute
1608 * bits and only take effect on the PGA if it is actually powered.
1609 */
1610static int wm8962_put_hp_sw(struct snd_kcontrol *kcontrol,
1611 struct snd_ctl_elem_value *ucontrol)
1612{
1613 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
Lars-Peter Clausen7f87e302010-12-28 21:38:01 +0100[diff] [blame]1614 u16 *reg_cache = codec->reg_cache;
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]1615 int ret;
1616
1617 /* Apply the update (if any) */
1618 ret = snd_soc_put_volsw(kcontrol, ucontrol);
1619 if (ret == 0)
1620 return 0;
1621
1622 /* If the left PGA is enabled hit that VU bit... */
Mark Brown0f82bdf2011-06-07 23:42:04 +0100[diff] [blame]1623 if (snd_soc_read(codec, WM8962_PWR_MGMT_2) & WM8962_HPOUTL_PGA_ENA)
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]1624 return snd_soc_write(codec, WM8962_HPOUTL_VOLUME,
1625 reg_cache[WM8962_HPOUTL_VOLUME]);
1626
1627 /* ...otherwise the right. The VU is stereo. */
Mark Brown0f82bdf2011-06-07 23:42:04 +0100[diff] [blame]1628 if (snd_soc_read(codec, WM8962_PWR_MGMT_2) & WM8962_HPOUTR_PGA_ENA)
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]1629 return snd_soc_write(codec, WM8962_HPOUTR_VOLUME,
1630 reg_cache[WM8962_HPOUTR_VOLUME]);
1631
1632 return 0;
1633}
1634
1635/* The VU bits for the speakers are in a different register to the mute
1636 * bits and only take effect on the PGA if it is actually powered.
1637 */
1638static int wm8962_put_spk_sw(struct snd_kcontrol *kcontrol,
1639 struct snd_ctl_elem_value *ucontrol)
1640{
1641 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]1642 int ret;
1643
1644 /* Apply the update (if any) */
1645 ret = snd_soc_put_volsw(kcontrol, ucontrol);
1646 if (ret == 0)
1647 return 0;
1648
1649 /* If the left PGA is enabled hit that VU bit... */
Mark Brown38f3f312011-09-23 21:26:33 +0100[diff] [blame]1650 ret = snd_soc_read(codec, WM8962_PWR_MGMT_2);
1651 if (ret & WM8962_SPKOUTL_PGA_ENA) {
1652 snd_soc_write(codec, WM8962_SPKOUTL_VOLUME,
1653 snd_soc_read(codec, WM8962_SPKOUTL_VOLUME));
1654 return 1;
1655 }
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]1656
1657 /* ...otherwise the right. The VU is stereo. */
Mark Brown38f3f312011-09-23 21:26:33 +0100[diff] [blame]1658 if (ret & WM8962_SPKOUTR_PGA_ENA)
1659 snd_soc_write(codec, WM8962_SPKOUTR_VOLUME,
1660 snd_soc_read(codec, WM8962_SPKOUTR_VOLUME));
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]1661
Mark Brown38f3f312011-09-23 21:26:33 +0100[diff] [blame]1662 return 1;
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]1663}
1664
Mark Brown6be449e2011-04-26 16:04:37 +0100[diff] [blame]1665static const char *cap_hpf_mode_text[] = {
1666 "Hi-fi", "Application"
1667};
1668
1669static const struct soc_enum cap_hpf_mode =
1670 SOC_ENUM_SINGLE(WM8962_ADC_DAC_CONTROL_2, 10, 2, cap_hpf_mode_text);
1671
Mark Brown1ab63da2011-08-21 10:54:38 +0100[diff] [blame]1672
1673static const char *cap_lhpf_mode_text[] = {
1674 "LPF", "HPF"
1675};
1676
1677static const struct soc_enum cap_lhpf_mode =
1678 SOC_ENUM_SINGLE(WM8962_LHPF1, 1, 2, cap_lhpf_mode_text);
1679
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]1680static const struct snd_kcontrol_new wm8962_snd_controls[] = {
1681SOC_DOUBLE("Input Mixer Switch", WM8962_INPUT_MIXER_CONTROL_1, 3, 2, 1, 1),
1682
1683SOC_SINGLE_TLV("MIXINL IN2L Volume", WM8962_LEFT_INPUT_MIXER_VOLUME, 6, 7, 0,
1684 mixin_tlv),
1685SOC_SINGLE_TLV("MIXINL PGA Volume", WM8962_LEFT_INPUT_MIXER_VOLUME, 3, 7, 0,
1686 mixinpga_tlv),
1687SOC_SINGLE_TLV("MIXINL IN3L Volume", WM8962_LEFT_INPUT_MIXER_VOLUME, 0, 7, 0,
1688 mixin_tlv),
1689
1690SOC_SINGLE_TLV("MIXINR IN2R Volume", WM8962_RIGHT_INPUT_MIXER_VOLUME, 6, 7, 0,
1691 mixin_tlv),
1692SOC_SINGLE_TLV("MIXINR PGA Volume", WM8962_RIGHT_INPUT_MIXER_VOLUME, 3, 7, 0,
1693 mixinpga_tlv),
1694SOC_SINGLE_TLV("MIXINR IN3R Volume", WM8962_RIGHT_INPUT_MIXER_VOLUME, 0, 7, 0,
1695 mixin_tlv),
1696
1697SOC_DOUBLE_R_TLV("Digital Capture Volume", WM8962_LEFT_ADC_VOLUME,
1698 WM8962_RIGHT_ADC_VOLUME, 1, 127, 0, digital_tlv),
1699SOC_DOUBLE_R_TLV("Capture Volume", WM8962_LEFT_INPUT_VOLUME,
1700 WM8962_RIGHT_INPUT_VOLUME, 0, 63, 0, inpga_tlv),
1701SOC_DOUBLE_R("Capture Switch", WM8962_LEFT_INPUT_VOLUME,
1702 WM8962_RIGHT_INPUT_VOLUME, 7, 1, 1),
1703SOC_DOUBLE_R("Capture ZC Switch", WM8962_LEFT_INPUT_VOLUME,
1704 WM8962_RIGHT_INPUT_VOLUME, 6, 1, 1),
Mark Brown6be449e2011-04-26 16:04:37 +0100[diff] [blame]1705SOC_SINGLE("Capture HPF Switch", WM8962_ADC_DAC_CONTROL_1, 0, 1, 1),
1706SOC_ENUM("Capture HPF Mode", cap_hpf_mode),
1707SOC_SINGLE("Capture HPF Cutoff", WM8962_ADC_DAC_CONTROL_2, 7, 7, 0),
Mark Brown1ab63da2011-08-21 10:54:38 +0100[diff] [blame]1708SOC_SINGLE("Capture LHPF Switch", WM8962_LHPF1, 0, 1, 0),
1709SOC_ENUM("Capture LHPF Mode", cap_lhpf_mode),
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]1710
1711SOC_DOUBLE_R_TLV("Sidetone Volume", WM8962_DAC_DSP_MIXING_1,
1712 WM8962_DAC_DSP_MIXING_2, 4, 12, 0, st_tlv),
1713
1714SOC_DOUBLE_R_TLV("Digital Playback Volume", WM8962_LEFT_DAC_VOLUME,
1715 WM8962_RIGHT_DAC_VOLUME, 1, 127, 0, digital_tlv),
1716SOC_SINGLE("DAC High Performance Switch", WM8962_ADC_DAC_CONTROL_2, 0, 1, 0),
Mark Brown5f52ee42012-01-11 16:31:00 -0800[diff] [blame^]1717SOC_SINGLE("DAC L/R Swap Switch", WM8962_AUDIO_INTERFACE_0, 5, 1, 0),
1718SOC_SINGLE("ADC L/R Swap Switch", WM8962_AUDIO_INTERFACE_0, 8, 1, 0),
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]1719
1720SOC_SINGLE("ADC High Performance Switch", WM8962_ADDITIONAL_CONTROL_1,
1721 5, 1, 0),
1722
1723SOC_SINGLE_TLV("Beep Volume", WM8962_BEEP_GENERATOR_1, 4, 15, 0, beep_tlv),
1724
1725SOC_DOUBLE_R_TLV("Headphone Volume", WM8962_HPOUTL_VOLUME,
1726 WM8962_HPOUTR_VOLUME, 0, 127, 0, out_tlv),
1727SOC_DOUBLE_EXT("Headphone Switch", WM8962_PWR_MGMT_2, 1, 0, 1, 1,
1728 snd_soc_get_volsw, wm8962_put_hp_sw),
1729SOC_DOUBLE_R("Headphone ZC Switch", WM8962_HPOUTL_VOLUME, WM8962_HPOUTR_VOLUME,
1730 7, 1, 0),
1731SOC_DOUBLE_TLV("Headphone Aux Volume", WM8962_ANALOGUE_HP_2, 3, 6, 7, 0,
1732 hp_tlv),
1733
1734SOC_DOUBLE_R("Headphone Mixer Switch", WM8962_HEADPHONE_MIXER_3,
1735 WM8962_HEADPHONE_MIXER_4, 8, 1, 1),
1736
1737SOC_SINGLE_TLV("HPMIXL IN4L Volume", WM8962_HEADPHONE_MIXER_3,
1738 3, 7, 0, bypass_tlv),
1739SOC_SINGLE_TLV("HPMIXL IN4R Volume", WM8962_HEADPHONE_MIXER_3,
1740 0, 7, 0, bypass_tlv),
1741SOC_SINGLE_TLV("HPMIXL MIXINL Volume", WM8962_HEADPHONE_MIXER_3,
1742 7, 1, 1, inmix_tlv),
1743SOC_SINGLE_TLV("HPMIXL MIXINR Volume", WM8962_HEADPHONE_MIXER_3,
1744 6, 1, 1, inmix_tlv),
1745
1746SOC_SINGLE_TLV("HPMIXR IN4L Volume", WM8962_HEADPHONE_MIXER_4,
1747 3, 7, 0, bypass_tlv),
1748SOC_SINGLE_TLV("HPMIXR IN4R Volume", WM8962_HEADPHONE_MIXER_4,
1749 0, 7, 0, bypass_tlv),
1750SOC_SINGLE_TLV("HPMIXR MIXINL Volume", WM8962_HEADPHONE_MIXER_4,
1751 7, 1, 1, inmix_tlv),
1752SOC_SINGLE_TLV("HPMIXR MIXINR Volume", WM8962_HEADPHONE_MIXER_4,
1753 6, 1, 1, inmix_tlv),
1754
1755SOC_SINGLE_TLV("Speaker Boost Volume", WM8962_CLASS_D_CONTROL_2, 0, 7, 0,
1756 classd_tlv),
Mark Brown8f63aaa882011-06-07 23:14:37 +0100[diff] [blame]1757
1758SOC_SINGLE("EQ Switch", WM8962_EQ1, WM8962_EQ_ENA_SHIFT, 1, 0),
1759SOC_DOUBLE_R_TLV("EQ1 Volume", WM8962_EQ2, WM8962_EQ22,
1760 WM8962_EQL_B1_GAIN_SHIFT, 31, 0, eq_tlv),
1761SOC_DOUBLE_R_TLV("EQ2 Volume", WM8962_EQ2, WM8962_EQ22,
1762 WM8962_EQL_B2_GAIN_SHIFT, 31, 0, eq_tlv),
1763SOC_DOUBLE_R_TLV("EQ3 Volume", WM8962_EQ2, WM8962_EQ22,
1764 WM8962_EQL_B3_GAIN_SHIFT, 31, 0, eq_tlv),
1765SOC_DOUBLE_R_TLV("EQ4 Volume", WM8962_EQ3, WM8962_EQ23,
1766 WM8962_EQL_B4_GAIN_SHIFT, 31, 0, eq_tlv),
1767SOC_DOUBLE_R_TLV("EQ5 Volume", WM8962_EQ3, WM8962_EQ23,
1768 WM8962_EQL_B5_GAIN_SHIFT, 31, 0, eq_tlv),
Mark Brown6f88a4e2011-08-17 10:03:51 +0900[diff] [blame]1769
1770WM8962_DSP2_ENABLE("VSS Switch", WM8962_VSS_ENA_SHIFT),
1771WM8962_DSP2_ENABLE("HPF1 Switch", WM8962_HPF1_ENA_SHIFT),
1772WM8962_DSP2_ENABLE("HPF2 Switch", WM8962_HPF2_ENA_SHIFT),
1773WM8962_DSP2_ENABLE("HD Bass Switch", WM8962_HDBASS_ENA_SHIFT),
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]1774};
1775
1776static const struct snd_kcontrol_new wm8962_spk_mono_controls[] = {
1777SOC_SINGLE_TLV("Speaker Volume", WM8962_SPKOUTL_VOLUME, 0, 127, 0, out_tlv),
1778SOC_SINGLE_EXT("Speaker Switch", WM8962_CLASS_D_CONTROL_1, 1, 1, 1,
1779 snd_soc_get_volsw, wm8962_put_spk_sw),
1780SOC_SINGLE("Speaker ZC Switch", WM8962_SPKOUTL_VOLUME, 7, 1, 0),
1781
1782SOC_SINGLE("Speaker Mixer Switch", WM8962_SPEAKER_MIXER_3, 8, 1, 1),
1783SOC_SINGLE_TLV("Speaker Mixer IN4L Volume", WM8962_SPEAKER_MIXER_3,
1784 3, 7, 0, bypass_tlv),
1785SOC_SINGLE_TLV("Speaker Mixer IN4R Volume", WM8962_SPEAKER_MIXER_3,
1786 0, 7, 0, bypass_tlv),
1787SOC_SINGLE_TLV("Speaker Mixer MIXINL Volume", WM8962_SPEAKER_MIXER_3,
1788 7, 1, 1, inmix_tlv),
1789SOC_SINGLE_TLV("Speaker Mixer MIXINR Volume", WM8962_SPEAKER_MIXER_3,
1790 6, 1, 1, inmix_tlv),
1791SOC_SINGLE_TLV("Speaker Mixer DACL Volume", WM8962_SPEAKER_MIXER_5,
1792 7, 1, 0, inmix_tlv),
1793SOC_SINGLE_TLV("Speaker Mixer DACR Volume", WM8962_SPEAKER_MIXER_5,
1794 6, 1, 0, inmix_tlv),
1795};
1796
1797static const struct snd_kcontrol_new wm8962_spk_stereo_controls[] = {
1798SOC_DOUBLE_R_TLV("Speaker Volume", WM8962_SPKOUTL_VOLUME,
1799 WM8962_SPKOUTR_VOLUME, 0, 127, 0, out_tlv),
1800SOC_DOUBLE_EXT("Speaker Switch", WM8962_CLASS_D_CONTROL_1, 1, 0, 1, 1,
1801 snd_soc_get_volsw, wm8962_put_spk_sw),
1802SOC_DOUBLE_R("Speaker ZC Switch", WM8962_SPKOUTL_VOLUME, WM8962_SPKOUTR_VOLUME,
1803 7, 1, 0),
1804
1805SOC_DOUBLE_R("Speaker Mixer Switch", WM8962_SPEAKER_MIXER_3,
1806 WM8962_SPEAKER_MIXER_4, 8, 1, 1),
1807
1808SOC_SINGLE_TLV("SPKOUTL Mixer IN4L Volume", WM8962_SPEAKER_MIXER_3,
1809 3, 7, 0, bypass_tlv),
1810SOC_SINGLE_TLV("SPKOUTL Mixer IN4R Volume", WM8962_SPEAKER_MIXER_3,
1811 0, 7, 0, bypass_tlv),
1812SOC_SINGLE_TLV("SPKOUTL Mixer MIXINL Volume", WM8962_SPEAKER_MIXER_3,
1813 7, 1, 1, inmix_tlv),
1814SOC_SINGLE_TLV("SPKOUTL Mixer MIXINR Volume", WM8962_SPEAKER_MIXER_3,
1815 6, 1, 1, inmix_tlv),
1816SOC_SINGLE_TLV("SPKOUTL Mixer DACL Volume", WM8962_SPEAKER_MIXER_5,
1817 7, 1, 0, inmix_tlv),
1818SOC_SINGLE_TLV("SPKOUTL Mixer DACR Volume", WM8962_SPEAKER_MIXER_5,
1819 6, 1, 0, inmix_tlv),
1820
1821SOC_SINGLE_TLV("SPKOUTR Mixer IN4L Volume", WM8962_SPEAKER_MIXER_4,
1822 3, 7, 0, bypass_tlv),
1823SOC_SINGLE_TLV("SPKOUTR Mixer IN4R Volume", WM8962_SPEAKER_MIXER_4,
1824 0, 7, 0, bypass_tlv),
1825SOC_SINGLE_TLV("SPKOUTR Mixer MIXINL Volume", WM8962_SPEAKER_MIXER_4,
1826 7, 1, 1, inmix_tlv),
1827SOC_SINGLE_TLV("SPKOUTR Mixer MIXINR Volume", WM8962_SPEAKER_MIXER_4,
1828 6, 1, 1, inmix_tlv),
1829SOC_SINGLE_TLV("SPKOUTR Mixer DACL Volume", WM8962_SPEAKER_MIXER_5,
1830 5, 1, 0, inmix_tlv),
1831SOC_SINGLE_TLV("SPKOUTR Mixer DACR Volume", WM8962_SPEAKER_MIXER_5,
1832 4, 1, 0, inmix_tlv),
1833};
1834
1835static int sysclk_event(struct snd_soc_dapm_widget *w,
1836 struct snd_kcontrol *kcontrol, int event)
1837{
1838 struct snd_soc_codec *codec = w->codec;
Mark Brown649a1a02011-06-07 23:16:29 +0100[diff] [blame]1839 struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec);
1840 unsigned long timeout;
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]1841 int src;
1842 int fll;
1843
Mark Brown7b16f562011-11-01 19:32:25 +0000[diff] [blame]1844 /* Ignore attempts to run the event during startup */
1845 if (codec->dapm.bias_level == SND_SOC_BIAS_OFF)
1846 return 0;
1847
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]1848 src = snd_soc_read(codec, WM8962_CLOCKING2) & WM8962_SYSCLK_SRC_MASK;
1849
1850 switch (src) {
1851 case 0: /* MCLK */
1852 fll = 0;
1853 break;
1854 case 0x200: /* FLL */
1855 fll = 1;
1856 break;
1857 default:
1858 dev_err(codec->dev, "Unknown SYSCLK source %x\n", src);
1859 return -EINVAL;
1860 }
1861
1862 switch (event) {
1863 case SND_SOC_DAPM_PRE_PMU:
Mark Brown649a1a02011-06-07 23:16:29 +0100[diff] [blame]1864 if (fll) {
Mark Brown4df0cb22011-08-21 17:18:52 +0100[diff] [blame]1865 try_wait_for_completion(&wm8962->fll_lock);
1866
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]1867 snd_soc_update_bits(codec, WM8962_FLL_CONTROL_1,
1868 WM8962_FLL_ENA, WM8962_FLL_ENA);
Mark Brown649a1a02011-06-07 23:16:29 +0100[diff] [blame]1869
Mark Brown0b7dd6a2011-11-01 13:53:54 +0000[diff] [blame]1870 timeout = msecs_to_jiffies(5);
1871 timeout = wait_for_completion_timeout(&wm8962->fll_lock,
1872 timeout);
1873
1874 if (wm8962->irq && timeout == 0)
1875 dev_err(codec->dev,
1876 "Timed out starting FLL\n");
Mark Brown649a1a02011-06-07 23:16:29 +0100[diff] [blame]1877 }
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]1878 break;
1879
1880 case SND_SOC_DAPM_POST_PMD:
1881 if (fll)
1882 snd_soc_update_bits(codec, WM8962_FLL_CONTROL_1,
1883 WM8962_FLL_ENA, 0);
1884 break;
1885
1886 default:
1887 BUG();
1888 return -EINVAL;
1889 }
1890
1891 return 0;
1892}
1893
1894static int cp_event(struct snd_soc_dapm_widget *w,
1895 struct snd_kcontrol *kcontrol, int event)
1896{
1897 switch (event) {
1898 case SND_SOC_DAPM_POST_PMU:
1899 msleep(5);
1900 break;
1901
1902 default:
1903 BUG();
1904 return -EINVAL;
1905 }
1906
1907 return 0;
1908}
1909
1910static int hp_event(struct snd_soc_dapm_widget *w,
1911 struct snd_kcontrol *kcontrol, int event)
1912{
1913 struct snd_soc_codec *codec = w->codec;
1914 int timeout;
1915 int reg;
1916 int expected = (WM8962_DCS_STARTUP_DONE_HP1L |
1917 WM8962_DCS_STARTUP_DONE_HP1R);
1918
1919 switch (event) {
1920 case SND_SOC_DAPM_POST_PMU:
1921 snd_soc_update_bits(codec, WM8962_ANALOGUE_HP_0,
1922 WM8962_HP1L_ENA | WM8962_HP1R_ENA,
1923 WM8962_HP1L_ENA | WM8962_HP1R_ENA);
1924 udelay(20);
1925
1926 snd_soc_update_bits(codec, WM8962_ANALOGUE_HP_0,
1927 WM8962_HP1L_ENA_DLY | WM8962_HP1R_ENA_DLY,
1928 WM8962_HP1L_ENA_DLY | WM8962_HP1R_ENA_DLY);
1929
1930 /* Start the DC servo */
1931 snd_soc_update_bits(codec, WM8962_DC_SERVO_1,
1932 WM8962_HP1L_DCS_ENA | WM8962_HP1R_DCS_ENA |
1933 WM8962_HP1L_DCS_STARTUP |
1934 WM8962_HP1R_DCS_STARTUP,
1935 WM8962_HP1L_DCS_ENA | WM8962_HP1R_DCS_ENA |
1936 WM8962_HP1L_DCS_STARTUP |
1937 WM8962_HP1R_DCS_STARTUP);
1938
1939 /* Wait for it to complete, should be well under 100ms */
1940 timeout = 0;
1941 do {
1942 msleep(1);
1943 reg = snd_soc_read(codec, WM8962_DC_SERVO_6);
1944 if (reg < 0) {
1945 dev_err(codec->dev,
1946 "Failed to read DCS status: %d\n",
1947 reg);
1948 continue;
1949 }
1950 dev_dbg(codec->dev, "DCS status: %x\n", reg);
1951 } while (++timeout < 200 && (reg & expected) != expected);
1952
1953 if ((reg & expected) != expected)
1954 dev_err(codec->dev, "DC servo timed out\n");
1955 else
1956 dev_dbg(codec->dev, "DC servo complete after %dms\n",
1957 timeout);
1958
1959 snd_soc_update_bits(codec, WM8962_ANALOGUE_HP_0,
1960 WM8962_HP1L_ENA_OUTP |
1961 WM8962_HP1R_ENA_OUTP,
1962 WM8962_HP1L_ENA_OUTP |
1963 WM8962_HP1R_ENA_OUTP);
1964 udelay(20);
1965
1966 snd_soc_update_bits(codec, WM8962_ANALOGUE_HP_0,
1967 WM8962_HP1L_RMV_SHORT |
1968 WM8962_HP1R_RMV_SHORT,
1969 WM8962_HP1L_RMV_SHORT |
1970 WM8962_HP1R_RMV_SHORT);
1971 break;
1972
1973 case SND_SOC_DAPM_PRE_PMD:
1974 snd_soc_update_bits(codec, WM8962_ANALOGUE_HP_0,
1975 WM8962_HP1L_RMV_SHORT |
1976 WM8962_HP1R_RMV_SHORT, 0);
1977
1978 udelay(20);
1979
1980 snd_soc_update_bits(codec, WM8962_DC_SERVO_1,
1981 WM8962_HP1L_DCS_ENA | WM8962_HP1R_DCS_ENA |
1982 WM8962_HP1L_DCS_STARTUP |
1983 WM8962_HP1R_DCS_STARTUP,
1984 0);
1985
1986 snd_soc_update_bits(codec, WM8962_ANALOGUE_HP_0,
1987 WM8962_HP1L_ENA | WM8962_HP1R_ENA |
1988 WM8962_HP1L_ENA_DLY | WM8962_HP1R_ENA_DLY |
1989 WM8962_HP1L_ENA_OUTP |
1990 WM8962_HP1R_ENA_OUTP, 0);
1991
1992 break;
1993
1994 default:
1995 BUG();
1996 return -EINVAL;
1997
1998 }
1999
2000 return 0;
2001}
2002
2003/* VU bits for the output PGAs only take effect while the PGA is powered */
2004static int out_pga_event(struct snd_soc_dapm_widget *w,
2005 struct snd_kcontrol *kcontrol, int event)
2006{
2007 struct snd_soc_codec *codec = w->codec;
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]2008 int reg;
2009
2010 switch (w->shift) {
2011 case WM8962_HPOUTR_PGA_ENA_SHIFT:
2012 reg = WM8962_HPOUTR_VOLUME;
2013 break;
2014 case WM8962_HPOUTL_PGA_ENA_SHIFT:
2015 reg = WM8962_HPOUTL_VOLUME;
2016 break;
2017 case WM8962_SPKOUTR_PGA_ENA_SHIFT:
2018 reg = WM8962_SPKOUTR_VOLUME;
2019 break;
2020 case WM8962_SPKOUTL_PGA_ENA_SHIFT:
2021 reg = WM8962_SPKOUTL_VOLUME;
2022 break;
2023 default:
2024 BUG();
2025 return -EINVAL;
2026 }
2027
2028 switch (event) {
2029 case SND_SOC_DAPM_POST_PMU:
Mark Brown38f3f312011-09-23 21:26:33 +0100[diff] [blame]2030 return snd_soc_write(codec, reg, snd_soc_read(codec, reg));
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]2031 default:
2032 BUG();
2033 return -EINVAL;
2034 }
2035}
2036
Mark Brown6f88a4e2011-08-17 10:03:51 +0900[diff] [blame]2037static int dsp2_event(struct snd_soc_dapm_widget *w,
2038 struct snd_kcontrol *kcontrol, int event)
2039{
2040 struct snd_soc_codec *codec = w->codec;
2041 struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec);
2042
2043 switch (event) {
2044 case SND_SOC_DAPM_POST_PMU:
2045 if (wm8962->dsp2_ena)
2046 wm8962_dsp2_start(codec);
2047 break;
2048
2049 case SND_SOC_DAPM_PRE_PMD:
2050 if (wm8962->dsp2_ena)
2051 wm8962_dsp2_stop(codec);
2052 break;
2053
2054 default:
2055 BUG();
2056 return -EINVAL;
2057 }
2058
2059 return 0;
2060}
2061
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]2062static const char *st_text[] = { "None", "Right", "Left" };
2063
2064static const struct soc_enum str_enum =
2065 SOC_ENUM_SINGLE(WM8962_DAC_DSP_MIXING_1, 2, 3, st_text);
2066
2067static const struct snd_kcontrol_new str_mux =
2068 SOC_DAPM_ENUM("Right Sidetone", str_enum);
2069
2070static const struct soc_enum stl_enum =
2071 SOC_ENUM_SINGLE(WM8962_DAC_DSP_MIXING_2, 2, 3, st_text);
2072
2073static const struct snd_kcontrol_new stl_mux =
2074 SOC_DAPM_ENUM("Left Sidetone", stl_enum);
2075
2076static const char *outmux_text[] = { "DAC", "Mixer" };
2077
2078static const struct soc_enum spkoutr_enum =
2079 SOC_ENUM_SINGLE(WM8962_SPEAKER_MIXER_2, 7, 2, outmux_text);
2080
2081static const struct snd_kcontrol_new spkoutr_mux =
2082 SOC_DAPM_ENUM("SPKOUTR Mux", spkoutr_enum);
2083
2084static const struct soc_enum spkoutl_enum =
2085 SOC_ENUM_SINGLE(WM8962_SPEAKER_MIXER_1, 7, 2, outmux_text);
2086
2087static const struct snd_kcontrol_new spkoutl_mux =
2088 SOC_DAPM_ENUM("SPKOUTL Mux", spkoutl_enum);
2089
2090static const struct soc_enum hpoutr_enum =
2091 SOC_ENUM_SINGLE(WM8962_HEADPHONE_MIXER_2, 7, 2, outmux_text);
2092
2093static const struct snd_kcontrol_new hpoutr_mux =
2094 SOC_DAPM_ENUM("HPOUTR Mux", hpoutr_enum);
2095
2096static const struct soc_enum hpoutl_enum =
2097 SOC_ENUM_SINGLE(WM8962_HEADPHONE_MIXER_1, 7, 2, outmux_text);
2098
2099static const struct snd_kcontrol_new hpoutl_mux =
2100 SOC_DAPM_ENUM("HPOUTL Mux", hpoutl_enum);
2101
2102static const struct snd_kcontrol_new inpgal[] = {
2103SOC_DAPM_SINGLE("IN1L Switch", WM8962_LEFT_INPUT_PGA_CONTROL, 3, 1, 0),
2104SOC_DAPM_SINGLE("IN2L Switch", WM8962_LEFT_INPUT_PGA_CONTROL, 2, 1, 0),
2105SOC_DAPM_SINGLE("IN3L Switch", WM8962_LEFT_INPUT_PGA_CONTROL, 1, 1, 0),
2106SOC_DAPM_SINGLE("IN4L Switch", WM8962_LEFT_INPUT_PGA_CONTROL, 0, 1, 0),
2107};
2108
2109static const struct snd_kcontrol_new inpgar[] = {
2110SOC_DAPM_SINGLE("IN1R Switch", WM8962_RIGHT_INPUT_PGA_CONTROL, 3, 1, 0),
2111SOC_DAPM_SINGLE("IN2R Switch", WM8962_RIGHT_INPUT_PGA_CONTROL, 2, 1, 0),
2112SOC_DAPM_SINGLE("IN3R Switch", WM8962_RIGHT_INPUT_PGA_CONTROL, 1, 1, 0),
2113SOC_DAPM_SINGLE("IN4R Switch", WM8962_RIGHT_INPUT_PGA_CONTROL, 0, 1, 0),
2114};
2115
2116static const struct snd_kcontrol_new mixinl[] = {
2117SOC_DAPM_SINGLE("IN2L Switch", WM8962_INPUT_MIXER_CONTROL_2, 5, 1, 0),
2118SOC_DAPM_SINGLE("IN3L Switch", WM8962_INPUT_MIXER_CONTROL_2, 4, 1, 0),
2119SOC_DAPM_SINGLE("PGA Switch", WM8962_INPUT_MIXER_CONTROL_2, 3, 1, 0),
2120};
2121
2122static const struct snd_kcontrol_new mixinr[] = {
2123SOC_DAPM_SINGLE("IN2R Switch", WM8962_INPUT_MIXER_CONTROL_2, 2, 1, 0),
2124SOC_DAPM_SINGLE("IN3R Switch", WM8962_INPUT_MIXER_CONTROL_2, 1, 1, 0),
2125SOC_DAPM_SINGLE("PGA Switch", WM8962_INPUT_MIXER_CONTROL_2, 0, 1, 0),
2126};
2127
2128static const struct snd_kcontrol_new hpmixl[] = {
2129SOC_DAPM_SINGLE("DACL Switch", WM8962_HEADPHONE_MIXER_1, 5, 1, 0),
2130SOC_DAPM_SINGLE("DACR Switch", WM8962_HEADPHONE_MIXER_1, 4, 1, 0),
2131SOC_DAPM_SINGLE("MIXINL Switch", WM8962_HEADPHONE_MIXER_1, 3, 1, 0),
2132SOC_DAPM_SINGLE("MIXINR Switch", WM8962_HEADPHONE_MIXER_1, 2, 1, 0),
2133SOC_DAPM_SINGLE("IN4L Switch", WM8962_HEADPHONE_MIXER_1, 1, 1, 0),
2134SOC_DAPM_SINGLE("IN4R Switch", WM8962_HEADPHONE_MIXER_1, 0, 1, 0),
2135};
2136
2137static const struct snd_kcontrol_new hpmixr[] = {
2138SOC_DAPM_SINGLE("DACL Switch", WM8962_HEADPHONE_MIXER_2, 5, 1, 0),
2139SOC_DAPM_SINGLE("DACR Switch", WM8962_HEADPHONE_MIXER_2, 4, 1, 0),
2140SOC_DAPM_SINGLE("MIXINL Switch", WM8962_HEADPHONE_MIXER_2, 3, 1, 0),
2141SOC_DAPM_SINGLE("MIXINR Switch", WM8962_HEADPHONE_MIXER_2, 2, 1, 0),
2142SOC_DAPM_SINGLE("IN4L Switch", WM8962_HEADPHONE_MIXER_2, 1, 1, 0),
2143SOC_DAPM_SINGLE("IN4R Switch", WM8962_HEADPHONE_MIXER_2, 0, 1, 0),
2144};
2145
2146static const struct snd_kcontrol_new spkmixl[] = {
2147SOC_DAPM_SINGLE("DACL Switch", WM8962_SPEAKER_MIXER_1, 5, 1, 0),
2148SOC_DAPM_SINGLE("DACR Switch", WM8962_SPEAKER_MIXER_1, 4, 1, 0),
2149SOC_DAPM_SINGLE("MIXINL Switch", WM8962_SPEAKER_MIXER_1, 3, 1, 0),
2150SOC_DAPM_SINGLE("MIXINR Switch", WM8962_SPEAKER_MIXER_1, 2, 1, 0),
2151SOC_DAPM_SINGLE("IN4L Switch", WM8962_SPEAKER_MIXER_1, 1, 1, 0),
2152SOC_DAPM_SINGLE("IN4R Switch", WM8962_SPEAKER_MIXER_1, 0, 1, 0),
2153};
2154
2155static const struct snd_kcontrol_new spkmixr[] = {
2156SOC_DAPM_SINGLE("DACL Switch", WM8962_SPEAKER_MIXER_2, 5, 1, 0),
2157SOC_DAPM_SINGLE("DACR Switch", WM8962_SPEAKER_MIXER_2, 4, 1, 0),
2158SOC_DAPM_SINGLE("MIXINL Switch", WM8962_SPEAKER_MIXER_2, 3, 1, 0),
2159SOC_DAPM_SINGLE("MIXINR Switch", WM8962_SPEAKER_MIXER_2, 2, 1, 0),
2160SOC_DAPM_SINGLE("IN4L Switch", WM8962_SPEAKER_MIXER_2, 1, 1, 0),
2161SOC_DAPM_SINGLE("IN4R Switch", WM8962_SPEAKER_MIXER_2, 0, 1, 0),
2162};
2163
2164static const struct snd_soc_dapm_widget wm8962_dapm_widgets[] = {
2165SND_SOC_DAPM_INPUT("IN1L"),
2166SND_SOC_DAPM_INPUT("IN1R"),
2167SND_SOC_DAPM_INPUT("IN2L"),
2168SND_SOC_DAPM_INPUT("IN2R"),
2169SND_SOC_DAPM_INPUT("IN3L"),
2170SND_SOC_DAPM_INPUT("IN3R"),
2171SND_SOC_DAPM_INPUT("IN4L"),
2172SND_SOC_DAPM_INPUT("IN4R"),
Mark Brown36c6b542011-11-27 16:24:18 +0000[diff] [blame]2173SND_SOC_DAPM_SIGGEN("Beep"),
Mark Browne47ac372011-04-25 20:14:21 +0100[diff] [blame]2174SND_SOC_DAPM_INPUT("DMICDAT"),
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]2175
Mark Brown086d7f82011-09-23 16:22:48 +0100[diff] [blame]2176SND_SOC_DAPM_SUPPLY("MICBIAS", WM8962_PWR_MGMT_1, 1, 0, NULL, 0),
Mark Browna4f28c02010-09-29 13:24:35 -0700[diff] [blame]2177
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]2178SND_SOC_DAPM_SUPPLY("Class G", WM8962_CHARGE_PUMP_B, 0, 1, NULL, 0),
2179SND_SOC_DAPM_SUPPLY("SYSCLK", WM8962_CLOCKING2, 5, 0, sysclk_event,
2180 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
2181SND_SOC_DAPM_SUPPLY("Charge Pump", WM8962_CHARGE_PUMP_1, 0, 0, cp_event,
2182 SND_SOC_DAPM_POST_PMU),
2183SND_SOC_DAPM_SUPPLY("TOCLK", WM8962_ADDITIONAL_CONTROL_1, 0, 0, NULL, 0),
Mark Brown6f88a4e2011-08-17 10:03:51 +0900[diff] [blame]2184SND_SOC_DAPM_SUPPLY_S("DSP2", 1, WM8962_DSP2_POWER_MANAGEMENT,
2185 WM8962_DSP2_ENA_SHIFT, 0, dsp2_event,
2186 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
Mark Brown94b88e62011-11-04 17:48:28 +0000[diff] [blame]2187SND_SOC_DAPM_SUPPLY("TEMP_HP", WM8962_ADDITIONAL_CONTROL_4, 2, 0, NULL, 0),
2188SND_SOC_DAPM_SUPPLY("TEMP_SPK", WM8962_ADDITIONAL_CONTROL_4, 1, 0, NULL, 0),
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]2189
2190SND_SOC_DAPM_MIXER("INPGAL", WM8962_LEFT_INPUT_PGA_CONTROL, 4, 0,
2191 inpgal, ARRAY_SIZE(inpgal)),
2192SND_SOC_DAPM_MIXER("INPGAR", WM8962_RIGHT_INPUT_PGA_CONTROL, 4, 0,
2193 inpgar, ARRAY_SIZE(inpgar)),
2194SND_SOC_DAPM_MIXER("MIXINL", WM8962_PWR_MGMT_1, 5, 0,
2195 mixinl, ARRAY_SIZE(mixinl)),
2196SND_SOC_DAPM_MIXER("MIXINR", WM8962_PWR_MGMT_1, 4, 0,
2197 mixinr, ARRAY_SIZE(mixinr)),
2198
Mark Brown3f7d55a2011-09-23 16:39:31 +0100[diff] [blame]2199SND_SOC_DAPM_AIF_IN("DMIC_ENA", NULL, 0, WM8962_PWR_MGMT_1, 10, 0),
Mark Browne47ac372011-04-25 20:14:21 +0100[diff] [blame]2200
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]2201SND_SOC_DAPM_ADC("ADCL", "Capture", WM8962_PWR_MGMT_1, 3, 0),
2202SND_SOC_DAPM_ADC("ADCR", "Capture", WM8962_PWR_MGMT_1, 2, 0),
2203
2204SND_SOC_DAPM_MUX("STL", SND_SOC_NOPM, 0, 0, &stl_mux),
2205SND_SOC_DAPM_MUX("STR", SND_SOC_NOPM, 0, 0, &str_mux),
2206
2207SND_SOC_DAPM_DAC("DACL", "Playback", WM8962_PWR_MGMT_2, 8, 0),
2208SND_SOC_DAPM_DAC("DACR", "Playback", WM8962_PWR_MGMT_2, 7, 0),
2209
2210SND_SOC_DAPM_PGA("Left Bypass", SND_SOC_NOPM, 0, 0, NULL, 0),
2211SND_SOC_DAPM_PGA("Right Bypass", SND_SOC_NOPM, 0, 0, NULL, 0),
2212
2213SND_SOC_DAPM_MIXER("HPMIXL", WM8962_MIXER_ENABLES, 3, 0,
2214 hpmixl, ARRAY_SIZE(hpmixl)),
2215SND_SOC_DAPM_MIXER("HPMIXR", WM8962_MIXER_ENABLES, 2, 0,
2216 hpmixr, ARRAY_SIZE(hpmixr)),
2217
2218SND_SOC_DAPM_MUX_E("HPOUTL PGA", WM8962_PWR_MGMT_2, 6, 0, &hpoutl_mux,
2219 out_pga_event, SND_SOC_DAPM_POST_PMU),
2220SND_SOC_DAPM_MUX_E("HPOUTR PGA", WM8962_PWR_MGMT_2, 5, 0, &hpoutr_mux,
2221 out_pga_event, SND_SOC_DAPM_POST_PMU),
2222
2223SND_SOC_DAPM_PGA_E("HPOUT", SND_SOC_NOPM, 0, 0, NULL, 0, hp_event,
2224 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
2225
2226SND_SOC_DAPM_OUTPUT("HPOUTL"),
2227SND_SOC_DAPM_OUTPUT("HPOUTR"),
2228};
2229
2230static const struct snd_soc_dapm_widget wm8962_dapm_spk_mono_widgets[] = {
2231SND_SOC_DAPM_MIXER("Speaker Mixer", WM8962_MIXER_ENABLES, 1, 0,
2232 spkmixl, ARRAY_SIZE(spkmixl)),
2233SND_SOC_DAPM_MUX_E("Speaker PGA", WM8962_PWR_MGMT_2, 4, 0, &spkoutl_mux,
2234 out_pga_event, SND_SOC_DAPM_POST_PMU),
2235SND_SOC_DAPM_PGA("Speaker Output", WM8962_CLASS_D_CONTROL_1, 7, 0, NULL, 0),
2236SND_SOC_DAPM_OUTPUT("SPKOUT"),
2237};
2238
2239static const struct snd_soc_dapm_widget wm8962_dapm_spk_stereo_widgets[] = {
2240SND_SOC_DAPM_MIXER("SPKOUTL Mixer", WM8962_MIXER_ENABLES, 1, 0,
2241 spkmixl, ARRAY_SIZE(spkmixl)),
2242SND_SOC_DAPM_MIXER("SPKOUTR Mixer", WM8962_MIXER_ENABLES, 0, 0,
2243 spkmixr, ARRAY_SIZE(spkmixr)),
2244
2245SND_SOC_DAPM_MUX_E("SPKOUTL PGA", WM8962_PWR_MGMT_2, 4, 0, &spkoutl_mux,
2246 out_pga_event, SND_SOC_DAPM_POST_PMU),
2247SND_SOC_DAPM_MUX_E("SPKOUTR PGA", WM8962_PWR_MGMT_2, 3, 0, &spkoutr_mux,
2248 out_pga_event, SND_SOC_DAPM_POST_PMU),
2249
2250SND_SOC_DAPM_PGA("SPKOUTR Output", WM8962_CLASS_D_CONTROL_1, 7, 0, NULL, 0),
2251SND_SOC_DAPM_PGA("SPKOUTL Output", WM8962_CLASS_D_CONTROL_1, 6, 0, NULL, 0),
2252
2253SND_SOC_DAPM_OUTPUT("SPKOUTL"),
2254SND_SOC_DAPM_OUTPUT("SPKOUTR"),
2255};
2256
2257static const struct snd_soc_dapm_route wm8962_intercon[] = {
2258 { "INPGAL", "IN1L Switch", "IN1L" },
2259 { "INPGAL", "IN2L Switch", "IN2L" },
2260 { "INPGAL", "IN3L Switch", "IN3L" },
2261 { "INPGAL", "IN4L Switch", "IN4L" },
2262
2263 { "INPGAR", "IN1R Switch", "IN1R" },
2264 { "INPGAR", "IN2R Switch", "IN2R" },
2265 { "INPGAR", "IN3R Switch", "IN3R" },
2266 { "INPGAR", "IN4R Switch", "IN4R" },
2267
2268 { "MIXINL", "IN2L Switch", "IN2L" },
2269 { "MIXINL", "IN3L Switch", "IN3L" },
2270 { "MIXINL", "PGA Switch", "INPGAL" },
2271
2272 { "MIXINR", "IN2R Switch", "IN2R" },
2273 { "MIXINR", "IN3R Switch", "IN3R" },
2274 { "MIXINR", "PGA Switch", "INPGAR" },
2275
Mark Brown821f4202010-09-21 17:53:38 +0100[diff] [blame]2276 { "MICBIAS", NULL, "SYSCLK" },
2277
Mark Brown3f7d55a2011-09-23 16:39:31 +0100[diff] [blame]2278 { "DMIC_ENA", NULL, "DMICDAT" },
Mark Browne47ac372011-04-25 20:14:21 +0100[diff] [blame]2279
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]2280 { "ADCL", NULL, "SYSCLK" },
2281 { "ADCL", NULL, "TOCLK" },
2282 { "ADCL", NULL, "MIXINL" },
Mark Brown3f7d55a2011-09-23 16:39:31 +0100[diff] [blame]2283 { "ADCL", NULL, "DMIC_ENA" },
Mark Brown6f88a4e2011-08-17 10:03:51 +0900[diff] [blame]2284 { "ADCL", NULL, "DSP2" },
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]2285
2286 { "ADCR", NULL, "SYSCLK" },
2287 { "ADCR", NULL, "TOCLK" },
2288 { "ADCR", NULL, "MIXINR" },
Mark Brown3f7d55a2011-09-23 16:39:31 +0100[diff] [blame]2289 { "ADCR", NULL, "DMIC_ENA" },
Mark Brown6f88a4e2011-08-17 10:03:51 +0900[diff] [blame]2290 { "ADCR", NULL, "DSP2" },
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]2291
2292 { "STL", "Left", "ADCL" },
2293 { "STL", "Right", "ADCR" },
2294
2295 { "STR", "Left", "ADCL" },
2296 { "STR", "Right", "ADCR" },
2297
2298 { "DACL", NULL, "SYSCLK" },
2299 { "DACL", NULL, "TOCLK" },
2300 { "DACL", NULL, "Beep" },
2301 { "DACL", NULL, "STL" },
Mark Brown6f88a4e2011-08-17 10:03:51 +0900[diff] [blame]2302 { "DACL", NULL, "DSP2" },
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]2303
2304 { "DACR", NULL, "SYSCLK" },
2305 { "DACR", NULL, "TOCLK" },
2306 { "DACR", NULL, "Beep" },
2307 { "DACR", NULL, "STR" },
Mark Brown6f88a4e2011-08-17 10:03:51 +0900[diff] [blame]2308 { "DACR", NULL, "DSP2" },
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]2309
2310 { "HPMIXL", "IN4L Switch", "IN4L" },
2311 { "HPMIXL", "IN4R Switch", "IN4R" },
2312 { "HPMIXL", "DACL Switch", "DACL" },
2313 { "HPMIXL", "DACR Switch", "DACR" },
2314 { "HPMIXL", "MIXINL Switch", "MIXINL" },
2315 { "HPMIXL", "MIXINR Switch", "MIXINR" },
2316
2317 { "HPMIXR", "IN4L Switch", "IN4L" },
2318 { "HPMIXR", "IN4R Switch", "IN4R" },
2319 { "HPMIXR", "DACL Switch", "DACL" },
2320 { "HPMIXR", "DACR Switch", "DACR" },
2321 { "HPMIXR", "MIXINL Switch", "MIXINL" },
2322 { "HPMIXR", "MIXINR Switch", "MIXINR" },
2323
2324 { "Left Bypass", NULL, "HPMIXL" },
2325 { "Left Bypass", NULL, "Class G" },
2326
2327 { "Right Bypass", NULL, "HPMIXR" },
2328 { "Right Bypass", NULL, "Class G" },
2329
2330 { "HPOUTL PGA", "Mixer", "Left Bypass" },
2331 { "HPOUTL PGA", "DAC", "DACL" },
2332
2333 { "HPOUTR PGA", "Mixer", "Right Bypass" },
2334 { "HPOUTR PGA", "DAC", "DACR" },
2335
2336 { "HPOUT", NULL, "HPOUTL PGA" },
2337 { "HPOUT", NULL, "HPOUTR PGA" },
2338 { "HPOUT", NULL, "Charge Pump" },
2339 { "HPOUT", NULL, "SYSCLK" },
2340 { "HPOUT", NULL, "TOCLK" },
2341
2342 { "HPOUTL", NULL, "HPOUT" },
2343 { "HPOUTR", NULL, "HPOUT" },
Mark Brown94b88e62011-11-04 17:48:28 +0000[diff] [blame]2344
2345 { "HPOUTL", NULL, "TEMP_HP" },
2346 { "HPOUTR", NULL, "TEMP_HP" },
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]2347};
2348
2349static const struct snd_soc_dapm_route wm8962_spk_mono_intercon[] = {
2350 { "Speaker Mixer", "IN4L Switch", "IN4L" },
2351 { "Speaker Mixer", "IN4R Switch", "IN4R" },
2352 { "Speaker Mixer", "DACL Switch", "DACL" },
2353 { "Speaker Mixer", "DACR Switch", "DACR" },
2354 { "Speaker Mixer", "MIXINL Switch", "MIXINL" },
2355 { "Speaker Mixer", "MIXINR Switch", "MIXINR" },
2356
2357 { "Speaker PGA", "Mixer", "Speaker Mixer" },
2358 { "Speaker PGA", "DAC", "DACL" },
2359
2360 { "Speaker Output", NULL, "Speaker PGA" },
2361 { "Speaker Output", NULL, "SYSCLK" },
2362 { "Speaker Output", NULL, "TOCLK" },
Mark Brown94b88e62011-11-04 17:48:28 +0000[diff] [blame]2363 { "Speaker Output", NULL, "TEMP_SPK" },
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]2364
2365 { "SPKOUT", NULL, "Speaker Output" },
2366};
2367
2368static const struct snd_soc_dapm_route wm8962_spk_stereo_intercon[] = {
2369 { "SPKOUTL Mixer", "IN4L Switch", "IN4L" },
2370 { "SPKOUTL Mixer", "IN4R Switch", "IN4R" },
2371 { "SPKOUTL Mixer", "DACL Switch", "DACL" },
2372 { "SPKOUTL Mixer", "DACR Switch", "DACR" },
2373 { "SPKOUTL Mixer", "MIXINL Switch", "MIXINL" },
2374 { "SPKOUTL Mixer", "MIXINR Switch", "MIXINR" },
2375
2376 { "SPKOUTR Mixer", "IN4L Switch", "IN4L" },
2377 { "SPKOUTR Mixer", "IN4R Switch", "IN4R" },
2378 { "SPKOUTR Mixer", "DACL Switch", "DACL" },
2379 { "SPKOUTR Mixer", "DACR Switch", "DACR" },
2380 { "SPKOUTR Mixer", "MIXINL Switch", "MIXINL" },
2381 { "SPKOUTR Mixer", "MIXINR Switch", "MIXINR" },
2382
2383 { "SPKOUTL PGA", "Mixer", "SPKOUTL Mixer" },
2384 { "SPKOUTL PGA", "DAC", "DACL" },
2385
2386 { "SPKOUTR PGA", "Mixer", "SPKOUTR Mixer" },
2387 { "SPKOUTR PGA", "DAC", "DACR" },
2388
2389 { "SPKOUTL Output", NULL, "SPKOUTL PGA" },
2390 { "SPKOUTL Output", NULL, "SYSCLK" },
2391 { "SPKOUTL Output", NULL, "TOCLK" },
Mark Brown94b88e62011-11-04 17:48:28 +0000[diff] [blame]2392 { "SPKOUTL Output", NULL, "TEMP_SPK" },
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]2393
2394 { "SPKOUTR Output", NULL, "SPKOUTR PGA" },
2395 { "SPKOUTR Output", NULL, "SYSCLK" },
2396 { "SPKOUTR Output", NULL, "TOCLK" },
Mark Brown94b88e62011-11-04 17:48:28 +0000[diff] [blame]2397 { "SPKOUTR Output", NULL, "TEMP_SPK" },
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]2398
2399 { "SPKOUTL", NULL, "SPKOUTL Output" },
2400 { "SPKOUTR", NULL, "SPKOUTR Output" },
2401};
2402
2403static int wm8962_add_widgets(struct snd_soc_codec *codec)
2404{
2405 struct wm8962_pdata *pdata = dev_get_platdata(codec->dev);
Liam Girdwoodce6120c2010-11-05 15:53:46 +0200[diff] [blame]2406 struct snd_soc_dapm_context *dapm = &codec->dapm;
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]2407
2408 snd_soc_add_controls(codec, wm8962_snd_controls,
2409 ARRAY_SIZE(wm8962_snd_controls));
2410 if (pdata && pdata->spk_mono)
2411 snd_soc_add_controls(codec, wm8962_spk_mono_controls,
2412 ARRAY_SIZE(wm8962_spk_mono_controls));
2413 else
2414 snd_soc_add_controls(codec, wm8962_spk_stereo_controls,
2415 ARRAY_SIZE(wm8962_spk_stereo_controls));
2416
2417
Liam Girdwoodce6120c2010-11-05 15:53:46 +0200[diff] [blame]2418 snd_soc_dapm_new_controls(dapm, wm8962_dapm_widgets,
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]2419 ARRAY_SIZE(wm8962_dapm_widgets));
2420 if (pdata && pdata->spk_mono)
Liam Girdwoodce6120c2010-11-05 15:53:46 +0200[diff] [blame]2421 snd_soc_dapm_new_controls(dapm, wm8962_dapm_spk_mono_widgets,
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]2422 ARRAY_SIZE(wm8962_dapm_spk_mono_widgets));
2423 else
Liam Girdwoodce6120c2010-11-05 15:53:46 +0200[diff] [blame]2424 snd_soc_dapm_new_controls(dapm, wm8962_dapm_spk_stereo_widgets,
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]2425 ARRAY_SIZE(wm8962_dapm_spk_stereo_widgets));
2426
Liam Girdwoodce6120c2010-11-05 15:53:46 +0200[diff] [blame]2427 snd_soc_dapm_add_routes(dapm, wm8962_intercon,
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]2428 ARRAY_SIZE(wm8962_intercon));
2429 if (pdata && pdata->spk_mono)
Liam Girdwoodce6120c2010-11-05 15:53:46 +0200[diff] [blame]2430 snd_soc_dapm_add_routes(dapm, wm8962_spk_mono_intercon,
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]2431 ARRAY_SIZE(wm8962_spk_mono_intercon));
2432 else
Liam Girdwoodce6120c2010-11-05 15:53:46 +0200[diff] [blame]2433 snd_soc_dapm_add_routes(dapm, wm8962_spk_stereo_intercon,
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]2434 ARRAY_SIZE(wm8962_spk_stereo_intercon));
2435
2436
Liam Girdwoodce6120c2010-11-05 15:53:46 +0200[diff] [blame]2437 snd_soc_dapm_disable_pin(dapm, "Beep");
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]2438
2439 return 0;
2440}
2441
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]2442/* -1 for reserved values */
2443static const int bclk_divs[] = {
2444 1, -1, 2, 3, 4, -1, 6, 8, -1, 12, 16, 24, -1, 32, 32, 32
2445};
2446
Mark Brown417ceff2011-06-08 14:44:06 +0100[diff] [blame]2447static const int sysclk_rates[] = {
2448 64, 128, 192, 256, 384, 512, 768, 1024, 1408, 1536,
2449};
2450
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]2451static void wm8962_configure_bclk(struct snd_soc_codec *codec)
2452{
2453 struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec);
2454 int dspclk, i;
2455 int clocking2 = 0;
Mark Brown417ceff2011-06-08 14:44:06 +0100[diff] [blame]2456 int clocking4 = 0;
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]2457 int aif2 = 0;
2458
Mark Brown417ceff2011-06-08 14:44:06 +0100[diff] [blame]2459 if (!wm8962->sysclk_rate) {
2460 dev_dbg(codec->dev, "No SYSCLK configured\n");
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]2461 return;
2462 }
2463
Mark Brown417ceff2011-06-08 14:44:06 +0100[diff] [blame]2464 if (!wm8962->bclk || !wm8962->lrclk) {
2465 dev_dbg(codec->dev, "No audio clocks configured\n");
2466 return;
2467 }
2468
2469 for (i = 0; i < ARRAY_SIZE(sysclk_rates); i++) {
2470 if (sysclk_rates[i] == wm8962->sysclk_rate / wm8962->lrclk) {
2471 clocking4 |= i << WM8962_SYSCLK_RATE_SHIFT;
2472 break;
2473 }
2474 }
2475
2476 if (i == ARRAY_SIZE(sysclk_rates)) {
2477 dev_err(codec->dev, "Unsupported sysclk ratio %d\n",
2478 wm8962->sysclk_rate / wm8962->lrclk);
2479 return;
2480 }
2481
2482 snd_soc_update_bits(codec, WM8962_CLOCKING_4,
2483 WM8962_SYSCLK_RATE_MASK, clocking4);
2484
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]2485 dspclk = snd_soc_read(codec, WM8962_CLOCKING1);
2486 if (dspclk < 0) {
2487 dev_err(codec->dev, "Failed to read DSPCLK: %d\n", dspclk);
2488 return;
2489 }
2490
2491 dspclk = (dspclk & WM8962_DSPCLK_DIV_MASK) >> WM8962_DSPCLK_DIV_SHIFT;
2492 switch (dspclk) {
2493 case 0:
2494 dspclk = wm8962->sysclk_rate;
2495 break;
2496 case 1:
2497 dspclk = wm8962->sysclk_rate / 2;
2498 break;
2499 case 2:
2500 dspclk = wm8962->sysclk_rate / 4;
2501 break;
2502 default:
2503 dev_warn(codec->dev, "Unknown DSPCLK divisor read back\n");
2504 dspclk = wm8962->sysclk;
2505 }
2506
2507 dev_dbg(codec->dev, "DSPCLK is %dHz, BCLK %d\n", dspclk, wm8962->bclk);
2508
2509 /* We're expecting an exact match */
2510 for (i = 0; i < ARRAY_SIZE(bclk_divs); i++) {
2511 if (bclk_divs[i] < 0)
2512 continue;
2513
2514 if (dspclk / bclk_divs[i] == wm8962->bclk) {
2515 dev_dbg(codec->dev, "Selected BCLK_DIV %d for %dHz\n",
2516 bclk_divs[i], wm8962->bclk);
2517 clocking2 |= i;
2518 break;
2519 }
2520 }
2521 if (i == ARRAY_SIZE(bclk_divs)) {
2522 dev_err(codec->dev, "Unsupported BCLK ratio %d\n",
2523 dspclk / wm8962->bclk);
2524 return;
2525 }
2526
2527 aif2 |= wm8962->bclk / wm8962->lrclk;
2528 dev_dbg(codec->dev, "Selected LRCLK divisor %d for %dHz\n",
2529 wm8962->bclk / wm8962->lrclk, wm8962->lrclk);
2530
2531 snd_soc_update_bits(codec, WM8962_CLOCKING2,
2532 WM8962_BCLK_DIV_MASK, clocking2);
2533 snd_soc_update_bits(codec, WM8962_AUDIO_INTERFACE_2,
2534 WM8962_AIF_RATE_MASK, aif2);
2535}
2536
2537static int wm8962_set_bias_level(struct snd_soc_codec *codec,
2538 enum snd_soc_bias_level level)
2539{
2540 struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec);
2541 int ret;
2542
Liam Girdwoodce6120c2010-11-05 15:53:46 +0200[diff] [blame]2543 if (level == codec->dapm.bias_level)
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]2544 return 0;
2545
2546 switch (level) {
2547 case SND_SOC_BIAS_ON:
2548 break;
2549
2550 case SND_SOC_BIAS_PREPARE:
2551 /* VMID 2*50k */
2552 snd_soc_update_bits(codec, WM8962_PWR_MGMT_1,
2553 WM8962_VMID_SEL_MASK, 0x80);
Mark Brown417ceff2011-06-08 14:44:06 +0100[diff] [blame]2554
2555 wm8962_configure_bclk(codec);
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]2556 break;
2557
2558 case SND_SOC_BIAS_STANDBY:
Liam Girdwoodce6120c2010-11-05 15:53:46 +0200[diff] [blame]2559 if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) {
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]2560 ret = regulator_bulk_enable(ARRAY_SIZE(wm8962->supplies),
2561 wm8962->supplies);
2562 if (ret != 0) {
2563 dev_err(codec->dev,
2564 "Failed to enable supplies: %d\n",
2565 ret);
2566 return ret;
2567 }
2568
Mark Brown7b16f562011-11-01 19:32:25 +0000[diff] [blame]2569 regcache_cache_only(wm8962->regmap, false);
2570 regcache_sync(wm8962->regmap);
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]2571
2572 snd_soc_update_bits(codec, WM8962_ANTI_POP,
2573 WM8962_STARTUP_BIAS_ENA |
2574 WM8962_VMID_BUF_ENA,
2575 WM8962_STARTUP_BIAS_ENA |
2576 WM8962_VMID_BUF_ENA);
2577
2578 /* Bias enable at 2*50k for ramp */
2579 snd_soc_update_bits(codec, WM8962_PWR_MGMT_1,
2580 WM8962_VMID_SEL_MASK |
2581 WM8962_BIAS_ENA,
2582 WM8962_BIAS_ENA | 0x180);
2583
2584 msleep(5);
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]2585 }
2586
2587 /* VMID 2*250k */
2588 snd_soc_update_bits(codec, WM8962_PWR_MGMT_1,
2589 WM8962_VMID_SEL_MASK, 0x100);
2590 break;
2591
2592 case SND_SOC_BIAS_OFF:
2593 snd_soc_update_bits(codec, WM8962_PWR_MGMT_1,
2594 WM8962_VMID_SEL_MASK | WM8962_BIAS_ENA, 0);
2595
2596 snd_soc_update_bits(codec, WM8962_ANTI_POP,
2597 WM8962_STARTUP_BIAS_ENA |
2598 WM8962_VMID_BUF_ENA, 0);
2599
2600 regulator_bulk_disable(ARRAY_SIZE(wm8962->supplies),
2601 wm8962->supplies);
2602 break;
2603 }
Liam Girdwoodce6120c2010-11-05 15:53:46 +0200[diff] [blame]2604 codec->dapm.bias_level = level;
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]2605 return 0;
2606}
2607
2608static const struct {
2609 int rate;
2610 int reg;
2611} sr_vals[] = {
2612 { 48000, 0 },
2613 { 44100, 0 },
2614 { 32000, 1 },
2615 { 22050, 2 },
2616 { 24000, 2 },
2617 { 16000, 3 },
2618 { 11025, 4 },
2619 { 12000, 4 },
2620 { 8000, 5 },
2621 { 88200, 6 },
2622 { 96000, 6 },
2623};
2624
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]2625static int wm8962_hw_params(struct snd_pcm_substream *substream,
2626 struct snd_pcm_hw_params *params,
2627 struct snd_soc_dai *dai)
2628{
2629 struct snd_soc_pcm_runtime *rtd = substream->private_data;
Mark Brown54d8d0a2010-08-12 15:02:11 +0100[diff] [blame]2630 struct snd_soc_codec *codec = rtd->codec;
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]2631 struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec);
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]2632 int i;
2633 int aif0 = 0;
2634 int adctl3 = 0;
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]2635
2636 wm8962->bclk = snd_soc_params_to_bclk(params);
2637 wm8962->lrclk = params_rate(params);
2638
2639 for (i = 0; i < ARRAY_SIZE(sr_vals); i++) {
Mark Brown417ceff2011-06-08 14:44:06 +0100[diff] [blame]2640 if (sr_vals[i].rate == wm8962->lrclk) {
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]2641 adctl3 |= sr_vals[i].reg;
2642 break;
2643 }
2644 }
2645 if (i == ARRAY_SIZE(sr_vals)) {
Mark Brown417ceff2011-06-08 14:44:06 +0100[diff] [blame]2646 dev_err(codec->dev, "Unsupported rate %dHz\n", wm8962->lrclk);
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]2647 return -EINVAL;
2648 }
2649
Mark Brown417ceff2011-06-08 14:44:06 +0100[diff] [blame]2650 if (wm8962->lrclk % 8000 == 0)
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]2651 adctl3 |= WM8962_SAMPLE_RATE_INT_MODE;
2652
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]2653 switch (params_format(params)) {
2654 case SNDRV_PCM_FORMAT_S16_LE:
2655 break;
2656 case SNDRV_PCM_FORMAT_S20_3LE:
2657 aif0 |= 0x40;
2658 break;
2659 case SNDRV_PCM_FORMAT_S24_LE:
2660 aif0 |= 0x80;
2661 break;
2662 case SNDRV_PCM_FORMAT_S32_LE:
2663 aif0 |= 0xc0;
2664 break;
2665 default:
2666 return -EINVAL;
2667 }
2668
2669 snd_soc_update_bits(codec, WM8962_AUDIO_INTERFACE_0,
2670 WM8962_WL_MASK, aif0);
2671 snd_soc_update_bits(codec, WM8962_ADDITIONAL_CONTROL_3,
2672 WM8962_SAMPLE_RATE_INT_MODE |
2673 WM8962_SAMPLE_RATE_MASK, adctl3);
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]2674
2675 wm8962_configure_bclk(codec);
2676
2677 return 0;
2678}
2679
2680static int wm8962_set_dai_sysclk(struct snd_soc_dai *dai, int clk_id,
2681 unsigned int freq, int dir)
2682{
2683 struct snd_soc_codec *codec = dai->codec;
2684 struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec);
2685 int src;
2686
2687 switch (clk_id) {
2688 case WM8962_SYSCLK_MCLK:
2689 wm8962->sysclk = WM8962_SYSCLK_MCLK;
2690 src = 0;
2691 break;
2692 case WM8962_SYSCLK_FLL:
2693 wm8962->sysclk = WM8962_SYSCLK_FLL;
2694 src = 1 << WM8962_SYSCLK_SRC_SHIFT;
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]2695 break;
2696 default:
2697 return -EINVAL;
2698 }
2699
2700 snd_soc_update_bits(codec, WM8962_CLOCKING2, WM8962_SYSCLK_SRC_MASK,
2701 src);
2702
2703 wm8962->sysclk_rate = freq;
2704
2705 return 0;
2706}
2707
2708static int wm8962_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
2709{
2710 struct snd_soc_codec *codec = dai->codec;
2711 int aif0 = 0;
2712
2713 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]2714 case SND_SOC_DAIFMT_DSP_B:
Susan Gaofbc7c622011-09-29 11:08:18 +0100[diff] [blame]2715 aif0 |= WM8962_LRCLK_INV | 3;
2716 case SND_SOC_DAIFMT_DSP_A:
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]2717 aif0 |= 3;
2718
2719 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
2720 case SND_SOC_DAIFMT_NB_NF:
2721 case SND_SOC_DAIFMT_IB_NF:
2722 break;
2723 default:
2724 return -EINVAL;
2725 }
2726 break;
2727
2728 case SND_SOC_DAIFMT_RIGHT_J:
2729 break;
2730 case SND_SOC_DAIFMT_LEFT_J:
2731 aif0 |= 1;
2732 break;
2733 case SND_SOC_DAIFMT_I2S:
2734 aif0 |= 2;
2735 break;
2736 default:
2737 return -EINVAL;
2738 }
2739
2740 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
2741 case SND_SOC_DAIFMT_NB_NF:
2742 break;
2743 case SND_SOC_DAIFMT_IB_NF:
2744 aif0 |= WM8962_BCLK_INV;
2745 break;
2746 case SND_SOC_DAIFMT_NB_IF:
2747 aif0 |= WM8962_LRCLK_INV;
2748 break;
2749 case SND_SOC_DAIFMT_IB_IF:
2750 aif0 |= WM8962_BCLK_INV | WM8962_LRCLK_INV;
2751 break;
2752 default:
2753 return -EINVAL;
2754 }
2755
2756 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
2757 case SND_SOC_DAIFMT_CBM_CFM:
2758 aif0 |= WM8962_MSTR;
2759 break;
2760 case SND_SOC_DAIFMT_CBS_CFS:
2761 break;
2762 default:
2763 return -EINVAL;
2764 }
2765
2766 snd_soc_update_bits(codec, WM8962_AUDIO_INTERFACE_0,
2767 WM8962_FMT_MASK | WM8962_BCLK_INV | WM8962_MSTR |
2768 WM8962_LRCLK_INV, aif0);
2769
2770 return 0;
2771}
2772
2773struct _fll_div {
2774 u16 fll_fratio;
2775 u16 fll_outdiv;
2776 u16 fll_refclk_div;
2777 u16 n;
2778 u16 theta;
2779 u16 lambda;
2780};
2781
2782/* The size in bits of the FLL divide multiplied by 10
2783 * to allow rounding later */
2784#define FIXED_FLL_SIZE ((1 << 16) * 10)
2785
2786static struct {
2787 unsigned int min;
2788 unsigned int max;
2789 u16 fll_fratio;
2790 int ratio;
2791} fll_fratios[] = {
2792 { 0, 64000, 4, 16 },
2793 { 64000, 128000, 3, 8 },
2794 { 128000, 256000, 2, 4 },
2795 { 256000, 1000000, 1, 2 },
2796 { 1000000, 13500000, 0, 1 },
2797};
2798
2799static int fll_factors(struct _fll_div *fll_div, unsigned int Fref,
2800 unsigned int Fout)
2801{
2802 unsigned int target;
2803 unsigned int div;
2804 unsigned int fratio, gcd_fll;
2805 int i;
2806
2807 /* Fref must be <=13.5MHz */
2808 div = 1;
2809 fll_div->fll_refclk_div = 0;
2810 while ((Fref / div) > 13500000) {
2811 div *= 2;
2812 fll_div->fll_refclk_div++;
2813
2814 if (div > 4) {
2815 pr_err("Can't scale %dMHz input down to <=13.5MHz\n",
2816 Fref);
2817 return -EINVAL;
2818 }
2819 }
2820
2821 pr_debug("FLL Fref=%u Fout=%u\n", Fref, Fout);
2822
2823 /* Apply the division for our remaining calculations */
2824 Fref /= div;
2825
2826 /* Fvco should be 90-100MHz; don't check the upper bound */
2827 div = 2;
2828 while (Fout * div < 90000000) {
2829 div++;
2830 if (div > 64) {
2831 pr_err("Unable to find FLL_OUTDIV for Fout=%uHz\n",
2832 Fout);
2833 return -EINVAL;
2834 }
2835 }
2836 target = Fout * div;
2837 fll_div->fll_outdiv = div - 1;
2838
2839 pr_debug("FLL Fvco=%dHz\n", target);
2840
Lucas De Marchi25985ed2011-03-30 22:57:33 -0300[diff] [blame]2841 /* Find an appropriate FLL_FRATIO and factor it out of the target */
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]2842 for (i = 0; i < ARRAY_SIZE(fll_fratios); i++) {
2843 if (fll_fratios[i].min <= Fref && Fref <= fll_fratios[i].max) {
2844 fll_div->fll_fratio = fll_fratios[i].fll_fratio;
2845 fratio = fll_fratios[i].ratio;
2846 break;
2847 }
2848 }
2849 if (i == ARRAY_SIZE(fll_fratios)) {
2850 pr_err("Unable to find FLL_FRATIO for Fref=%uHz\n", Fref);
2851 return -EINVAL;
2852 }
2853
2854 fll_div->n = target / (fratio * Fref);
2855
2856 if (target % Fref == 0) {
2857 fll_div->theta = 0;
2858 fll_div->lambda = 0;
2859 } else {
2860 gcd_fll = gcd(target, fratio * Fref);
2861
2862 fll_div->theta = (target - (fll_div->n * fratio * Fref))
2863 / gcd_fll;
2864 fll_div->lambda = (fratio * Fref) / gcd_fll;
2865 }
2866
2867 pr_debug("FLL N=%x THETA=%x LAMBDA=%x\n",
2868 fll_div->n, fll_div->theta, fll_div->lambda);
2869 pr_debug("FLL_FRATIO=%x FLL_OUTDIV=%x FLL_REFCLK_DIV=%x\n",
2870 fll_div->fll_fratio, fll_div->fll_outdiv,
2871 fll_div->fll_refclk_div);
2872
2873 return 0;
2874}
2875
Mark Brown92a43522011-04-25 18:44:01 +0100[diff] [blame]2876static int wm8962_set_fll(struct snd_soc_codec *codec, int fll_id, int source,
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]2877 unsigned int Fref, unsigned int Fout)
2878{
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]2879 struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec);
2880 struct _fll_div fll_div;
Mark Brown3b8a6d82011-04-25 17:53:43 +0100[diff] [blame]2881 unsigned long timeout;
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]2882 int ret;
Mark Brown61371122010-09-27 17:20:11 -0700[diff] [blame]2883 int fll1 = snd_soc_read(codec, WM8962_FLL_CONTROL_1) & WM8962_FLL_ENA;
Mark Brown2a761cd2011-11-01 15:19:23 +0000[diff] [blame]2884 int sysclk = snd_soc_read(codec, WM8962_CLOCKING2) & WM8962_SYSCLK_ENA;
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]2885
2886 /* Any change? */
2887 if (source == wm8962->fll_src && Fref == wm8962->fll_fref &&
2888 Fout == wm8962->fll_fout)
2889 return 0;
2890
2891 if (Fout == 0) {
2892 dev_dbg(codec->dev, "FLL disabled\n");
2893
2894 wm8962->fll_fref = 0;
2895 wm8962->fll_fout = 0;
2896
2897 snd_soc_update_bits(codec, WM8962_FLL_CONTROL_1,
2898 WM8962_FLL_ENA, 0);
2899
2900 return 0;
2901 }
2902
2903 ret = fll_factors(&fll_div, Fref, Fout);
2904 if (ret != 0)
2905 return ret;
2906
2907 switch (fll_id) {
2908 case WM8962_FLL_MCLK:
2909 case WM8962_FLL_BCLK:
2910 case WM8962_FLL_OSC:
2911 fll1 |= (fll_id - 1) << WM8962_FLL_REFCLK_SRC_SHIFT;
2912 break;
2913 case WM8962_FLL_INT:
2914 snd_soc_update_bits(codec, WM8962_FLL_CONTROL_1,
2915 WM8962_FLL_OSC_ENA, WM8962_FLL_OSC_ENA);
2916 snd_soc_update_bits(codec, WM8962_FLL_CONTROL_5,
2917 WM8962_FLL_FRC_NCO, WM8962_FLL_FRC_NCO);
2918 break;
2919 default:
2920 dev_err(codec->dev, "Unknown FLL source %d\n", ret);
2921 return -EINVAL;
2922 }
2923
2924 if (fll_div.theta || fll_div.lambda)
2925 fll1 |= WM8962_FLL_FRAC;
2926
2927 /* Stop the FLL while we reconfigure */
2928 snd_soc_update_bits(codec, WM8962_FLL_CONTROL_1, WM8962_FLL_ENA, 0);
2929
2930 snd_soc_update_bits(codec, WM8962_FLL_CONTROL_2,
2931 WM8962_FLL_OUTDIV_MASK |
2932 WM8962_FLL_REFCLK_DIV_MASK,
2933 (fll_div.fll_outdiv << WM8962_FLL_OUTDIV_SHIFT) |
2934 (fll_div.fll_refclk_div));
2935
2936 snd_soc_update_bits(codec, WM8962_FLL_CONTROL_3,
2937 WM8962_FLL_FRATIO_MASK, fll_div.fll_fratio);
2938
2939 snd_soc_write(codec, WM8962_FLL_CONTROL_6, fll_div.theta);
2940 snd_soc_write(codec, WM8962_FLL_CONTROL_7, fll_div.lambda);
2941 snd_soc_write(codec, WM8962_FLL_CONTROL_8, fll_div.n);
2942
Mark Brown4df0cb22011-08-21 17:18:52 +0100[diff] [blame]2943 try_wait_for_completion(&wm8962->fll_lock);
2944
Mark Brown2a761cd2011-11-01 15:19:23 +0000[diff] [blame]2945 if (sysclk)
2946 fll1 |= WM8962_FLL_ENA;
2947
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]2948 snd_soc_update_bits(codec, WM8962_FLL_CONTROL_1,
2949 WM8962_FLL_FRAC | WM8962_FLL_REFCLK_SRC_MASK |
2950 WM8962_FLL_ENA, fll1);
2951
2952 dev_dbg(codec->dev, "FLL configured for %dHz->%dHz\n", Fref, Fout);
2953
Mark Brown649a1a02011-06-07 23:16:29 +0100[diff] [blame]2954 ret = 0;
Mark Brown3b8a6d82011-04-25 17:53:43 +0100[diff] [blame]2955
Mark Brown649a1a02011-06-07 23:16:29 +0100[diff] [blame]2956 if (fll1 & WM8962_FLL_ENA) {
2957 /* This should be a massive overestimate but go even
2958 * higher if we'll error out
2959 */
2960 if (wm8962->irq)
2961 timeout = msecs_to_jiffies(5);
2962 else
2963 timeout = msecs_to_jiffies(1);
2964
2965 timeout = wait_for_completion_timeout(&wm8962->fll_lock,
2966 timeout);
2967
2968 if (timeout == 0 && wm8962->irq) {
2969 dev_err(codec->dev, "FLL lock timed out");
2970 ret = -ETIMEDOUT;
2971 }
2972 }
Mark Brown3b8a6d82011-04-25 17:53:43 +0100[diff] [blame]2973
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]2974 wm8962->fll_fref = Fref;
2975 wm8962->fll_fout = Fout;
2976 wm8962->fll_src = source;
2977
Mark Brown649a1a02011-06-07 23:16:29 +0100[diff] [blame]2978 return ret;
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]2979}
2980
2981static int wm8962_mute(struct snd_soc_dai *dai, int mute)
2982{
2983 struct snd_soc_codec *codec = dai->codec;
2984 int val;
2985
2986 if (mute)
2987 val = WM8962_DAC_MUTE;
2988 else
2989 val = 0;
2990
2991 return snd_soc_update_bits(codec, WM8962_ADC_DAC_CONTROL_1,
2992 WM8962_DAC_MUTE, val);
2993}
2994
2995#define WM8962_RATES SNDRV_PCM_RATE_8000_96000
2996
2997#define WM8962_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\
2998 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
2999
Lars-Peter Clausen85e76522011-11-23 11:40:40 +0100[diff] [blame]3000static const struct snd_soc_dai_ops wm8962_dai_ops = {
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]3001 .hw_params = wm8962_hw_params,
3002 .set_sysclk = wm8962_set_dai_sysclk,
3003 .set_fmt = wm8962_set_dai_fmt,
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]3004 .digital_mute = wm8962_mute,
3005};
3006
Mark Brown54d8d0a2010-08-12 15:02:11 +0100[diff] [blame]3007static struct snd_soc_dai_driver wm8962_dai = {
3008 .name = "wm8962",
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]3009 .playback = {
3010 .stream_name = "Playback",
3011 .channels_min = 2,
3012 .channels_max = 2,
3013 .rates = WM8962_RATES,
3014 .formats = WM8962_FORMATS,
3015 },
3016 .capture = {
3017 .stream_name = "Capture",
3018 .channels_min = 2,
3019 .channels_max = 2,
3020 .rates = WM8962_RATES,
3021 .formats = WM8962_FORMATS,
3022 },
3023 .ops = &wm8962_dai_ops,
3024 .symmetric_rates = 1,
3025};
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]3026
Mark Brown77113082010-09-30 15:37:53 -0700[diff] [blame]3027static void wm8962_mic_work(struct work_struct *work)
3028{
3029 struct wm8962_priv *wm8962 = container_of(work,
3030 struct wm8962_priv,
3031 mic_work.work);
3032 struct snd_soc_codec *codec = wm8962->codec;
3033 int status = 0;
3034 int irq_pol = 0;
3035 int reg;
3036
3037 reg = snd_soc_read(codec, WM8962_ADDITIONAL_CONTROL_4);
3038
3039 if (reg & WM8962_MICDET_STS) {
3040 status |= SND_JACK_MICROPHONE;
3041 irq_pol |= WM8962_MICD_IRQ_POL;
3042 }
3043
3044 if (reg & WM8962_MICSHORT_STS) {
3045 status |= SND_JACK_BTN_0;
3046 irq_pol |= WM8962_MICSCD_IRQ_POL;
3047 }
3048
3049 snd_soc_jack_report(wm8962->jack, status,
3050 SND_JACK_MICROPHONE | SND_JACK_BTN_0);
3051
3052 snd_soc_update_bits(codec, WM8962_MICINT_SOURCE_POL,
3053 WM8962_MICSCD_IRQ_POL |
3054 WM8962_MICD_IRQ_POL, irq_pol);
3055}
3056
Mark Brown45e65502010-09-28 16:01:20 -0700[diff] [blame]3057static irqreturn_t wm8962_irq(int irq, void *data)
3058{
3059 struct snd_soc_codec *codec = data;
Mark Brown77113082010-09-30 15:37:53 -0700[diff] [blame]3060 struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec);
Mark Brown45e65502010-09-28 16:01:20 -0700[diff] [blame]3061 int mask;
3062 int active;
Mark Brownfbf04072011-08-21 18:07:44 +0100[diff] [blame]3063 int reg;
Mark Brown45e65502010-09-28 16:01:20 -0700[diff] [blame]3064
Mark Brown2a7b1a02010-12-07 15:32:38 +0000[diff] [blame]3065 mask = snd_soc_read(codec, WM8962_INTERRUPT_STATUS_2_MASK);
Mark Brown45e65502010-09-28 16:01:20 -0700[diff] [blame]3066
3067 active = snd_soc_read(codec, WM8962_INTERRUPT_STATUS_2);
3068 active &= ~mask;
3069
Mark Browne6ef5872011-08-21 11:47:14 +0100[diff] [blame]3070 if (!active)
3071 return IRQ_NONE;
3072
Mark Brown3198b9e2011-07-20 13:50:10 +0100[diff] [blame]3073 /* Acknowledge the interrupts */
3074 snd_soc_write(codec, WM8962_INTERRUPT_STATUS_2, active);
3075
Mark Brown3b8a6d82011-04-25 17:53:43 +0100[diff] [blame]3076 if (active & WM8962_FLL_LOCK_EINT) {
3077 dev_dbg(codec->dev, "FLL locked\n");
3078 complete(&wm8962->fll_lock);
3079 }
3080
Mark Brown45e65502010-09-28 16:01:20 -0700[diff] [blame]3081 if (active & WM8962_FIFOS_ERR_EINT)
3082 dev_err(codec->dev, "FIFO error\n");
3083
Mark Brownfbf04072011-08-21 18:07:44 +0100[diff] [blame]3084 if (active & WM8962_TEMP_SHUT_EINT) {
Mark Brown45e65502010-09-28 16:01:20 -0700[diff] [blame]3085 dev_crit(codec->dev, "Thermal shutdown\n");
3086
Mark Brownfbf04072011-08-21 18:07:44 +0100[diff] [blame]3087 reg = snd_soc_read(codec, WM8962_THERMAL_SHUTDOWN_STATUS);
3088
3089 if (reg & WM8962_TEMP_ERR_HP)
3090 dev_crit(codec->dev, "Headphone thermal error\n");
3091 if (reg & WM8962_TEMP_WARN_HP)
3092 dev_crit(codec->dev, "Headphone thermal warning\n");
3093 if (reg & WM8962_TEMP_ERR_SPK)
3094 dev_crit(codec->dev, "Speaker thermal error\n");
3095 if (reg & WM8962_TEMP_WARN_SPK)
3096 dev_crit(codec->dev, "Speaker thermal warning\n");
3097 }
3098
Mark Brown77113082010-09-30 15:37:53 -0700[diff] [blame]3099 if (active & (WM8962_MICSCD_EINT | WM8962_MICD_EINT)) {
3100 dev_dbg(codec->dev, "Microphone event detected\n");
3101
Mark Brown6dc47e92010-12-28 02:14:25 +0000[diff] [blame]3102#ifndef CONFIG_SND_SOC_WM8962_MODULE
Mark Brown2bbb5d62010-12-05 12:50:12 +0000[diff] [blame]3103 trace_snd_soc_jack_irq(dev_name(codec->dev));
Mark Brown1435b942010-12-23 01:56:20 +0000[diff] [blame]3104#endif
Mark Brown2bbb5d62010-12-05 12:50:12 +0000[diff] [blame]3105
Mark Brown11e16eb2010-11-03 14:45:07 -0400[diff] [blame]3106 pm_wakeup_event(codec->dev, 300);
3107
Mark Brown77113082010-09-30 15:37:53 -0700[diff] [blame]3108 schedule_delayed_work(&wm8962->mic_work,
3109 msecs_to_jiffies(250));
3110 }
3111
Mark Brown45e65502010-09-28 16:01:20 -0700[diff] [blame]3112 return IRQ_HANDLED;
3113}
3114
Mark Brown77113082010-09-30 15:37:53 -0700[diff] [blame]3115/**
3116 * wm8962_mic_detect - Enable microphone detection via the WM8962 IRQ
3117 *
3118 * @codec: WM8962 codec
3119 * @jack: jack to report detection events on
3120 *
3121 * Enable microphone detection via IRQ on the WM8962. If GPIOs are
3122 * being used to bring out signals to the processor then only platform
3123 * data configuration is needed for WM8962 and processor GPIOs should
3124 * be configured using snd_soc_jack_add_gpios() instead.
3125 *
3126 * If no jack is supplied detection will be disabled.
3127 */
3128int wm8962_mic_detect(struct snd_soc_codec *codec, struct snd_soc_jack *jack)
3129{
3130 struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec);
3131 int irq_mask, enable;
3132
3133 wm8962->jack = jack;
3134 if (jack) {
3135 irq_mask = 0;
3136 enable = WM8962_MICDET_ENA;
3137 } else {
3138 irq_mask = WM8962_MICD_EINT | WM8962_MICSCD_EINT;
3139 enable = 0;
3140 }
3141
3142 snd_soc_update_bits(codec, WM8962_INTERRUPT_STATUS_2_MASK,
3143 WM8962_MICD_EINT | WM8962_MICSCD_EINT, irq_mask);
3144 snd_soc_update_bits(codec, WM8962_ADDITIONAL_CONTROL_4,
3145 WM8962_MICDET_ENA, enable);
3146
3147 /* Send an initial empty report */
3148 snd_soc_jack_report(wm8962->jack, 0,
3149 SND_JACK_MICROPHONE | SND_JACK_BTN_0);
3150
Mark Browna5ef9882011-11-01 16:00:15 +0000[diff] [blame]3151 if (jack) {
Mark Browndb0e5542011-11-01 15:59:03 +0000[diff] [blame]3152 snd_soc_dapm_force_enable_pin(&codec->dapm, "SYSCLK");
Mark Browna5ef9882011-11-01 16:00:15 +0000[diff] [blame]3153 snd_soc_dapm_force_enable_pin(&codec->dapm, "MICBIAS");
Mark Brown00ae3b82011-11-01 16:02:01 +0000[diff] [blame]3154 } else {
3155 snd_soc_dapm_disable_pin(&codec->dapm, "SYSCLK");
3156 snd_soc_dapm_disable_pin(&codec->dapm, "MICBIAS");
Mark Browna5ef9882011-11-01 16:00:15 +0000[diff] [blame]3157 }
Mark Browndb0e5542011-11-01 15:59:03 +0000[diff] [blame]3158
Mark Brown77113082010-09-30 15:37:53 -0700[diff] [blame]3159 return 0;
3160}
3161EXPORT_SYMBOL_GPL(wm8962_mic_detect);
3162
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]3163#if defined(CONFIG_INPUT) || defined(CONFIG_INPUT_MODULE)
3164static int beep_rates[] = {
3165 500, 1000, 2000, 4000,
3166};
3167
3168static void wm8962_beep_work(struct work_struct *work)
3169{
3170 struct wm8962_priv *wm8962 =
3171 container_of(work, struct wm8962_priv, beep_work);
Mark Brown54d8d0a2010-08-12 15:02:11 +0100[diff] [blame]3172 struct snd_soc_codec *codec = wm8962->codec;
Liam Girdwoodce6120c2010-11-05 15:53:46 +0200[diff] [blame]3173 struct snd_soc_dapm_context *dapm = &codec->dapm;
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]3174 int i;
3175 int reg = 0;
3176 int best = 0;
3177
3178 if (wm8962->beep_rate) {
3179 for (i = 0; i < ARRAY_SIZE(beep_rates); i++) {
3180 if (abs(wm8962->beep_rate - beep_rates[i]) <
3181 abs(wm8962->beep_rate - beep_rates[best]))
3182 best = i;
3183 }
3184
3185 dev_dbg(codec->dev, "Set beep rate %dHz for requested %dHz\n",
3186 beep_rates[best], wm8962->beep_rate);
3187
3188 reg = WM8962_BEEP_ENA | (best << WM8962_BEEP_RATE_SHIFT);
3189
Liam Girdwoodce6120c2010-11-05 15:53:46 +0200[diff] [blame]3190 snd_soc_dapm_enable_pin(dapm, "Beep");
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]3191 } else {
3192 dev_dbg(codec->dev, "Disabling beep\n");
Liam Girdwoodce6120c2010-11-05 15:53:46 +0200[diff] [blame]3193 snd_soc_dapm_disable_pin(dapm, "Beep");
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]3194 }
3195
3196 snd_soc_update_bits(codec, WM8962_BEEP_GENERATOR_1,
3197 WM8962_BEEP_ENA | WM8962_BEEP_RATE_MASK, reg);
3198
Liam Girdwoodce6120c2010-11-05 15:53:46 +0200[diff] [blame]3199 snd_soc_dapm_sync(dapm);
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]3200}
3201
3202/* For usability define a way of injecting beep events for the device -
3203 * many systems will not have a keyboard.
3204 */
3205static int wm8962_beep_event(struct input_dev *dev, unsigned int type,
3206 unsigned int code, int hz)
3207{
3208 struct snd_soc_codec *codec = input_get_drvdata(dev);
3209 struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec);
3210
3211 dev_dbg(codec->dev, "Beep event %x %x\n", code, hz);
3212
3213 switch (code) {
3214 case SND_BELL:
3215 if (hz)
3216 hz = 1000;
3217 case SND_TONE:
3218 break;
3219 default:
3220 return -1;
3221 }
3222
3223 /* Kick the beep from a workqueue */
3224 wm8962->beep_rate = hz;
3225 schedule_work(&wm8962->beep_work);
3226 return 0;
3227}
3228
3229static ssize_t wm8962_beep_set(struct device *dev,
3230 struct device_attribute *attr,
3231 const char *buf, size_t count)
3232{
3233 struct wm8962_priv *wm8962 = dev_get_drvdata(dev);
3234 long int time;
Mark Brown74a557e2010-11-03 09:37:06 -0400[diff] [blame]3235 int ret;
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]3236
Mark Brown74a557e2010-11-03 09:37:06 -0400[diff] [blame]3237 ret = strict_strtol(buf, 10, &time);
3238 if (ret != 0)
3239 return ret;
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]3240
3241 input_event(wm8962->beep, EV_SND, SND_TONE, time);
3242
3243 return count;
3244}
3245
3246static DEVICE_ATTR(beep, 0200, NULL, wm8962_beep_set);
3247
3248static void wm8962_init_beep(struct snd_soc_codec *codec)
3249{
3250 struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec);
3251 int ret;
3252
3253 wm8962->beep = input_allocate_device();
3254 if (!wm8962->beep) {
3255 dev_err(codec->dev, "Failed to allocate beep device\n");
3256 return;
3257 }
3258
3259 INIT_WORK(&wm8962->beep_work, wm8962_beep_work);
3260 wm8962->beep_rate = 0;
3261
3262 wm8962->beep->name = "WM8962 Beep Generator";
3263 wm8962->beep->phys = dev_name(codec->dev);
3264 wm8962->beep->id.bustype = BUS_I2C;
3265
3266 wm8962->beep->evbit[0] = BIT_MASK(EV_SND);
3267 wm8962->beep->sndbit[0] = BIT_MASK(SND_BELL) | BIT_MASK(SND_TONE);
3268 wm8962->beep->event = wm8962_beep_event;
3269 wm8962->beep->dev.parent = codec->dev;
3270 input_set_drvdata(wm8962->beep, codec);
3271
3272 ret = input_register_device(wm8962->beep);
3273 if (ret != 0) {
3274 input_free_device(wm8962->beep);
3275 wm8962->beep = NULL;
3276 dev_err(codec->dev, "Failed to register beep device\n");
3277 }
3278
3279 ret = device_create_file(codec->dev, &dev_attr_beep);
3280 if (ret != 0) {
3281 dev_err(codec->dev, "Failed to create keyclick file: %d\n",
3282 ret);
3283 }
3284}
3285
3286static void wm8962_free_beep(struct snd_soc_codec *codec)
3287{
3288 struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec);
3289
3290 device_remove_file(codec->dev, &dev_attr_beep);
3291 input_unregister_device(wm8962->beep);
3292 cancel_work_sync(&wm8962->beep_work);
3293 wm8962->beep = NULL;
3294
3295 snd_soc_update_bits(codec, WM8962_BEEP_GENERATOR_1, WM8962_BEEP_ENA,0);
3296}
3297#else
3298static void wm8962_init_beep(struct snd_soc_codec *codec)
3299{
3300}
3301
3302static void wm8962_free_beep(struct snd_soc_codec *codec)
3303{
3304}
3305#endif
3306
Mark Brown8ca2aa92010-10-01 17:46:37 -0700[diff] [blame]3307static void wm8962_set_gpio_mode(struct snd_soc_codec *codec, int gpio)
3308{
3309 int mask = 0;
3310 int val = 0;
3311
3312 /* Some of the GPIOs are behind MFP configuration and need to
3313 * be put into GPIO mode. */
3314 switch (gpio) {
3315 case 2:
3316 mask = WM8962_CLKOUT2_SEL_MASK;
3317 val = 1 << WM8962_CLKOUT2_SEL_SHIFT;
3318 break;
3319 case 3:
3320 mask = WM8962_CLKOUT3_SEL_MASK;
3321 val = 1 << WM8962_CLKOUT3_SEL_SHIFT;
3322 break;
3323 default:
3324 break;
3325 }
3326
3327 if (mask)
3328 snd_soc_update_bits(codec, WM8962_ANALOGUE_CLOCKING1,
3329 mask, val);
3330}
3331
Mark Brown3367b8d2010-09-20 17:34:58 +0100[diff] [blame]3332#ifdef CONFIG_GPIOLIB
3333static inline struct wm8962_priv *gpio_to_wm8962(struct gpio_chip *chip)
3334{
3335 return container_of(chip, struct wm8962_priv, gpio_chip);
3336}
3337
3338static int wm8962_gpio_request(struct gpio_chip *chip, unsigned offset)
3339{
3340 struct wm8962_priv *wm8962 = gpio_to_wm8962(chip);
3341 struct snd_soc_codec *codec = wm8962->codec;
Mark Brown3367b8d2010-09-20 17:34:58 +0100[diff] [blame]3342
3343 /* The WM8962 GPIOs aren't linearly numbered. For simplicity
3344 * we export linear numbers and error out if the unsupported
3345 * ones are requsted.
3346 */
3347 switch (offset + 1) {
3348 case 2:
Mark Brown3367b8d2010-09-20 17:34:58 +0100[diff] [blame]3349 case 3:
Mark Brown3367b8d2010-09-20 17:34:58 +0100[diff] [blame]3350 case 5:
3351 case 6:
3352 break;
3353 default:
3354 return -EINVAL;
3355 }
3356
Mark Brown8ca2aa92010-10-01 17:46:37 -0700[diff] [blame]3357 wm8962_set_gpio_mode(codec, offset + 1);
Mark Brown3367b8d2010-09-20 17:34:58 +0100[diff] [blame]3358
3359 return 0;
3360}
3361
3362static void wm8962_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
3363{
3364 struct wm8962_priv *wm8962 = gpio_to_wm8962(chip);
3365 struct snd_soc_codec *codec = wm8962->codec;
3366
3367 snd_soc_update_bits(codec, WM8962_GPIO_BASE + offset,
Mark Brownd71bb812011-01-31 13:41:03 +0000[diff] [blame]3368 WM8962_GP2_LVL, !!value << WM8962_GP2_LVL_SHIFT);
Mark Brown3367b8d2010-09-20 17:34:58 +0100[diff] [blame]3369}
3370
3371static int wm8962_gpio_direction_out(struct gpio_chip *chip,
3372 unsigned offset, int value)
3373{
3374 struct wm8962_priv *wm8962 = gpio_to_wm8962(chip);
3375 struct snd_soc_codec *codec = wm8962->codec;
Axel Linfe75fe02011-12-30 23:38:03 +0800[diff] [blame]3376 int ret, val;
Mark Brown3367b8d2010-09-20 17:34:58 +0100[diff] [blame]3377
3378 /* Force function 1 (logic output) */
3379 val = (1 << WM8962_GP2_FN_SHIFT) | (value << WM8962_GP2_LVL_SHIFT);
3380
Axel Linfe75fe02011-12-30 23:38:03 +0800[diff] [blame]3381 ret = snd_soc_update_bits(codec, WM8962_GPIO_BASE + offset,
3382 WM8962_GP2_FN_MASK | WM8962_GP2_LVL, val);
3383 if (ret < 0)
3384 return ret;
3385
3386 return 0;
Mark Brown3367b8d2010-09-20 17:34:58 +0100[diff] [blame]3387}
3388
3389static struct gpio_chip wm8962_template_chip = {
3390 .label = "wm8962",
3391 .owner = THIS_MODULE,
3392 .request = wm8962_gpio_request,
3393 .direction_output = wm8962_gpio_direction_out,
3394 .set = wm8962_gpio_set,
3395 .can_sleep = 1,
3396};
3397
3398static void wm8962_init_gpio(struct snd_soc_codec *codec)
3399{
3400 struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec);
3401 struct wm8962_pdata *pdata = dev_get_platdata(codec->dev);
3402 int ret;
3403
3404 wm8962->gpio_chip = wm8962_template_chip;
3405 wm8962->gpio_chip.ngpio = WM8962_MAX_GPIO;
3406 wm8962->gpio_chip.dev = codec->dev;
3407
3408 if (pdata && pdata->gpio_base)
3409 wm8962->gpio_chip.base = pdata->gpio_base;
3410 else
3411 wm8962->gpio_chip.base = -1;
3412
3413 ret = gpiochip_add(&wm8962->gpio_chip);
3414 if (ret != 0)
3415 dev_err(codec->dev, "Failed to add GPIOs: %d\n", ret);
3416}
3417
3418static void wm8962_free_gpio(struct snd_soc_codec *codec)
3419{
3420 struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec);
3421 int ret;
3422
3423 ret = gpiochip_remove(&wm8962->gpio_chip);
3424 if (ret != 0)
3425 dev_err(codec->dev, "Failed to remove GPIOs: %d\n", ret);
3426}
3427#else
3428static void wm8962_init_gpio(struct snd_soc_codec *codec)
3429{
3430}
3431
3432static void wm8962_free_gpio(struct snd_soc_codec *codec)
3433{
3434}
3435#endif
3436
Mark Brown54d8d0a2010-08-12 15:02:11 +0100[diff] [blame]3437static int wm8962_probe(struct snd_soc_codec *codec)
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]3438{
3439 int ret;
Mark Brown54d8d0a2010-08-12 15:02:11 +0100[diff] [blame]3440 struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec);
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]3441 struct wm8962_pdata *pdata = dev_get_platdata(codec->dev);
Lars-Peter Clausen7f87e302010-12-28 21:38:01 +0100[diff] [blame]3442 u16 *reg_cache = codec->reg_cache;
Mark Brown45e65502010-09-28 16:01:20 -0700[diff] [blame]3443 int i, trigger, irq_pol;
Mark Browne47ac372011-04-25 20:14:21 +0100[diff] [blame]3444 bool dmicclk, dmicdat;
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]3445
Mark Brown54d8d0a2010-08-12 15:02:11 +0100[diff] [blame]3446 wm8962->codec = codec;
Mark Brown7b16f562011-11-01 19:32:25 +0000[diff] [blame]3447 codec->control_data = wm8962->regmap;
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]3448
Mark Brown7b16f562011-11-01 19:32:25 +0000[diff] [blame]3449 ret = snd_soc_codec_set_cache_io(codec, 16, 16, SND_SOC_REGMAP);
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]3450 if (ret != 0) {
3451 dev_err(codec->dev, "Failed to set cache I/O: %d\n", ret);
Mark Brown7b16f562011-11-01 19:32:25 +0000[diff] [blame]3452 return ret;
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]3453 }
3454
3455 wm8962->disable_nb[0].notifier_call = wm8962_regulator_event_0;
3456 wm8962->disable_nb[1].notifier_call = wm8962_regulator_event_1;
3457 wm8962->disable_nb[2].notifier_call = wm8962_regulator_event_2;
3458 wm8962->disable_nb[3].notifier_call = wm8962_regulator_event_3;
3459 wm8962->disable_nb[4].notifier_call = wm8962_regulator_event_4;
3460 wm8962->disable_nb[5].notifier_call = wm8962_regulator_event_5;
3461 wm8962->disable_nb[6].notifier_call = wm8962_regulator_event_6;
3462 wm8962->disable_nb[7].notifier_call = wm8962_regulator_event_7;
3463
3464 /* This should really be moved into the regulator core */
3465 for (i = 0; i < ARRAY_SIZE(wm8962->supplies); i++) {
3466 ret = regulator_register_notifier(wm8962->supplies[i].consumer,
3467 &wm8962->disable_nb[i]);
3468 if (ret != 0) {
3469 dev_err(codec->dev,
3470 "Failed to register regulator notifier: %d\n",
3471 ret);
3472 }
3473 }
3474
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]3475 /* SYSCLK defaults to on; make sure it is off so we can safely
3476 * write to registers if the device is declocked.
3477 */
3478 snd_soc_update_bits(codec, WM8962_CLOCKING2, WM8962_SYSCLK_ENA, 0);
3479
Mark Browna115c722011-08-04 13:23:38 +0900[diff] [blame]3480 /* Ensure we have soft control over all registers */
3481 snd_soc_update_bits(codec, WM8962_CLOCKING2,
3482 WM8962_CLKREG_OVD, WM8962_CLKREG_OVD);
3483
Mark Brown2af8de82011-11-01 13:53:37 +0000[diff] [blame]3484 /* Ensure that the oscillator and PLLs are disabled */
3485 snd_soc_update_bits(codec, WM8962_PLL2,
3486 WM8962_OSC_ENA | WM8962_PLL2_ENA | WM8962_PLL3_ENA,
3487 0);
3488
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]3489 if (pdata) {
3490 /* Apply static configuration for GPIOs */
3491 for (i = 0; i < ARRAY_SIZE(pdata->gpio_init); i++)
Mark Brown8ca2aa92010-10-01 17:46:37 -0700[diff] [blame]3492 if (pdata->gpio_init[i]) {
3493 wm8962_set_gpio_mode(codec, i + 1);
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]3494 snd_soc_write(codec, 0x200 + i,
3495 pdata->gpio_init[i] & 0xffff);
Mark Brown8ca2aa92010-10-01 17:46:37 -0700[diff] [blame]3496 }
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]3497
3498 /* Put the speakers into mono mode? */
3499 if (pdata->spk_mono)
Lars-Peter Clausen7f87e302010-12-28 21:38:01 +0100[diff] [blame]3500 reg_cache[WM8962_CLASS_D_CONTROL_2]
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]3501 |= WM8962_SPK_MONO;
Mark Browna4f28c02010-09-29 13:24:35 -0700[diff] [blame]3502
3503 /* Micbias setup, detection enable and detection
3504 * threasholds. */
3505 if (pdata->mic_cfg)
3506 snd_soc_update_bits(codec, WM8962_ADDITIONAL_CONTROL_4,
3507 WM8962_MICDET_ENA |
3508 WM8962_MICDET_THR_MASK |
3509 WM8962_MICSHORT_THR_MASK |
3510 WM8962_MICBIAS_LVL,
3511 pdata->mic_cfg);
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]3512 }
3513
3514 /* Latch volume update bits */
Mark Browna1b3b5e2010-12-24 16:59:30 +0000[diff] [blame]3515 snd_soc_update_bits(codec, WM8962_LEFT_INPUT_VOLUME,
3516 WM8962_IN_VU, WM8962_IN_VU);
3517 snd_soc_update_bits(codec, WM8962_RIGHT_INPUT_VOLUME,
3518 WM8962_IN_VU, WM8962_IN_VU);
3519 snd_soc_update_bits(codec, WM8962_LEFT_ADC_VOLUME,
3520 WM8962_ADC_VU, WM8962_ADC_VU);
3521 snd_soc_update_bits(codec, WM8962_RIGHT_ADC_VOLUME,
3522 WM8962_ADC_VU, WM8962_ADC_VU);
3523 snd_soc_update_bits(codec, WM8962_LEFT_DAC_VOLUME,
3524 WM8962_DAC_VU, WM8962_DAC_VU);
3525 snd_soc_update_bits(codec, WM8962_RIGHT_DAC_VOLUME,
3526 WM8962_DAC_VU, WM8962_DAC_VU);
3527 snd_soc_update_bits(codec, WM8962_SPKOUTL_VOLUME,
3528 WM8962_SPKOUT_VU, WM8962_SPKOUT_VU);
3529 snd_soc_update_bits(codec, WM8962_SPKOUTR_VOLUME,
3530 WM8962_SPKOUT_VU, WM8962_SPKOUT_VU);
3531 snd_soc_update_bits(codec, WM8962_HPOUTL_VOLUME,
3532 WM8962_HPOUT_VU, WM8962_HPOUT_VU);
3533 snd_soc_update_bits(codec, WM8962_HPOUTR_VOLUME,
3534 WM8962_HPOUT_VU, WM8962_HPOUT_VU);
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]3535
Mark Brown8f63aaa882011-06-07 23:14:37 +0100[diff] [blame]3536 /* Stereo control for EQ */
3537 snd_soc_update_bits(codec, WM8962_EQ1, WM8962_EQ_SHARED_COEFF, 0);
3538
Mark Brown0469e7b2011-11-08 15:22:09 +0000[diff] [blame]3539 /* Don't debouce interrupts so we don't need SYSCLK */
3540 snd_soc_update_bits(codec, WM8962_IRQ_DEBOUNCE,
3541 WM8962_FLL_LOCK_DB | WM8962_PLL3_LOCK_DB |
3542 WM8962_PLL2_LOCK_DB | WM8962_TEMP_SHUT_DB,
3543 0);
3544
Mark Brown54d8d0a2010-08-12 15:02:11 +0100[diff] [blame]3545 wm8962_add_widgets(codec);
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]3546
Mark Browne47ac372011-04-25 20:14:21 +0100[diff] [blame]3547 /* Save boards having to disable DMIC when not in use */
3548 dmicclk = false;
3549 dmicdat = false;
3550 for (i = 0; i < WM8962_MAX_GPIO; i++) {
3551 switch (snd_soc_read(codec, WM8962_GPIO_BASE + i)
3552 & WM8962_GP2_FN_MASK) {
3553 case WM8962_GPIO_FN_DMICCLK:
3554 dmicclk = true;
3555 break;
3556 case WM8962_GPIO_FN_DMICDAT:
3557 dmicdat = true;
3558 break;
3559 default:
3560 break;
3561 }
3562 }
3563 if (!dmicclk || !dmicdat) {
3564 dev_dbg(codec->dev, "DMIC not in use, disabling\n");
3565 snd_soc_dapm_nc_pin(&codec->dapm, "DMICDAT");
3566 }
3567 if (dmicclk != dmicdat)
3568 dev_warn(codec->dev, "DMIC GPIOs partially configured\n");
3569
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]3570 wm8962_init_beep(codec);
Mark Brown3367b8d2010-09-20 17:34:58 +0100[diff] [blame]3571 wm8962_init_gpio(codec);
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]3572
Mark Brownc7356da2011-06-07 23:13:53 +0100[diff] [blame]3573 if (wm8962->irq) {
Mark Brown45e65502010-09-28 16:01:20 -0700[diff] [blame]3574 if (pdata && pdata->irq_active_low) {
3575 trigger = IRQF_TRIGGER_LOW;
3576 irq_pol = WM8962_IRQ_POL;
3577 } else {
3578 trigger = IRQF_TRIGGER_HIGH;
3579 irq_pol = 0;
3580 }
3581
3582 snd_soc_update_bits(codec, WM8962_INTERRUPT_CONTROL,
3583 WM8962_IRQ_POL, irq_pol);
3584
Mark Brownc7356da2011-06-07 23:13:53 +0100[diff] [blame]3585 ret = request_threaded_irq(wm8962->irq, NULL, wm8962_irq,
Mark Brown45e65502010-09-28 16:01:20 -0700[diff] [blame]3586 trigger | IRQF_ONESHOT,
3587 "wm8962", codec);
3588 if (ret != 0) {
3589 dev_err(codec->dev, "Failed to request IRQ %d: %d\n",
Mark Brownc7356da2011-06-07 23:13:53 +0100[diff] [blame]3590 wm8962->irq, ret);
3591 wm8962->irq = 0;
Mark Brown45e65502010-09-28 16:01:20 -0700[diff] [blame]3592 /* Non-fatal */
3593 } else {
Mark Brown3b8a6d82011-04-25 17:53:43 +0100[diff] [blame]3594 /* Enable some IRQs by default */
Mark Brown45e65502010-09-28 16:01:20 -0700[diff] [blame]3595 snd_soc_update_bits(codec,
3596 WM8962_INTERRUPT_STATUS_2_MASK,
Mark Brown3b8a6d82011-04-25 17:53:43 +0100[diff] [blame]3597 WM8962_FLL_LOCK_EINT |
Mark Brown45e65502010-09-28 16:01:20 -0700[diff] [blame]3598 WM8962_TEMP_SHUT_EINT |
3599 WM8962_FIFOS_ERR_EINT, 0);
3600 }
3601 }
3602
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]3603 return 0;
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]3604}
3605
Mark Brown54d8d0a2010-08-12 15:02:11 +0100[diff] [blame]3606static int wm8962_remove(struct snd_soc_codec *codec)
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]3607{
Mark Brown54d8d0a2010-08-12 15:02:11 +0100[diff] [blame]3608 struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec);
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]3609 int i;
3610
Mark Brownc7356da2011-06-07 23:13:53 +0100[diff] [blame]3611 if (wm8962->irq)
3612 free_irq(wm8962->irq, codec);
Mark Brown45e65502010-09-28 16:01:20 -0700[diff] [blame]3613
Mark Brown77113082010-09-30 15:37:53 -0700[diff] [blame]3614 cancel_delayed_work_sync(&wm8962->mic_work);
3615
Mark Brown3367b8d2010-09-20 17:34:58 +0100[diff] [blame]3616 wm8962_free_gpio(codec);
Mark Brown54d8d0a2010-08-12 15:02:11 +0100[diff] [blame]3617 wm8962_free_beep(codec);
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]3618 for (i = 0; i < ARRAY_SIZE(wm8962->supplies); i++)
3619 regulator_unregister_notifier(wm8962->supplies[i].consumer,
3620 &wm8962->disable_nb[i]);
Mark Brown54d8d0a2010-08-12 15:02:11 +0100[diff] [blame]3621
3622 return 0;
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]3623}
3624
Mark Brown1b39bf32011-12-29 12:18:53 +0000[diff] [blame]3625static int wm8962_soc_volatile(struct snd_soc_codec *codec,
3626 unsigned int reg)
3627{
3628 return true;
3629}
3630
3631
Mark Brown54d8d0a2010-08-12 15:02:11 +0100[diff] [blame]3632static struct snd_soc_codec_driver soc_codec_dev_wm8962 = {
3633 .probe = wm8962_probe,
3634 .remove = wm8962_remove,
Mark Brown54d8d0a2010-08-12 15:02:11 +0100[diff] [blame]3635 .set_bias_level = wm8962_set_bias_level,
Mark Brown92a43522011-04-25 18:44:01 +0100[diff] [blame]3636 .set_pll = wm8962_set_fll,
Mark Brown1b39bf32011-12-29 12:18:53 +0000[diff] [blame]3637 .reg_cache_size = WM8962_MAX_REGISTER,
3638 .volatile_register = wm8962_soc_volatile,
Mark Brown54d8d0a2010-08-12 15:02:11 +0100[diff] [blame]3639};
3640
Mark Brown7b16f562011-11-01 19:32:25 +0000[diff] [blame]3641static const struct regmap_config wm8962_regmap = {
3642 .reg_bits = 16,
3643 .val_bits = 16,
3644
3645 .max_register = WM8962_MAX_REGISTER,
3646 .reg_defaults = wm8962_reg,
3647 .num_reg_defaults = ARRAY_SIZE(wm8962_reg),
3648 .volatile_reg = wm8962_volatile_register,
3649 .readable_reg = wm8962_readable_register,
3650 .cache_type = REGCACHE_RBTREE,
3651};
3652
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]3653static __devinit int wm8962_i2c_probe(struct i2c_client *i2c,
3654 const struct i2c_device_id *id)
3655{
3656 struct wm8962_priv *wm8962;
Mark Brown7b16f562011-11-01 19:32:25 +0000[diff] [blame]3657 unsigned int reg;
3658 int ret, i;
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]3659
Mark Brownbe086aa2011-11-27 19:56:52 +0000[diff] [blame]3660 wm8962 = devm_kzalloc(&i2c->dev, sizeof(struct wm8962_priv),
3661 GFP_KERNEL);
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]3662 if (wm8962 == NULL)
3663 return -ENOMEM;
3664
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]3665 i2c_set_clientdata(i2c, wm8962);
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]3666
Mark Brown7b16f562011-11-01 19:32:25 +0000[diff] [blame]3667 INIT_DELAYED_WORK(&wm8962->mic_work, wm8962_mic_work);
3668 init_completion(&wm8962->fll_lock);
Mark Brownc7356da2011-06-07 23:13:53 +0100[diff] [blame]3669 wm8962->irq = i2c->irq;
3670
Mark Brown7b16f562011-11-01 19:32:25 +0000[diff] [blame]3671 for (i = 0; i < ARRAY_SIZE(wm8962->supplies); i++)
3672 wm8962->supplies[i].supply = wm8962_supply_names[i];
3673
3674 ret = regulator_bulk_get(&i2c->dev, ARRAY_SIZE(wm8962->supplies),
3675 wm8962->supplies);
3676 if (ret != 0) {
3677 dev_err(&i2c->dev, "Failed to request supplies: %d\n", ret);
Mark Brownbe086aa2011-11-27 19:56:52 +0000[diff] [blame]3678 goto err;
Mark Brown7b16f562011-11-01 19:32:25 +0000[diff] [blame]3679 }
3680
3681 ret = regulator_bulk_enable(ARRAY_SIZE(wm8962->supplies),
3682 wm8962->supplies);
3683 if (ret != 0) {
3684 dev_err(&i2c->dev, "Failed to enable supplies: %d\n", ret);
3685 goto err_get;
3686 }
3687
3688 wm8962->regmap = regmap_init_i2c(i2c, &wm8962_regmap);
3689 if (IS_ERR(wm8962->regmap)) {
3690 ret = PTR_ERR(wm8962->regmap);
3691 dev_err(&i2c->dev, "Failed to allocate regmap: %d\n", ret);
3692 goto err_enable;
3693 }
3694
3695 /*
3696 * We haven't marked the chip revision as volatile due to
3697 * sharing a register with the right input volume; explicitly
3698 * bypass the cache to read it.
3699 */
3700 regcache_cache_bypass(wm8962->regmap, true);
3701
3702 ret = regmap_read(wm8962->regmap, WM8962_SOFTWARE_RESET, &reg);
3703 if (ret < 0) {
3704 dev_err(&i2c->dev, "Failed to read ID register\n");
3705 goto err_regmap;
3706 }
3707 if (reg != 0x6243) {
3708 dev_err(&i2c->dev,
3709 "Device is not a WM8962, ID %x != 0x6243\n", ret);
3710 ret = -EINVAL;
3711 goto err_regmap;
3712 }
3713
3714 ret = regmap_read(wm8962->regmap, WM8962_RIGHT_INPUT_VOLUME, &reg);
3715 if (ret < 0) {
3716 dev_err(&i2c->dev, "Failed to read device revision: %d\n",
3717 ret);
3718 goto err_regmap;
3719 }
3720
3721 dev_info(&i2c->dev, "customer id %x revision %c\n",
3722 (reg & WM8962_CUST_ID_MASK) >> WM8962_CUST_ID_SHIFT,
3723 ((reg & WM8962_CHIP_REV_MASK) >> WM8962_CHIP_REV_SHIFT)
3724 + 'A');
3725
3726 regcache_cache_bypass(wm8962->regmap, false);
3727
3728 ret = wm8962_reset(wm8962);
3729 if (ret < 0) {
3730 dev_err(&i2c->dev, "Failed to issue reset\n");
3731 goto err_regmap;
3732 }
3733
3734 regcache_cache_only(wm8962->regmap, true);
3735
Mark Brown54d8d0a2010-08-12 15:02:11 +0100[diff] [blame]3736 ret = snd_soc_register_codec(&i2c->dev,
3737 &soc_codec_dev_wm8962, &wm8962_dai, 1);
3738 if (ret < 0)
Mark Brown7b16f562011-11-01 19:32:25 +0000[diff] [blame]3739 goto err_regmap;
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]3740
Mark Brown7b16f562011-11-01 19:32:25 +0000[diff] [blame]3741 /* The drivers should power up as needed */
3742 regulator_bulk_disable(ARRAY_SIZE(wm8962->supplies), wm8962->supplies);
3743
3744 return 0;
3745
3746err_regmap:
3747 regmap_exit(wm8962->regmap);
3748err_enable:
3749 regulator_bulk_disable(ARRAY_SIZE(wm8962->supplies), wm8962->supplies);
3750err_get:
3751 regulator_bulk_free(ARRAY_SIZE(wm8962->supplies), wm8962->supplies);
Mark Brownbe086aa2011-11-27 19:56:52 +0000[diff] [blame]3752err:
Mark Brown54d8d0a2010-08-12 15:02:11 +0100[diff] [blame]3753 return ret;
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]3754}
3755
3756static __devexit int wm8962_i2c_remove(struct i2c_client *client)
3757{
Mark Brown7b16f562011-11-01 19:32:25 +0000[diff] [blame]3758 struct wm8962_priv *wm8962 = dev_get_drvdata(&client->dev);
3759
Mark Brown54d8d0a2010-08-12 15:02:11 +0100[diff] [blame]3760 snd_soc_unregister_codec(&client->dev);
Mark Brown7b16f562011-11-01 19:32:25 +0000[diff] [blame]3761 regmap_exit(wm8962->regmap);
3762 regulator_bulk_free(ARRAY_SIZE(wm8962->supplies), wm8962->supplies);
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]3763 return 0;
3764}
3765
3766static const struct i2c_device_id wm8962_i2c_id[] = {
3767 { "wm8962", 0 },
3768 { }
3769};
3770MODULE_DEVICE_TABLE(i2c, wm8962_i2c_id);
3771
3772static struct i2c_driver wm8962_i2c_driver = {
3773 .driver = {
Mark Brownea738ba2010-09-20 20:36:19 +0100[diff] [blame]3774 .name = "wm8962",
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]3775 .owner = THIS_MODULE,
3776 },
3777 .probe = wm8962_i2c_probe,
3778 .remove = __devexit_p(wm8962_i2c_remove),
3779 .id_table = wm8962_i2c_id,
3780};
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]3781
3782static int __init wm8962_modinit(void)
3783{
Mark Brown291d64b2012-01-10 10:53:49 -0800[diff] [blame]3784 return i2c_add_driver(&wm8962_i2c_driver);
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]3785}
3786module_init(wm8962_modinit);
3787
3788static void __exit wm8962_exit(void)
3789{
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]3790 i2c_del_driver(&wm8962_i2c_driver);
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]3791}
3792module_exit(wm8962_exit);
3793
3794MODULE_DESCRIPTION("ASoC WM8962 driver");
3795MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>");
3796MODULE_LICENSE("GPL");