Emilio López | e874a66 | 2013-02-25 11:44:26 -0300 | [diff] [blame] | 1 | /* |
| 2 | * Copyright 2013 Emilio López |
| 3 | * |
| 4 | * Emilio López <emilio@elopez.com.ar> |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; either version 2 of the License, or |
| 9 | * (at your option) any later version. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
| 15 | */ |
| 16 | |
| 17 | #include <linux/clk-provider.h> |
| 18 | #include <linux/clkdev.h> |
Emilio López | e874a66 | 2013-02-25 11:44:26 -0300 | [diff] [blame] | 19 | #include <linux/of.h> |
| 20 | #include <linux/of_address.h> |
| 21 | |
| 22 | #include "clk-factors.h" |
| 23 | |
| 24 | static DEFINE_SPINLOCK(clk_lock); |
| 25 | |
Emilio López | 40a5dcb | 2013-12-23 00:32:32 -0300 | [diff] [blame] | 26 | /* Maximum number of parents our clocks have */ |
| 27 | #define SUNXI_MAX_PARENTS 5 |
| 28 | |
Emilio López | e874a66 | 2013-02-25 11:44:26 -0300 | [diff] [blame] | 29 | /** |
Maxime Ripard | 81ba6c5 | 2013-07-22 18:21:32 +0200 | [diff] [blame] | 30 | * sun4i_osc_clk_setup() - Setup function for gatable oscillator |
Emilio López | e874a66 | 2013-02-25 11:44:26 -0300 | [diff] [blame] | 31 | */ |
| 32 | |
| 33 | #define SUNXI_OSC24M_GATE 0 |
| 34 | |
Maxime Ripard | 81ba6c5 | 2013-07-22 18:21:32 +0200 | [diff] [blame] | 35 | static void __init sun4i_osc_clk_setup(struct device_node *node) |
Emilio López | e874a66 | 2013-02-25 11:44:26 -0300 | [diff] [blame] | 36 | { |
| 37 | struct clk *clk; |
Emilio López | 38e4aa0 | 2013-04-10 15:02:57 -0700 | [diff] [blame] | 38 | struct clk_fixed_rate *fixed; |
| 39 | struct clk_gate *gate; |
Emilio López | e874a66 | 2013-02-25 11:44:26 -0300 | [diff] [blame] | 40 | const char *clk_name = node->name; |
Emilio López | 38e4aa0 | 2013-04-10 15:02:57 -0700 | [diff] [blame] | 41 | u32 rate; |
Emilio López | e874a66 | 2013-02-25 11:44:26 -0300 | [diff] [blame] | 42 | |
Victor N. Ramos Mello | e71c69f | 2013-10-18 20:27:51 -0300 | [diff] [blame] | 43 | if (of_property_read_u32(node, "clock-frequency", &rate)) |
| 44 | return; |
| 45 | |
Emilio López | 38e4aa0 | 2013-04-10 15:02:57 -0700 | [diff] [blame] | 46 | /* allocate fixed-rate and gate clock structs */ |
| 47 | fixed = kzalloc(sizeof(struct clk_fixed_rate), GFP_KERNEL); |
| 48 | if (!fixed) |
| 49 | return; |
| 50 | gate = kzalloc(sizeof(struct clk_gate), GFP_KERNEL); |
Victor N. Ramos Mello | e71c69f | 2013-10-18 20:27:51 -0300 | [diff] [blame] | 51 | if (!gate) |
| 52 | goto err_free_fixed; |
Emilio López | e874a66 | 2013-02-25 11:44:26 -0300 | [diff] [blame] | 53 | |
Emilio López | 38e4aa0 | 2013-04-10 15:02:57 -0700 | [diff] [blame] | 54 | /* set up gate and fixed rate properties */ |
| 55 | gate->reg = of_iomap(node, 0); |
| 56 | gate->bit_idx = SUNXI_OSC24M_GATE; |
| 57 | gate->lock = &clk_lock; |
| 58 | fixed->fixed_rate = rate; |
| 59 | |
| 60 | clk = clk_register_composite(NULL, clk_name, |
| 61 | NULL, 0, |
| 62 | NULL, NULL, |
| 63 | &fixed->hw, &clk_fixed_rate_ops, |
| 64 | &gate->hw, &clk_gate_ops, |
| 65 | CLK_IS_ROOT); |
Emilio López | e874a66 | 2013-02-25 11:44:26 -0300 | [diff] [blame] | 66 | |
Victor N. Ramos Mello | e71c69f | 2013-10-18 20:27:51 -0300 | [diff] [blame] | 67 | if (IS_ERR(clk)) |
| 68 | goto err_free_gate; |
| 69 | |
| 70 | of_clk_add_provider(node, of_clk_src_simple_get, clk); |
| 71 | clk_register_clkdev(clk, clk_name, NULL); |
| 72 | |
| 73 | return; |
| 74 | |
| 75 | err_free_gate: |
| 76 | kfree(gate); |
| 77 | err_free_fixed: |
| 78 | kfree(fixed); |
Emilio López | e874a66 | 2013-02-25 11:44:26 -0300 | [diff] [blame] | 79 | } |
Maxime Ripard | 81ba6c5 | 2013-07-22 18:21:32 +0200 | [diff] [blame] | 80 | CLK_OF_DECLARE(sun4i_osc, "allwinner,sun4i-osc-clk", sun4i_osc_clk_setup); |
Emilio López | e874a66 | 2013-02-25 11:44:26 -0300 | [diff] [blame] | 81 | |
| 82 | |
| 83 | |
| 84 | /** |
Maxime Ripard | 81ba6c5 | 2013-07-22 18:21:32 +0200 | [diff] [blame] | 85 | * sun4i_get_pll1_factors() - calculates n, k, m, p factors for PLL1 |
Emilio López | e874a66 | 2013-02-25 11:44:26 -0300 | [diff] [blame] | 86 | * PLL1 rate is calculated as follows |
| 87 | * rate = (parent_rate * n * (k + 1) >> p) / (m + 1); |
| 88 | * parent_rate is always 24Mhz |
| 89 | */ |
| 90 | |
Maxime Ripard | 81ba6c5 | 2013-07-22 18:21:32 +0200 | [diff] [blame] | 91 | static void sun4i_get_pll1_factors(u32 *freq, u32 parent_rate, |
Emilio López | e874a66 | 2013-02-25 11:44:26 -0300 | [diff] [blame] | 92 | u8 *n, u8 *k, u8 *m, u8 *p) |
| 93 | { |
| 94 | u8 div; |
| 95 | |
| 96 | /* Normalize value to a 6M multiple */ |
| 97 | div = *freq / 6000000; |
| 98 | *freq = 6000000 * div; |
| 99 | |
| 100 | /* we were called to round the frequency, we can now return */ |
| 101 | if (n == NULL) |
| 102 | return; |
| 103 | |
| 104 | /* m is always zero for pll1 */ |
| 105 | *m = 0; |
| 106 | |
| 107 | /* k is 1 only on these cases */ |
| 108 | if (*freq >= 768000000 || *freq == 42000000 || *freq == 54000000) |
| 109 | *k = 1; |
| 110 | else |
| 111 | *k = 0; |
| 112 | |
| 113 | /* p will be 3 for divs under 10 */ |
| 114 | if (div < 10) |
| 115 | *p = 3; |
| 116 | |
| 117 | /* p will be 2 for divs between 10 - 20 and odd divs under 32 */ |
| 118 | else if (div < 20 || (div < 32 && (div & 1))) |
| 119 | *p = 2; |
| 120 | |
| 121 | /* p will be 1 for even divs under 32, divs under 40 and odd pairs |
| 122 | * of divs between 40-62 */ |
| 123 | else if (div < 40 || (div < 64 && (div & 2))) |
| 124 | *p = 1; |
| 125 | |
| 126 | /* any other entries have p = 0 */ |
| 127 | else |
| 128 | *p = 0; |
| 129 | |
| 130 | /* calculate a suitable n based on k and p */ |
| 131 | div <<= *p; |
| 132 | div /= (*k + 1); |
| 133 | *n = div / 4; |
| 134 | } |
| 135 | |
Maxime Ripard | 6a721db | 2013-07-23 23:34:10 +0200 | [diff] [blame] | 136 | /** |
| 137 | * sun6i_a31_get_pll1_factors() - calculates n, k and m factors for PLL1 |
| 138 | * PLL1 rate is calculated as follows |
| 139 | * rate = parent_rate * (n + 1) * (k + 1) / (m + 1); |
| 140 | * parent_rate should always be 24MHz |
| 141 | */ |
| 142 | static void sun6i_a31_get_pll1_factors(u32 *freq, u32 parent_rate, |
| 143 | u8 *n, u8 *k, u8 *m, u8 *p) |
| 144 | { |
| 145 | /* |
| 146 | * We can operate only on MHz, this will make our life easier |
| 147 | * later. |
| 148 | */ |
| 149 | u32 freq_mhz = *freq / 1000000; |
| 150 | u32 parent_freq_mhz = parent_rate / 1000000; |
Emilio López | e874a66 | 2013-02-25 11:44:26 -0300 | [diff] [blame] | 151 | |
Maxime Ripard | 6a721db | 2013-07-23 23:34:10 +0200 | [diff] [blame] | 152 | /* |
| 153 | * Round down the frequency to the closest multiple of either |
| 154 | * 6 or 16 |
| 155 | */ |
| 156 | u32 round_freq_6 = round_down(freq_mhz, 6); |
| 157 | u32 round_freq_16 = round_down(freq_mhz, 16); |
| 158 | |
| 159 | if (round_freq_6 > round_freq_16) |
| 160 | freq_mhz = round_freq_6; |
| 161 | else |
| 162 | freq_mhz = round_freq_16; |
| 163 | |
| 164 | *freq = freq_mhz * 1000000; |
| 165 | |
| 166 | /* |
| 167 | * If the factors pointer are null, we were just called to |
| 168 | * round down the frequency. |
| 169 | * Exit. |
| 170 | */ |
| 171 | if (n == NULL) |
| 172 | return; |
| 173 | |
| 174 | /* If the frequency is a multiple of 32 MHz, k is always 3 */ |
| 175 | if (!(freq_mhz % 32)) |
| 176 | *k = 3; |
| 177 | /* If the frequency is a multiple of 9 MHz, k is always 2 */ |
| 178 | else if (!(freq_mhz % 9)) |
| 179 | *k = 2; |
| 180 | /* If the frequency is a multiple of 8 MHz, k is always 1 */ |
| 181 | else if (!(freq_mhz % 8)) |
| 182 | *k = 1; |
| 183 | /* Otherwise, we don't use the k factor */ |
| 184 | else |
| 185 | *k = 0; |
| 186 | |
| 187 | /* |
| 188 | * If the frequency is a multiple of 2 but not a multiple of |
| 189 | * 3, m is 3. This is the first time we use 6 here, yet we |
| 190 | * will use it on several other places. |
| 191 | * We use this number because it's the lowest frequency we can |
| 192 | * generate (with n = 0, k = 0, m = 3), so every other frequency |
| 193 | * somehow relates to this frequency. |
| 194 | */ |
| 195 | if ((freq_mhz % 6) == 2 || (freq_mhz % 6) == 4) |
| 196 | *m = 2; |
| 197 | /* |
| 198 | * If the frequency is a multiple of 6MHz, but the factor is |
| 199 | * odd, m will be 3 |
| 200 | */ |
| 201 | else if ((freq_mhz / 6) & 1) |
| 202 | *m = 3; |
| 203 | /* Otherwise, we end up with m = 1 */ |
| 204 | else |
| 205 | *m = 1; |
| 206 | |
| 207 | /* Calculate n thanks to the above factors we already got */ |
| 208 | *n = freq_mhz * (*m + 1) / ((*k + 1) * parent_freq_mhz) - 1; |
| 209 | |
| 210 | /* |
| 211 | * If n end up being outbound, and that we can still decrease |
| 212 | * m, do it. |
| 213 | */ |
| 214 | if ((*n + 1) > 31 && (*m + 1) > 1) { |
| 215 | *n = (*n + 1) / 2 - 1; |
| 216 | *m = (*m + 1) / 2 - 1; |
| 217 | } |
| 218 | } |
Emilio López | e874a66 | 2013-02-25 11:44:26 -0300 | [diff] [blame] | 219 | |
| 220 | /** |
Emilio López | d584c13 | 2013-12-23 00:32:37 -0300 | [diff] [blame] | 221 | * sun4i_get_pll5_factors() - calculates n, k factors for PLL5 |
| 222 | * PLL5 rate is calculated as follows |
| 223 | * rate = parent_rate * n * (k + 1) |
| 224 | * parent_rate is always 24Mhz |
| 225 | */ |
| 226 | |
| 227 | static void sun4i_get_pll5_factors(u32 *freq, u32 parent_rate, |
| 228 | u8 *n, u8 *k, u8 *m, u8 *p) |
| 229 | { |
| 230 | u8 div; |
| 231 | |
| 232 | /* Normalize value to a parent_rate multiple (24M) */ |
| 233 | div = *freq / parent_rate; |
| 234 | *freq = parent_rate * div; |
| 235 | |
| 236 | /* we were called to round the frequency, we can now return */ |
| 237 | if (n == NULL) |
| 238 | return; |
| 239 | |
| 240 | if (div < 31) |
| 241 | *k = 0; |
| 242 | else if (div / 2 < 31) |
| 243 | *k = 1; |
| 244 | else if (div / 3 < 31) |
| 245 | *k = 2; |
| 246 | else |
| 247 | *k = 3; |
| 248 | |
| 249 | *n = DIV_ROUND_UP(div, (*k+1)); |
| 250 | } |
| 251 | |
| 252 | |
| 253 | |
| 254 | /** |
Maxime Ripard | 81ba6c5 | 2013-07-22 18:21:32 +0200 | [diff] [blame] | 255 | * sun4i_get_apb1_factors() - calculates m, p factors for APB1 |
Emilio López | e874a66 | 2013-02-25 11:44:26 -0300 | [diff] [blame] | 256 | * APB1 rate is calculated as follows |
| 257 | * rate = (parent_rate >> p) / (m + 1); |
| 258 | */ |
| 259 | |
Maxime Ripard | 81ba6c5 | 2013-07-22 18:21:32 +0200 | [diff] [blame] | 260 | static void sun4i_get_apb1_factors(u32 *freq, u32 parent_rate, |
Emilio López | e874a66 | 2013-02-25 11:44:26 -0300 | [diff] [blame] | 261 | u8 *n, u8 *k, u8 *m, u8 *p) |
| 262 | { |
| 263 | u8 calcm, calcp; |
| 264 | |
| 265 | if (parent_rate < *freq) |
| 266 | *freq = parent_rate; |
| 267 | |
| 268 | parent_rate = (parent_rate + (*freq - 1)) / *freq; |
| 269 | |
| 270 | /* Invalid rate! */ |
| 271 | if (parent_rate > 32) |
| 272 | return; |
| 273 | |
| 274 | if (parent_rate <= 4) |
| 275 | calcp = 0; |
| 276 | else if (parent_rate <= 8) |
| 277 | calcp = 1; |
| 278 | else if (parent_rate <= 16) |
| 279 | calcp = 2; |
| 280 | else |
| 281 | calcp = 3; |
| 282 | |
| 283 | calcm = (parent_rate >> calcp) - 1; |
| 284 | |
| 285 | *freq = (parent_rate >> calcp) / (calcm + 1); |
| 286 | |
| 287 | /* we were called to round the frequency, we can now return */ |
| 288 | if (n == NULL) |
| 289 | return; |
| 290 | |
| 291 | *m = calcm; |
| 292 | *p = calcp; |
| 293 | } |
| 294 | |
| 295 | |
| 296 | |
| 297 | /** |
Emilio López | 7551769 | 2013-12-23 00:32:39 -0300 | [diff] [blame^] | 298 | * sun4i_get_mod0_factors() - calculates m, n factors for MOD0-style clocks |
| 299 | * MMC rate is calculated as follows |
| 300 | * rate = (parent_rate >> p) / (m + 1); |
| 301 | */ |
| 302 | |
| 303 | static void sun4i_get_mod0_factors(u32 *freq, u32 parent_rate, |
| 304 | u8 *n, u8 *k, u8 *m, u8 *p) |
| 305 | { |
| 306 | u8 div, calcm, calcp; |
| 307 | |
| 308 | /* These clocks can only divide, so we will never be able to achieve |
| 309 | * frequencies higher than the parent frequency */ |
| 310 | if (*freq > parent_rate) |
| 311 | *freq = parent_rate; |
| 312 | |
| 313 | div = parent_rate / *freq; |
| 314 | |
| 315 | if (div < 16) |
| 316 | calcp = 0; |
| 317 | else if (div / 2 < 16) |
| 318 | calcp = 1; |
| 319 | else if (div / 4 < 16) |
| 320 | calcp = 2; |
| 321 | else |
| 322 | calcp = 3; |
| 323 | |
| 324 | calcm = DIV_ROUND_UP(div, 1 << calcp); |
| 325 | |
| 326 | *freq = (parent_rate >> calcp) / calcm; |
| 327 | |
| 328 | /* we were called to round the frequency, we can now return */ |
| 329 | if (n == NULL) |
| 330 | return; |
| 331 | |
| 332 | *m = calcm - 1; |
| 333 | *p = calcp; |
| 334 | } |
| 335 | |
| 336 | |
| 337 | |
| 338 | /** |
Emilio López | e874a66 | 2013-02-25 11:44:26 -0300 | [diff] [blame] | 339 | * sunxi_factors_clk_setup() - Setup function for factor clocks |
| 340 | */ |
| 341 | |
Emilio López | 40a5dcb | 2013-12-23 00:32:32 -0300 | [diff] [blame] | 342 | #define SUNXI_FACTORS_MUX_MASK 0x3 |
| 343 | |
Emilio López | e874a66 | 2013-02-25 11:44:26 -0300 | [diff] [blame] | 344 | struct factors_data { |
Emilio López | 40a5dcb | 2013-12-23 00:32:32 -0300 | [diff] [blame] | 345 | int enable; |
| 346 | int mux; |
Emilio López | e874a66 | 2013-02-25 11:44:26 -0300 | [diff] [blame] | 347 | struct clk_factors_config *table; |
| 348 | void (*getter) (u32 *rate, u32 parent_rate, u8 *n, u8 *k, u8 *m, u8 *p); |
| 349 | }; |
| 350 | |
Maxime Ripard | 81ba6c5 | 2013-07-22 18:21:32 +0200 | [diff] [blame] | 351 | static struct clk_factors_config sun4i_pll1_config = { |
Emilio López | e874a66 | 2013-02-25 11:44:26 -0300 | [diff] [blame] | 352 | .nshift = 8, |
| 353 | .nwidth = 5, |
| 354 | .kshift = 4, |
| 355 | .kwidth = 2, |
| 356 | .mshift = 0, |
| 357 | .mwidth = 2, |
| 358 | .pshift = 16, |
| 359 | .pwidth = 2, |
| 360 | }; |
| 361 | |
Maxime Ripard | 6a721db | 2013-07-23 23:34:10 +0200 | [diff] [blame] | 362 | static struct clk_factors_config sun6i_a31_pll1_config = { |
| 363 | .nshift = 8, |
| 364 | .nwidth = 5, |
| 365 | .kshift = 4, |
| 366 | .kwidth = 2, |
| 367 | .mshift = 0, |
| 368 | .mwidth = 2, |
| 369 | }; |
| 370 | |
Emilio López | d584c13 | 2013-12-23 00:32:37 -0300 | [diff] [blame] | 371 | static struct clk_factors_config sun4i_pll5_config = { |
| 372 | .nshift = 8, |
| 373 | .nwidth = 5, |
| 374 | .kshift = 4, |
| 375 | .kwidth = 2, |
| 376 | }; |
| 377 | |
Maxime Ripard | 81ba6c5 | 2013-07-22 18:21:32 +0200 | [diff] [blame] | 378 | static struct clk_factors_config sun4i_apb1_config = { |
Emilio López | e874a66 | 2013-02-25 11:44:26 -0300 | [diff] [blame] | 379 | .mshift = 0, |
| 380 | .mwidth = 5, |
| 381 | .pshift = 16, |
| 382 | .pwidth = 2, |
| 383 | }; |
| 384 | |
Emilio López | 7551769 | 2013-12-23 00:32:39 -0300 | [diff] [blame^] | 385 | /* user manual says "n" but it's really "p" */ |
| 386 | static struct clk_factors_config sun4i_mod0_config = { |
| 387 | .mshift = 0, |
| 388 | .mwidth = 4, |
| 389 | .pshift = 16, |
| 390 | .pwidth = 2, |
| 391 | }; |
| 392 | |
Sachin Kamat | 52be7cc | 2013-08-12 14:44:06 +0530 | [diff] [blame] | 393 | static const struct factors_data sun4i_pll1_data __initconst = { |
Emilio López | d838ff3 | 2013-12-23 00:32:34 -0300 | [diff] [blame] | 394 | .enable = 31, |
Maxime Ripard | 81ba6c5 | 2013-07-22 18:21:32 +0200 | [diff] [blame] | 395 | .table = &sun4i_pll1_config, |
| 396 | .getter = sun4i_get_pll1_factors, |
Emilio López | e874a66 | 2013-02-25 11:44:26 -0300 | [diff] [blame] | 397 | }; |
| 398 | |
Sachin Kamat | 52be7cc | 2013-08-12 14:44:06 +0530 | [diff] [blame] | 399 | static const struct factors_data sun6i_a31_pll1_data __initconst = { |
Emilio López | d838ff3 | 2013-12-23 00:32:34 -0300 | [diff] [blame] | 400 | .enable = 31, |
Maxime Ripard | 6a721db | 2013-07-23 23:34:10 +0200 | [diff] [blame] | 401 | .table = &sun6i_a31_pll1_config, |
| 402 | .getter = sun6i_a31_get_pll1_factors, |
| 403 | }; |
| 404 | |
Emilio López | d584c13 | 2013-12-23 00:32:37 -0300 | [diff] [blame] | 405 | static const struct factors_data sun4i_pll5_data __initconst = { |
| 406 | .enable = 31, |
| 407 | .table = &sun4i_pll5_config, |
| 408 | .getter = sun4i_get_pll5_factors, |
| 409 | }; |
| 410 | |
Sachin Kamat | 52be7cc | 2013-08-12 14:44:06 +0530 | [diff] [blame] | 411 | static const struct factors_data sun4i_apb1_data __initconst = { |
Maxime Ripard | 81ba6c5 | 2013-07-22 18:21:32 +0200 | [diff] [blame] | 412 | .table = &sun4i_apb1_config, |
| 413 | .getter = sun4i_get_apb1_factors, |
Emilio López | e874a66 | 2013-02-25 11:44:26 -0300 | [diff] [blame] | 414 | }; |
| 415 | |
Emilio López | 7551769 | 2013-12-23 00:32:39 -0300 | [diff] [blame^] | 416 | static const struct factors_data sun4i_mod0_data __initconst = { |
| 417 | .enable = 31, |
| 418 | .mux = 24, |
| 419 | .table = &sun4i_mod0_config, |
| 420 | .getter = sun4i_get_mod0_factors, |
| 421 | }; |
| 422 | |
Emilio López | 5f4e0be | 2013-12-23 00:32:36 -0300 | [diff] [blame] | 423 | static struct clk * __init sunxi_factors_clk_setup(struct device_node *node, |
| 424 | const struct factors_data *data) |
Emilio López | e874a66 | 2013-02-25 11:44:26 -0300 | [diff] [blame] | 425 | { |
| 426 | struct clk *clk; |
Emilio López | 40a5dcb | 2013-12-23 00:32:32 -0300 | [diff] [blame] | 427 | struct clk_factors *factors; |
| 428 | struct clk_gate *gate = NULL; |
| 429 | struct clk_mux *mux = NULL; |
| 430 | struct clk_hw *gate_hw = NULL; |
| 431 | struct clk_hw *mux_hw = NULL; |
Emilio López | e874a66 | 2013-02-25 11:44:26 -0300 | [diff] [blame] | 432 | const char *clk_name = node->name; |
Emilio López | 40a5dcb | 2013-12-23 00:32:32 -0300 | [diff] [blame] | 433 | const char *parents[SUNXI_MAX_PARENTS]; |
Emilio López | e874a66 | 2013-02-25 11:44:26 -0300 | [diff] [blame] | 434 | void *reg; |
Emilio López | 40a5dcb | 2013-12-23 00:32:32 -0300 | [diff] [blame] | 435 | int i = 0; |
Emilio López | e874a66 | 2013-02-25 11:44:26 -0300 | [diff] [blame] | 436 | |
| 437 | reg = of_iomap(node, 0); |
| 438 | |
Emilio López | 40a5dcb | 2013-12-23 00:32:32 -0300 | [diff] [blame] | 439 | /* if we have a mux, we will have >1 parents */ |
| 440 | while (i < SUNXI_MAX_PARENTS && |
| 441 | (parents[i] = of_clk_get_parent_name(node, i)) != NULL) |
| 442 | i++; |
Emilio López | e874a66 | 2013-02-25 11:44:26 -0300 | [diff] [blame] | 443 | |
Emilio López | 40a5dcb | 2013-12-23 00:32:32 -0300 | [diff] [blame] | 444 | factors = kzalloc(sizeof(struct clk_factors), GFP_KERNEL); |
| 445 | if (!factors) |
Emilio López | 5f4e0be | 2013-12-23 00:32:36 -0300 | [diff] [blame] | 446 | return NULL; |
Emilio López | 40a5dcb | 2013-12-23 00:32:32 -0300 | [diff] [blame] | 447 | |
| 448 | /* Add a gate if this factor clock can be gated */ |
| 449 | if (data->enable) { |
| 450 | gate = kzalloc(sizeof(struct clk_gate), GFP_KERNEL); |
| 451 | if (!gate) { |
| 452 | kfree(factors); |
Emilio López | 5f4e0be | 2013-12-23 00:32:36 -0300 | [diff] [blame] | 453 | return NULL; |
Emilio López | 40a5dcb | 2013-12-23 00:32:32 -0300 | [diff] [blame] | 454 | } |
| 455 | |
| 456 | /* set up gate properties */ |
| 457 | gate->reg = reg; |
| 458 | gate->bit_idx = data->enable; |
| 459 | gate->lock = &clk_lock; |
| 460 | gate_hw = &gate->hw; |
| 461 | } |
| 462 | |
| 463 | /* Add a mux if this factor clock can be muxed */ |
| 464 | if (data->mux) { |
| 465 | mux = kzalloc(sizeof(struct clk_mux), GFP_KERNEL); |
| 466 | if (!mux) { |
| 467 | kfree(factors); |
| 468 | kfree(gate); |
Emilio López | 5f4e0be | 2013-12-23 00:32:36 -0300 | [diff] [blame] | 469 | return NULL; |
Emilio López | 40a5dcb | 2013-12-23 00:32:32 -0300 | [diff] [blame] | 470 | } |
| 471 | |
| 472 | /* set up gate properties */ |
| 473 | mux->reg = reg; |
| 474 | mux->shift = data->mux; |
| 475 | mux->mask = SUNXI_FACTORS_MUX_MASK; |
| 476 | mux->lock = &clk_lock; |
| 477 | mux_hw = &mux->hw; |
| 478 | } |
| 479 | |
| 480 | /* set up factors properties */ |
| 481 | factors->reg = reg; |
| 482 | factors->config = data->table; |
| 483 | factors->get_factors = data->getter; |
| 484 | factors->lock = &clk_lock; |
| 485 | |
| 486 | clk = clk_register_composite(NULL, clk_name, |
| 487 | parents, i, |
| 488 | mux_hw, &clk_mux_ops, |
| 489 | &factors->hw, &clk_factors_ops, |
Emilio López | 5f4e0be | 2013-12-23 00:32:36 -0300 | [diff] [blame] | 490 | gate_hw, &clk_gate_ops, 0); |
Emilio López | e874a66 | 2013-02-25 11:44:26 -0300 | [diff] [blame] | 491 | |
Axel Lin | ee85e9b | 2013-07-12 16:15:15 +0800 | [diff] [blame] | 492 | if (!IS_ERR(clk)) { |
Emilio López | e874a66 | 2013-02-25 11:44:26 -0300 | [diff] [blame] | 493 | of_clk_add_provider(node, of_clk_src_simple_get, clk); |
| 494 | clk_register_clkdev(clk, clk_name, NULL); |
| 495 | } |
Emilio López | 5f4e0be | 2013-12-23 00:32:36 -0300 | [diff] [blame] | 496 | |
| 497 | return clk; |
Emilio López | e874a66 | 2013-02-25 11:44:26 -0300 | [diff] [blame] | 498 | } |
| 499 | |
| 500 | |
| 501 | |
| 502 | /** |
| 503 | * sunxi_mux_clk_setup() - Setup function for muxes |
| 504 | */ |
| 505 | |
| 506 | #define SUNXI_MUX_GATE_WIDTH 2 |
| 507 | |
| 508 | struct mux_data { |
| 509 | u8 shift; |
| 510 | }; |
| 511 | |
Sachin Kamat | 52be7cc | 2013-08-12 14:44:06 +0530 | [diff] [blame] | 512 | static const struct mux_data sun4i_cpu_mux_data __initconst = { |
Emilio López | e874a66 | 2013-02-25 11:44:26 -0300 | [diff] [blame] | 513 | .shift = 16, |
| 514 | }; |
| 515 | |
Sachin Kamat | 52be7cc | 2013-08-12 14:44:06 +0530 | [diff] [blame] | 516 | static const struct mux_data sun6i_a31_ahb1_mux_data __initconst = { |
Maxime Ripard | 6a721db | 2013-07-23 23:34:10 +0200 | [diff] [blame] | 517 | .shift = 12, |
| 518 | }; |
| 519 | |
Sachin Kamat | 52be7cc | 2013-08-12 14:44:06 +0530 | [diff] [blame] | 520 | static const struct mux_data sun4i_apb1_mux_data __initconst = { |
Emilio López | e874a66 | 2013-02-25 11:44:26 -0300 | [diff] [blame] | 521 | .shift = 24, |
| 522 | }; |
| 523 | |
| 524 | static void __init sunxi_mux_clk_setup(struct device_node *node, |
| 525 | struct mux_data *data) |
| 526 | { |
| 527 | struct clk *clk; |
| 528 | const char *clk_name = node->name; |
Emilio López | edaf3fb | 2013-12-23 00:32:33 -0300 | [diff] [blame] | 529 | const char *parents[SUNXI_MAX_PARENTS]; |
Emilio López | e874a66 | 2013-02-25 11:44:26 -0300 | [diff] [blame] | 530 | void *reg; |
| 531 | int i = 0; |
| 532 | |
| 533 | reg = of_iomap(node, 0); |
| 534 | |
Emilio López | edaf3fb | 2013-12-23 00:32:33 -0300 | [diff] [blame] | 535 | while (i < SUNXI_MAX_PARENTS && |
| 536 | (parents[i] = of_clk_get_parent_name(node, i)) != NULL) |
Emilio López | e874a66 | 2013-02-25 11:44:26 -0300 | [diff] [blame] | 537 | i++; |
| 538 | |
James Hogan | 819c1de | 2013-07-29 12:25:01 +0100 | [diff] [blame] | 539 | clk = clk_register_mux(NULL, clk_name, parents, i, |
| 540 | CLK_SET_RATE_NO_REPARENT, reg, |
Emilio López | e874a66 | 2013-02-25 11:44:26 -0300 | [diff] [blame] | 541 | data->shift, SUNXI_MUX_GATE_WIDTH, |
| 542 | 0, &clk_lock); |
| 543 | |
| 544 | if (clk) { |
| 545 | of_clk_add_provider(node, of_clk_src_simple_get, clk); |
| 546 | clk_register_clkdev(clk, clk_name, NULL); |
| 547 | } |
| 548 | } |
| 549 | |
| 550 | |
| 551 | |
| 552 | /** |
| 553 | * sunxi_divider_clk_setup() - Setup function for simple divider clocks |
| 554 | */ |
| 555 | |
Emilio López | e874a66 | 2013-02-25 11:44:26 -0300 | [diff] [blame] | 556 | struct div_data { |
Maxime Ripard | 70855bb | 2013-07-23 09:25:56 +0200 | [diff] [blame] | 557 | u8 shift; |
| 558 | u8 pow; |
| 559 | u8 width; |
Emilio López | e874a66 | 2013-02-25 11:44:26 -0300 | [diff] [blame] | 560 | }; |
| 561 | |
Sachin Kamat | 52be7cc | 2013-08-12 14:44:06 +0530 | [diff] [blame] | 562 | static const struct div_data sun4i_axi_data __initconst = { |
Maxime Ripard | 70855bb | 2013-07-23 09:25:56 +0200 | [diff] [blame] | 563 | .shift = 0, |
| 564 | .pow = 0, |
| 565 | .width = 2, |
Emilio López | e874a66 | 2013-02-25 11:44:26 -0300 | [diff] [blame] | 566 | }; |
| 567 | |
Sachin Kamat | 52be7cc | 2013-08-12 14:44:06 +0530 | [diff] [blame] | 568 | static const struct div_data sun4i_ahb_data __initconst = { |
Maxime Ripard | 70855bb | 2013-07-23 09:25:56 +0200 | [diff] [blame] | 569 | .shift = 4, |
| 570 | .pow = 1, |
| 571 | .width = 2, |
Emilio López | e874a66 | 2013-02-25 11:44:26 -0300 | [diff] [blame] | 572 | }; |
| 573 | |
Sachin Kamat | 52be7cc | 2013-08-12 14:44:06 +0530 | [diff] [blame] | 574 | static const struct div_data sun4i_apb0_data __initconst = { |
Maxime Ripard | 70855bb | 2013-07-23 09:25:56 +0200 | [diff] [blame] | 575 | .shift = 8, |
| 576 | .pow = 1, |
| 577 | .width = 2, |
Emilio López | e874a66 | 2013-02-25 11:44:26 -0300 | [diff] [blame] | 578 | }; |
| 579 | |
Sachin Kamat | 52be7cc | 2013-08-12 14:44:06 +0530 | [diff] [blame] | 580 | static const struct div_data sun6i_a31_apb2_div_data __initconst = { |
Maxime Ripard | 6a721db | 2013-07-23 23:34:10 +0200 | [diff] [blame] | 581 | .shift = 0, |
| 582 | .pow = 0, |
| 583 | .width = 4, |
| 584 | }; |
| 585 | |
Emilio López | e874a66 | 2013-02-25 11:44:26 -0300 | [diff] [blame] | 586 | static void __init sunxi_divider_clk_setup(struct device_node *node, |
| 587 | struct div_data *data) |
| 588 | { |
| 589 | struct clk *clk; |
| 590 | const char *clk_name = node->name; |
| 591 | const char *clk_parent; |
| 592 | void *reg; |
| 593 | |
| 594 | reg = of_iomap(node, 0); |
| 595 | |
| 596 | clk_parent = of_clk_get_parent_name(node, 0); |
| 597 | |
| 598 | clk = clk_register_divider(NULL, clk_name, clk_parent, 0, |
Maxime Ripard | 70855bb | 2013-07-23 09:25:56 +0200 | [diff] [blame] | 599 | reg, data->shift, data->width, |
Emilio López | e874a66 | 2013-02-25 11:44:26 -0300 | [diff] [blame] | 600 | data->pow ? CLK_DIVIDER_POWER_OF_TWO : 0, |
| 601 | &clk_lock); |
| 602 | if (clk) { |
| 603 | of_clk_add_provider(node, of_clk_src_simple_get, clk); |
| 604 | clk_register_clkdev(clk, clk_name, NULL); |
| 605 | } |
| 606 | } |
| 607 | |
| 608 | |
Emilio López | 13569a7 | 2013-03-27 18:20:37 -0300 | [diff] [blame] | 609 | |
| 610 | /** |
| 611 | * sunxi_gates_clk_setup() - Setup function for leaf gates on clocks |
| 612 | */ |
| 613 | |
| 614 | #define SUNXI_GATES_MAX_SIZE 64 |
| 615 | |
| 616 | struct gates_data { |
| 617 | DECLARE_BITMAP(mask, SUNXI_GATES_MAX_SIZE); |
| 618 | }; |
| 619 | |
Sachin Kamat | 52be7cc | 2013-08-12 14:44:06 +0530 | [diff] [blame] | 620 | static const struct gates_data sun4i_axi_gates_data __initconst = { |
Emilio López | 13569a7 | 2013-03-27 18:20:37 -0300 | [diff] [blame] | 621 | .mask = {1}, |
| 622 | }; |
| 623 | |
Sachin Kamat | 52be7cc | 2013-08-12 14:44:06 +0530 | [diff] [blame] | 624 | static const struct gates_data sun4i_ahb_gates_data __initconst = { |
Emilio López | 13569a7 | 2013-03-27 18:20:37 -0300 | [diff] [blame] | 625 | .mask = {0x7F77FFF, 0x14FB3F}, |
| 626 | }; |
| 627 | |
Sachin Kamat | 52be7cc | 2013-08-12 14:44:06 +0530 | [diff] [blame] | 628 | static const struct gates_data sun5i_a10s_ahb_gates_data __initconst = { |
Maxime Ripard | 2371dd8 | 2013-07-16 11:21:59 +0200 | [diff] [blame] | 629 | .mask = {0x147667e7, 0x185915}, |
| 630 | }; |
| 631 | |
Sachin Kamat | 52be7cc | 2013-08-12 14:44:06 +0530 | [diff] [blame] | 632 | static const struct gates_data sun5i_a13_ahb_gates_data __initconst = { |
Maxime Ripard | 4f985b4 | 2013-04-30 11:56:22 +0200 | [diff] [blame] | 633 | .mask = {0x107067e7, 0x185111}, |
| 634 | }; |
| 635 | |
Sachin Kamat | 52be7cc | 2013-08-12 14:44:06 +0530 | [diff] [blame] | 636 | static const struct gates_data sun6i_a31_ahb1_gates_data __initconst = { |
Maxime Ripard | 6a721db | 2013-07-23 23:34:10 +0200 | [diff] [blame] | 637 | .mask = {0xEDFE7F62, 0x794F931}, |
| 638 | }; |
| 639 | |
Sachin Kamat | 52be7cc | 2013-08-12 14:44:06 +0530 | [diff] [blame] | 640 | static const struct gates_data sun7i_a20_ahb_gates_data __initconst = { |
Maxime Ripard | 1fb2e4a | 2013-07-25 21:06:56 +0200 | [diff] [blame] | 641 | .mask = { 0x12f77fff, 0x16ff3f }, |
| 642 | }; |
| 643 | |
Sachin Kamat | 52be7cc | 2013-08-12 14:44:06 +0530 | [diff] [blame] | 644 | static const struct gates_data sun4i_apb0_gates_data __initconst = { |
Emilio López | 13569a7 | 2013-03-27 18:20:37 -0300 | [diff] [blame] | 645 | .mask = {0x4EF}, |
| 646 | }; |
| 647 | |
Sachin Kamat | 52be7cc | 2013-08-12 14:44:06 +0530 | [diff] [blame] | 648 | static const struct gates_data sun5i_a10s_apb0_gates_data __initconst = { |
Maxime Ripard | 2371dd8 | 2013-07-16 11:21:59 +0200 | [diff] [blame] | 649 | .mask = {0x469}, |
| 650 | }; |
| 651 | |
Sachin Kamat | 52be7cc | 2013-08-12 14:44:06 +0530 | [diff] [blame] | 652 | static const struct gates_data sun5i_a13_apb0_gates_data __initconst = { |
Maxime Ripard | 4f985b4 | 2013-04-30 11:56:22 +0200 | [diff] [blame] | 653 | .mask = {0x61}, |
| 654 | }; |
| 655 | |
Sachin Kamat | 52be7cc | 2013-08-12 14:44:06 +0530 | [diff] [blame] | 656 | static const struct gates_data sun7i_a20_apb0_gates_data __initconst = { |
Maxime Ripard | 1fb2e4a | 2013-07-25 21:06:56 +0200 | [diff] [blame] | 657 | .mask = { 0x4ff }, |
| 658 | }; |
| 659 | |
Sachin Kamat | 52be7cc | 2013-08-12 14:44:06 +0530 | [diff] [blame] | 660 | static const struct gates_data sun4i_apb1_gates_data __initconst = { |
Emilio López | 13569a7 | 2013-03-27 18:20:37 -0300 | [diff] [blame] | 661 | .mask = {0xFF00F7}, |
| 662 | }; |
| 663 | |
Sachin Kamat | 52be7cc | 2013-08-12 14:44:06 +0530 | [diff] [blame] | 664 | static const struct gates_data sun5i_a10s_apb1_gates_data __initconst = { |
Maxime Ripard | 2371dd8 | 2013-07-16 11:21:59 +0200 | [diff] [blame] | 665 | .mask = {0xf0007}, |
| 666 | }; |
| 667 | |
Sachin Kamat | 52be7cc | 2013-08-12 14:44:06 +0530 | [diff] [blame] | 668 | static const struct gates_data sun5i_a13_apb1_gates_data __initconst = { |
Maxime Ripard | 4f985b4 | 2013-04-30 11:56:22 +0200 | [diff] [blame] | 669 | .mask = {0xa0007}, |
| 670 | }; |
| 671 | |
Sachin Kamat | 52be7cc | 2013-08-12 14:44:06 +0530 | [diff] [blame] | 672 | static const struct gates_data sun6i_a31_apb1_gates_data __initconst = { |
Maxime Ripard | 6a721db | 2013-07-23 23:34:10 +0200 | [diff] [blame] | 673 | .mask = {0x3031}, |
| 674 | }; |
| 675 | |
Sachin Kamat | 52be7cc | 2013-08-12 14:44:06 +0530 | [diff] [blame] | 676 | static const struct gates_data sun6i_a31_apb2_gates_data __initconst = { |
Maxime Ripard | 6a721db | 2013-07-23 23:34:10 +0200 | [diff] [blame] | 677 | .mask = {0x3F000F}, |
| 678 | }; |
| 679 | |
Sachin Kamat | 52be7cc | 2013-08-12 14:44:06 +0530 | [diff] [blame] | 680 | static const struct gates_data sun7i_a20_apb1_gates_data __initconst = { |
Maxime Ripard | 1fb2e4a | 2013-07-25 21:06:56 +0200 | [diff] [blame] | 681 | .mask = { 0xff80ff }, |
| 682 | }; |
| 683 | |
Emilio López | 13569a7 | 2013-03-27 18:20:37 -0300 | [diff] [blame] | 684 | static void __init sunxi_gates_clk_setup(struct device_node *node, |
| 685 | struct gates_data *data) |
| 686 | { |
| 687 | struct clk_onecell_data *clk_data; |
| 688 | const char *clk_parent; |
| 689 | const char *clk_name; |
| 690 | void *reg; |
| 691 | int qty; |
| 692 | int i = 0; |
| 693 | int j = 0; |
| 694 | int ignore; |
| 695 | |
| 696 | reg = of_iomap(node, 0); |
| 697 | |
| 698 | clk_parent = of_clk_get_parent_name(node, 0); |
| 699 | |
| 700 | /* Worst-case size approximation and memory allocation */ |
| 701 | qty = find_last_bit(data->mask, SUNXI_GATES_MAX_SIZE); |
| 702 | clk_data = kmalloc(sizeof(struct clk_onecell_data), GFP_KERNEL); |
| 703 | if (!clk_data) |
| 704 | return; |
| 705 | clk_data->clks = kzalloc((qty+1) * sizeof(struct clk *), GFP_KERNEL); |
| 706 | if (!clk_data->clks) { |
| 707 | kfree(clk_data); |
| 708 | return; |
| 709 | } |
| 710 | |
| 711 | for_each_set_bit(i, data->mask, SUNXI_GATES_MAX_SIZE) { |
| 712 | of_property_read_string_index(node, "clock-output-names", |
| 713 | j, &clk_name); |
| 714 | |
| 715 | /* No driver claims this clock, but it should remain gated */ |
| 716 | ignore = !strcmp("ahb_sdram", clk_name) ? CLK_IGNORE_UNUSED : 0; |
| 717 | |
| 718 | clk_data->clks[i] = clk_register_gate(NULL, clk_name, |
| 719 | clk_parent, ignore, |
| 720 | reg + 4 * (i/32), i % 32, |
| 721 | 0, &clk_lock); |
| 722 | WARN_ON(IS_ERR(clk_data->clks[i])); |
| 723 | |
| 724 | j++; |
| 725 | } |
| 726 | |
| 727 | /* Adjust to the real max */ |
| 728 | clk_data->clk_num = i; |
| 729 | |
| 730 | of_clk_add_provider(node, of_clk_src_onecell_get, clk_data); |
| 731 | } |
| 732 | |
Emilio López | d584c13 | 2013-12-23 00:32:37 -0300 | [diff] [blame] | 733 | |
| 734 | |
| 735 | /** |
| 736 | * sunxi_divs_clk_setup() helper data |
| 737 | */ |
| 738 | |
| 739 | #define SUNXI_DIVS_MAX_QTY 2 |
| 740 | #define SUNXI_DIVISOR_WIDTH 2 |
| 741 | |
| 742 | struct divs_data { |
| 743 | const struct factors_data *factors; /* data for the factor clock */ |
| 744 | struct { |
| 745 | u8 fixed; /* is it a fixed divisor? if not... */ |
| 746 | struct clk_div_table *table; /* is it a table based divisor? */ |
| 747 | u8 shift; /* otherwise it's a normal divisor with this shift */ |
| 748 | u8 pow; /* is it power-of-two based? */ |
| 749 | u8 gate; /* is it independently gateable? */ |
| 750 | } div[SUNXI_DIVS_MAX_QTY]; |
| 751 | }; |
| 752 | |
| 753 | static struct clk_div_table pll6_sata_tbl[] = { |
| 754 | { .val = 0, .div = 6, }, |
| 755 | { .val = 1, .div = 12, }, |
| 756 | { .val = 2, .div = 18, }, |
| 757 | { .val = 3, .div = 24, }, |
| 758 | { } /* sentinel */ |
| 759 | }; |
| 760 | |
| 761 | static const struct divs_data pll5_divs_data __initconst = { |
| 762 | .factors = &sun4i_pll5_data, |
| 763 | .div = { |
| 764 | { .shift = 0, .pow = 0, }, /* M, DDR */ |
| 765 | { .shift = 16, .pow = 1, }, /* P, other */ |
| 766 | } |
| 767 | }; |
| 768 | |
| 769 | static const struct divs_data pll6_divs_data __initconst = { |
| 770 | .factors = &sun4i_pll5_data, |
| 771 | .div = { |
| 772 | { .shift = 0, .table = pll6_sata_tbl, .gate = 14 }, /* M, SATA */ |
| 773 | { .fixed = 2 }, /* P, other */ |
| 774 | } |
| 775 | }; |
| 776 | |
| 777 | /** |
| 778 | * sunxi_divs_clk_setup() - Setup function for leaf divisors on clocks |
| 779 | * |
| 780 | * These clocks look something like this |
| 781 | * ________________________ |
| 782 | * | ___divisor 1---|----> to consumer |
| 783 | * parent >--| pll___/___divisor 2---|----> to consumer |
| 784 | * | \_______________|____> to consumer |
| 785 | * |________________________| |
| 786 | */ |
| 787 | |
| 788 | static void __init sunxi_divs_clk_setup(struct device_node *node, |
| 789 | struct divs_data *data) |
| 790 | { |
| 791 | struct clk_onecell_data *clk_data; |
| 792 | const char *parent = node->name; |
| 793 | const char *clk_name; |
| 794 | struct clk **clks, *pclk; |
| 795 | struct clk_hw *gate_hw, *rate_hw; |
| 796 | const struct clk_ops *rate_ops; |
| 797 | struct clk_gate *gate = NULL; |
| 798 | struct clk_fixed_factor *fix_factor; |
| 799 | struct clk_divider *divider; |
| 800 | void *reg; |
| 801 | int i = 0; |
| 802 | int flags, clkflags; |
| 803 | |
| 804 | /* Set up factor clock that we will be dividing */ |
| 805 | pclk = sunxi_factors_clk_setup(node, data->factors); |
| 806 | |
| 807 | reg = of_iomap(node, 0); |
| 808 | |
| 809 | clk_data = kmalloc(sizeof(struct clk_onecell_data), GFP_KERNEL); |
| 810 | if (!clk_data) |
| 811 | return; |
| 812 | |
| 813 | clks = kzalloc(SUNXI_DIVS_MAX_QTY * sizeof(struct clk *), GFP_KERNEL); |
| 814 | if (!clks) |
| 815 | goto free_clkdata; |
| 816 | |
| 817 | clk_data->clks = clks; |
| 818 | |
| 819 | /* It's not a good idea to have automatic reparenting changing |
| 820 | * our RAM clock! */ |
| 821 | clkflags = !strcmp("pll5", parent) ? 0 : CLK_SET_RATE_PARENT; |
| 822 | |
| 823 | for (i = 0; i < SUNXI_DIVS_MAX_QTY; i++) { |
| 824 | if (of_property_read_string_index(node, "clock-output-names", |
| 825 | i, &clk_name) != 0) |
| 826 | break; |
| 827 | |
| 828 | gate_hw = NULL; |
| 829 | rate_hw = NULL; |
| 830 | rate_ops = NULL; |
| 831 | |
| 832 | /* If this leaf clock can be gated, create a gate */ |
| 833 | if (data->div[i].gate) { |
| 834 | gate = kzalloc(sizeof(*gate), GFP_KERNEL); |
| 835 | if (!gate) |
| 836 | goto free_clks; |
| 837 | |
| 838 | gate->reg = reg; |
| 839 | gate->bit_idx = data->div[i].gate; |
| 840 | gate->lock = &clk_lock; |
| 841 | |
| 842 | gate_hw = &gate->hw; |
| 843 | } |
| 844 | |
| 845 | /* Leaves can be fixed or configurable divisors */ |
| 846 | if (data->div[i].fixed) { |
| 847 | fix_factor = kzalloc(sizeof(*fix_factor), GFP_KERNEL); |
| 848 | if (!fix_factor) |
| 849 | goto free_gate; |
| 850 | |
| 851 | fix_factor->mult = 1; |
| 852 | fix_factor->div = data->div[i].fixed; |
| 853 | |
| 854 | rate_hw = &fix_factor->hw; |
| 855 | rate_ops = &clk_fixed_factor_ops; |
| 856 | } else { |
| 857 | divider = kzalloc(sizeof(*divider), GFP_KERNEL); |
| 858 | if (!divider) |
| 859 | goto free_gate; |
| 860 | |
| 861 | flags = data->div[i].pow ? CLK_DIVIDER_POWER_OF_TWO : 0; |
| 862 | |
| 863 | divider->reg = reg; |
| 864 | divider->shift = data->div[i].shift; |
| 865 | divider->width = SUNXI_DIVISOR_WIDTH; |
| 866 | divider->flags = flags; |
| 867 | divider->lock = &clk_lock; |
| 868 | divider->table = data->div[i].table; |
| 869 | |
| 870 | rate_hw = ÷r->hw; |
| 871 | rate_ops = &clk_divider_ops; |
| 872 | } |
| 873 | |
| 874 | /* Wrap the (potential) gate and the divisor on a composite |
| 875 | * clock to unify them */ |
| 876 | clks[i] = clk_register_composite(NULL, clk_name, &parent, 1, |
| 877 | NULL, NULL, |
| 878 | rate_hw, rate_ops, |
| 879 | gate_hw, &clk_gate_ops, |
| 880 | clkflags); |
| 881 | |
| 882 | WARN_ON(IS_ERR(clk_data->clks[i])); |
| 883 | clk_register_clkdev(clks[i], clk_name, NULL); |
| 884 | } |
| 885 | |
| 886 | /* The last clock available on the getter is the parent */ |
| 887 | clks[i++] = pclk; |
| 888 | |
| 889 | /* Adjust to the real max */ |
| 890 | clk_data->clk_num = i; |
| 891 | |
| 892 | of_clk_add_provider(node, of_clk_src_onecell_get, clk_data); |
| 893 | |
| 894 | return; |
| 895 | |
| 896 | free_gate: |
| 897 | kfree(gate); |
| 898 | free_clks: |
| 899 | kfree(clks); |
| 900 | free_clkdata: |
| 901 | kfree(clk_data); |
| 902 | } |
| 903 | |
| 904 | |
| 905 | |
Emilio López | e874a66 | 2013-02-25 11:44:26 -0300 | [diff] [blame] | 906 | /* Matches for factors clocks */ |
Sachin Kamat | 52be7cc | 2013-08-12 14:44:06 +0530 | [diff] [blame] | 907 | static const struct of_device_id clk_factors_match[] __initconst = { |
Maxime Ripard | 81ba6c5 | 2013-07-22 18:21:32 +0200 | [diff] [blame] | 908 | {.compatible = "allwinner,sun4i-pll1-clk", .data = &sun4i_pll1_data,}, |
Maxime Ripard | 6a721db | 2013-07-23 23:34:10 +0200 | [diff] [blame] | 909 | {.compatible = "allwinner,sun6i-a31-pll1-clk", .data = &sun6i_a31_pll1_data,}, |
Maxime Ripard | 81ba6c5 | 2013-07-22 18:21:32 +0200 | [diff] [blame] | 910 | {.compatible = "allwinner,sun4i-apb1-clk", .data = &sun4i_apb1_data,}, |
Emilio López | 7551769 | 2013-12-23 00:32:39 -0300 | [diff] [blame^] | 911 | {.compatible = "allwinner,sun4i-mod0-clk", .data = &sun4i_mod0_data,}, |
Emilio López | e874a66 | 2013-02-25 11:44:26 -0300 | [diff] [blame] | 912 | {} |
| 913 | }; |
| 914 | |
| 915 | /* Matches for divider clocks */ |
Sachin Kamat | 52be7cc | 2013-08-12 14:44:06 +0530 | [diff] [blame] | 916 | static const struct of_device_id clk_div_match[] __initconst = { |
Maxime Ripard | 81ba6c5 | 2013-07-22 18:21:32 +0200 | [diff] [blame] | 917 | {.compatible = "allwinner,sun4i-axi-clk", .data = &sun4i_axi_data,}, |
| 918 | {.compatible = "allwinner,sun4i-ahb-clk", .data = &sun4i_ahb_data,}, |
| 919 | {.compatible = "allwinner,sun4i-apb0-clk", .data = &sun4i_apb0_data,}, |
Maxime Ripard | 6a721db | 2013-07-23 23:34:10 +0200 | [diff] [blame] | 920 | {.compatible = "allwinner,sun6i-a31-apb2-div-clk", .data = &sun6i_a31_apb2_div_data,}, |
Emilio López | e874a66 | 2013-02-25 11:44:26 -0300 | [diff] [blame] | 921 | {} |
| 922 | }; |
| 923 | |
Emilio López | d584c13 | 2013-12-23 00:32:37 -0300 | [diff] [blame] | 924 | /* Matches for divided outputs */ |
| 925 | static const struct of_device_id clk_divs_match[] __initconst = { |
| 926 | {.compatible = "allwinner,sun4i-pll5-clk", .data = &pll5_divs_data,}, |
| 927 | {.compatible = "allwinner,sun4i-pll6-clk", .data = &pll6_divs_data,}, |
| 928 | {} |
| 929 | }; |
| 930 | |
Emilio López | e874a66 | 2013-02-25 11:44:26 -0300 | [diff] [blame] | 931 | /* Matches for mux clocks */ |
Sachin Kamat | 52be7cc | 2013-08-12 14:44:06 +0530 | [diff] [blame] | 932 | static const struct of_device_id clk_mux_match[] __initconst = { |
Maxime Ripard | 81ba6c5 | 2013-07-22 18:21:32 +0200 | [diff] [blame] | 933 | {.compatible = "allwinner,sun4i-cpu-clk", .data = &sun4i_cpu_mux_data,}, |
| 934 | {.compatible = "allwinner,sun4i-apb1-mux-clk", .data = &sun4i_apb1_mux_data,}, |
Maxime Ripard | 6a721db | 2013-07-23 23:34:10 +0200 | [diff] [blame] | 935 | {.compatible = "allwinner,sun6i-a31-ahb1-mux-clk", .data = &sun6i_a31_ahb1_mux_data,}, |
Emilio López | e874a66 | 2013-02-25 11:44:26 -0300 | [diff] [blame] | 936 | {} |
| 937 | }; |
| 938 | |
Emilio López | 13569a7 | 2013-03-27 18:20:37 -0300 | [diff] [blame] | 939 | /* Matches for gate clocks */ |
Sachin Kamat | 52be7cc | 2013-08-12 14:44:06 +0530 | [diff] [blame] | 940 | static const struct of_device_id clk_gates_match[] __initconst = { |
Maxime Ripard | 4f985b4 | 2013-04-30 11:56:22 +0200 | [diff] [blame] | 941 | {.compatible = "allwinner,sun4i-axi-gates-clk", .data = &sun4i_axi_gates_data,}, |
| 942 | {.compatible = "allwinner,sun4i-ahb-gates-clk", .data = &sun4i_ahb_gates_data,}, |
Maxime Ripard | 2371dd8 | 2013-07-16 11:21:59 +0200 | [diff] [blame] | 943 | {.compatible = "allwinner,sun5i-a10s-ahb-gates-clk", .data = &sun5i_a10s_ahb_gates_data,}, |
Maxime Ripard | 4f985b4 | 2013-04-30 11:56:22 +0200 | [diff] [blame] | 944 | {.compatible = "allwinner,sun5i-a13-ahb-gates-clk", .data = &sun5i_a13_ahb_gates_data,}, |
Maxime Ripard | 6a721db | 2013-07-23 23:34:10 +0200 | [diff] [blame] | 945 | {.compatible = "allwinner,sun6i-a31-ahb1-gates-clk", .data = &sun6i_a31_ahb1_gates_data,}, |
Maxime Ripard | 1fb2e4a | 2013-07-25 21:06:56 +0200 | [diff] [blame] | 946 | {.compatible = "allwinner,sun7i-a20-ahb-gates-clk", .data = &sun7i_a20_ahb_gates_data,}, |
Maxime Ripard | 4f985b4 | 2013-04-30 11:56:22 +0200 | [diff] [blame] | 947 | {.compatible = "allwinner,sun4i-apb0-gates-clk", .data = &sun4i_apb0_gates_data,}, |
Maxime Ripard | 2371dd8 | 2013-07-16 11:21:59 +0200 | [diff] [blame] | 948 | {.compatible = "allwinner,sun5i-a10s-apb0-gates-clk", .data = &sun5i_a10s_apb0_gates_data,}, |
Maxime Ripard | 4f985b4 | 2013-04-30 11:56:22 +0200 | [diff] [blame] | 949 | {.compatible = "allwinner,sun5i-a13-apb0-gates-clk", .data = &sun5i_a13_apb0_gates_data,}, |
Maxime Ripard | 1fb2e4a | 2013-07-25 21:06:56 +0200 | [diff] [blame] | 950 | {.compatible = "allwinner,sun7i-a20-apb0-gates-clk", .data = &sun7i_a20_apb0_gates_data,}, |
Maxime Ripard | 4f985b4 | 2013-04-30 11:56:22 +0200 | [diff] [blame] | 951 | {.compatible = "allwinner,sun4i-apb1-gates-clk", .data = &sun4i_apb1_gates_data,}, |
Maxime Ripard | 2371dd8 | 2013-07-16 11:21:59 +0200 | [diff] [blame] | 952 | {.compatible = "allwinner,sun5i-a10s-apb1-gates-clk", .data = &sun5i_a10s_apb1_gates_data,}, |
Maxime Ripard | 4f985b4 | 2013-04-30 11:56:22 +0200 | [diff] [blame] | 953 | {.compatible = "allwinner,sun5i-a13-apb1-gates-clk", .data = &sun5i_a13_apb1_gates_data,}, |
Maxime Ripard | 6a721db | 2013-07-23 23:34:10 +0200 | [diff] [blame] | 954 | {.compatible = "allwinner,sun6i-a31-apb1-gates-clk", .data = &sun6i_a31_apb1_gates_data,}, |
Maxime Ripard | 1fb2e4a | 2013-07-25 21:06:56 +0200 | [diff] [blame] | 955 | {.compatible = "allwinner,sun7i-a20-apb1-gates-clk", .data = &sun7i_a20_apb1_gates_data,}, |
Maxime Ripard | 6a721db | 2013-07-23 23:34:10 +0200 | [diff] [blame] | 956 | {.compatible = "allwinner,sun6i-a31-apb2-gates-clk", .data = &sun6i_a31_apb2_gates_data,}, |
Emilio López | 13569a7 | 2013-03-27 18:20:37 -0300 | [diff] [blame] | 957 | {} |
| 958 | }; |
| 959 | |
Emilio López | e874a66 | 2013-02-25 11:44:26 -0300 | [diff] [blame] | 960 | static void __init of_sunxi_table_clock_setup(const struct of_device_id *clk_match, |
| 961 | void *function) |
| 962 | { |
| 963 | struct device_node *np; |
| 964 | const struct div_data *data; |
| 965 | const struct of_device_id *match; |
| 966 | void (*setup_function)(struct device_node *, const void *) = function; |
| 967 | |
| 968 | for_each_matching_node(np, clk_match) { |
| 969 | match = of_match_node(clk_match, np); |
| 970 | data = match->data; |
| 971 | setup_function(np, data); |
| 972 | } |
| 973 | } |
| 974 | |
Emilio López | 8e6a4c4 | 2013-09-20 22:03:12 -0300 | [diff] [blame] | 975 | /** |
| 976 | * System clock protection |
| 977 | * |
| 978 | * By enabling these critical clocks, we prevent their accidental gating |
| 979 | * by the framework |
| 980 | */ |
| 981 | static void __init sunxi_clock_protect(void) |
| 982 | { |
| 983 | struct clk *clk; |
| 984 | |
| 985 | /* memory bus clock - sun5i+ */ |
| 986 | clk = clk_get(NULL, "mbus"); |
| 987 | if (!IS_ERR(clk)) { |
| 988 | clk_prepare_enable(clk); |
| 989 | clk_put(clk); |
| 990 | } |
| 991 | |
| 992 | /* DDR clock - sun4i+ */ |
| 993 | clk = clk_get(NULL, "pll5_ddr"); |
| 994 | if (!IS_ERR(clk)) { |
| 995 | clk_prepare_enable(clk); |
| 996 | clk_put(clk); |
| 997 | } |
| 998 | } |
| 999 | |
Mike Turquette | 1d9438f | 2013-12-01 12:42:45 -0800 | [diff] [blame] | 1000 | static void __init sunxi_init_clocks(void) |
Emilio López | e874a66 | 2013-02-25 11:44:26 -0300 | [diff] [blame] | 1001 | { |
Emilio López | e874a66 | 2013-02-25 11:44:26 -0300 | [diff] [blame] | 1002 | /* Register factor clocks */ |
| 1003 | of_sunxi_table_clock_setup(clk_factors_match, sunxi_factors_clk_setup); |
| 1004 | |
| 1005 | /* Register divider clocks */ |
| 1006 | of_sunxi_table_clock_setup(clk_div_match, sunxi_divider_clk_setup); |
| 1007 | |
Emilio López | d584c13 | 2013-12-23 00:32:37 -0300 | [diff] [blame] | 1008 | /* Register divided output clocks */ |
| 1009 | of_sunxi_table_clock_setup(clk_divs_match, sunxi_divs_clk_setup); |
| 1010 | |
Emilio López | e874a66 | 2013-02-25 11:44:26 -0300 | [diff] [blame] | 1011 | /* Register mux clocks */ |
| 1012 | of_sunxi_table_clock_setup(clk_mux_match, sunxi_mux_clk_setup); |
Emilio López | 13569a7 | 2013-03-27 18:20:37 -0300 | [diff] [blame] | 1013 | |
| 1014 | /* Register gate clocks */ |
| 1015 | of_sunxi_table_clock_setup(clk_gates_match, sunxi_gates_clk_setup); |
Emilio López | 8e6a4c4 | 2013-09-20 22:03:12 -0300 | [diff] [blame] | 1016 | |
| 1017 | /* Enable core system clocks */ |
| 1018 | sunxi_clock_protect(); |
Emilio López | e874a66 | 2013-02-25 11:44:26 -0300 | [diff] [blame] | 1019 | } |
Sebastian Hesselbarth | be08045 | 2013-09-06 14:59:57 +0200 | [diff] [blame] | 1020 | CLK_OF_DECLARE(sun4i_a10_clk_init, "allwinner,sun4i-a10", sunxi_init_clocks); |
| 1021 | CLK_OF_DECLARE(sun5i_a10s_clk_init, "allwinner,sun5i-a10s", sunxi_init_clocks); |
| 1022 | CLK_OF_DECLARE(sun5i_a13_clk_init, "allwinner,sun5i-a13", sunxi_init_clocks); |
| 1023 | CLK_OF_DECLARE(sun6i_a31_clk_init, "allwinner,sun6i-a31", sunxi_init_clocks); |
| 1024 | CLK_OF_DECLARE(sun7i_a20_clk_init, "allwinner,sun7i-a20", sunxi_init_clocks); |