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Graeme Gregory518fb722011-05-02 16:20:08 -05001/*
2 * tps65910.c -- TI tps65910
3 *
4 * Copyright 2010 Texas Instruments Inc.
5 *
6 * Author: Graeme Gregory <gg@slimlogic.co.uk>
7 * Author: Jorge Eduardo Candelaria <jedu@slimlogic.co.uk>
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License as published by the
11 * Free Software Foundation; either version 2 of the License, or (at your
12 * option) any later version.
13 *
14 */
15
16#include <linux/kernel.h>
17#include <linux/module.h>
18#include <linux/init.h>
19#include <linux/err.h>
20#include <linux/platform_device.h>
21#include <linux/regulator/driver.h>
22#include <linux/regulator/machine.h>
Graeme Gregory518fb722011-05-02 16:20:08 -050023#include <linux/slab.h>
24#include <linux/gpio.h>
25#include <linux/mfd/tps65910.h>
Rhyland Klein67901782012-05-08 11:42:41 -070026#include <linux/regulator/of_regulator.h>
Graeme Gregory518fb722011-05-02 16:20:08 -050027
Graeme Gregory518fb722011-05-02 16:20:08 -050028#define TPS65910_SUPPLY_STATE_ENABLED 0x1
Laxman Dewangan1e0c66f2012-01-28 15:07:57 +053029#define EXT_SLEEP_CONTROL (TPS65910_SLEEP_CONTROL_EXT_INPUT_EN1 | \
30 TPS65910_SLEEP_CONTROL_EXT_INPUT_EN2 | \
Laxman Dewanganf30b0712012-03-07 18:21:49 +053031 TPS65910_SLEEP_CONTROL_EXT_INPUT_EN3 | \
32 TPS65911_SLEEP_CONTROL_EXT_INPUT_SLEEP)
Graeme Gregory518fb722011-05-02 16:20:08 -050033
34/* supported VIO voltages in milivolts */
35static const u16 VIO_VSEL_table[] = {
36 1500, 1800, 2500, 3300,
37};
38
Jorge Eduardo Candelariaa320e3c2011-05-16 18:35:03 -050039/* VSEL tables for TPS65910 specific LDOs and dcdc's */
40
41/* supported VDD3 voltages in milivolts */
Graeme Gregory518fb722011-05-02 16:20:08 -050042static const u16 VDD3_VSEL_table[] = {
43 5000,
44};
45
46/* supported VDIG1 voltages in milivolts */
47static const u16 VDIG1_VSEL_table[] = {
48 1200, 1500, 1800, 2700,
49};
50
51/* supported VDIG2 voltages in milivolts */
52static const u16 VDIG2_VSEL_table[] = {
53 1000, 1100, 1200, 1800,
54};
55
56/* supported VPLL voltages in milivolts */
57static const u16 VPLL_VSEL_table[] = {
58 1000, 1100, 1800, 2500,
59};
60
61/* supported VDAC voltages in milivolts */
62static const u16 VDAC_VSEL_table[] = {
63 1800, 2600, 2800, 2850,
64};
65
66/* supported VAUX1 voltages in milivolts */
67static const u16 VAUX1_VSEL_table[] = {
68 1800, 2500, 2800, 2850,
69};
70
71/* supported VAUX2 voltages in milivolts */
72static const u16 VAUX2_VSEL_table[] = {
73 1800, 2800, 2900, 3300,
74};
75
76/* supported VAUX33 voltages in milivolts */
77static const u16 VAUX33_VSEL_table[] = {
78 1800, 2000, 2800, 3300,
79};
80
81/* supported VMMC voltages in milivolts */
82static const u16 VMMC_VSEL_table[] = {
83 1800, 2800, 3000, 3300,
84};
85
86struct tps_info {
87 const char *name;
88 unsigned min_uV;
89 unsigned max_uV;
Laxman Dewangan7d38a3c2012-01-20 16:36:22 +053090 u8 n_voltages;
91 const u16 *voltage_table;
Laxman Dewangan0651eed2012-03-13 11:35:20 +053092 int enable_time_us;
Graeme Gregory518fb722011-05-02 16:20:08 -050093};
94
95static struct tps_info tps65910_regs[] = {
96 {
Laxman Dewangan33a69432012-05-19 20:04:06 +053097 .name = "vrtc",
Laxman Dewangan0651eed2012-03-13 11:35:20 +053098 .enable_time_us = 2200,
Graeme Gregory518fb722011-05-02 16:20:08 -050099 },
100 {
Laxman Dewangan33a69432012-05-19 20:04:06 +0530101 .name = "vio",
Graeme Gregory518fb722011-05-02 16:20:08 -0500102 .min_uV = 1500000,
103 .max_uV = 3300000,
Laxman Dewangan7d38a3c2012-01-20 16:36:22 +0530104 .n_voltages = ARRAY_SIZE(VIO_VSEL_table),
105 .voltage_table = VIO_VSEL_table,
Laxman Dewangan0651eed2012-03-13 11:35:20 +0530106 .enable_time_us = 350,
Graeme Gregory518fb722011-05-02 16:20:08 -0500107 },
108 {
Laxman Dewangan33a69432012-05-19 20:04:06 +0530109 .name = "vdd1",
Graeme Gregory518fb722011-05-02 16:20:08 -0500110 .min_uV = 600000,
111 .max_uV = 4500000,
Laxman Dewangan0651eed2012-03-13 11:35:20 +0530112 .enable_time_us = 350,
Graeme Gregory518fb722011-05-02 16:20:08 -0500113 },
114 {
Laxman Dewangan33a69432012-05-19 20:04:06 +0530115 .name = "vdd2",
Graeme Gregory518fb722011-05-02 16:20:08 -0500116 .min_uV = 600000,
117 .max_uV = 4500000,
Laxman Dewangan0651eed2012-03-13 11:35:20 +0530118 .enable_time_us = 350,
Graeme Gregory518fb722011-05-02 16:20:08 -0500119 },
120 {
Laxman Dewangan33a69432012-05-19 20:04:06 +0530121 .name = "vdd3",
Graeme Gregory518fb722011-05-02 16:20:08 -0500122 .min_uV = 5000000,
123 .max_uV = 5000000,
Laxman Dewangan7d38a3c2012-01-20 16:36:22 +0530124 .n_voltages = ARRAY_SIZE(VDD3_VSEL_table),
125 .voltage_table = VDD3_VSEL_table,
Laxman Dewangan0651eed2012-03-13 11:35:20 +0530126 .enable_time_us = 200,
Graeme Gregory518fb722011-05-02 16:20:08 -0500127 },
128 {
Laxman Dewangan33a69432012-05-19 20:04:06 +0530129 .name = "vdig1",
Graeme Gregory518fb722011-05-02 16:20:08 -0500130 .min_uV = 1200000,
131 .max_uV = 2700000,
Laxman Dewangan7d38a3c2012-01-20 16:36:22 +0530132 .n_voltages = ARRAY_SIZE(VDIG1_VSEL_table),
133 .voltage_table = VDIG1_VSEL_table,
Laxman Dewangan0651eed2012-03-13 11:35:20 +0530134 .enable_time_us = 100,
Graeme Gregory518fb722011-05-02 16:20:08 -0500135 },
136 {
Laxman Dewangan33a69432012-05-19 20:04:06 +0530137 .name = "vdig2",
Graeme Gregory518fb722011-05-02 16:20:08 -0500138 .min_uV = 1000000,
139 .max_uV = 1800000,
Laxman Dewangan7d38a3c2012-01-20 16:36:22 +0530140 .n_voltages = ARRAY_SIZE(VDIG2_VSEL_table),
141 .voltage_table = VDIG2_VSEL_table,
Laxman Dewangan0651eed2012-03-13 11:35:20 +0530142 .enable_time_us = 100,
Graeme Gregory518fb722011-05-02 16:20:08 -0500143 },
144 {
Laxman Dewangan33a69432012-05-19 20:04:06 +0530145 .name = "vpll",
Graeme Gregory518fb722011-05-02 16:20:08 -0500146 .min_uV = 1000000,
147 .max_uV = 2500000,
Laxman Dewangan7d38a3c2012-01-20 16:36:22 +0530148 .n_voltages = ARRAY_SIZE(VPLL_VSEL_table),
149 .voltage_table = VPLL_VSEL_table,
Laxman Dewangan0651eed2012-03-13 11:35:20 +0530150 .enable_time_us = 100,
Graeme Gregory518fb722011-05-02 16:20:08 -0500151 },
152 {
Laxman Dewangan33a69432012-05-19 20:04:06 +0530153 .name = "vdac",
Graeme Gregory518fb722011-05-02 16:20:08 -0500154 .min_uV = 1800000,
155 .max_uV = 2850000,
Laxman Dewangan7d38a3c2012-01-20 16:36:22 +0530156 .n_voltages = ARRAY_SIZE(VDAC_VSEL_table),
157 .voltage_table = VDAC_VSEL_table,
Laxman Dewangan0651eed2012-03-13 11:35:20 +0530158 .enable_time_us = 100,
Graeme Gregory518fb722011-05-02 16:20:08 -0500159 },
160 {
Laxman Dewangan33a69432012-05-19 20:04:06 +0530161 .name = "vaux1",
Graeme Gregory518fb722011-05-02 16:20:08 -0500162 .min_uV = 1800000,
163 .max_uV = 2850000,
Laxman Dewangan7d38a3c2012-01-20 16:36:22 +0530164 .n_voltages = ARRAY_SIZE(VAUX1_VSEL_table),
165 .voltage_table = VAUX1_VSEL_table,
Laxman Dewangan0651eed2012-03-13 11:35:20 +0530166 .enable_time_us = 100,
Graeme Gregory518fb722011-05-02 16:20:08 -0500167 },
168 {
Laxman Dewangan33a69432012-05-19 20:04:06 +0530169 .name = "vaux2",
Graeme Gregory518fb722011-05-02 16:20:08 -0500170 .min_uV = 1800000,
171 .max_uV = 3300000,
Laxman Dewangan7d38a3c2012-01-20 16:36:22 +0530172 .n_voltages = ARRAY_SIZE(VAUX2_VSEL_table),
173 .voltage_table = VAUX2_VSEL_table,
Laxman Dewangan0651eed2012-03-13 11:35:20 +0530174 .enable_time_us = 100,
Graeme Gregory518fb722011-05-02 16:20:08 -0500175 },
176 {
Laxman Dewangan33a69432012-05-19 20:04:06 +0530177 .name = "vaux33",
Graeme Gregory518fb722011-05-02 16:20:08 -0500178 .min_uV = 1800000,
179 .max_uV = 3300000,
Laxman Dewangan7d38a3c2012-01-20 16:36:22 +0530180 .n_voltages = ARRAY_SIZE(VAUX33_VSEL_table),
181 .voltage_table = VAUX33_VSEL_table,
Laxman Dewangan0651eed2012-03-13 11:35:20 +0530182 .enable_time_us = 100,
Graeme Gregory518fb722011-05-02 16:20:08 -0500183 },
184 {
Laxman Dewangan33a69432012-05-19 20:04:06 +0530185 .name = "vmmc",
Graeme Gregory518fb722011-05-02 16:20:08 -0500186 .min_uV = 1800000,
187 .max_uV = 3300000,
Laxman Dewangan7d38a3c2012-01-20 16:36:22 +0530188 .n_voltages = ARRAY_SIZE(VMMC_VSEL_table),
189 .voltage_table = VMMC_VSEL_table,
Laxman Dewangan0651eed2012-03-13 11:35:20 +0530190 .enable_time_us = 100,
Graeme Gregory518fb722011-05-02 16:20:08 -0500191 },
192};
193
Jorge Eduardo Candelariaa320e3c2011-05-16 18:35:03 -0500194static struct tps_info tps65911_regs[] = {
195 {
Laxman Dewangan33a69432012-05-19 20:04:06 +0530196 .name = "vrtc",
Laxman Dewangan0651eed2012-03-13 11:35:20 +0530197 .enable_time_us = 2200,
Laxman Dewanganc2f8efd2012-01-18 20:46:56 +0530198 },
199 {
Laxman Dewangan33a69432012-05-19 20:04:06 +0530200 .name = "vio",
Jorge Eduardo Candelariaa320e3c2011-05-16 18:35:03 -0500201 .min_uV = 1500000,
202 .max_uV = 3300000,
Laxman Dewangan7d38a3c2012-01-20 16:36:22 +0530203 .n_voltages = ARRAY_SIZE(VIO_VSEL_table),
204 .voltage_table = VIO_VSEL_table,
Laxman Dewangan0651eed2012-03-13 11:35:20 +0530205 .enable_time_us = 350,
Jorge Eduardo Candelariaa320e3c2011-05-16 18:35:03 -0500206 },
207 {
Laxman Dewangan33a69432012-05-19 20:04:06 +0530208 .name = "vdd1",
Jorge Eduardo Candelariaa320e3c2011-05-16 18:35:03 -0500209 .min_uV = 600000,
210 .max_uV = 4500000,
Laxman Dewangan7d38a3c2012-01-20 16:36:22 +0530211 .n_voltages = 73,
Laxman Dewangan0651eed2012-03-13 11:35:20 +0530212 .enable_time_us = 350,
Jorge Eduardo Candelariaa320e3c2011-05-16 18:35:03 -0500213 },
214 {
Laxman Dewangan33a69432012-05-19 20:04:06 +0530215 .name = "vdd2",
Jorge Eduardo Candelariaa320e3c2011-05-16 18:35:03 -0500216 .min_uV = 600000,
217 .max_uV = 4500000,
Laxman Dewangan7d38a3c2012-01-20 16:36:22 +0530218 .n_voltages = 73,
Laxman Dewangan0651eed2012-03-13 11:35:20 +0530219 .enable_time_us = 350,
Jorge Eduardo Candelariaa320e3c2011-05-16 18:35:03 -0500220 },
221 {
Laxman Dewangan33a69432012-05-19 20:04:06 +0530222 .name = "vddctrl",
Jorge Eduardo Candelariaa320e3c2011-05-16 18:35:03 -0500223 .min_uV = 600000,
224 .max_uV = 1400000,
Laxman Dewangan7d38a3c2012-01-20 16:36:22 +0530225 .n_voltages = 65,
Laxman Dewangan0651eed2012-03-13 11:35:20 +0530226 .enable_time_us = 900,
Jorge Eduardo Candelariaa320e3c2011-05-16 18:35:03 -0500227 },
228 {
Laxman Dewangan33a69432012-05-19 20:04:06 +0530229 .name = "ldo1",
Jorge Eduardo Candelariaa320e3c2011-05-16 18:35:03 -0500230 .min_uV = 1000000,
231 .max_uV = 3300000,
Laxman Dewangan7d38a3c2012-01-20 16:36:22 +0530232 .n_voltages = 47,
Laxman Dewangan0651eed2012-03-13 11:35:20 +0530233 .enable_time_us = 420,
Jorge Eduardo Candelariaa320e3c2011-05-16 18:35:03 -0500234 },
235 {
Laxman Dewangan33a69432012-05-19 20:04:06 +0530236 .name = "ldo2",
Jorge Eduardo Candelariaa320e3c2011-05-16 18:35:03 -0500237 .min_uV = 1000000,
238 .max_uV = 3300000,
Laxman Dewangan7d38a3c2012-01-20 16:36:22 +0530239 .n_voltages = 47,
Laxman Dewangan0651eed2012-03-13 11:35:20 +0530240 .enable_time_us = 420,
Jorge Eduardo Candelariaa320e3c2011-05-16 18:35:03 -0500241 },
242 {
Laxman Dewangan33a69432012-05-19 20:04:06 +0530243 .name = "ldo3",
Jorge Eduardo Candelariaa320e3c2011-05-16 18:35:03 -0500244 .min_uV = 1000000,
245 .max_uV = 3300000,
Laxman Dewangan7d38a3c2012-01-20 16:36:22 +0530246 .n_voltages = 24,
Laxman Dewangan0651eed2012-03-13 11:35:20 +0530247 .enable_time_us = 230,
Jorge Eduardo Candelariaa320e3c2011-05-16 18:35:03 -0500248 },
249 {
Laxman Dewangan33a69432012-05-19 20:04:06 +0530250 .name = "ldo4",
Jorge Eduardo Candelariaa320e3c2011-05-16 18:35:03 -0500251 .min_uV = 1000000,
252 .max_uV = 3300000,
Laxman Dewangan7d38a3c2012-01-20 16:36:22 +0530253 .n_voltages = 47,
Laxman Dewangan0651eed2012-03-13 11:35:20 +0530254 .enable_time_us = 230,
Jorge Eduardo Candelariaa320e3c2011-05-16 18:35:03 -0500255 },
256 {
Laxman Dewangan33a69432012-05-19 20:04:06 +0530257 .name = "ldo5",
Jorge Eduardo Candelariaa320e3c2011-05-16 18:35:03 -0500258 .min_uV = 1000000,
259 .max_uV = 3300000,
Laxman Dewangan7d38a3c2012-01-20 16:36:22 +0530260 .n_voltages = 24,
Laxman Dewangan0651eed2012-03-13 11:35:20 +0530261 .enable_time_us = 230,
Jorge Eduardo Candelariaa320e3c2011-05-16 18:35:03 -0500262 },
263 {
Laxman Dewangan33a69432012-05-19 20:04:06 +0530264 .name = "ldo6",
Jorge Eduardo Candelariaa320e3c2011-05-16 18:35:03 -0500265 .min_uV = 1000000,
266 .max_uV = 3300000,
Laxman Dewangan7d38a3c2012-01-20 16:36:22 +0530267 .n_voltages = 24,
Laxman Dewangan0651eed2012-03-13 11:35:20 +0530268 .enable_time_us = 230,
Jorge Eduardo Candelariaa320e3c2011-05-16 18:35:03 -0500269 },
270 {
Laxman Dewangan33a69432012-05-19 20:04:06 +0530271 .name = "ldo7",
Jorge Eduardo Candelariaa320e3c2011-05-16 18:35:03 -0500272 .min_uV = 1000000,
273 .max_uV = 3300000,
Laxman Dewangan7d38a3c2012-01-20 16:36:22 +0530274 .n_voltages = 24,
Laxman Dewangan0651eed2012-03-13 11:35:20 +0530275 .enable_time_us = 230,
Jorge Eduardo Candelariaa320e3c2011-05-16 18:35:03 -0500276 },
277 {
Laxman Dewangan33a69432012-05-19 20:04:06 +0530278 .name = "ldo8",
Jorge Eduardo Candelariaa320e3c2011-05-16 18:35:03 -0500279 .min_uV = 1000000,
280 .max_uV = 3300000,
Laxman Dewangan7d38a3c2012-01-20 16:36:22 +0530281 .n_voltages = 24,
Laxman Dewangan0651eed2012-03-13 11:35:20 +0530282 .enable_time_us = 230,
Jorge Eduardo Candelariaa320e3c2011-05-16 18:35:03 -0500283 },
284};
285
Laxman Dewangan1e0c66f2012-01-28 15:07:57 +0530286#define EXT_CONTROL_REG_BITS(id, regs_offs, bits) (((regs_offs) << 8) | (bits))
287static unsigned int tps65910_ext_sleep_control[] = {
288 0,
289 EXT_CONTROL_REG_BITS(VIO, 1, 0),
290 EXT_CONTROL_REG_BITS(VDD1, 1, 1),
291 EXT_CONTROL_REG_BITS(VDD2, 1, 2),
292 EXT_CONTROL_REG_BITS(VDD3, 1, 3),
293 EXT_CONTROL_REG_BITS(VDIG1, 0, 1),
294 EXT_CONTROL_REG_BITS(VDIG2, 0, 2),
295 EXT_CONTROL_REG_BITS(VPLL, 0, 6),
296 EXT_CONTROL_REG_BITS(VDAC, 0, 7),
297 EXT_CONTROL_REG_BITS(VAUX1, 0, 3),
298 EXT_CONTROL_REG_BITS(VAUX2, 0, 4),
299 EXT_CONTROL_REG_BITS(VAUX33, 0, 5),
300 EXT_CONTROL_REG_BITS(VMMC, 0, 0),
301};
302
303static unsigned int tps65911_ext_sleep_control[] = {
304 0,
305 EXT_CONTROL_REG_BITS(VIO, 1, 0),
306 EXT_CONTROL_REG_BITS(VDD1, 1, 1),
307 EXT_CONTROL_REG_BITS(VDD2, 1, 2),
308 EXT_CONTROL_REG_BITS(VDDCTRL, 1, 3),
309 EXT_CONTROL_REG_BITS(LDO1, 0, 1),
310 EXT_CONTROL_REG_BITS(LDO2, 0, 2),
311 EXT_CONTROL_REG_BITS(LDO3, 0, 7),
312 EXT_CONTROL_REG_BITS(LDO4, 0, 6),
313 EXT_CONTROL_REG_BITS(LDO5, 0, 3),
314 EXT_CONTROL_REG_BITS(LDO6, 0, 0),
315 EXT_CONTROL_REG_BITS(LDO7, 0, 5),
316 EXT_CONTROL_REG_BITS(LDO8, 0, 4),
317};
318
Graeme Gregory518fb722011-05-02 16:20:08 -0500319struct tps65910_reg {
Axel Lin39aa9b62011-07-11 09:57:43 +0800320 struct regulator_desc *desc;
Graeme Gregory518fb722011-05-02 16:20:08 -0500321 struct tps65910 *mfd;
Axel Lin39aa9b62011-07-11 09:57:43 +0800322 struct regulator_dev **rdev;
323 struct tps_info **info;
Graeme Gregory518fb722011-05-02 16:20:08 -0500324 struct mutex mutex;
Axel Lin39aa9b62011-07-11 09:57:43 +0800325 int num_regulators;
Graeme Gregory518fb722011-05-02 16:20:08 -0500326 int mode;
Jorge Eduardo Candelariaa320e3c2011-05-16 18:35:03 -0500327 int (*get_ctrl_reg)(int);
Laxman Dewangan1e0c66f2012-01-28 15:07:57 +0530328 unsigned int *ext_sleep_control;
329 unsigned int board_ext_control[TPS65910_NUM_REGS];
Graeme Gregory518fb722011-05-02 16:20:08 -0500330};
331
332static inline int tps65910_read(struct tps65910_reg *pmic, u8 reg)
333{
334 u8 val;
335 int err;
336
337 err = pmic->mfd->read(pmic->mfd, reg, 1, &val);
338 if (err)
339 return err;
340
341 return val;
342}
343
344static inline int tps65910_write(struct tps65910_reg *pmic, u8 reg, u8 val)
345{
346 return pmic->mfd->write(pmic->mfd, reg, 1, &val);
347}
348
349static int tps65910_modify_bits(struct tps65910_reg *pmic, u8 reg,
350 u8 set_mask, u8 clear_mask)
351{
352 int err, data;
353
354 mutex_lock(&pmic->mutex);
355
356 data = tps65910_read(pmic, reg);
357 if (data < 0) {
358 dev_err(pmic->mfd->dev, "Read from reg 0x%x failed\n", reg);
359 err = data;
360 goto out;
361 }
362
363 data &= ~clear_mask;
364 data |= set_mask;
365 err = tps65910_write(pmic, reg, data);
366 if (err)
367 dev_err(pmic->mfd->dev, "Write for reg 0x%x failed\n", reg);
368
369out:
370 mutex_unlock(&pmic->mutex);
371 return err;
372}
373
374static int tps65910_reg_read(struct tps65910_reg *pmic, u8 reg)
375{
376 int data;
377
378 mutex_lock(&pmic->mutex);
379
380 data = tps65910_read(pmic, reg);
381 if (data < 0)
382 dev_err(pmic->mfd->dev, "Read from reg 0x%x failed\n", reg);
383
384 mutex_unlock(&pmic->mutex);
385 return data;
386}
387
388static int tps65910_reg_write(struct tps65910_reg *pmic, u8 reg, u8 val)
389{
390 int err;
391
392 mutex_lock(&pmic->mutex);
393
394 err = tps65910_write(pmic, reg, val);
395 if (err < 0)
396 dev_err(pmic->mfd->dev, "Write for reg 0x%x failed\n", reg);
397
398 mutex_unlock(&pmic->mutex);
399 return err;
400}
401
402static int tps65910_get_ctrl_register(int id)
403{
404 switch (id) {
405 case TPS65910_REG_VRTC:
406 return TPS65910_VRTC;
407 case TPS65910_REG_VIO:
408 return TPS65910_VIO;
409 case TPS65910_REG_VDD1:
410 return TPS65910_VDD1;
411 case TPS65910_REG_VDD2:
412 return TPS65910_VDD2;
413 case TPS65910_REG_VDD3:
414 return TPS65910_VDD3;
415 case TPS65910_REG_VDIG1:
416 return TPS65910_VDIG1;
417 case TPS65910_REG_VDIG2:
418 return TPS65910_VDIG2;
419 case TPS65910_REG_VPLL:
420 return TPS65910_VPLL;
421 case TPS65910_REG_VDAC:
422 return TPS65910_VDAC;
423 case TPS65910_REG_VAUX1:
424 return TPS65910_VAUX1;
425 case TPS65910_REG_VAUX2:
426 return TPS65910_VAUX2;
427 case TPS65910_REG_VAUX33:
428 return TPS65910_VAUX33;
429 case TPS65910_REG_VMMC:
430 return TPS65910_VMMC;
431 default:
432 return -EINVAL;
433 }
434}
435
Jorge Eduardo Candelariaa320e3c2011-05-16 18:35:03 -0500436static int tps65911_get_ctrl_register(int id)
437{
438 switch (id) {
439 case TPS65910_REG_VRTC:
440 return TPS65910_VRTC;
441 case TPS65910_REG_VIO:
442 return TPS65910_VIO;
443 case TPS65910_REG_VDD1:
444 return TPS65910_VDD1;
445 case TPS65910_REG_VDD2:
446 return TPS65910_VDD2;
447 case TPS65911_REG_VDDCTRL:
448 return TPS65911_VDDCTRL;
449 case TPS65911_REG_LDO1:
450 return TPS65911_LDO1;
451 case TPS65911_REG_LDO2:
452 return TPS65911_LDO2;
453 case TPS65911_REG_LDO3:
454 return TPS65911_LDO3;
455 case TPS65911_REG_LDO4:
456 return TPS65911_LDO4;
457 case TPS65911_REG_LDO5:
458 return TPS65911_LDO5;
459 case TPS65911_REG_LDO6:
460 return TPS65911_LDO6;
461 case TPS65911_REG_LDO7:
462 return TPS65911_LDO7;
463 case TPS65911_REG_LDO8:
464 return TPS65911_LDO8;
465 default:
466 return -EINVAL;
467 }
468}
469
Laxman Dewangan0651eed2012-03-13 11:35:20 +0530470static int tps65910_enable_time(struct regulator_dev *dev)
471{
472 struct tps65910_reg *pmic = rdev_get_drvdata(dev);
473 int id = rdev_get_id(dev);
474 return pmic->info[id]->enable_time_us;
475}
Graeme Gregory518fb722011-05-02 16:20:08 -0500476
477static int tps65910_set_mode(struct regulator_dev *dev, unsigned int mode)
478{
479 struct tps65910_reg *pmic = rdev_get_drvdata(dev);
480 struct tps65910 *mfd = pmic->mfd;
481 int reg, value, id = rdev_get_id(dev);
Jorge Eduardo Candelariaa320e3c2011-05-16 18:35:03 -0500482
483 reg = pmic->get_ctrl_reg(id);
Graeme Gregory518fb722011-05-02 16:20:08 -0500484 if (reg < 0)
485 return reg;
486
487 switch (mode) {
488 case REGULATOR_MODE_NORMAL:
489 return tps65910_modify_bits(pmic, reg, LDO_ST_ON_BIT,
490 LDO_ST_MODE_BIT);
491 case REGULATOR_MODE_IDLE:
492 value = LDO_ST_ON_BIT | LDO_ST_MODE_BIT;
493 return tps65910_set_bits(mfd, reg, value);
494 case REGULATOR_MODE_STANDBY:
495 return tps65910_clear_bits(mfd, reg, LDO_ST_ON_BIT);
496 }
497
498 return -EINVAL;
499}
500
501static unsigned int tps65910_get_mode(struct regulator_dev *dev)
502{
503 struct tps65910_reg *pmic = rdev_get_drvdata(dev);
504 int reg, value, id = rdev_get_id(dev);
505
Jorge Eduardo Candelariaa320e3c2011-05-16 18:35:03 -0500506 reg = pmic->get_ctrl_reg(id);
Graeme Gregory518fb722011-05-02 16:20:08 -0500507 if (reg < 0)
508 return reg;
509
510 value = tps65910_reg_read(pmic, reg);
511 if (value < 0)
512 return value;
513
Axel Lin58599392012-03-13 07:15:27 +0800514 if (!(value & LDO_ST_ON_BIT))
Graeme Gregory518fb722011-05-02 16:20:08 -0500515 return REGULATOR_MODE_STANDBY;
516 else if (value & LDO_ST_MODE_BIT)
517 return REGULATOR_MODE_IDLE;
518 else
519 return REGULATOR_MODE_NORMAL;
520}
521
Laxman Dewangan18039e02012-03-14 13:00:58 +0530522static int tps65910_get_voltage_dcdc_sel(struct regulator_dev *dev)
Graeme Gregory518fb722011-05-02 16:20:08 -0500523{
524 struct tps65910_reg *pmic = rdev_get_drvdata(dev);
Laxman Dewangan18039e02012-03-14 13:00:58 +0530525 int id = rdev_get_id(dev);
Jorge Eduardo Candelariaa320e3c2011-05-16 18:35:03 -0500526 int opvsel = 0, srvsel = 0, vselmax = 0, mult = 0, sr = 0;
Graeme Gregory518fb722011-05-02 16:20:08 -0500527
528 switch (id) {
529 case TPS65910_REG_VDD1:
530 opvsel = tps65910_reg_read(pmic, TPS65910_VDD1_OP);
531 mult = tps65910_reg_read(pmic, TPS65910_VDD1);
532 mult = (mult & VDD1_VGAIN_SEL_MASK) >> VDD1_VGAIN_SEL_SHIFT;
533 srvsel = tps65910_reg_read(pmic, TPS65910_VDD1_SR);
534 sr = opvsel & VDD1_OP_CMD_MASK;
535 opvsel &= VDD1_OP_SEL_MASK;
536 srvsel &= VDD1_SR_SEL_MASK;
Jorge Eduardo Candelariaa320e3c2011-05-16 18:35:03 -0500537 vselmax = 75;
Graeme Gregory518fb722011-05-02 16:20:08 -0500538 break;
539 case TPS65910_REG_VDD2:
540 opvsel = tps65910_reg_read(pmic, TPS65910_VDD2_OP);
541 mult = tps65910_reg_read(pmic, TPS65910_VDD2);
542 mult = (mult & VDD2_VGAIN_SEL_MASK) >> VDD2_VGAIN_SEL_SHIFT;
543 srvsel = tps65910_reg_read(pmic, TPS65910_VDD2_SR);
544 sr = opvsel & VDD2_OP_CMD_MASK;
545 opvsel &= VDD2_OP_SEL_MASK;
546 srvsel &= VDD2_SR_SEL_MASK;
Jorge Eduardo Candelariaa320e3c2011-05-16 18:35:03 -0500547 vselmax = 75;
548 break;
549 case TPS65911_REG_VDDCTRL:
550 opvsel = tps65910_reg_read(pmic, TPS65911_VDDCTRL_OP);
551 srvsel = tps65910_reg_read(pmic, TPS65911_VDDCTRL_SR);
552 sr = opvsel & VDDCTRL_OP_CMD_MASK;
553 opvsel &= VDDCTRL_OP_SEL_MASK;
554 srvsel &= VDDCTRL_SR_SEL_MASK;
555 vselmax = 64;
Graeme Gregory518fb722011-05-02 16:20:08 -0500556 break;
557 }
558
559 /* multiplier 0 == 1 but 2,3 normal */
560 if (!mult)
561 mult=1;
562
563 if (sr) {
Jorge Eduardo Candelariaa320e3c2011-05-16 18:35:03 -0500564 /* normalise to valid range */
565 if (srvsel < 3)
566 srvsel = 3;
567 if (srvsel > vselmax)
568 srvsel = vselmax;
Laxman Dewangan18039e02012-03-14 13:00:58 +0530569 return srvsel - 3;
Graeme Gregory518fb722011-05-02 16:20:08 -0500570 } else {
571
Jorge Eduardo Candelariaa320e3c2011-05-16 18:35:03 -0500572 /* normalise to valid range*/
573 if (opvsel < 3)
574 opvsel = 3;
575 if (opvsel > vselmax)
576 opvsel = vselmax;
Laxman Dewangan18039e02012-03-14 13:00:58 +0530577 return opvsel - 3;
Graeme Gregory518fb722011-05-02 16:20:08 -0500578 }
Laxman Dewangan18039e02012-03-14 13:00:58 +0530579 return -EINVAL;
Graeme Gregory518fb722011-05-02 16:20:08 -0500580}
581
Axel Lin1f904fd2012-05-09 09:22:47 +0800582static int tps65910_get_voltage_sel(struct regulator_dev *dev)
Graeme Gregory518fb722011-05-02 16:20:08 -0500583{
584 struct tps65910_reg *pmic = rdev_get_drvdata(dev);
Axel Lin1f904fd2012-05-09 09:22:47 +0800585 int reg, value, id = rdev_get_id(dev);
Graeme Gregory518fb722011-05-02 16:20:08 -0500586
Jorge Eduardo Candelariaa320e3c2011-05-16 18:35:03 -0500587 reg = pmic->get_ctrl_reg(id);
Graeme Gregory518fb722011-05-02 16:20:08 -0500588 if (reg < 0)
589 return reg;
590
591 value = tps65910_reg_read(pmic, reg);
592 if (value < 0)
593 return value;
594
595 switch (id) {
596 case TPS65910_REG_VIO:
597 case TPS65910_REG_VDIG1:
598 case TPS65910_REG_VDIG2:
599 case TPS65910_REG_VPLL:
600 case TPS65910_REG_VDAC:
601 case TPS65910_REG_VAUX1:
602 case TPS65910_REG_VAUX2:
603 case TPS65910_REG_VAUX33:
604 case TPS65910_REG_VMMC:
605 value &= LDO_SEL_MASK;
606 value >>= LDO_SEL_SHIFT;
607 break;
608 default:
609 return -EINVAL;
610 }
611
Axel Lin1f904fd2012-05-09 09:22:47 +0800612 return value;
Graeme Gregory518fb722011-05-02 16:20:08 -0500613}
614
615static int tps65910_get_voltage_vdd3(struct regulator_dev *dev)
616{
617 return 5 * 1000 * 1000;
618}
619
Axel Lin1f904fd2012-05-09 09:22:47 +0800620static int tps65911_get_voltage_sel(struct regulator_dev *dev)
Jorge Eduardo Candelariaa320e3c2011-05-16 18:35:03 -0500621{
622 struct tps65910_reg *pmic = rdev_get_drvdata(dev);
Axel Lin1f904fd2012-05-09 09:22:47 +0800623 int id = rdev_get_id(dev);
Jorge Eduardo Candelariaa320e3c2011-05-16 18:35:03 -0500624 u8 value, reg;
625
626 reg = pmic->get_ctrl_reg(id);
627
628 value = tps65910_reg_read(pmic, reg);
629
630 switch (id) {
631 case TPS65911_REG_LDO1:
632 case TPS65911_REG_LDO2:
633 case TPS65911_REG_LDO4:
634 value &= LDO1_SEL_MASK;
635 value >>= LDO_SEL_SHIFT;
Jorge Eduardo Candelariaa320e3c2011-05-16 18:35:03 -0500636 break;
637 case TPS65911_REG_LDO3:
638 case TPS65911_REG_LDO5:
639 case TPS65911_REG_LDO6:
640 case TPS65911_REG_LDO7:
641 case TPS65911_REG_LDO8:
642 value &= LDO3_SEL_MASK;
643 value >>= LDO_SEL_SHIFT;
Jorge Eduardo Candelariaa320e3c2011-05-16 18:35:03 -0500644 break;
645 case TPS65910_REG_VIO:
Laxman Dewangane882eae2012-02-17 18:56:11 +0530646 value &= LDO_SEL_MASK;
647 value >>= LDO_SEL_SHIFT;
Axel Lin1f904fd2012-05-09 09:22:47 +0800648 break;
Jorge Eduardo Candelariaa320e3c2011-05-16 18:35:03 -0500649 default:
650 return -EINVAL;
651 }
652
Axel Lin1f904fd2012-05-09 09:22:47 +0800653 return value;
Jorge Eduardo Candelariaa320e3c2011-05-16 18:35:03 -0500654}
655
Axel Lin94732b92012-03-09 10:22:20 +0800656static int tps65910_set_voltage_dcdc_sel(struct regulator_dev *dev,
657 unsigned selector)
Graeme Gregory518fb722011-05-02 16:20:08 -0500658{
659 struct tps65910_reg *pmic = rdev_get_drvdata(dev);
660 int id = rdev_get_id(dev), vsel;
Jorge Eduardo Candelariaa320e3c2011-05-16 18:35:03 -0500661 int dcdc_mult = 0;
Graeme Gregory518fb722011-05-02 16:20:08 -0500662
Jorge Eduardo Candelariaa320e3c2011-05-16 18:35:03 -0500663 switch (id) {
664 case TPS65910_REG_VDD1:
Afzal Mohammed780dc9b2011-11-08 18:54:10 +0530665 dcdc_mult = (selector / VDD1_2_NUM_VOLT_FINE) + 1;
Jorge Eduardo Candelariaa320e3c2011-05-16 18:35:03 -0500666 if (dcdc_mult == 1)
667 dcdc_mult--;
Afzal Mohammed780dc9b2011-11-08 18:54:10 +0530668 vsel = (selector % VDD1_2_NUM_VOLT_FINE) + 3;
Graeme Gregory518fb722011-05-02 16:20:08 -0500669
Graeme Gregory518fb722011-05-02 16:20:08 -0500670 tps65910_modify_bits(pmic, TPS65910_VDD1,
671 (dcdc_mult << VDD1_VGAIN_SEL_SHIFT),
672 VDD1_VGAIN_SEL_MASK);
673 tps65910_reg_write(pmic, TPS65910_VDD1_OP, vsel);
Jorge Eduardo Candelariaa320e3c2011-05-16 18:35:03 -0500674 break;
675 case TPS65910_REG_VDD2:
Afzal Mohammed780dc9b2011-11-08 18:54:10 +0530676 dcdc_mult = (selector / VDD1_2_NUM_VOLT_FINE) + 1;
Jorge Eduardo Candelariaa320e3c2011-05-16 18:35:03 -0500677 if (dcdc_mult == 1)
678 dcdc_mult--;
Afzal Mohammed780dc9b2011-11-08 18:54:10 +0530679 vsel = (selector % VDD1_2_NUM_VOLT_FINE) + 3;
Jorge Eduardo Candelariaa320e3c2011-05-16 18:35:03 -0500680
Graeme Gregory518fb722011-05-02 16:20:08 -0500681 tps65910_modify_bits(pmic, TPS65910_VDD2,
682 (dcdc_mult << VDD2_VGAIN_SEL_SHIFT),
683 VDD1_VGAIN_SEL_MASK);
684 tps65910_reg_write(pmic, TPS65910_VDD2_OP, vsel);
Jorge Eduardo Candelariaa320e3c2011-05-16 18:35:03 -0500685 break;
686 case TPS65911_REG_VDDCTRL:
Laxman Dewanganc4632ae2012-03-07 16:39:05 +0530687 vsel = selector + 3;
Jorge Eduardo Candelariaa320e3c2011-05-16 18:35:03 -0500688 tps65910_reg_write(pmic, TPS65911_VDDCTRL_OP, vsel);
Graeme Gregory518fb722011-05-02 16:20:08 -0500689 }
690
691 return 0;
692}
693
Axel Lin94732b92012-03-09 10:22:20 +0800694static int tps65910_set_voltage_sel(struct regulator_dev *dev,
695 unsigned selector)
Graeme Gregory518fb722011-05-02 16:20:08 -0500696{
697 struct tps65910_reg *pmic = rdev_get_drvdata(dev);
698 int reg, id = rdev_get_id(dev);
699
Jorge Eduardo Candelariaa320e3c2011-05-16 18:35:03 -0500700 reg = pmic->get_ctrl_reg(id);
Graeme Gregory518fb722011-05-02 16:20:08 -0500701 if (reg < 0)
702 return reg;
703
704 switch (id) {
705 case TPS65910_REG_VIO:
706 case TPS65910_REG_VDIG1:
707 case TPS65910_REG_VDIG2:
708 case TPS65910_REG_VPLL:
709 case TPS65910_REG_VDAC:
710 case TPS65910_REG_VAUX1:
711 case TPS65910_REG_VAUX2:
712 case TPS65910_REG_VAUX33:
713 case TPS65910_REG_VMMC:
714 return tps65910_modify_bits(pmic, reg,
715 (selector << LDO_SEL_SHIFT), LDO_SEL_MASK);
716 }
717
718 return -EINVAL;
719}
720
Axel Lin94732b92012-03-09 10:22:20 +0800721static int tps65911_set_voltage_sel(struct regulator_dev *dev,
722 unsigned selector)
Jorge Eduardo Candelariaa320e3c2011-05-16 18:35:03 -0500723{
724 struct tps65910_reg *pmic = rdev_get_drvdata(dev);
725 int reg, id = rdev_get_id(dev);
726
727 reg = pmic->get_ctrl_reg(id);
728 if (reg < 0)
729 return reg;
730
731 switch (id) {
732 case TPS65911_REG_LDO1:
733 case TPS65911_REG_LDO2:
734 case TPS65911_REG_LDO4:
735 return tps65910_modify_bits(pmic, reg,
736 (selector << LDO_SEL_SHIFT), LDO1_SEL_MASK);
737 case TPS65911_REG_LDO3:
738 case TPS65911_REG_LDO5:
739 case TPS65911_REG_LDO6:
740 case TPS65911_REG_LDO7:
741 case TPS65911_REG_LDO8:
Jorge Eduardo Candelariaa320e3c2011-05-16 18:35:03 -0500742 return tps65910_modify_bits(pmic, reg,
743 (selector << LDO_SEL_SHIFT), LDO3_SEL_MASK);
Laxman Dewangane882eae2012-02-17 18:56:11 +0530744 case TPS65910_REG_VIO:
745 return tps65910_modify_bits(pmic, reg,
746 (selector << LDO_SEL_SHIFT), LDO_SEL_MASK);
Jorge Eduardo Candelariaa320e3c2011-05-16 18:35:03 -0500747 }
748
749 return -EINVAL;
750}
751
752
Graeme Gregory518fb722011-05-02 16:20:08 -0500753static int tps65910_list_voltage_dcdc(struct regulator_dev *dev,
754 unsigned selector)
755{
Jorge Eduardo Candelariaa320e3c2011-05-16 18:35:03 -0500756 int volt, mult = 1, id = rdev_get_id(dev);
Graeme Gregory518fb722011-05-02 16:20:08 -0500757
Jorge Eduardo Candelariaa320e3c2011-05-16 18:35:03 -0500758 switch (id) {
759 case TPS65910_REG_VDD1:
760 case TPS65910_REG_VDD2:
Afzal Mohammed780dc9b2011-11-08 18:54:10 +0530761 mult = (selector / VDD1_2_NUM_VOLT_FINE) + 1;
Jorge Eduardo Candelariaa320e3c2011-05-16 18:35:03 -0500762 volt = VDD1_2_MIN_VOLT +
Afzal Mohammed780dc9b2011-11-08 18:54:10 +0530763 (selector % VDD1_2_NUM_VOLT_FINE) * VDD1_2_OFFSET;
Axel Lind04156b2011-07-10 21:44:09 +0800764 break;
Jorge Eduardo Candelariaa320e3c2011-05-16 18:35:03 -0500765 case TPS65911_REG_VDDCTRL:
766 volt = VDDCTRL_MIN_VOLT + (selector * VDDCTRL_OFFSET);
Axel Lind04156b2011-07-10 21:44:09 +0800767 break;
768 default:
769 BUG();
770 return -EINVAL;
Jorge Eduardo Candelariaa320e3c2011-05-16 18:35:03 -0500771 }
Graeme Gregory518fb722011-05-02 16:20:08 -0500772
773 return volt * 100 * mult;
774}
775
776static int tps65910_list_voltage(struct regulator_dev *dev,
777 unsigned selector)
778{
779 struct tps65910_reg *pmic = rdev_get_drvdata(dev);
780 int id = rdev_get_id(dev), voltage;
781
782 if (id < TPS65910_REG_VIO || id > TPS65910_REG_VMMC)
783 return -EINVAL;
784
Laxman Dewangan7d38a3c2012-01-20 16:36:22 +0530785 if (selector >= pmic->info[id]->n_voltages)
Graeme Gregory518fb722011-05-02 16:20:08 -0500786 return -EINVAL;
787 else
Laxman Dewangan7d38a3c2012-01-20 16:36:22 +0530788 voltage = pmic->info[id]->voltage_table[selector] * 1000;
Graeme Gregory518fb722011-05-02 16:20:08 -0500789
790 return voltage;
791}
792
Jorge Eduardo Candelariaa320e3c2011-05-16 18:35:03 -0500793static int tps65911_list_voltage(struct regulator_dev *dev, unsigned selector)
794{
795 struct tps65910_reg *pmic = rdev_get_drvdata(dev);
796 int step_mv = 0, id = rdev_get_id(dev);
797
798 switch(id) {
799 case TPS65911_REG_LDO1:
800 case TPS65911_REG_LDO2:
801 case TPS65911_REG_LDO4:
802 /* The first 5 values of the selector correspond to 1V */
803 if (selector < 5)
804 selector = 0;
805 else
806 selector -= 4;
807
808 step_mv = 50;
809 break;
810 case TPS65911_REG_LDO3:
811 case TPS65911_REG_LDO5:
812 case TPS65911_REG_LDO6:
813 case TPS65911_REG_LDO7:
814 case TPS65911_REG_LDO8:
815 /* The first 3 values of the selector correspond to 1V */
816 if (selector < 3)
817 selector = 0;
818 else
819 selector -= 2;
820
821 step_mv = 100;
822 break;
823 case TPS65910_REG_VIO:
Laxman Dewangan7d38a3c2012-01-20 16:36:22 +0530824 return pmic->info[id]->voltage_table[selector] * 1000;
Jorge Eduardo Candelariaa320e3c2011-05-16 18:35:03 -0500825 default:
826 return -EINVAL;
827 }
828
829 return (LDO_MIN_VOLT + selector * step_mv) * 1000;
830}
831
Laxman Dewangan18039e02012-03-14 13:00:58 +0530832static int tps65910_set_voltage_dcdc_time_sel(struct regulator_dev *dev,
833 unsigned int old_selector, unsigned int new_selector)
834{
835 int id = rdev_get_id(dev);
836 int old_volt, new_volt;
837
838 old_volt = tps65910_list_voltage_dcdc(dev, old_selector);
839 if (old_volt < 0)
840 return old_volt;
841
842 new_volt = tps65910_list_voltage_dcdc(dev, new_selector);
843 if (new_volt < 0)
844 return new_volt;
845
846 /* VDD1 and VDD2 are 12.5mV/us, VDDCTRL is 100mV/20us */
847 switch (id) {
848 case TPS65910_REG_VDD1:
849 case TPS65910_REG_VDD2:
850 return DIV_ROUND_UP(abs(old_volt - new_volt), 12500);
851 case TPS65911_REG_VDDCTRL:
852 return DIV_ROUND_UP(abs(old_volt - new_volt), 5000);
853 }
854 return -EINVAL;
855}
856
Graeme Gregory518fb722011-05-02 16:20:08 -0500857/* Regulator ops (except VRTC) */
858static struct regulator_ops tps65910_ops_dcdc = {
Axel Lina40a9c42012-04-17 14:34:46 +0800859 .is_enabled = regulator_is_enabled_regmap,
860 .enable = regulator_enable_regmap,
861 .disable = regulator_disable_regmap,
Laxman Dewangan0651eed2012-03-13 11:35:20 +0530862 .enable_time = tps65910_enable_time,
Graeme Gregory518fb722011-05-02 16:20:08 -0500863 .set_mode = tps65910_set_mode,
864 .get_mode = tps65910_get_mode,
Laxman Dewangan18039e02012-03-14 13:00:58 +0530865 .get_voltage_sel = tps65910_get_voltage_dcdc_sel,
Axel Lin94732b92012-03-09 10:22:20 +0800866 .set_voltage_sel = tps65910_set_voltage_dcdc_sel,
Laxman Dewangan18039e02012-03-14 13:00:58 +0530867 .set_voltage_time_sel = tps65910_set_voltage_dcdc_time_sel,
Graeme Gregory518fb722011-05-02 16:20:08 -0500868 .list_voltage = tps65910_list_voltage_dcdc,
869};
870
871static struct regulator_ops tps65910_ops_vdd3 = {
Axel Lina40a9c42012-04-17 14:34:46 +0800872 .is_enabled = regulator_is_enabled_regmap,
873 .enable = regulator_enable_regmap,
874 .disable = regulator_disable_regmap,
Laxman Dewangan0651eed2012-03-13 11:35:20 +0530875 .enable_time = tps65910_enable_time,
Graeme Gregory518fb722011-05-02 16:20:08 -0500876 .set_mode = tps65910_set_mode,
877 .get_mode = tps65910_get_mode,
878 .get_voltage = tps65910_get_voltage_vdd3,
879 .list_voltage = tps65910_list_voltage,
880};
881
882static struct regulator_ops tps65910_ops = {
Axel Lina40a9c42012-04-17 14:34:46 +0800883 .is_enabled = regulator_is_enabled_regmap,
884 .enable = regulator_enable_regmap,
885 .disable = regulator_disable_regmap,
Laxman Dewangan0651eed2012-03-13 11:35:20 +0530886 .enable_time = tps65910_enable_time,
Graeme Gregory518fb722011-05-02 16:20:08 -0500887 .set_mode = tps65910_set_mode,
888 .get_mode = tps65910_get_mode,
Axel Lin1f904fd2012-05-09 09:22:47 +0800889 .get_voltage_sel = tps65910_get_voltage_sel,
Axel Lin94732b92012-03-09 10:22:20 +0800890 .set_voltage_sel = tps65910_set_voltage_sel,
Graeme Gregory518fb722011-05-02 16:20:08 -0500891 .list_voltage = tps65910_list_voltage,
892};
893
Jorge Eduardo Candelariaa320e3c2011-05-16 18:35:03 -0500894static struct regulator_ops tps65911_ops = {
Axel Lina40a9c42012-04-17 14:34:46 +0800895 .is_enabled = regulator_is_enabled_regmap,
896 .enable = regulator_enable_regmap,
897 .disable = regulator_disable_regmap,
Laxman Dewangan0651eed2012-03-13 11:35:20 +0530898 .enable_time = tps65910_enable_time,
Jorge Eduardo Candelariaa320e3c2011-05-16 18:35:03 -0500899 .set_mode = tps65910_set_mode,
900 .get_mode = tps65910_get_mode,
Axel Lin1f904fd2012-05-09 09:22:47 +0800901 .get_voltage_sel = tps65911_get_voltage_sel,
Axel Lin94732b92012-03-09 10:22:20 +0800902 .set_voltage_sel = tps65911_set_voltage_sel,
Jorge Eduardo Candelariaa320e3c2011-05-16 18:35:03 -0500903 .list_voltage = tps65911_list_voltage,
904};
905
Laxman Dewangan1e0c66f2012-01-28 15:07:57 +0530906static int tps65910_set_ext_sleep_config(struct tps65910_reg *pmic,
907 int id, int ext_sleep_config)
908{
909 struct tps65910 *mfd = pmic->mfd;
910 u8 regoffs = (pmic->ext_sleep_control[id] >> 8) & 0xFF;
911 u8 bit_pos = (1 << pmic->ext_sleep_control[id] & 0xFF);
912 int ret;
913
914 /*
915 * Regulator can not be control from multiple external input EN1, EN2
916 * and EN3 together.
917 */
918 if (ext_sleep_config & EXT_SLEEP_CONTROL) {
919 int en_count;
920 en_count = ((ext_sleep_config &
921 TPS65910_SLEEP_CONTROL_EXT_INPUT_EN1) != 0);
922 en_count += ((ext_sleep_config &
923 TPS65910_SLEEP_CONTROL_EXT_INPUT_EN2) != 0);
924 en_count += ((ext_sleep_config &
925 TPS65910_SLEEP_CONTROL_EXT_INPUT_EN3) != 0);
Laxman Dewanganf30b0712012-03-07 18:21:49 +0530926 en_count += ((ext_sleep_config &
927 TPS65911_SLEEP_CONTROL_EXT_INPUT_SLEEP) != 0);
Laxman Dewangan1e0c66f2012-01-28 15:07:57 +0530928 if (en_count > 1) {
929 dev_err(mfd->dev,
930 "External sleep control flag is not proper\n");
931 return -EINVAL;
932 }
933 }
934
935 pmic->board_ext_control[id] = ext_sleep_config;
936
937 /* External EN1 control */
938 if (ext_sleep_config & TPS65910_SLEEP_CONTROL_EXT_INPUT_EN1)
939 ret = tps65910_set_bits(mfd,
940 TPS65910_EN1_LDO_ASS + regoffs, bit_pos);
941 else
942 ret = tps65910_clear_bits(mfd,
943 TPS65910_EN1_LDO_ASS + regoffs, bit_pos);
944 if (ret < 0) {
945 dev_err(mfd->dev,
946 "Error in configuring external control EN1\n");
947 return ret;
948 }
949
950 /* External EN2 control */
951 if (ext_sleep_config & TPS65910_SLEEP_CONTROL_EXT_INPUT_EN2)
952 ret = tps65910_set_bits(mfd,
953 TPS65910_EN2_LDO_ASS + regoffs, bit_pos);
954 else
955 ret = tps65910_clear_bits(mfd,
956 TPS65910_EN2_LDO_ASS + regoffs, bit_pos);
957 if (ret < 0) {
958 dev_err(mfd->dev,
959 "Error in configuring external control EN2\n");
960 return ret;
961 }
962
963 /* External EN3 control for TPS65910 LDO only */
964 if ((tps65910_chip_id(mfd) == TPS65910) &&
965 (id >= TPS65910_REG_VDIG1)) {
966 if (ext_sleep_config & TPS65910_SLEEP_CONTROL_EXT_INPUT_EN3)
967 ret = tps65910_set_bits(mfd,
968 TPS65910_EN3_LDO_ASS + regoffs, bit_pos);
969 else
970 ret = tps65910_clear_bits(mfd,
971 TPS65910_EN3_LDO_ASS + regoffs, bit_pos);
972 if (ret < 0) {
973 dev_err(mfd->dev,
974 "Error in configuring external control EN3\n");
975 return ret;
976 }
977 }
978
979 /* Return if no external control is selected */
980 if (!(ext_sleep_config & EXT_SLEEP_CONTROL)) {
981 /* Clear all sleep controls */
982 ret = tps65910_clear_bits(mfd,
983 TPS65910_SLEEP_KEEP_LDO_ON + regoffs, bit_pos);
984 if (!ret)
985 ret = tps65910_clear_bits(mfd,
986 TPS65910_SLEEP_SET_LDO_OFF + regoffs, bit_pos);
987 if (ret < 0)
988 dev_err(mfd->dev,
989 "Error in configuring SLEEP register\n");
990 return ret;
991 }
992
993 /*
994 * For regulator that has separate operational and sleep register make
995 * sure that operational is used and clear sleep register to turn
996 * regulator off when external control is inactive
997 */
998 if ((id == TPS65910_REG_VDD1) ||
999 (id == TPS65910_REG_VDD2) ||
1000 ((id == TPS65911_REG_VDDCTRL) &&
1001 (tps65910_chip_id(mfd) == TPS65911))) {
1002 int op_reg_add = pmic->get_ctrl_reg(id) + 1;
1003 int sr_reg_add = pmic->get_ctrl_reg(id) + 2;
1004 int opvsel = tps65910_reg_read(pmic, op_reg_add);
1005 int srvsel = tps65910_reg_read(pmic, sr_reg_add);
1006 if (opvsel & VDD1_OP_CMD_MASK) {
1007 u8 reg_val = srvsel & VDD1_OP_SEL_MASK;
1008 ret = tps65910_reg_write(pmic, op_reg_add, reg_val);
1009 if (ret < 0) {
1010 dev_err(mfd->dev,
1011 "Error in configuring op register\n");
1012 return ret;
1013 }
1014 }
1015 ret = tps65910_reg_write(pmic, sr_reg_add, 0);
1016 if (ret < 0) {
1017 dev_err(mfd->dev, "Error in settting sr register\n");
1018 return ret;
1019 }
1020 }
1021
1022 ret = tps65910_clear_bits(mfd,
1023 TPS65910_SLEEP_KEEP_LDO_ON + regoffs, bit_pos);
Laxman Dewanganf30b0712012-03-07 18:21:49 +05301024 if (!ret) {
1025 if (ext_sleep_config & TPS65911_SLEEP_CONTROL_EXT_INPUT_SLEEP)
1026 ret = tps65910_set_bits(mfd,
1027 TPS65910_SLEEP_SET_LDO_OFF + regoffs, bit_pos);
1028 else
1029 ret = tps65910_clear_bits(mfd,
1030 TPS65910_SLEEP_SET_LDO_OFF + regoffs, bit_pos);
1031 }
Laxman Dewangan1e0c66f2012-01-28 15:07:57 +05301032 if (ret < 0)
1033 dev_err(mfd->dev,
1034 "Error in configuring SLEEP register\n");
Laxman Dewanganf30b0712012-03-07 18:21:49 +05301035
Laxman Dewangan1e0c66f2012-01-28 15:07:57 +05301036 return ret;
1037}
1038
Rhyland Klein67901782012-05-08 11:42:41 -07001039#ifdef CONFIG_OF
1040
1041static struct of_regulator_match tps65910_matches[] = {
Laxman Dewangan33a69432012-05-19 20:04:06 +05301042 { .name = "vrtc", .driver_data = (void *) &tps65910_regs[0] },
1043 { .name = "vio", .driver_data = (void *) &tps65910_regs[1] },
1044 { .name = "vdd1", .driver_data = (void *) &tps65910_regs[2] },
1045 { .name = "vdd2", .driver_data = (void *) &tps65910_regs[3] },
1046 { .name = "vdd3", .driver_data = (void *) &tps65910_regs[4] },
1047 { .name = "vdig1", .driver_data = (void *) &tps65910_regs[5] },
1048 { .name = "vdig2", .driver_data = (void *) &tps65910_regs[6] },
1049 { .name = "vpll", .driver_data = (void *) &tps65910_regs[7] },
1050 { .name = "vdac", .driver_data = (void *) &tps65910_regs[8] },
1051 { .name = "vaux1", .driver_data = (void *) &tps65910_regs[9] },
1052 { .name = "vaux2", .driver_data = (void *) &tps65910_regs[10] },
1053 { .name = "vaux33", .driver_data = (void *) &tps65910_regs[11] },
1054 { .name = "vmmc", .driver_data = (void *) &tps65910_regs[12] },
Rhyland Klein67901782012-05-08 11:42:41 -07001055};
1056
1057static struct of_regulator_match tps65911_matches[] = {
Laxman Dewangan33a69432012-05-19 20:04:06 +05301058 { .name = "vrtc", .driver_data = (void *) &tps65911_regs[0] },
1059 { .name = "vio", .driver_data = (void *) &tps65911_regs[1] },
1060 { .name = "vdd1", .driver_data = (void *) &tps65911_regs[2] },
1061 { .name = "vdd2", .driver_data = (void *) &tps65911_regs[3] },
1062 { .name = "vddctrl", .driver_data = (void *) &tps65911_regs[4] },
1063 { .name = "ldo1", .driver_data = (void *) &tps65911_regs[5] },
1064 { .name = "ldo2", .driver_data = (void *) &tps65911_regs[6] },
1065 { .name = "ldo3", .driver_data = (void *) &tps65911_regs[7] },
1066 { .name = "ldo4", .driver_data = (void *) &tps65911_regs[8] },
1067 { .name = "ldo5", .driver_data = (void *) &tps65911_regs[9] },
1068 { .name = "ldo6", .driver_data = (void *) &tps65911_regs[10] },
1069 { .name = "ldo7", .driver_data = (void *) &tps65911_regs[11] },
1070 { .name = "ldo8", .driver_data = (void *) &tps65911_regs[12] },
Rhyland Klein67901782012-05-08 11:42:41 -07001071};
1072
1073static struct tps65910_board *tps65910_parse_dt_reg_data(
1074 struct platform_device *pdev)
1075{
1076 struct tps65910_board *pmic_plat_data;
1077 struct tps65910 *tps65910 = dev_get_drvdata(pdev->dev.parent);
1078 struct device_node *np = pdev->dev.parent->of_node;
1079 struct device_node *regulators;
1080 struct of_regulator_match *matches;
1081 unsigned int prop;
1082 int idx = 0, ret, count;
1083
1084 pmic_plat_data = devm_kzalloc(&pdev->dev, sizeof(*pmic_plat_data),
1085 GFP_KERNEL);
1086
1087 if (!pmic_plat_data) {
1088 dev_err(&pdev->dev, "Failure to alloc pdata for regulators.\n");
1089 return NULL;
1090 }
1091
1092 regulators = of_find_node_by_name(np, "regulators");
1093
1094 switch (tps65910_chip_id(tps65910)) {
1095 case TPS65910:
1096 count = ARRAY_SIZE(tps65910_matches);
1097 matches = tps65910_matches;
1098 break;
1099 case TPS65911:
1100 count = ARRAY_SIZE(tps65911_matches);
1101 matches = tps65911_matches;
1102 break;
1103 default:
Laxman Dewangan7e9a57e2012-05-20 21:48:48 +05301104 dev_err(&pdev->dev, "Invalid tps chip version\n");
Rhyland Klein67901782012-05-08 11:42:41 -07001105 return NULL;
1106 }
1107
1108 ret = of_regulator_match(pdev->dev.parent, regulators, matches, count);
1109 if (ret < 0) {
1110 dev_err(&pdev->dev, "Error parsing regulator init data: %d\n",
1111 ret);
1112 return NULL;
1113 }
1114
1115 for (idx = 0; idx < count; idx++) {
1116 if (!matches[idx].init_data || !matches[idx].of_node)
1117 continue;
1118
1119 pmic_plat_data->tps65910_pmic_init_data[idx] =
1120 matches[idx].init_data;
1121
1122 ret = of_property_read_u32(matches[idx].of_node,
1123 "ti,regulator-ext-sleep-control", &prop);
1124 if (!ret)
1125 pmic_plat_data->regulator_ext_sleep_control[idx] = prop;
1126 }
1127
1128 return pmic_plat_data;
1129}
1130#else
1131static inline struct tps65910_board *tps65910_parse_dt_reg_data(
1132 struct platform_device *pdev)
1133{
1134 return 0;
1135}
1136#endif
1137
Graeme Gregory518fb722011-05-02 16:20:08 -05001138static __devinit int tps65910_probe(struct platform_device *pdev)
1139{
1140 struct tps65910 *tps65910 = dev_get_drvdata(pdev->dev.parent);
Mark Brownc1727082012-04-04 00:50:22 +01001141 struct regulator_config config = { };
Jorge Eduardo Candelariaa320e3c2011-05-16 18:35:03 -05001142 struct tps_info *info;
Graeme Gregory518fb722011-05-02 16:20:08 -05001143 struct regulator_init_data *reg_data;
1144 struct regulator_dev *rdev;
1145 struct tps65910_reg *pmic;
1146 struct tps65910_board *pmic_plat_data;
Graeme Gregory518fb722011-05-02 16:20:08 -05001147 int i, err;
1148
1149 pmic_plat_data = dev_get_platdata(tps65910->dev);
Rhyland Klein67901782012-05-08 11:42:41 -07001150 if (!pmic_plat_data && tps65910->dev->of_node)
1151 pmic_plat_data = tps65910_parse_dt_reg_data(pdev);
1152
Laxman Dewangan7e9a57e2012-05-20 21:48:48 +05301153 if (!pmic_plat_data) {
1154 dev_err(&pdev->dev, "Platform data not found\n");
Graeme Gregory518fb722011-05-02 16:20:08 -05001155 return -EINVAL;
Laxman Dewangan7e9a57e2012-05-20 21:48:48 +05301156 }
Graeme Gregory518fb722011-05-02 16:20:08 -05001157
Axel Lin9eb0c422012-04-11 14:40:18 +08001158 pmic = devm_kzalloc(&pdev->dev, sizeof(*pmic), GFP_KERNEL);
Laxman Dewangan7e9a57e2012-05-20 21:48:48 +05301159 if (!pmic) {
1160 dev_err(&pdev->dev, "Memory allocation failed for pmic\n");
Graeme Gregory518fb722011-05-02 16:20:08 -05001161 return -ENOMEM;
Laxman Dewangan7e9a57e2012-05-20 21:48:48 +05301162 }
Graeme Gregory518fb722011-05-02 16:20:08 -05001163
1164 mutex_init(&pmic->mutex);
1165 pmic->mfd = tps65910;
1166 platform_set_drvdata(pdev, pmic);
1167
1168 /* Give control of all register to control port */
1169 tps65910_set_bits(pmic->mfd, TPS65910_DEVCTRL,
1170 DEVCTRL_SR_CTL_I2C_SEL_MASK);
1171
Jorge Eduardo Candelariaa320e3c2011-05-16 18:35:03 -05001172 switch(tps65910_chip_id(tps65910)) {
1173 case TPS65910:
1174 pmic->get_ctrl_reg = &tps65910_get_ctrl_register;
Axel Lin39aa9b62011-07-11 09:57:43 +08001175 pmic->num_regulators = ARRAY_SIZE(tps65910_regs);
Laxman Dewangan1e0c66f2012-01-28 15:07:57 +05301176 pmic->ext_sleep_control = tps65910_ext_sleep_control;
Jorge Eduardo Candelariaa320e3c2011-05-16 18:35:03 -05001177 info = tps65910_regs;
Axel Lind04156b2011-07-10 21:44:09 +08001178 break;
Jorge Eduardo Candelariaa320e3c2011-05-16 18:35:03 -05001179 case TPS65911:
1180 pmic->get_ctrl_reg = &tps65911_get_ctrl_register;
Axel Lin39aa9b62011-07-11 09:57:43 +08001181 pmic->num_regulators = ARRAY_SIZE(tps65911_regs);
Laxman Dewangan1e0c66f2012-01-28 15:07:57 +05301182 pmic->ext_sleep_control = tps65911_ext_sleep_control;
Jorge Eduardo Candelariaa320e3c2011-05-16 18:35:03 -05001183 info = tps65911_regs;
Axel Lind04156b2011-07-10 21:44:09 +08001184 break;
Jorge Eduardo Candelariaa320e3c2011-05-16 18:35:03 -05001185 default:
Laxman Dewangan7e9a57e2012-05-20 21:48:48 +05301186 dev_err(&pdev->dev, "Invalid tps chip version\n");
Jorge Eduardo Candelariaa320e3c2011-05-16 18:35:03 -05001187 return -ENODEV;
1188 }
1189
Laxman Dewangan68d8c1c2012-05-19 20:04:09 +05301190 pmic->desc = devm_kzalloc(&pdev->dev, pmic->num_regulators *
Axel Lin39aa9b62011-07-11 09:57:43 +08001191 sizeof(struct regulator_desc), GFP_KERNEL);
1192 if (!pmic->desc) {
Laxman Dewangan68d8c1c2012-05-19 20:04:09 +05301193 dev_err(&pdev->dev, "Memory alloc fails for desc\n");
1194 return -ENOMEM;
Axel Lin39aa9b62011-07-11 09:57:43 +08001195 }
1196
Laxman Dewangan68d8c1c2012-05-19 20:04:09 +05301197 pmic->info = devm_kzalloc(&pdev->dev, pmic->num_regulators *
Axel Lin39aa9b62011-07-11 09:57:43 +08001198 sizeof(struct tps_info *), GFP_KERNEL);
1199 if (!pmic->info) {
Laxman Dewangan68d8c1c2012-05-19 20:04:09 +05301200 dev_err(&pdev->dev, "Memory alloc fails for info\n");
1201 return -ENOMEM;
Axel Lin39aa9b62011-07-11 09:57:43 +08001202 }
1203
Laxman Dewangan68d8c1c2012-05-19 20:04:09 +05301204 pmic->rdev = devm_kzalloc(&pdev->dev, pmic->num_regulators *
Axel Lin39aa9b62011-07-11 09:57:43 +08001205 sizeof(struct regulator_dev *), GFP_KERNEL);
1206 if (!pmic->rdev) {
Laxman Dewangan68d8c1c2012-05-19 20:04:09 +05301207 dev_err(&pdev->dev, "Memory alloc fails for rdev\n");
1208 return -ENOMEM;
Axel Lin39aa9b62011-07-11 09:57:43 +08001209 }
1210
Kyle Mannac1fc1482011-11-03 12:08:06 -05001211 for (i = 0; i < pmic->num_regulators && i < TPS65910_NUM_REGS;
1212 i++, info++) {
1213
1214 reg_data = pmic_plat_data->tps65910_pmic_init_data[i];
1215
1216 /* Regulator API handles empty constraints but not NULL
1217 * constraints */
1218 if (!reg_data)
1219 continue;
1220
Graeme Gregory518fb722011-05-02 16:20:08 -05001221 /* Register the regulators */
1222 pmic->info[i] = info;
1223
1224 pmic->desc[i].name = info->name;
Axel Lin77fa44d2011-05-12 13:47:50 +08001225 pmic->desc[i].id = i;
Laxman Dewangan7d38a3c2012-01-20 16:36:22 +05301226 pmic->desc[i].n_voltages = info->n_voltages;
Graeme Gregory518fb722011-05-02 16:20:08 -05001227
Jorge Eduardo Candelariaa320e3c2011-05-16 18:35:03 -05001228 if (i == TPS65910_REG_VDD1 || i == TPS65910_REG_VDD2) {
Graeme Gregory518fb722011-05-02 16:20:08 -05001229 pmic->desc[i].ops = &tps65910_ops_dcdc;
Afzal Mohammed780dc9b2011-11-08 18:54:10 +05301230 pmic->desc[i].n_voltages = VDD1_2_NUM_VOLT_FINE *
1231 VDD1_2_NUM_VOLT_COARSE;
Jorge Eduardo Candelariaa320e3c2011-05-16 18:35:03 -05001232 } else if (i == TPS65910_REG_VDD3) {
1233 if (tps65910_chip_id(tps65910) == TPS65910)
1234 pmic->desc[i].ops = &tps65910_ops_vdd3;
1235 else
1236 pmic->desc[i].ops = &tps65910_ops_dcdc;
1237 } else {
1238 if (tps65910_chip_id(tps65910) == TPS65910)
1239 pmic->desc[i].ops = &tps65910_ops;
1240 else
1241 pmic->desc[i].ops = &tps65911_ops;
1242 }
Graeme Gregory518fb722011-05-02 16:20:08 -05001243
Laxman Dewangan1e0c66f2012-01-28 15:07:57 +05301244 err = tps65910_set_ext_sleep_config(pmic, i,
1245 pmic_plat_data->regulator_ext_sleep_control[i]);
1246 /*
1247 * Failing on regulator for configuring externally control
1248 * is not a serious issue, just throw warning.
1249 */
1250 if (err < 0)
1251 dev_warn(tps65910->dev,
1252 "Failed to initialise ext control config\n");
1253
Graeme Gregory518fb722011-05-02 16:20:08 -05001254 pmic->desc[i].type = REGULATOR_VOLTAGE;
1255 pmic->desc[i].owner = THIS_MODULE;
Axel Lina40a9c42012-04-17 14:34:46 +08001256 pmic->desc[i].enable_reg = pmic->get_ctrl_reg(i);
1257 pmic->desc[i].enable_mask = TPS65910_SUPPLY_STATE_ENABLED;
Graeme Gregory518fb722011-05-02 16:20:08 -05001258
Mark Brownc1727082012-04-04 00:50:22 +01001259 config.dev = tps65910->dev;
1260 config.init_data = reg_data;
1261 config.driver_data = pmic;
Axel Lina40a9c42012-04-17 14:34:46 +08001262 config.regmap = tps65910->regmap;
Mark Brownc1727082012-04-04 00:50:22 +01001263
Rhyland Klein67901782012-05-08 11:42:41 -07001264#ifdef CONFIG_OF
1265 config.of_node = of_find_node_by_name(tps65910->dev->of_node,
1266 info->name);
1267#endif
1268
Mark Brownc1727082012-04-04 00:50:22 +01001269 rdev = regulator_register(&pmic->desc[i], &config);
Graeme Gregory518fb722011-05-02 16:20:08 -05001270 if (IS_ERR(rdev)) {
1271 dev_err(tps65910->dev,
1272 "failed to register %s regulator\n",
1273 pdev->name);
1274 err = PTR_ERR(rdev);
Axel Lin39aa9b62011-07-11 09:57:43 +08001275 goto err_unregister_regulator;
Graeme Gregory518fb722011-05-02 16:20:08 -05001276 }
1277
1278 /* Save regulator for cleanup */
1279 pmic->rdev[i] = rdev;
1280 }
1281 return 0;
1282
Axel Lin39aa9b62011-07-11 09:57:43 +08001283err_unregister_regulator:
Graeme Gregory518fb722011-05-02 16:20:08 -05001284 while (--i >= 0)
1285 regulator_unregister(pmic->rdev[i]);
Graeme Gregory518fb722011-05-02 16:20:08 -05001286 return err;
1287}
1288
1289static int __devexit tps65910_remove(struct platform_device *pdev)
1290{
Axel Lin39aa9b62011-07-11 09:57:43 +08001291 struct tps65910_reg *pmic = platform_get_drvdata(pdev);
Graeme Gregory518fb722011-05-02 16:20:08 -05001292 int i;
1293
Axel Lin39aa9b62011-07-11 09:57:43 +08001294 for (i = 0; i < pmic->num_regulators; i++)
1295 regulator_unregister(pmic->rdev[i]);
Graeme Gregory518fb722011-05-02 16:20:08 -05001296
Graeme Gregory518fb722011-05-02 16:20:08 -05001297 return 0;
1298}
1299
Laxman Dewangan1e0c66f2012-01-28 15:07:57 +05301300static void tps65910_shutdown(struct platform_device *pdev)
1301{
1302 struct tps65910_reg *pmic = platform_get_drvdata(pdev);
1303 int i;
1304
1305 /*
1306 * Before bootloader jumps to kernel, it makes sure that required
1307 * external control signals are in desired state so that given rails
1308 * can be configure accordingly.
1309 * If rails are configured to be controlled from external control
1310 * then before shutting down/rebooting the system, the external
1311 * control configuration need to be remove from the rails so that
1312 * its output will be available as per register programming even
1313 * if external controls are removed. This is require when the POR
1314 * value of the control signals are not in active state and before
1315 * bootloader initializes it, the system requires the rail output
1316 * to be active for booting.
1317 */
1318 for (i = 0; i < pmic->num_regulators; i++) {
1319 int err;
1320 if (!pmic->rdev[i])
1321 continue;
1322
1323 err = tps65910_set_ext_sleep_config(pmic, i, 0);
1324 if (err < 0)
1325 dev_err(&pdev->dev,
1326 "Error in clearing external control\n");
1327 }
1328}
1329
Graeme Gregory518fb722011-05-02 16:20:08 -05001330static struct platform_driver tps65910_driver = {
1331 .driver = {
1332 .name = "tps65910-pmic",
1333 .owner = THIS_MODULE,
1334 },
1335 .probe = tps65910_probe,
1336 .remove = __devexit_p(tps65910_remove),
Laxman Dewangan1e0c66f2012-01-28 15:07:57 +05301337 .shutdown = tps65910_shutdown,
Graeme Gregory518fb722011-05-02 16:20:08 -05001338};
1339
1340static int __init tps65910_init(void)
1341{
1342 return platform_driver_register(&tps65910_driver);
1343}
1344subsys_initcall(tps65910_init);
1345
1346static void __exit tps65910_cleanup(void)
1347{
1348 platform_driver_unregister(&tps65910_driver);
1349}
1350module_exit(tps65910_cleanup);
1351
1352MODULE_AUTHOR("Graeme Gregory <gg@slimlogic.co.uk>");
Axel Linae0e6542012-02-21 10:14:55 +08001353MODULE_DESCRIPTION("TPS65910/TPS65911 voltage regulator driver");
Graeme Gregory518fb722011-05-02 16:20:08 -05001354MODULE_LICENSE("GPL v2");
1355MODULE_ALIAS("platform:tps65910-pmic");