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Eilon Greensteind05c26c2009-01-17 23:26:13 -08001/* Copyright 2008-2009 Broadcom Corporation
Yaniv Rosnerea4e0402008-06-23 20:27:26 -07002 *
3 * Unless you and Broadcom execute a separate written software license
4 * agreement governing use of this software, this software is licensed to you
5 * under the terms of the GNU General Public License version 2, available
6 * at http://www.gnu.org/licenses/old-licenses/gpl-2.0.html (the "GPL").
7 *
8 * Notwithstanding the above, under no circumstances may you combine this
9 * software in any way with any other Broadcom software provided under a
10 * license other than the GPL, without Broadcom's express prior written
11 * consent.
12 *
13 * Written by Yaniv Rosner
14 *
15 */
16
Joe Perches7995c642010-02-17 15:01:52 +000017#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
18
Yaniv Rosnerea4e0402008-06-23 20:27:26 -070019#include <linux/kernel.h>
20#include <linux/errno.h>
21#include <linux/pci.h>
22#include <linux/netdevice.h>
23#include <linux/delay.h>
24#include <linux/ethtool.h>
25#include <linux/mutex.h>
Yaniv Rosnerea4e0402008-06-23 20:27:26 -070026
Yaniv Rosnerea4e0402008-06-23 20:27:26 -070027#include "bnx2x.h"
28
29/********************************************************/
Eilon Greenstein3196a882008-08-13 15:58:49 -070030#define ETH_HLEN 14
Dmitry Kravkov523224a2010-10-06 03:23:26 +000031#define ETH_OVREHEAD (ETH_HLEN + 8 + 8)/* 16 for CRC + VLAN + LLC */
Yaniv Rosnerea4e0402008-06-23 20:27:26 -070032#define ETH_MIN_PACKET_SIZE 60
33#define ETH_MAX_PACKET_SIZE 1500
34#define ETH_MAX_JUMBO_PACKET_SIZE 9600
35#define MDIO_ACCESS_TIMEOUT 1000
36#define BMAC_CONTROL_RX_ENABLE 2
Yaniv Rosnerea4e0402008-06-23 20:27:26 -070037
38/***********************************************************/
Eilon Greenstein3196a882008-08-13 15:58:49 -070039/* Shortcut definitions */
Yaniv Rosnerea4e0402008-06-23 20:27:26 -070040/***********************************************************/
41
Eilon Greenstein2f904462009-08-12 08:22:16 +000042#define NIG_LATCH_BC_ENABLE_MI_INT 0
43
44#define NIG_STATUS_EMAC0_MI_INT \
45 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_EMAC0_MISC_MI_INT
Yaniv Rosnerea4e0402008-06-23 20:27:26 -070046#define NIG_STATUS_XGXS0_LINK10G \
47 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK10G
48#define NIG_STATUS_XGXS0_LINK_STATUS \
49 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK_STATUS
50#define NIG_STATUS_XGXS0_LINK_STATUS_SIZE \
51 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK_STATUS_SIZE
52#define NIG_STATUS_SERDES0_LINK_STATUS \
53 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_SERDES0_LINK_STATUS
54#define NIG_MASK_MI_INT \
55 NIG_MASK_INTERRUPT_PORT0_REG_MASK_EMAC0_MISC_MI_INT
56#define NIG_MASK_XGXS0_LINK10G \
57 NIG_MASK_INTERRUPT_PORT0_REG_MASK_XGXS0_LINK10G
58#define NIG_MASK_XGXS0_LINK_STATUS \
59 NIG_MASK_INTERRUPT_PORT0_REG_MASK_XGXS0_LINK_STATUS
60#define NIG_MASK_SERDES0_LINK_STATUS \
61 NIG_MASK_INTERRUPT_PORT0_REG_MASK_SERDES0_LINK_STATUS
62
63#define MDIO_AN_CL73_OR_37_COMPLETE \
64 (MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_AUTONEG_COMPLETE | \
65 MDIO_GP_STATUS_TOP_AN_STATUS1_CL37_AUTONEG_COMPLETE)
66
67#define XGXS_RESET_BITS \
68 (MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_RSTB_HW | \
69 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_IDDQ | \
70 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_PWRDWN | \
71 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_PWRDWN_SD | \
72 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_TXD_FIFO_RSTB)
73
74#define SERDES_RESET_BITS \
75 (MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_RSTB_HW | \
76 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_IDDQ | \
77 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_PWRDWN | \
78 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_PWRDWN_SD)
79
80#define AUTONEG_CL37 SHARED_HW_CFG_AN_ENABLE_CL37
81#define AUTONEG_CL73 SHARED_HW_CFG_AN_ENABLE_CL73
Eilon Greenstein3196a882008-08-13 15:58:49 -070082#define AUTONEG_BAM SHARED_HW_CFG_AN_ENABLE_BAM
83#define AUTONEG_PARALLEL \
Yaniv Rosnerea4e0402008-06-23 20:27:26 -070084 SHARED_HW_CFG_AN_ENABLE_PARALLEL_DETECTION
Eilon Greenstein3196a882008-08-13 15:58:49 -070085#define AUTONEG_SGMII_FIBER_AUTODET \
Yaniv Rosnerea4e0402008-06-23 20:27:26 -070086 SHARED_HW_CFG_AN_EN_SGMII_FIBER_AUTO_DETECT
Eilon Greenstein3196a882008-08-13 15:58:49 -070087#define AUTONEG_REMOTE_PHY SHARED_HW_CFG_AN_ENABLE_REMOTE_PHY
Yaniv Rosnerea4e0402008-06-23 20:27:26 -070088
89#define GP_STATUS_PAUSE_RSOLUTION_TXSIDE \
90 MDIO_GP_STATUS_TOP_AN_STATUS1_PAUSE_RSOLUTION_TXSIDE
91#define GP_STATUS_PAUSE_RSOLUTION_RXSIDE \
92 MDIO_GP_STATUS_TOP_AN_STATUS1_PAUSE_RSOLUTION_RXSIDE
93#define GP_STATUS_SPEED_MASK \
94 MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_MASK
95#define GP_STATUS_10M MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10M
96#define GP_STATUS_100M MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_100M
97#define GP_STATUS_1G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_1G
98#define GP_STATUS_2_5G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_2_5G
99#define GP_STATUS_5G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_5G
100#define GP_STATUS_6G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_6G
101#define GP_STATUS_10G_HIG \
102 MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_HIG
103#define GP_STATUS_10G_CX4 \
104 MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_CX4
105#define GP_STATUS_12G_HIG \
106 MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_12G_HIG
107#define GP_STATUS_12_5G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_12_5G
108#define GP_STATUS_13G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_13G
109#define GP_STATUS_15G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_15G
110#define GP_STATUS_16G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_16G
111#define GP_STATUS_1G_KX MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_1G_KX
112#define GP_STATUS_10G_KX4 \
113 MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_KX4
114
115#define LINK_10THD LINK_STATUS_SPEED_AND_DUPLEX_10THD
116#define LINK_10TFD LINK_STATUS_SPEED_AND_DUPLEX_10TFD
117#define LINK_100TXHD LINK_STATUS_SPEED_AND_DUPLEX_100TXHD
118#define LINK_100T4 LINK_STATUS_SPEED_AND_DUPLEX_100T4
119#define LINK_100TXFD LINK_STATUS_SPEED_AND_DUPLEX_100TXFD
120#define LINK_1000THD LINK_STATUS_SPEED_AND_DUPLEX_1000THD
121#define LINK_1000TFD LINK_STATUS_SPEED_AND_DUPLEX_1000TFD
122#define LINK_1000XFD LINK_STATUS_SPEED_AND_DUPLEX_1000XFD
123#define LINK_2500THD LINK_STATUS_SPEED_AND_DUPLEX_2500THD
124#define LINK_2500TFD LINK_STATUS_SPEED_AND_DUPLEX_2500TFD
125#define LINK_2500XFD LINK_STATUS_SPEED_AND_DUPLEX_2500XFD
126#define LINK_10GTFD LINK_STATUS_SPEED_AND_DUPLEX_10GTFD
127#define LINK_10GXFD LINK_STATUS_SPEED_AND_DUPLEX_10GXFD
128#define LINK_12GTFD LINK_STATUS_SPEED_AND_DUPLEX_12GTFD
129#define LINK_12GXFD LINK_STATUS_SPEED_AND_DUPLEX_12GXFD
130#define LINK_12_5GTFD LINK_STATUS_SPEED_AND_DUPLEX_12_5GTFD
131#define LINK_12_5GXFD LINK_STATUS_SPEED_AND_DUPLEX_12_5GXFD
132#define LINK_13GTFD LINK_STATUS_SPEED_AND_DUPLEX_13GTFD
133#define LINK_13GXFD LINK_STATUS_SPEED_AND_DUPLEX_13GXFD
134#define LINK_15GTFD LINK_STATUS_SPEED_AND_DUPLEX_15GTFD
135#define LINK_15GXFD LINK_STATUS_SPEED_AND_DUPLEX_15GXFD
136#define LINK_16GTFD LINK_STATUS_SPEED_AND_DUPLEX_16GTFD
137#define LINK_16GXFD LINK_STATUS_SPEED_AND_DUPLEX_16GXFD
138
139#define PHY_XGXS_FLAG 0x1
140#define PHY_SGMII_FLAG 0x2
141#define PHY_SERDES_FLAG 0x4
142
Eilon Greenstein589abe32009-02-12 08:36:55 +0000143/* */
144#define SFP_EEPROM_CON_TYPE_ADDR 0x2
145 #define SFP_EEPROM_CON_TYPE_VAL_LC 0x7
146 #define SFP_EEPROM_CON_TYPE_VAL_COPPER 0x21
147
Eilon Greenstein4d295db2009-07-21 05:47:47 +0000148
149#define SFP_EEPROM_COMP_CODE_ADDR 0x3
150 #define SFP_EEPROM_COMP_CODE_SR_MASK (1<<4)
151 #define SFP_EEPROM_COMP_CODE_LR_MASK (1<<5)
152 #define SFP_EEPROM_COMP_CODE_LRM_MASK (1<<6)
153
Eilon Greenstein589abe32009-02-12 08:36:55 +0000154#define SFP_EEPROM_FC_TX_TECH_ADDR 0x8
155 #define SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_PASSIVE 0x4
156 #define SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_ACTIVE 0x8
Eilon Greenstein4d295db2009-07-21 05:47:47 +0000157
Eilon Greenstein589abe32009-02-12 08:36:55 +0000158#define SFP_EEPROM_OPTIONS_ADDR 0x40
159 #define SFP_EEPROM_OPTIONS_LINEAR_RX_OUT_MASK 0x1
160#define SFP_EEPROM_OPTIONS_SIZE 2
161
Eilon Greenstein4d295db2009-07-21 05:47:47 +0000162#define EDC_MODE_LINEAR 0x0022
163#define EDC_MODE_LIMITING 0x0044
164#define EDC_MODE_PASSIVE_DAC 0x0055
Eilon Greenstein589abe32009-02-12 08:36:55 +0000165
Eilon Greenstein4d295db2009-07-21 05:47:47 +0000166
Vladislav Zolotarovbcab15c2010-12-13 05:44:25 +0000167#define ETS_BW_LIMIT_CREDIT_UPPER_BOUND (0x5000)
168#define ETS_BW_LIMIT_CREDIT_WEIGHT (0x5000)
Yaniv Rosnerea4e0402008-06-23 20:27:26 -0700169/**********************************************************/
170/* INTERFACE */
171/**********************************************************/
Yaniv Rosnere10bc842010-09-07 11:40:50 +0000172
173#define CL45_WR_OVER_CL22(_bp, _phy, _bank, _addr, _val) \
174 bnx2x_cl45_write(_bp, _phy, \
Yaniv Rosner7aa07112010-09-07 11:41:01 +0000175 (_phy)->def_md_devad, \
Yaniv Rosnerea4e0402008-06-23 20:27:26 -0700176 (_bank + (_addr & 0xf)), \
177 _val)
178
Yaniv Rosnere10bc842010-09-07 11:40:50 +0000179#define CL45_RD_OVER_CL22(_bp, _phy, _bank, _addr, _val) \
180 bnx2x_cl45_read(_bp, _phy, \
Yaniv Rosner7aa07112010-09-07 11:41:01 +0000181 (_phy)->def_md_devad, \
Yaniv Rosnerea4e0402008-06-23 20:27:26 -0700182 (_bank + (_addr & 0xf)), \
183 _val)
184
stephen hemminger8d962862010-10-21 07:50:56 +0000185static u8 bnx2x_cl45_read(struct bnx2x *bp, struct bnx2x_phy *phy,
186 u8 devad, u16 reg, u16 *ret_val);
187
188static u8 bnx2x_cl45_write(struct bnx2x *bp, struct bnx2x_phy *phy,
189 u8 devad, u16 reg, u16 val);
190
Yaniv Rosnerea4e0402008-06-23 20:27:26 -0700191static u32 bnx2x_bits_en(struct bnx2x *bp, u32 reg, u32 bits)
192{
193 u32 val = REG_RD(bp, reg);
194
195 val |= bits;
196 REG_WR(bp, reg, val);
197 return val;
198}
199
200static u32 bnx2x_bits_dis(struct bnx2x *bp, u32 reg, u32 bits)
201{
202 u32 val = REG_RD(bp, reg);
203
204 val &= ~bits;
205 REG_WR(bp, reg, val);
206 return val;
207}
208
Vladislav Zolotarovbcab15c2010-12-13 05:44:25 +0000209/******************************************************************/
210/* ETS section */
211/******************************************************************/
212void bnx2x_ets_disabled(struct link_params *params)
213{
214 /* ETS disabled configuration*/
215 struct bnx2x *bp = params->bp;
216
217 DP(NETIF_MSG_LINK, "ETS disabled configuration\n");
218
219 /**
220 * mapping between entry priority to client number (0,1,2 -debug and
221 * management clients, 3 - COS0 client, 4 - COS client)(HIGHEST)
222 * 3bits client num.
223 * PRI4 | PRI3 | PRI2 | PRI1 | PRI0
224 * cos1-100 cos0-011 dbg1-010 dbg0-001 MCP-000
225 */
226
227 REG_WR(bp, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT, 0x4688);
228 /**
229 * Bitmap of 5bits length. Each bit specifies whether the entry behaves
230 * as strict. Bits 0,1,2 - debug and management entries, 3 -
231 * COS0 entry, 4 - COS1 entry.
232 * COS1 | COS0 | DEBUG1 | DEBUG0 | MGMT
233 * bit4 bit3 bit2 bit1 bit0
234 * MCP and debug are strict
235 */
236
237 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, 0x7);
238 /* defines which entries (clients) are subjected to WFQ arbitration */
239 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_SUBJECT2WFQ, 0);
240 /**
241 * For strict priority entries defines the number of consecutive
242 * slots for the highest priority.
243 */
244 REG_WR(bp, NIG_REG_P0_TX_ARB_NUM_STRICT_ARB_SLOTS, 0x100);
245 /**
246 * mapping between the CREDIT_WEIGHT registers and actual client
247 * numbers
248 */
249 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP, 0);
250 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_0, 0);
251 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_1, 0);
252
253 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_0, 0);
254 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_1, 0);
255 REG_WR(bp, PBF_REG_HIGH_PRIORITY_COS_NUM, 0);
256 /* ETS mode disable */
257 REG_WR(bp, PBF_REG_ETS_ENABLED, 0);
258 /**
259 * If ETS mode is enabled (there is no strict priority) defines a WFQ
260 * weight for COS0/COS1.
261 */
262 REG_WR(bp, PBF_REG_COS0_WEIGHT, 0x2710);
263 REG_WR(bp, PBF_REG_COS1_WEIGHT, 0x2710);
264 /* Upper bound that COS0_WEIGHT can reach in the WFQ arbiter */
265 REG_WR(bp, PBF_REG_COS0_UPPER_BOUND, 0x989680);
266 REG_WR(bp, PBF_REG_COS1_UPPER_BOUND, 0x989680);
267 /* Defines the number of consecutive slots for the strict priority */
268 REG_WR(bp, PBF_REG_NUM_STRICT_ARB_SLOTS, 0);
269}
270
271void bnx2x_ets_bw_limit_common(const struct link_params *params)
272{
273 /* ETS disabled configuration */
274 struct bnx2x *bp = params->bp;
275 DP(NETIF_MSG_LINK, "ETS enabled BW limit configuration\n");
276 /**
277 * defines which entries (clients) are subjected to WFQ arbitration
278 * COS0 0x8
279 * COS1 0x10
280 */
281 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_SUBJECT2WFQ, 0x18);
282 /**
283 * mapping between the ARB_CREDIT_WEIGHT registers and actual
284 * client numbers (WEIGHT_0 does not actually have to represent
285 * client 0)
286 * PRI4 | PRI3 | PRI2 | PRI1 | PRI0
287 * cos1-001 cos0-000 dbg1-100 dbg0-011 MCP-010
288 */
289 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP, 0x111A);
290
291 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_0,
292 ETS_BW_LIMIT_CREDIT_UPPER_BOUND);
293 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_1,
294 ETS_BW_LIMIT_CREDIT_UPPER_BOUND);
295
296 /* ETS mode enabled*/
297 REG_WR(bp, PBF_REG_ETS_ENABLED, 1);
298
299 /* Defines the number of consecutive slots for the strict priority */
300 REG_WR(bp, PBF_REG_NUM_STRICT_ARB_SLOTS, 0);
301 /**
302 * Bitmap of 5bits length. Each bit specifies whether the entry behaves
303 * as strict. Bits 0,1,2 - debug and management entries, 3 - COS0
304 * entry, 4 - COS1 entry.
305 * COS1 | COS0 | DEBUG21 | DEBUG0 | MGMT
306 * bit4 bit3 bit2 bit1 bit0
307 * MCP and debug are strict
308 */
309 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, 0x7);
310
311 /* Upper bound that COS0_WEIGHT can reach in the WFQ arbiter.*/
312 REG_WR(bp, PBF_REG_COS0_UPPER_BOUND,
313 ETS_BW_LIMIT_CREDIT_UPPER_BOUND);
314 REG_WR(bp, PBF_REG_COS1_UPPER_BOUND,
315 ETS_BW_LIMIT_CREDIT_UPPER_BOUND);
316}
317
318void bnx2x_ets_bw_limit(const struct link_params *params, const u32 cos0_bw,
319 const u32 cos1_bw)
320{
321 /* ETS disabled configuration*/
322 struct bnx2x *bp = params->bp;
323 const u32 total_bw = cos0_bw + cos1_bw;
324 u32 cos0_credit_weight = 0;
325 u32 cos1_credit_weight = 0;
326
327 DP(NETIF_MSG_LINK, "ETS enabled BW limit configuration\n");
328
329 if ((0 == total_bw) ||
330 (0 == cos0_bw) ||
331 (0 == cos1_bw)) {
332 DP(NETIF_MSG_LINK,
333 "bnx2x_ets_bw_limit: Total BW can't be zero\n");
334 return;
335 }
336
337 cos0_credit_weight = (cos0_bw * ETS_BW_LIMIT_CREDIT_WEIGHT)/
338 total_bw;
339 cos1_credit_weight = (cos1_bw * ETS_BW_LIMIT_CREDIT_WEIGHT)/
340 total_bw;
341
342 bnx2x_ets_bw_limit_common(params);
343
344 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_0, cos0_credit_weight);
345 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_1, cos1_credit_weight);
346
347 REG_WR(bp, PBF_REG_COS0_WEIGHT, cos0_credit_weight);
348 REG_WR(bp, PBF_REG_COS1_WEIGHT, cos1_credit_weight);
349}
350
351u8 bnx2x_ets_strict(const struct link_params *params, const u8 strict_cos)
352{
353 /* ETS disabled configuration*/
354 struct bnx2x *bp = params->bp;
355 u32 val = 0;
356
Vladislav Zolotarovbcab15c2010-12-13 05:44:25 +0000357 DP(NETIF_MSG_LINK, "ETS enabled strict configuration\n");
358 /**
359 * Bitmap of 5bits length. Each bit specifies whether the entry behaves
360 * as strict. Bits 0,1,2 - debug and management entries,
361 * 3 - COS0 entry, 4 - COS1 entry.
362 * COS1 | COS0 | DEBUG21 | DEBUG0 | MGMT
363 * bit4 bit3 bit2 bit1 bit0
364 * MCP and debug are strict
365 */
366 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, 0x1F);
367 /**
368 * For strict priority entries defines the number of consecutive slots
369 * for the highest priority.
370 */
371 REG_WR(bp, NIG_REG_P0_TX_ARB_NUM_STRICT_ARB_SLOTS, 0x100);
372 /* ETS mode disable */
373 REG_WR(bp, PBF_REG_ETS_ENABLED, 0);
374 /* Defines the number of consecutive slots for the strict priority */
375 REG_WR(bp, PBF_REG_NUM_STRICT_ARB_SLOTS, 0x100);
376
377 /* Defines the number of consecutive slots for the strict priority */
378 REG_WR(bp, PBF_REG_HIGH_PRIORITY_COS_NUM, strict_cos);
379
380 /**
381 * mapping between entry priority to client number (0,1,2 -debug and
382 * management clients, 3 - COS0 client, 4 - COS client)(HIGHEST)
383 * 3bits client num.
384 * PRI4 | PRI3 | PRI2 | PRI1 | PRI0
385 * dbg0-010 dbg1-001 cos1-100 cos0-011 MCP-000
386 * dbg0-010 dbg1-001 cos0-011 cos1-100 MCP-000
387 */
388 val = (0 == strict_cos) ? 0x2318 : 0x22E0;
389 REG_WR(bp, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT, val);
390
391 return 0;
392}
393/******************************************************************/
394/* ETS section */
395/******************************************************************/
396
397static void bnx2x_bmac2_get_pfc_stat(struct link_params *params,
398 u32 pfc_frames_sent[2],
399 u32 pfc_frames_received[2])
400{
401 /* Read pfc statistic */
402 struct bnx2x *bp = params->bp;
403 u32 bmac_addr = params->port ? NIG_REG_INGRESS_BMAC1_MEM :
404 NIG_REG_INGRESS_BMAC0_MEM;
405
406 DP(NETIF_MSG_LINK, "pfc statistic read from BMAC\n");
407
408 REG_RD_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_TX_STAT_GTPP,
409 pfc_frames_sent, 2);
410
411 REG_RD_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_RX_STAT_GRPP,
412 pfc_frames_received, 2);
413
414}
415static void bnx2x_emac_get_pfc_stat(struct link_params *params,
416 u32 pfc_frames_sent[2],
417 u32 pfc_frames_received[2])
418{
419 /* Read pfc statistic */
420 struct bnx2x *bp = params->bp;
421 u32 emac_base = params->port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
422 u32 val_xon = 0;
423 u32 val_xoff = 0;
424
425 DP(NETIF_MSG_LINK, "pfc statistic read from EMAC\n");
426
427 /* PFC received frames */
428 val_xoff = REG_RD(bp, emac_base +
429 EMAC_REG_RX_PFC_STATS_XOFF_RCVD);
430 val_xoff &= EMAC_REG_RX_PFC_STATS_XOFF_RCVD_COUNT;
431 val_xon = REG_RD(bp, emac_base + EMAC_REG_RX_PFC_STATS_XON_RCVD);
432 val_xon &= EMAC_REG_RX_PFC_STATS_XON_RCVD_COUNT;
433
434 pfc_frames_received[0] = val_xon + val_xoff;
435
436 /* PFC received sent */
437 val_xoff = REG_RD(bp, emac_base +
438 EMAC_REG_RX_PFC_STATS_XOFF_SENT);
439 val_xoff &= EMAC_REG_RX_PFC_STATS_XOFF_SENT_COUNT;
440 val_xon = REG_RD(bp, emac_base + EMAC_REG_RX_PFC_STATS_XON_SENT);
441 val_xon &= EMAC_REG_RX_PFC_STATS_XON_SENT_COUNT;
442
443 pfc_frames_sent[0] = val_xon + val_xoff;
444}
445
446void bnx2x_pfc_statistic(struct link_params *params, struct link_vars *vars,
447 u32 pfc_frames_sent[2],
448 u32 pfc_frames_received[2])
449{
450 /* Read pfc statistic */
451 struct bnx2x *bp = params->bp;
452 u32 val = 0;
453 DP(NETIF_MSG_LINK, "pfc statistic\n");
454
455 if (!vars->link_up)
456 return;
457
458 val = REG_RD(bp, MISC_REG_RESET_REG_2);
459 if ((val & (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << params->port))
460 == 0) {
461 DP(NETIF_MSG_LINK, "About to read stats from EMAC\n");
462 bnx2x_emac_get_pfc_stat(params, pfc_frames_sent,
463 pfc_frames_received);
464 } else {
465 DP(NETIF_MSG_LINK, "About to read stats from BMAC\n");
466 bnx2x_bmac2_get_pfc_stat(params, pfc_frames_sent,
467 pfc_frames_received);
468 }
469}
470/******************************************************************/
471/* MAC/PBF section */
472/******************************************************************/
Yaniv Rosnerea4e0402008-06-23 20:27:26 -0700473static void bnx2x_emac_init(struct link_params *params,
474 struct link_vars *vars)
475{
476 /* reset and unreset the emac core */
477 struct bnx2x *bp = params->bp;
478 u8 port = params->port;
479 u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
480 u32 val;
481 u16 timeout;
482
483 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
484 (MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE << port));
485 udelay(5);
486 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
487 (MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE << port));
488
489 /* init emac - use read-modify-write */
490 /* self clear reset */
491 val = REG_RD(bp, emac_base + EMAC_REG_EMAC_MODE);
Eilon Greenstein3196a882008-08-13 15:58:49 -0700492 EMAC_WR(bp, EMAC_REG_EMAC_MODE, (val | EMAC_MODE_RESET));
Yaniv Rosnerea4e0402008-06-23 20:27:26 -0700493
494 timeout = 200;
Eilon Greenstein3196a882008-08-13 15:58:49 -0700495 do {
Yaniv Rosnerea4e0402008-06-23 20:27:26 -0700496 val = REG_RD(bp, emac_base + EMAC_REG_EMAC_MODE);
497 DP(NETIF_MSG_LINK, "EMAC reset reg is %u\n", val);
498 if (!timeout) {
499 DP(NETIF_MSG_LINK, "EMAC timeout!\n");
500 return;
501 }
502 timeout--;
Eilon Greenstein3196a882008-08-13 15:58:49 -0700503 } while (val & EMAC_MODE_RESET);
Yaniv Rosnerea4e0402008-06-23 20:27:26 -0700504
505 /* Set mac address */
506 val = ((params->mac_addr[0] << 8) |
507 params->mac_addr[1]);
Eilon Greenstein3196a882008-08-13 15:58:49 -0700508 EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH, val);
Yaniv Rosnerea4e0402008-06-23 20:27:26 -0700509
510 val = ((params->mac_addr[2] << 24) |
511 (params->mac_addr[3] << 16) |
512 (params->mac_addr[4] << 8) |
513 params->mac_addr[5]);
Eilon Greenstein3196a882008-08-13 15:58:49 -0700514 EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH + 4, val);
Yaniv Rosnerea4e0402008-06-23 20:27:26 -0700515}
516
517static u8 bnx2x_emac_enable(struct link_params *params,
518 struct link_vars *vars, u8 lb)
519{
520 struct bnx2x *bp = params->bp;
521 u8 port = params->port;
522 u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
523 u32 val;
524
525 DP(NETIF_MSG_LINK, "enabling EMAC\n");
526
527 /* enable emac and not bmac */
528 REG_WR(bp, NIG_REG_EGRESS_EMAC0_PORT + port*4, 1);
529
530 /* for paladium */
531 if (CHIP_REV_IS_EMUL(bp)) {
532 /* Use lane 1 (of lanes 0-3) */
533 REG_WR(bp, NIG_REG_XGXS_LANE_SEL_P0 + port*4, 1);
534 REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL +
535 port*4, 1);
536 }
537 /* for fpga */
538 else
539
540 if (CHIP_REV_IS_FPGA(bp)) {
541 /* Use lane 1 (of lanes 0-3) */
542 DP(NETIF_MSG_LINK, "bnx2x_emac_enable: Setting FPGA\n");
543
544 REG_WR(bp, NIG_REG_XGXS_LANE_SEL_P0 + port*4, 1);
545 REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4,
546 0);
547 } else
548 /* ASIC */
549 if (vars->phy_flags & PHY_XGXS_FLAG) {
550 u32 ser_lane = ((params->lane_config &
551 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >>
552 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT);
553
554 DP(NETIF_MSG_LINK, "XGXS\n");
555 /* select the master lanes (out of 0-3) */
556 REG_WR(bp, NIG_REG_XGXS_LANE_SEL_P0 +
557 port*4, ser_lane);
558 /* select XGXS */
559 REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL +
560 port*4, 1);
561
562 } else { /* SerDes */
563 DP(NETIF_MSG_LINK, "SerDes\n");
564 /* select SerDes */
565 REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL +
566 port*4, 0);
567 }
568
Eilon Greenstein811a2f22009-02-12 08:37:04 +0000569 bnx2x_bits_en(bp, emac_base + EMAC_REG_EMAC_RX_MODE,
570 EMAC_RX_MODE_RESET);
571 bnx2x_bits_en(bp, emac_base + EMAC_REG_EMAC_TX_MODE,
572 EMAC_TX_MODE_RESET);
Yaniv Rosnerea4e0402008-06-23 20:27:26 -0700573
574 if (CHIP_REV_IS_SLOW(bp)) {
575 /* config GMII mode */
576 val = REG_RD(bp, emac_base + EMAC_REG_EMAC_MODE);
Eilon Greenstein3196a882008-08-13 15:58:49 -0700577 EMAC_WR(bp, EMAC_REG_EMAC_MODE,
Yaniv Rosnerea4e0402008-06-23 20:27:26 -0700578 (val | EMAC_MODE_PORT_GMII));
579 } else { /* ASIC */
580 /* pause enable/disable */
581 bnx2x_bits_dis(bp, emac_base + EMAC_REG_EMAC_RX_MODE,
582 EMAC_RX_MODE_FLOW_EN);
Yaniv Rosnerea4e0402008-06-23 20:27:26 -0700583
584 bnx2x_bits_dis(bp, emac_base + EMAC_REG_EMAC_TX_MODE,
Vladislav Zolotarovbcab15c2010-12-13 05:44:25 +0000585 (EMAC_TX_MODE_EXT_PAUSE_EN |
586 EMAC_TX_MODE_FLOW_EN));
587 if (!(params->feature_config_flags &
588 FEATURE_CONFIG_PFC_ENABLED)) {
589 if (vars->flow_ctrl & BNX2X_FLOW_CTRL_RX)
590 bnx2x_bits_en(bp, emac_base +
591 EMAC_REG_EMAC_RX_MODE,
592 EMAC_RX_MODE_FLOW_EN);
593
594 if (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX)
595 bnx2x_bits_en(bp, emac_base +
596 EMAC_REG_EMAC_TX_MODE,
597 (EMAC_TX_MODE_EXT_PAUSE_EN |
598 EMAC_TX_MODE_FLOW_EN));
599 } else
600 bnx2x_bits_en(bp, emac_base + EMAC_REG_EMAC_TX_MODE,
601 EMAC_TX_MODE_FLOW_EN);
Yaniv Rosnerea4e0402008-06-23 20:27:26 -0700602 }
603
604 /* KEEP_VLAN_TAG, promiscuous */
605 val = REG_RD(bp, emac_base + EMAC_REG_EMAC_RX_MODE);
606 val |= EMAC_RX_MODE_KEEP_VLAN_TAG | EMAC_RX_MODE_PROMISCUOUS;
Vladislav Zolotarovbcab15c2010-12-13 05:44:25 +0000607
608 /**
609 * Setting this bit causes MAC control frames (except for pause
610 * frames) to be passed on for processing. This setting has no
611 * affect on the operation of the pause frames. This bit effects
612 * all packets regardless of RX Parser packet sorting logic.
613 * Turn the PFC off to make sure we are in Xon state before
614 * enabling it.
615 */
616 EMAC_WR(bp, EMAC_REG_RX_PFC_MODE, 0);
617 if (params->feature_config_flags & FEATURE_CONFIG_PFC_ENABLED) {
618 DP(NETIF_MSG_LINK, "PFC is enabled\n");
619 /* Enable PFC again */
620 EMAC_WR(bp, EMAC_REG_RX_PFC_MODE,
621 EMAC_REG_RX_PFC_MODE_RX_EN |
622 EMAC_REG_RX_PFC_MODE_TX_EN |
623 EMAC_REG_RX_PFC_MODE_PRIORITIES);
624
625 EMAC_WR(bp, EMAC_REG_RX_PFC_PARAM,
626 ((0x0101 <<
627 EMAC_REG_RX_PFC_PARAM_OPCODE_BITSHIFT) |
628 (0x00ff <<
629 EMAC_REG_RX_PFC_PARAM_PRIORITY_EN_BITSHIFT)));
630 val |= EMAC_RX_MODE_KEEP_MAC_CONTROL;
631 }
Eilon Greenstein3196a882008-08-13 15:58:49 -0700632 EMAC_WR(bp, EMAC_REG_EMAC_RX_MODE, val);
Yaniv Rosnerea4e0402008-06-23 20:27:26 -0700633
634 /* Set Loopback */
635 val = REG_RD(bp, emac_base + EMAC_REG_EMAC_MODE);
636 if (lb)
637 val |= 0x810;
638 else
639 val &= ~0x810;
Eilon Greenstein3196a882008-08-13 15:58:49 -0700640 EMAC_WR(bp, EMAC_REG_EMAC_MODE, val);
Yaniv Rosnerea4e0402008-06-23 20:27:26 -0700641
Eilon Greenstein6c55c3cd2009-01-14 06:44:13 +0000642 /* enable emac */
643 REG_WR(bp, NIG_REG_NIG_EMAC0_EN + port*4, 1);
644
Yaniv Rosnerea4e0402008-06-23 20:27:26 -0700645 /* enable emac for jumbo packets */
Eilon Greenstein3196a882008-08-13 15:58:49 -0700646 EMAC_WR(bp, EMAC_REG_EMAC_RX_MTU_SIZE,
Yaniv Rosnerea4e0402008-06-23 20:27:26 -0700647 (EMAC_RX_MTU_SIZE_JUMBO_ENA |
648 (ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD)));
649
650 /* strip CRC */
651 REG_WR(bp, NIG_REG_NIG_INGRESS_EMAC0_NO_CRC + port*4, 0x1);
652
653 /* disable the NIG in/out to the bmac */
654 REG_WR(bp, NIG_REG_BMAC0_IN_EN + port*4, 0x0);
655 REG_WR(bp, NIG_REG_BMAC0_PAUSE_OUT_EN + port*4, 0x0);
656 REG_WR(bp, NIG_REG_BMAC0_OUT_EN + port*4, 0x0);
657
658 /* enable the NIG in/out to the emac */
659 REG_WR(bp, NIG_REG_EMAC0_IN_EN + port*4, 0x1);
660 val = 0;
Vladislav Zolotarovbcab15c2010-12-13 05:44:25 +0000661 if ((params->feature_config_flags &
662 FEATURE_CONFIG_PFC_ENABLED) ||
663 (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX))
Yaniv Rosnerea4e0402008-06-23 20:27:26 -0700664 val = 1;
665
666 REG_WR(bp, NIG_REG_EMAC0_PAUSE_OUT_EN + port*4, val);
667 REG_WR(bp, NIG_REG_EGRESS_EMAC0_OUT_EN + port*4, 0x1);
668
669 if (CHIP_REV_IS_EMUL(bp)) {
670 /* take the BigMac out of reset */
671 REG_WR(bp,
672 GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
673 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port));
674
675 /* enable access for bmac registers */
676 REG_WR(bp, NIG_REG_BMAC0_REGS_OUT_EN + port*4, 0x1);
Eilon Greenstein6f654972009-08-12 08:23:51 +0000677 } else
678 REG_WR(bp, NIG_REG_BMAC0_REGS_OUT_EN + port*4, 0x0);
Yaniv Rosnerea4e0402008-06-23 20:27:26 -0700679
680 vars->mac_type = MAC_TYPE_EMAC;
681 return 0;
682}
683
Vladislav Zolotarovbcab15c2010-12-13 05:44:25 +0000684static void bnx2x_update_pfc_bmac1(struct link_params *params,
685 struct link_vars *vars)
686{
687 u32 wb_data[2];
688 struct bnx2x *bp = params->bp;
689 u32 bmac_addr = params->port ? NIG_REG_INGRESS_BMAC1_MEM :
690 NIG_REG_INGRESS_BMAC0_MEM;
691
692 u32 val = 0x14;
693 if ((!(params->feature_config_flags &
694 FEATURE_CONFIG_PFC_ENABLED)) &&
695 (vars->flow_ctrl & BNX2X_FLOW_CTRL_RX))
696 /* Enable BigMAC to react on received Pause packets */
697 val |= (1<<5);
698 wb_data[0] = val;
699 wb_data[1] = 0;
700 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_RX_CONTROL, wb_data, 2);
701
702 /* tx control */
703 val = 0xc0;
704 if (!(params->feature_config_flags &
705 FEATURE_CONFIG_PFC_ENABLED) &&
706 (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX))
707 val |= 0x800000;
708 wb_data[0] = val;
709 wb_data[1] = 0;
710 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_TX_CONTROL, wb_data, 2);
711}
712
713static void bnx2x_update_pfc_bmac2(struct link_params *params,
714 struct link_vars *vars,
715 u8 is_lb)
Dmitry Kravkovf2e08992010-10-06 03:28:26 +0000716{
717 /*
718 * Set rx control: Strip CRC and enable BigMAC to relay
719 * control packets to the system as well
720 */
721 u32 wb_data[2];
722 struct bnx2x *bp = params->bp;
723 u32 bmac_addr = params->port ? NIG_REG_INGRESS_BMAC1_MEM :
724 NIG_REG_INGRESS_BMAC0_MEM;
725 u32 val = 0x14;
726
Vladislav Zolotarovbcab15c2010-12-13 05:44:25 +0000727 if ((!(params->feature_config_flags &
728 FEATURE_CONFIG_PFC_ENABLED)) &&
729 (vars->flow_ctrl & BNX2X_FLOW_CTRL_RX))
Dmitry Kravkovf2e08992010-10-06 03:28:26 +0000730 /* Enable BigMAC to react on received Pause packets */
731 val |= (1<<5);
732 wb_data[0] = val;
733 wb_data[1] = 0;
734 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_RX_CONTROL,
735 wb_data, 2);
736 udelay(30);
737
738 /* Tx control */
739 val = 0xc0;
Vladislav Zolotarovbcab15c2010-12-13 05:44:25 +0000740 if (!(params->feature_config_flags &
741 FEATURE_CONFIG_PFC_ENABLED) &&
742 (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX))
Dmitry Kravkovf2e08992010-10-06 03:28:26 +0000743 val |= 0x800000;
744 wb_data[0] = val;
745 wb_data[1] = 0;
Vladislav Zolotarovbcab15c2010-12-13 05:44:25 +0000746 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_TX_CONTROL, wb_data, 2);
Dmitry Kravkovf2e08992010-10-06 03:28:26 +0000747
Vladislav Zolotarovbcab15c2010-12-13 05:44:25 +0000748 if (params->feature_config_flags & FEATURE_CONFIG_PFC_ENABLED) {
749 DP(NETIF_MSG_LINK, "PFC is enabled\n");
750 /* Enable PFC RX & TX & STATS and set 8 COS */
751 wb_data[0] = 0x0;
752 wb_data[0] |= (1<<0); /* RX */
753 wb_data[0] |= (1<<1); /* TX */
754 wb_data[0] |= (1<<2); /* Force initial Xon */
755 wb_data[0] |= (1<<3); /* 8 cos */
756 wb_data[0] |= (1<<5); /* STATS */
757 wb_data[1] = 0;
758 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_PFC_CONTROL,
759 wb_data, 2);
760 /* Clear the force Xon */
761 wb_data[0] &= ~(1<<2);
762 } else {
763 DP(NETIF_MSG_LINK, "PFC is disabled\n");
764 /* disable PFC RX & TX & STATS and set 8 COS */
765 wb_data[0] = 0x8;
766 wb_data[1] = 0;
767 }
768
769 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_PFC_CONTROL, wb_data, 2);
770
771 /**
772 * Set Time (based unit is 512 bit time) between automatic
773 * re-sending of PP packets amd enable automatic re-send of
774 * Per-Priroity Packet as long as pp_gen is asserted and
775 * pp_disable is low.
776 */
Dmitry Kravkovf2e08992010-10-06 03:28:26 +0000777 val = 0x8000;
Vladislav Zolotarovbcab15c2010-12-13 05:44:25 +0000778 if (params->feature_config_flags & FEATURE_CONFIG_PFC_ENABLED)
779 val |= (1<<16); /* enable automatic re-send */
780
Dmitry Kravkovf2e08992010-10-06 03:28:26 +0000781 wb_data[0] = val;
782 wb_data[1] = 0;
783 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_TX_PAUSE_CONTROL,
784 wb_data, 2);
785
786 /* mac control */
787 val = 0x3; /* Enable RX and TX */
788 if (is_lb) {
789 val |= 0x4; /* Local loopback */
790 DP(NETIF_MSG_LINK, "enable bmac loopback\n");
791 }
Vladislav Zolotarovbcab15c2010-12-13 05:44:25 +0000792 /* When PFC enabled, Pass pause frames towards the NIG. */
793 if (params->feature_config_flags & FEATURE_CONFIG_PFC_ENABLED)
794 val |= ((1<<6)|(1<<5));
Dmitry Kravkovf2e08992010-10-06 03:28:26 +0000795
796 wb_data[0] = val;
797 wb_data[1] = 0;
798 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_BMAC_CONTROL,
799 wb_data, 2);
800}
Yaniv Rosnerea4e0402008-06-23 20:27:26 -0700801
Vladislav Zolotarovbcab15c2010-12-13 05:44:25 +0000802static void bnx2x_update_pfc_brb(struct link_params *params,
803 struct link_vars *vars,
804 struct bnx2x_nig_brb_pfc_port_params *pfc_params)
805{
806 struct bnx2x *bp = params->bp;
807 int set_pfc = params->feature_config_flags &
808 FEATURE_CONFIG_PFC_ENABLED;
809
810 /* default - pause configuration */
811 u32 pause_xoff_th = PFC_BRB_MAC_PAUSE_XOFF_THRESHOLD_PAUSEABLE;
812 u32 pause_xon_th = PFC_BRB_MAC_PAUSE_XON_THRESHOLD_PAUSEABLE;
813 u32 full_xoff_th = PFC_BRB_MAC_FULL_XOFF_THRESHOLD_PAUSEABLE;
814 u32 full_xon_th = PFC_BRB_MAC_FULL_XON_THRESHOLD_PAUSEABLE;
815
816 if (set_pfc && pfc_params)
817 /* First COS */
818 if (!pfc_params->cos0_pauseable) {
819 pause_xoff_th =
820 PFC_BRB_MAC_PAUSE_XOFF_THRESHOLD_NON_PAUSEABLE;
821 pause_xon_th =
822 PFC_BRB_MAC_PAUSE_XON_THRESHOLD_NON_PAUSEABLE;
823 full_xoff_th =
824 PFC_BRB_MAC_FULL_XOFF_THRESHOLD_NON_PAUSEABLE;
825 full_xon_th =
826 PFC_BRB_MAC_FULL_XON_THRESHOLD_NON_PAUSEABLE;
827 }
828 /* The number of free blocks below which the pause signal to class 0
829 of MAC #n is asserted. n=0,1 */
830 REG_WR(bp, BRB1_REG_PAUSE_0_XOFF_THRESHOLD_0 , pause_xoff_th);
831 /* The number of free blocks above which the pause signal to class 0
832 of MAC #n is de-asserted. n=0,1 */
833 REG_WR(bp, BRB1_REG_PAUSE_0_XON_THRESHOLD_0 , pause_xon_th);
834 /* The number of free blocks below which the full signal to class 0
835 of MAC #n is asserted. n=0,1 */
836 REG_WR(bp, BRB1_REG_FULL_0_XOFF_THRESHOLD_0 , full_xoff_th);
837 /* The number of free blocks above which the full signal to class 0
838 of MAC #n is de-asserted. n=0,1 */
839 REG_WR(bp, BRB1_REG_FULL_0_XON_THRESHOLD_0 , full_xon_th);
840
841 if (set_pfc && pfc_params) {
842 /* Second COS */
843 if (pfc_params->cos1_pauseable) {
844 pause_xoff_th =
845 PFC_BRB_MAC_PAUSE_XOFF_THRESHOLD_PAUSEABLE;
846 pause_xon_th =
847 PFC_BRB_MAC_PAUSE_XON_THRESHOLD_PAUSEABLE;
848 full_xoff_th =
849 PFC_BRB_MAC_FULL_XOFF_THRESHOLD_PAUSEABLE;
850 full_xon_th =
851 PFC_BRB_MAC_FULL_XON_THRESHOLD_PAUSEABLE;
852 } else {
853 pause_xoff_th =
854 PFC_BRB_MAC_PAUSE_XOFF_THRESHOLD_NON_PAUSEABLE;
855 pause_xon_th =
856 PFC_BRB_MAC_PAUSE_XON_THRESHOLD_NON_PAUSEABLE;
857 full_xoff_th =
858 PFC_BRB_MAC_FULL_XOFF_THRESHOLD_NON_PAUSEABLE;
859 full_xon_th =
860 PFC_BRB_MAC_FULL_XON_THRESHOLD_NON_PAUSEABLE;
861 }
862 /**
863 * The number of free blocks below which the pause signal to
864 * class 1 of MAC #n is asserted. n=0,1
865 **/
866 REG_WR(bp, BRB1_REG_PAUSE_1_XOFF_THRESHOLD_0, pause_xoff_th);
867 /**
868 * The number of free blocks above which the pause signal to
869 * class 1 of MAC #n is de-asserted. n=0,1
870 **/
871 REG_WR(bp, BRB1_REG_PAUSE_1_XON_THRESHOLD_0, pause_xon_th);
872 /**
873 * The number of free blocks below which the full signal to
874 * class 1 of MAC #n is asserted. n=0,1
875 **/
876 REG_WR(bp, BRB1_REG_FULL_1_XOFF_THRESHOLD_0, full_xoff_th);
877 /**
878 * The number of free blocks above which the full signal to
879 * class 1 of MAC #n is de-asserted. n=0,1
880 **/
881 REG_WR(bp, BRB1_REG_FULL_1_XON_THRESHOLD_0, full_xon_th);
882 }
883}
884
885static void bnx2x_update_pfc_nig(struct link_params *params,
886 struct link_vars *vars,
887 struct bnx2x_nig_brb_pfc_port_params *nig_params)
888{
889 u32 xcm_mask = 0, ppp_enable = 0, pause_enable = 0, llfc_out_en = 0;
890 u32 llfc_enable = 0, xcm0_out_en = 0, p0_hwpfc_enable = 0;
891 u32 pkt_priority_to_cos = 0;
892 u32 val;
893 struct bnx2x *bp = params->bp;
894 int port = params->port;
895 int set_pfc = params->feature_config_flags &
896 FEATURE_CONFIG_PFC_ENABLED;
897 DP(NETIF_MSG_LINK, "updating pfc nig parameters\n");
898
899 /**
900 * When NIG_LLH0_XCM_MASK_REG_LLHX_XCM_MASK_BCN bit is set
901 * MAC control frames (that are not pause packets)
902 * will be forwarded to the XCM.
903 */
904 xcm_mask = REG_RD(bp,
905 port ? NIG_REG_LLH1_XCM_MASK :
906 NIG_REG_LLH0_XCM_MASK);
907 /**
908 * nig params will override non PFC params, since it's possible to
909 * do transition from PFC to SAFC
910 */
911 if (set_pfc) {
912 pause_enable = 0;
913 llfc_out_en = 0;
914 llfc_enable = 0;
915 ppp_enable = 1;
916 xcm_mask &= ~(port ? NIG_LLH1_XCM_MASK_REG_LLH1_XCM_MASK_BCN :
917 NIG_LLH0_XCM_MASK_REG_LLH0_XCM_MASK_BCN);
918 xcm0_out_en = 0;
919 p0_hwpfc_enable = 1;
920 } else {
921 if (nig_params) {
922 llfc_out_en = nig_params->llfc_out_en;
923 llfc_enable = nig_params->llfc_enable;
924 pause_enable = nig_params->pause_enable;
925 } else /*defaul non PFC mode - PAUSE */
926 pause_enable = 1;
927
928 xcm_mask |= (port ? NIG_LLH1_XCM_MASK_REG_LLH1_XCM_MASK_BCN :
929 NIG_LLH0_XCM_MASK_REG_LLH0_XCM_MASK_BCN);
930 xcm0_out_en = 1;
931 }
932
933 REG_WR(bp, port ? NIG_REG_LLFC_OUT_EN_1 :
934 NIG_REG_LLFC_OUT_EN_0, llfc_out_en);
935 REG_WR(bp, port ? NIG_REG_LLFC_ENABLE_1 :
936 NIG_REG_LLFC_ENABLE_0, llfc_enable);
937 REG_WR(bp, port ? NIG_REG_PAUSE_ENABLE_1 :
938 NIG_REG_PAUSE_ENABLE_0, pause_enable);
939
940 REG_WR(bp, port ? NIG_REG_PPP_ENABLE_1 :
941 NIG_REG_PPP_ENABLE_0, ppp_enable);
942
943 REG_WR(bp, port ? NIG_REG_LLH1_XCM_MASK :
944 NIG_REG_LLH0_XCM_MASK, xcm_mask);
945
946 REG_WR(bp, NIG_REG_LLFC_EGRESS_SRC_ENABLE_0, 0x7);
947
948 /* output enable for RX_XCM # IF */
949 REG_WR(bp, NIG_REG_XCM0_OUT_EN, xcm0_out_en);
950
951 /* HW PFC TX enable */
952 REG_WR(bp, NIG_REG_P0_HWPFC_ENABLE, p0_hwpfc_enable);
953
954 /* 0x2 = BMAC, 0x1= EMAC */
955 switch (vars->mac_type) {
956 case MAC_TYPE_EMAC:
957 val = 1;
958 break;
959 case MAC_TYPE_BMAC:
960 val = 0;
961 break;
962 default:
963 val = 0;
964 break;
965 }
966 REG_WR(bp, NIG_REG_EGRESS_EMAC0_PORT, val);
967
968 if (nig_params) {
969 pkt_priority_to_cos = nig_params->pkt_priority_to_cos;
970
971 REG_WR(bp, port ? NIG_REG_P1_RX_COS0_PRIORITY_MASK :
972 NIG_REG_P0_RX_COS0_PRIORITY_MASK,
973 nig_params->rx_cos0_priority_mask);
974
975 REG_WR(bp, port ? NIG_REG_P1_RX_COS1_PRIORITY_MASK :
976 NIG_REG_P0_RX_COS1_PRIORITY_MASK,
977 nig_params->rx_cos1_priority_mask);
978
979 REG_WR(bp, port ? NIG_REG_LLFC_HIGH_PRIORITY_CLASSES_1 :
980 NIG_REG_LLFC_HIGH_PRIORITY_CLASSES_0,
981 nig_params->llfc_high_priority_classes);
982
983 REG_WR(bp, port ? NIG_REG_LLFC_LOW_PRIORITY_CLASSES_1 :
984 NIG_REG_LLFC_LOW_PRIORITY_CLASSES_0,
985 nig_params->llfc_low_priority_classes);
986 }
987 REG_WR(bp, port ? NIG_REG_P1_PKT_PRIORITY_TO_COS :
988 NIG_REG_P0_PKT_PRIORITY_TO_COS,
989 pkt_priority_to_cos);
990}
991
992
993void bnx2x_update_pfc(struct link_params *params,
994 struct link_vars *vars,
995 struct bnx2x_nig_brb_pfc_port_params *pfc_params)
996{
997 /**
998 * The PFC and pause are orthogonal to one another, meaning when
999 * PFC is enabled, the pause are disabled, and when PFC is
1000 * disabled, pause are set according to the pause result.
1001 */
1002 u32 val;
1003 struct bnx2x *bp = params->bp;
1004
1005 /* update NIG params */
1006 bnx2x_update_pfc_nig(params, vars, pfc_params);
1007
1008 /* update BRB params */
1009 bnx2x_update_pfc_brb(params, vars, pfc_params);
1010
1011 if (!vars->link_up)
1012 return;
1013
1014 val = REG_RD(bp, MISC_REG_RESET_REG_2);
1015 if ((val & (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << params->port))
1016 == 0) {
1017 DP(NETIF_MSG_LINK, "About to update PFC in EMAC\n");
1018 bnx2x_emac_enable(params, vars, 0);
1019 return;
1020 }
1021
1022 DP(NETIF_MSG_LINK, "About to update PFC in BMAC\n");
1023 if (CHIP_IS_E2(bp))
1024 bnx2x_update_pfc_bmac2(params, vars, 0);
1025 else
1026 bnx2x_update_pfc_bmac1(params, vars);
1027
1028 val = 0;
1029 if ((params->feature_config_flags &
1030 FEATURE_CONFIG_PFC_ENABLED) ||
1031 (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX))
1032 val = 1;
1033 REG_WR(bp, NIG_REG_BMAC0_PAUSE_OUT_EN + params->port*4, val);
1034}
Yaniv Rosnerea4e0402008-06-23 20:27:26 -07001035
Dmitry Kravkovf2e08992010-10-06 03:28:26 +00001036static u8 bnx2x_bmac1_enable(struct link_params *params,
1037 struct link_vars *vars,
Yaniv Rosnerea4e0402008-06-23 20:27:26 -07001038 u8 is_lb)
1039{
1040 struct bnx2x *bp = params->bp;
1041 u8 port = params->port;
1042 u32 bmac_addr = port ? NIG_REG_INGRESS_BMAC1_MEM :
1043 NIG_REG_INGRESS_BMAC0_MEM;
1044 u32 wb_data[2];
1045 u32 val;
1046
Dmitry Kravkovf2e08992010-10-06 03:28:26 +00001047 DP(NETIF_MSG_LINK, "Enabling BigMAC1\n");
Yaniv Rosnerea4e0402008-06-23 20:27:26 -07001048
1049 /* XGXS control */
1050 wb_data[0] = 0x3c;
1051 wb_data[1] = 0;
1052 REG_WR_DMAE(bp, bmac_addr +
1053 BIGMAC_REGISTER_BMAC_XGXS_CONTROL,
1054 wb_data, 2);
1055
1056 /* tx MAC SA */
1057 wb_data[0] = ((params->mac_addr[2] << 24) |
1058 (params->mac_addr[3] << 16) |
1059 (params->mac_addr[4] << 8) |
1060 params->mac_addr[5]);
1061 wb_data[1] = ((params->mac_addr[0] << 8) |
1062 params->mac_addr[1]);
1063 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_TX_SOURCE_ADDR,
1064 wb_data, 2);
1065
Yaniv Rosnerea4e0402008-06-23 20:27:26 -07001066 /* mac control */
1067 val = 0x3;
1068 if (is_lb) {
1069 val |= 0x4;
1070 DP(NETIF_MSG_LINK, "enable bmac loopback\n");
1071 }
1072 wb_data[0] = val;
1073 wb_data[1] = 0;
1074 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_BMAC_CONTROL,
1075 wb_data, 2);
1076
Yaniv Rosnerea4e0402008-06-23 20:27:26 -07001077 /* set rx mtu */
1078 wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD;
1079 wb_data[1] = 0;
1080 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_RX_MAX_SIZE,
1081 wb_data, 2);
1082
Vladislav Zolotarovbcab15c2010-12-13 05:44:25 +00001083 bnx2x_update_pfc_bmac1(params, vars);
Yaniv Rosnerea4e0402008-06-23 20:27:26 -07001084
1085 /* set tx mtu */
1086 wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD;
1087 wb_data[1] = 0;
1088 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_TX_MAX_SIZE,
1089 wb_data, 2);
1090
1091 /* set cnt max size */
1092 wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD;
1093 wb_data[1] = 0;
1094 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_CNT_MAX_SIZE,
1095 wb_data, 2);
1096
1097 /* configure safc */
1098 wb_data[0] = 0x1000200;
1099 wb_data[1] = 0;
1100 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_RX_LLFC_MSG_FLDS,
1101 wb_data, 2);
1102 /* fix for emulation */
1103 if (CHIP_REV_IS_EMUL(bp)) {
1104 wb_data[0] = 0xf000;
1105 wb_data[1] = 0;
1106 REG_WR_DMAE(bp,
1107 bmac_addr + BIGMAC_REGISTER_TX_PAUSE_THRESHOLD,
1108 wb_data, 2);
1109 }
1110
Dmitry Kravkovf2e08992010-10-06 03:28:26 +00001111
1112 return 0;
1113}
1114
1115static u8 bnx2x_bmac2_enable(struct link_params *params,
1116 struct link_vars *vars,
1117 u8 is_lb)
1118{
1119 struct bnx2x *bp = params->bp;
1120 u8 port = params->port;
1121 u32 bmac_addr = port ? NIG_REG_INGRESS_BMAC1_MEM :
1122 NIG_REG_INGRESS_BMAC0_MEM;
1123 u32 wb_data[2];
1124
1125 DP(NETIF_MSG_LINK, "Enabling BigMAC2\n");
1126
1127 wb_data[0] = 0;
1128 wb_data[1] = 0;
1129 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_BMAC_CONTROL,
1130 wb_data, 2);
1131 udelay(30);
1132
1133 /* XGXS control: Reset phy HW, MDIO registers, PHY PLL and BMAC */
1134 wb_data[0] = 0x3c;
1135 wb_data[1] = 0;
1136 REG_WR_DMAE(bp, bmac_addr +
1137 BIGMAC2_REGISTER_BMAC_XGXS_CONTROL,
1138 wb_data, 2);
1139
1140 udelay(30);
1141
1142 /* tx MAC SA */
1143 wb_data[0] = ((params->mac_addr[2] << 24) |
1144 (params->mac_addr[3] << 16) |
1145 (params->mac_addr[4] << 8) |
1146 params->mac_addr[5]);
1147 wb_data[1] = ((params->mac_addr[0] << 8) |
1148 params->mac_addr[1]);
1149 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_TX_SOURCE_ADDR,
1150 wb_data, 2);
1151
1152 udelay(30);
1153
1154 /* Configure SAFC */
1155 wb_data[0] = 0x1000200;
1156 wb_data[1] = 0;
1157 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_RX_LLFC_MSG_FLDS,
1158 wb_data, 2);
1159 udelay(30);
1160
1161 /* set rx mtu */
1162 wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD;
1163 wb_data[1] = 0;
1164 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_RX_MAX_SIZE,
1165 wb_data, 2);
1166 udelay(30);
1167
1168 /* set tx mtu */
1169 wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD;
1170 wb_data[1] = 0;
1171 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_TX_MAX_SIZE,
1172 wb_data, 2);
1173 udelay(30);
1174 /* set cnt max size */
1175 wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD - 2;
1176 wb_data[1] = 0;
1177 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_CNT_MAX_SIZE,
1178 wb_data, 2);
1179 udelay(30);
Vladislav Zolotarovbcab15c2010-12-13 05:44:25 +00001180 bnx2x_update_pfc_bmac2(params, vars, is_lb);
Dmitry Kravkovf2e08992010-10-06 03:28:26 +00001181
1182 return 0;
1183}
1184
stephen hemminger8d962862010-10-21 07:50:56 +00001185static u8 bnx2x_bmac_enable(struct link_params *params,
Dmitry Kravkovf2e08992010-10-06 03:28:26 +00001186 struct link_vars *vars,
1187 u8 is_lb)
1188{
1189 u8 rc, port = params->port;
1190 struct bnx2x *bp = params->bp;
1191 u32 val;
1192 /* reset and unreset the BigMac */
1193 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
1194 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port));
Yaniv Rosner1d9c05d2010-11-01 05:32:25 +00001195 msleep(1);
Dmitry Kravkovf2e08992010-10-06 03:28:26 +00001196
1197 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
1198 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port));
1199
1200 /* enable access for bmac registers */
1201 REG_WR(bp, NIG_REG_BMAC0_REGS_OUT_EN + port*4, 0x1);
1202
1203 /* Enable BMAC according to BMAC type*/
1204 if (CHIP_IS_E2(bp))
1205 rc = bnx2x_bmac2_enable(params, vars, is_lb);
1206 else
1207 rc = bnx2x_bmac1_enable(params, vars, is_lb);
Yaniv Rosnerea4e0402008-06-23 20:27:26 -07001208 REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 0x1);
1209 REG_WR(bp, NIG_REG_XGXS_LANE_SEL_P0 + port*4, 0x0);
1210 REG_WR(bp, NIG_REG_EGRESS_EMAC0_PORT + port*4, 0x0);
1211 val = 0;
Vladislav Zolotarovbcab15c2010-12-13 05:44:25 +00001212 if ((params->feature_config_flags &
1213 FEATURE_CONFIG_PFC_ENABLED) ||
1214 (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX))
Yaniv Rosnerea4e0402008-06-23 20:27:26 -07001215 val = 1;
1216 REG_WR(bp, NIG_REG_BMAC0_PAUSE_OUT_EN + port*4, val);
1217 REG_WR(bp, NIG_REG_EGRESS_EMAC0_OUT_EN + port*4, 0x0);
1218 REG_WR(bp, NIG_REG_EMAC0_IN_EN + port*4, 0x0);
1219 REG_WR(bp, NIG_REG_EMAC0_PAUSE_OUT_EN + port*4, 0x0);
1220 REG_WR(bp, NIG_REG_BMAC0_IN_EN + port*4, 0x1);
1221 REG_WR(bp, NIG_REG_BMAC0_OUT_EN + port*4, 0x1);
1222
1223 vars->mac_type = MAC_TYPE_BMAC;
Dmitry Kravkovf2e08992010-10-06 03:28:26 +00001224 return rc;
Yaniv Rosnerea4e0402008-06-23 20:27:26 -07001225}
1226
Yaniv Rosnerea4e0402008-06-23 20:27:26 -07001227
1228static void bnx2x_update_mng(struct link_params *params, u32 link_status)
1229{
1230 struct bnx2x *bp = params->bp;
Eilon Greensteinab6ad5a2009-08-12 08:24:29 +00001231
Yaniv Rosnerea4e0402008-06-23 20:27:26 -07001232 REG_WR(bp, params->shmem_base +
1233 offsetof(struct shmem_region,
1234 port_mb[params->port].link_status),
1235 link_status);
1236}
1237
1238static void bnx2x_bmac_rx_disable(struct bnx2x *bp, u8 port)
1239{
1240 u32 bmac_addr = port ? NIG_REG_INGRESS_BMAC1_MEM :
1241 NIG_REG_INGRESS_BMAC0_MEM;
1242 u32 wb_data[2];
Eilon Greenstein3196a882008-08-13 15:58:49 -07001243 u32 nig_bmac_enable = REG_RD(bp, NIG_REG_BMAC0_REGS_OUT_EN + port*4);
Yaniv Rosnerea4e0402008-06-23 20:27:26 -07001244
1245 /* Only if the bmac is out of reset */
1246 if (REG_RD(bp, MISC_REG_RESET_REG_2) &
1247 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port) &&
1248 nig_bmac_enable) {
1249
Dmitry Kravkovf2e08992010-10-06 03:28:26 +00001250 if (CHIP_IS_E2(bp)) {
1251 /* Clear Rx Enable bit in BMAC_CONTROL register */
1252 REG_RD_DMAE(bp, bmac_addr +
1253 BIGMAC2_REGISTER_BMAC_CONTROL,
1254 wb_data, 2);
1255 wb_data[0] &= ~BMAC_CONTROL_RX_ENABLE;
1256 REG_WR_DMAE(bp, bmac_addr +
1257 BIGMAC2_REGISTER_BMAC_CONTROL,
1258 wb_data, 2);
1259 } else {
1260 /* Clear Rx Enable bit in BMAC_CONTROL register */
1261 REG_RD_DMAE(bp, bmac_addr +
1262 BIGMAC_REGISTER_BMAC_CONTROL,
1263 wb_data, 2);
1264 wb_data[0] &= ~BMAC_CONTROL_RX_ENABLE;
1265 REG_WR_DMAE(bp, bmac_addr +
1266 BIGMAC_REGISTER_BMAC_CONTROL,
1267 wb_data, 2);
1268 }
Yaniv Rosnerea4e0402008-06-23 20:27:26 -07001269 msleep(1);
1270 }
1271}
1272
1273static u8 bnx2x_pbf_update(struct link_params *params, u32 flow_ctrl,
1274 u32 line_speed)
1275{
1276 struct bnx2x *bp = params->bp;
1277 u8 port = params->port;
1278 u32 init_crd, crd;
1279 u32 count = 1000;
Yaniv Rosnerea4e0402008-06-23 20:27:26 -07001280
1281 /* disable port */
1282 REG_WR(bp, PBF_REG_DISABLE_NEW_TASK_PROC_P0 + port*4, 0x1);
1283
1284 /* wait for init credit */
1285 init_crd = REG_RD(bp, PBF_REG_P0_INIT_CRD + port*4);
1286 crd = REG_RD(bp, PBF_REG_P0_CREDIT + port*8);
1287 DP(NETIF_MSG_LINK, "init_crd 0x%x crd 0x%x\n", init_crd, crd);
1288
1289 while ((init_crd != crd) && count) {
1290 msleep(5);
1291
1292 crd = REG_RD(bp, PBF_REG_P0_CREDIT + port*8);
1293 count--;
1294 }
1295 crd = REG_RD(bp, PBF_REG_P0_CREDIT + port*8);
1296 if (init_crd != crd) {
1297 DP(NETIF_MSG_LINK, "BUG! init_crd 0x%x != crd 0x%x\n",
1298 init_crd, crd);
1299 return -EINVAL;
1300 }
1301
David S. Millerc0700f92008-12-16 23:53:20 -08001302 if (flow_ctrl & BNX2X_FLOW_CTRL_RX ||
Yaniv Rosner8c99e7b2008-08-13 15:56:17 -07001303 line_speed == SPEED_10 ||
1304 line_speed == SPEED_100 ||
1305 line_speed == SPEED_1000 ||
1306 line_speed == SPEED_2500) {
1307 REG_WR(bp, PBF_REG_P0_PAUSE_ENABLE + port*4, 1);
Yaniv Rosnerea4e0402008-06-23 20:27:26 -07001308 /* update threshold */
1309 REG_WR(bp, PBF_REG_P0_ARB_THRSH + port*4, 0);
1310 /* update init credit */
Yaniv Rosner8c99e7b2008-08-13 15:56:17 -07001311 init_crd = 778; /* (800-18-4) */
Yaniv Rosnerea4e0402008-06-23 20:27:26 -07001312
1313 } else {
1314 u32 thresh = (ETH_MAX_JUMBO_PACKET_SIZE +
1315 ETH_OVREHEAD)/16;
Yaniv Rosner8c99e7b2008-08-13 15:56:17 -07001316 REG_WR(bp, PBF_REG_P0_PAUSE_ENABLE + port*4, 0);
Yaniv Rosnerea4e0402008-06-23 20:27:26 -07001317 /* update threshold */
1318 REG_WR(bp, PBF_REG_P0_ARB_THRSH + port*4, thresh);
1319 /* update init credit */
1320 switch (line_speed) {
Yaniv Rosnerea4e0402008-06-23 20:27:26 -07001321 case SPEED_10000:
1322 init_crd = thresh + 553 - 22;
1323 break;
1324
1325 case SPEED_12000:
1326 init_crd = thresh + 664 - 22;
1327 break;
1328
1329 case SPEED_13000:
1330 init_crd = thresh + 742 - 22;
1331 break;
1332
1333 case SPEED_16000:
1334 init_crd = thresh + 778 - 22;
1335 break;
1336 default:
1337 DP(NETIF_MSG_LINK, "Invalid line_speed 0x%x\n",
1338 line_speed);
1339 return -EINVAL;
Yaniv Rosnerea4e0402008-06-23 20:27:26 -07001340 }
1341 }
1342 REG_WR(bp, PBF_REG_P0_INIT_CRD + port*4, init_crd);
1343 DP(NETIF_MSG_LINK, "PBF updated to speed %d credit %d\n",
1344 line_speed, init_crd);
1345
1346 /* probe the credit changes */
1347 REG_WR(bp, PBF_REG_INIT_P0 + port*4, 0x1);
1348 msleep(5);
1349 REG_WR(bp, PBF_REG_INIT_P0 + port*4, 0x0);
1350
1351 /* enable port */
1352 REG_WR(bp, PBF_REG_DISABLE_NEW_TASK_PROC_P0 + port*4, 0x0);
1353 return 0;
1354}
1355
Yaniv Rosnerc18aa152010-09-07 11:41:07 +00001356static u32 bnx2x_get_emac_base(struct bnx2x *bp,
1357 u32 mdc_mdio_access, u8 port)
Yaniv Rosnerea4e0402008-06-23 20:27:26 -07001358{
Yaniv Rosnerc18aa152010-09-07 11:41:07 +00001359 u32 emac_base = 0;
1360 switch (mdc_mdio_access) {
1361 case SHARED_HW_CFG_MDC_MDIO_ACCESS1_PHY_TYPE:
1362 break;
1363 case SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC0:
1364 if (REG_RD(bp, NIG_REG_PORT_SWAP))
1365 emac_base = GRCBASE_EMAC1;
1366 else
1367 emac_base = GRCBASE_EMAC0;
1368 break;
1369 case SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC1:
Eilon Greenstein589abe32009-02-12 08:36:55 +00001370 if (REG_RD(bp, NIG_REG_PORT_SWAP))
1371 emac_base = GRCBASE_EMAC0;
1372 else
1373 emac_base = GRCBASE_EMAC1;
Yaniv Rosnerea4e0402008-06-23 20:27:26 -07001374 break;
Yaniv Rosnerc18aa152010-09-07 11:41:07 +00001375 case SHARED_HW_CFG_MDC_MDIO_ACCESS1_BOTH:
1376 emac_base = (port) ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
1377 break;
1378 case SHARED_HW_CFG_MDC_MDIO_ACCESS1_SWAPPED:
Eilon Greenstein6378c022008-08-13 15:59:25 -07001379 emac_base = (port) ? GRCBASE_EMAC0 : GRCBASE_EMAC1;
Yaniv Rosnerea4e0402008-06-23 20:27:26 -07001380 break;
1381 default:
Yaniv Rosnerea4e0402008-06-23 20:27:26 -07001382 break;
1383 }
1384 return emac_base;
1385
1386}
1387
Yaniv Rosnere10bc842010-09-07 11:40:50 +00001388u8 bnx2x_cl45_write(struct bnx2x *bp, struct bnx2x_phy *phy,
1389 u8 devad, u16 reg, u16 val)
Yaniv Rosnerea4e0402008-06-23 20:27:26 -07001390{
1391 u32 tmp, saved_mode;
1392 u8 i, rc = 0;
Yaniv Rosnerea4e0402008-06-23 20:27:26 -07001393
1394 /* set clause 45 mode, slow down the MDIO clock to 2.5MHz
1395 * (a value of 49==0x31) and make sure that the AUTO poll is off
1396 */
Eilon Greenstein589abe32009-02-12 08:36:55 +00001397
Yaniv Rosnere10bc842010-09-07 11:40:50 +00001398 saved_mode = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE);
Yaniv Rosnerea4e0402008-06-23 20:27:26 -07001399 tmp = saved_mode & ~(EMAC_MDIO_MODE_AUTO_POLL |
1400 EMAC_MDIO_MODE_CLOCK_CNT);
1401 tmp |= (EMAC_MDIO_MODE_CLAUSE_45 |
1402 (49 << EMAC_MDIO_MODE_CLOCK_CNT_BITSHIFT));
Yaniv Rosnere10bc842010-09-07 11:40:50 +00001403 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE, tmp);
1404 REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE);
Yaniv Rosnerea4e0402008-06-23 20:27:26 -07001405 udelay(40);
1406
1407 /* address */
1408
Yaniv Rosnere10bc842010-09-07 11:40:50 +00001409 tmp = ((phy->addr << 21) | (devad << 16) | reg |
Yaniv Rosnerea4e0402008-06-23 20:27:26 -07001410 EMAC_MDIO_COMM_COMMAND_ADDRESS |
1411 EMAC_MDIO_COMM_START_BUSY);
Yaniv Rosnere10bc842010-09-07 11:40:50 +00001412 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, tmp);
Yaniv Rosnerea4e0402008-06-23 20:27:26 -07001413
1414 for (i = 0; i < 50; i++) {
1415 udelay(10);
1416
Yaniv Rosnere10bc842010-09-07 11:40:50 +00001417 tmp = REG_RD(bp, phy->mdio_ctrl +
1418 EMAC_REG_EMAC_MDIO_COMM);
Yaniv Rosnerea4e0402008-06-23 20:27:26 -07001419 if (!(tmp & EMAC_MDIO_COMM_START_BUSY)) {
1420 udelay(5);
1421 break;
1422 }
1423 }
1424 if (tmp & EMAC_MDIO_COMM_START_BUSY) {
1425 DP(NETIF_MSG_LINK, "write phy register failed\n");
1426 rc = -EFAULT;
1427 } else {
1428 /* data */
Yaniv Rosnere10bc842010-09-07 11:40:50 +00001429 tmp = ((phy->addr << 21) | (devad << 16) | val |
Yaniv Rosnerea4e0402008-06-23 20:27:26 -07001430 EMAC_MDIO_COMM_COMMAND_WRITE_45 |
1431 EMAC_MDIO_COMM_START_BUSY);
Yaniv Rosnere10bc842010-09-07 11:40:50 +00001432 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, tmp);
Yaniv Rosnerea4e0402008-06-23 20:27:26 -07001433
1434 for (i = 0; i < 50; i++) {
1435 udelay(10);
1436
Yaniv Rosnere10bc842010-09-07 11:40:50 +00001437 tmp = REG_RD(bp, phy->mdio_ctrl +
Yaniv Rosnerea4e0402008-06-23 20:27:26 -07001438 EMAC_REG_EMAC_MDIO_COMM);
1439 if (!(tmp & EMAC_MDIO_COMM_START_BUSY)) {
1440 udelay(5);
1441 break;
1442 }
1443 }
1444 if (tmp & EMAC_MDIO_COMM_START_BUSY) {
1445 DP(NETIF_MSG_LINK, "write phy register failed\n");
1446 rc = -EFAULT;
1447 }
1448 }
1449
1450 /* Restore the saved mode */
Yaniv Rosnere10bc842010-09-07 11:40:50 +00001451 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE, saved_mode);
Yaniv Rosnerea4e0402008-06-23 20:27:26 -07001452
1453 return rc;
1454}
1455
Yaniv Rosnere10bc842010-09-07 11:40:50 +00001456u8 bnx2x_cl45_read(struct bnx2x *bp, struct bnx2x_phy *phy,
1457 u8 devad, u16 reg, u16 *ret_val)
Yaniv Rosnerea4e0402008-06-23 20:27:26 -07001458{
1459 u32 val, saved_mode;
1460 u16 i;
1461 u8 rc = 0;
1462
Yaniv Rosnerea4e0402008-06-23 20:27:26 -07001463 /* set clause 45 mode, slow down the MDIO clock to 2.5MHz
1464 * (a value of 49==0x31) and make sure that the AUTO poll is off
1465 */
Eilon Greenstein589abe32009-02-12 08:36:55 +00001466
Yaniv Rosnere10bc842010-09-07 11:40:50 +00001467 saved_mode = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE);
1468 val = saved_mode & ~((EMAC_MDIO_MODE_AUTO_POLL |
Yaniv Rosnerea4e0402008-06-23 20:27:26 -07001469 EMAC_MDIO_MODE_CLOCK_CNT));
1470 val |= (EMAC_MDIO_MODE_CLAUSE_45 |
Eilon Greensteinab6ad5a2009-08-12 08:24:29 +00001471 (49L << EMAC_MDIO_MODE_CLOCK_CNT_BITSHIFT));
Yaniv Rosnere10bc842010-09-07 11:40:50 +00001472 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE, val);
1473 REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE);
Yaniv Rosnerea4e0402008-06-23 20:27:26 -07001474 udelay(40);
1475
1476 /* address */
Yaniv Rosnere10bc842010-09-07 11:40:50 +00001477 val = ((phy->addr << 21) | (devad << 16) | reg |
Yaniv Rosnerea4e0402008-06-23 20:27:26 -07001478 EMAC_MDIO_COMM_COMMAND_ADDRESS |
1479 EMAC_MDIO_COMM_START_BUSY);
Yaniv Rosnere10bc842010-09-07 11:40:50 +00001480 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, val);
Yaniv Rosnerea4e0402008-06-23 20:27:26 -07001481
1482 for (i = 0; i < 50; i++) {
1483 udelay(10);
1484
Yaniv Rosnere10bc842010-09-07 11:40:50 +00001485 val = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM);
Yaniv Rosnerea4e0402008-06-23 20:27:26 -07001486 if (!(val & EMAC_MDIO_COMM_START_BUSY)) {
1487 udelay(5);
1488 break;
1489 }
1490 }
1491 if (val & EMAC_MDIO_COMM_START_BUSY) {
1492 DP(NETIF_MSG_LINK, "read phy register failed\n");
1493
1494 *ret_val = 0;
1495 rc = -EFAULT;
1496
1497 } else {
1498 /* data */
Yaniv Rosnere10bc842010-09-07 11:40:50 +00001499 val = ((phy->addr << 21) | (devad << 16) |
Yaniv Rosnerea4e0402008-06-23 20:27:26 -07001500 EMAC_MDIO_COMM_COMMAND_READ_45 |
1501 EMAC_MDIO_COMM_START_BUSY);
Yaniv Rosnere10bc842010-09-07 11:40:50 +00001502 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, val);
Yaniv Rosnerea4e0402008-06-23 20:27:26 -07001503
1504 for (i = 0; i < 50; i++) {
1505 udelay(10);
1506
Yaniv Rosnere10bc842010-09-07 11:40:50 +00001507 val = REG_RD(bp, phy->mdio_ctrl +
Yaniv Rosnerea4e0402008-06-23 20:27:26 -07001508 EMAC_REG_EMAC_MDIO_COMM);
1509 if (!(val & EMAC_MDIO_COMM_START_BUSY)) {
1510 *ret_val = (u16)(val & EMAC_MDIO_COMM_DATA);
1511 break;
1512 }
1513 }
1514 if (val & EMAC_MDIO_COMM_START_BUSY) {
1515 DP(NETIF_MSG_LINK, "read phy register failed\n");
1516
1517 *ret_val = 0;
1518 rc = -EFAULT;
1519 }
1520 }
1521
1522 /* Restore the saved mode */
Yaniv Rosnere10bc842010-09-07 11:40:50 +00001523 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE, saved_mode);
Yaniv Rosnerea4e0402008-06-23 20:27:26 -07001524
1525 return rc;
1526}
1527
Yaniv Rosnere10bc842010-09-07 11:40:50 +00001528u8 bnx2x_phy_read(struct link_params *params, u8 phy_addr,
1529 u8 devad, u16 reg, u16 *ret_val)
1530{
1531 u8 phy_index;
1532 /**
1533 * Probe for the phy according to the given phy_addr, and execute
1534 * the read request on it
1535 */
1536 for (phy_index = 0; phy_index < params->num_phys; phy_index++) {
1537 if (params->phy[phy_index].addr == phy_addr) {
1538 return bnx2x_cl45_read(params->bp,
1539 &params->phy[phy_index], devad,
1540 reg, ret_val);
1541 }
1542 }
1543 return -EINVAL;
1544}
1545
1546u8 bnx2x_phy_write(struct link_params *params, u8 phy_addr,
1547 u8 devad, u16 reg, u16 val)
1548{
1549 u8 phy_index;
1550 /**
1551 * Probe for the phy according to the given phy_addr, and execute
1552 * the write request on it
1553 */
1554 for (phy_index = 0; phy_index < params->num_phys; phy_index++) {
1555 if (params->phy[phy_index].addr == phy_addr) {
1556 return bnx2x_cl45_write(params->bp,
1557 &params->phy[phy_index], devad,
1558 reg, val);
1559 }
1560 }
1561 return -EINVAL;
1562}
1563
Dmitry Kravkovf2e08992010-10-06 03:28:26 +00001564static void bnx2x_set_aer_mmd_xgxs(struct link_params *params,
1565 struct bnx2x_phy *phy)
Yaniv Rosnerea4e0402008-06-23 20:27:26 -07001566{
Yaniv Rosnerea4e0402008-06-23 20:27:26 -07001567 u32 ser_lane;
Dmitry Kravkovf2e08992010-10-06 03:28:26 +00001568 u16 offset, aer_val;
1569 struct bnx2x *bp = params->bp;
Yaniv Rosnerea4e0402008-06-23 20:27:26 -07001570 ser_lane = ((params->lane_config &
1571 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >>
1572 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT);
1573
Dmitry Kravkovf2e08992010-10-06 03:28:26 +00001574 offset = phy->addr + ser_lane;
1575 if (CHIP_IS_E2(bp))
Yaniv Rosner82a0d472011-01-18 04:33:52 +00001576 aer_val = 0x3800 + offset - 1;
Dmitry Kravkovf2e08992010-10-06 03:28:26 +00001577 else
1578 aer_val = 0x3800 + offset;
Yaniv Rosnere10bc842010-09-07 11:40:50 +00001579 CL45_WR_OVER_CL22(bp, phy,
Dmitry Kravkovf2e08992010-10-06 03:28:26 +00001580 MDIO_REG_BANK_AER_BLOCK,
1581 MDIO_AER_BLOCK_AER_REG, aer_val);
1582}
1583static void bnx2x_set_aer_mmd_serdes(struct bnx2x *bp,
1584 struct bnx2x_phy *phy)
1585{
1586 CL45_WR_OVER_CL22(bp, phy,
1587 MDIO_REG_BANK_AER_BLOCK,
1588 MDIO_AER_BLOCK_AER_REG, 0x3800);
Yaniv Rosnerea4e0402008-06-23 20:27:26 -07001589}
1590
Yaniv Rosnerde6eae12010-09-07 11:41:13 +00001591/******************************************************************/
1592/* Internal phy section */
1593/******************************************************************/
1594
1595static void bnx2x_set_serdes_access(struct bnx2x *bp, u8 port)
1596{
1597 u32 emac_base = (port) ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
1598
1599 /* Set Clause 22 */
1600 REG_WR(bp, NIG_REG_SERDES0_CTRL_MD_ST + port*0x10, 1);
1601 REG_WR(bp, emac_base + EMAC_REG_EMAC_MDIO_COMM, 0x245f8000);
1602 udelay(500);
1603 REG_WR(bp, emac_base + EMAC_REG_EMAC_MDIO_COMM, 0x245d000f);
1604 udelay(500);
1605 /* Set Clause 45 */
1606 REG_WR(bp, NIG_REG_SERDES0_CTRL_MD_ST + port*0x10, 0);
1607}
1608
1609static void bnx2x_serdes_deassert(struct bnx2x *bp, u8 port)
1610{
1611 u32 val;
1612
1613 DP(NETIF_MSG_LINK, "bnx2x_serdes_deassert\n");
1614
1615 val = SERDES_RESET_BITS << (port*16);
1616
1617 /* reset and unreset the SerDes/XGXS */
1618 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_CLEAR, val);
1619 udelay(500);
1620 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_SET, val);
1621
1622 bnx2x_set_serdes_access(bp, port);
1623
1624 REG_WR(bp, NIG_REG_SERDES0_CTRL_MD_DEVAD +
1625 port*0x10,
1626 DEFAULT_PHY_DEV_ADDR);
1627}
1628
1629static void bnx2x_xgxs_deassert(struct link_params *params)
1630{
1631 struct bnx2x *bp = params->bp;
1632 u8 port;
1633 u32 val;
1634 DP(NETIF_MSG_LINK, "bnx2x_xgxs_deassert\n");
1635 port = params->port;
1636
1637 val = XGXS_RESET_BITS << (port*16);
1638
1639 /* reset and unreset the SerDes/XGXS */
1640 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_CLEAR, val);
1641 udelay(500);
1642 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_SET, val);
1643
1644 REG_WR(bp, NIG_REG_XGXS0_CTRL_MD_ST +
1645 port*0x18, 0);
1646 REG_WR(bp, NIG_REG_XGXS0_CTRL_MD_DEVAD + port*0x18,
1647 params->phy[INT_PHY].def_md_devad);
1648}
1649
Yaniv Rosnera22f0782010-09-07 11:41:20 +00001650
Yaniv Rosnerde6eae12010-09-07 11:41:13 +00001651void bnx2x_link_status_update(struct link_params *params,
1652 struct link_vars *vars)
1653{
1654 struct bnx2x *bp = params->bp;
1655 u8 link_10g;
1656 u8 port = params->port;
1657
Yaniv Rosnerde6eae12010-09-07 11:41:13 +00001658 vars->link_status = REG_RD(bp, params->shmem_base +
1659 offsetof(struct shmem_region,
1660 port_mb[port].link_status));
1661
1662 vars->link_up = (vars->link_status & LINK_STATUS_LINK_UP);
1663
1664 if (vars->link_up) {
1665 DP(NETIF_MSG_LINK, "phy link up\n");
1666
1667 vars->phy_link_up = 1;
1668 vars->duplex = DUPLEX_FULL;
1669 switch (vars->link_status &
1670 LINK_STATUS_SPEED_AND_DUPLEX_MASK) {
1671 case LINK_10THD:
1672 vars->duplex = DUPLEX_HALF;
1673 /* fall thru */
1674 case LINK_10TFD:
1675 vars->line_speed = SPEED_10;
1676 break;
1677
1678 case LINK_100TXHD:
1679 vars->duplex = DUPLEX_HALF;
1680 /* fall thru */
1681 case LINK_100T4:
1682 case LINK_100TXFD:
1683 vars->line_speed = SPEED_100;
1684 break;
1685
1686 case LINK_1000THD:
1687 vars->duplex = DUPLEX_HALF;
1688 /* fall thru */
1689 case LINK_1000TFD:
1690 vars->line_speed = SPEED_1000;
1691 break;
1692
1693 case LINK_2500THD:
1694 vars->duplex = DUPLEX_HALF;
1695 /* fall thru */
1696 case LINK_2500TFD:
1697 vars->line_speed = SPEED_2500;
1698 break;
1699
1700 case LINK_10GTFD:
1701 vars->line_speed = SPEED_10000;
1702 break;
1703
1704 case LINK_12GTFD:
1705 vars->line_speed = SPEED_12000;
1706 break;
1707
1708 case LINK_12_5GTFD:
1709 vars->line_speed = SPEED_12500;
1710 break;
1711
1712 case LINK_13GTFD:
1713 vars->line_speed = SPEED_13000;
1714 break;
1715
1716 case LINK_15GTFD:
1717 vars->line_speed = SPEED_15000;
1718 break;
1719
1720 case LINK_16GTFD:
1721 vars->line_speed = SPEED_16000;
1722 break;
1723
1724 default:
1725 break;
1726 }
Yaniv Rosnerde6eae12010-09-07 11:41:13 +00001727 vars->flow_ctrl = 0;
1728 if (vars->link_status & LINK_STATUS_TX_FLOW_CONTROL_ENABLED)
1729 vars->flow_ctrl |= BNX2X_FLOW_CTRL_TX;
1730
1731 if (vars->link_status & LINK_STATUS_RX_FLOW_CONTROL_ENABLED)
1732 vars->flow_ctrl |= BNX2X_FLOW_CTRL_RX;
1733
1734 if (!vars->flow_ctrl)
1735 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
1736
1737 if (vars->line_speed &&
1738 ((vars->line_speed == SPEED_10) ||
1739 (vars->line_speed == SPEED_100))) {
1740 vars->phy_flags |= PHY_SGMII_FLAG;
1741 } else {
1742 vars->phy_flags &= ~PHY_SGMII_FLAG;
1743 }
1744
1745 /* anything 10 and over uses the bmac */
1746 link_10g = ((vars->line_speed == SPEED_10000) ||
1747 (vars->line_speed == SPEED_12000) ||
1748 (vars->line_speed == SPEED_12500) ||
1749 (vars->line_speed == SPEED_13000) ||
1750 (vars->line_speed == SPEED_15000) ||
1751 (vars->line_speed == SPEED_16000));
1752 if (link_10g)
1753 vars->mac_type = MAC_TYPE_BMAC;
1754 else
1755 vars->mac_type = MAC_TYPE_EMAC;
1756
1757 } else { /* link down */
1758 DP(NETIF_MSG_LINK, "phy link down\n");
1759
1760 vars->phy_link_up = 0;
1761
1762 vars->line_speed = 0;
1763 vars->duplex = DUPLEX_FULL;
1764 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
1765
1766 /* indicate no mac active */
1767 vars->mac_type = MAC_TYPE_NONE;
1768 }
1769
1770 DP(NETIF_MSG_LINK, "link_status 0x%x phy_link_up %x\n",
1771 vars->link_status, vars->phy_link_up);
1772 DP(NETIF_MSG_LINK, "line_speed %x duplex %x flow_ctrl 0x%x\n",
1773 vars->line_speed, vars->duplex, vars->flow_ctrl);
1774}
1775
1776
Yaniv Rosnere10bc842010-09-07 11:40:50 +00001777static void bnx2x_set_master_ln(struct link_params *params,
1778 struct bnx2x_phy *phy)
Yaniv Rosnerea4e0402008-06-23 20:27:26 -07001779{
1780 struct bnx2x *bp = params->bp;
1781 u16 new_master_ln, ser_lane;
1782 ser_lane = ((params->lane_config &
1783 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >>
1784 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT);
1785
1786 /* set the master_ln for AN */
Yaniv Rosnere10bc842010-09-07 11:40:50 +00001787 CL45_RD_OVER_CL22(bp, phy,
Yaniv Rosnerea4e0402008-06-23 20:27:26 -07001788 MDIO_REG_BANK_XGXS_BLOCK2,
1789 MDIO_XGXS_BLOCK2_TEST_MODE_LANE,
1790 &new_master_ln);
1791
Yaniv Rosnere10bc842010-09-07 11:40:50 +00001792 CL45_WR_OVER_CL22(bp, phy,
Yaniv Rosnerea4e0402008-06-23 20:27:26 -07001793 MDIO_REG_BANK_XGXS_BLOCK2 ,
1794 MDIO_XGXS_BLOCK2_TEST_MODE_LANE,
1795 (new_master_ln | ser_lane));
1796}
1797
Yaniv Rosnere10bc842010-09-07 11:40:50 +00001798static u8 bnx2x_reset_unicore(struct link_params *params,
1799 struct bnx2x_phy *phy,
1800 u8 set_serdes)
Yaniv Rosnerea4e0402008-06-23 20:27:26 -07001801{
1802 struct bnx2x *bp = params->bp;
1803 u16 mii_control;
1804 u16 i;
1805
Yaniv Rosnere10bc842010-09-07 11:40:50 +00001806 CL45_RD_OVER_CL22(bp, phy,
Yaniv Rosnerea4e0402008-06-23 20:27:26 -07001807 MDIO_REG_BANK_COMBO_IEEE0,
1808 MDIO_COMBO_IEEE0_MII_CONTROL, &mii_control);
1809
1810 /* reset the unicore */
Yaniv Rosnere10bc842010-09-07 11:40:50 +00001811 CL45_WR_OVER_CL22(bp, phy,
Yaniv Rosnerea4e0402008-06-23 20:27:26 -07001812 MDIO_REG_BANK_COMBO_IEEE0,
1813 MDIO_COMBO_IEEE0_MII_CONTROL,
1814 (mii_control |
1815 MDIO_COMBO_IEEO_MII_CONTROL_RESET));
Yaniv Rosnere10bc842010-09-07 11:40:50 +00001816 if (set_serdes)
1817 bnx2x_set_serdes_access(bp, params->port);
Eilon Greensteinc1b73992009-02-12 08:37:07 +00001818
Yaniv Rosnerea4e0402008-06-23 20:27:26 -07001819 /* wait for the reset to self clear */
1820 for (i = 0; i < MDIO_ACCESS_TIMEOUT; i++) {
1821 udelay(5);
1822
1823 /* the reset erased the previous bank value */
Yaniv Rosnere10bc842010-09-07 11:40:50 +00001824 CL45_RD_OVER_CL22(bp, phy,
Yaniv Rosnerea4e0402008-06-23 20:27:26 -07001825 MDIO_REG_BANK_COMBO_IEEE0,
1826 MDIO_COMBO_IEEE0_MII_CONTROL,
1827 &mii_control);
1828
1829 if (!(mii_control & MDIO_COMBO_IEEO_MII_CONTROL_RESET)) {
1830 udelay(5);
1831 return 0;
1832 }
1833 }
1834
1835 DP(NETIF_MSG_LINK, "BUG! XGXS is still in reset!\n");
1836 return -EINVAL;
1837
1838}
1839
Yaniv Rosnere10bc842010-09-07 11:40:50 +00001840static void bnx2x_set_swap_lanes(struct link_params *params,
1841 struct bnx2x_phy *phy)
Yaniv Rosnerea4e0402008-06-23 20:27:26 -07001842{
1843 struct bnx2x *bp = params->bp;
1844 /* Each two bits represents a lane number:
1845 No swap is 0123 => 0x1b no need to enable the swap */
1846 u16 ser_lane, rx_lane_swap, tx_lane_swap;
1847
1848 ser_lane = ((params->lane_config &
1849 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >>
1850 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT);
1851 rx_lane_swap = ((params->lane_config &
1852 PORT_HW_CFG_LANE_SWAP_CFG_RX_MASK) >>
1853 PORT_HW_CFG_LANE_SWAP_CFG_RX_SHIFT);
1854 tx_lane_swap = ((params->lane_config &
1855 PORT_HW_CFG_LANE_SWAP_CFG_TX_MASK) >>
1856 PORT_HW_CFG_LANE_SWAP_CFG_TX_SHIFT);
1857
1858 if (rx_lane_swap != 0x1b) {
Yaniv Rosnere10bc842010-09-07 11:40:50 +00001859 CL45_WR_OVER_CL22(bp, phy,
Yaniv Rosnerea4e0402008-06-23 20:27:26 -07001860 MDIO_REG_BANK_XGXS_BLOCK2,
1861 MDIO_XGXS_BLOCK2_RX_LN_SWAP,
1862 (rx_lane_swap |
1863 MDIO_XGXS_BLOCK2_RX_LN_SWAP_ENABLE |
1864 MDIO_XGXS_BLOCK2_RX_LN_SWAP_FORCE_ENABLE));
1865 } else {
Yaniv Rosnere10bc842010-09-07 11:40:50 +00001866 CL45_WR_OVER_CL22(bp, phy,
Yaniv Rosnerea4e0402008-06-23 20:27:26 -07001867 MDIO_REG_BANK_XGXS_BLOCK2,
1868 MDIO_XGXS_BLOCK2_RX_LN_SWAP, 0);
1869 }
1870
1871 if (tx_lane_swap != 0x1b) {
Yaniv Rosnere10bc842010-09-07 11:40:50 +00001872 CL45_WR_OVER_CL22(bp, phy,
Yaniv Rosnerea4e0402008-06-23 20:27:26 -07001873 MDIO_REG_BANK_XGXS_BLOCK2,
1874 MDIO_XGXS_BLOCK2_TX_LN_SWAP,
1875 (tx_lane_swap |
1876 MDIO_XGXS_BLOCK2_TX_LN_SWAP_ENABLE));
1877 } else {
Yaniv Rosnere10bc842010-09-07 11:40:50 +00001878 CL45_WR_OVER_CL22(bp, phy,
Yaniv Rosnerea4e0402008-06-23 20:27:26 -07001879 MDIO_REG_BANK_XGXS_BLOCK2,
1880 MDIO_XGXS_BLOCK2_TX_LN_SWAP, 0);
1881 }
1882}
1883
Yaniv Rosnere10bc842010-09-07 11:40:50 +00001884static void bnx2x_set_parallel_detection(struct bnx2x_phy *phy,
1885 struct link_params *params)
Yaniv Rosnerea4e0402008-06-23 20:27:26 -07001886{
1887 struct bnx2x *bp = params->bp;
1888 u16 control2;
Yaniv Rosnere10bc842010-09-07 11:40:50 +00001889 CL45_RD_OVER_CL22(bp, phy,
Yaniv Rosnerea4e0402008-06-23 20:27:26 -07001890 MDIO_REG_BANK_SERDES_DIGITAL,
1891 MDIO_SERDES_DIGITAL_A_1000X_CONTROL2,
1892 &control2);
Yaniv Rosner7aa07112010-09-07 11:41:01 +00001893 if (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)
Yaniv Rosner18afb0a2009-11-05 19:18:04 +02001894 control2 |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL2_PRL_DT_EN;
1895 else
1896 control2 &= ~MDIO_SERDES_DIGITAL_A_1000X_CONTROL2_PRL_DT_EN;
Yaniv Rosner7aa07112010-09-07 11:41:01 +00001897 DP(NETIF_MSG_LINK, "phy->speed_cap_mask = 0x%x, control2 = 0x%x\n",
1898 phy->speed_cap_mask, control2);
Yaniv Rosnere10bc842010-09-07 11:40:50 +00001899 CL45_WR_OVER_CL22(bp, phy,
Yaniv Rosnerea4e0402008-06-23 20:27:26 -07001900 MDIO_REG_BANK_SERDES_DIGITAL,
1901 MDIO_SERDES_DIGITAL_A_1000X_CONTROL2,
1902 control2);
1903
Yaniv Rosnere10bc842010-09-07 11:40:50 +00001904 if ((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) &&
Yaniv Rosnerc18aa152010-09-07 11:41:07 +00001905 (phy->speed_cap_mask &
Yaniv Rosner18afb0a2009-11-05 19:18:04 +02001906 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) {
Yaniv Rosnerea4e0402008-06-23 20:27:26 -07001907 DP(NETIF_MSG_LINK, "XGXS\n");
1908
Yaniv Rosnere10bc842010-09-07 11:40:50 +00001909 CL45_WR_OVER_CL22(bp, phy,
Yaniv Rosnerea4e0402008-06-23 20:27:26 -07001910 MDIO_REG_BANK_10G_PARALLEL_DETECT,
1911 MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_LINK,
1912 MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_LINK_CNT);
1913
Yaniv Rosnere10bc842010-09-07 11:40:50 +00001914 CL45_RD_OVER_CL22(bp, phy,
Yaniv Rosnerea4e0402008-06-23 20:27:26 -07001915 MDIO_REG_BANK_10G_PARALLEL_DETECT,
1916 MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL,
1917 &control2);
1918
1919
1920 control2 |=
1921 MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL_PARDET10G_EN;
1922
Yaniv Rosnere10bc842010-09-07 11:40:50 +00001923 CL45_WR_OVER_CL22(bp, phy,
Yaniv Rosnerea4e0402008-06-23 20:27:26 -07001924 MDIO_REG_BANK_10G_PARALLEL_DETECT,
1925 MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL,
1926 control2);
1927
1928 /* Disable parallel detection of HiG */
Yaniv Rosnere10bc842010-09-07 11:40:50 +00001929 CL45_WR_OVER_CL22(bp, phy,
Yaniv Rosnerea4e0402008-06-23 20:27:26 -07001930 MDIO_REG_BANK_XGXS_BLOCK2,
1931 MDIO_XGXS_BLOCK2_UNICORE_MODE_10G,
1932 MDIO_XGXS_BLOCK2_UNICORE_MODE_10G_CX4_XGXS |
1933 MDIO_XGXS_BLOCK2_UNICORE_MODE_10G_HIGIG_XGXS);
1934 }
1935}
1936
Yaniv Rosnere10bc842010-09-07 11:40:50 +00001937static void bnx2x_set_autoneg(struct bnx2x_phy *phy,
1938 struct link_params *params,
Eilon Greenstein239d6862009-08-12 08:23:04 +00001939 struct link_vars *vars,
1940 u8 enable_cl73)
Yaniv Rosnerea4e0402008-06-23 20:27:26 -07001941{
1942 struct bnx2x *bp = params->bp;
1943 u16 reg_val;
1944
1945 /* CL37 Autoneg */
Yaniv Rosnere10bc842010-09-07 11:40:50 +00001946 CL45_RD_OVER_CL22(bp, phy,
Yaniv Rosnerea4e0402008-06-23 20:27:26 -07001947 MDIO_REG_BANK_COMBO_IEEE0,
1948 MDIO_COMBO_IEEE0_MII_CONTROL, &reg_val);
1949
1950 /* CL37 Autoneg Enabled */
Yaniv Rosner8c99e7b2008-08-13 15:56:17 -07001951 if (vars->line_speed == SPEED_AUTO_NEG)
Yaniv Rosnerea4e0402008-06-23 20:27:26 -07001952 reg_val |= MDIO_COMBO_IEEO_MII_CONTROL_AN_EN;
1953 else /* CL37 Autoneg Disabled */
1954 reg_val &= ~(MDIO_COMBO_IEEO_MII_CONTROL_AN_EN |
1955 MDIO_COMBO_IEEO_MII_CONTROL_RESTART_AN);
1956
Yaniv Rosnere10bc842010-09-07 11:40:50 +00001957 CL45_WR_OVER_CL22(bp, phy,
Yaniv Rosnerea4e0402008-06-23 20:27:26 -07001958 MDIO_REG_BANK_COMBO_IEEE0,
1959 MDIO_COMBO_IEEE0_MII_CONTROL, reg_val);
1960
1961 /* Enable/Disable Autodetection */
1962
Yaniv Rosnere10bc842010-09-07 11:40:50 +00001963 CL45_RD_OVER_CL22(bp, phy,
Yaniv Rosnerea4e0402008-06-23 20:27:26 -07001964 MDIO_REG_BANK_SERDES_DIGITAL,
1965 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1, &reg_val);
Eilon Greenstein239d6862009-08-12 08:23:04 +00001966 reg_val &= ~(MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_SIGNAL_DETECT_EN |
1967 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_INVERT_SIGNAL_DETECT);
1968 reg_val |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_FIBER_MODE;
Yaniv Rosner8c99e7b2008-08-13 15:56:17 -07001969 if (vars->line_speed == SPEED_AUTO_NEG)
Yaniv Rosnerea4e0402008-06-23 20:27:26 -07001970 reg_val |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_AUTODET;
1971 else
1972 reg_val &= ~MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_AUTODET;
1973
Yaniv Rosnere10bc842010-09-07 11:40:50 +00001974 CL45_WR_OVER_CL22(bp, phy,
Yaniv Rosnerea4e0402008-06-23 20:27:26 -07001975 MDIO_REG_BANK_SERDES_DIGITAL,
1976 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1, reg_val);
1977
1978 /* Enable TetonII and BAM autoneg */
Yaniv Rosnere10bc842010-09-07 11:40:50 +00001979 CL45_RD_OVER_CL22(bp, phy,
Yaniv Rosnerea4e0402008-06-23 20:27:26 -07001980 MDIO_REG_BANK_BAM_NEXT_PAGE,
1981 MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL,
1982 &reg_val);
Yaniv Rosner8c99e7b2008-08-13 15:56:17 -07001983 if (vars->line_speed == SPEED_AUTO_NEG) {
Yaniv Rosnerea4e0402008-06-23 20:27:26 -07001984 /* Enable BAM aneg Mode and TetonII aneg Mode */
1985 reg_val |= (MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_BAM_MODE |
1986 MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_TETON_AN);
1987 } else {
1988 /* TetonII and BAM Autoneg Disabled */
1989 reg_val &= ~(MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_BAM_MODE |
1990 MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_TETON_AN);
1991 }
Yaniv Rosnere10bc842010-09-07 11:40:50 +00001992 CL45_WR_OVER_CL22(bp, phy,
Yaniv Rosnerea4e0402008-06-23 20:27:26 -07001993 MDIO_REG_BANK_BAM_NEXT_PAGE,
1994 MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL,
1995 reg_val);
1996
Eilon Greenstein239d6862009-08-12 08:23:04 +00001997 if (enable_cl73) {
1998 /* Enable Cl73 FSM status bits */
Yaniv Rosnere10bc842010-09-07 11:40:50 +00001999 CL45_WR_OVER_CL22(bp, phy,
Eilon Greenstein239d6862009-08-12 08:23:04 +00002000 MDIO_REG_BANK_CL73_USERB0,
2001 MDIO_CL73_USERB0_CL73_UCTRL,
Yaniv Rosner7846e472009-11-05 19:18:07 +02002002 0xe);
Eilon Greenstein239d6862009-08-12 08:23:04 +00002003
2004 /* Enable BAM Station Manager*/
Yaniv Rosnere10bc842010-09-07 11:40:50 +00002005 CL45_WR_OVER_CL22(bp, phy,
Eilon Greenstein239d6862009-08-12 08:23:04 +00002006 MDIO_REG_BANK_CL73_USERB0,
2007 MDIO_CL73_USERB0_CL73_BAM_CTRL1,
2008 MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_EN |
2009 MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_STATION_MNGR_EN |
2010 MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_NP_AFTER_BP_EN);
2011
Yaniv Rosner7846e472009-11-05 19:18:07 +02002012 /* Advertise CL73 link speeds */
Yaniv Rosnere10bc842010-09-07 11:40:50 +00002013 CL45_RD_OVER_CL22(bp, phy,
Eilon Greenstein239d6862009-08-12 08:23:04 +00002014 MDIO_REG_BANK_CL73_IEEEB1,
2015 MDIO_CL73_IEEEB1_AN_ADV2,
2016 &reg_val);
Yaniv Rosner7aa07112010-09-07 11:41:01 +00002017 if (phy->speed_cap_mask &
Yaniv Rosner7846e472009-11-05 19:18:07 +02002018 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)
2019 reg_val |= MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KX4;
Yaniv Rosner7aa07112010-09-07 11:41:01 +00002020 if (phy->speed_cap_mask &
Yaniv Rosner7846e472009-11-05 19:18:07 +02002021 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)
2022 reg_val |= MDIO_CL73_IEEEB1_AN_ADV2_ADVR_1000M_KX;
Eilon Greenstein239d6862009-08-12 08:23:04 +00002023
Yaniv Rosnere10bc842010-09-07 11:40:50 +00002024 CL45_WR_OVER_CL22(bp, phy,
Yaniv Rosnerde6eae12010-09-07 11:41:13 +00002025 MDIO_REG_BANK_CL73_IEEEB1,
2026 MDIO_CL73_IEEEB1_AN_ADV2,
2027 reg_val);
Eilon Greenstein239d6862009-08-12 08:23:04 +00002028
Eilon Greenstein239d6862009-08-12 08:23:04 +00002029 /* CL73 Autoneg Enabled */
2030 reg_val = MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN;
2031
2032 } else /* CL73 Autoneg Disabled */
2033 reg_val = 0;
Yaniv Rosnerea4e0402008-06-23 20:27:26 -07002034
Yaniv Rosnere10bc842010-09-07 11:40:50 +00002035 CL45_WR_OVER_CL22(bp, phy,
Yaniv Rosnerea4e0402008-06-23 20:27:26 -07002036 MDIO_REG_BANK_CL73_IEEEB0,
2037 MDIO_CL73_IEEEB0_CL73_AN_CONTROL, reg_val);
2038}
2039
2040/* program SerDes, forced speed */
Yaniv Rosnere10bc842010-09-07 11:40:50 +00002041static void bnx2x_program_serdes(struct bnx2x_phy *phy,
2042 struct link_params *params,
Yaniv Rosner8c99e7b2008-08-13 15:56:17 -07002043 struct link_vars *vars)
Yaniv Rosnerea4e0402008-06-23 20:27:26 -07002044{
2045 struct bnx2x *bp = params->bp;
2046 u16 reg_val;
2047
Eilon Greenstein57937202009-08-12 08:23:53 +00002048 /* program duplex, disable autoneg and sgmii*/
Yaniv Rosnere10bc842010-09-07 11:40:50 +00002049 CL45_RD_OVER_CL22(bp, phy,
Yaniv Rosnerea4e0402008-06-23 20:27:26 -07002050 MDIO_REG_BANK_COMBO_IEEE0,
2051 MDIO_COMBO_IEEE0_MII_CONTROL, &reg_val);
2052 reg_val &= ~(MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX |
Eilon Greenstein57937202009-08-12 08:23:53 +00002053 MDIO_COMBO_IEEO_MII_CONTROL_AN_EN |
2054 MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_MASK);
Yaniv Rosner7aa07112010-09-07 11:41:01 +00002055 if (phy->req_duplex == DUPLEX_FULL)
Yaniv Rosnerea4e0402008-06-23 20:27:26 -07002056 reg_val |= MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX;
Yaniv Rosnere10bc842010-09-07 11:40:50 +00002057 CL45_WR_OVER_CL22(bp, phy,
Yaniv Rosnerea4e0402008-06-23 20:27:26 -07002058 MDIO_REG_BANK_COMBO_IEEE0,
2059 MDIO_COMBO_IEEE0_MII_CONTROL, reg_val);
2060
2061 /* program speed
2062 - needed only if the speed is greater than 1G (2.5G or 10G) */
Yaniv Rosnere10bc842010-09-07 11:40:50 +00002063 CL45_RD_OVER_CL22(bp, phy,
Yaniv Rosnerea4e0402008-06-23 20:27:26 -07002064 MDIO_REG_BANK_SERDES_DIGITAL,
2065 MDIO_SERDES_DIGITAL_MISC1, &reg_val);
Yaniv Rosner8c99e7b2008-08-13 15:56:17 -07002066 /* clearing the speed value before setting the right speed */
2067 DP(NETIF_MSG_LINK, "MDIO_REG_BANK_SERDES_DIGITAL = 0x%x\n", reg_val);
2068
2069 reg_val &= ~(MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_MASK |
2070 MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_SEL);
2071
2072 if (!((vars->line_speed == SPEED_1000) ||
2073 (vars->line_speed == SPEED_100) ||
2074 (vars->line_speed == SPEED_10))) {
2075
Yaniv Rosnerea4e0402008-06-23 20:27:26 -07002076 reg_val |= (MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_156_25M |
2077 MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_SEL);
Yaniv Rosner8c99e7b2008-08-13 15:56:17 -07002078 if (vars->line_speed == SPEED_10000)
Yaniv Rosnerea4e0402008-06-23 20:27:26 -07002079 reg_val |=
2080 MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_10G_CX4;
Yaniv Rosner8c99e7b2008-08-13 15:56:17 -07002081 if (vars->line_speed == SPEED_13000)
Yaniv Rosnerea4e0402008-06-23 20:27:26 -07002082 reg_val |=
2083 MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_13G;
Yaniv Rosner8c99e7b2008-08-13 15:56:17 -07002084 }
2085
Yaniv Rosnere10bc842010-09-07 11:40:50 +00002086 CL45_WR_OVER_CL22(bp, phy,
Yaniv Rosnerea4e0402008-06-23 20:27:26 -07002087 MDIO_REG_BANK_SERDES_DIGITAL,
2088 MDIO_SERDES_DIGITAL_MISC1, reg_val);
Yaniv Rosner8c99e7b2008-08-13 15:56:17 -07002089
Yaniv Rosnerea4e0402008-06-23 20:27:26 -07002090}
2091
Yaniv Rosnere10bc842010-09-07 11:40:50 +00002092static void bnx2x_set_brcm_cl37_advertisment(struct bnx2x_phy *phy,
2093 struct link_params *params)
Yaniv Rosnerea4e0402008-06-23 20:27:26 -07002094{
2095 struct bnx2x *bp = params->bp;
2096 u16 val = 0;
2097
2098 /* configure the 48 bits for BAM AN */
2099
2100 /* set extended capabilities */
Yaniv Rosner7aa07112010-09-07 11:41:01 +00002101 if (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G)
Yaniv Rosnerea4e0402008-06-23 20:27:26 -07002102 val |= MDIO_OVER_1G_UP1_2_5G;
Yaniv Rosner7aa07112010-09-07 11:41:01 +00002103 if (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)
Yaniv Rosnerea4e0402008-06-23 20:27:26 -07002104 val |= MDIO_OVER_1G_UP1_10G;
Yaniv Rosnere10bc842010-09-07 11:40:50 +00002105 CL45_WR_OVER_CL22(bp, phy,
Yaniv Rosnerea4e0402008-06-23 20:27:26 -07002106 MDIO_REG_BANK_OVER_1G,
2107 MDIO_OVER_1G_UP1, val);
2108
Yaniv Rosnere10bc842010-09-07 11:40:50 +00002109 CL45_WR_OVER_CL22(bp, phy,
Yaniv Rosnerea4e0402008-06-23 20:27:26 -07002110 MDIO_REG_BANK_OVER_1G,
Eilon Greenstein239d6862009-08-12 08:23:04 +00002111 MDIO_OVER_1G_UP3, 0x400);
Yaniv Rosnerea4e0402008-06-23 20:27:26 -07002112}
2113
Yaniv Rosnere10bc842010-09-07 11:40:50 +00002114static void bnx2x_calc_ieee_aneg_adv(struct bnx2x_phy *phy,
2115 struct link_params *params, u16 *ieee_fc)
Yaniv Rosnerea4e0402008-06-23 20:27:26 -07002116{
Yaniv Rosnerd5cb9e92009-11-05 19:18:10 +02002117 struct bnx2x *bp = params->bp;
Yaniv Rosner8c99e7b2008-08-13 15:56:17 -07002118 *ieee_fc = MDIO_COMBO_IEEE0_AUTO_NEG_ADV_FULL_DUPLEX;
Yaniv Rosnerea4e0402008-06-23 20:27:26 -07002119 /* resolve pause mode and advertisement
2120 * Please refer to Table 28B-3 of the 802.3ab-1999 spec */
2121
Yaniv Rosner7aa07112010-09-07 11:41:01 +00002122 switch (phy->req_flow_ctrl) {
David S. Millerc0700f92008-12-16 23:53:20 -08002123 case BNX2X_FLOW_CTRL_AUTO:
2124 if (params->req_fc_auto_adv == BNX2X_FLOW_CTRL_BOTH) {
Yaniv Rosner8c99e7b2008-08-13 15:56:17 -07002125 *ieee_fc |=
Yaniv Rosnerea4e0402008-06-23 20:27:26 -07002126 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH;
2127 } else {
Yaniv Rosner8c99e7b2008-08-13 15:56:17 -07002128 *ieee_fc |=
Yaniv Rosnerea4e0402008-06-23 20:27:26 -07002129 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC;
2130 }
2131 break;
David S. Millerc0700f92008-12-16 23:53:20 -08002132 case BNX2X_FLOW_CTRL_TX:
Yaniv Rosner8c99e7b2008-08-13 15:56:17 -07002133 *ieee_fc |=
Yaniv Rosnerea4e0402008-06-23 20:27:26 -07002134 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC;
2135 break;
2136
David S. Millerc0700f92008-12-16 23:53:20 -08002137 case BNX2X_FLOW_CTRL_RX:
2138 case BNX2X_FLOW_CTRL_BOTH:
Yaniv Rosner8c99e7b2008-08-13 15:56:17 -07002139 *ieee_fc |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH;
Yaniv Rosnerea4e0402008-06-23 20:27:26 -07002140 break;
2141
David S. Millerc0700f92008-12-16 23:53:20 -08002142 case BNX2X_FLOW_CTRL_NONE:
Yaniv Rosnerea4e0402008-06-23 20:27:26 -07002143 default:
Yaniv Rosner8c99e7b2008-08-13 15:56:17 -07002144 *ieee_fc |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_NONE;
Yaniv Rosnerea4e0402008-06-23 20:27:26 -07002145 break;
2146 }
Yaniv Rosnerd5cb9e92009-11-05 19:18:10 +02002147 DP(NETIF_MSG_LINK, "ieee_fc = 0x%x\n", *ieee_fc);
Yaniv Rosner8c99e7b2008-08-13 15:56:17 -07002148}
Yaniv Rosnerea4e0402008-06-23 20:27:26 -07002149
Yaniv Rosnere10bc842010-09-07 11:40:50 +00002150static void bnx2x_set_ieee_aneg_advertisment(struct bnx2x_phy *phy,
2151 struct link_params *params,
Eilon Greenstein1ef70b92009-08-12 08:23:59 +00002152 u16 ieee_fc)
Yaniv Rosner8c99e7b2008-08-13 15:56:17 -07002153{
2154 struct bnx2x *bp = params->bp;
Yaniv Rosner7846e472009-11-05 19:18:07 +02002155 u16 val;
Yaniv Rosner8c99e7b2008-08-13 15:56:17 -07002156 /* for AN, we are always publishing full duplex */
Yaniv Rosnerea4e0402008-06-23 20:27:26 -07002157
Yaniv Rosnere10bc842010-09-07 11:40:50 +00002158 CL45_WR_OVER_CL22(bp, phy,
Yaniv Rosnerea4e0402008-06-23 20:27:26 -07002159 MDIO_REG_BANK_COMBO_IEEE0,
Eilon Greenstein1ef70b92009-08-12 08:23:59 +00002160 MDIO_COMBO_IEEE0_AUTO_NEG_ADV, ieee_fc);
Yaniv Rosnere10bc842010-09-07 11:40:50 +00002161 CL45_RD_OVER_CL22(bp, phy,
Yaniv Rosner7846e472009-11-05 19:18:07 +02002162 MDIO_REG_BANK_CL73_IEEEB1,
2163 MDIO_CL73_IEEEB1_AN_ADV1, &val);
2164 val &= ~MDIO_CL73_IEEEB1_AN_ADV1_PAUSE_BOTH;
2165 val |= ((ieee_fc<<3) & MDIO_CL73_IEEEB1_AN_ADV1_PAUSE_MASK);
Yaniv Rosnere10bc842010-09-07 11:40:50 +00002166 CL45_WR_OVER_CL22(bp, phy,
Yaniv Rosner7846e472009-11-05 19:18:07 +02002167 MDIO_REG_BANK_CL73_IEEEB1,
2168 MDIO_CL73_IEEEB1_AN_ADV1, val);
Yaniv Rosnerea4e0402008-06-23 20:27:26 -07002169}
2170
Yaniv Rosnere10bc842010-09-07 11:40:50 +00002171static void bnx2x_restart_autoneg(struct bnx2x_phy *phy,
2172 struct link_params *params,
2173 u8 enable_cl73)
Yaniv Rosnerea4e0402008-06-23 20:27:26 -07002174{
2175 struct bnx2x *bp = params->bp;
Eilon Greenstein3a36f2e2009-02-12 08:37:09 +00002176 u16 mii_control;
Eilon Greenstein239d6862009-08-12 08:23:04 +00002177
Yaniv Rosnerea4e0402008-06-23 20:27:26 -07002178 DP(NETIF_MSG_LINK, "bnx2x_restart_autoneg\n");
Eilon Greenstein3a36f2e2009-02-12 08:37:09 +00002179 /* Enable and restart BAM/CL37 aneg */
Yaniv Rosnerea4e0402008-06-23 20:27:26 -07002180
Eilon Greenstein239d6862009-08-12 08:23:04 +00002181 if (enable_cl73) {
Yaniv Rosnere10bc842010-09-07 11:40:50 +00002182 CL45_RD_OVER_CL22(bp, phy,
Eilon Greenstein239d6862009-08-12 08:23:04 +00002183 MDIO_REG_BANK_CL73_IEEEB0,
2184 MDIO_CL73_IEEEB0_CL73_AN_CONTROL,
2185 &mii_control);
2186
Yaniv Rosnere10bc842010-09-07 11:40:50 +00002187 CL45_WR_OVER_CL22(bp, phy,
Eilon Greenstein239d6862009-08-12 08:23:04 +00002188 MDIO_REG_BANK_CL73_IEEEB0,
2189 MDIO_CL73_IEEEB0_CL73_AN_CONTROL,
2190 (mii_control |
2191 MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN |
2192 MDIO_CL73_IEEEB0_CL73_AN_CONTROL_RESTART_AN));
2193 } else {
2194
Yaniv Rosnere10bc842010-09-07 11:40:50 +00002195 CL45_RD_OVER_CL22(bp, phy,
Eilon Greenstein239d6862009-08-12 08:23:04 +00002196 MDIO_REG_BANK_COMBO_IEEE0,
2197 MDIO_COMBO_IEEE0_MII_CONTROL,
2198 &mii_control);
2199 DP(NETIF_MSG_LINK,
2200 "bnx2x_restart_autoneg mii_control before = 0x%x\n",
2201 mii_control);
Yaniv Rosnere10bc842010-09-07 11:40:50 +00002202 CL45_WR_OVER_CL22(bp, phy,
Eilon Greenstein239d6862009-08-12 08:23:04 +00002203 MDIO_REG_BANK_COMBO_IEEE0,
2204 MDIO_COMBO_IEEE0_MII_CONTROL,
2205 (mii_control |
2206 MDIO_COMBO_IEEO_MII_CONTROL_AN_EN |
2207 MDIO_COMBO_IEEO_MII_CONTROL_RESTART_AN));
2208 }
Yaniv Rosnerea4e0402008-06-23 20:27:26 -07002209}
2210
Yaniv Rosnere10bc842010-09-07 11:40:50 +00002211static void bnx2x_initialize_sgmii_process(struct bnx2x_phy *phy,
2212 struct link_params *params,
Yaniv Rosner8c99e7b2008-08-13 15:56:17 -07002213 struct link_vars *vars)
Yaniv Rosnerea4e0402008-06-23 20:27:26 -07002214{
2215 struct bnx2x *bp = params->bp;
2216 u16 control1;
2217
2218 /* in SGMII mode, the unicore is always slave */
2219
Yaniv Rosnere10bc842010-09-07 11:40:50 +00002220 CL45_RD_OVER_CL22(bp, phy,
Yaniv Rosnerea4e0402008-06-23 20:27:26 -07002221 MDIO_REG_BANK_SERDES_DIGITAL,
2222 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1,
2223 &control1);
2224 control1 |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_INVERT_SIGNAL_DETECT;
2225 /* set sgmii mode (and not fiber) */
2226 control1 &= ~(MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_FIBER_MODE |
2227 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_AUTODET |
2228 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_MSTR_MODE);
Yaniv Rosnere10bc842010-09-07 11:40:50 +00002229 CL45_WR_OVER_CL22(bp, phy,
Yaniv Rosnerea4e0402008-06-23 20:27:26 -07002230 MDIO_REG_BANK_SERDES_DIGITAL,
2231 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1,
2232 control1);
2233
2234 /* if forced speed */
Yaniv Rosner8c99e7b2008-08-13 15:56:17 -07002235 if (!(vars->line_speed == SPEED_AUTO_NEG)) {
Yaniv Rosnerea4e0402008-06-23 20:27:26 -07002236 /* set speed, disable autoneg */
2237 u16 mii_control;
2238
Yaniv Rosnere10bc842010-09-07 11:40:50 +00002239 CL45_RD_OVER_CL22(bp, phy,
Yaniv Rosnerea4e0402008-06-23 20:27:26 -07002240 MDIO_REG_BANK_COMBO_IEEE0,
2241 MDIO_COMBO_IEEE0_MII_CONTROL,
2242 &mii_control);
2243 mii_control &= ~(MDIO_COMBO_IEEO_MII_CONTROL_AN_EN |
2244 MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_MASK|
2245 MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX);
2246
Yaniv Rosner8c99e7b2008-08-13 15:56:17 -07002247 switch (vars->line_speed) {
Yaniv Rosnerea4e0402008-06-23 20:27:26 -07002248 case SPEED_100:
2249 mii_control |=
2250 MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_100;
2251 break;
2252 case SPEED_1000:
2253 mii_control |=
2254 MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_1000;
2255 break;
2256 case SPEED_10:
2257 /* there is nothing to set for 10M */
2258 break;
2259 default:
2260 /* invalid speed for SGMII */
Yaniv Rosner8c99e7b2008-08-13 15:56:17 -07002261 DP(NETIF_MSG_LINK, "Invalid line_speed 0x%x\n",
2262 vars->line_speed);
Yaniv Rosnerea4e0402008-06-23 20:27:26 -07002263 break;
2264 }
2265
2266 /* setting the full duplex */
Yaniv Rosner7aa07112010-09-07 11:41:01 +00002267 if (phy->req_duplex == DUPLEX_FULL)
Yaniv Rosnerea4e0402008-06-23 20:27:26 -07002268 mii_control |=
2269 MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX;
Yaniv Rosnere10bc842010-09-07 11:40:50 +00002270 CL45_WR_OVER_CL22(bp, phy,
Yaniv Rosnerea4e0402008-06-23 20:27:26 -07002271 MDIO_REG_BANK_COMBO_IEEE0,
2272 MDIO_COMBO_IEEE0_MII_CONTROL,
2273 mii_control);
2274
2275 } else { /* AN mode */
2276 /* enable and restart AN */
Yaniv Rosnere10bc842010-09-07 11:40:50 +00002277 bnx2x_restart_autoneg(phy, params, 0);
Yaniv Rosnerea4e0402008-06-23 20:27:26 -07002278 }
2279}
2280
2281
2282/*
2283 * link management
2284 */
2285
2286static void bnx2x_pause_resolve(struct link_vars *vars, u32 pause_result)
Yaniv Rosner8c99e7b2008-08-13 15:56:17 -07002287{ /* LD LP */
2288 switch (pause_result) { /* ASYM P ASYM P */
2289 case 0xb: /* 1 0 1 1 */
David S. Millerc0700f92008-12-16 23:53:20 -08002290 vars->flow_ctrl = BNX2X_FLOW_CTRL_TX;
Yaniv Rosnerea4e0402008-06-23 20:27:26 -07002291 break;
2292
Yaniv Rosner8c99e7b2008-08-13 15:56:17 -07002293 case 0xe: /* 1 1 1 0 */
David S. Millerc0700f92008-12-16 23:53:20 -08002294 vars->flow_ctrl = BNX2X_FLOW_CTRL_RX;
Yaniv Rosnerea4e0402008-06-23 20:27:26 -07002295 break;
2296
Yaniv Rosner8c99e7b2008-08-13 15:56:17 -07002297 case 0x5: /* 0 1 0 1 */
2298 case 0x7: /* 0 1 1 1 */
2299 case 0xd: /* 1 1 0 1 */
2300 case 0xf: /* 1 1 1 1 */
David S. Millerc0700f92008-12-16 23:53:20 -08002301 vars->flow_ctrl = BNX2X_FLOW_CTRL_BOTH;
Yaniv Rosnerea4e0402008-06-23 20:27:26 -07002302 break;
2303
2304 default:
2305 break;
2306 }
Yaniv Rosner7aa07112010-09-07 11:41:01 +00002307 if (pause_result & (1<<0))
2308 vars->link_status |= LINK_STATUS_LINK_PARTNER_SYMMETRIC_PAUSE;
2309 if (pause_result & (1<<1))
2310 vars->link_status |= LINK_STATUS_LINK_PARTNER_ASYMMETRIC_PAUSE;
Yaniv Rosnerea4e0402008-06-23 20:27:26 -07002311}
2312
Yaniv Rosnere10bc842010-09-07 11:40:50 +00002313static u8 bnx2x_direct_parallel_detect_used(struct bnx2x_phy *phy,
2314 struct link_params *params)
Yaniv Rosner15ddd2d2009-11-05 19:18:12 +02002315{
2316 struct bnx2x *bp = params->bp;
2317 u16 pd_10g, status2_1000x;
Yaniv Rosner7aa07112010-09-07 11:41:01 +00002318 if (phy->req_line_speed != SPEED_AUTO_NEG)
2319 return 0;
Yaniv Rosnere10bc842010-09-07 11:40:50 +00002320 CL45_RD_OVER_CL22(bp, phy,
Yaniv Rosner15ddd2d2009-11-05 19:18:12 +02002321 MDIO_REG_BANK_SERDES_DIGITAL,
2322 MDIO_SERDES_DIGITAL_A_1000X_STATUS2,
2323 &status2_1000x);
Yaniv Rosnere10bc842010-09-07 11:40:50 +00002324 CL45_RD_OVER_CL22(bp, phy,
Yaniv Rosner15ddd2d2009-11-05 19:18:12 +02002325 MDIO_REG_BANK_SERDES_DIGITAL,
2326 MDIO_SERDES_DIGITAL_A_1000X_STATUS2,
2327 &status2_1000x);
2328 if (status2_1000x & MDIO_SERDES_DIGITAL_A_1000X_STATUS2_AN_DISABLED) {
2329 DP(NETIF_MSG_LINK, "1G parallel detect link on port %d\n",
2330 params->port);
2331 return 1;
2332 }
2333
Yaniv Rosnere10bc842010-09-07 11:40:50 +00002334 CL45_RD_OVER_CL22(bp, phy,
Yaniv Rosner15ddd2d2009-11-05 19:18:12 +02002335 MDIO_REG_BANK_10G_PARALLEL_DETECT,
2336 MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_STATUS,
2337 &pd_10g);
2338
2339 if (pd_10g & MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_STATUS_PD_LINK) {
2340 DP(NETIF_MSG_LINK, "10G parallel detect link on port %d\n",
2341 params->port);
2342 return 1;
2343 }
2344 return 0;
2345}
Yaniv Rosnerea4e0402008-06-23 20:27:26 -07002346
Yaniv Rosnere10bc842010-09-07 11:40:50 +00002347static void bnx2x_flow_ctrl_resolve(struct bnx2x_phy *phy,
2348 struct link_params *params,
2349 struct link_vars *vars,
2350 u32 gp_status)
Yaniv Rosnerea4e0402008-06-23 20:27:26 -07002351{
2352 struct bnx2x *bp = params->bp;
Eilon Greenstein3196a882008-08-13 15:58:49 -07002353 u16 ld_pause; /* local driver */
2354 u16 lp_pause; /* link partner */
Yaniv Rosnerea4e0402008-06-23 20:27:26 -07002355 u16 pause_result;
2356
David S. Millerc0700f92008-12-16 23:53:20 -08002357 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
Yaniv Rosnerea4e0402008-06-23 20:27:26 -07002358
2359 /* resolve from gp_status in case of AN complete and not sgmii */
Yaniv Rosner7aa07112010-09-07 11:41:01 +00002360 if (phy->req_flow_ctrl != BNX2X_FLOW_CTRL_AUTO)
2361 vars->flow_ctrl = phy->req_flow_ctrl;
2362 else if (phy->req_line_speed != SPEED_AUTO_NEG)
2363 vars->flow_ctrl = params->req_fc_auto_adv;
2364 else if ((gp_status & MDIO_AN_CL73_OR_37_COMPLETE) &&
2365 (!(vars->phy_flags & PHY_SGMII_FLAG))) {
Yaniv Rosnere10bc842010-09-07 11:40:50 +00002366 if (bnx2x_direct_parallel_detect_used(phy, params)) {
Yaniv Rosner15ddd2d2009-11-05 19:18:12 +02002367 vars->flow_ctrl = params->req_fc_auto_adv;
2368 return;
2369 }
Yaniv Rosner7846e472009-11-05 19:18:07 +02002370 if ((gp_status &
2371 (MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_AUTONEG_COMPLETE |
2372 MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_MR_LP_NP_AN_ABLE)) ==
2373 (MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_AUTONEG_COMPLETE |
2374 MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_MR_LP_NP_AN_ABLE)) {
2375
Yaniv Rosnere10bc842010-09-07 11:40:50 +00002376 CL45_RD_OVER_CL22(bp, phy,
Yaniv Rosner7846e472009-11-05 19:18:07 +02002377 MDIO_REG_BANK_CL73_IEEEB1,
2378 MDIO_CL73_IEEEB1_AN_ADV1,
2379 &ld_pause);
Yaniv Rosnere10bc842010-09-07 11:40:50 +00002380 CL45_RD_OVER_CL22(bp, phy,
Yaniv Rosner7846e472009-11-05 19:18:07 +02002381 MDIO_REG_BANK_CL73_IEEEB1,
2382 MDIO_CL73_IEEEB1_AN_LP_ADV1,
2383 &lp_pause);
2384 pause_result = (ld_pause &
2385 MDIO_CL73_IEEEB1_AN_ADV1_PAUSE_MASK)
2386 >> 8;
2387 pause_result |= (lp_pause &
2388 MDIO_CL73_IEEEB1_AN_LP_ADV1_PAUSE_MASK)
2389 >> 10;
2390 DP(NETIF_MSG_LINK, "pause_result CL73 0x%x\n",
2391 pause_result);
2392 } else {
Yaniv Rosnere10bc842010-09-07 11:40:50 +00002393 CL45_RD_OVER_CL22(bp, phy,
Yaniv Rosner7846e472009-11-05 19:18:07 +02002394 MDIO_REG_BANK_COMBO_IEEE0,
2395 MDIO_COMBO_IEEE0_AUTO_NEG_ADV,
2396 &ld_pause);
Yaniv Rosnere10bc842010-09-07 11:40:50 +00002397 CL45_RD_OVER_CL22(bp, phy,
Yaniv Rosner7846e472009-11-05 19:18:07 +02002398 MDIO_REG_BANK_COMBO_IEEE0,
2399 MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1,
2400 &lp_pause);
2401 pause_result = (ld_pause &
Yaniv Rosnerea4e0402008-06-23 20:27:26 -07002402 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK)>>5;
Yaniv Rosner7846e472009-11-05 19:18:07 +02002403 pause_result |= (lp_pause &
Yaniv Rosnerea4e0402008-06-23 20:27:26 -07002404 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK)>>7;
Yaniv Rosner7846e472009-11-05 19:18:07 +02002405 DP(NETIF_MSG_LINK, "pause_result CL37 0x%x\n",
2406 pause_result);
2407 }
Yaniv Rosnerea4e0402008-06-23 20:27:26 -07002408 bnx2x_pause_resolve(vars, pause_result);
Yaniv Rosnerea4e0402008-06-23 20:27:26 -07002409 }
2410 DP(NETIF_MSG_LINK, "flow_ctrl 0x%x\n", vars->flow_ctrl);
2411}
2412
Yaniv Rosnere10bc842010-09-07 11:40:50 +00002413static void bnx2x_check_fallback_to_cl37(struct bnx2x_phy *phy,
2414 struct link_params *params)
Eilon Greenstein239d6862009-08-12 08:23:04 +00002415{
2416 struct bnx2x *bp = params->bp;
2417 u16 rx_status, ustat_val, cl37_fsm_recieved;
2418 DP(NETIF_MSG_LINK, "bnx2x_check_fallback_to_cl37\n");
2419 /* Step 1: Make sure signal is detected */
Yaniv Rosnere10bc842010-09-07 11:40:50 +00002420 CL45_RD_OVER_CL22(bp, phy,
Eilon Greenstein239d6862009-08-12 08:23:04 +00002421 MDIO_REG_BANK_RX0,
2422 MDIO_RX0_RX_STATUS,
2423 &rx_status);
2424 if ((rx_status & MDIO_RX0_RX_STATUS_SIGDET) !=
2425 (MDIO_RX0_RX_STATUS_SIGDET)) {
2426 DP(NETIF_MSG_LINK, "Signal is not detected. Restoring CL73."
2427 "rx_status(0x80b0) = 0x%x\n", rx_status);
Yaniv Rosnere10bc842010-09-07 11:40:50 +00002428 CL45_WR_OVER_CL22(bp, phy,
Eilon Greenstein239d6862009-08-12 08:23:04 +00002429 MDIO_REG_BANK_CL73_IEEEB0,
2430 MDIO_CL73_IEEEB0_CL73_AN_CONTROL,
2431 MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN);
2432 return;
2433 }
2434 /* Step 2: Check CL73 state machine */
Yaniv Rosnere10bc842010-09-07 11:40:50 +00002435 CL45_RD_OVER_CL22(bp, phy,
Eilon Greenstein239d6862009-08-12 08:23:04 +00002436 MDIO_REG_BANK_CL73_USERB0,
2437 MDIO_CL73_USERB0_CL73_USTAT1,
2438 &ustat_val);
2439 if ((ustat_val &
2440 (MDIO_CL73_USERB0_CL73_USTAT1_LINK_STATUS_CHECK |
2441 MDIO_CL73_USERB0_CL73_USTAT1_AN_GOOD_CHECK_BAM37)) !=
2442 (MDIO_CL73_USERB0_CL73_USTAT1_LINK_STATUS_CHECK |
2443 MDIO_CL73_USERB0_CL73_USTAT1_AN_GOOD_CHECK_BAM37)) {
2444 DP(NETIF_MSG_LINK, "CL73 state-machine is not stable. "
2445 "ustat_val(0x8371) = 0x%x\n", ustat_val);
2446 return;
2447 }
2448 /* Step 3: Check CL37 Message Pages received to indicate LP
2449 supports only CL37 */
Yaniv Rosnere10bc842010-09-07 11:40:50 +00002450 CL45_RD_OVER_CL22(bp, phy,
Eilon Greenstein239d6862009-08-12 08:23:04 +00002451 MDIO_REG_BANK_REMOTE_PHY,
2452 MDIO_REMOTE_PHY_MISC_RX_STATUS,
2453 &cl37_fsm_recieved);
2454 if ((cl37_fsm_recieved &
2455 (MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_OVER1G_MSG |
2456 MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_BRCM_OUI_MSG)) !=
2457 (MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_OVER1G_MSG |
2458 MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_BRCM_OUI_MSG)) {
2459 DP(NETIF_MSG_LINK, "No CL37 FSM were received. "
2460 "misc_rx_status(0x8330) = 0x%x\n",
2461 cl37_fsm_recieved);
2462 return;
2463 }
2464 /* The combined cl37/cl73 fsm state information indicating that we are
2465 connected to a device which does not support cl73, but does support
2466 cl37 BAM. In this case we disable cl73 and restart cl37 auto-neg */
2467 /* Disable CL73 */
Yaniv Rosnere10bc842010-09-07 11:40:50 +00002468 CL45_WR_OVER_CL22(bp, phy,
Eilon Greenstein239d6862009-08-12 08:23:04 +00002469 MDIO_REG_BANK_CL73_IEEEB0,
2470 MDIO_CL73_IEEEB0_CL73_AN_CONTROL,
2471 0);
2472 /* Restart CL37 autoneg */
Yaniv Rosnere10bc842010-09-07 11:40:50 +00002473 bnx2x_restart_autoneg(phy, params, 0);
Eilon Greenstein239d6862009-08-12 08:23:04 +00002474 DP(NETIF_MSG_LINK, "Disabling CL73, and restarting CL37 autoneg\n");
2475}
Yaniv Rosner7aa07112010-09-07 11:41:01 +00002476
2477static void bnx2x_xgxs_an_resolve(struct bnx2x_phy *phy,
2478 struct link_params *params,
2479 struct link_vars *vars,
2480 u32 gp_status)
2481{
2482 if (gp_status & MDIO_AN_CL73_OR_37_COMPLETE)
2483 vars->link_status |=
2484 LINK_STATUS_AUTO_NEGOTIATE_COMPLETE;
2485
2486 if (bnx2x_direct_parallel_detect_used(phy, params))
2487 vars->link_status |=
2488 LINK_STATUS_PARALLEL_DETECTION_USED;
2489}
2490
Yaniv Rosnerb7737c92010-09-07 11:40:54 +00002491static u8 bnx2x_link_settings_status(struct bnx2x_phy *phy,
2492 struct link_params *params,
2493 struct link_vars *vars)
Yaniv Rosnerea4e0402008-06-23 20:27:26 -07002494{
2495 struct bnx2x *bp = params->bp;
Yaniv Rosnerb7737c92010-09-07 11:40:54 +00002496 u16 new_line_speed , gp_status;
Yaniv Rosnerea4e0402008-06-23 20:27:26 -07002497 u8 rc = 0;
Yaniv Rosnerc18aa152010-09-07 11:41:07 +00002498
Yaniv Rosnerb7737c92010-09-07 11:40:54 +00002499 /* Read gp_status */
2500 CL45_RD_OVER_CL22(bp, phy,
2501 MDIO_REG_BANK_GP_STATUS,
2502 MDIO_GP_STATUS_TOP_AN_STATUS1,
2503 &gp_status);
Yaniv Rosner7f02c4a2010-09-07 11:41:23 +00002504
Yaniv Rosner7aa07112010-09-07 11:41:01 +00002505 if (phy->req_line_speed == SPEED_AUTO_NEG)
2506 vars->link_status |= LINK_STATUS_AUTO_NEGOTIATE_ENABLED;
Yaniv Rosnerea4e0402008-06-23 20:27:26 -07002507 if (gp_status & MDIO_GP_STATUS_TOP_AN_STATUS1_LINK_STATUS) {
2508 DP(NETIF_MSG_LINK, "phy link up gp_status=0x%x\n",
2509 gp_status);
2510
2511 vars->phy_link_up = 1;
2512 vars->link_status |= LINK_STATUS_LINK_UP;
2513
2514 if (gp_status & MDIO_GP_STATUS_TOP_AN_STATUS1_DUPLEX_STATUS)
2515 vars->duplex = DUPLEX_FULL;
2516 else
2517 vars->duplex = DUPLEX_HALF;
2518
Yaniv Rosner7aa07112010-09-07 11:41:01 +00002519 if (SINGLE_MEDIA_DIRECT(params)) {
2520 bnx2x_flow_ctrl_resolve(phy, params, vars, gp_status);
2521 if (phy->req_line_speed == SPEED_AUTO_NEG)
2522 bnx2x_xgxs_an_resolve(phy, params, vars,
2523 gp_status);
2524 }
Yaniv Rosnerea4e0402008-06-23 20:27:26 -07002525
2526 switch (gp_status & GP_STATUS_SPEED_MASK) {
2527 case GP_STATUS_10M:
Eilon Greenstein6c55c3cd2009-01-14 06:44:13 +00002528 new_line_speed = SPEED_10;
Yaniv Rosnerea4e0402008-06-23 20:27:26 -07002529 if (vars->duplex == DUPLEX_FULL)
2530 vars->link_status |= LINK_10TFD;
2531 else
2532 vars->link_status |= LINK_10THD;
2533 break;
2534
2535 case GP_STATUS_100M:
Eilon Greenstein6c55c3cd2009-01-14 06:44:13 +00002536 new_line_speed = SPEED_100;
Yaniv Rosnerea4e0402008-06-23 20:27:26 -07002537 if (vars->duplex == DUPLEX_FULL)
2538 vars->link_status |= LINK_100TXFD;
2539 else
2540 vars->link_status |= LINK_100TXHD;
2541 break;
2542
2543 case GP_STATUS_1G:
2544 case GP_STATUS_1G_KX:
Eilon Greenstein6c55c3cd2009-01-14 06:44:13 +00002545 new_line_speed = SPEED_1000;
Yaniv Rosnerea4e0402008-06-23 20:27:26 -07002546 if (vars->duplex == DUPLEX_FULL)
2547 vars->link_status |= LINK_1000TFD;
2548 else
2549 vars->link_status |= LINK_1000THD;
2550 break;
2551
2552 case GP_STATUS_2_5G:
Eilon Greenstein6c55c3cd2009-01-14 06:44:13 +00002553 new_line_speed = SPEED_2500;
Yaniv Rosnerea4e0402008-06-23 20:27:26 -07002554 if (vars->duplex == DUPLEX_FULL)
2555 vars->link_status |= LINK_2500TFD;
2556 else
2557 vars->link_status |= LINK_2500THD;
2558 break;
2559
2560 case GP_STATUS_5G:
2561 case GP_STATUS_6G:
2562 DP(NETIF_MSG_LINK,
2563 "link speed unsupported gp_status 0x%x\n",
2564 gp_status);
2565 return -EINVAL;
Eilon Greensteinab6ad5a2009-08-12 08:24:29 +00002566
Yaniv Rosnerea4e0402008-06-23 20:27:26 -07002567 case GP_STATUS_10G_KX4:
2568 case GP_STATUS_10G_HIG:
2569 case GP_STATUS_10G_CX4:
Eilon Greenstein6c55c3cd2009-01-14 06:44:13 +00002570 new_line_speed = SPEED_10000;
Yaniv Rosnerea4e0402008-06-23 20:27:26 -07002571 vars->link_status |= LINK_10GTFD;
2572 break;
2573
2574 case GP_STATUS_12G_HIG:
Eilon Greenstein6c55c3cd2009-01-14 06:44:13 +00002575 new_line_speed = SPEED_12000;
Yaniv Rosnerea4e0402008-06-23 20:27:26 -07002576 vars->link_status |= LINK_12GTFD;
2577 break;
2578
2579 case GP_STATUS_12_5G:
Eilon Greenstein6c55c3cd2009-01-14 06:44:13 +00002580 new_line_speed = SPEED_12500;
Yaniv Rosnerea4e0402008-06-23 20:27:26 -07002581 vars->link_status |= LINK_12_5GTFD;
2582 break;
2583
2584 case GP_STATUS_13G:
Eilon Greenstein6c55c3cd2009-01-14 06:44:13 +00002585 new_line_speed = SPEED_13000;
Yaniv Rosnerea4e0402008-06-23 20:27:26 -07002586 vars->link_status |= LINK_13GTFD;
2587 break;
2588
2589 case GP_STATUS_15G:
Eilon Greenstein6c55c3cd2009-01-14 06:44:13 +00002590 new_line_speed = SPEED_15000;
Yaniv Rosnerea4e0402008-06-23 20:27:26 -07002591 vars->link_status |= LINK_15GTFD;
2592 break;
2593
2594 case GP_STATUS_16G:
Eilon Greenstein6c55c3cd2009-01-14 06:44:13 +00002595 new_line_speed = SPEED_16000;
Yaniv Rosnerea4e0402008-06-23 20:27:26 -07002596 vars->link_status |= LINK_16GTFD;
2597 break;
2598
2599 default:
2600 DP(NETIF_MSG_LINK,
2601 "link speed unsupported gp_status 0x%x\n",
2602 gp_status);
Eilon Greensteinab6ad5a2009-08-12 08:24:29 +00002603 return -EINVAL;
Yaniv Rosnerea4e0402008-06-23 20:27:26 -07002604 }
2605
Eilon Greenstein6c55c3cd2009-01-14 06:44:13 +00002606 vars->line_speed = new_line_speed;
Yaniv Rosnerea4e0402008-06-23 20:27:26 -07002607
Yaniv Rosnerea4e0402008-06-23 20:27:26 -07002608 } else { /* link_down */
2609 DP(NETIF_MSG_LINK, "phy link down\n");
2610
2611 vars->phy_link_up = 0;
Yaniv Rosner57963ed2008-08-13 15:55:28 -07002612
Yaniv Rosnerea4e0402008-06-23 20:27:26 -07002613 vars->duplex = DUPLEX_FULL;
David S. Millerc0700f92008-12-16 23:53:20 -08002614 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
Yaniv Rosnerea4e0402008-06-23 20:27:26 -07002615 vars->mac_type = MAC_TYPE_NONE;
Eilon Greenstein239d6862009-08-12 08:23:04 +00002616
Yaniv Rosnerc18aa152010-09-07 11:41:07 +00002617 if ((phy->req_line_speed == SPEED_AUTO_NEG) &&
2618 SINGLE_MEDIA_DIRECT(params)) {
Eilon Greenstein239d6862009-08-12 08:23:04 +00002619 /* Check signal is detected */
Yaniv Rosnerc18aa152010-09-07 11:41:07 +00002620 bnx2x_check_fallback_to_cl37(phy, params);
Eilon Greenstein239d6862009-08-12 08:23:04 +00002621 }
Yaniv Rosnerea4e0402008-06-23 20:27:26 -07002622 }
2623
Frans Pop2381a552010-03-24 07:57:36 +00002624 DP(NETIF_MSG_LINK, "gp_status 0x%x phy_link_up %x line_speed %x\n",
Yaniv Rosnerea4e0402008-06-23 20:27:26 -07002625 gp_status, vars->phy_link_up, vars->line_speed);
Yaniv Rosnera22f0782010-09-07 11:41:20 +00002626 DP(NETIF_MSG_LINK, "duplex %x flow_ctrl 0x%x link_status 0x%x\n",
2627 vars->duplex, vars->flow_ctrl, vars->link_status);
Yaniv Rosnerea4e0402008-06-23 20:27:26 -07002628 return rc;
2629}
2630
Eilon Greensteined8680a2009-02-12 08:37:12 +00002631static void bnx2x_set_gmii_tx_driver(struct link_params *params)
Yaniv Rosnerea4e0402008-06-23 20:27:26 -07002632{
2633 struct bnx2x *bp = params->bp;
Yaniv Rosnere10bc842010-09-07 11:40:50 +00002634 struct bnx2x_phy *phy = &params->phy[INT_PHY];
Yaniv Rosnerea4e0402008-06-23 20:27:26 -07002635 u16 lp_up2;
2636 u16 tx_driver;
Eilon Greensteinc2c8b032009-02-12 08:37:14 +00002637 u16 bank;
Yaniv Rosnerea4e0402008-06-23 20:27:26 -07002638
2639 /* read precomp */
Yaniv Rosnere10bc842010-09-07 11:40:50 +00002640 CL45_RD_OVER_CL22(bp, phy,
Yaniv Rosnerea4e0402008-06-23 20:27:26 -07002641 MDIO_REG_BANK_OVER_1G,
2642 MDIO_OVER_1G_LP_UP2, &lp_up2);
2643
Yaniv Rosnerea4e0402008-06-23 20:27:26 -07002644 /* bits [10:7] at lp_up2, positioned at [15:12] */
2645 lp_up2 = (((lp_up2 & MDIO_OVER_1G_LP_UP2_PREEMPHASIS_MASK) >>
2646 MDIO_OVER_1G_LP_UP2_PREEMPHASIS_SHIFT) <<
2647 MDIO_TX0_TX_DRIVER_PREEMPHASIS_SHIFT);
2648
Eilon Greensteinc2c8b032009-02-12 08:37:14 +00002649 if (lp_up2 == 0)
2650 return;
2651
2652 for (bank = MDIO_REG_BANK_TX0; bank <= MDIO_REG_BANK_TX3;
2653 bank += (MDIO_REG_BANK_TX1 - MDIO_REG_BANK_TX0)) {
Yaniv Rosnere10bc842010-09-07 11:40:50 +00002654 CL45_RD_OVER_CL22(bp, phy,
Eilon Greensteinc2c8b032009-02-12 08:37:14 +00002655 bank,
2656 MDIO_TX0_TX_DRIVER, &tx_driver);
2657
2658 /* replace tx_driver bits [15:12] */
2659 if (lp_up2 !=
2660 (tx_driver & MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK)) {
2661 tx_driver &= ~MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK;
2662 tx_driver |= lp_up2;
Yaniv Rosnere10bc842010-09-07 11:40:50 +00002663 CL45_WR_OVER_CL22(bp, phy,
Eilon Greensteinc2c8b032009-02-12 08:37:14 +00002664 bank,
2665 MDIO_TX0_TX_DRIVER, tx_driver);
2666 }
Yaniv Rosnerea4e0402008-06-23 20:27:26 -07002667 }
2668}
2669
2670static u8 bnx2x_emac_program(struct link_params *params,
Yaniv Rosnerb7737c92010-09-07 11:40:54 +00002671 struct link_vars *vars)
Yaniv Rosnerea4e0402008-06-23 20:27:26 -07002672{
2673 struct bnx2x *bp = params->bp;
2674 u8 port = params->port;
2675 u16 mode = 0;
2676
2677 DP(NETIF_MSG_LINK, "setting link speed & duplex\n");
2678 bnx2x_bits_dis(bp, GRCBASE_EMAC0 + port*0x400 +
2679 EMAC_REG_EMAC_MODE,
2680 (EMAC_MODE_25G_MODE |
2681 EMAC_MODE_PORT_MII_10M |
2682 EMAC_MODE_HALF_DUPLEX));
Yaniv Rosnerb7737c92010-09-07 11:40:54 +00002683 switch (vars->line_speed) {
Yaniv Rosnerea4e0402008-06-23 20:27:26 -07002684 case SPEED_10:
2685 mode |= EMAC_MODE_PORT_MII_10M;
2686 break;
2687
2688 case SPEED_100:
2689 mode |= EMAC_MODE_PORT_MII;
2690 break;
2691
2692 case SPEED_1000:
2693 mode |= EMAC_MODE_PORT_GMII;
2694 break;
2695
2696 case SPEED_2500:
2697 mode |= (EMAC_MODE_25G_MODE | EMAC_MODE_PORT_GMII);
2698 break;
2699
2700 default:
2701 /* 10G not valid for EMAC */
Yaniv Rosnerb7737c92010-09-07 11:40:54 +00002702 DP(NETIF_MSG_LINK, "Invalid line_speed 0x%x\n",
2703 vars->line_speed);
Yaniv Rosnerea4e0402008-06-23 20:27:26 -07002704 return -EINVAL;
2705 }
2706
Yaniv Rosnerb7737c92010-09-07 11:40:54 +00002707 if (vars->duplex == DUPLEX_HALF)
Yaniv Rosnerea4e0402008-06-23 20:27:26 -07002708 mode |= EMAC_MODE_HALF_DUPLEX;
2709 bnx2x_bits_en(bp,
2710 GRCBASE_EMAC0 + port*0x400 + EMAC_REG_EMAC_MODE,
2711 mode);
2712
Yaniv Rosner7f02c4a2010-09-07 11:41:23 +00002713 bnx2x_set_led(params, vars, LED_MODE_OPER, vars->line_speed);
Yaniv Rosnerea4e0402008-06-23 20:27:26 -07002714 return 0;
2715}
2716
Yaniv Rosnerde6eae12010-09-07 11:41:13 +00002717static void bnx2x_set_preemphasis(struct bnx2x_phy *phy,
2718 struct link_params *params)
2719{
2720
2721 u16 bank, i = 0;
2722 struct bnx2x *bp = params->bp;
2723
2724 for (bank = MDIO_REG_BANK_RX0, i = 0; bank <= MDIO_REG_BANK_RX3;
2725 bank += (MDIO_REG_BANK_RX1-MDIO_REG_BANK_RX0), i++) {
2726 CL45_WR_OVER_CL22(bp, phy,
2727 bank,
2728 MDIO_RX0_RX_EQ_BOOST,
2729 phy->rx_preemphasis[i]);
2730 }
2731
2732 for (bank = MDIO_REG_BANK_TX0, i = 0; bank <= MDIO_REG_BANK_TX3;
2733 bank += (MDIO_REG_BANK_TX1 - MDIO_REG_BANK_TX0), i++) {
2734 CL45_WR_OVER_CL22(bp, phy,
2735 bank,
2736 MDIO_TX0_TX_DRIVER,
2737 phy->tx_preemphasis[i]);
2738 }
2739}
2740
2741static void bnx2x_init_internal_phy(struct bnx2x_phy *phy,
2742 struct link_params *params,
2743 struct link_vars *vars)
2744{
2745 struct bnx2x *bp = params->bp;
2746 u8 enable_cl73 = (SINGLE_MEDIA_DIRECT(params) ||
2747 (params->loopback_mode == LOOPBACK_XGXS));
2748 if (!(vars->phy_flags & PHY_SGMII_FLAG)) {
2749 if (SINGLE_MEDIA_DIRECT(params) &&
2750 (params->feature_config_flags &
2751 FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED))
2752 bnx2x_set_preemphasis(phy, params);
2753
2754 /* forced speed requested? */
2755 if (vars->line_speed != SPEED_AUTO_NEG ||
2756 (SINGLE_MEDIA_DIRECT(params) &&
2757 params->loopback_mode == LOOPBACK_EXT)) {
2758 DP(NETIF_MSG_LINK, "not SGMII, no AN\n");
2759
2760 /* disable autoneg */
2761 bnx2x_set_autoneg(phy, params, vars, 0);
2762
2763 /* program speed and duplex */
2764 bnx2x_program_serdes(phy, params, vars);
2765
2766 } else { /* AN_mode */
2767 DP(NETIF_MSG_LINK, "not SGMII, AN\n");
2768
2769 /* AN enabled */
2770 bnx2x_set_brcm_cl37_advertisment(phy, params);
2771
2772 /* program duplex & pause advertisement (for aneg) */
2773 bnx2x_set_ieee_aneg_advertisment(phy, params,
2774 vars->ieee_fc);
2775
2776 /* enable autoneg */
2777 bnx2x_set_autoneg(phy, params, vars, enable_cl73);
2778
2779 /* enable and restart AN */
2780 bnx2x_restart_autoneg(phy, params, enable_cl73);
2781 }
2782
2783 } else { /* SGMII mode */
2784 DP(NETIF_MSG_LINK, "SGMII\n");
2785
2786 bnx2x_initialize_sgmii_process(phy, params, vars);
2787 }
2788}
2789
Yaniv Rosnerb7737c92010-09-07 11:40:54 +00002790static u8 bnx2x_init_serdes(struct bnx2x_phy *phy,
2791 struct link_params *params,
2792 struct link_vars *vars)
2793{
2794 u8 rc;
2795 vars->phy_flags |= PHY_SGMII_FLAG;
2796 bnx2x_calc_ieee_aneg_adv(phy, params, &vars->ieee_fc);
Dmitry Kravkovf2e08992010-10-06 03:28:26 +00002797 bnx2x_set_aer_mmd_serdes(params->bp, phy);
Yaniv Rosnerb7737c92010-09-07 11:40:54 +00002798 rc = bnx2x_reset_unicore(params, phy, 1);
2799 /* reset the SerDes and wait for reset bit return low */
2800 if (rc != 0)
2801 return rc;
Dmitry Kravkovf2e08992010-10-06 03:28:26 +00002802 bnx2x_set_aer_mmd_serdes(params->bp, phy);
Yaniv Rosnere10bc842010-09-07 11:40:50 +00002803
Yaniv Rosnerb7737c92010-09-07 11:40:54 +00002804 return rc;
2805}
2806
2807static u8 bnx2x_init_xgxs(struct bnx2x_phy *phy,
2808 struct link_params *params,
2809 struct link_vars *vars)
2810{
2811 u8 rc;
2812 vars->phy_flags = PHY_XGXS_FLAG;
2813 if ((phy->req_line_speed &&
2814 ((phy->req_line_speed == SPEED_100) ||
2815 (phy->req_line_speed == SPEED_10))) ||
2816 (!phy->req_line_speed &&
2817 (phy->speed_cap_mask >=
2818 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL) &&
2819 (phy->speed_cap_mask <
2820 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)
2821 ))
2822 vars->phy_flags |= PHY_SGMII_FLAG;
2823 else
2824 vars->phy_flags &= ~PHY_SGMII_FLAG;
2825
2826 bnx2x_calc_ieee_aneg_adv(phy, params, &vars->ieee_fc);
Dmitry Kravkovf2e08992010-10-06 03:28:26 +00002827 bnx2x_set_aer_mmd_xgxs(params, phy);
Yaniv Rosnerb7737c92010-09-07 11:40:54 +00002828 bnx2x_set_master_ln(params, phy);
2829
2830 rc = bnx2x_reset_unicore(params, phy, 0);
2831 /* reset the SerDes and wait for reset bit return low */
2832 if (rc != 0)
2833 return rc;
2834
Dmitry Kravkovf2e08992010-10-06 03:28:26 +00002835 bnx2x_set_aer_mmd_xgxs(params, phy);
Yaniv Rosnerb7737c92010-09-07 11:40:54 +00002836
2837 /* setting the masterLn_def again after the reset */
2838 bnx2x_set_master_ln(params, phy);
2839 bnx2x_set_swap_lanes(params, phy);
2840
2841 return rc;
2842}
Yaniv Rosnerc18aa152010-09-07 11:41:07 +00002843
Yaniv Rosnerb7737c92010-09-07 11:40:54 +00002844static u16 bnx2x_wait_reset_complete(struct bnx2x *bp,
2845 struct bnx2x_phy *phy)
Yaniv Rosnerea4e0402008-06-23 20:27:26 -07002846{
Yaniv Rosnerb7737c92010-09-07 11:40:54 +00002847 u16 cnt, ctrl;
Yaniv Rosner62b29a52010-09-07 11:40:58 +00002848 /* Wait for soft reset to get cleared upto 1 sec */
2849 for (cnt = 0; cnt < 1000; cnt++) {
2850 bnx2x_cl45_read(bp, phy,
2851 MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, &ctrl);
2852 if (!(ctrl & (1<<15)))
2853 break;
2854 msleep(1);
2855 }
2856 DP(NETIF_MSG_LINK, "control reg 0x%x (after %d ms)\n", ctrl, cnt);
2857 return cnt;
Yaniv Rosnerb7737c92010-09-07 11:40:54 +00002858}
Yaniv Rosnerea4e0402008-06-23 20:27:26 -07002859
Yaniv Rosnerea4e0402008-06-23 20:27:26 -07002860static void bnx2x_link_int_enable(struct link_params *params)
2861{
2862 u8 port = params->port;
Yaniv Rosnerea4e0402008-06-23 20:27:26 -07002863 u32 mask;
2864 struct bnx2x *bp = params->bp;
Eilon Greensteinab6ad5a2009-08-12 08:24:29 +00002865
Yaniv Rosnerea4e0402008-06-23 20:27:26 -07002866 /* setting the status to report on link up
2867 for either XGXS or SerDes */
2868
2869 if (params->switch_cfg == SWITCH_CFG_10G) {
2870 mask = (NIG_MASK_XGXS0_LINK10G |
2871 NIG_MASK_XGXS0_LINK_STATUS);
2872 DP(NETIF_MSG_LINK, "enabled XGXS interrupt\n");
Yaniv Rosnere10bc842010-09-07 11:40:50 +00002873 if (!(SINGLE_MEDIA_DIRECT(params)) &&
2874 params->phy[INT_PHY].type !=
2875 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE) {
Yaniv Rosnerea4e0402008-06-23 20:27:26 -07002876 mask |= NIG_MASK_MI_INT;
2877 DP(NETIF_MSG_LINK, "enabled external phy int\n");
2878 }
2879
2880 } else { /* SerDes */
2881 mask = NIG_MASK_SERDES0_LINK_STATUS;
2882 DP(NETIF_MSG_LINK, "enabled SerDes interrupt\n");
Yaniv Rosnere10bc842010-09-07 11:40:50 +00002883 if (!(SINGLE_MEDIA_DIRECT(params)) &&
2884 params->phy[INT_PHY].type !=
2885 PORT_HW_CFG_SERDES_EXT_PHY_TYPE_NOT_CONN) {
Yaniv Rosnerea4e0402008-06-23 20:27:26 -07002886 mask |= NIG_MASK_MI_INT;
2887 DP(NETIF_MSG_LINK, "enabled external phy int\n");
2888 }
2889 }
2890 bnx2x_bits_en(bp,
2891 NIG_REG_MASK_INTERRUPT_PORT0 + port*4,
2892 mask);
Eilon Greensteinab6ad5a2009-08-12 08:24:29 +00002893
2894 DP(NETIF_MSG_LINK, "port %x, is_xgxs %x, int_status 0x%x\n", port,
Yaniv Rosnerea4e0402008-06-23 20:27:26 -07002895 (params->switch_cfg == SWITCH_CFG_10G),
2896 REG_RD(bp, NIG_REG_STATUS_INTERRUPT_PORT0 + port*4));
Yaniv Rosnerea4e0402008-06-23 20:27:26 -07002897 DP(NETIF_MSG_LINK, " int_mask 0x%x, MI_INT %x, SERDES_LINK %x\n",
2898 REG_RD(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4),
2899 REG_RD(bp, NIG_REG_EMAC0_STATUS_MISC_MI_INT + port*0x18),
2900 REG_RD(bp, NIG_REG_SERDES0_STATUS_LINK_STATUS+port*0x3c));
2901 DP(NETIF_MSG_LINK, " 10G %x, XGXS_LINK %x\n",
2902 REG_RD(bp, NIG_REG_XGXS0_STATUS_LINK10G + port*0x68),
2903 REG_RD(bp, NIG_REG_XGXS0_STATUS_LINK_STATUS + port*0x68));
2904}
2905
Yaniv Rosnera22f0782010-09-07 11:41:20 +00002906static void bnx2x_rearm_latch_signal(struct bnx2x *bp, u8 port,
2907 u8 exp_mi_int)
Eilon Greenstein2f904462009-08-12 08:22:16 +00002908{
Yaniv Rosnera22f0782010-09-07 11:41:20 +00002909 u32 latch_status = 0;
2910
2911 /**
2912 * Disable the MI INT ( external phy int ) by writing 1 to the
2913 * status register. Link down indication is high-active-signal,
2914 * so in this case we need to write the status to clear the XOR
Eilon Greenstein2f904462009-08-12 08:22:16 +00002915 */
2916 /* Read Latched signals */
2917 latch_status = REG_RD(bp,
Yaniv Rosnera22f0782010-09-07 11:41:20 +00002918 NIG_REG_LATCH_STATUS_0 + port*8);
2919 DP(NETIF_MSG_LINK, "latch_status = 0x%x\n", latch_status);
Eilon Greenstein2f904462009-08-12 08:22:16 +00002920 /* Handle only those with latched-signal=up.*/
Yaniv Rosnera22f0782010-09-07 11:41:20 +00002921 if (exp_mi_int)
2922 bnx2x_bits_en(bp,
2923 NIG_REG_STATUS_INTERRUPT_PORT0
2924 + port*4,
2925 NIG_STATUS_EMAC0_MI_INT);
2926 else
2927 bnx2x_bits_dis(bp,
2928 NIG_REG_STATUS_INTERRUPT_PORT0
2929 + port*4,
2930 NIG_STATUS_EMAC0_MI_INT);
2931
Eilon Greenstein2f904462009-08-12 08:22:16 +00002932 if (latch_status & 1) {
Yaniv Rosnera22f0782010-09-07 11:41:20 +00002933
Eilon Greenstein2f904462009-08-12 08:22:16 +00002934 /* For all latched-signal=up : Re-Arm Latch signals */
2935 REG_WR(bp, NIG_REG_LATCH_STATUS_0 + port*8,
Yaniv Rosner7f02c4a2010-09-07 11:41:23 +00002936 (latch_status & 0xfffe) | (latch_status & 1));
Eilon Greenstein2f904462009-08-12 08:22:16 +00002937 }
Yaniv Rosnera22f0782010-09-07 11:41:20 +00002938 /* For all latched-signal=up,Write original_signal to status */
Eilon Greenstein2f904462009-08-12 08:22:16 +00002939}
Yaniv Rosnere10bc842010-09-07 11:40:50 +00002940
Yaniv Rosnerea4e0402008-06-23 20:27:26 -07002941static void bnx2x_link_int_ack(struct link_params *params,
Yaniv Rosnera22f0782010-09-07 11:41:20 +00002942 struct link_vars *vars, u8 is_10g)
Yaniv Rosnerea4e0402008-06-23 20:27:26 -07002943{
2944 struct bnx2x *bp = params->bp;
2945 u8 port = params->port;
2946
2947 /* first reset all status
2948 * we assume only one line will be change at a time */
2949 bnx2x_bits_dis(bp, NIG_REG_STATUS_INTERRUPT_PORT0 + port*4,
2950 (NIG_STATUS_XGXS0_LINK10G |
2951 NIG_STATUS_XGXS0_LINK_STATUS |
2952 NIG_STATUS_SERDES0_LINK_STATUS));
2953 if (vars->phy_link_up) {
2954 if (is_10g) {
2955 /* Disable the 10G link interrupt
2956 * by writing 1 to the status register
2957 */
2958 DP(NETIF_MSG_LINK, "10G XGXS phy link up\n");
2959 bnx2x_bits_en(bp,
2960 NIG_REG_STATUS_INTERRUPT_PORT0 + port*4,
2961 NIG_STATUS_XGXS0_LINK10G);
2962
2963 } else if (params->switch_cfg == SWITCH_CFG_10G) {
2964 /* Disable the link interrupt
2965 * by writing 1 to the relevant lane
2966 * in the status register
2967 */
2968 u32 ser_lane = ((params->lane_config &
2969 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >>
2970 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT);
2971
Eilon Greenstein2f904462009-08-12 08:22:16 +00002972 DP(NETIF_MSG_LINK, "%d speed XGXS phy link up\n",
2973 vars->line_speed);
Yaniv Rosnerea4e0402008-06-23 20:27:26 -07002974 bnx2x_bits_en(bp,
2975 NIG_REG_STATUS_INTERRUPT_PORT0 + port*4,
2976 ((1 << ser_lane) <<
2977 NIG_STATUS_XGXS0_LINK_STATUS_SIZE));
2978
2979 } else { /* SerDes */
2980 DP(NETIF_MSG_LINK, "SerDes phy link up\n");
2981 /* Disable the link interrupt
2982 * by writing 1 to the status register
2983 */
2984 bnx2x_bits_en(bp,
2985 NIG_REG_STATUS_INTERRUPT_PORT0 + port*4,
2986 NIG_STATUS_SERDES0_LINK_STATUS);
2987 }
2988
Yaniv Rosnerea4e0402008-06-23 20:27:26 -07002989 }
2990}
2991
Yaniv Rosnerb7737c92010-09-07 11:40:54 +00002992static u8 bnx2x_format_ver(u32 num, u8 *str, u16 *len)
Yaniv Rosnerea4e0402008-06-23 20:27:26 -07002993{
2994 u8 *str_ptr = str;
2995 u32 mask = 0xf0000000;
2996 u8 shift = 8*4;
2997 u8 digit;
Yaniv Rosnera22f0782010-09-07 11:41:20 +00002998 u8 remove_leading_zeros = 1;
Yaniv Rosnerb7737c92010-09-07 11:40:54 +00002999 if (*len < 10) {
Frederik Schwarzer025dfda2008-10-16 19:02:37 +02003000 /* Need more than 10chars for this format */
Yaniv Rosnerea4e0402008-06-23 20:27:26 -07003001 *str_ptr = '\0';
Yaniv Rosnera22f0782010-09-07 11:41:20 +00003002 (*len)--;
Yaniv Rosnerea4e0402008-06-23 20:27:26 -07003003 return -EINVAL;
3004 }
3005 while (shift > 0) {
3006
3007 shift -= 4;
3008 digit = ((num & mask) >> shift);
Yaniv Rosnera22f0782010-09-07 11:41:20 +00003009 if (digit == 0 && remove_leading_zeros) {
3010 mask = mask >> 4;
3011 continue;
3012 } else if (digit < 0xa)
Yaniv Rosnerea4e0402008-06-23 20:27:26 -07003013 *str_ptr = digit + '0';
3014 else
3015 *str_ptr = digit - 0xa + 'a';
Yaniv Rosnera22f0782010-09-07 11:41:20 +00003016 remove_leading_zeros = 0;
Yaniv Rosnerea4e0402008-06-23 20:27:26 -07003017 str_ptr++;
Yaniv Rosnera22f0782010-09-07 11:41:20 +00003018 (*len)--;
Yaniv Rosnerea4e0402008-06-23 20:27:26 -07003019 mask = mask >> 4;
3020 if (shift == 4*4) {
Yaniv Rosnera22f0782010-09-07 11:41:20 +00003021 *str_ptr = '.';
Yaniv Rosnerea4e0402008-06-23 20:27:26 -07003022 str_ptr++;
Yaniv Rosnera22f0782010-09-07 11:41:20 +00003023 (*len)--;
3024 remove_leading_zeros = 1;
Yaniv Rosnerea4e0402008-06-23 20:27:26 -07003025 }
3026 }
Yaniv Rosnerea4e0402008-06-23 20:27:26 -07003027 return 0;
3028}
3029
Yaniv Rosnera22f0782010-09-07 11:41:20 +00003030
Yaniv Rosnerb7737c92010-09-07 11:40:54 +00003031static u8 bnx2x_null_format_ver(u32 spirom_ver, u8 *str, u16 *len)
3032{
3033 str[0] = '\0';
3034 (*len)--;
3035 return 0;
3036}
Yaniv Rosnerde6eae12010-09-07 11:41:13 +00003037
Yaniv Rosnerea4e0402008-06-23 20:27:26 -07003038u8 bnx2x_get_ext_phy_fw_version(struct link_params *params, u8 driver_loaded,
3039 u8 *version, u16 len)
3040{
Julia Lawall0376d5b2009-07-19 05:26:35 +00003041 struct bnx2x *bp;
Eilon Greensteina35da8d2009-02-12 08:37:02 +00003042 u32 spirom_ver = 0;
Yaniv Rosnerb7737c92010-09-07 11:40:54 +00003043 u8 status = 0;
3044 u8 *ver_p = version;
Yaniv Rosnera22f0782010-09-07 11:41:20 +00003045 u16 remain_len = len;
Yaniv Rosnerea4e0402008-06-23 20:27:26 -07003046 if (version == NULL || params == NULL)
3047 return -EINVAL;
Julia Lawall0376d5b2009-07-19 05:26:35 +00003048 bp = params->bp;
Yaniv Rosnerea4e0402008-06-23 20:27:26 -07003049
Yaniv Rosnerb7737c92010-09-07 11:40:54 +00003050 /* Extract first external phy*/
3051 version[0] = '\0';
3052 spirom_ver = REG_RD(bp, params->phy[EXT_PHY1].ver_addr);
Eilon Greensteina35da8d2009-02-12 08:37:02 +00003053
Yaniv Rosnera22f0782010-09-07 11:41:20 +00003054 if (params->phy[EXT_PHY1].format_fw_ver) {
Yaniv Rosnerb7737c92010-09-07 11:40:54 +00003055 status |= params->phy[EXT_PHY1].format_fw_ver(spirom_ver,
3056 ver_p,
Yaniv Rosnera22f0782010-09-07 11:41:20 +00003057 &remain_len);
3058 ver_p += (len - remain_len);
3059 }
3060 if ((params->num_phys == MAX_PHYS) &&
3061 (params->phy[EXT_PHY2].ver_addr != 0)) {
3062 spirom_ver = REG_RD(bp,
3063 params->phy[EXT_PHY2].ver_addr);
3064 if (params->phy[EXT_PHY2].format_fw_ver) {
3065 *ver_p = '/';
3066 ver_p++;
3067 remain_len--;
3068 status |= params->phy[EXT_PHY2].format_fw_ver(
3069 spirom_ver,
3070 ver_p,
3071 &remain_len);
3072 ver_p = version + (len - remain_len);
3073 }
3074 }
3075 *ver_p = '\0';
Yaniv Rosnerea4e0402008-06-23 20:27:26 -07003076 return status;
3077}
3078
Yaniv Rosnere10bc842010-09-07 11:40:50 +00003079static void bnx2x_set_xgxs_loopback(struct bnx2x_phy *phy,
Yaniv Rosner62b29a52010-09-07 11:40:58 +00003080 struct link_params *params)
Yaniv Rosnerea4e0402008-06-23 20:27:26 -07003081{
3082 u8 port = params->port;
3083 struct bnx2x *bp = params->bp;
3084
Yaniv Rosner62b29a52010-09-07 11:40:58 +00003085 if (phy->req_line_speed != SPEED_1000) {
Eilon Greenstein6378c022008-08-13 15:59:25 -07003086 u32 md_devad;
Yaniv Rosnerea4e0402008-06-23 20:27:26 -07003087
3088 DP(NETIF_MSG_LINK, "XGXS 10G loopback enable\n");
3089
3090 /* change the uni_phy_addr in the nig */
3091 md_devad = REG_RD(bp, (NIG_REG_XGXS0_CTRL_MD_DEVAD +
3092 port*0x18));
3093
3094 REG_WR(bp, NIG_REG_XGXS0_CTRL_MD_DEVAD + port*0x18, 0x5);
3095
Yaniv Rosnere10bc842010-09-07 11:40:50 +00003096 bnx2x_cl45_write(bp, phy,
Yaniv Rosnerea4e0402008-06-23 20:27:26 -07003097 5,
3098 (MDIO_REG_BANK_AER_BLOCK +
3099 (MDIO_AER_BLOCK_AER_REG & 0xf)),
3100 0x2800);
3101
Yaniv Rosnere10bc842010-09-07 11:40:50 +00003102 bnx2x_cl45_write(bp, phy,
Yaniv Rosnerea4e0402008-06-23 20:27:26 -07003103 5,
3104 (MDIO_REG_BANK_CL73_IEEEB0 +
3105 (MDIO_CL73_IEEEB0_CL73_AN_CONTROL & 0xf)),
3106 0x6041);
Eilon Greenstein38582762009-01-14 06:44:16 +00003107 msleep(200);
Yaniv Rosnerea4e0402008-06-23 20:27:26 -07003108 /* set aer mmd back */
Dmitry Kravkovf2e08992010-10-06 03:28:26 +00003109 bnx2x_set_aer_mmd_xgxs(params, phy);
Yaniv Rosnerea4e0402008-06-23 20:27:26 -07003110
3111 /* and md_devad */
3112 REG_WR(bp, NIG_REG_XGXS0_CTRL_MD_DEVAD + port*0x18,
3113 md_devad);
3114
3115 } else {
Yaniv Rosnere10bc842010-09-07 11:40:50 +00003116 u16 mii_ctrl;
Yaniv Rosnerea4e0402008-06-23 20:27:26 -07003117 DP(NETIF_MSG_LINK, "XGXS 1G loopback enable\n");
Yaniv Rosnere10bc842010-09-07 11:40:50 +00003118 bnx2x_cl45_read(bp, phy, 5,
3119 (MDIO_REG_BANK_COMBO_IEEE0 +
3120 (MDIO_COMBO_IEEE0_MII_CONTROL & 0xf)),
3121 &mii_ctrl);
3122 bnx2x_cl45_write(bp, phy, 5,
3123 (MDIO_REG_BANK_COMBO_IEEE0 +
3124 (MDIO_COMBO_IEEE0_MII_CONTROL & 0xf)),
3125 mii_ctrl |
3126 MDIO_COMBO_IEEO_MII_CONTROL_LOOPBACK);
Yaniv Rosnerea4e0402008-06-23 20:27:26 -07003127 }
3128}
3129
Yaniv Rosner7f02c4a2010-09-07 11:41:23 +00003130u8 bnx2x_set_led(struct link_params *params,
3131 struct link_vars *vars, u8 mode, u32 speed)
Yaniv Rosnerea4e0402008-06-23 20:27:26 -07003132{
Yaniv Rosner7846e472009-11-05 19:18:07 +02003133 u8 port = params->port;
3134 u16 hw_led_mode = params->hw_led_mode;
Yaniv Rosner7f02c4a2010-09-07 11:41:23 +00003135 u8 rc = 0, phy_idx;
Eilon Greenstein345b5d52008-08-13 15:58:12 -07003136 u32 tmp;
3137 u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
Yaniv Rosner7846e472009-11-05 19:18:07 +02003138 struct bnx2x *bp = params->bp;
Yaniv Rosnerea4e0402008-06-23 20:27:26 -07003139 DP(NETIF_MSG_LINK, "bnx2x_set_led: port %x, mode %d\n", port, mode);
3140 DP(NETIF_MSG_LINK, "speed 0x%x, hw_led_mode 0x%x\n",
3141 speed, hw_led_mode);
Yaniv Rosner7f02c4a2010-09-07 11:41:23 +00003142 /* In case */
3143 for (phy_idx = EXT_PHY1; phy_idx < MAX_PHYS; phy_idx++) {
3144 if (params->phy[phy_idx].set_link_led) {
3145 params->phy[phy_idx].set_link_led(
3146 &params->phy[phy_idx], params, mode);
3147 }
3148 }
3149
Yaniv Rosnerea4e0402008-06-23 20:27:26 -07003150 switch (mode) {
Yaniv Rosner7f02c4a2010-09-07 11:41:23 +00003151 case LED_MODE_FRONT_PANEL_OFF:
Yaniv Rosnerea4e0402008-06-23 20:27:26 -07003152 case LED_MODE_OFF:
3153 REG_WR(bp, NIG_REG_LED_10G_P0 + port*4, 0);
3154 REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4,
3155 SHARED_HW_CFG_LED_MAC1);
Eilon Greenstein345b5d52008-08-13 15:58:12 -07003156
3157 tmp = EMAC_RD(bp, EMAC_REG_EMAC_LED);
Eilon Greenstein3196a882008-08-13 15:58:49 -07003158 EMAC_WR(bp, EMAC_REG_EMAC_LED, (tmp | EMAC_LED_OVERRIDE));
Yaniv Rosnerea4e0402008-06-23 20:27:26 -07003159 break;
3160
3161 case LED_MODE_OPER:
Yaniv Rosner7f02c4a2010-09-07 11:41:23 +00003162 /**
3163 * For all other phys, OPER mode is same as ON, so in case
3164 * link is down, do nothing
3165 **/
3166 if (!vars->link_up)
3167 break;
3168 case LED_MODE_ON:
Yaniv Rosner1f483532011-01-18 04:33:31 +00003169 if (params->phy[EXT_PHY1].type ==
3170 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727 &&
3171 CHIP_IS_E2(bp) && params->num_phys == 2) {
3172 /**
3173 * This is a work-around for E2+8727 Configurations
3174 */
3175 if (mode == LED_MODE_ON ||
3176 speed == SPEED_10000){
3177 REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4, 0);
3178 REG_WR(bp, NIG_REG_LED_10G_P0 + port*4, 1);
3179
3180 tmp = EMAC_RD(bp, EMAC_REG_EMAC_LED);
3181 EMAC_WR(bp, EMAC_REG_EMAC_LED,
3182 (tmp | EMAC_LED_OVERRIDE));
3183 return rc;
3184 }
3185 } else if (SINGLE_MEDIA_DIRECT(params)) {
Yaniv Rosner7f02c4a2010-09-07 11:41:23 +00003186 /**
3187 * This is a work-around for HW issue found when link
3188 * is up in CL73
3189 */
Yaniv Rosner7846e472009-11-05 19:18:07 +02003190 REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4, 0);
3191 REG_WR(bp, NIG_REG_LED_10G_P0 + port*4, 1);
3192 } else {
3193 REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4,
3194 hw_led_mode);
3195 }
3196
Yaniv Rosnerea4e0402008-06-23 20:27:26 -07003197 REG_WR(bp, NIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC_P0 +
3198 port*4, 0);
3199 /* Set blinking rate to ~15.9Hz */
3200 REG_WR(bp, NIG_REG_LED_CONTROL_BLINK_RATE_P0 + port*4,
3201 LED_BLINK_RATE_VAL);
3202 REG_WR(bp, NIG_REG_LED_CONTROL_BLINK_RATE_ENA_P0 +
3203 port*4, 1);
Eilon Greenstein345b5d52008-08-13 15:58:12 -07003204 tmp = EMAC_RD(bp, EMAC_REG_EMAC_LED);
Eilon Greenstein3196a882008-08-13 15:58:49 -07003205 EMAC_WR(bp, EMAC_REG_EMAC_LED,
Eilon Greenstein345b5d52008-08-13 15:58:12 -07003206 (tmp & (~EMAC_LED_OVERRIDE)));
3207
Yaniv Rosner7846e472009-11-05 19:18:07 +02003208 if (CHIP_IS_E1(bp) &&
Eilon Greenstein34f80b02008-06-23 20:33:01 -07003209 ((speed == SPEED_2500) ||
Yaniv Rosnerea4e0402008-06-23 20:27:26 -07003210 (speed == SPEED_1000) ||
3211 (speed == SPEED_100) ||
3212 (speed == SPEED_10))) {
3213 /* On Everest 1 Ax chip versions for speeds less than
3214 10G LED scheme is different */
3215 REG_WR(bp, NIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC_P0
3216 + port*4, 1);
3217 REG_WR(bp, NIG_REG_LED_CONTROL_TRAFFIC_P0 +
3218 port*4, 0);
3219 REG_WR(bp, NIG_REG_LED_CONTROL_BLINK_TRAFFIC_P0 +
3220 port*4, 1);
3221 }
3222 break;
3223
3224 default:
3225 rc = -EINVAL;
3226 DP(NETIF_MSG_LINK, "bnx2x_set_led: Invalid led mode %d\n",
3227 mode);
3228 break;
3229 }
3230 return rc;
3231
3232}
3233
Yaniv Rosnera22f0782010-09-07 11:41:20 +00003234/**
3235 * This function comes to reflect the actual link state read DIRECTLY from the
3236 * HW
3237 */
3238u8 bnx2x_test_link(struct link_params *params, struct link_vars *vars,
3239 u8 is_serdes)
Yaniv Rosnerea4e0402008-06-23 20:27:26 -07003240{
3241 struct bnx2x *bp = params->bp;
Yaniv Rosnerc18aa152010-09-07 11:41:07 +00003242 u16 gp_status = 0, phy_index = 0;
Yaniv Rosnera22f0782010-09-07 11:41:20 +00003243 u8 ext_phy_link_up = 0, serdes_phy_type;
3244 struct link_vars temp_vars;
Yaniv Rosnerea4e0402008-06-23 20:27:26 -07003245
Yaniv Rosnere10bc842010-09-07 11:40:50 +00003246 CL45_RD_OVER_CL22(bp, &params->phy[INT_PHY],
Yaniv Rosnerea4e0402008-06-23 20:27:26 -07003247 MDIO_REG_BANK_GP_STATUS,
3248 MDIO_GP_STATUS_TOP_AN_STATUS1,
3249 &gp_status);
3250 /* link is up only if both local phy and external phy are up */
Yaniv Rosnera22f0782010-09-07 11:41:20 +00003251 if (!(gp_status & MDIO_GP_STATUS_TOP_AN_STATUS1_LINK_STATUS))
3252 return -ESRCH;
3253
3254 switch (params->num_phys) {
3255 case 1:
3256 /* No external PHY */
3257 return 0;
3258 case 2:
3259 ext_phy_link_up = params->phy[EXT_PHY1].read_status(
3260 &params->phy[EXT_PHY1],
3261 params, &temp_vars);
3262 break;
3263 case 3: /* Dual Media */
Yaniv Rosnerc18aa152010-09-07 11:41:07 +00003264 for (phy_index = EXT_PHY1; phy_index < params->num_phys;
3265 phy_index++) {
Yaniv Rosnera22f0782010-09-07 11:41:20 +00003266 serdes_phy_type = ((params->phy[phy_index].media_type ==
3267 ETH_PHY_SFP_FIBER) ||
3268 (params->phy[phy_index].media_type ==
3269 ETH_PHY_XFP_FIBER));
3270
3271 if (is_serdes != serdes_phy_type)
3272 continue;
3273 if (params->phy[phy_index].read_status) {
3274 ext_phy_link_up |=
Yaniv Rosnerc18aa152010-09-07 11:41:07 +00003275 params->phy[phy_index].read_status(
3276 &params->phy[phy_index],
Yaniv Rosnerb7737c92010-09-07 11:40:54 +00003277 params, &temp_vars);
Yaniv Rosnera22f0782010-09-07 11:41:20 +00003278 }
Yaniv Rosnerc18aa152010-09-07 11:41:07 +00003279 }
Yaniv Rosnera22f0782010-09-07 11:41:20 +00003280 break;
Yaniv Rosnerb7737c92010-09-07 11:40:54 +00003281 }
Yaniv Rosnera22f0782010-09-07 11:41:20 +00003282 if (ext_phy_link_up)
3283 return 0;
Yaniv Rosnerea4e0402008-06-23 20:27:26 -07003284 return -ESRCH;
3285}
3286
3287static u8 bnx2x_link_initialize(struct link_params *params,
Yaniv Rosnerd90d96b2010-09-07 11:41:04 +00003288 struct link_vars *vars)
Yaniv Rosnerea4e0402008-06-23 20:27:26 -07003289{
Yaniv Rosnerea4e0402008-06-23 20:27:26 -07003290 u8 rc = 0;
Yaniv Rosnerb7737c92010-09-07 11:40:54 +00003291 u8 phy_index, non_ext_phy;
Yaniv Rosnerc18aa152010-09-07 11:41:07 +00003292 struct bnx2x *bp = params->bp;
3293 /**
3294 * In case of external phy existence, the line speed would be the
3295 * line speed linked up by the external phy. In case it is direct
3296 * only, then the line_speed during initialization will be
3297 * equal to the req_line_speed
3298 */
3299 vars->line_speed = params->phy[INT_PHY].req_line_speed;
Yaniv Rosnerea4e0402008-06-23 20:27:26 -07003300
Yaniv Rosnerc18aa152010-09-07 11:41:07 +00003301 /**
3302 * Initialize the internal phy in case this is a direct board
3303 * (no external phys), or this board has external phy which requires
3304 * to first.
3305 */
Yaniv Rosnerea4e0402008-06-23 20:27:26 -07003306
Yaniv Rosnerc18aa152010-09-07 11:41:07 +00003307 if (params->phy[INT_PHY].config_init)
3308 params->phy[INT_PHY].config_init(
3309 &params->phy[INT_PHY],
3310 params, vars);
Yaniv Rosnerea4e0402008-06-23 20:27:26 -07003311
3312 /* init ext phy and enable link state int */
Yaniv Rosnerc18aa152010-09-07 11:41:07 +00003313 non_ext_phy = (SINGLE_MEDIA_DIRECT(params) ||
Yaniv Rosnerde6eae12010-09-07 11:41:13 +00003314 (params->loopback_mode == LOOPBACK_XGXS));
Yaniv Rosner57963ed2008-08-13 15:55:28 -07003315
3316 if (non_ext_phy ||
Yaniv Rosnerc18aa152010-09-07 11:41:07 +00003317 (params->phy[EXT_PHY1].flags & FLAGS_INIT_XGXS_FIRST) ||
Eilon Greenstein8660d8c2009-03-02 08:01:02 +00003318 (params->loopback_mode == LOOPBACK_EXT_PHY)) {
Yaniv Rosnerc18aa152010-09-07 11:41:07 +00003319 struct bnx2x_phy *phy = &params->phy[INT_PHY];
Yaniv Rosnere10bc842010-09-07 11:40:50 +00003320 if (vars->line_speed == SPEED_AUTO_NEG)
Yaniv Rosnerc18aa152010-09-07 11:41:07 +00003321 bnx2x_set_parallel_detection(phy, params);
3322 bnx2x_init_internal_phy(phy, params, vars);
Yaniv Rosner57963ed2008-08-13 15:55:28 -07003323 }
3324
Yaniv Rosnerc18aa152010-09-07 11:41:07 +00003325 /* Init external phy*/
Yaniv Rosner57963ed2008-08-13 15:55:28 -07003326 if (!non_ext_phy)
Yaniv Rosnerb7737c92010-09-07 11:40:54 +00003327 for (phy_index = EXT_PHY1; phy_index < params->num_phys;
3328 phy_index++) {
Yaniv Rosnera22f0782010-09-07 11:41:20 +00003329 /**
3330 * No need to initialize second phy in case of first
3331 * phy only selection. In case of second phy, we do
3332 * need to initialize the first phy, since they are
3333 * connected.
3334 **/
3335 if (phy_index == EXT_PHY2 &&
3336 (bnx2x_phy_selection(params) ==
3337 PORT_HW_CFG_PHY_SELECTION_FIRST_PHY)) {
3338 DP(NETIF_MSG_LINK, "Not initializing"
3339 "second phy\n");
3340 continue;
3341 }
Yaniv Rosnerb7737c92010-09-07 11:40:54 +00003342 params->phy[phy_index].config_init(
3343 &params->phy[phy_index],
3344 params, vars);
3345 }
Yaniv Rosnerea4e0402008-06-23 20:27:26 -07003346
Yaniv Rosnerd90d96b2010-09-07 11:41:04 +00003347 /* Reset the interrupt indication after phy was initialized */
3348 bnx2x_bits_dis(bp, NIG_REG_STATUS_INTERRUPT_PORT0 +
3349 params->port*4,
3350 (NIG_STATUS_XGXS0_LINK10G |
3351 NIG_STATUS_XGXS0_LINK_STATUS |
3352 NIG_STATUS_SERDES0_LINK_STATUS |
3353 NIG_MASK_MI_INT));
Yaniv Rosnerea4e0402008-06-23 20:27:26 -07003354 return rc;
Yaniv Rosnerea4e0402008-06-23 20:27:26 -07003355}
3356
Yaniv Rosnerde6eae12010-09-07 11:41:13 +00003357static void bnx2x_int_link_reset(struct bnx2x_phy *phy,
3358 struct link_params *params)
Yaniv Rosnerb7737c92010-09-07 11:40:54 +00003359{
Yaniv Rosnerde6eae12010-09-07 11:41:13 +00003360 /* reset the SerDes/XGXS */
3361 REG_WR(params->bp, GRCBASE_MISC +
3362 MISC_REGISTERS_RESET_REG_3_CLEAR,
3363 (0x1ff << (params->port*16)));
Yaniv Rosnerb7737c92010-09-07 11:40:54 +00003364}
3365
3366static void bnx2x_common_ext_link_reset(struct bnx2x_phy *phy,
3367 struct link_params *params)
3368{
3369 struct bnx2x *bp = params->bp;
3370 u8 gpio_port;
3371 /* HW reset */
Dmitry Kravkovf2e08992010-10-06 03:28:26 +00003372 if (CHIP_IS_E2(bp))
3373 gpio_port = BP_PATH(bp);
3374 else
3375 gpio_port = params->port;
Yaniv Rosnerb7737c92010-09-07 11:40:54 +00003376 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1,
3377 MISC_REGISTERS_GPIO_OUTPUT_LOW,
3378 gpio_port);
3379 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
3380 MISC_REGISTERS_GPIO_OUTPUT_LOW,
3381 gpio_port);
3382 DP(NETIF_MSG_LINK, "reset external PHY\n");
3383}
3384
Yaniv Rosner57963ed2008-08-13 15:55:28 -07003385static u8 bnx2x_update_link_down(struct link_params *params,
3386 struct link_vars *vars)
3387{
3388 struct bnx2x *bp = params->bp;
3389 u8 port = params->port;
Eilon Greensteinab6ad5a2009-08-12 08:24:29 +00003390
Yaniv Rosner57963ed2008-08-13 15:55:28 -07003391 DP(NETIF_MSG_LINK, "Port %x: Link is down\n", port);
Yaniv Rosner7f02c4a2010-09-07 11:41:23 +00003392 bnx2x_set_led(params, vars, LED_MODE_OFF, 0);
Yaniv Rosner57963ed2008-08-13 15:55:28 -07003393
3394 /* indicate no mac active */
3395 vars->mac_type = MAC_TYPE_NONE;
3396
3397 /* update shared memory */
3398 vars->link_status = 0;
3399 vars->line_speed = 0;
3400 bnx2x_update_mng(params, vars->link_status);
3401
3402 /* activate nig drain */
3403 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + port*4, 1);
3404
Eilon Greenstein6c55c3cd2009-01-14 06:44:13 +00003405 /* disable emac */
3406 REG_WR(bp, NIG_REG_NIG_EMAC0_EN + port*4, 0);
3407
3408 msleep(10);
3409
Yaniv Rosner57963ed2008-08-13 15:55:28 -07003410 /* reset BigMac */
3411 bnx2x_bmac_rx_disable(bp, params->port);
3412 REG_WR(bp, GRCBASE_MISC +
3413 MISC_REGISTERS_RESET_REG_2_CLEAR,
3414 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port));
3415 return 0;
3416}
3417
3418static u8 bnx2x_update_link_up(struct link_params *params,
3419 struct link_vars *vars,
Yaniv Rosnerb7737c92010-09-07 11:40:54 +00003420 u8 link_10g)
Yaniv Rosner57963ed2008-08-13 15:55:28 -07003421{
3422 struct bnx2x *bp = params->bp;
3423 u8 port = params->port;
3424 u8 rc = 0;
Eilon Greensteinab6ad5a2009-08-12 08:24:29 +00003425
Yaniv Rosner57963ed2008-08-13 15:55:28 -07003426 vars->link_status |= LINK_STATUS_LINK_UP;
Yaniv Rosner7f02c4a2010-09-07 11:41:23 +00003427
Yaniv Rosner7aa07112010-09-07 11:41:01 +00003428 if (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX)
3429 vars->link_status |=
3430 LINK_STATUS_TX_FLOW_CONTROL_ENABLED;
3431
3432 if (vars->flow_ctrl & BNX2X_FLOW_CTRL_RX)
3433 vars->link_status |=
3434 LINK_STATUS_RX_FLOW_CONTROL_ENABLED;
Yaniv Rosner7f02c4a2010-09-07 11:41:23 +00003435
Yaniv Rosner57963ed2008-08-13 15:55:28 -07003436 if (link_10g) {
3437 bnx2x_bmac_enable(params, vars, 0);
Yaniv Rosner7f02c4a2010-09-07 11:41:23 +00003438 bnx2x_set_led(params, vars,
3439 LED_MODE_OPER, SPEED_10000);
Yaniv Rosner57963ed2008-08-13 15:55:28 -07003440 } else {
Yaniv Rosnerb7737c92010-09-07 11:40:54 +00003441 rc = bnx2x_emac_program(params, vars);
Yaniv Rosner57963ed2008-08-13 15:55:28 -07003442
Yaniv Rosner0c786f02009-11-05 19:18:32 +02003443 bnx2x_emac_enable(params, vars, 0);
3444
Yaniv Rosner57963ed2008-08-13 15:55:28 -07003445 /* AN complete? */
Yaniv Rosnere10bc842010-09-07 11:40:50 +00003446 if ((vars->link_status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE)
3447 && (!(vars->phy_flags & PHY_SGMII_FLAG)) &&
3448 SINGLE_MEDIA_DIRECT(params))
3449 bnx2x_set_gmii_tx_driver(params);
Yaniv Rosner57963ed2008-08-13 15:55:28 -07003450 }
3451
3452 /* PBF - link up */
Dmitry Kravkovf2e08992010-10-06 03:28:26 +00003453 if (!(CHIP_IS_E2(bp)))
3454 rc |= bnx2x_pbf_update(params, vars->flow_ctrl,
3455 vars->line_speed);
Yaniv Rosner57963ed2008-08-13 15:55:28 -07003456
3457 /* disable drain */
3458 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + port*4, 0);
3459
3460 /* update shared memory */
3461 bnx2x_update_mng(params, vars->link_status);
Eilon Greenstein6c55c3cd2009-01-14 06:44:13 +00003462 msleep(20);
Yaniv Rosner57963ed2008-08-13 15:55:28 -07003463 return rc;
3464}
Yaniv Rosnerb7737c92010-09-07 11:40:54 +00003465/**
3466 * The bnx2x_link_update function should be called upon link
3467 * interrupt.
3468 * Link is considered up as follows:
3469 * - DIRECT_SINGLE_MEDIA - Only XGXS link (internal link) needs
3470 * to be up
3471 * - SINGLE_MEDIA - The link between the 577xx and the external
3472 * phy (XGXS) need to up as well as the external link of the
3473 * phy (PHY_EXT1)
3474 * - DUAL_MEDIA - The link between the 577xx and the first
3475 * external phy needs to be up, and at least one of the 2
3476 * external phy link must be up.
Yaniv Rosner62b29a52010-09-07 11:40:58 +00003477 */
Yaniv Rosnerea4e0402008-06-23 20:27:26 -07003478u8 bnx2x_link_update(struct link_params *params, struct link_vars *vars)
3479{
3480 struct bnx2x *bp = params->bp;
Yaniv Rosnerb7737c92010-09-07 11:40:54 +00003481 struct link_vars phy_vars[MAX_PHYS];
Yaniv Rosnerea4e0402008-06-23 20:27:26 -07003482 u8 port = params->port;
Yaniv Rosnerb7737c92010-09-07 11:40:54 +00003483 u8 link_10g, phy_index;
3484 u8 ext_phy_link_up = 0, cur_link_up, rc = 0;
Eilon Greenstein2f904462009-08-12 08:22:16 +00003485 u8 is_mi_int = 0;
Yaniv Rosnerb7737c92010-09-07 11:40:54 +00003486 u16 ext_phy_line_speed = 0, prev_line_speed = vars->line_speed;
3487 u8 active_external_phy = INT_PHY;
3488 vars->link_status = 0;
3489 for (phy_index = INT_PHY; phy_index < params->num_phys;
3490 phy_index++) {
3491 phy_vars[phy_index].flow_ctrl = 0;
3492 phy_vars[phy_index].link_status = 0;
3493 phy_vars[phy_index].line_speed = 0;
3494 phy_vars[phy_index].duplex = DUPLEX_FULL;
3495 phy_vars[phy_index].phy_link_up = 0;
3496 phy_vars[phy_index].link_up = 0;
3497 }
Yaniv Rosnerea4e0402008-06-23 20:27:26 -07003498
3499 DP(NETIF_MSG_LINK, "port %x, XGXS?%x, int_status 0x%x\n",
Eilon Greenstein2f904462009-08-12 08:22:16 +00003500 port, (vars->phy_flags & PHY_XGXS_FLAG),
3501 REG_RD(bp, NIG_REG_STATUS_INTERRUPT_PORT0 + port*4));
Yaniv Rosnerea4e0402008-06-23 20:27:26 -07003502
Eilon Greenstein2f904462009-08-12 08:22:16 +00003503 is_mi_int = (u8)(REG_RD(bp, NIG_REG_EMAC0_STATUS_MISC_MI_INT +
3504 port*0x18) > 0);
Yaniv Rosnerea4e0402008-06-23 20:27:26 -07003505 DP(NETIF_MSG_LINK, "int_mask 0x%x MI_INT %x, SERDES_LINK %x\n",
Eilon Greenstein2f904462009-08-12 08:22:16 +00003506 REG_RD(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4),
3507 is_mi_int,
3508 REG_RD(bp,
3509 NIG_REG_SERDES0_STATUS_LINK_STATUS + port*0x3c));
Yaniv Rosnerea4e0402008-06-23 20:27:26 -07003510
3511 DP(NETIF_MSG_LINK, " 10G %x, XGXS_LINK %x\n",
3512 REG_RD(bp, NIG_REG_XGXS0_STATUS_LINK10G + port*0x68),
3513 REG_RD(bp, NIG_REG_XGXS0_STATUS_LINK_STATUS + port*0x68));
3514
Eilon Greenstein6c55c3cd2009-01-14 06:44:13 +00003515 /* disable emac */
3516 REG_WR(bp, NIG_REG_NIG_EMAC0_EN + port*4, 0);
3517
Yaniv Rosnerb7737c92010-09-07 11:40:54 +00003518 /**
3519 * Step 1:
3520 * Check external link change only for external phys, and apply
3521 * priority selection between them in case the link on both phys
3522 * is up. Note that the instead of the common vars, a temporary
3523 * vars argument is used since each phy may have different link/
3524 * speed/duplex result
3525 */
3526 for (phy_index = EXT_PHY1; phy_index < params->num_phys;
3527 phy_index++) {
3528 struct bnx2x_phy *phy = &params->phy[phy_index];
3529 if (!phy->read_status)
3530 continue;
3531 /* Read link status and params of this ext phy */
3532 cur_link_up = phy->read_status(phy, params,
3533 &phy_vars[phy_index]);
3534 if (cur_link_up) {
3535 DP(NETIF_MSG_LINK, "phy in index %d link is up\n",
3536 phy_index);
3537 } else {
3538 DP(NETIF_MSG_LINK, "phy in index %d link is down\n",
3539 phy_index);
3540 continue;
3541 }
Yaniv Rosner57963ed2008-08-13 15:55:28 -07003542
Yaniv Rosnerb7737c92010-09-07 11:40:54 +00003543 if (!ext_phy_link_up) {
3544 ext_phy_link_up = 1;
3545 active_external_phy = phy_index;
Yaniv Rosnera22f0782010-09-07 11:41:20 +00003546 } else {
3547 switch (bnx2x_phy_selection(params)) {
3548 case PORT_HW_CFG_PHY_SELECTION_HARDWARE_DEFAULT:
3549 case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY:
3550 /**
3551 * In this option, the first PHY makes sure to pass the
3552 * traffic through itself only.
3553 * Its not clear how to reset the link on the second phy
3554 **/
3555 active_external_phy = EXT_PHY1;
3556 break;
3557 case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY:
3558 /**
3559 * In this option, the first PHY makes sure to pass the
3560 * traffic through the second PHY.
3561 **/
3562 active_external_phy = EXT_PHY2;
3563 break;
3564 default:
3565 /**
3566 * Link indication on both PHYs with the following cases
3567 * is invalid:
3568 * - FIRST_PHY means that second phy wasn't initialized,
3569 * hence its link is expected to be down
3570 * - SECOND_PHY means that first phy should not be able
3571 * to link up by itself (using configuration)
3572 * - DEFAULT should be overriden during initialiazation
3573 **/
3574 DP(NETIF_MSG_LINK, "Invalid link indication"
3575 "mpc=0x%x. DISABLING LINK !!!\n",
3576 params->multi_phy_config);
3577 ext_phy_link_up = 0;
3578 break;
3579 }
Yaniv Rosnerb7737c92010-09-07 11:40:54 +00003580 }
3581 }
3582 prev_line_speed = vars->line_speed;
3583 /**
3584 * Step 2:
3585 * Read the status of the internal phy. In case of
3586 * DIRECT_SINGLE_MEDIA board, this link is the external link,
3587 * otherwise this is the link between the 577xx and the first
3588 * external phy
3589 */
3590 if (params->phy[INT_PHY].read_status)
3591 params->phy[INT_PHY].read_status(
3592 &params->phy[INT_PHY],
3593 params, vars);
3594 /**
3595 * The INT_PHY flow control reside in the vars. This include the
3596 * case where the speed or flow control are not set to AUTO.
3597 * Otherwise, the active external phy flow control result is set
3598 * to the vars. The ext_phy_line_speed is needed to check if the
3599 * speed is different between the internal phy and external phy.
3600 * This case may be result of intermediate link speed change.
3601 */
3602 if (active_external_phy > INT_PHY) {
3603 vars->flow_ctrl = phy_vars[active_external_phy].flow_ctrl;
3604 /**
3605 * Link speed is taken from the XGXS. AN and FC result from
3606 * the external phy.
3607 */
3608 vars->link_status |= phy_vars[active_external_phy].link_status;
Yaniv Rosnera22f0782010-09-07 11:41:20 +00003609
3610 /**
3611 * if active_external_phy is first PHY and link is up - disable
3612 * disable TX on second external PHY
3613 */
3614 if (active_external_phy == EXT_PHY1) {
3615 if (params->phy[EXT_PHY2].phy_specific_func) {
3616 DP(NETIF_MSG_LINK, "Disabling TX on"
3617 " EXT_PHY2\n");
3618 params->phy[EXT_PHY2].phy_specific_func(
3619 &params->phy[EXT_PHY2],
3620 params, DISABLE_TX);
3621 }
3622 }
3623
Yaniv Rosnerb7737c92010-09-07 11:40:54 +00003624 ext_phy_line_speed = phy_vars[active_external_phy].line_speed;
3625 vars->duplex = phy_vars[active_external_phy].duplex;
3626 if (params->phy[active_external_phy].supported &
3627 SUPPORTED_FIBRE)
3628 vars->link_status |= LINK_STATUS_SERDES_LINK;
3629 DP(NETIF_MSG_LINK, "Active external phy selected: %x\n",
3630 active_external_phy);
3631 }
Yaniv Rosnera22f0782010-09-07 11:41:20 +00003632
3633 for (phy_index = EXT_PHY1; phy_index < params->num_phys;
3634 phy_index++) {
3635 if (params->phy[phy_index].flags &
3636 FLAGS_REARM_LATCH_SIGNAL) {
3637 bnx2x_rearm_latch_signal(bp, port,
3638 phy_index ==
3639 active_external_phy);
3640 break;
3641 }
3642 }
Yaniv Rosnerb7737c92010-09-07 11:40:54 +00003643 DP(NETIF_MSG_LINK, "vars->flow_ctrl = 0x%x, vars->link_status = 0x%x,"
3644 " ext_phy_line_speed = %d\n", vars->flow_ctrl,
3645 vars->link_status, ext_phy_line_speed);
3646 /**
3647 * Upon link speed change set the NIG into drain mode. Comes to
3648 * deals with possible FIFO glitch due to clk change when speed
3649 * is decreased without link down indicator
3650 */
Yaniv Rosnerea4e0402008-06-23 20:27:26 -07003651
Yaniv Rosnerb7737c92010-09-07 11:40:54 +00003652 if (vars->phy_link_up) {
3653 if (!(SINGLE_MEDIA_DIRECT(params)) && ext_phy_link_up &&
3654 (ext_phy_line_speed != vars->line_speed)) {
3655 DP(NETIF_MSG_LINK, "Internal link speed %d is"
3656 " different than the external"
3657 " link speed %d\n", vars->line_speed,
3658 ext_phy_line_speed);
3659 vars->phy_link_up = 0;
3660 } else if (prev_line_speed != vars->line_speed) {
3661 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE
3662 + params->port*4, 0);
3663 msleep(1);
3664 }
3665 }
Yaniv Rosnerea4e0402008-06-23 20:27:26 -07003666
3667 /* anything 10 and over uses the bmac */
3668 link_10g = ((vars->line_speed == SPEED_10000) ||
3669 (vars->line_speed == SPEED_12000) ||
3670 (vars->line_speed == SPEED_12500) ||
3671 (vars->line_speed == SPEED_13000) ||
3672 (vars->line_speed == SPEED_15000) ||
3673 (vars->line_speed == SPEED_16000));
3674
Yaniv Rosnera22f0782010-09-07 11:41:20 +00003675 bnx2x_link_int_ack(params, vars, link_10g);
Yaniv Rosnerea4e0402008-06-23 20:27:26 -07003676
Yaniv Rosnerb7737c92010-09-07 11:40:54 +00003677 /**
3678 * In case external phy link is up, and internal link is down
3679 * (not initialized yet probably after link initialization, it
3680 * needs to be initialized.
3681 * Note that after link down-up as result of cable plug, the xgxs
3682 * link would probably become up again without the need
3683 * initialize it
3684 */
3685 if (!(SINGLE_MEDIA_DIRECT(params))) {
3686 DP(NETIF_MSG_LINK, "ext_phy_link_up = %d, int_link_up = %d,"
3687 " init_preceding = %d\n", ext_phy_link_up,
3688 vars->phy_link_up,
3689 params->phy[EXT_PHY1].flags &
3690 FLAGS_INIT_XGXS_FIRST);
3691 if (!(params->phy[EXT_PHY1].flags &
3692 FLAGS_INIT_XGXS_FIRST)
3693 && ext_phy_link_up && !vars->phy_link_up) {
3694 vars->line_speed = ext_phy_line_speed;
3695 if (vars->line_speed < SPEED_1000)
3696 vars->phy_flags |= PHY_SGMII_FLAG;
3697 else
3698 vars->phy_flags &= ~PHY_SGMII_FLAG;
3699 bnx2x_init_internal_phy(&params->phy[INT_PHY],
3700 params,
3701 vars);
3702 }
3703 }
3704 /**
3705 * Link is up only if both local phy and external phy (in case of
3706 * non-direct board) are up
3707 */
3708 vars->link_up = (vars->phy_link_up &&
3709 (ext_phy_link_up ||
3710 SINGLE_MEDIA_DIRECT(params)));
Yaniv Rosnerea4e0402008-06-23 20:27:26 -07003711
Yaniv Rosner57963ed2008-08-13 15:55:28 -07003712 if (vars->link_up)
Yaniv Rosnerb7737c92010-09-07 11:40:54 +00003713 rc = bnx2x_update_link_up(params, vars, link_10g);
Yaniv Rosner57963ed2008-08-13 15:55:28 -07003714 else
3715 rc = bnx2x_update_link_down(params, vars);
Yaniv Rosnerea4e0402008-06-23 20:27:26 -07003716
3717 return rc;
3718}
3719
Yaniv Rosnerde6eae12010-09-07 11:41:13 +00003720
3721/*****************************************************************************/
3722/* External Phy section */
3723/*****************************************************************************/
3724void bnx2x_ext_phy_hw_reset(struct bnx2x *bp, u8 port)
Yaniv Rosnerb7737c92010-09-07 11:40:54 +00003725{
Yaniv Rosnerde6eae12010-09-07 11:41:13 +00003726 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1,
3727 MISC_REGISTERS_GPIO_OUTPUT_LOW, port);
3728 msleep(1);
3729 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1,
3730 MISC_REGISTERS_GPIO_OUTPUT_HIGH, port);
Yaniv Rosnerb7737c92010-09-07 11:40:54 +00003731}
3732
Yaniv Rosnerde6eae12010-09-07 11:41:13 +00003733static void bnx2x_save_spirom_version(struct bnx2x *bp, u8 port,
3734 u32 spirom_ver, u32 ver_addr)
3735{
3736 DP(NETIF_MSG_LINK, "FW version 0x%x:0x%x for port %d\n",
3737 (u16)(spirom_ver>>16), (u16)spirom_ver, port);
3738
3739 if (ver_addr)
3740 REG_WR(bp, ver_addr, spirom_ver);
3741}
3742
3743static void bnx2x_save_bcm_spirom_ver(struct bnx2x *bp,
3744 struct bnx2x_phy *phy,
3745 u8 port)
3746{
3747 u16 fw_ver1, fw_ver2;
3748
3749 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD,
3750 MDIO_PMA_REG_ROM_VER1, &fw_ver1);
3751 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD,
3752 MDIO_PMA_REG_ROM_VER2, &fw_ver2);
3753 bnx2x_save_spirom_version(bp, port, (u32)(fw_ver1<<16 | fw_ver2),
3754 phy->ver_addr);
3755}
3756
3757static void bnx2x_ext_phy_set_pause(struct link_params *params,
3758 struct bnx2x_phy *phy,
3759 struct link_vars *vars)
3760{
3761 u16 val;
3762 struct bnx2x *bp = params->bp;
3763 /* read modify write pause advertizing */
3764 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV_PAUSE, &val);
3765
3766 val &= ~MDIO_AN_REG_ADV_PAUSE_BOTH;
3767
3768 /* Please refer to Table 28B-3 of 802.3ab-1999 spec. */
3769 bnx2x_calc_ieee_aneg_adv(phy, params, &vars->ieee_fc);
3770 if ((vars->ieee_fc &
3771 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) ==
3772 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) {
3773 val |= MDIO_AN_REG_ADV_PAUSE_ASYMMETRIC;
3774 }
3775 if ((vars->ieee_fc &
3776 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) ==
3777 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) {
3778 val |= MDIO_AN_REG_ADV_PAUSE_PAUSE;
3779 }
3780 DP(NETIF_MSG_LINK, "Ext phy AN advertize 0x%x\n", val);
3781 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV_PAUSE, val);
3782}
3783
3784static u8 bnx2x_ext_phy_resolve_fc(struct bnx2x_phy *phy,
3785 struct link_params *params,
3786 struct link_vars *vars)
3787{
3788 struct bnx2x *bp = params->bp;
3789 u16 ld_pause; /* local */
3790 u16 lp_pause; /* link partner */
3791 u16 pause_result;
3792 u8 ret = 0;
3793 /* read twice */
3794
3795 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
3796
3797 if (phy->req_flow_ctrl != BNX2X_FLOW_CTRL_AUTO)
3798 vars->flow_ctrl = phy->req_flow_ctrl;
3799 else if (phy->req_line_speed != SPEED_AUTO_NEG)
3800 vars->flow_ctrl = params->req_fc_auto_adv;
3801 else if (vars->link_status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE) {
3802 ret = 1;
3803 bnx2x_cl45_read(bp, phy,
3804 MDIO_AN_DEVAD,
3805 MDIO_AN_REG_ADV_PAUSE, &ld_pause);
3806 bnx2x_cl45_read(bp, phy,
3807 MDIO_AN_DEVAD,
3808 MDIO_AN_REG_LP_AUTO_NEG, &lp_pause);
3809 pause_result = (ld_pause &
3810 MDIO_AN_REG_ADV_PAUSE_MASK) >> 8;
3811 pause_result |= (lp_pause &
3812 MDIO_AN_REG_ADV_PAUSE_MASK) >> 10;
3813 DP(NETIF_MSG_LINK, "Ext PHY pause result 0x%x\n",
3814 pause_result);
3815 bnx2x_pause_resolve(vars, pause_result);
3816 }
3817 return ret;
3818}
3819
3820static void bnx2x_ext_phy_10G_an_resolve(struct bnx2x *bp,
3821 struct bnx2x_phy *phy,
3822 struct link_vars *vars)
3823{
3824 u16 val;
3825 bnx2x_cl45_read(bp, phy,
3826 MDIO_AN_DEVAD,
3827 MDIO_AN_REG_STATUS, &val);
3828 bnx2x_cl45_read(bp, phy,
3829 MDIO_AN_DEVAD,
3830 MDIO_AN_REG_STATUS, &val);
3831 if (val & (1<<5))
3832 vars->link_status |= LINK_STATUS_AUTO_NEGOTIATE_COMPLETE;
3833 if ((val & (1<<0)) == 0)
3834 vars->link_status |= LINK_STATUS_PARALLEL_DETECTION_USED;
3835}
3836
3837/******************************************************************/
3838/* common BCM8073/BCM8727 PHY SECTION */
3839/******************************************************************/
3840static void bnx2x_8073_resolve_fc(struct bnx2x_phy *phy,
3841 struct link_params *params,
3842 struct link_vars *vars)
3843{
3844 struct bnx2x *bp = params->bp;
3845 if (phy->req_line_speed == SPEED_10 ||
3846 phy->req_line_speed == SPEED_100) {
3847 vars->flow_ctrl = phy->req_flow_ctrl;
3848 return;
3849 }
3850
3851 if (bnx2x_ext_phy_resolve_fc(phy, params, vars) &&
3852 (vars->flow_ctrl == BNX2X_FLOW_CTRL_NONE)) {
3853 u16 pause_result;
3854 u16 ld_pause; /* local */
3855 u16 lp_pause; /* link partner */
3856 bnx2x_cl45_read(bp, phy,
3857 MDIO_AN_DEVAD,
3858 MDIO_AN_REG_CL37_FC_LD, &ld_pause);
3859
3860 bnx2x_cl45_read(bp, phy,
3861 MDIO_AN_DEVAD,
3862 MDIO_AN_REG_CL37_FC_LP, &lp_pause);
3863 pause_result = (ld_pause &
3864 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) >> 5;
3865 pause_result |= (lp_pause &
3866 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) >> 7;
3867
3868 bnx2x_pause_resolve(vars, pause_result);
3869 DP(NETIF_MSG_LINK, "Ext PHY CL37 pause result 0x%x\n",
3870 pause_result);
3871 }
3872}
Yaniv Rosner5c99274b2011-01-18 04:33:36 +00003873static u8 bnx2x_8073_8727_external_rom_boot(struct bnx2x *bp,
Yaniv Rosnerde6eae12010-09-07 11:41:13 +00003874 struct bnx2x_phy *phy,
3875 u8 port)
3876{
Yaniv Rosner5c99274b2011-01-18 04:33:36 +00003877 u32 count = 0;
3878 u16 fw_ver1, fw_msgout;
3879 u8 rc = 0;
3880
Yaniv Rosnerde6eae12010-09-07 11:41:13 +00003881 /* Boot port from external ROM */
3882 /* EDC grst */
3883 bnx2x_cl45_write(bp, phy,
3884 MDIO_PMA_DEVAD,
3885 MDIO_PMA_REG_GEN_CTRL,
3886 0x0001);
3887
3888 /* ucode reboot and rst */
3889 bnx2x_cl45_write(bp, phy,
3890 MDIO_PMA_DEVAD,
3891 MDIO_PMA_REG_GEN_CTRL,
3892 0x008c);
3893
3894 bnx2x_cl45_write(bp, phy,
3895 MDIO_PMA_DEVAD,
3896 MDIO_PMA_REG_MISC_CTRL1, 0x0001);
3897
3898 /* Reset internal microprocessor */
3899 bnx2x_cl45_write(bp, phy,
3900 MDIO_PMA_DEVAD,
3901 MDIO_PMA_REG_GEN_CTRL,
3902 MDIO_PMA_REG_GEN_CTRL_ROM_MICRO_RESET);
3903
3904 /* Release srst bit */
3905 bnx2x_cl45_write(bp, phy,
3906 MDIO_PMA_DEVAD,
3907 MDIO_PMA_REG_GEN_CTRL,
3908 MDIO_PMA_REG_GEN_CTRL_ROM_RESET_INTERNAL_MP);
3909
Yaniv Rosner5c99274b2011-01-18 04:33:36 +00003910 /* Delay 100ms per the PHY specifications */
3911 msleep(100);
3912
3913 /* 8073 sometimes taking longer to download */
3914 do {
3915 count++;
3916 if (count > 300) {
3917 DP(NETIF_MSG_LINK,
3918 "bnx2x_8073_8727_external_rom_boot port %x:"
3919 "Download failed. fw version = 0x%x\n",
3920 port, fw_ver1);
3921 rc = -EINVAL;
3922 break;
3923 }
3924
3925 bnx2x_cl45_read(bp, phy,
3926 MDIO_PMA_DEVAD,
3927 MDIO_PMA_REG_ROM_VER1, &fw_ver1);
3928 bnx2x_cl45_read(bp, phy,
3929 MDIO_PMA_DEVAD,
3930 MDIO_PMA_REG_M8051_MSGOUT_REG, &fw_msgout);
3931
3932 msleep(1);
3933 } while (fw_ver1 == 0 || fw_ver1 == 0x4321 ||
3934 ((fw_msgout & 0xff) != 0x03 && (phy->type ==
3935 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073)));
Yaniv Rosnerde6eae12010-09-07 11:41:13 +00003936
3937 /* Clear ser_boot_ctl bit */
3938 bnx2x_cl45_write(bp, phy,
3939 MDIO_PMA_DEVAD,
3940 MDIO_PMA_REG_MISC_CTRL1, 0x0000);
3941 bnx2x_save_bcm_spirom_ver(bp, phy, port);
Yaniv Rosner5c99274b2011-01-18 04:33:36 +00003942
3943 DP(NETIF_MSG_LINK,
3944 "bnx2x_8073_8727_external_rom_boot port %x:"
3945 "Download complete. fw version = 0x%x\n",
3946 port, fw_ver1);
3947
3948 return rc;
Yaniv Rosnerde6eae12010-09-07 11:41:13 +00003949}
3950
3951static void bnx2x_8073_set_xaui_low_power_mode(struct bnx2x *bp,
3952 struct bnx2x_phy *phy)
3953{
3954 u16 val;
3955 bnx2x_cl45_read(bp, phy,
3956 MDIO_PMA_DEVAD, MDIO_PMA_REG_8073_CHIP_REV, &val);
3957
3958 if (val == 0) {
3959 /* Mustn't set low power mode in 8073 A0 */
3960 return;
3961 }
3962
3963 /* Disable PLL sequencer (use read-modify-write to clear bit 13) */
3964 bnx2x_cl45_read(bp, phy,
3965 MDIO_XS_DEVAD, MDIO_XS_PLL_SEQUENCER, &val);
3966 val &= ~(1<<13);
3967 bnx2x_cl45_write(bp, phy,
3968 MDIO_XS_DEVAD, MDIO_XS_PLL_SEQUENCER, val);
3969
3970 /* PLL controls */
3971 bnx2x_cl45_write(bp, phy, MDIO_XS_DEVAD, 0x805E, 0x1077);
3972 bnx2x_cl45_write(bp, phy, MDIO_XS_DEVAD, 0x805D, 0x0000);
3973 bnx2x_cl45_write(bp, phy, MDIO_XS_DEVAD, 0x805C, 0x030B);
3974 bnx2x_cl45_write(bp, phy, MDIO_XS_DEVAD, 0x805B, 0x1240);
3975 bnx2x_cl45_write(bp, phy, MDIO_XS_DEVAD, 0x805A, 0x2490);
3976
3977 /* Tx Controls */
3978 bnx2x_cl45_write(bp, phy, MDIO_XS_DEVAD, 0x80A7, 0x0C74);
3979 bnx2x_cl45_write(bp, phy, MDIO_XS_DEVAD, 0x80A6, 0x9041);
3980 bnx2x_cl45_write(bp, phy, MDIO_XS_DEVAD, 0x80A5, 0x4640);
3981
3982 /* Rx Controls */
3983 bnx2x_cl45_write(bp, phy, MDIO_XS_DEVAD, 0x80FE, 0x01C4);
3984 bnx2x_cl45_write(bp, phy, MDIO_XS_DEVAD, 0x80FD, 0x9249);
3985 bnx2x_cl45_write(bp, phy, MDIO_XS_DEVAD, 0x80FC, 0x2015);
3986
3987 /* Enable PLL sequencer (use read-modify-write to set bit 13) */
3988 bnx2x_cl45_read(bp, phy, MDIO_XS_DEVAD, MDIO_XS_PLL_SEQUENCER, &val);
3989 val |= (1<<13);
3990 bnx2x_cl45_write(bp, phy, MDIO_XS_DEVAD, MDIO_XS_PLL_SEQUENCER, val);
3991}
3992
3993/******************************************************************/
3994/* BCM8073 PHY SECTION */
3995/******************************************************************/
3996static u8 bnx2x_8073_is_snr_needed(struct bnx2x *bp, struct bnx2x_phy *phy)
3997{
3998 /* This is only required for 8073A1, version 102 only */
3999 u16 val;
4000
4001 /* Read 8073 HW revision*/
4002 bnx2x_cl45_read(bp, phy,
4003 MDIO_PMA_DEVAD,
4004 MDIO_PMA_REG_8073_CHIP_REV, &val);
4005
4006 if (val != 1) {
4007 /* No need to workaround in 8073 A1 */
4008 return 0;
4009 }
4010
4011 bnx2x_cl45_read(bp, phy,
4012 MDIO_PMA_DEVAD,
4013 MDIO_PMA_REG_ROM_VER2, &val);
4014
4015 /* SNR should be applied only for version 0x102 */
4016 if (val != 0x102)
4017 return 0;
4018
4019 return 1;
4020}
4021
4022static u8 bnx2x_8073_xaui_wa(struct bnx2x *bp, struct bnx2x_phy *phy)
4023{
4024 u16 val, cnt, cnt1 ;
4025
4026 bnx2x_cl45_read(bp, phy,
4027 MDIO_PMA_DEVAD,
4028 MDIO_PMA_REG_8073_CHIP_REV, &val);
4029
4030 if (val > 0) {
4031 /* No need to workaround in 8073 A1 */
4032 return 0;
4033 }
4034 /* XAUI workaround in 8073 A0: */
4035
4036 /* After loading the boot ROM and restarting Autoneg,
4037 poll Dev1, Reg $C820: */
4038
4039 for (cnt = 0; cnt < 1000; cnt++) {
4040 bnx2x_cl45_read(bp, phy,
4041 MDIO_PMA_DEVAD,
4042 MDIO_PMA_REG_8073_SPEED_LINK_STATUS,
4043 &val);
4044 /* If bit [14] = 0 or bit [13] = 0, continue on with
4045 system initialization (XAUI work-around not required,
4046 as these bits indicate 2.5G or 1G link up). */
4047 if (!(val & (1<<14)) || !(val & (1<<13))) {
4048 DP(NETIF_MSG_LINK, "XAUI work-around not required\n");
4049 return 0;
4050 } else if (!(val & (1<<15))) {
4051 DP(NETIF_MSG_LINK, "clc bit 15 went off\n");
4052 /* If bit 15 is 0, then poll Dev1, Reg $C841 until
4053 it's MSB (bit 15) goes to 1 (indicating that the
4054 XAUI workaround has completed),
4055 then continue on with system initialization.*/
4056 for (cnt1 = 0; cnt1 < 1000; cnt1++) {
4057 bnx2x_cl45_read(bp, phy,
4058 MDIO_PMA_DEVAD,
4059 MDIO_PMA_REG_8073_XAUI_WA, &val);
4060 if (val & (1<<15)) {
4061 DP(NETIF_MSG_LINK,
4062 "XAUI workaround has completed\n");
4063 return 0;
4064 }
4065 msleep(3);
4066 }
4067 break;
4068 }
4069 msleep(3);
4070 }
4071 DP(NETIF_MSG_LINK, "Warning: XAUI work-around timeout !!!\n");
4072 return -EINVAL;
4073}
4074
4075static void bnx2x_807x_force_10G(struct bnx2x *bp, struct bnx2x_phy *phy)
4076{
4077 /* Force KR or KX */
4078 bnx2x_cl45_write(bp, phy,
4079 MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x2040);
4080 bnx2x_cl45_write(bp, phy,
4081 MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2, 0x000b);
4082 bnx2x_cl45_write(bp, phy,
4083 MDIO_PMA_DEVAD, MDIO_PMA_REG_BCM_CTRL, 0x0000);
4084 bnx2x_cl45_write(bp, phy,
4085 MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x0000);
4086}
4087
4088static void bnx2x_8073_set_pause_cl37(struct link_params *params,
4089 struct bnx2x_phy *phy,
4090 struct link_vars *vars)
4091{
4092 u16 cl37_val;
4093 struct bnx2x *bp = params->bp;
4094 bnx2x_cl45_read(bp, phy,
4095 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD, &cl37_val);
4096
4097 cl37_val &= ~MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH;
4098 /* Please refer to Table 28B-3 of 802.3ab-1999 spec. */
4099 bnx2x_calc_ieee_aneg_adv(phy, params, &vars->ieee_fc);
4100 if ((vars->ieee_fc &
4101 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_SYMMETRIC) ==
4102 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_SYMMETRIC) {
4103 cl37_val |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_SYMMETRIC;
4104 }
4105 if ((vars->ieee_fc &
4106 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) ==
4107 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) {
4108 cl37_val |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC;
4109 }
4110 if ((vars->ieee_fc &
4111 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) ==
4112 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) {
4113 cl37_val |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH;
4114 }
4115 DP(NETIF_MSG_LINK,
4116 "Ext phy AN advertize cl37 0x%x\n", cl37_val);
4117
4118 bnx2x_cl45_write(bp, phy,
4119 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD, cl37_val);
4120 msleep(500);
4121}
4122
4123static u8 bnx2x_8073_config_init(struct bnx2x_phy *phy,
4124 struct link_params *params,
4125 struct link_vars *vars)
4126{
4127 struct bnx2x *bp = params->bp;
4128 u16 val = 0, tmp1;
4129 u8 gpio_port;
4130 DP(NETIF_MSG_LINK, "Init 8073\n");
4131
Dmitry Kravkovf2e08992010-10-06 03:28:26 +00004132 if (CHIP_IS_E2(bp))
4133 gpio_port = BP_PATH(bp);
4134 else
4135 gpio_port = params->port;
Yaniv Rosnerde6eae12010-09-07 11:41:13 +00004136 /* Restore normal power mode*/
4137 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
4138 MISC_REGISTERS_GPIO_OUTPUT_HIGH, gpio_port);
4139
4140 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1,
4141 MISC_REGISTERS_GPIO_OUTPUT_HIGH, gpio_port);
4142
4143 /* enable LASI */
4144 bnx2x_cl45_write(bp, phy,
4145 MDIO_PMA_DEVAD, MDIO_PMA_REG_RX_ALARM_CTRL, (1<<2));
4146 bnx2x_cl45_write(bp, phy,
4147 MDIO_PMA_DEVAD, MDIO_PMA_REG_LASI_CTRL, 0x0004);
4148
4149 bnx2x_8073_set_pause_cl37(params, phy, vars);
4150
4151 bnx2x_8073_set_xaui_low_power_mode(bp, phy);
4152
4153 bnx2x_cl45_read(bp, phy,
4154 MDIO_PMA_DEVAD, MDIO_PMA_REG_M8051_MSGOUT_REG, &tmp1);
4155
4156 bnx2x_cl45_read(bp, phy,
4157 MDIO_PMA_DEVAD, MDIO_PMA_REG_RX_ALARM, &tmp1);
4158
4159 DP(NETIF_MSG_LINK, "Before rom RX_ALARM(port1): 0x%x\n", tmp1);
4160
Yaniv Rosner74d7a112011-01-18 04:33:18 +00004161 /**
4162 * If this is forced speed, set to KR or KX (all other are not
4163 * supported)
4164 */
4165 /* Swap polarity if required - Must be done only in non-1G mode */
4166 if (params->lane_config & PORT_HW_CFG_SWAP_PHY_POLARITY_ENABLED) {
4167 /* Configure the 8073 to swap _P and _N of the KR lines */
4168 DP(NETIF_MSG_LINK, "Swapping polarity for the 8073\n");
4169 /* 10G Rx/Tx and 1G Tx signal polarity swap */
4170 bnx2x_cl45_read(bp, phy,
4171 MDIO_PMA_DEVAD,
4172 MDIO_PMA_REG_8073_OPT_DIGITAL_CTRL, &val);
4173 bnx2x_cl45_write(bp, phy,
4174 MDIO_PMA_DEVAD,
4175 MDIO_PMA_REG_8073_OPT_DIGITAL_CTRL,
4176 (val | (3<<9)));
4177 }
4178
4179
Yaniv Rosnerde6eae12010-09-07 11:41:13 +00004180 /* Enable CL37 BAM */
Yaniv Rosner121839b2010-11-01 05:32:38 +00004181 if (REG_RD(bp, params->shmem_base +
4182 offsetof(struct shmem_region, dev_info.
4183 port_hw_config[params->port].default_cfg)) &
4184 PORT_HW_CFG_ENABLE_BAM_ON_KR_ENABLED) {
Yaniv Rosnerde6eae12010-09-07 11:41:13 +00004185
Yaniv Rosner121839b2010-11-01 05:32:38 +00004186 bnx2x_cl45_read(bp, phy,
4187 MDIO_AN_DEVAD,
4188 MDIO_AN_REG_8073_BAM, &val);
4189 bnx2x_cl45_write(bp, phy,
4190 MDIO_AN_DEVAD,
4191 MDIO_AN_REG_8073_BAM, val | 1);
4192 DP(NETIF_MSG_LINK, "Enable CL37 BAM on KR\n");
4193 }
Yaniv Rosnerde6eae12010-09-07 11:41:13 +00004194 if (params->loopback_mode == LOOPBACK_EXT) {
4195 bnx2x_807x_force_10G(bp, phy);
4196 DP(NETIF_MSG_LINK, "Forced speed 10G on 807X\n");
4197 return 0;
4198 } else {
4199 bnx2x_cl45_write(bp, phy,
4200 MDIO_PMA_DEVAD, MDIO_PMA_REG_BCM_CTRL, 0x0002);
4201 }
4202 if (phy->req_line_speed != SPEED_AUTO_NEG) {
4203 if (phy->req_line_speed == SPEED_10000) {
4204 val = (1<<7);
4205 } else if (phy->req_line_speed == SPEED_2500) {
4206 val = (1<<5);
4207 /* Note that 2.5G works only
4208 when used with 1G advertisment */
4209 } else
4210 val = (1<<5);
4211 } else {
4212 val = 0;
4213 if (phy->speed_cap_mask &
4214 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)
4215 val |= (1<<7);
4216
4217 /* Note that 2.5G works only when
4218 used with 1G advertisment */
4219 if (phy->speed_cap_mask &
4220 (PORT_HW_CFG_SPEED_CAPABILITY_D0_1G |
4221 PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G))
4222 val |= (1<<5);
4223 DP(NETIF_MSG_LINK, "807x autoneg val = 0x%x\n", val);
4224 }
4225
4226 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV, val);
4227 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_8073_2_5G, &tmp1);
4228
4229 if (((phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G) &&
4230 (phy->req_line_speed == SPEED_AUTO_NEG)) ||
4231 (phy->req_line_speed == SPEED_2500)) {
4232 u16 phy_ver;
4233 /* Allow 2.5G for A1 and above */
4234 bnx2x_cl45_read(bp, phy,
4235 MDIO_PMA_DEVAD, MDIO_PMA_REG_8073_CHIP_REV,
4236 &phy_ver);
4237 DP(NETIF_MSG_LINK, "Add 2.5G\n");
4238 if (phy_ver > 0)
4239 tmp1 |= 1;
4240 else
4241 tmp1 &= 0xfffe;
4242 } else {
4243 DP(NETIF_MSG_LINK, "Disable 2.5G\n");
4244 tmp1 &= 0xfffe;
4245 }
4246
4247 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_8073_2_5G, tmp1);
4248 /* Add support for CL37 (passive mode) II */
4249
4250 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD, &tmp1);
4251 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD,
4252 (tmp1 | ((phy->req_duplex == DUPLEX_FULL) ?
4253 0x20 : 0x40)));
4254
4255 /* Add support for CL37 (passive mode) III */
4256 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x1000);
4257
4258 /* The SNR will improve about 2db by changing
4259 BW and FEE main tap. Rest commands are executed
4260 after link is up*/
4261 if (bnx2x_8073_is_snr_needed(bp, phy))
4262 bnx2x_cl45_write(bp, phy,
4263 MDIO_PMA_DEVAD, MDIO_PMA_REG_EDC_FFE_MAIN,
4264 0xFB0C);
4265
4266 /* Enable FEC (Forware Error Correction) Request in the AN */
4267 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV2, &tmp1);
4268 tmp1 |= (1<<15);
4269 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV2, tmp1);
4270
4271 bnx2x_ext_phy_set_pause(params, phy, vars);
4272
4273 /* Restart autoneg */
4274 msleep(500);
4275 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x1200);
4276 DP(NETIF_MSG_LINK, "807x Autoneg Restart: Advertise 1G=%x, 10G=%x\n",
4277 ((val & (1<<5)) > 0), ((val & (1<<7)) > 0));
4278 return 0;
4279}
4280
4281static u8 bnx2x_8073_read_status(struct bnx2x_phy *phy,
4282 struct link_params *params,
4283 struct link_vars *vars)
4284{
4285 struct bnx2x *bp = params->bp;
4286 u8 link_up = 0;
4287 u16 val1, val2;
4288 u16 link_status = 0;
4289 u16 an1000_status = 0;
4290
4291 bnx2x_cl45_read(bp, phy,
4292 MDIO_PMA_DEVAD, MDIO_PMA_REG_LASI_STATUS, &val1);
4293
4294 DP(NETIF_MSG_LINK, "8703 LASI status 0x%x\n", val1);
4295
4296 /* clear the interrupt LASI status register */
4297 bnx2x_cl45_read(bp, phy,
4298 MDIO_PCS_DEVAD, MDIO_PCS_REG_STATUS, &val2);
4299 bnx2x_cl45_read(bp, phy,
4300 MDIO_PCS_DEVAD, MDIO_PCS_REG_STATUS, &val1);
4301 DP(NETIF_MSG_LINK, "807x PCS status 0x%x->0x%x\n", val2, val1);
4302 /* Clear MSG-OUT */
4303 bnx2x_cl45_read(bp, phy,
4304 MDIO_PMA_DEVAD, MDIO_PMA_REG_M8051_MSGOUT_REG, &val1);
4305
4306 /* Check the LASI */
4307 bnx2x_cl45_read(bp, phy,
4308 MDIO_PMA_DEVAD, MDIO_PMA_REG_RX_ALARM, &val2);
4309
4310 DP(NETIF_MSG_LINK, "KR 0x9003 0x%x\n", val2);
4311
4312 /* Check the link status */
4313 bnx2x_cl45_read(bp, phy,
4314 MDIO_PCS_DEVAD, MDIO_PCS_REG_STATUS, &val2);
4315 DP(NETIF_MSG_LINK, "KR PCS status 0x%x\n", val2);
4316
4317 bnx2x_cl45_read(bp, phy,
4318 MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val2);
4319 bnx2x_cl45_read(bp, phy,
4320 MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val1);
4321 link_up = ((val1 & 4) == 4);
4322 DP(NETIF_MSG_LINK, "PMA_REG_STATUS=0x%x\n", val1);
4323
4324 if (link_up &&
4325 ((phy->req_line_speed != SPEED_10000))) {
4326 if (bnx2x_8073_xaui_wa(bp, phy) != 0)
4327 return 0;
4328 }
4329 bnx2x_cl45_read(bp, phy,
4330 MDIO_AN_DEVAD, MDIO_AN_REG_LINK_STATUS, &an1000_status);
4331 bnx2x_cl45_read(bp, phy,
4332 MDIO_AN_DEVAD, MDIO_AN_REG_LINK_STATUS, &an1000_status);
4333
4334 /* Check the link status on 1.1.2 */
4335 bnx2x_cl45_read(bp, phy,
4336 MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val2);
4337 bnx2x_cl45_read(bp, phy,
4338 MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val1);
4339 DP(NETIF_MSG_LINK, "KR PMA status 0x%x->0x%x,"
4340 "an_link_status=0x%x\n", val2, val1, an1000_status);
4341
4342 link_up = (((val1 & 4) == 4) || (an1000_status & (1<<1)));
4343 if (link_up && bnx2x_8073_is_snr_needed(bp, phy)) {
4344 /* The SNR will improve about 2dbby
4345 changing the BW and FEE main tap.*/
4346 /* The 1st write to change FFE main
4347 tap is set before restart AN */
4348 /* Change PLL Bandwidth in EDC
4349 register */
4350 bnx2x_cl45_write(bp, phy,
4351 MDIO_PMA_DEVAD, MDIO_PMA_REG_PLL_BANDWIDTH,
4352 0x26BC);
4353
4354 /* Change CDR Bandwidth in EDC register */
4355 bnx2x_cl45_write(bp, phy,
4356 MDIO_PMA_DEVAD, MDIO_PMA_REG_CDR_BANDWIDTH,
4357 0x0333);
4358 }
4359 bnx2x_cl45_read(bp, phy,
4360 MDIO_PMA_DEVAD, MDIO_PMA_REG_8073_SPEED_LINK_STATUS,
4361 &link_status);
4362
4363 /* Bits 0..2 --> speed detected, bits 13..15--> link is down */
4364 if ((link_status & (1<<2)) && (!(link_status & (1<<15)))) {
4365 link_up = 1;
4366 vars->line_speed = SPEED_10000;
4367 DP(NETIF_MSG_LINK, "port %x: External link up in 10G\n",
4368 params->port);
4369 } else if ((link_status & (1<<1)) && (!(link_status & (1<<14)))) {
4370 link_up = 1;
4371 vars->line_speed = SPEED_2500;
4372 DP(NETIF_MSG_LINK, "port %x: External link up in 2.5G\n",
4373 params->port);
4374 } else if ((link_status & (1<<0)) && (!(link_status & (1<<13)))) {
4375 link_up = 1;
4376 vars->line_speed = SPEED_1000;
4377 DP(NETIF_MSG_LINK, "port %x: External link up in 1G\n",
4378 params->port);
4379 } else {
4380 link_up = 0;
4381 DP(NETIF_MSG_LINK, "port %x: External link is down\n",
4382 params->port);
4383 }
4384
4385 if (link_up) {
Yaniv Rosner74d7a112011-01-18 04:33:18 +00004386 /* Swap polarity if required */
4387 if (params->lane_config &
4388 PORT_HW_CFG_SWAP_PHY_POLARITY_ENABLED) {
4389 /* Configure the 8073 to swap P and N of the KR lines */
4390 bnx2x_cl45_read(bp, phy,
4391 MDIO_XS_DEVAD,
4392 MDIO_XS_REG_8073_RX_CTRL_PCIE, &val1);
4393 /**
4394 * Set bit 3 to invert Rx in 1G mode and clear this bit
4395 * when it`s in 10G mode.
4396 */
4397 if (vars->line_speed == SPEED_1000) {
4398 DP(NETIF_MSG_LINK, "Swapping 1G polarity for"
4399 "the 8073\n");
4400 val1 |= (1<<3);
4401 } else
4402 val1 &= ~(1<<3);
4403
4404 bnx2x_cl45_write(bp, phy,
4405 MDIO_XS_DEVAD,
4406 MDIO_XS_REG_8073_RX_CTRL_PCIE,
4407 val1);
4408 }
Yaniv Rosnerde6eae12010-09-07 11:41:13 +00004409 bnx2x_ext_phy_10G_an_resolve(bp, phy, vars);
4410 bnx2x_8073_resolve_fc(phy, params, vars);
Yaniv Rosner791f18c2011-01-18 04:33:42 +00004411 vars->duplex = DUPLEX_FULL;
Yaniv Rosnerde6eae12010-09-07 11:41:13 +00004412 }
4413 return link_up;
4414}
4415
4416static void bnx2x_8073_link_reset(struct bnx2x_phy *phy,
4417 struct link_params *params)
4418{
4419 struct bnx2x *bp = params->bp;
4420 u8 gpio_port;
Dmitry Kravkovf2e08992010-10-06 03:28:26 +00004421 if (CHIP_IS_E2(bp))
4422 gpio_port = BP_PATH(bp);
4423 else
4424 gpio_port = params->port;
Yaniv Rosnerde6eae12010-09-07 11:41:13 +00004425 DP(NETIF_MSG_LINK, "Setting 8073 port %d into low power mode\n",
4426 gpio_port);
4427 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
4428 MISC_REGISTERS_GPIO_OUTPUT_LOW,
4429 gpio_port);
4430}
4431
4432/******************************************************************/
4433/* BCM8705 PHY SECTION */
4434/******************************************************************/
4435static u8 bnx2x_8705_config_init(struct bnx2x_phy *phy,
4436 struct link_params *params,
4437 struct link_vars *vars)
4438{
4439 struct bnx2x *bp = params->bp;
4440 DP(NETIF_MSG_LINK, "init 8705\n");
4441 /* Restore normal power mode*/
4442 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
4443 MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port);
4444 /* HW reset */
4445 bnx2x_ext_phy_hw_reset(bp, params->port);
4446 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0xa040);
4447 bnx2x_wait_reset_complete(bp, phy);
4448
4449 bnx2x_cl45_write(bp, phy,
4450 MDIO_PMA_DEVAD, MDIO_PMA_REG_MISC_CTRL, 0x8288);
4451 bnx2x_cl45_write(bp, phy,
4452 MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER, 0x7fbf);
4453 bnx2x_cl45_write(bp, phy,
4454 MDIO_PMA_DEVAD, MDIO_PMA_REG_CMU_PLL_BYPASS, 0x0100);
4455 bnx2x_cl45_write(bp, phy,
4456 MDIO_WIS_DEVAD, MDIO_WIS_REG_LASI_CNTL, 0x1);
4457 /* BCM8705 doesn't have microcode, hence the 0 */
4458 bnx2x_save_spirom_version(bp, params->port, params->shmem_base, 0);
4459 return 0;
4460}
4461
4462static u8 bnx2x_8705_read_status(struct bnx2x_phy *phy,
4463 struct link_params *params,
4464 struct link_vars *vars)
4465{
4466 u8 link_up = 0;
4467 u16 val1, rx_sd;
4468 struct bnx2x *bp = params->bp;
4469 DP(NETIF_MSG_LINK, "read status 8705\n");
4470 bnx2x_cl45_read(bp, phy,
4471 MDIO_WIS_DEVAD, MDIO_WIS_REG_LASI_STATUS, &val1);
4472 DP(NETIF_MSG_LINK, "8705 LASI status 0x%x\n", val1);
4473
4474 bnx2x_cl45_read(bp, phy,
4475 MDIO_WIS_DEVAD, MDIO_WIS_REG_LASI_STATUS, &val1);
4476 DP(NETIF_MSG_LINK, "8705 LASI status 0x%x\n", val1);
4477
4478 bnx2x_cl45_read(bp, phy,
4479 MDIO_PMA_DEVAD, MDIO_PMA_REG_RX_SD, &rx_sd);
4480
4481 bnx2x_cl45_read(bp, phy,
4482 MDIO_PMA_DEVAD, 0xc809, &val1);
4483 bnx2x_cl45_read(bp, phy,
4484 MDIO_PMA_DEVAD, 0xc809, &val1);
4485
4486 DP(NETIF_MSG_LINK, "8705 1.c809 val=0x%x\n", val1);
4487 link_up = ((rx_sd & 0x1) && (val1 & (1<<9)) && ((val1 & (1<<8)) == 0));
4488 if (link_up) {
4489 vars->line_speed = SPEED_10000;
4490 bnx2x_ext_phy_resolve_fc(phy, params, vars);
4491 }
4492 return link_up;
4493}
4494
4495/******************************************************************/
4496/* SFP+ module Section */
4497/******************************************************************/
4498static void bnx2x_sfp_set_transmitter(struct bnx2x *bp,
4499 struct bnx2x_phy *phy,
4500 u8 port,
4501 u8 tx_en)
4502{
4503 u16 val;
4504
4505 DP(NETIF_MSG_LINK, "Setting transmitter tx_en=%x for port %x\n",
4506 tx_en, port);
4507 /* Disable/Enable transmitter ( TX laser of the SFP+ module.)*/
4508 bnx2x_cl45_read(bp, phy,
4509 MDIO_PMA_DEVAD,
4510 MDIO_PMA_REG_PHY_IDENTIFIER,
4511 &val);
4512
4513 if (tx_en)
4514 val &= ~(1<<15);
4515 else
4516 val |= (1<<15);
4517
4518 bnx2x_cl45_write(bp, phy,
4519 MDIO_PMA_DEVAD,
4520 MDIO_PMA_REG_PHY_IDENTIFIER,
4521 val);
4522}
4523
4524static u8 bnx2x_8726_read_sfp_module_eeprom(struct bnx2x_phy *phy,
4525 struct link_params *params,
4526 u16 addr, u8 byte_cnt, u8 *o_buf)
4527{
4528 struct bnx2x *bp = params->bp;
4529 u16 val = 0;
4530 u16 i;
4531 if (byte_cnt > 16) {
4532 DP(NETIF_MSG_LINK, "Reading from eeprom is"
4533 " is limited to 0xf\n");
4534 return -EINVAL;
4535 }
4536 /* Set the read command byte count */
4537 bnx2x_cl45_write(bp, phy,
4538 MDIO_PMA_DEVAD, MDIO_PMA_REG_SFP_TWO_WIRE_BYTE_CNT,
4539 (byte_cnt | 0xa000));
4540
4541 /* Set the read command address */
4542 bnx2x_cl45_write(bp, phy,
4543 MDIO_PMA_DEVAD, MDIO_PMA_REG_SFP_TWO_WIRE_MEM_ADDR,
4544 addr);
4545
4546 /* Activate read command */
4547 bnx2x_cl45_write(bp, phy,
4548 MDIO_PMA_DEVAD, MDIO_PMA_REG_SFP_TWO_WIRE_CTRL,
4549 0x2c0f);
4550
4551 /* Wait up to 500us for command complete status */
4552 for (i = 0; i < 100; i++) {
4553 bnx2x_cl45_read(bp, phy,
4554 MDIO_PMA_DEVAD,
4555 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, &val);
4556 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) ==
4557 MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE)
4558 break;
4559 udelay(5);
4560 }
4561
4562 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) !=
4563 MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE) {
4564 DP(NETIF_MSG_LINK,
4565 "Got bad status 0x%x when reading from SFP+ EEPROM\n",
4566 (val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK));
4567 return -EINVAL;
4568 }
4569
4570 /* Read the buffer */
4571 for (i = 0; i < byte_cnt; i++) {
4572 bnx2x_cl45_read(bp, phy,
4573 MDIO_PMA_DEVAD,
4574 MDIO_PMA_REG_8726_TWO_WIRE_DATA_BUF + i, &val);
4575 o_buf[i] = (u8)(val & MDIO_PMA_REG_8726_TWO_WIRE_DATA_MASK);
4576 }
4577
4578 for (i = 0; i < 100; i++) {
4579 bnx2x_cl45_read(bp, phy,
4580 MDIO_PMA_DEVAD,
4581 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, &val);
4582 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) ==
4583 MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_IDLE)
Joe Perches6f38ad92010-11-14 17:04:31 +00004584 return 0;
Yaniv Rosnerde6eae12010-09-07 11:41:13 +00004585 msleep(1);
4586 }
4587 return -EINVAL;
4588}
4589
4590static u8 bnx2x_8727_read_sfp_module_eeprom(struct bnx2x_phy *phy,
4591 struct link_params *params,
4592 u16 addr, u8 byte_cnt, u8 *o_buf)
4593{
4594 struct bnx2x *bp = params->bp;
4595 u16 val, i;
4596
4597 if (byte_cnt > 16) {
4598 DP(NETIF_MSG_LINK, "Reading from eeprom is"
4599 " is limited to 0xf\n");
4600 return -EINVAL;
4601 }
4602
4603 /* Need to read from 1.8000 to clear it */
4604 bnx2x_cl45_read(bp, phy,
4605 MDIO_PMA_DEVAD,
4606 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL,
4607 &val);
4608
4609 /* Set the read command byte count */
4610 bnx2x_cl45_write(bp, phy,
4611 MDIO_PMA_DEVAD,
4612 MDIO_PMA_REG_SFP_TWO_WIRE_BYTE_CNT,
4613 ((byte_cnt < 2) ? 2 : byte_cnt));
4614
4615 /* Set the read command address */
4616 bnx2x_cl45_write(bp, phy,
4617 MDIO_PMA_DEVAD,
4618 MDIO_PMA_REG_SFP_TWO_WIRE_MEM_ADDR,
4619 addr);
4620 /* Set the destination address */
4621 bnx2x_cl45_write(bp, phy,
4622 MDIO_PMA_DEVAD,
4623 0x8004,
4624 MDIO_PMA_REG_8727_TWO_WIRE_DATA_BUF);
4625
4626 /* Activate read command */
4627 bnx2x_cl45_write(bp, phy,
4628 MDIO_PMA_DEVAD,
4629 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL,
4630 0x8002);
4631 /* Wait appropriate time for two-wire command to finish before
4632 polling the status register */
4633 msleep(1);
4634
4635 /* Wait up to 500us for command complete status */
4636 for (i = 0; i < 100; i++) {
4637 bnx2x_cl45_read(bp, phy,
4638 MDIO_PMA_DEVAD,
4639 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, &val);
4640 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) ==
4641 MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE)
4642 break;
4643 udelay(5);
4644 }
4645
4646 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) !=
4647 MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE) {
4648 DP(NETIF_MSG_LINK,
4649 "Got bad status 0x%x when reading from SFP+ EEPROM\n",
4650 (val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK));
4651 return -EINVAL;
4652 }
4653
4654 /* Read the buffer */
4655 for (i = 0; i < byte_cnt; i++) {
4656 bnx2x_cl45_read(bp, phy,
4657 MDIO_PMA_DEVAD,
4658 MDIO_PMA_REG_8727_TWO_WIRE_DATA_BUF + i, &val);
4659 o_buf[i] = (u8)(val & MDIO_PMA_REG_8727_TWO_WIRE_DATA_MASK);
4660 }
4661
4662 for (i = 0; i < 100; i++) {
4663 bnx2x_cl45_read(bp, phy,
4664 MDIO_PMA_DEVAD,
4665 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, &val);
4666 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) ==
4667 MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_IDLE)
Joe Perches6f38ad92010-11-14 17:04:31 +00004668 return 0;
Yaniv Rosnerde6eae12010-09-07 11:41:13 +00004669 msleep(1);
4670 }
4671
4672 return -EINVAL;
4673}
4674
stephen hemminger8d962862010-10-21 07:50:56 +00004675static u8 bnx2x_read_sfp_module_eeprom(struct bnx2x_phy *phy,
4676 struct link_params *params, u16 addr,
4677 u8 byte_cnt, u8 *o_buf)
Yaniv Rosnerde6eae12010-09-07 11:41:13 +00004678{
4679 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726)
4680 return bnx2x_8726_read_sfp_module_eeprom(phy, params, addr,
4681 byte_cnt, o_buf);
4682 else if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727)
4683 return bnx2x_8727_read_sfp_module_eeprom(phy, params, addr,
4684 byte_cnt, o_buf);
4685 return -EINVAL;
4686}
4687
4688static u8 bnx2x_get_edc_mode(struct bnx2x_phy *phy,
4689 struct link_params *params,
4690 u16 *edc_mode)
4691{
4692 struct bnx2x *bp = params->bp;
4693 u8 val, check_limiting_mode = 0;
4694 *edc_mode = EDC_MODE_LIMITING;
4695
4696 /* First check for copper cable */
4697 if (bnx2x_read_sfp_module_eeprom(phy,
4698 params,
4699 SFP_EEPROM_CON_TYPE_ADDR,
4700 1,
4701 &val) != 0) {
4702 DP(NETIF_MSG_LINK, "Failed to read from SFP+ module EEPROM\n");
4703 return -EINVAL;
4704 }
4705
4706 switch (val) {
4707 case SFP_EEPROM_CON_TYPE_VAL_COPPER:
4708 {
4709 u8 copper_module_type;
4710
4711 /* Check if its active cable( includes SFP+ module)
4712 of passive cable*/
4713 if (bnx2x_read_sfp_module_eeprom(phy,
4714 params,
4715 SFP_EEPROM_FC_TX_TECH_ADDR,
4716 1,
4717 &copper_module_type) !=
4718 0) {
4719 DP(NETIF_MSG_LINK,
4720 "Failed to read copper-cable-type"
4721 " from SFP+ EEPROM\n");
4722 return -EINVAL;
4723 }
4724
4725 if (copper_module_type &
4726 SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_ACTIVE) {
4727 DP(NETIF_MSG_LINK, "Active Copper cable detected\n");
4728 check_limiting_mode = 1;
4729 } else if (copper_module_type &
4730 SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_PASSIVE) {
4731 DP(NETIF_MSG_LINK, "Passive Copper"
4732 " cable detected\n");
4733 *edc_mode =
4734 EDC_MODE_PASSIVE_DAC;
4735 } else {
4736 DP(NETIF_MSG_LINK, "Unknown copper-cable-"
4737 "type 0x%x !!!\n", copper_module_type);
4738 return -EINVAL;
4739 }
4740 break;
4741 }
4742 case SFP_EEPROM_CON_TYPE_VAL_LC:
4743 DP(NETIF_MSG_LINK, "Optic module detected\n");
4744 check_limiting_mode = 1;
4745 break;
4746 default:
4747 DP(NETIF_MSG_LINK, "Unable to determine module type 0x%x !!!\n",
4748 val);
4749 return -EINVAL;
4750 }
4751
4752 if (check_limiting_mode) {
4753 u8 options[SFP_EEPROM_OPTIONS_SIZE];
4754 if (bnx2x_read_sfp_module_eeprom(phy,
4755 params,
4756 SFP_EEPROM_OPTIONS_ADDR,
4757 SFP_EEPROM_OPTIONS_SIZE,
4758 options) != 0) {
4759 DP(NETIF_MSG_LINK, "Failed to read Option"
4760 " field from module EEPROM\n");
4761 return -EINVAL;
4762 }
4763 if ((options[0] & SFP_EEPROM_OPTIONS_LINEAR_RX_OUT_MASK))
4764 *edc_mode = EDC_MODE_LINEAR;
4765 else
4766 *edc_mode = EDC_MODE_LIMITING;
4767 }
4768 DP(NETIF_MSG_LINK, "EDC mode is set to 0x%x\n", *edc_mode);
4769 return 0;
4770}
4771/* This function read the relevant field from the module ( SFP+ ),
4772 and verify it is compliant with this board */
4773static u8 bnx2x_verify_sfp_module(struct bnx2x_phy *phy,
4774 struct link_params *params)
4775{
4776 struct bnx2x *bp = params->bp;
Yaniv Rosnera22f0782010-09-07 11:41:20 +00004777 u32 val, cmd;
4778 u32 fw_resp, fw_cmd_param;
Yaniv Rosnerde6eae12010-09-07 11:41:13 +00004779 char vendor_name[SFP_EEPROM_VENDOR_NAME_SIZE+1];
4780 char vendor_pn[SFP_EEPROM_PART_NO_SIZE+1];
Yaniv Rosnera22f0782010-09-07 11:41:20 +00004781 phy->flags &= ~FLAGS_SFP_NOT_APPROVED;
Yaniv Rosnerde6eae12010-09-07 11:41:13 +00004782 val = REG_RD(bp, params->shmem_base +
4783 offsetof(struct shmem_region, dev_info.
4784 port_feature_config[params->port].config));
4785 if ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) ==
4786 PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_NO_ENFORCEMENT) {
4787 DP(NETIF_MSG_LINK, "NOT enforcing module verification\n");
4788 return 0;
4789 }
4790
Yaniv Rosnera22f0782010-09-07 11:41:20 +00004791 if (params->feature_config_flags &
4792 FEATURE_CONFIG_BC_SUPPORTS_DUAL_PHY_OPT_MDL_VRFY) {
4793 /* Use specific phy request */
4794 cmd = DRV_MSG_CODE_VRFY_SPECIFIC_PHY_OPT_MDL;
4795 } else if (params->feature_config_flags &
4796 FEATURE_CONFIG_BC_SUPPORTS_OPT_MDL_VRFY) {
4797 /* Use first phy request only in case of non-dual media*/
4798 if (DUAL_MEDIA(params)) {
4799 DP(NETIF_MSG_LINK, "FW does not support OPT MDL "
4800 "verification\n");
4801 return -EINVAL;
4802 }
4803 cmd = DRV_MSG_CODE_VRFY_FIRST_PHY_OPT_MDL;
4804 } else {
4805 /* No support in OPT MDL detection */
Yaniv Rosnerde6eae12010-09-07 11:41:13 +00004806 DP(NETIF_MSG_LINK, "FW does not support OPT MDL "
Yaniv Rosnera22f0782010-09-07 11:41:20 +00004807 "verification\n");
Yaniv Rosnerde6eae12010-09-07 11:41:13 +00004808 return -EINVAL;
4809 }
Dmitry Kravkov523224a2010-10-06 03:23:26 +00004810
Yaniv Rosnera22f0782010-09-07 11:41:20 +00004811 fw_cmd_param = FW_PARAM_SET(phy->addr, phy->type, phy->mdio_ctrl);
4812 fw_resp = bnx2x_fw_command(bp, cmd, fw_cmd_param);
Yaniv Rosnerde6eae12010-09-07 11:41:13 +00004813 if (fw_resp == FW_MSG_CODE_VRFY_OPT_MDL_SUCCESS) {
4814 DP(NETIF_MSG_LINK, "Approved module\n");
4815 return 0;
4816 }
4817
4818 /* format the warning message */
4819 if (bnx2x_read_sfp_module_eeprom(phy,
4820 params,
4821 SFP_EEPROM_VENDOR_NAME_ADDR,
4822 SFP_EEPROM_VENDOR_NAME_SIZE,
4823 (u8 *)vendor_name))
4824 vendor_name[0] = '\0';
4825 else
4826 vendor_name[SFP_EEPROM_VENDOR_NAME_SIZE] = '\0';
4827 if (bnx2x_read_sfp_module_eeprom(phy,
4828 params,
4829 SFP_EEPROM_PART_NO_ADDR,
4830 SFP_EEPROM_PART_NO_SIZE,
4831 (u8 *)vendor_pn))
4832 vendor_pn[0] = '\0';
4833 else
4834 vendor_pn[SFP_EEPROM_PART_NO_SIZE] = '\0';
4835
4836 netdev_info(bp->dev, "Warning: Unqualified SFP+ module detected,"
4837 " Port %d from %s part number %s\n",
4838 params->port, vendor_name, vendor_pn);
Yaniv Rosnera22f0782010-09-07 11:41:20 +00004839 phy->flags |= FLAGS_SFP_NOT_APPROVED;
Yaniv Rosnerde6eae12010-09-07 11:41:13 +00004840 return -EINVAL;
4841}
4842
4843static u8 bnx2x_wait_for_sfp_module_initialized(struct bnx2x_phy *phy,
4844 struct link_params *params)
4845
4846{
4847 u8 val;
4848 struct bnx2x *bp = params->bp;
4849 u16 timeout;
4850 /* Initialization time after hot-plug may take up to 300ms for some
4851 phys type ( e.g. JDSU ) */
4852 for (timeout = 0; timeout < 60; timeout++) {
4853 if (bnx2x_read_sfp_module_eeprom(phy, params, 1, 1, &val)
4854 == 0) {
4855 DP(NETIF_MSG_LINK, "SFP+ module initialization "
4856 "took %d ms\n", timeout * 5);
4857 return 0;
4858 }
4859 msleep(5);
4860 }
4861 return -EINVAL;
4862}
4863
4864static void bnx2x_8727_power_module(struct bnx2x *bp,
4865 struct bnx2x_phy *phy,
4866 u8 is_power_up) {
4867 /* Make sure GPIOs are not using for LED mode */
4868 u16 val;
4869 /*
4870 * In the GPIO register, bit 4 is use to detemine if the GPIOs are
4871 * operating as INPUT or as OUTPUT. Bit 1 is for input, and 0 for
4872 * output
4873 * Bits 0-1 determine the gpios value for OUTPUT in case bit 4 val is 0
4874 * Bits 8-9 determine the gpios value for INPUT in case bit 4 val is 1
4875 * where the 1st bit is the over-current(only input), and 2nd bit is
4876 * for power( only output )
4877 */
4878
4879 /*
4880 * In case of NOC feature is disabled and power is up, set GPIO control
4881 * as input to enable listening of over-current indication
4882 */
4883 if (phy->flags & FLAGS_NOC)
4884 return;
4885 if (!(phy->flags &
4886 FLAGS_NOC) && is_power_up)
4887 val = (1<<4);
4888 else
4889 /*
4890 * Set GPIO control to OUTPUT, and set the power bit
4891 * to according to the is_power_up
4892 */
4893 val = ((!(is_power_up)) << 1);
4894
4895 bnx2x_cl45_write(bp, phy,
4896 MDIO_PMA_DEVAD,
4897 MDIO_PMA_REG_8727_GPIO_CTRL,
4898 val);
4899}
4900
4901static u8 bnx2x_8726_set_limiting_mode(struct bnx2x *bp,
4902 struct bnx2x_phy *phy,
4903 u16 edc_mode)
4904{
4905 u16 cur_limiting_mode;
4906
4907 bnx2x_cl45_read(bp, phy,
4908 MDIO_PMA_DEVAD,
4909 MDIO_PMA_REG_ROM_VER2,
4910 &cur_limiting_mode);
4911 DP(NETIF_MSG_LINK, "Current Limiting mode is 0x%x\n",
4912 cur_limiting_mode);
4913
4914 if (edc_mode == EDC_MODE_LIMITING) {
4915 DP(NETIF_MSG_LINK,
4916 "Setting LIMITING MODE\n");
4917 bnx2x_cl45_write(bp, phy,
4918 MDIO_PMA_DEVAD,
4919 MDIO_PMA_REG_ROM_VER2,
4920 EDC_MODE_LIMITING);
4921 } else { /* LRM mode ( default )*/
4922
4923 DP(NETIF_MSG_LINK, "Setting LRM MODE\n");
4924
4925 /* Changing to LRM mode takes quite few seconds.
4926 So do it only if current mode is limiting
4927 ( default is LRM )*/
4928 if (cur_limiting_mode != EDC_MODE_LIMITING)
4929 return 0;
4930
4931 bnx2x_cl45_write(bp, phy,
4932 MDIO_PMA_DEVAD,
4933 MDIO_PMA_REG_LRM_MODE,
4934 0);
4935 bnx2x_cl45_write(bp, phy,
4936 MDIO_PMA_DEVAD,
4937 MDIO_PMA_REG_ROM_VER2,
4938 0x128);
4939 bnx2x_cl45_write(bp, phy,
4940 MDIO_PMA_DEVAD,
4941 MDIO_PMA_REG_MISC_CTRL0,
4942 0x4008);
4943 bnx2x_cl45_write(bp, phy,
4944 MDIO_PMA_DEVAD,
4945 MDIO_PMA_REG_LRM_MODE,
4946 0xaaaa);
4947 }
4948 return 0;
4949}
4950
4951static u8 bnx2x_8727_set_limiting_mode(struct bnx2x *bp,
4952 struct bnx2x_phy *phy,
4953 u16 edc_mode)
4954{
4955 u16 phy_identifier;
4956 u16 rom_ver2_val;
4957 bnx2x_cl45_read(bp, phy,
4958 MDIO_PMA_DEVAD,
4959 MDIO_PMA_REG_PHY_IDENTIFIER,
4960 &phy_identifier);
4961
4962 bnx2x_cl45_write(bp, phy,
4963 MDIO_PMA_DEVAD,
4964 MDIO_PMA_REG_PHY_IDENTIFIER,
4965 (phy_identifier & ~(1<<9)));
4966
4967 bnx2x_cl45_read(bp, phy,
4968 MDIO_PMA_DEVAD,
4969 MDIO_PMA_REG_ROM_VER2,
4970 &rom_ver2_val);
4971 /* Keep the MSB 8-bits, and set the LSB 8-bits with the edc_mode */
4972 bnx2x_cl45_write(bp, phy,
4973 MDIO_PMA_DEVAD,
4974 MDIO_PMA_REG_ROM_VER2,
4975 (rom_ver2_val & 0xff00) | (edc_mode & 0x00ff));
4976
4977 bnx2x_cl45_write(bp, phy,
4978 MDIO_PMA_DEVAD,
4979 MDIO_PMA_REG_PHY_IDENTIFIER,
4980 (phy_identifier | (1<<9)));
4981
4982 return 0;
4983}
4984
Yaniv Rosnera22f0782010-09-07 11:41:20 +00004985static void bnx2x_8727_specific_func(struct bnx2x_phy *phy,
4986 struct link_params *params,
4987 u32 action)
4988{
4989 struct bnx2x *bp = params->bp;
4990
4991 switch (action) {
4992 case DISABLE_TX:
4993 bnx2x_sfp_set_transmitter(bp, phy, params->port, 0);
4994 break;
4995 case ENABLE_TX:
4996 if (!(phy->flags & FLAGS_SFP_NOT_APPROVED))
4997 bnx2x_sfp_set_transmitter(bp, phy, params->port, 1);
4998 break;
4999 default:
5000 DP(NETIF_MSG_LINK, "Function 0x%x not supported by 8727\n",
5001 action);
5002 return;
5003 }
5004}
5005
Yaniv Rosnerde6eae12010-09-07 11:41:13 +00005006static u8 bnx2x_sfp_module_detection(struct bnx2x_phy *phy,
5007 struct link_params *params)
5008{
5009 struct bnx2x *bp = params->bp;
5010 u16 edc_mode;
5011 u8 rc = 0;
5012
5013 u32 val = REG_RD(bp, params->shmem_base +
5014 offsetof(struct shmem_region, dev_info.
5015 port_feature_config[params->port].config));
5016
5017 DP(NETIF_MSG_LINK, "SFP+ module plugged in/out detected on port %d\n",
5018 params->port);
5019
5020 if (bnx2x_get_edc_mode(phy, params, &edc_mode) != 0) {
5021 DP(NETIF_MSG_LINK, "Failed to get valid module type\n");
5022 return -EINVAL;
5023 } else if (bnx2x_verify_sfp_module(phy, params) !=
5024 0) {
5025 /* check SFP+ module compatibility */
5026 DP(NETIF_MSG_LINK, "Module verification failed!!\n");
5027 rc = -EINVAL;
5028 /* Turn on fault module-detected led */
5029 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_0,
5030 MISC_REGISTERS_GPIO_HIGH,
5031 params->port);
5032 if ((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727) &&
5033 ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) ==
5034 PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_POWER_DOWN)) {
5035 /* Shutdown SFP+ module */
5036 DP(NETIF_MSG_LINK, "Shutdown SFP+ module!!\n");
5037 bnx2x_8727_power_module(bp, phy, 0);
5038 return rc;
5039 }
5040 } else {
5041 /* Turn off fault module-detected led */
5042 DP(NETIF_MSG_LINK, "Turn off fault module-detected led\n");
5043 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_0,
5044 MISC_REGISTERS_GPIO_LOW,
5045 params->port);
5046 }
5047
5048 /* power up the SFP module */
5049 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727)
5050 bnx2x_8727_power_module(bp, phy, 1);
5051
5052 /* Check and set limiting mode / LRM mode on 8726.
5053 On 8727 it is done automatically */
5054 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726)
5055 bnx2x_8726_set_limiting_mode(bp, phy, edc_mode);
5056 else
5057 bnx2x_8727_set_limiting_mode(bp, phy, edc_mode);
5058 /*
5059 * Enable transmit for this module if the module is approved, or
5060 * if unapproved modules should also enable the Tx laser
5061 */
5062 if (rc == 0 ||
5063 (val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) !=
5064 PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_DISABLE_TX_LASER)
5065 bnx2x_sfp_set_transmitter(bp, phy, params->port, 1);
5066 else
5067 bnx2x_sfp_set_transmitter(bp, phy, params->port, 0);
5068
5069 return rc;
5070}
5071
5072void bnx2x_handle_module_detect_int(struct link_params *params)
5073{
5074 struct bnx2x *bp = params->bp;
5075 struct bnx2x_phy *phy = &params->phy[EXT_PHY1];
5076 u32 gpio_val;
5077 u8 port = params->port;
5078
5079 /* Set valid module led off */
5080 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_0,
5081 MISC_REGISTERS_GPIO_HIGH,
5082 params->port);
5083
5084 /* Get current gpio val refelecting module plugged in / out*/
5085 gpio_val = bnx2x_get_gpio(bp, MISC_REGISTERS_GPIO_3, port);
5086
5087 /* Call the handling function in case module is detected */
5088 if (gpio_val == 0) {
5089
5090 bnx2x_set_gpio_int(bp, MISC_REGISTERS_GPIO_3,
5091 MISC_REGISTERS_GPIO_INT_OUTPUT_CLR,
5092 port);
5093
5094 if (bnx2x_wait_for_sfp_module_initialized(phy, params) == 0)
5095 bnx2x_sfp_module_detection(phy, params);
5096 else
5097 DP(NETIF_MSG_LINK, "SFP+ module is not initialized\n");
5098 } else {
5099 u32 val = REG_RD(bp, params->shmem_base +
5100 offsetof(struct shmem_region, dev_info.
5101 port_feature_config[params->port].
5102 config));
5103
5104 bnx2x_set_gpio_int(bp, MISC_REGISTERS_GPIO_3,
5105 MISC_REGISTERS_GPIO_INT_OUTPUT_SET,
5106 port);
5107 /* Module was plugged out. */
5108 /* Disable transmit for this module */
5109 if ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) ==
5110 PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_DISABLE_TX_LASER)
5111 bnx2x_sfp_set_transmitter(bp, phy, params->port, 0);
5112 }
5113}
5114
5115/******************************************************************/
5116/* common BCM8706/BCM8726 PHY SECTION */
5117/******************************************************************/
5118static u8 bnx2x_8706_8726_read_status(struct bnx2x_phy *phy,
5119 struct link_params *params,
5120 struct link_vars *vars)
5121{
5122 u8 link_up = 0;
5123 u16 val1, val2, rx_sd, pcs_status;
5124 struct bnx2x *bp = params->bp;
5125 DP(NETIF_MSG_LINK, "XGXS 8706/8726\n");
5126 /* Clear RX Alarm*/
5127 bnx2x_cl45_read(bp, phy,
5128 MDIO_PMA_DEVAD, MDIO_PMA_REG_RX_ALARM, &val2);
5129 /* clear LASI indication*/
5130 bnx2x_cl45_read(bp, phy,
5131 MDIO_PMA_DEVAD, MDIO_PMA_REG_LASI_STATUS, &val1);
5132 bnx2x_cl45_read(bp, phy,
5133 MDIO_PMA_DEVAD, MDIO_PMA_REG_LASI_STATUS, &val2);
5134 DP(NETIF_MSG_LINK, "8706/8726 LASI status 0x%x--> 0x%x\n", val1, val2);
5135
5136 bnx2x_cl45_read(bp, phy,
5137 MDIO_PMA_DEVAD, MDIO_PMA_REG_RX_SD, &rx_sd);
5138 bnx2x_cl45_read(bp, phy,
5139 MDIO_PCS_DEVAD, MDIO_PCS_REG_STATUS, &pcs_status);
5140 bnx2x_cl45_read(bp, phy,
5141 MDIO_AN_DEVAD, MDIO_AN_REG_LINK_STATUS, &val2);
5142 bnx2x_cl45_read(bp, phy,
5143 MDIO_AN_DEVAD, MDIO_AN_REG_LINK_STATUS, &val2);
5144
5145 DP(NETIF_MSG_LINK, "8706/8726 rx_sd 0x%x pcs_status 0x%x 1Gbps"
5146 " link_status 0x%x\n", rx_sd, pcs_status, val2);
5147 /* link is up if both bit 0 of pmd_rx_sd and
5148 * bit 0 of pcs_status are set, or if the autoneg bit
5149 * 1 is set
5150 */
5151 link_up = ((rx_sd & pcs_status & 0x1) || (val2 & (1<<1)));
5152 if (link_up) {
5153 if (val2 & (1<<1))
5154 vars->line_speed = SPEED_1000;
5155 else
5156 vars->line_speed = SPEED_10000;
5157 bnx2x_ext_phy_resolve_fc(phy, params, vars);
Yaniv Rosner791f18c2011-01-18 04:33:42 +00005158 vars->duplex = DUPLEX_FULL;
Yaniv Rosnerde6eae12010-09-07 11:41:13 +00005159 }
5160 return link_up;
5161}
5162
5163/******************************************************************/
5164/* BCM8706 PHY SECTION */
5165/******************************************************************/
5166static u8 bnx2x_8706_config_init(struct bnx2x_phy *phy,
5167 struct link_params *params,
5168 struct link_vars *vars)
5169{
5170 u16 cnt, val;
5171 struct bnx2x *bp = params->bp;
5172 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
5173 MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port);
5174 /* HW reset */
5175 bnx2x_ext_phy_hw_reset(bp, params->port);
5176 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0xa040);
5177 bnx2x_wait_reset_complete(bp, phy);
5178
5179 /* Wait until fw is loaded */
5180 for (cnt = 0; cnt < 100; cnt++) {
5181 bnx2x_cl45_read(bp, phy,
5182 MDIO_PMA_DEVAD, MDIO_PMA_REG_ROM_VER1, &val);
5183 if (val)
5184 break;
5185 msleep(10);
5186 }
5187 DP(NETIF_MSG_LINK, "XGXS 8706 is initialized after %d ms\n", cnt);
5188 if ((params->feature_config_flags &
5189 FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED)) {
5190 u8 i;
5191 u16 reg;
5192 for (i = 0; i < 4; i++) {
5193 reg = MDIO_XS_8706_REG_BANK_RX0 +
5194 i*(MDIO_XS_8706_REG_BANK_RX1 -
5195 MDIO_XS_8706_REG_BANK_RX0);
5196 bnx2x_cl45_read(bp, phy, MDIO_XS_DEVAD, reg, &val);
5197 /* Clear first 3 bits of the control */
5198 val &= ~0x7;
5199 /* Set control bits according to configuration */
5200 val |= (phy->rx_preemphasis[i] & 0x7);
5201 DP(NETIF_MSG_LINK, "Setting RX Equalizer to BCM8706"
5202 " reg 0x%x <-- val 0x%x\n", reg, val);
5203 bnx2x_cl45_write(bp, phy, MDIO_XS_DEVAD, reg, val);
5204 }
5205 }
5206 /* Force speed */
5207 if (phy->req_line_speed == SPEED_10000) {
5208 DP(NETIF_MSG_LINK, "XGXS 8706 force 10Gbps\n");
5209
5210 bnx2x_cl45_write(bp, phy,
5211 MDIO_PMA_DEVAD,
5212 MDIO_PMA_REG_DIGITAL_CTRL, 0x400);
5213 bnx2x_cl45_write(bp, phy,
5214 MDIO_PMA_DEVAD, MDIO_PMA_REG_LASI_CTRL, 1);
5215 } else {
5216 /* Force 1Gbps using autoneg with 1G advertisment */
5217
5218 /* Allow CL37 through CL73 */
5219 DP(NETIF_MSG_LINK, "XGXS 8706 AutoNeg\n");
5220 bnx2x_cl45_write(bp, phy,
5221 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_CL73, 0x040c);
5222
5223 /* Enable Full-Duplex advertisment on CL37 */
5224 bnx2x_cl45_write(bp, phy,
5225 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LP, 0x0020);
5226 /* Enable CL37 AN */
5227 bnx2x_cl45_write(bp, phy,
5228 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x1000);
5229 /* 1G support */
5230 bnx2x_cl45_write(bp, phy,
5231 MDIO_AN_DEVAD, MDIO_AN_REG_ADV, (1<<5));
5232
5233 /* Enable clause 73 AN */
5234 bnx2x_cl45_write(bp, phy,
5235 MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x1200);
5236 bnx2x_cl45_write(bp, phy,
5237 MDIO_PMA_DEVAD, MDIO_PMA_REG_RX_ALARM_CTRL,
5238 0x0400);
5239 bnx2x_cl45_write(bp, phy,
5240 MDIO_PMA_DEVAD, MDIO_PMA_REG_LASI_CTRL,
5241 0x0004);
5242 }
5243 bnx2x_save_bcm_spirom_ver(bp, phy, params->port);
5244 return 0;
5245}
5246
5247static u8 bnx2x_8706_read_status(struct bnx2x_phy *phy,
5248 struct link_params *params,
5249 struct link_vars *vars)
5250{
5251 return bnx2x_8706_8726_read_status(phy, params, vars);
5252}
5253
5254/******************************************************************/
5255/* BCM8726 PHY SECTION */
5256/******************************************************************/
5257static void bnx2x_8726_config_loopback(struct bnx2x_phy *phy,
5258 struct link_params *params)
5259{
5260 struct bnx2x *bp = params->bp;
5261 DP(NETIF_MSG_LINK, "PMA/PMD ext_phy_loopback: 8726\n");
5262 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x0001);
5263}
5264
5265static void bnx2x_8726_external_rom_boot(struct bnx2x_phy *phy,
5266 struct link_params *params)
5267{
5268 struct bnx2x *bp = params->bp;
5269 /* Need to wait 100ms after reset */
5270 msleep(100);
5271
5272 /* Micro controller re-boot */
5273 bnx2x_cl45_write(bp, phy,
5274 MDIO_PMA_DEVAD, MDIO_PMA_REG_GEN_CTRL, 0x018B);
5275
5276 /* Set soft reset */
5277 bnx2x_cl45_write(bp, phy,
5278 MDIO_PMA_DEVAD,
5279 MDIO_PMA_REG_GEN_CTRL,
5280 MDIO_PMA_REG_GEN_CTRL_ROM_MICRO_RESET);
5281
5282 bnx2x_cl45_write(bp, phy,
5283 MDIO_PMA_DEVAD,
5284 MDIO_PMA_REG_MISC_CTRL1, 0x0001);
5285
5286 bnx2x_cl45_write(bp, phy,
5287 MDIO_PMA_DEVAD,
5288 MDIO_PMA_REG_GEN_CTRL,
5289 MDIO_PMA_REG_GEN_CTRL_ROM_RESET_INTERNAL_MP);
5290
5291 /* wait for 150ms for microcode load */
5292 msleep(150);
5293
5294 /* Disable serial boot control, tristates pins SS_N, SCK, MOSI, MISO */
5295 bnx2x_cl45_write(bp, phy,
5296 MDIO_PMA_DEVAD,
5297 MDIO_PMA_REG_MISC_CTRL1, 0x0000);
5298
5299 msleep(200);
5300 bnx2x_save_bcm_spirom_ver(bp, phy, params->port);
5301}
5302
5303static u8 bnx2x_8726_read_status(struct bnx2x_phy *phy,
5304 struct link_params *params,
5305 struct link_vars *vars)
5306{
5307 struct bnx2x *bp = params->bp;
5308 u16 val1;
5309 u8 link_up = bnx2x_8706_8726_read_status(phy, params, vars);
5310 if (link_up) {
5311 bnx2x_cl45_read(bp, phy,
5312 MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER,
5313 &val1);
5314 if (val1 & (1<<15)) {
5315 DP(NETIF_MSG_LINK, "Tx is disabled\n");
5316 link_up = 0;
5317 vars->line_speed = 0;
5318 }
5319 }
5320 return link_up;
5321}
5322
5323
5324static u8 bnx2x_8726_config_init(struct bnx2x_phy *phy,
5325 struct link_params *params,
5326 struct link_vars *vars)
5327{
5328 struct bnx2x *bp = params->bp;
5329 u32 val;
5330 u32 swap_val, swap_override, aeu_gpio_mask, offset;
5331 DP(NETIF_MSG_LINK, "Initializing BCM8726\n");
5332 /* Restore normal power mode*/
5333 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
5334 MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port);
5335
5336 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1,
5337 MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port);
5338
5339 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 1<<15);
5340 bnx2x_wait_reset_complete(bp, phy);
5341
5342 bnx2x_8726_external_rom_boot(phy, params);
5343
5344 /* Need to call module detected on initialization since
5345 the module detection triggered by actual module
5346 insertion might occur before driver is loaded, and when
5347 driver is loaded, it reset all registers, including the
5348 transmitter */
5349 bnx2x_sfp_module_detection(phy, params);
5350
5351 if (phy->req_line_speed == SPEED_1000) {
5352 DP(NETIF_MSG_LINK, "Setting 1G force\n");
5353 bnx2x_cl45_write(bp, phy,
5354 MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x40);
5355 bnx2x_cl45_write(bp, phy,
5356 MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2, 0xD);
5357 bnx2x_cl45_write(bp, phy,
5358 MDIO_PMA_DEVAD, MDIO_PMA_REG_LASI_CTRL, 0x5);
5359 bnx2x_cl45_write(bp, phy,
5360 MDIO_PMA_DEVAD, MDIO_PMA_REG_RX_ALARM_CTRL,
5361 0x400);
5362 } else if ((phy->req_line_speed == SPEED_AUTO_NEG) &&
5363 (phy->speed_cap_mask &
5364 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G) &&
5365 ((phy->speed_cap_mask &
5366 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G) !=
5367 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) {
5368 DP(NETIF_MSG_LINK, "Setting 1G clause37\n");
5369 /* Set Flow control */
5370 bnx2x_ext_phy_set_pause(params, phy, vars);
5371 bnx2x_cl45_write(bp, phy,
5372 MDIO_AN_DEVAD, MDIO_AN_REG_ADV, 0x20);
5373 bnx2x_cl45_write(bp, phy,
5374 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_CL73, 0x040c);
5375 bnx2x_cl45_write(bp, phy,
5376 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD, 0x0020);
5377 bnx2x_cl45_write(bp, phy,
5378 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x1000);
5379 bnx2x_cl45_write(bp, phy,
5380 MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x1200);
5381 /* Enable RX-ALARM control to receive
5382 interrupt for 1G speed change */
5383 bnx2x_cl45_write(bp, phy,
5384 MDIO_PMA_DEVAD, MDIO_PMA_REG_LASI_CTRL, 0x4);
5385 bnx2x_cl45_write(bp, phy,
5386 MDIO_PMA_DEVAD, MDIO_PMA_REG_RX_ALARM_CTRL,
5387 0x400);
5388
5389 } else { /* Default 10G. Set only LASI control */
5390 bnx2x_cl45_write(bp, phy,
5391 MDIO_PMA_DEVAD, MDIO_PMA_REG_LASI_CTRL, 1);
5392 }
5393
5394 /* Set TX PreEmphasis if needed */
5395 if ((params->feature_config_flags &
5396 FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED)) {
5397 DP(NETIF_MSG_LINK, "Setting TX_CTRL1 0x%x,"
5398 "TX_CTRL2 0x%x\n",
5399 phy->tx_preemphasis[0],
5400 phy->tx_preemphasis[1]);
5401 bnx2x_cl45_write(bp, phy,
5402 MDIO_PMA_DEVAD,
5403 MDIO_PMA_REG_8726_TX_CTRL1,
5404 phy->tx_preemphasis[0]);
5405
5406 bnx2x_cl45_write(bp, phy,
5407 MDIO_PMA_DEVAD,
5408 MDIO_PMA_REG_8726_TX_CTRL2,
5409 phy->tx_preemphasis[1]);
5410 }
5411
5412 /* Set GPIO3 to trigger SFP+ module insertion/removal */
5413 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_3,
5414 MISC_REGISTERS_GPIO_INPUT_HI_Z, params->port);
5415
5416 /* The GPIO should be swapped if the swap register is set and active */
5417 swap_val = REG_RD(bp, NIG_REG_PORT_SWAP);
5418 swap_override = REG_RD(bp, NIG_REG_STRAP_OVERRIDE);
5419
5420 /* Select function upon port-swap configuration */
5421 if (params->port == 0) {
5422 offset = MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0;
5423 aeu_gpio_mask = (swap_val && swap_override) ?
5424 AEU_INPUTS_ATTN_BITS_GPIO3_FUNCTION_1 :
5425 AEU_INPUTS_ATTN_BITS_GPIO3_FUNCTION_0;
5426 } else {
5427 offset = MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0;
5428 aeu_gpio_mask = (swap_val && swap_override) ?
5429 AEU_INPUTS_ATTN_BITS_GPIO3_FUNCTION_0 :
5430 AEU_INPUTS_ATTN_BITS_GPIO3_FUNCTION_1;
5431 }
5432 val = REG_RD(bp, offset);
5433 /* add GPIO3 to group */
5434 val |= aeu_gpio_mask;
5435 REG_WR(bp, offset, val);
5436 return 0;
5437
5438}
5439
5440static void bnx2x_8726_link_reset(struct bnx2x_phy *phy,
5441 struct link_params *params)
5442{
5443 struct bnx2x *bp = params->bp;
5444 DP(NETIF_MSG_LINK, "bnx2x_8726_link_reset port %d\n", params->port);
5445 /* Set serial boot control for external load */
5446 bnx2x_cl45_write(bp, phy,
5447 MDIO_PMA_DEVAD,
5448 MDIO_PMA_REG_GEN_CTRL, 0x0001);
5449}
5450
5451/******************************************************************/
5452/* BCM8727 PHY SECTION */
5453/******************************************************************/
Yaniv Rosner7f02c4a2010-09-07 11:41:23 +00005454
5455static void bnx2x_8727_set_link_led(struct bnx2x_phy *phy,
5456 struct link_params *params, u8 mode)
5457{
5458 struct bnx2x *bp = params->bp;
5459 u16 led_mode_bitmask = 0;
5460 u16 gpio_pins_bitmask = 0;
5461 u16 val;
5462 /* Only NOC flavor requires to set the LED specifically */
5463 if (!(phy->flags & FLAGS_NOC))
5464 return;
5465 switch (mode) {
5466 case LED_MODE_FRONT_PANEL_OFF:
5467 case LED_MODE_OFF:
5468 led_mode_bitmask = 0;
5469 gpio_pins_bitmask = 0x03;
5470 break;
5471 case LED_MODE_ON:
5472 led_mode_bitmask = 0;
5473 gpio_pins_bitmask = 0x02;
5474 break;
5475 case LED_MODE_OPER:
5476 led_mode_bitmask = 0x60;
5477 gpio_pins_bitmask = 0x11;
5478 break;
5479 }
5480 bnx2x_cl45_read(bp, phy,
5481 MDIO_PMA_DEVAD,
5482 MDIO_PMA_REG_8727_PCS_OPT_CTRL,
5483 &val);
5484 val &= 0xff8f;
5485 val |= led_mode_bitmask;
5486 bnx2x_cl45_write(bp, phy,
5487 MDIO_PMA_DEVAD,
5488 MDIO_PMA_REG_8727_PCS_OPT_CTRL,
5489 val);
5490 bnx2x_cl45_read(bp, phy,
5491 MDIO_PMA_DEVAD,
5492 MDIO_PMA_REG_8727_GPIO_CTRL,
5493 &val);
5494 val &= 0xffe0;
5495 val |= gpio_pins_bitmask;
5496 bnx2x_cl45_write(bp, phy,
5497 MDIO_PMA_DEVAD,
5498 MDIO_PMA_REG_8727_GPIO_CTRL,
5499 val);
5500}
Yaniv Rosnerb7737c92010-09-07 11:40:54 +00005501static void bnx2x_8727_hw_reset(struct bnx2x_phy *phy,
5502 struct link_params *params) {
5503 u32 swap_val, swap_override;
5504 u8 port;
5505 /**
5506 * The PHY reset is controlled by GPIO 1. Fake the port number
5507 * to cancel the swap done in set_gpio()
5508 */
5509 struct bnx2x *bp = params->bp;
5510 swap_val = REG_RD(bp, NIG_REG_PORT_SWAP);
5511 swap_override = REG_RD(bp, NIG_REG_STRAP_OVERRIDE);
5512 port = (swap_val && swap_override) ^ 1;
5513 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1,
5514 MISC_REGISTERS_GPIO_OUTPUT_LOW, port);
5515}
5516
Yaniv Rosnerde6eae12010-09-07 11:41:13 +00005517static u8 bnx2x_8727_config_init(struct bnx2x_phy *phy,
5518 struct link_params *params,
5519 struct link_vars *vars)
5520{
5521 u16 tmp1, val, mod_abs;
5522 u16 rx_alarm_ctrl_val;
5523 u16 lasi_ctrl_val;
5524 struct bnx2x *bp = params->bp;
5525 /* Enable PMD link, MOD_ABS_FLT, and 1G link alarm */
5526
5527 bnx2x_wait_reset_complete(bp, phy);
5528 rx_alarm_ctrl_val = (1<<2) | (1<<5) ;
5529 lasi_ctrl_val = 0x0004;
5530
5531 DP(NETIF_MSG_LINK, "Initializing BCM8727\n");
5532 /* enable LASI */
5533 bnx2x_cl45_write(bp, phy,
5534 MDIO_PMA_DEVAD, MDIO_PMA_REG_RX_ALARM_CTRL,
5535 rx_alarm_ctrl_val);
5536
5537 bnx2x_cl45_write(bp, phy,
5538 MDIO_PMA_DEVAD, MDIO_PMA_REG_LASI_CTRL, lasi_ctrl_val);
5539
5540 /* Initially configure MOD_ABS to interrupt when
5541 module is presence( bit 8) */
5542 bnx2x_cl45_read(bp, phy,
5543 MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER, &mod_abs);
5544 /* Set EDC off by setting OPTXLOS signal input to low
5545 (bit 9).
5546 When the EDC is off it locks onto a reference clock and
5547 avoids becoming 'lost'.*/
Yaniv Rosner7f02c4a2010-09-07 11:41:23 +00005548 mod_abs &= ~(1<<8);
5549 if (!(phy->flags & FLAGS_NOC))
5550 mod_abs &= ~(1<<9);
Yaniv Rosnerde6eae12010-09-07 11:41:13 +00005551 bnx2x_cl45_write(bp, phy,
5552 MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER, mod_abs);
5553
5554
5555 /* Make MOD_ABS give interrupt on change */
5556 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_PCS_OPT_CTRL,
5557 &val);
5558 val |= (1<<12);
Yaniv Rosner7f02c4a2010-09-07 11:41:23 +00005559 if (phy->flags & FLAGS_NOC)
5560 val |= (3<<5);
Yaniv Rosnerde6eae12010-09-07 11:41:13 +00005561
Yaniv Rosner7f02c4a2010-09-07 11:41:23 +00005562 /**
5563 * Set 8727 GPIOs to input to allow reading from the 8727 GPIO0
5564 * status which reflect SFP+ module over-current
5565 */
5566 if (!(phy->flags & FLAGS_NOC))
5567 val &= 0xff8f; /* Reset bits 4-6 */
Yaniv Rosnerde6eae12010-09-07 11:41:13 +00005568 bnx2x_cl45_write(bp, phy,
5569 MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_PCS_OPT_CTRL, val);
5570
5571 bnx2x_8727_power_module(bp, phy, 1);
5572
5573 bnx2x_cl45_read(bp, phy,
5574 MDIO_PMA_DEVAD, MDIO_PMA_REG_M8051_MSGOUT_REG, &tmp1);
5575
5576 bnx2x_cl45_read(bp, phy,
5577 MDIO_PMA_DEVAD, MDIO_PMA_REG_RX_ALARM, &tmp1);
5578
5579 /* Set option 1G speed */
5580 if (phy->req_line_speed == SPEED_1000) {
5581 DP(NETIF_MSG_LINK, "Setting 1G force\n");
5582 bnx2x_cl45_write(bp, phy,
5583 MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x40);
5584 bnx2x_cl45_write(bp, phy,
5585 MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2, 0xD);
5586 bnx2x_cl45_read(bp, phy,
5587 MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2, &tmp1);
5588 DP(NETIF_MSG_LINK, "1.7 = 0x%x\n", tmp1);
Yaniv Rosnera22f0782010-09-07 11:41:20 +00005589 /**
5590 * Power down the XAUI until link is up in case of dual-media
5591 * and 1G
5592 */
5593 if (DUAL_MEDIA(params)) {
5594 bnx2x_cl45_read(bp, phy,
5595 MDIO_PMA_DEVAD,
5596 MDIO_PMA_REG_8727_PCS_GP, &val);
5597 val |= (3<<10);
5598 bnx2x_cl45_write(bp, phy,
5599 MDIO_PMA_DEVAD,
5600 MDIO_PMA_REG_8727_PCS_GP, val);
5601 }
Yaniv Rosnerde6eae12010-09-07 11:41:13 +00005602 } else if ((phy->req_line_speed == SPEED_AUTO_NEG) &&
5603 ((phy->speed_cap_mask &
5604 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) &&
5605 ((phy->speed_cap_mask &
5606 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G) !=
5607 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) {
5608
5609 DP(NETIF_MSG_LINK, "Setting 1G clause37\n");
5610 bnx2x_cl45_write(bp, phy,
5611 MDIO_AN_DEVAD, MDIO_AN_REG_8727_MISC_CTRL, 0);
5612 bnx2x_cl45_write(bp, phy,
5613 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x1300);
5614 } else {
5615 /**
5616 * Since the 8727 has only single reset pin, need to set the 10G
5617 * registers although it is default
5618 */
5619 bnx2x_cl45_write(bp, phy,
5620 MDIO_AN_DEVAD, MDIO_AN_REG_8727_MISC_CTRL,
5621 0x0020);
5622 bnx2x_cl45_write(bp, phy,
5623 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x0100);
5624 bnx2x_cl45_write(bp, phy,
5625 MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x2040);
5626 bnx2x_cl45_write(bp, phy,
5627 MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2,
5628 0x0008);
5629 }
5630
5631 /* Set 2-wire transfer rate of SFP+ module EEPROM
5632 * to 100Khz since some DACs(direct attached cables) do
5633 * not work at 400Khz.
5634 */
5635 bnx2x_cl45_write(bp, phy,
5636 MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_TWO_WIRE_SLAVE_ADDR,
5637 0xa001);
5638
5639 /* Set TX PreEmphasis if needed */
5640 if ((params->feature_config_flags &
5641 FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED)) {
5642 DP(NETIF_MSG_LINK, "Setting TX_CTRL1 0x%x, TX_CTRL2 0x%x\n",
5643 phy->tx_preemphasis[0],
5644 phy->tx_preemphasis[1]);
5645 bnx2x_cl45_write(bp, phy,
5646 MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_TX_CTRL1,
5647 phy->tx_preemphasis[0]);
5648
5649 bnx2x_cl45_write(bp, phy,
5650 MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_TX_CTRL2,
5651 phy->tx_preemphasis[1]);
5652 }
5653
5654 return 0;
5655}
5656
5657static void bnx2x_8727_handle_mod_abs(struct bnx2x_phy *phy,
5658 struct link_params *params)
5659{
5660 struct bnx2x *bp = params->bp;
5661 u16 mod_abs, rx_alarm_status;
5662 u32 val = REG_RD(bp, params->shmem_base +
5663 offsetof(struct shmem_region, dev_info.
5664 port_feature_config[params->port].
5665 config));
5666 bnx2x_cl45_read(bp, phy,
5667 MDIO_PMA_DEVAD,
5668 MDIO_PMA_REG_PHY_IDENTIFIER, &mod_abs);
5669 if (mod_abs & (1<<8)) {
5670
5671 /* Module is absent */
5672 DP(NETIF_MSG_LINK, "MOD_ABS indication "
5673 "show module is absent\n");
5674
5675 /* 1. Set mod_abs to detect next module
5676 presence event
5677 2. Set EDC off by setting OPTXLOS signal input to low
5678 (bit 9).
5679 When the EDC is off it locks onto a reference clock and
5680 avoids becoming 'lost'.*/
Yaniv Rosner7f02c4a2010-09-07 11:41:23 +00005681 mod_abs &= ~(1<<8);
5682 if (!(phy->flags & FLAGS_NOC))
5683 mod_abs &= ~(1<<9);
Yaniv Rosnerde6eae12010-09-07 11:41:13 +00005684 bnx2x_cl45_write(bp, phy,
5685 MDIO_PMA_DEVAD,
5686 MDIO_PMA_REG_PHY_IDENTIFIER, mod_abs);
5687
5688 /* Clear RX alarm since it stays up as long as
5689 the mod_abs wasn't changed */
5690 bnx2x_cl45_read(bp, phy,
5691 MDIO_PMA_DEVAD,
5692 MDIO_PMA_REG_RX_ALARM, &rx_alarm_status);
5693
5694 } else {
5695 /* Module is present */
5696 DP(NETIF_MSG_LINK, "MOD_ABS indication "
5697 "show module is present\n");
5698 /* First thing, disable transmitter,
5699 and if the module is ok, the
5700 module_detection will enable it*/
5701
5702 /* 1. Set mod_abs to detect next module
5703 absent event ( bit 8)
5704 2. Restore the default polarity of the OPRXLOS signal and
5705 this signal will then correctly indicate the presence or
5706 absence of the Rx signal. (bit 9) */
Yaniv Rosner7f02c4a2010-09-07 11:41:23 +00005707 mod_abs |= (1<<8);
5708 if (!(phy->flags & FLAGS_NOC))
5709 mod_abs |= (1<<9);
Yaniv Rosnerde6eae12010-09-07 11:41:13 +00005710 bnx2x_cl45_write(bp, phy,
5711 MDIO_PMA_DEVAD,
5712 MDIO_PMA_REG_PHY_IDENTIFIER, mod_abs);
5713
5714 /* Clear RX alarm since it stays up as long as
5715 the mod_abs wasn't changed. This is need to be done
5716 before calling the module detection, otherwise it will clear
5717 the link update alarm */
5718 bnx2x_cl45_read(bp, phy,
5719 MDIO_PMA_DEVAD,
5720 MDIO_PMA_REG_RX_ALARM, &rx_alarm_status);
5721
5722
5723 if ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) ==
5724 PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_DISABLE_TX_LASER)
5725 bnx2x_sfp_set_transmitter(bp, phy, params->port, 0);
5726
5727 if (bnx2x_wait_for_sfp_module_initialized(phy, params) == 0)
5728 bnx2x_sfp_module_detection(phy, params);
5729 else
5730 DP(NETIF_MSG_LINK, "SFP+ module is not initialized\n");
5731 }
5732
5733 DP(NETIF_MSG_LINK, "8727 RX_ALARM_STATUS 0x%x\n",
5734 rx_alarm_status);
5735 /* No need to check link status in case of
5736 module plugged in/out */
5737}
5738
5739static u8 bnx2x_8727_read_status(struct bnx2x_phy *phy,
5740 struct link_params *params,
5741 struct link_vars *vars)
5742
5743{
5744 struct bnx2x *bp = params->bp;
5745 u8 link_up = 0;
5746 u16 link_status = 0;
Yaniv Rosnera22f0782010-09-07 11:41:20 +00005747 u16 rx_alarm_status, lasi_ctrl, val1;
5748
5749 /* If PHY is not initialized, do not check link status */
5750 bnx2x_cl45_read(bp, phy,
5751 MDIO_PMA_DEVAD, MDIO_PMA_REG_LASI_CTRL,
5752 &lasi_ctrl);
5753 if (!lasi_ctrl)
5754 return 0;
5755
Yaniv Rosnerde6eae12010-09-07 11:41:13 +00005756 /* Check the LASI */
5757 bnx2x_cl45_read(bp, phy,
5758 MDIO_PMA_DEVAD, MDIO_PMA_REG_RX_ALARM,
5759 &rx_alarm_status);
5760 vars->line_speed = 0;
5761 DP(NETIF_MSG_LINK, "8727 RX_ALARM_STATUS 0x%x\n", rx_alarm_status);
5762
5763 bnx2x_cl45_read(bp, phy,
5764 MDIO_PMA_DEVAD, MDIO_PMA_REG_LASI_STATUS, &val1);
5765
5766 DP(NETIF_MSG_LINK, "8727 LASI status 0x%x\n", val1);
5767
5768 /* Clear MSG-OUT */
5769 bnx2x_cl45_read(bp, phy,
5770 MDIO_PMA_DEVAD, MDIO_PMA_REG_M8051_MSGOUT_REG, &val1);
5771
5772 /**
5773 * If a module is present and there is need to check
5774 * for over current
5775 */
5776 if (!(phy->flags & FLAGS_NOC) && !(rx_alarm_status & (1<<5))) {
5777 /* Check over-current using 8727 GPIO0 input*/
5778 bnx2x_cl45_read(bp, phy,
5779 MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_GPIO_CTRL,
5780 &val1);
5781
5782 if ((val1 & (1<<8)) == 0) {
5783 DP(NETIF_MSG_LINK, "8727 Power fault has been detected"
5784 " on port %d\n", params->port);
5785 netdev_err(bp->dev, "Error: Power fault on Port %d has"
5786 " been detected and the power to "
5787 "that SFP+ module has been removed"
5788 " to prevent failure of the card."
5789 " Please remove the SFP+ module and"
5790 " restart the system to clear this"
5791 " error.\n",
5792 params->port);
5793
5794 /*
5795 * Disable all RX_ALARMs except for
5796 * mod_abs
5797 */
5798 bnx2x_cl45_write(bp, phy,
5799 MDIO_PMA_DEVAD,
5800 MDIO_PMA_REG_RX_ALARM_CTRL, (1<<5));
5801
5802 bnx2x_cl45_read(bp, phy,
5803 MDIO_PMA_DEVAD,
5804 MDIO_PMA_REG_PHY_IDENTIFIER, &val1);
5805 /* Wait for module_absent_event */
5806 val1 |= (1<<8);
5807 bnx2x_cl45_write(bp, phy,
5808 MDIO_PMA_DEVAD,
5809 MDIO_PMA_REG_PHY_IDENTIFIER, val1);
5810 /* Clear RX alarm */
5811 bnx2x_cl45_read(bp, phy,
5812 MDIO_PMA_DEVAD,
5813 MDIO_PMA_REG_RX_ALARM, &rx_alarm_status);
5814 return 0;
5815 }
5816 } /* Over current check */
5817
5818 /* When module absent bit is set, check module */
5819 if (rx_alarm_status & (1<<5)) {
5820 bnx2x_8727_handle_mod_abs(phy, params);
5821 /* Enable all mod_abs and link detection bits */
5822 bnx2x_cl45_write(bp, phy,
5823 MDIO_PMA_DEVAD, MDIO_PMA_REG_RX_ALARM_CTRL,
5824 ((1<<5) | (1<<2)));
5825 }
Yaniv Rosnera22f0782010-09-07 11:41:20 +00005826 DP(NETIF_MSG_LINK, "Enabling 8727 TX laser if SFP is approved\n");
5827 bnx2x_8727_specific_func(phy, params, ENABLE_TX);
Yaniv Rosnerde6eae12010-09-07 11:41:13 +00005828 /* If transmitter is disabled, ignore false link up indication */
5829 bnx2x_cl45_read(bp, phy,
5830 MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER, &val1);
5831 if (val1 & (1<<15)) {
5832 DP(NETIF_MSG_LINK, "Tx is disabled\n");
5833 return 0;
5834 }
5835
5836 bnx2x_cl45_read(bp, phy,
5837 MDIO_PMA_DEVAD,
5838 MDIO_PMA_REG_8073_SPEED_LINK_STATUS, &link_status);
5839
5840 /* Bits 0..2 --> speed detected,
5841 bits 13..15--> link is down */
5842 if ((link_status & (1<<2)) && (!(link_status & (1<<15)))) {
5843 link_up = 1;
5844 vars->line_speed = SPEED_10000;
5845 } else if ((link_status & (1<<0)) && (!(link_status & (1<<13)))) {
5846 link_up = 1;
5847 vars->line_speed = SPEED_1000;
5848 DP(NETIF_MSG_LINK, "port %x: External link up in 1G\n",
5849 params->port);
5850 } else {
5851 link_up = 0;
5852 DP(NETIF_MSG_LINK, "port %x: External link is down\n",
5853 params->port);
5854 }
Yaniv Rosner791f18c2011-01-18 04:33:42 +00005855 if (link_up) {
Yaniv Rosnerde6eae12010-09-07 11:41:13 +00005856 bnx2x_ext_phy_resolve_fc(phy, params, vars);
Yaniv Rosner791f18c2011-01-18 04:33:42 +00005857 vars->duplex = DUPLEX_FULL;
5858 DP(NETIF_MSG_LINK, "duplex = 0x%x\n", vars->duplex);
5859 }
Yaniv Rosnera22f0782010-09-07 11:41:20 +00005860
5861 if ((DUAL_MEDIA(params)) &&
5862 (phy->req_line_speed == SPEED_1000)) {
5863 bnx2x_cl45_read(bp, phy,
5864 MDIO_PMA_DEVAD,
5865 MDIO_PMA_REG_8727_PCS_GP, &val1);
5866 /**
5867 * In case of dual-media board and 1G, power up the XAUI side,
5868 * otherwise power it down. For 10G it is done automatically
5869 */
5870 if (link_up)
5871 val1 &= ~(3<<10);
5872 else
5873 val1 |= (3<<10);
5874 bnx2x_cl45_write(bp, phy,
5875 MDIO_PMA_DEVAD,
5876 MDIO_PMA_REG_8727_PCS_GP, val1);
5877 }
Yaniv Rosnerde6eae12010-09-07 11:41:13 +00005878 return link_up;
5879}
5880
5881static void bnx2x_8727_link_reset(struct bnx2x_phy *phy,
5882 struct link_params *params)
5883{
5884 struct bnx2x *bp = params->bp;
5885 /* Disable Transmitter */
5886 bnx2x_sfp_set_transmitter(bp, phy, params->port, 0);
Yaniv Rosnera22f0782010-09-07 11:41:20 +00005887 /* Clear LASI */
5888 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_LASI_CTRL, 0);
5889
Yaniv Rosnerde6eae12010-09-07 11:41:13 +00005890}
5891
5892/******************************************************************/
5893/* BCM8481/BCM84823/BCM84833 PHY SECTION */
5894/******************************************************************/
5895static void bnx2x_save_848xx_spirom_version(struct bnx2x_phy *phy,
5896 struct link_params *params)
5897{
5898 u16 val, fw_ver1, fw_ver2, cnt;
5899 struct bnx2x *bp = params->bp;
5900
5901 /* For the 32 bits registers in 848xx, access via MDIO2ARM interface.*/
5902 /* (1) set register 0xc200_0014(SPI_BRIDGE_CTRL_2) to 0x03000000 */
5903 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA819, 0x0014);
5904 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA81A, 0xc200);
5905 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA81B, 0x0000);
5906 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA81C, 0x0300);
5907 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA817, 0x0009);
5908
5909 for (cnt = 0; cnt < 100; cnt++) {
5910 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, 0xA818, &val);
5911 if (val & 1)
5912 break;
5913 udelay(5);
5914 }
5915 if (cnt == 100) {
5916 DP(NETIF_MSG_LINK, "Unable to read 848xx phy fw version(1)\n");
5917 bnx2x_save_spirom_version(bp, params->port, 0,
5918 phy->ver_addr);
5919 return;
5920 }
5921
5922
5923 /* 2) read register 0xc200_0000 (SPI_FW_STATUS) */
5924 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA819, 0x0000);
5925 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA81A, 0xc200);
5926 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA817, 0x000A);
5927 for (cnt = 0; cnt < 100; cnt++) {
5928 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, 0xA818, &val);
5929 if (val & 1)
5930 break;
5931 udelay(5);
5932 }
5933 if (cnt == 100) {
5934 DP(NETIF_MSG_LINK, "Unable to read 848xx phy fw version(2)\n");
5935 bnx2x_save_spirom_version(bp, params->port, 0,
5936 phy->ver_addr);
5937 return;
5938 }
5939
5940 /* lower 16 bits of the register SPI_FW_STATUS */
5941 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, 0xA81B, &fw_ver1);
5942 /* upper 16 bits of register SPI_FW_STATUS */
5943 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, 0xA81C, &fw_ver2);
5944
5945 bnx2x_save_spirom_version(bp, params->port, (fw_ver2<<16) | fw_ver1,
5946 phy->ver_addr);
5947}
5948
5949static void bnx2x_848xx_set_led(struct bnx2x *bp,
5950 struct bnx2x_phy *phy)
5951{
5952 u16 val;
5953
5954 /* PHYC_CTL_LED_CTL */
5955 bnx2x_cl45_read(bp, phy,
5956 MDIO_PMA_DEVAD,
5957 MDIO_PMA_REG_8481_LINK_SIGNAL, &val);
5958 val &= 0xFE00;
5959 val |= 0x0092;
5960
5961 bnx2x_cl45_write(bp, phy,
5962 MDIO_PMA_DEVAD,
5963 MDIO_PMA_REG_8481_LINK_SIGNAL, val);
5964
5965 bnx2x_cl45_write(bp, phy,
5966 MDIO_PMA_DEVAD,
5967 MDIO_PMA_REG_8481_LED1_MASK,
5968 0x80);
5969
5970 bnx2x_cl45_write(bp, phy,
5971 MDIO_PMA_DEVAD,
5972 MDIO_PMA_REG_8481_LED2_MASK,
5973 0x18);
5974
Yaniv Rosnerf25b3c82011-01-18 04:33:47 +00005975 /* Select activity source by Tx and Rx, as suggested by PHY AE */
Yaniv Rosnerde6eae12010-09-07 11:41:13 +00005976 bnx2x_cl45_write(bp, phy,
5977 MDIO_PMA_DEVAD,
5978 MDIO_PMA_REG_8481_LED3_MASK,
Yaniv Rosnerf25b3c82011-01-18 04:33:47 +00005979 0x0006);
5980
5981 /* Select the closest activity blink rate to that in 10/100/1000 */
5982 bnx2x_cl45_write(bp, phy,
5983 MDIO_PMA_DEVAD,
5984 MDIO_PMA_REG_8481_LED3_BLINK,
5985 0);
5986
5987 bnx2x_cl45_read(bp, phy,
5988 MDIO_PMA_DEVAD,
5989 MDIO_PMA_REG_84823_CTL_LED_CTL_1, &val);
5990 val |= MDIO_PMA_REG_84823_LED3_STRETCH_EN; /* stretch_en for LED3*/
5991
5992 bnx2x_cl45_write(bp, phy,
5993 MDIO_PMA_DEVAD,
5994 MDIO_PMA_REG_84823_CTL_LED_CTL_1, val);
Yaniv Rosnerde6eae12010-09-07 11:41:13 +00005995
5996 /* 'Interrupt Mask' */
5997 bnx2x_cl45_write(bp, phy,
5998 MDIO_AN_DEVAD,
5999 0xFFFB, 0xFFFD);
6000}
6001
6002static u8 bnx2x_848xx_cmn_config_init(struct bnx2x_phy *phy,
Yaniv Rosnera22f0782010-09-07 11:41:20 +00006003 struct link_params *params,
6004 struct link_vars *vars)
Yaniv Rosnerde6eae12010-09-07 11:41:13 +00006005{
6006 struct bnx2x *bp = params->bp;
6007 u16 autoneg_val, an_1000_val, an_10_100_val;
Yaniv Rosner9bffeac2010-11-01 05:32:27 +00006008
Yaniv Rosnerde6eae12010-09-07 11:41:13 +00006009 bnx2x_bits_en(bp, NIG_REG_LATCH_BC_0 + params->port*4,
6010 1 << NIG_LATCH_BC_ENABLE_MI_INT);
6011
6012 bnx2x_cl45_write(bp, phy,
6013 MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x0000);
6014
6015 bnx2x_848xx_set_led(bp, phy);
6016
6017 /* set 1000 speed advertisement */
6018 bnx2x_cl45_read(bp, phy,
6019 MDIO_AN_DEVAD, MDIO_AN_REG_8481_1000T_CTRL,
6020 &an_1000_val);
6021
6022 bnx2x_ext_phy_set_pause(params, phy, vars);
6023 bnx2x_cl45_read(bp, phy,
6024 MDIO_AN_DEVAD,
6025 MDIO_AN_REG_8481_LEGACY_AN_ADV,
6026 &an_10_100_val);
6027 bnx2x_cl45_read(bp, phy,
6028 MDIO_AN_DEVAD, MDIO_AN_REG_8481_LEGACY_MII_CTRL,
6029 &autoneg_val);
6030 /* Disable forced speed */
6031 autoneg_val &= ~((1<<6) | (1<<8) | (1<<9) | (1<<12) | (1<<13));
6032 an_10_100_val &= ~((1<<5) | (1<<6) | (1<<7) | (1<<8));
6033
6034 if (((phy->req_line_speed == SPEED_AUTO_NEG) &&
6035 (phy->speed_cap_mask &
6036 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) ||
6037 (phy->req_line_speed == SPEED_1000)) {
6038 an_1000_val |= (1<<8);
6039 autoneg_val |= (1<<9 | 1<<12);
6040 if (phy->req_duplex == DUPLEX_FULL)
6041 an_1000_val |= (1<<9);
6042 DP(NETIF_MSG_LINK, "Advertising 1G\n");
6043 } else
6044 an_1000_val &= ~((1<<8) | (1<<9));
6045
6046 bnx2x_cl45_write(bp, phy,
6047 MDIO_AN_DEVAD, MDIO_AN_REG_8481_1000T_CTRL,
6048 an_1000_val);
6049
6050 /* set 10 speed advertisement */
6051 if (((phy->req_line_speed == SPEED_AUTO_NEG) &&
6052 (phy->speed_cap_mask &
6053 (PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL |
6054 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF)))) {
6055 an_10_100_val |= (1<<7);
6056 /* Enable autoneg and restart autoneg for legacy speeds */
6057 autoneg_val |= (1<<9 | 1<<12);
6058
6059 if (phy->req_duplex == DUPLEX_FULL)
6060 an_10_100_val |= (1<<8);
6061 DP(NETIF_MSG_LINK, "Advertising 100M\n");
6062 }
6063 /* set 10 speed advertisement */
6064 if (((phy->req_line_speed == SPEED_AUTO_NEG) &&
6065 (phy->speed_cap_mask &
6066 (PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL |
6067 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF)))) {
6068 an_10_100_val |= (1<<5);
6069 autoneg_val |= (1<<9 | 1<<12);
6070 if (phy->req_duplex == DUPLEX_FULL)
6071 an_10_100_val |= (1<<6);
6072 DP(NETIF_MSG_LINK, "Advertising 10M\n");
6073 }
6074
6075 /* Only 10/100 are allowed to work in FORCE mode */
6076 if (phy->req_line_speed == SPEED_100) {
6077 autoneg_val |= (1<<13);
6078 /* Enabled AUTO-MDIX when autoneg is disabled */
6079 bnx2x_cl45_write(bp, phy,
6080 MDIO_AN_DEVAD, MDIO_AN_REG_8481_AUX_CTRL,
6081 (1<<15 | 1<<9 | 7<<0));
6082 DP(NETIF_MSG_LINK, "Setting 100M force\n");
6083 }
6084 if (phy->req_line_speed == SPEED_10) {
6085 /* Enabled AUTO-MDIX when autoneg is disabled */
6086 bnx2x_cl45_write(bp, phy,
6087 MDIO_AN_DEVAD, MDIO_AN_REG_8481_AUX_CTRL,
6088 (1<<15 | 1<<9 | 7<<0));
6089 DP(NETIF_MSG_LINK, "Setting 10M force\n");
6090 }
6091
6092 bnx2x_cl45_write(bp, phy,
6093 MDIO_AN_DEVAD, MDIO_AN_REG_8481_LEGACY_AN_ADV,
6094 an_10_100_val);
6095
6096 if (phy->req_duplex == DUPLEX_FULL)
6097 autoneg_val |= (1<<8);
6098
6099 bnx2x_cl45_write(bp, phy,
6100 MDIO_AN_DEVAD,
6101 MDIO_AN_REG_8481_LEGACY_MII_CTRL, autoneg_val);
6102
6103 if (((phy->req_line_speed == SPEED_AUTO_NEG) &&
6104 (phy->speed_cap_mask &
6105 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) ||
6106 (phy->req_line_speed == SPEED_10000)) {
6107 DP(NETIF_MSG_LINK, "Advertising 10G\n");
6108 /* Restart autoneg for 10G*/
6109
6110 bnx2x_cl45_write(bp, phy,
6111 MDIO_AN_DEVAD, MDIO_AN_REG_CTRL,
6112 0x3200);
6113 } else if (phy->req_line_speed != SPEED_10 &&
6114 phy->req_line_speed != SPEED_100) {
6115 bnx2x_cl45_write(bp, phy,
6116 MDIO_AN_DEVAD,
6117 MDIO_AN_REG_8481_10GBASE_T_AN_CTRL,
6118 1);
6119 }
6120 /* Save spirom version */
6121 bnx2x_save_848xx_spirom_version(phy, params);
6122
6123 return 0;
6124}
6125
6126static u8 bnx2x_8481_config_init(struct bnx2x_phy *phy,
6127 struct link_params *params,
6128 struct link_vars *vars)
6129{
6130 struct bnx2x *bp = params->bp;
6131 /* Restore normal power mode*/
6132 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
6133 MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port);
6134
6135 /* HW reset */
6136 bnx2x_ext_phy_hw_reset(bp, params->port);
Yaniv Rosner9bffeac2010-11-01 05:32:27 +00006137 bnx2x_wait_reset_complete(bp, phy);
Yaniv Rosnerde6eae12010-09-07 11:41:13 +00006138
6139 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 1<<15);
6140 return bnx2x_848xx_cmn_config_init(phy, params, vars);
6141}
6142
6143static u8 bnx2x_848x3_config_init(struct bnx2x_phy *phy,
6144 struct link_params *params,
6145 struct link_vars *vars)
6146{
6147 struct bnx2x *bp = params->bp;
Yaniv Rosner6a71bbe2010-11-01 05:32:31 +00006148 u8 port, initialize = 1;
Yaniv Rosnera22f0782010-09-07 11:41:20 +00006149 u16 val;
Yaniv Rosnerde6eae12010-09-07 11:41:13 +00006150 u16 temp;
Yaniv Rosnera22f0782010-09-07 11:41:20 +00006151 u32 actual_phy_selection;
6152 u8 rc = 0;
Yaniv Rosner7f02c4a2010-09-07 11:41:23 +00006153
6154 /* This is just for MDIO_CTL_REG_84823_MEDIA register. */
6155
Yaniv Rosnerde6eae12010-09-07 11:41:13 +00006156 msleep(1);
Yaniv Rosner6a71bbe2010-11-01 05:32:31 +00006157 if (CHIP_IS_E2(bp))
6158 port = BP_PATH(bp);
6159 else
6160 port = params->port;
Yaniv Rosnerde6eae12010-09-07 11:41:13 +00006161 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_3,
6162 MISC_REGISTERS_GPIO_OUTPUT_HIGH,
Yaniv Rosner7f02c4a2010-09-07 11:41:23 +00006163 port);
Yaniv Rosner9bffeac2010-11-01 05:32:27 +00006164 bnx2x_wait_reset_complete(bp, phy);
6165 /* Wait for GPHY to come out of reset */
6166 msleep(50);
Yaniv Rosner7f02c4a2010-09-07 11:41:23 +00006167 /* BCM84823 requires that XGXS links up first @ 10G for normal
6168 behavior */
Yaniv Rosnerde6eae12010-09-07 11:41:13 +00006169 temp = vars->line_speed;
6170 vars->line_speed = SPEED_10000;
Yaniv Rosnera22f0782010-09-07 11:41:20 +00006171 bnx2x_set_autoneg(&params->phy[INT_PHY], params, vars, 0);
6172 bnx2x_program_serdes(&params->phy[INT_PHY], params, vars);
Yaniv Rosnerde6eae12010-09-07 11:41:13 +00006173 vars->line_speed = temp;
Yaniv Rosnera22f0782010-09-07 11:41:20 +00006174
6175 /* Set dual-media configuration according to configuration */
6176
6177 bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD,
6178 MDIO_CTL_REG_84823_MEDIA, &val);
6179 val &= ~(MDIO_CTL_REG_84823_MEDIA_MAC_MASK |
6180 MDIO_CTL_REG_84823_MEDIA_LINE_MASK |
6181 MDIO_CTL_REG_84823_MEDIA_COPPER_CORE_DOWN |
6182 MDIO_CTL_REG_84823_MEDIA_PRIORITY_MASK |
6183 MDIO_CTL_REG_84823_MEDIA_FIBER_1G);
6184 val |= MDIO_CTL_REG_84823_CTRL_MAC_XFI |
6185 MDIO_CTL_REG_84823_MEDIA_LINE_XAUI_L;
6186
6187 actual_phy_selection = bnx2x_phy_selection(params);
6188
6189 switch (actual_phy_selection) {
6190 case PORT_HW_CFG_PHY_SELECTION_HARDWARE_DEFAULT:
6191 /* Do nothing. Essentialy this is like the priority copper */
6192 break;
6193 case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY:
6194 val |= MDIO_CTL_REG_84823_MEDIA_PRIORITY_COPPER;
6195 break;
6196 case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY:
6197 val |= MDIO_CTL_REG_84823_MEDIA_PRIORITY_FIBER;
6198 break;
6199 case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY:
6200 /* Do nothing here. The first PHY won't be initialized at all */
6201 break;
6202 case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY:
6203 val |= MDIO_CTL_REG_84823_MEDIA_COPPER_CORE_DOWN;
6204 initialize = 0;
6205 break;
6206 }
6207 if (params->phy[EXT_PHY2].req_line_speed == SPEED_1000)
6208 val |= MDIO_CTL_REG_84823_MEDIA_FIBER_1G;
6209
6210 bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD,
6211 MDIO_CTL_REG_84823_MEDIA, val);
6212 DP(NETIF_MSG_LINK, "Multi_phy config = 0x%x, Media control = 0x%x\n",
6213 params->multi_phy_config, val);
6214
6215 if (initialize)
6216 rc = bnx2x_848xx_cmn_config_init(phy, params, vars);
6217 else
6218 bnx2x_save_848xx_spirom_version(phy, params);
6219 return rc;
Yaniv Rosnerde6eae12010-09-07 11:41:13 +00006220}
6221
6222static u8 bnx2x_848xx_read_status(struct bnx2x_phy *phy,
6223 struct link_params *params,
6224 struct link_vars *vars)
6225{
6226 struct bnx2x *bp = params->bp;
6227 u16 val, val1, val2;
6228 u8 link_up = 0;
6229
6230 /* Check 10G-BaseT link status */
6231 /* Check PMD signal ok */
6232 bnx2x_cl45_read(bp, phy,
6233 MDIO_AN_DEVAD, 0xFFFA, &val1);
6234 bnx2x_cl45_read(bp, phy,
6235 MDIO_PMA_DEVAD, MDIO_PMA_REG_8481_PMD_SIGNAL,
6236 &val2);
6237 DP(NETIF_MSG_LINK, "BCM848xx: PMD_SIGNAL 1.a811 = 0x%x\n", val2);
6238
6239 /* Check link 10G */
6240 if (val2 & (1<<11)) {
6241 vars->line_speed = SPEED_10000;
Yaniv Rosner791f18c2011-01-18 04:33:42 +00006242 vars->duplex = DUPLEX_FULL;
Yaniv Rosnerde6eae12010-09-07 11:41:13 +00006243 link_up = 1;
6244 bnx2x_ext_phy_10G_an_resolve(bp, phy, vars);
6245 } else { /* Check Legacy speed link */
6246 u16 legacy_status, legacy_speed;
6247
6248 /* Enable expansion register 0x42 (Operation mode status) */
6249 bnx2x_cl45_write(bp, phy,
6250 MDIO_AN_DEVAD,
6251 MDIO_AN_REG_8481_EXPANSION_REG_ACCESS, 0xf42);
6252
6253 /* Get legacy speed operation status */
6254 bnx2x_cl45_read(bp, phy,
6255 MDIO_AN_DEVAD,
6256 MDIO_AN_REG_8481_EXPANSION_REG_RD_RW,
6257 &legacy_status);
6258
6259 DP(NETIF_MSG_LINK, "Legacy speed status"
6260 " = 0x%x\n", legacy_status);
6261 link_up = ((legacy_status & (1<<11)) == (1<<11));
6262 if (link_up) {
6263 legacy_speed = (legacy_status & (3<<9));
6264 if (legacy_speed == (0<<9))
6265 vars->line_speed = SPEED_10;
6266 else if (legacy_speed == (1<<9))
6267 vars->line_speed = SPEED_100;
6268 else if (legacy_speed == (2<<9))
6269 vars->line_speed = SPEED_1000;
6270 else /* Should not happen */
6271 vars->line_speed = 0;
6272
6273 if (legacy_status & (1<<8))
6274 vars->duplex = DUPLEX_FULL;
6275 else
6276 vars->duplex = DUPLEX_HALF;
6277
6278 DP(NETIF_MSG_LINK, "Link is up in %dMbps,"
6279 " is_duplex_full= %d\n", vars->line_speed,
6280 (vars->duplex == DUPLEX_FULL));
6281 /* Check legacy speed AN resolution */
6282 bnx2x_cl45_read(bp, phy,
6283 MDIO_AN_DEVAD,
6284 MDIO_AN_REG_8481_LEGACY_MII_STATUS,
6285 &val);
6286 if (val & (1<<5))
6287 vars->link_status |=
6288 LINK_STATUS_AUTO_NEGOTIATE_COMPLETE;
6289 bnx2x_cl45_read(bp, phy,
6290 MDIO_AN_DEVAD,
6291 MDIO_AN_REG_8481_LEGACY_AN_EXPANSION,
6292 &val);
6293 if ((val & (1<<0)) == 0)
6294 vars->link_status |=
6295 LINK_STATUS_PARALLEL_DETECTION_USED;
6296 }
6297 }
6298 if (link_up) {
6299 DP(NETIF_MSG_LINK, "BCM84823: link speed is %d\n",
6300 vars->line_speed);
6301 bnx2x_ext_phy_resolve_fc(phy, params, vars);
6302 }
6303
6304 return link_up;
6305}
6306
6307static u8 bnx2x_848xx_format_ver(u32 raw_ver, u8 *str, u16 *len)
6308{
6309 u8 status = 0;
6310 u32 spirom_ver;
6311 spirom_ver = ((raw_ver & 0xF80) >> 7) << 16 | (raw_ver & 0x7F);
6312 status = bnx2x_format_ver(spirom_ver, str, len);
6313 return status;
6314}
6315
6316static void bnx2x_8481_hw_reset(struct bnx2x_phy *phy,
6317 struct link_params *params)
6318{
6319 bnx2x_set_gpio(params->bp, MISC_REGISTERS_GPIO_1,
6320 MISC_REGISTERS_GPIO_OUTPUT_LOW, 0);
6321 bnx2x_set_gpio(params->bp, MISC_REGISTERS_GPIO_1,
6322 MISC_REGISTERS_GPIO_OUTPUT_LOW, 1);
6323}
6324
6325static void bnx2x_8481_link_reset(struct bnx2x_phy *phy,
6326 struct link_params *params)
6327{
6328 bnx2x_cl45_write(params->bp, phy,
6329 MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x0000);
6330 bnx2x_cl45_write(params->bp, phy,
6331 MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 1);
6332}
6333
6334static void bnx2x_848x3_link_reset(struct bnx2x_phy *phy,
6335 struct link_params *params)
6336{
6337 struct bnx2x *bp = params->bp;
Yaniv Rosner6a71bbe2010-11-01 05:32:31 +00006338 u8 port;
6339 if (CHIP_IS_E2(bp))
6340 port = BP_PATH(bp);
6341 else
6342 port = params->port;
Yaniv Rosnerde6eae12010-09-07 11:41:13 +00006343 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_3,
6344 MISC_REGISTERS_GPIO_OUTPUT_LOW,
6345 port);
6346}
6347
Yaniv Rosner7f02c4a2010-09-07 11:41:23 +00006348static void bnx2x_848xx_set_link_led(struct bnx2x_phy *phy,
6349 struct link_params *params, u8 mode)
6350{
6351 struct bnx2x *bp = params->bp;
6352 u16 val;
6353
6354 switch (mode) {
6355 case LED_MODE_OFF:
6356
6357 DP(NETIF_MSG_LINK, "Port 0x%x: LED MODE OFF\n", params->port);
6358
6359 if ((params->hw_led_mode << SHARED_HW_CFG_LED_MODE_SHIFT) ==
6360 SHARED_HW_CFG_LED_EXTPHY1) {
6361
6362 /* Set LED masks */
6363 bnx2x_cl45_write(bp, phy,
6364 MDIO_PMA_DEVAD,
6365 MDIO_PMA_REG_8481_LED1_MASK,
6366 0x0);
6367
6368 bnx2x_cl45_write(bp, phy,
6369 MDIO_PMA_DEVAD,
6370 MDIO_PMA_REG_8481_LED2_MASK,
6371 0x0);
6372
6373 bnx2x_cl45_write(bp, phy,
6374 MDIO_PMA_DEVAD,
6375 MDIO_PMA_REG_8481_LED3_MASK,
6376 0x0);
6377
6378 bnx2x_cl45_write(bp, phy,
6379 MDIO_PMA_DEVAD,
6380 MDIO_PMA_REG_8481_LED5_MASK,
6381 0x0);
6382
6383 } else {
6384 bnx2x_cl45_write(bp, phy,
6385 MDIO_PMA_DEVAD,
6386 MDIO_PMA_REG_8481_LED1_MASK,
6387 0x0);
6388 }
6389 break;
6390 case LED_MODE_FRONT_PANEL_OFF:
6391
6392 DP(NETIF_MSG_LINK, "Port 0x%x: LED MODE FRONT PANEL OFF\n",
6393 params->port);
6394
6395 if ((params->hw_led_mode << SHARED_HW_CFG_LED_MODE_SHIFT) ==
6396 SHARED_HW_CFG_LED_EXTPHY1) {
6397
6398 /* Set LED masks */
6399 bnx2x_cl45_write(bp, phy,
6400 MDIO_PMA_DEVAD,
6401 MDIO_PMA_REG_8481_LED1_MASK,
6402 0x0);
6403
6404 bnx2x_cl45_write(bp, phy,
6405 MDIO_PMA_DEVAD,
6406 MDIO_PMA_REG_8481_LED2_MASK,
6407 0x0);
6408
6409 bnx2x_cl45_write(bp, phy,
6410 MDIO_PMA_DEVAD,
6411 MDIO_PMA_REG_8481_LED3_MASK,
6412 0x0);
6413
6414 bnx2x_cl45_write(bp, phy,
6415 MDIO_PMA_DEVAD,
6416 MDIO_PMA_REG_8481_LED5_MASK,
6417 0x20);
6418
6419 } else {
6420 bnx2x_cl45_write(bp, phy,
6421 MDIO_PMA_DEVAD,
6422 MDIO_PMA_REG_8481_LED1_MASK,
6423 0x0);
6424 }
6425 break;
6426 case LED_MODE_ON:
6427
6428 DP(NETIF_MSG_LINK, "Port 0x%x: LED MODE ON\n", params->port);
6429
6430 if ((params->hw_led_mode << SHARED_HW_CFG_LED_MODE_SHIFT) ==
6431 SHARED_HW_CFG_LED_EXTPHY1) {
6432 /* Set control reg */
6433 bnx2x_cl45_read(bp, phy,
6434 MDIO_PMA_DEVAD,
6435 MDIO_PMA_REG_8481_LINK_SIGNAL,
6436 &val);
6437 val &= 0x8000;
6438 val |= 0x2492;
6439
6440 bnx2x_cl45_write(bp, phy,
6441 MDIO_PMA_DEVAD,
6442 MDIO_PMA_REG_8481_LINK_SIGNAL,
6443 val);
6444
6445 /* Set LED masks */
6446 bnx2x_cl45_write(bp, phy,
6447 MDIO_PMA_DEVAD,
6448 MDIO_PMA_REG_8481_LED1_MASK,
6449 0x0);
6450
6451 bnx2x_cl45_write(bp, phy,
6452 MDIO_PMA_DEVAD,
6453 MDIO_PMA_REG_8481_LED2_MASK,
6454 0x20);
6455
6456 bnx2x_cl45_write(bp, phy,
6457 MDIO_PMA_DEVAD,
6458 MDIO_PMA_REG_8481_LED3_MASK,
6459 0x20);
6460
6461 bnx2x_cl45_write(bp, phy,
6462 MDIO_PMA_DEVAD,
6463 MDIO_PMA_REG_8481_LED5_MASK,
6464 0x0);
6465 } else {
6466 bnx2x_cl45_write(bp, phy,
6467 MDIO_PMA_DEVAD,
6468 MDIO_PMA_REG_8481_LED1_MASK,
6469 0x20);
6470 }
6471 break;
6472
6473 case LED_MODE_OPER:
6474
6475 DP(NETIF_MSG_LINK, "Port 0x%x: LED MODE OPER\n", params->port);
6476
6477 if ((params->hw_led_mode << SHARED_HW_CFG_LED_MODE_SHIFT) ==
6478 SHARED_HW_CFG_LED_EXTPHY1) {
6479
6480 /* Set control reg */
6481 bnx2x_cl45_read(bp, phy,
6482 MDIO_PMA_DEVAD,
6483 MDIO_PMA_REG_8481_LINK_SIGNAL,
6484 &val);
6485
6486 if (!((val &
6487 MDIO_PMA_REG_8481_LINK_SIGNAL_LED4_ENABLE_MASK)
6488 >> MDIO_PMA_REG_8481_LINK_SIGNAL_LED4_ENABLE_SHIFT)){
6489 DP(NETIF_MSG_LINK, "Seting LINK_SIGNAL\n");
6490 bnx2x_cl45_write(bp, phy,
6491 MDIO_PMA_DEVAD,
6492 MDIO_PMA_REG_8481_LINK_SIGNAL,
6493 0xa492);
6494 }
6495
6496 /* Set LED masks */
6497 bnx2x_cl45_write(bp, phy,
6498 MDIO_PMA_DEVAD,
6499 MDIO_PMA_REG_8481_LED1_MASK,
6500 0x10);
6501
6502 bnx2x_cl45_write(bp, phy,
6503 MDIO_PMA_DEVAD,
6504 MDIO_PMA_REG_8481_LED2_MASK,
6505 0x80);
6506
6507 bnx2x_cl45_write(bp, phy,
6508 MDIO_PMA_DEVAD,
6509 MDIO_PMA_REG_8481_LED3_MASK,
6510 0x98);
6511
6512 bnx2x_cl45_write(bp, phy,
6513 MDIO_PMA_DEVAD,
6514 MDIO_PMA_REG_8481_LED5_MASK,
6515 0x40);
6516
6517 } else {
6518 bnx2x_cl45_write(bp, phy,
6519 MDIO_PMA_DEVAD,
6520 MDIO_PMA_REG_8481_LED1_MASK,
6521 0x80);
6522 }
6523 break;
6524 }
6525}
Yaniv Rosnerde6eae12010-09-07 11:41:13 +00006526/******************************************************************/
6527/* SFX7101 PHY SECTION */
6528/******************************************************************/
6529static void bnx2x_7101_config_loopback(struct bnx2x_phy *phy,
6530 struct link_params *params)
6531{
6532 struct bnx2x *bp = params->bp;
6533 /* SFX7101_XGXS_TEST1 */
6534 bnx2x_cl45_write(bp, phy,
6535 MDIO_XS_DEVAD, MDIO_XS_SFX7101_XGXS_TEST1, 0x100);
6536}
6537
6538static u8 bnx2x_7101_config_init(struct bnx2x_phy *phy,
6539 struct link_params *params,
6540 struct link_vars *vars)
6541{
6542 u16 fw_ver1, fw_ver2, val;
6543 struct bnx2x *bp = params->bp;
6544 DP(NETIF_MSG_LINK, "Setting the SFX7101 LASI indication\n");
6545
6546 /* Restore normal power mode*/
6547 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
6548 MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port);
6549 /* HW reset */
6550 bnx2x_ext_phy_hw_reset(bp, params->port);
6551 bnx2x_wait_reset_complete(bp, phy);
6552
6553 bnx2x_cl45_write(bp, phy,
6554 MDIO_PMA_DEVAD, MDIO_PMA_REG_LASI_CTRL, 0x1);
6555 DP(NETIF_MSG_LINK, "Setting the SFX7101 LED to blink on traffic\n");
6556 bnx2x_cl45_write(bp, phy,
6557 MDIO_PMA_DEVAD, MDIO_PMA_REG_7107_LED_CNTL, (1<<3));
6558
6559 bnx2x_ext_phy_set_pause(params, phy, vars);
6560 /* Restart autoneg */
6561 bnx2x_cl45_read(bp, phy,
6562 MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, &val);
6563 val |= 0x200;
6564 bnx2x_cl45_write(bp, phy,
6565 MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, val);
6566
6567 /* Save spirom version */
6568 bnx2x_cl45_read(bp, phy,
6569 MDIO_PMA_DEVAD, MDIO_PMA_REG_7101_VER1, &fw_ver1);
6570
6571 bnx2x_cl45_read(bp, phy,
6572 MDIO_PMA_DEVAD, MDIO_PMA_REG_7101_VER2, &fw_ver2);
6573 bnx2x_save_spirom_version(bp, params->port,
6574 (u32)(fw_ver1<<16 | fw_ver2), phy->ver_addr);
6575 return 0;
6576}
6577
6578static u8 bnx2x_7101_read_status(struct bnx2x_phy *phy,
6579 struct link_params *params,
6580 struct link_vars *vars)
6581{
6582 struct bnx2x *bp = params->bp;
6583 u8 link_up;
6584 u16 val1, val2;
6585 bnx2x_cl45_read(bp, phy,
6586 MDIO_PMA_DEVAD, MDIO_PMA_REG_LASI_STATUS, &val2);
6587 bnx2x_cl45_read(bp, phy,
6588 MDIO_PMA_DEVAD, MDIO_PMA_REG_LASI_STATUS, &val1);
6589 DP(NETIF_MSG_LINK, "10G-base-T LASI status 0x%x->0x%x\n",
6590 val2, val1);
6591 bnx2x_cl45_read(bp, phy,
6592 MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val2);
6593 bnx2x_cl45_read(bp, phy,
6594 MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val1);
6595 DP(NETIF_MSG_LINK, "10G-base-T PMA status 0x%x->0x%x\n",
6596 val2, val1);
6597 link_up = ((val1 & 4) == 4);
6598 /* if link is up
6599 * print the AN outcome of the SFX7101 PHY
6600 */
6601 if (link_up) {
6602 bnx2x_cl45_read(bp, phy,
6603 MDIO_AN_DEVAD, MDIO_AN_REG_MASTER_STATUS,
6604 &val2);
6605 vars->line_speed = SPEED_10000;
Yaniv Rosner791f18c2011-01-18 04:33:42 +00006606 vars->duplex = DUPLEX_FULL;
Yaniv Rosnerde6eae12010-09-07 11:41:13 +00006607 DP(NETIF_MSG_LINK, "SFX7101 AN status 0x%x->Master=%x\n",
6608 val2, (val2 & (1<<14)));
6609 bnx2x_ext_phy_10G_an_resolve(bp, phy, vars);
6610 bnx2x_ext_phy_resolve_fc(phy, params, vars);
6611 }
6612 return link_up;
6613}
6614
6615
6616static u8 bnx2x_7101_format_ver(u32 spirom_ver, u8 *str, u16 *len)
6617{
6618 if (*len < 5)
6619 return -EINVAL;
6620 str[0] = (spirom_ver & 0xFF);
6621 str[1] = (spirom_ver & 0xFF00) >> 8;
6622 str[2] = (spirom_ver & 0xFF0000) >> 16;
6623 str[3] = (spirom_ver & 0xFF000000) >> 24;
6624 str[4] = '\0';
6625 *len -= 5;
6626 return 0;
6627}
6628
6629void bnx2x_sfx7101_sp_sw_reset(struct bnx2x *bp, struct bnx2x_phy *phy)
6630{
6631 u16 val, cnt;
6632
6633 bnx2x_cl45_read(bp, phy,
6634 MDIO_PMA_DEVAD,
6635 MDIO_PMA_REG_7101_RESET, &val);
6636
6637 for (cnt = 0; cnt < 10; cnt++) {
6638 msleep(50);
6639 /* Writes a self-clearing reset */
6640 bnx2x_cl45_write(bp, phy,
6641 MDIO_PMA_DEVAD,
6642 MDIO_PMA_REG_7101_RESET,
6643 (val | (1<<15)));
6644 /* Wait for clear */
6645 bnx2x_cl45_read(bp, phy,
6646 MDIO_PMA_DEVAD,
6647 MDIO_PMA_REG_7101_RESET, &val);
6648
6649 if ((val & (1<<15)) == 0)
6650 break;
6651 }
6652}
6653
Yaniv Rosnerb7737c92010-09-07 11:40:54 +00006654static void bnx2x_7101_hw_reset(struct bnx2x_phy *phy,
6655 struct link_params *params) {
6656 /* Low power mode is controlled by GPIO 2 */
6657 bnx2x_set_gpio(params->bp, MISC_REGISTERS_GPIO_2,
6658 MISC_REGISTERS_GPIO_OUTPUT_LOW, params->port);
6659 /* The PHY reset is controlled by GPIO 1 */
6660 bnx2x_set_gpio(params->bp, MISC_REGISTERS_GPIO_1,
6661 MISC_REGISTERS_GPIO_OUTPUT_LOW, params->port);
6662}
Yaniv Rosnerde6eae12010-09-07 11:41:13 +00006663
Yaniv Rosner7f02c4a2010-09-07 11:41:23 +00006664static void bnx2x_7101_set_link_led(struct bnx2x_phy *phy,
6665 struct link_params *params, u8 mode)
6666{
6667 u16 val = 0;
6668 struct bnx2x *bp = params->bp;
6669 switch (mode) {
6670 case LED_MODE_FRONT_PANEL_OFF:
6671 case LED_MODE_OFF:
6672 val = 2;
6673 break;
6674 case LED_MODE_ON:
6675 val = 1;
6676 break;
6677 case LED_MODE_OPER:
6678 val = 0;
6679 break;
6680 }
6681 bnx2x_cl45_write(bp, phy,
6682 MDIO_PMA_DEVAD,
6683 MDIO_PMA_REG_7107_LINK_LED_CNTL,
6684 val);
6685}
6686
Yaniv Rosnerb7737c92010-09-07 11:40:54 +00006687/******************************************************************/
6688/* STATIC PHY DECLARATION */
6689/******************************************************************/
6690
6691static struct bnx2x_phy phy_null = {
6692 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN,
6693 .addr = 0,
6694 .flags = FLAGS_INIT_XGXS_FIRST,
6695 .def_md_devad = 0,
6696 .reserved = 0,
6697 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
6698 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
6699 .mdio_ctrl = 0,
6700 .supported = 0,
6701 .media_type = ETH_PHY_NOT_PRESENT,
6702 .ver_addr = 0,
6703 .req_flow_ctrl = 0,
6704 .req_line_speed = 0,
6705 .speed_cap_mask = 0,
6706 .req_duplex = 0,
6707 .rsrv = 0,
6708 .config_init = (config_init_t)NULL,
6709 .read_status = (read_status_t)NULL,
6710 .link_reset = (link_reset_t)NULL,
6711 .config_loopback = (config_loopback_t)NULL,
6712 .format_fw_ver = (format_fw_ver_t)NULL,
6713 .hw_reset = (hw_reset_t)NULL,
Yaniv Rosnera22f0782010-09-07 11:41:20 +00006714 .set_link_led = (set_link_led_t)NULL,
6715 .phy_specific_func = (phy_specific_func_t)NULL
Yaniv Rosnerb7737c92010-09-07 11:40:54 +00006716};
6717
6718static struct bnx2x_phy phy_serdes = {
6719 .type = PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT,
6720 .addr = 0xff,
6721 .flags = 0,
6722 .def_md_devad = 0,
6723 .reserved = 0,
6724 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
6725 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
6726 .mdio_ctrl = 0,
6727 .supported = (SUPPORTED_10baseT_Half |
6728 SUPPORTED_10baseT_Full |
6729 SUPPORTED_100baseT_Half |
6730 SUPPORTED_100baseT_Full |
6731 SUPPORTED_1000baseT_Full |
6732 SUPPORTED_2500baseX_Full |
6733 SUPPORTED_TP |
6734 SUPPORTED_Autoneg |
6735 SUPPORTED_Pause |
6736 SUPPORTED_Asym_Pause),
6737 .media_type = ETH_PHY_UNSPECIFIED,
6738 .ver_addr = 0,
6739 .req_flow_ctrl = 0,
6740 .req_line_speed = 0,
6741 .speed_cap_mask = 0,
6742 .req_duplex = 0,
6743 .rsrv = 0,
6744 .config_init = (config_init_t)bnx2x_init_serdes,
6745 .read_status = (read_status_t)bnx2x_link_settings_status,
6746 .link_reset = (link_reset_t)bnx2x_int_link_reset,
6747 .config_loopback = (config_loopback_t)NULL,
6748 .format_fw_ver = (format_fw_ver_t)NULL,
6749 .hw_reset = (hw_reset_t)NULL,
Yaniv Rosnera22f0782010-09-07 11:41:20 +00006750 .set_link_led = (set_link_led_t)NULL,
6751 .phy_specific_func = (phy_specific_func_t)NULL
Yaniv Rosnerb7737c92010-09-07 11:40:54 +00006752};
6753
6754static struct bnx2x_phy phy_xgxs = {
6755 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT,
6756 .addr = 0xff,
6757 .flags = 0,
6758 .def_md_devad = 0,
6759 .reserved = 0,
6760 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
6761 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
6762 .mdio_ctrl = 0,
6763 .supported = (SUPPORTED_10baseT_Half |
6764 SUPPORTED_10baseT_Full |
6765 SUPPORTED_100baseT_Half |
6766 SUPPORTED_100baseT_Full |
6767 SUPPORTED_1000baseT_Full |
6768 SUPPORTED_2500baseX_Full |
6769 SUPPORTED_10000baseT_Full |
6770 SUPPORTED_FIBRE |
6771 SUPPORTED_Autoneg |
6772 SUPPORTED_Pause |
6773 SUPPORTED_Asym_Pause),
6774 .media_type = ETH_PHY_UNSPECIFIED,
6775 .ver_addr = 0,
6776 .req_flow_ctrl = 0,
6777 .req_line_speed = 0,
6778 .speed_cap_mask = 0,
6779 .req_duplex = 0,
6780 .rsrv = 0,
6781 .config_init = (config_init_t)bnx2x_init_xgxs,
6782 .read_status = (read_status_t)bnx2x_link_settings_status,
6783 .link_reset = (link_reset_t)bnx2x_int_link_reset,
6784 .config_loopback = (config_loopback_t)bnx2x_set_xgxs_loopback,
6785 .format_fw_ver = (format_fw_ver_t)NULL,
6786 .hw_reset = (hw_reset_t)NULL,
Yaniv Rosnera22f0782010-09-07 11:41:20 +00006787 .set_link_led = (set_link_led_t)NULL,
6788 .phy_specific_func = (phy_specific_func_t)NULL
Yaniv Rosnerb7737c92010-09-07 11:40:54 +00006789};
6790
6791static struct bnx2x_phy phy_7101 = {
6792 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101,
6793 .addr = 0xff,
6794 .flags = FLAGS_FAN_FAILURE_DET_REQ,
6795 .def_md_devad = 0,
6796 .reserved = 0,
6797 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
6798 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
6799 .mdio_ctrl = 0,
6800 .supported = (SUPPORTED_10000baseT_Full |
6801 SUPPORTED_TP |
6802 SUPPORTED_Autoneg |
6803 SUPPORTED_Pause |
6804 SUPPORTED_Asym_Pause),
6805 .media_type = ETH_PHY_BASE_T,
6806 .ver_addr = 0,
6807 .req_flow_ctrl = 0,
6808 .req_line_speed = 0,
6809 .speed_cap_mask = 0,
6810 .req_duplex = 0,
6811 .rsrv = 0,
6812 .config_init = (config_init_t)bnx2x_7101_config_init,
6813 .read_status = (read_status_t)bnx2x_7101_read_status,
6814 .link_reset = (link_reset_t)bnx2x_common_ext_link_reset,
6815 .config_loopback = (config_loopback_t)bnx2x_7101_config_loopback,
6816 .format_fw_ver = (format_fw_ver_t)bnx2x_7101_format_ver,
6817 .hw_reset = (hw_reset_t)bnx2x_7101_hw_reset,
Yaniv Rosner7f02c4a2010-09-07 11:41:23 +00006818 .set_link_led = (set_link_led_t)bnx2x_7101_set_link_led,
Yaniv Rosnera22f0782010-09-07 11:41:20 +00006819 .phy_specific_func = (phy_specific_func_t)NULL
Yaniv Rosnerb7737c92010-09-07 11:40:54 +00006820};
6821static struct bnx2x_phy phy_8073 = {
6822 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073,
6823 .addr = 0xff,
6824 .flags = FLAGS_HW_LOCK_REQUIRED,
6825 .def_md_devad = 0,
6826 .reserved = 0,
6827 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
6828 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
6829 .mdio_ctrl = 0,
6830 .supported = (SUPPORTED_10000baseT_Full |
6831 SUPPORTED_2500baseX_Full |
6832 SUPPORTED_1000baseT_Full |
6833 SUPPORTED_FIBRE |
6834 SUPPORTED_Autoneg |
6835 SUPPORTED_Pause |
6836 SUPPORTED_Asym_Pause),
6837 .media_type = ETH_PHY_UNSPECIFIED,
6838 .ver_addr = 0,
6839 .req_flow_ctrl = 0,
6840 .req_line_speed = 0,
6841 .speed_cap_mask = 0,
6842 .req_duplex = 0,
6843 .rsrv = 0,
Yaniv Rosner62b29a52010-09-07 11:40:58 +00006844 .config_init = (config_init_t)bnx2x_8073_config_init,
Yaniv Rosnerb7737c92010-09-07 11:40:54 +00006845 .read_status = (read_status_t)bnx2x_8073_read_status,
6846 .link_reset = (link_reset_t)bnx2x_8073_link_reset,
6847 .config_loopback = (config_loopback_t)NULL,
6848 .format_fw_ver = (format_fw_ver_t)bnx2x_format_ver,
6849 .hw_reset = (hw_reset_t)NULL,
Yaniv Rosnera22f0782010-09-07 11:41:20 +00006850 .set_link_led = (set_link_led_t)NULL,
6851 .phy_specific_func = (phy_specific_func_t)NULL
Yaniv Rosnerb7737c92010-09-07 11:40:54 +00006852};
6853static struct bnx2x_phy phy_8705 = {
6854 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705,
6855 .addr = 0xff,
6856 .flags = FLAGS_INIT_XGXS_FIRST,
6857 .def_md_devad = 0,
6858 .reserved = 0,
6859 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
6860 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
6861 .mdio_ctrl = 0,
6862 .supported = (SUPPORTED_10000baseT_Full |
6863 SUPPORTED_FIBRE |
6864 SUPPORTED_Pause |
6865 SUPPORTED_Asym_Pause),
6866 .media_type = ETH_PHY_XFP_FIBER,
6867 .ver_addr = 0,
6868 .req_flow_ctrl = 0,
6869 .req_line_speed = 0,
6870 .speed_cap_mask = 0,
6871 .req_duplex = 0,
6872 .rsrv = 0,
6873 .config_init = (config_init_t)bnx2x_8705_config_init,
6874 .read_status = (read_status_t)bnx2x_8705_read_status,
6875 .link_reset = (link_reset_t)bnx2x_common_ext_link_reset,
6876 .config_loopback = (config_loopback_t)NULL,
6877 .format_fw_ver = (format_fw_ver_t)bnx2x_null_format_ver,
6878 .hw_reset = (hw_reset_t)NULL,
Yaniv Rosnera22f0782010-09-07 11:41:20 +00006879 .set_link_led = (set_link_led_t)NULL,
6880 .phy_specific_func = (phy_specific_func_t)NULL
Yaniv Rosnerb7737c92010-09-07 11:40:54 +00006881};
6882static struct bnx2x_phy phy_8706 = {
6883 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706,
6884 .addr = 0xff,
6885 .flags = FLAGS_INIT_XGXS_FIRST,
6886 .def_md_devad = 0,
6887 .reserved = 0,
6888 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
6889 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
6890 .mdio_ctrl = 0,
6891 .supported = (SUPPORTED_10000baseT_Full |
6892 SUPPORTED_1000baseT_Full |
6893 SUPPORTED_FIBRE |
6894 SUPPORTED_Pause |
6895 SUPPORTED_Asym_Pause),
6896 .media_type = ETH_PHY_SFP_FIBER,
6897 .ver_addr = 0,
6898 .req_flow_ctrl = 0,
6899 .req_line_speed = 0,
6900 .speed_cap_mask = 0,
6901 .req_duplex = 0,
6902 .rsrv = 0,
6903 .config_init = (config_init_t)bnx2x_8706_config_init,
6904 .read_status = (read_status_t)bnx2x_8706_read_status,
6905 .link_reset = (link_reset_t)bnx2x_common_ext_link_reset,
6906 .config_loopback = (config_loopback_t)NULL,
6907 .format_fw_ver = (format_fw_ver_t)bnx2x_format_ver,
6908 .hw_reset = (hw_reset_t)NULL,
Yaniv Rosnera22f0782010-09-07 11:41:20 +00006909 .set_link_led = (set_link_led_t)NULL,
6910 .phy_specific_func = (phy_specific_func_t)NULL
Yaniv Rosnerb7737c92010-09-07 11:40:54 +00006911};
6912
6913static struct bnx2x_phy phy_8726 = {
6914 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726,
6915 .addr = 0xff,
6916 .flags = (FLAGS_HW_LOCK_REQUIRED |
6917 FLAGS_INIT_XGXS_FIRST),
6918 .def_md_devad = 0,
6919 .reserved = 0,
6920 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
6921 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
6922 .mdio_ctrl = 0,
6923 .supported = (SUPPORTED_10000baseT_Full |
6924 SUPPORTED_1000baseT_Full |
6925 SUPPORTED_Autoneg |
6926 SUPPORTED_FIBRE |
6927 SUPPORTED_Pause |
6928 SUPPORTED_Asym_Pause),
6929 .media_type = ETH_PHY_SFP_FIBER,
6930 .ver_addr = 0,
6931 .req_flow_ctrl = 0,
6932 .req_line_speed = 0,
6933 .speed_cap_mask = 0,
6934 .req_duplex = 0,
6935 .rsrv = 0,
6936 .config_init = (config_init_t)bnx2x_8726_config_init,
6937 .read_status = (read_status_t)bnx2x_8726_read_status,
6938 .link_reset = (link_reset_t)bnx2x_8726_link_reset,
6939 .config_loopback = (config_loopback_t)bnx2x_8726_config_loopback,
6940 .format_fw_ver = (format_fw_ver_t)bnx2x_format_ver,
6941 .hw_reset = (hw_reset_t)NULL,
Yaniv Rosnera22f0782010-09-07 11:41:20 +00006942 .set_link_led = (set_link_led_t)NULL,
6943 .phy_specific_func = (phy_specific_func_t)NULL
Yaniv Rosnerb7737c92010-09-07 11:40:54 +00006944};
6945
6946static struct bnx2x_phy phy_8727 = {
6947 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727,
6948 .addr = 0xff,
6949 .flags = FLAGS_FAN_FAILURE_DET_REQ,
6950 .def_md_devad = 0,
6951 .reserved = 0,
6952 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
6953 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
6954 .mdio_ctrl = 0,
6955 .supported = (SUPPORTED_10000baseT_Full |
6956 SUPPORTED_1000baseT_Full |
Yaniv Rosnerb7737c92010-09-07 11:40:54 +00006957 SUPPORTED_FIBRE |
6958 SUPPORTED_Pause |
6959 SUPPORTED_Asym_Pause),
6960 .media_type = ETH_PHY_SFP_FIBER,
6961 .ver_addr = 0,
6962 .req_flow_ctrl = 0,
6963 .req_line_speed = 0,
6964 .speed_cap_mask = 0,
6965 .req_duplex = 0,
6966 .rsrv = 0,
6967 .config_init = (config_init_t)bnx2x_8727_config_init,
6968 .read_status = (read_status_t)bnx2x_8727_read_status,
6969 .link_reset = (link_reset_t)bnx2x_8727_link_reset,
6970 .config_loopback = (config_loopback_t)NULL,
6971 .format_fw_ver = (format_fw_ver_t)bnx2x_format_ver,
6972 .hw_reset = (hw_reset_t)bnx2x_8727_hw_reset,
Yaniv Rosner7f02c4a2010-09-07 11:41:23 +00006973 .set_link_led = (set_link_led_t)bnx2x_8727_set_link_led,
Yaniv Rosnera22f0782010-09-07 11:41:20 +00006974 .phy_specific_func = (phy_specific_func_t)bnx2x_8727_specific_func
Yaniv Rosnerb7737c92010-09-07 11:40:54 +00006975};
6976static struct bnx2x_phy phy_8481 = {
6977 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481,
6978 .addr = 0xff,
Yaniv Rosnera22f0782010-09-07 11:41:20 +00006979 .flags = FLAGS_FAN_FAILURE_DET_REQ |
6980 FLAGS_REARM_LATCH_SIGNAL,
Yaniv Rosnerb7737c92010-09-07 11:40:54 +00006981 .def_md_devad = 0,
6982 .reserved = 0,
6983 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
6984 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
6985 .mdio_ctrl = 0,
6986 .supported = (SUPPORTED_10baseT_Half |
6987 SUPPORTED_10baseT_Full |
6988 SUPPORTED_100baseT_Half |
6989 SUPPORTED_100baseT_Full |
6990 SUPPORTED_1000baseT_Full |
6991 SUPPORTED_10000baseT_Full |
6992 SUPPORTED_TP |
6993 SUPPORTED_Autoneg |
6994 SUPPORTED_Pause |
6995 SUPPORTED_Asym_Pause),
6996 .media_type = ETH_PHY_BASE_T,
6997 .ver_addr = 0,
6998 .req_flow_ctrl = 0,
6999 .req_line_speed = 0,
7000 .speed_cap_mask = 0,
7001 .req_duplex = 0,
7002 .rsrv = 0,
7003 .config_init = (config_init_t)bnx2x_8481_config_init,
7004 .read_status = (read_status_t)bnx2x_848xx_read_status,
7005 .link_reset = (link_reset_t)bnx2x_8481_link_reset,
7006 .config_loopback = (config_loopback_t)NULL,
7007 .format_fw_ver = (format_fw_ver_t)bnx2x_848xx_format_ver,
7008 .hw_reset = (hw_reset_t)bnx2x_8481_hw_reset,
Yaniv Rosner7f02c4a2010-09-07 11:41:23 +00007009 .set_link_led = (set_link_led_t)bnx2x_848xx_set_link_led,
Yaniv Rosnera22f0782010-09-07 11:41:20 +00007010 .phy_specific_func = (phy_specific_func_t)NULL
Yaniv Rosnerb7737c92010-09-07 11:40:54 +00007011};
7012
7013static struct bnx2x_phy phy_84823 = {
7014 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823,
7015 .addr = 0xff,
Yaniv Rosnera22f0782010-09-07 11:41:20 +00007016 .flags = FLAGS_FAN_FAILURE_DET_REQ |
7017 FLAGS_REARM_LATCH_SIGNAL,
Yaniv Rosnerb7737c92010-09-07 11:40:54 +00007018 .def_md_devad = 0,
7019 .reserved = 0,
7020 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
7021 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
7022 .mdio_ctrl = 0,
7023 .supported = (SUPPORTED_10baseT_Half |
7024 SUPPORTED_10baseT_Full |
7025 SUPPORTED_100baseT_Half |
7026 SUPPORTED_100baseT_Full |
7027 SUPPORTED_1000baseT_Full |
7028 SUPPORTED_10000baseT_Full |
7029 SUPPORTED_TP |
7030 SUPPORTED_Autoneg |
7031 SUPPORTED_Pause |
7032 SUPPORTED_Asym_Pause),
7033 .media_type = ETH_PHY_BASE_T,
7034 .ver_addr = 0,
7035 .req_flow_ctrl = 0,
7036 .req_line_speed = 0,
7037 .speed_cap_mask = 0,
7038 .req_duplex = 0,
7039 .rsrv = 0,
7040 .config_init = (config_init_t)bnx2x_848x3_config_init,
7041 .read_status = (read_status_t)bnx2x_848xx_read_status,
7042 .link_reset = (link_reset_t)bnx2x_848x3_link_reset,
7043 .config_loopback = (config_loopback_t)NULL,
7044 .format_fw_ver = (format_fw_ver_t)bnx2x_848xx_format_ver,
7045 .hw_reset = (hw_reset_t)NULL,
Yaniv Rosner7f02c4a2010-09-07 11:41:23 +00007046 .set_link_led = (set_link_led_t)bnx2x_848xx_set_link_led,
Yaniv Rosnera22f0782010-09-07 11:41:20 +00007047 .phy_specific_func = (phy_specific_func_t)NULL
Yaniv Rosnerb7737c92010-09-07 11:40:54 +00007048};
7049
7050/*****************************************************************/
7051/* */
7052/* Populate the phy according. Main function: bnx2x_populate_phy */
7053/* */
7054/*****************************************************************/
7055
7056static void bnx2x_populate_preemphasis(struct bnx2x *bp, u32 shmem_base,
7057 struct bnx2x_phy *phy, u8 port,
7058 u8 phy_index)
7059{
7060 /* Get the 4 lanes xgxs config rx and tx */
7061 u32 rx = 0, tx = 0, i;
7062 for (i = 0; i < 2; i++) {
7063 /**
7064 * INT_PHY and EXT_PHY1 share the same value location in the
7065 * shmem. When num_phys is greater than 1, than this value
7066 * applies only to EXT_PHY1
7067 */
Yaniv Rosnera22f0782010-09-07 11:41:20 +00007068 if (phy_index == INT_PHY || phy_index == EXT_PHY1) {
7069 rx = REG_RD(bp, shmem_base +
7070 offsetof(struct shmem_region,
7071 dev_info.port_hw_config[port].xgxs_config_rx[i<<1]));
Yaniv Rosnerb7737c92010-09-07 11:40:54 +00007072
Yaniv Rosnera22f0782010-09-07 11:41:20 +00007073 tx = REG_RD(bp, shmem_base +
7074 offsetof(struct shmem_region,
7075 dev_info.port_hw_config[port].xgxs_config_tx[i<<1]));
7076 } else {
7077 rx = REG_RD(bp, shmem_base +
7078 offsetof(struct shmem_region,
7079 dev_info.port_hw_config[port].xgxs_config2_rx[i<<1]));
Yaniv Rosnerb7737c92010-09-07 11:40:54 +00007080
Yaniv Rosnera22f0782010-09-07 11:41:20 +00007081 tx = REG_RD(bp, shmem_base +
7082 offsetof(struct shmem_region,
7083 dev_info.port_hw_config[port].xgxs_config2_rx[i<<1]));
7084 }
Yaniv Rosnerb7737c92010-09-07 11:40:54 +00007085
7086 phy->rx_preemphasis[i << 1] = ((rx>>16) & 0xffff);
7087 phy->rx_preemphasis[(i << 1) + 1] = (rx & 0xffff);
7088
7089 phy->tx_preemphasis[i << 1] = ((tx>>16) & 0xffff);
7090 phy->tx_preemphasis[(i << 1) + 1] = (tx & 0xffff);
7091 }
7092}
7093
Yaniv Rosnere10bc842010-09-07 11:40:50 +00007094static u32 bnx2x_get_ext_phy_config(struct bnx2x *bp, u32 shmem_base,
7095 u8 phy_index, u8 port)
7096{
7097 u32 ext_phy_config = 0;
7098 switch (phy_index) {
7099 case EXT_PHY1:
7100 ext_phy_config = REG_RD(bp, shmem_base +
7101 offsetof(struct shmem_region,
7102 dev_info.port_hw_config[port].external_phy_config));
7103 break;
Yaniv Rosnera22f0782010-09-07 11:41:20 +00007104 case EXT_PHY2:
7105 ext_phy_config = REG_RD(bp, shmem_base +
7106 offsetof(struct shmem_region,
7107 dev_info.port_hw_config[port].external_phy_config2));
7108 break;
Yaniv Rosnere10bc842010-09-07 11:40:50 +00007109 default:
7110 DP(NETIF_MSG_LINK, "Invalid phy_index %d\n", phy_index);
7111 return -EINVAL;
7112 }
7113
7114 return ext_phy_config;
7115}
Yaniv Rosnerb7737c92010-09-07 11:40:54 +00007116static u8 bnx2x_populate_int_phy(struct bnx2x *bp, u32 shmem_base, u8 port,
7117 struct bnx2x_phy *phy)
7118{
7119 u32 phy_addr;
7120 u32 chip_id;
7121 u32 switch_cfg = (REG_RD(bp, shmem_base +
7122 offsetof(struct shmem_region,
7123 dev_info.port_feature_config[port].link_config)) &
7124 PORT_FEATURE_CONNECTED_SWITCH_MASK);
7125 chip_id = REG_RD(bp, MISC_REG_CHIP_NUM) << 16;
7126 switch (switch_cfg) {
7127 case SWITCH_CFG_1G:
7128 phy_addr = REG_RD(bp,
7129 NIG_REG_SERDES0_CTRL_PHY_ADDR +
7130 port * 0x10);
7131 *phy = phy_serdes;
7132 break;
7133 case SWITCH_CFG_10G:
7134 phy_addr = REG_RD(bp,
7135 NIG_REG_XGXS0_CTRL_PHY_ADDR +
7136 port * 0x18);
7137 *phy = phy_xgxs;
7138 break;
7139 default:
7140 DP(NETIF_MSG_LINK, "Invalid switch_cfg\n");
7141 return -EINVAL;
7142 }
7143 phy->addr = (u8)phy_addr;
7144 phy->mdio_ctrl = bnx2x_get_emac_base(bp,
Yaniv Rosnerc18aa152010-09-07 11:41:07 +00007145 SHARED_HW_CFG_MDC_MDIO_ACCESS1_BOTH,
Yaniv Rosnerb7737c92010-09-07 11:40:54 +00007146 port);
Dmitry Kravkovf2e08992010-10-06 03:28:26 +00007147 if (CHIP_IS_E2(bp))
7148 phy->def_md_devad = E2_DEFAULT_PHY_DEV_ADDR;
7149 else
7150 phy->def_md_devad = DEFAULT_PHY_DEV_ADDR;
Yaniv Rosnerb7737c92010-09-07 11:40:54 +00007151
7152 DP(NETIF_MSG_LINK, "Internal phy port=%d, addr=0x%x, mdio_ctl=0x%x\n",
7153 port, phy->addr, phy->mdio_ctrl);
7154
7155 bnx2x_populate_preemphasis(bp, shmem_base, phy, port, INT_PHY);
7156 return 0;
7157}
Yaniv Rosnere10bc842010-09-07 11:40:50 +00007158
7159static u8 bnx2x_populate_ext_phy(struct bnx2x *bp,
7160 u8 phy_index,
7161 u32 shmem_base,
Yaniv Rosnera22f0782010-09-07 11:41:20 +00007162 u32 shmem2_base,
Yaniv Rosnere10bc842010-09-07 11:40:50 +00007163 u8 port,
7164 struct bnx2x_phy *phy)
7165{
Yaniv Rosnerc18aa152010-09-07 11:41:07 +00007166 u32 ext_phy_config, phy_type, config2;
7167 u32 mdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_BOTH;
Yaniv Rosnere10bc842010-09-07 11:40:50 +00007168 ext_phy_config = bnx2x_get_ext_phy_config(bp, shmem_base,
7169 phy_index, port);
Yaniv Rosnerb7737c92010-09-07 11:40:54 +00007170 phy_type = XGXS_EXT_PHY_TYPE(ext_phy_config);
7171 /* Select the phy type */
7172 switch (phy_type) {
7173 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073:
Yaniv Rosnerc18aa152010-09-07 11:41:07 +00007174 mdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_SWAPPED;
Yaniv Rosnerb7737c92010-09-07 11:40:54 +00007175 *phy = phy_8073;
7176 break;
7177 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705:
7178 *phy = phy_8705;
7179 break;
7180 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706:
7181 *phy = phy_8706;
7182 break;
7183 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726:
Yaniv Rosnerc18aa152010-09-07 11:41:07 +00007184 mdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC1;
Yaniv Rosnerb7737c92010-09-07 11:40:54 +00007185 *phy = phy_8726;
7186 break;
7187 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727_NOC:
7188 /* BCM8727_NOC => BCM8727 no over current */
Yaniv Rosnerc18aa152010-09-07 11:41:07 +00007189 mdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC1;
Yaniv Rosnerb7737c92010-09-07 11:40:54 +00007190 *phy = phy_8727;
7191 phy->flags |= FLAGS_NOC;
7192 break;
7193 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727:
Yaniv Rosnerc18aa152010-09-07 11:41:07 +00007194 mdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC1;
Yaniv Rosnerb7737c92010-09-07 11:40:54 +00007195 *phy = phy_8727;
7196 break;
7197 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481:
7198 *phy = phy_8481;
7199 break;
7200 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823:
7201 *phy = phy_84823;
7202 break;
7203 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101:
7204 *phy = phy_7101;
7205 break;
7206 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE:
7207 *phy = phy_null;
7208 return -EINVAL;
7209 default:
7210 *phy = phy_null;
7211 return 0;
7212 }
7213
Yaniv Rosnere10bc842010-09-07 11:40:50 +00007214 phy->addr = XGXS_EXT_PHY_ADDR(ext_phy_config);
Yaniv Rosnerb7737c92010-09-07 11:40:54 +00007215 bnx2x_populate_preemphasis(bp, shmem_base, phy, port, phy_index);
Yaniv Rosner62b29a52010-09-07 11:40:58 +00007216
Yaniv Rosnerc18aa152010-09-07 11:41:07 +00007217 /**
7218 * The shmem address of the phy version is located on different
7219 * structures. In case this structure is too old, do not set
7220 * the address
7221 */
7222 config2 = REG_RD(bp, shmem_base + offsetof(struct shmem_region,
7223 dev_info.shared_hw_config.config2));
Yaniv Rosnera22f0782010-09-07 11:41:20 +00007224 if (phy_index == EXT_PHY1) {
7225 phy->ver_addr = shmem_base + offsetof(struct shmem_region,
7226 port_mb[port].ext_phy_fw_version);
Yaniv Rosnerc18aa152010-09-07 11:41:07 +00007227
7228 /* Check specific mdc mdio settings */
7229 if (config2 & SHARED_HW_CFG_MDC_MDIO_ACCESS1_MASK)
7230 mdc_mdio_access = config2 &
7231 SHARED_HW_CFG_MDC_MDIO_ACCESS1_MASK;
Yaniv Rosnera22f0782010-09-07 11:41:20 +00007232 } else {
7233 u32 size = REG_RD(bp, shmem2_base);
Yaniv Rosnerc18aa152010-09-07 11:41:07 +00007234
Yaniv Rosnera22f0782010-09-07 11:41:20 +00007235 if (size >
7236 offsetof(struct shmem2_region, ext_phy_fw_version2)) {
7237 phy->ver_addr = shmem2_base +
7238 offsetof(struct shmem2_region,
7239 ext_phy_fw_version2[port]);
7240 }
7241 /* Check specific mdc mdio settings */
7242 if (config2 & SHARED_HW_CFG_MDC_MDIO_ACCESS2_MASK)
7243 mdc_mdio_access = (config2 &
7244 SHARED_HW_CFG_MDC_MDIO_ACCESS2_MASK) >>
7245 (SHARED_HW_CFG_MDC_MDIO_ACCESS2_SHIFT -
7246 SHARED_HW_CFG_MDC_MDIO_ACCESS1_SHIFT);
7247 }
Yaniv Rosnerc18aa152010-09-07 11:41:07 +00007248 phy->mdio_ctrl = bnx2x_get_emac_base(bp, mdc_mdio_access, port);
7249
7250 /**
7251 * In case mdc/mdio_access of the external phy is different than the
7252 * mdc/mdio access of the XGXS, a HW lock must be taken in each access
7253 * to prevent one port interfere with another port's CL45 operations.
7254 */
7255 if (mdc_mdio_access != SHARED_HW_CFG_MDC_MDIO_ACCESS1_BOTH)
7256 phy->flags |= FLAGS_HW_LOCK_REQUIRED;
7257 DP(NETIF_MSG_LINK, "phy_type 0x%x port %d found in index %d\n",
7258 phy_type, port, phy_index);
7259 DP(NETIF_MSG_LINK, " addr=0x%x, mdio_ctl=0x%x\n",
7260 phy->addr, phy->mdio_ctrl);
Yaniv Rosnere10bc842010-09-07 11:40:50 +00007261 return 0;
7262}
7263
7264static u8 bnx2x_populate_phy(struct bnx2x *bp, u8 phy_index, u32 shmem_base,
Yaniv Rosnera22f0782010-09-07 11:41:20 +00007265 u32 shmem2_base, u8 port, struct bnx2x_phy *phy)
Yaniv Rosnere10bc842010-09-07 11:40:50 +00007266{
7267 u8 status = 0;
Yaniv Rosnerb7737c92010-09-07 11:40:54 +00007268 phy->type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN;
7269 if (phy_index == INT_PHY)
7270 return bnx2x_populate_int_phy(bp, shmem_base, port, phy);
Yaniv Rosnera22f0782010-09-07 11:41:20 +00007271 status = bnx2x_populate_ext_phy(bp, phy_index, shmem_base, shmem2_base,
Yaniv Rosnere10bc842010-09-07 11:40:50 +00007272 port, phy);
7273 return status;
7274}
7275
Yaniv Rosnerb7737c92010-09-07 11:40:54 +00007276static void bnx2x_phy_def_cfg(struct link_params *params,
7277 struct bnx2x_phy *phy,
Yaniv Rosnera22f0782010-09-07 11:41:20 +00007278 u8 phy_index)
Yaniv Rosnerb7737c92010-09-07 11:40:54 +00007279{
7280 struct bnx2x *bp = params->bp;
7281 u32 link_config;
7282 /* Populate the default phy configuration for MF mode */
Yaniv Rosnera22f0782010-09-07 11:41:20 +00007283 if (phy_index == EXT_PHY2) {
7284 link_config = REG_RD(bp, params->shmem_base +
7285 offsetof(struct shmem_region, dev_info.
7286 port_feature_config[params->port].link_config2));
7287 phy->speed_cap_mask = REG_RD(bp, params->shmem_base +
7288 offsetof(struct shmem_region, dev_info.
7289 port_hw_config[params->port].speed_capability_mask2));
7290 } else {
7291 link_config = REG_RD(bp, params->shmem_base +
Yaniv Rosnerb7737c92010-09-07 11:40:54 +00007292 offsetof(struct shmem_region, dev_info.
Yaniv Rosnera22f0782010-09-07 11:41:20 +00007293 port_feature_config[params->port].link_config));
7294 phy->speed_cap_mask = REG_RD(bp, params->shmem_base +
7295 offsetof(struct shmem_region, dev_info.
7296 port_hw_config[params->port].speed_capability_mask));
7297 }
7298 DP(NETIF_MSG_LINK, "Default config phy idx %x cfg 0x%x speed_cap_mask"
7299 " 0x%x\n", phy_index, link_config, phy->speed_cap_mask);
Yaniv Rosnerb7737c92010-09-07 11:40:54 +00007300
7301 phy->req_duplex = DUPLEX_FULL;
7302 switch (link_config & PORT_FEATURE_LINK_SPEED_MASK) {
7303 case PORT_FEATURE_LINK_SPEED_10M_HALF:
7304 phy->req_duplex = DUPLEX_HALF;
7305 case PORT_FEATURE_LINK_SPEED_10M_FULL:
7306 phy->req_line_speed = SPEED_10;
7307 break;
7308 case PORT_FEATURE_LINK_SPEED_100M_HALF:
7309 phy->req_duplex = DUPLEX_HALF;
7310 case PORT_FEATURE_LINK_SPEED_100M_FULL:
7311 phy->req_line_speed = SPEED_100;
7312 break;
7313 case PORT_FEATURE_LINK_SPEED_1G:
7314 phy->req_line_speed = SPEED_1000;
7315 break;
7316 case PORT_FEATURE_LINK_SPEED_2_5G:
7317 phy->req_line_speed = SPEED_2500;
7318 break;
7319 case PORT_FEATURE_LINK_SPEED_10G_CX4:
7320 phy->req_line_speed = SPEED_10000;
7321 break;
7322 default:
7323 phy->req_line_speed = SPEED_AUTO_NEG;
7324 break;
7325 }
7326
7327 switch (link_config & PORT_FEATURE_FLOW_CONTROL_MASK) {
7328 case PORT_FEATURE_FLOW_CONTROL_AUTO:
7329 phy->req_flow_ctrl = BNX2X_FLOW_CTRL_AUTO;
7330 break;
7331 case PORT_FEATURE_FLOW_CONTROL_TX:
7332 phy->req_flow_ctrl = BNX2X_FLOW_CTRL_TX;
7333 break;
7334 case PORT_FEATURE_FLOW_CONTROL_RX:
7335 phy->req_flow_ctrl = BNX2X_FLOW_CTRL_RX;
7336 break;
7337 case PORT_FEATURE_FLOW_CONTROL_BOTH:
7338 phy->req_flow_ctrl = BNX2X_FLOW_CTRL_BOTH;
7339 break;
7340 default:
7341 phy->req_flow_ctrl = BNX2X_FLOW_CTRL_NONE;
7342 break;
7343 }
7344}
7345
Yaniv Rosnera22f0782010-09-07 11:41:20 +00007346u32 bnx2x_phy_selection(struct link_params *params)
7347{
7348 u32 phy_config_swapped, prio_cfg;
7349 u32 return_cfg = PORT_HW_CFG_PHY_SELECTION_HARDWARE_DEFAULT;
7350
7351 phy_config_swapped = params->multi_phy_config &
7352 PORT_HW_CFG_PHY_SWAPPED_ENABLED;
7353
7354 prio_cfg = params->multi_phy_config &
7355 PORT_HW_CFG_PHY_SELECTION_MASK;
7356
7357 if (phy_config_swapped) {
7358 switch (prio_cfg) {
7359 case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY:
7360 return_cfg = PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY;
7361 break;
7362 case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY:
7363 return_cfg = PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY;
7364 break;
7365 case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY:
7366 return_cfg = PORT_HW_CFG_PHY_SELECTION_FIRST_PHY;
7367 break;
7368 case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY:
7369 return_cfg = PORT_HW_CFG_PHY_SELECTION_SECOND_PHY;
7370 break;
7371 }
7372 } else
7373 return_cfg = prio_cfg;
7374
7375 return return_cfg;
7376}
7377
7378
Yaniv Rosnerb7737c92010-09-07 11:40:54 +00007379u8 bnx2x_phy_probe(struct link_params *params)
7380{
7381 u8 phy_index, actual_phy_idx, link_cfg_idx;
Yaniv Rosnera22f0782010-09-07 11:41:20 +00007382 u32 phy_config_swapped;
Yaniv Rosnerb7737c92010-09-07 11:40:54 +00007383 struct bnx2x *bp = params->bp;
7384 struct bnx2x_phy *phy;
7385 params->num_phys = 0;
7386 DP(NETIF_MSG_LINK, "Begin phy probe\n");
Yaniv Rosnera22f0782010-09-07 11:41:20 +00007387 phy_config_swapped = params->multi_phy_config &
7388 PORT_HW_CFG_PHY_SWAPPED_ENABLED;
Yaniv Rosnerb7737c92010-09-07 11:40:54 +00007389
7390 for (phy_index = INT_PHY; phy_index < MAX_PHYS;
7391 phy_index++) {
7392 link_cfg_idx = LINK_CONFIG_IDX(phy_index);
7393 actual_phy_idx = phy_index;
Yaniv Rosnera22f0782010-09-07 11:41:20 +00007394 if (phy_config_swapped) {
7395 if (phy_index == EXT_PHY1)
7396 actual_phy_idx = EXT_PHY2;
7397 else if (phy_index == EXT_PHY2)
7398 actual_phy_idx = EXT_PHY1;
7399 }
7400 DP(NETIF_MSG_LINK, "phy_config_swapped %x, phy_index %x,"
7401 " actual_phy_idx %x\n", phy_config_swapped,
7402 phy_index, actual_phy_idx);
Yaniv Rosnerb7737c92010-09-07 11:40:54 +00007403 phy = &params->phy[actual_phy_idx];
7404 if (bnx2x_populate_phy(bp, phy_index, params->shmem_base,
Yaniv Rosnera22f0782010-09-07 11:41:20 +00007405 params->shmem2_base, params->port,
Yaniv Rosnerb7737c92010-09-07 11:40:54 +00007406 phy) != 0) {
7407 params->num_phys = 0;
7408 DP(NETIF_MSG_LINK, "phy probe failed in phy index %d\n",
7409 phy_index);
7410 for (phy_index = INT_PHY;
7411 phy_index < MAX_PHYS;
7412 phy_index++)
7413 *phy = phy_null;
7414 return -EINVAL;
7415 }
7416 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN)
7417 break;
7418
Yaniv Rosnera22f0782010-09-07 11:41:20 +00007419 bnx2x_phy_def_cfg(params, phy, phy_index);
Yaniv Rosnerb7737c92010-09-07 11:40:54 +00007420 params->num_phys++;
7421 }
7422
7423 DP(NETIF_MSG_LINK, "End phy probe. #phys found %x\n", params->num_phys);
7424 return 0;
7425}
7426
Yaniv Rosnerde6eae12010-09-07 11:41:13 +00007427static void set_phy_vars(struct link_params *params)
7428{
7429 struct bnx2x *bp = params->bp;
Yaniv Rosnera22f0782010-09-07 11:41:20 +00007430 u8 actual_phy_idx, phy_index, link_cfg_idx;
7431 u8 phy_config_swapped = params->multi_phy_config &
7432 PORT_HW_CFG_PHY_SWAPPED_ENABLED;
Yaniv Rosnerde6eae12010-09-07 11:41:13 +00007433 for (phy_index = INT_PHY; phy_index < params->num_phys;
7434 phy_index++) {
Yaniv Rosnera22f0782010-09-07 11:41:20 +00007435 link_cfg_idx = LINK_CONFIG_IDX(phy_index);
Yaniv Rosnerde6eae12010-09-07 11:41:13 +00007436 actual_phy_idx = phy_index;
Yaniv Rosnera22f0782010-09-07 11:41:20 +00007437 if (phy_config_swapped) {
7438 if (phy_index == EXT_PHY1)
7439 actual_phy_idx = EXT_PHY2;
7440 else if (phy_index == EXT_PHY2)
7441 actual_phy_idx = EXT_PHY1;
7442 }
Yaniv Rosnerde6eae12010-09-07 11:41:13 +00007443 params->phy[actual_phy_idx].req_flow_ctrl =
Yaniv Rosnera22f0782010-09-07 11:41:20 +00007444 params->req_flow_ctrl[link_cfg_idx];
Yaniv Rosnerde6eae12010-09-07 11:41:13 +00007445
7446 params->phy[actual_phy_idx].req_line_speed =
Yaniv Rosnera22f0782010-09-07 11:41:20 +00007447 params->req_line_speed[link_cfg_idx];
Yaniv Rosnerde6eae12010-09-07 11:41:13 +00007448
7449 params->phy[actual_phy_idx].speed_cap_mask =
Yaniv Rosnera22f0782010-09-07 11:41:20 +00007450 params->speed_cap_mask[link_cfg_idx];
Yaniv Rosnerde6eae12010-09-07 11:41:13 +00007451
7452 params->phy[actual_phy_idx].req_duplex =
Yaniv Rosnera22f0782010-09-07 11:41:20 +00007453 params->req_duplex[link_cfg_idx];
Yaniv Rosnerde6eae12010-09-07 11:41:13 +00007454
7455 DP(NETIF_MSG_LINK, "req_flow_ctrl %x, req_line_speed %x,"
7456 " speed_cap_mask %x\n",
7457 params->phy[actual_phy_idx].req_flow_ctrl,
7458 params->phy[actual_phy_idx].req_line_speed,
7459 params->phy[actual_phy_idx].speed_cap_mask);
7460 }
7461}
7462
7463u8 bnx2x_phy_init(struct link_params *params, struct link_vars *vars)
7464{
7465 struct bnx2x *bp = params->bp;
Yaniv Rosnerde6eae12010-09-07 11:41:13 +00007466 DP(NETIF_MSG_LINK, "Phy Initialization started\n");
Yaniv Rosnera22f0782010-09-07 11:41:20 +00007467 DP(NETIF_MSG_LINK, "(1) req_speed %d, req_flowctrl %d\n",
7468 params->req_line_speed[0], params->req_flow_ctrl[0]);
7469 DP(NETIF_MSG_LINK, "(2) req_speed %d, req_flowctrl %d\n",
7470 params->req_line_speed[1], params->req_flow_ctrl[1]);
Yaniv Rosnerde6eae12010-09-07 11:41:13 +00007471 vars->link_status = 0;
7472 vars->phy_link_up = 0;
7473 vars->link_up = 0;
7474 vars->line_speed = 0;
7475 vars->duplex = DUPLEX_FULL;
7476 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
7477 vars->mac_type = MAC_TYPE_NONE;
7478 vars->phy_flags = 0;
7479
7480 /* disable attentions */
7481 bnx2x_bits_dis(bp, NIG_REG_MASK_INTERRUPT_PORT0 + params->port*4,
7482 (NIG_MASK_XGXS0_LINK_STATUS |
7483 NIG_MASK_XGXS0_LINK10G |
7484 NIG_MASK_SERDES0_LINK_STATUS |
7485 NIG_MASK_MI_INT));
7486
7487 bnx2x_emac_init(params, vars);
7488
7489 if (params->num_phys == 0) {
7490 DP(NETIF_MSG_LINK, "No phy found for initialization !!\n");
7491 return -EINVAL;
7492 }
7493 set_phy_vars(params);
7494
7495 DP(NETIF_MSG_LINK, "Num of phys on board: %d\n", params->num_phys);
7496 if (CHIP_REV_IS_FPGA(bp)) {
7497
7498 vars->link_up = 1;
7499 vars->line_speed = SPEED_10000;
7500 vars->duplex = DUPLEX_FULL;
7501 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
7502 vars->link_status = (LINK_STATUS_LINK_UP | LINK_10GTFD);
7503 /* enable on E1.5 FPGA */
7504 if (CHIP_IS_E1H(bp)) {
7505 vars->flow_ctrl |=
7506 (BNX2X_FLOW_CTRL_TX |
7507 BNX2X_FLOW_CTRL_RX);
7508 vars->link_status |=
7509 (LINK_STATUS_TX_FLOW_CONTROL_ENABLED |
7510 LINK_STATUS_RX_FLOW_CONTROL_ENABLED);
7511 }
7512
7513 bnx2x_emac_enable(params, vars, 0);
Dmitry Kravkovf2e08992010-10-06 03:28:26 +00007514 if (!(CHIP_IS_E2(bp)))
7515 bnx2x_pbf_update(params, vars->flow_ctrl,
7516 vars->line_speed);
Yaniv Rosnerde6eae12010-09-07 11:41:13 +00007517 /* disable drain */
7518 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0);
7519
7520 /* update shared memory */
7521 bnx2x_update_mng(params, vars->link_status);
7522
7523 return 0;
7524
7525 } else
7526 if (CHIP_REV_IS_EMUL(bp)) {
7527
7528 vars->link_up = 1;
7529 vars->line_speed = SPEED_10000;
7530 vars->duplex = DUPLEX_FULL;
7531 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
7532 vars->link_status = (LINK_STATUS_LINK_UP | LINK_10GTFD);
7533
7534 bnx2x_bmac_enable(params, vars, 0);
7535
7536 bnx2x_pbf_update(params, vars->flow_ctrl, vars->line_speed);
7537 /* Disable drain */
7538 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE
7539 + params->port*4, 0);
7540
7541 /* update shared memory */
7542 bnx2x_update_mng(params, vars->link_status);
7543
7544 return 0;
7545
7546 } else
7547 if (params->loopback_mode == LOOPBACK_BMAC) {
7548
7549 vars->link_up = 1;
7550 vars->line_speed = SPEED_10000;
7551 vars->duplex = DUPLEX_FULL;
7552 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
7553 vars->mac_type = MAC_TYPE_BMAC;
7554
7555 vars->phy_flags = PHY_XGXS_FLAG;
7556
7557 bnx2x_xgxs_deassert(params);
7558
7559 /* set bmac loopback */
7560 bnx2x_bmac_enable(params, vars, 1);
7561
7562 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE +
7563 params->port*4, 0);
7564
7565 } else if (params->loopback_mode == LOOPBACK_EMAC) {
7566
7567 vars->link_up = 1;
7568 vars->line_speed = SPEED_1000;
7569 vars->duplex = DUPLEX_FULL;
7570 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
7571 vars->mac_type = MAC_TYPE_EMAC;
7572
7573 vars->phy_flags = PHY_XGXS_FLAG;
7574
7575 bnx2x_xgxs_deassert(params);
7576 /* set bmac loopback */
7577 bnx2x_emac_enable(params, vars, 1);
7578 bnx2x_emac_program(params, vars);
7579 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE +
7580 params->port*4, 0);
7581
7582 } else if ((params->loopback_mode == LOOPBACK_XGXS) ||
7583 (params->loopback_mode == LOOPBACK_EXT_PHY)) {
7584
7585 vars->link_up = 1;
Yaniv Rosnerde6eae12010-09-07 11:41:13 +00007586 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
Yaniv Rosnera22f0782010-09-07 11:41:20 +00007587 vars->duplex = DUPLEX_FULL;
7588 if (params->req_line_speed[0] == SPEED_1000) {
7589 vars->line_speed = SPEED_1000;
7590 vars->mac_type = MAC_TYPE_EMAC;
7591 } else {
7592 vars->line_speed = SPEED_10000;
7593 vars->mac_type = MAC_TYPE_BMAC;
7594 }
Yaniv Rosnerde6eae12010-09-07 11:41:13 +00007595
7596 bnx2x_xgxs_deassert(params);
7597 bnx2x_link_initialize(params, vars);
7598
Yaniv Rosnera22f0782010-09-07 11:41:20 +00007599 if (params->req_line_speed[0] == SPEED_1000) {
7600 bnx2x_emac_program(params, vars);
7601 bnx2x_emac_enable(params, vars, 0);
7602 } else
Yaniv Rosnerde6eae12010-09-07 11:41:13 +00007603 bnx2x_bmac_enable(params, vars, 0);
7604
7605 if (params->loopback_mode == LOOPBACK_XGXS) {
7606 /* set 10G XGXS loopback */
7607 params->phy[INT_PHY].config_loopback(
7608 &params->phy[INT_PHY],
7609 params);
7610
7611 } else {
7612 /* set external phy loopback */
7613 u8 phy_index;
7614 for (phy_index = EXT_PHY1;
7615 phy_index < params->num_phys; phy_index++) {
7616 if (params->phy[phy_index].config_loopback)
7617 params->phy[phy_index].config_loopback(
7618 &params->phy[phy_index],
7619 params);
7620 }
7621 }
7622
7623 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE +
7624 params->port*4, 0);
7625
Yaniv Rosner7f02c4a2010-09-07 11:41:23 +00007626 bnx2x_set_led(params, vars,
7627 LED_MODE_OPER, vars->line_speed);
Yaniv Rosnerde6eae12010-09-07 11:41:13 +00007628 } else
7629 /* No loopback */
7630 {
7631 if (params->switch_cfg == SWITCH_CFG_10G)
7632 bnx2x_xgxs_deassert(params);
7633 else
7634 bnx2x_serdes_deassert(bp, params->port);
Yaniv Rosner7f02c4a2010-09-07 11:41:23 +00007635
Yaniv Rosnerde6eae12010-09-07 11:41:13 +00007636 bnx2x_link_initialize(params, vars);
7637 msleep(30);
7638 bnx2x_link_int_enable(params);
7639 }
7640 return 0;
7641}
7642u8 bnx2x_link_reset(struct link_params *params, struct link_vars *vars,
7643 u8 reset_ext_phy)
7644{
7645 struct bnx2x *bp = params->bp;
Yaniv Rosnercf1d9722010-11-01 05:32:34 +00007646 u8 phy_index, port = params->port, clear_latch_ind = 0;
Yaniv Rosnerde6eae12010-09-07 11:41:13 +00007647 DP(NETIF_MSG_LINK, "Resetting the link of port %d\n", port);
7648 /* disable attentions */
7649 vars->link_status = 0;
7650 bnx2x_update_mng(params, vars->link_status);
7651 bnx2x_bits_dis(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4,
7652 (NIG_MASK_XGXS0_LINK_STATUS |
7653 NIG_MASK_XGXS0_LINK10G |
7654 NIG_MASK_SERDES0_LINK_STATUS |
7655 NIG_MASK_MI_INT));
7656
7657 /* activate nig drain */
7658 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + port*4, 1);
7659
7660 /* disable nig egress interface */
7661 REG_WR(bp, NIG_REG_BMAC0_OUT_EN + port*4, 0);
7662 REG_WR(bp, NIG_REG_EGRESS_EMAC0_OUT_EN + port*4, 0);
7663
7664 /* Stop BigMac rx */
7665 bnx2x_bmac_rx_disable(bp, port);
7666
7667 /* disable emac */
7668 REG_WR(bp, NIG_REG_NIG_EMAC0_EN + port*4, 0);
7669
7670 msleep(10);
7671 /* The PHY reset is controled by GPIO 1
7672 * Hold it as vars low
7673 */
7674 /* clear link led */
Yaniv Rosner7f02c4a2010-09-07 11:41:23 +00007675 bnx2x_set_led(params, vars, LED_MODE_OFF, 0);
7676
Yaniv Rosnerde6eae12010-09-07 11:41:13 +00007677 if (reset_ext_phy) {
7678 for (phy_index = EXT_PHY1; phy_index < params->num_phys;
7679 phy_index++) {
7680 if (params->phy[phy_index].link_reset)
7681 params->phy[phy_index].link_reset(
7682 &params->phy[phy_index],
7683 params);
Yaniv Rosnercf1d9722010-11-01 05:32:34 +00007684 if (params->phy[phy_index].flags &
7685 FLAGS_REARM_LATCH_SIGNAL)
7686 clear_latch_ind = 1;
Yaniv Rosnerde6eae12010-09-07 11:41:13 +00007687 }
7688 }
7689
Yaniv Rosnercf1d9722010-11-01 05:32:34 +00007690 if (clear_latch_ind) {
7691 /* Clear latching indication */
7692 bnx2x_rearm_latch_signal(bp, port, 0);
7693 bnx2x_bits_dis(bp, NIG_REG_LATCH_BC_0 + port*4,
7694 1 << NIG_LATCH_BC_ENABLE_MI_INT);
7695 }
Yaniv Rosnerde6eae12010-09-07 11:41:13 +00007696 if (params->phy[INT_PHY].link_reset)
7697 params->phy[INT_PHY].link_reset(
7698 &params->phy[INT_PHY], params);
7699 /* reset BigMac */
7700 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
7701 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port));
7702
7703 /* disable nig ingress interface */
7704 REG_WR(bp, NIG_REG_BMAC0_IN_EN + port*4, 0);
7705 REG_WR(bp, NIG_REG_EMAC0_IN_EN + port*4, 0);
7706 REG_WR(bp, NIG_REG_BMAC0_OUT_EN + port*4, 0);
7707 REG_WR(bp, NIG_REG_EGRESS_EMAC0_OUT_EN + port*4, 0);
7708 vars->link_up = 0;
7709 return 0;
7710}
7711
7712/****************************************************************************/
7713/* Common function */
7714/****************************************************************************/
Dmitry Kravkovf2e08992010-10-06 03:28:26 +00007715static u8 bnx2x_8073_common_init_phy(struct bnx2x *bp,
7716 u32 shmem_base_path[],
7717 u32 shmem2_base_path[], u8 phy_index,
7718 u32 chip_id)
Yaniv Rosner6bbca912008-08-13 15:57:28 -07007719{
Yaniv Rosnere10bc842010-09-07 11:40:50 +00007720 struct bnx2x_phy phy[PORT_MAX];
7721 struct bnx2x_phy *phy_blk[PORT_MAX];
Yaniv Rosner6bbca912008-08-13 15:57:28 -07007722 u16 val;
7723 s8 port;
Dmitry Kravkovf2e08992010-10-06 03:28:26 +00007724 s8 port_of_path = 0;
Yaniv Rosner6bbca912008-08-13 15:57:28 -07007725
Yaniv Rosner1d03f062010-11-01 05:32:41 +00007726 bnx2x_ext_phy_hw_reset(bp, 0);
Yaniv Rosner6bbca912008-08-13 15:57:28 -07007727 /* PART1 - Reset both phys */
7728 for (port = PORT_MAX - 1; port >= PORT_0; port--) {
Dmitry Kravkovf2e08992010-10-06 03:28:26 +00007729 u32 shmem_base, shmem2_base;
7730 /* In E2, same phy is using for port0 of the two paths */
7731 if (CHIP_IS_E2(bp)) {
7732 shmem_base = shmem_base_path[port];
7733 shmem2_base = shmem2_base_path[port];
7734 port_of_path = 0;
7735 } else {
7736 shmem_base = shmem_base_path[0];
7737 shmem2_base = shmem2_base_path[0];
7738 port_of_path = port;
7739 }
7740
Yaniv Rosner6bbca912008-08-13 15:57:28 -07007741 /* Extract the ext phy address for the port */
Yaniv Rosnera22f0782010-09-07 11:41:20 +00007742 if (bnx2x_populate_phy(bp, phy_index, shmem_base, shmem2_base,
Dmitry Kravkovf2e08992010-10-06 03:28:26 +00007743 port_of_path, &phy[port]) !=
Yaniv Rosnere10bc842010-09-07 11:40:50 +00007744 0) {
7745 DP(NETIF_MSG_LINK, "populate_phy failed\n");
7746 return -EINVAL;
7747 }
Yaniv Rosner6bbca912008-08-13 15:57:28 -07007748 /* disable attentions */
Yaniv Rosner6a71bbe2010-11-01 05:32:31 +00007749 bnx2x_bits_dis(bp, NIG_REG_MASK_INTERRUPT_PORT0 +
7750 port_of_path*4,
Yaniv Rosner6bbca912008-08-13 15:57:28 -07007751 (NIG_MASK_XGXS0_LINK_STATUS |
7752 NIG_MASK_XGXS0_LINK10G |
7753 NIG_MASK_SERDES0_LINK_STATUS |
7754 NIG_MASK_MI_INT));
7755
Yaniv Rosner6bbca912008-08-13 15:57:28 -07007756 /* Need to take the phy out of low power mode in order
7757 to write to access its registers */
7758 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
7759 MISC_REGISTERS_GPIO_OUTPUT_HIGH, port);
7760
7761 /* Reset the phy */
Yaniv Rosnere10bc842010-09-07 11:40:50 +00007762 bnx2x_cl45_write(bp, &phy[port],
Yaniv Rosner6bbca912008-08-13 15:57:28 -07007763 MDIO_PMA_DEVAD,
7764 MDIO_PMA_REG_CTRL,
7765 1<<15);
7766 }
7767
7768 /* Add delay of 150ms after reset */
7769 msleep(150);
7770
Yaniv Rosnere10bc842010-09-07 11:40:50 +00007771 if (phy[PORT_0].addr & 0x1) {
7772 phy_blk[PORT_0] = &(phy[PORT_1]);
7773 phy_blk[PORT_1] = &(phy[PORT_0]);
7774 } else {
7775 phy_blk[PORT_0] = &(phy[PORT_0]);
7776 phy_blk[PORT_1] = &(phy[PORT_1]);
7777 }
7778
Yaniv Rosner6bbca912008-08-13 15:57:28 -07007779 /* PART2 - Download firmware to both phys */
7780 for (port = PORT_MAX - 1; port >= PORT_0; port--) {
Dmitry Kravkovf2e08992010-10-06 03:28:26 +00007781 if (CHIP_IS_E2(bp))
7782 port_of_path = 0;
7783 else
7784 port_of_path = port;
Yaniv Rosner6bbca912008-08-13 15:57:28 -07007785
Dmitry Kravkovf2e08992010-10-06 03:28:26 +00007786 DP(NETIF_MSG_LINK, "Loading spirom for phy address 0x%x\n",
7787 phy_blk[port]->addr);
Yaniv Rosner5c99274b2011-01-18 04:33:36 +00007788 if (bnx2x_8073_8727_external_rom_boot(bp, phy_blk[port],
7789 port_of_path))
Yaniv Rosner6bbca912008-08-13 15:57:28 -07007790 return -EINVAL;
Yaniv Rosner6bbca912008-08-13 15:57:28 -07007791
7792 /* Only set bit 10 = 1 (Tx power down) */
Yaniv Rosnere10bc842010-09-07 11:40:50 +00007793 bnx2x_cl45_read(bp, phy_blk[port],
Yaniv Rosner6bbca912008-08-13 15:57:28 -07007794 MDIO_PMA_DEVAD,
7795 MDIO_PMA_REG_TX_POWER_DOWN, &val);
7796
7797 /* Phase1 of TX_POWER_DOWN reset */
Yaniv Rosnere10bc842010-09-07 11:40:50 +00007798 bnx2x_cl45_write(bp, phy_blk[port],
Yaniv Rosner6bbca912008-08-13 15:57:28 -07007799 MDIO_PMA_DEVAD,
7800 MDIO_PMA_REG_TX_POWER_DOWN,
7801 (val | 1<<10));
7802 }
7803
7804 /* Toggle Transmitter: Power down and then up with 600ms
7805 delay between */
7806 msleep(600);
7807
7808 /* PART3 - complete TX_POWER_DOWN process, and set GPIO2 back to low */
7809 for (port = PORT_MAX - 1; port >= PORT_0; port--) {
Eilon Greensteinf5372252009-02-12 08:38:30 +00007810 /* Phase2 of POWER_DOWN_RESET */
Yaniv Rosner6bbca912008-08-13 15:57:28 -07007811 /* Release bit 10 (Release Tx power down) */
Yaniv Rosnere10bc842010-09-07 11:40:50 +00007812 bnx2x_cl45_read(bp, phy_blk[port],
Yaniv Rosner6bbca912008-08-13 15:57:28 -07007813 MDIO_PMA_DEVAD,
7814 MDIO_PMA_REG_TX_POWER_DOWN, &val);
7815
Yaniv Rosnere10bc842010-09-07 11:40:50 +00007816 bnx2x_cl45_write(bp, phy_blk[port],
Yaniv Rosner6bbca912008-08-13 15:57:28 -07007817 MDIO_PMA_DEVAD,
7818 MDIO_PMA_REG_TX_POWER_DOWN, (val & (~(1<<10))));
7819 msleep(15);
7820
7821 /* Read modify write the SPI-ROM version select register */
Yaniv Rosnere10bc842010-09-07 11:40:50 +00007822 bnx2x_cl45_read(bp, phy_blk[port],
Yaniv Rosner6bbca912008-08-13 15:57:28 -07007823 MDIO_PMA_DEVAD,
7824 MDIO_PMA_REG_EDC_FFE_MAIN, &val);
Yaniv Rosnere10bc842010-09-07 11:40:50 +00007825 bnx2x_cl45_write(bp, phy_blk[port],
Yaniv Rosner6bbca912008-08-13 15:57:28 -07007826 MDIO_PMA_DEVAD,
7827 MDIO_PMA_REG_EDC_FFE_MAIN, (val | (1<<12)));
7828
7829 /* set GPIO2 back to LOW */
7830 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
7831 MISC_REGISTERS_GPIO_OUTPUT_LOW, port);
7832 }
7833 return 0;
Yaniv Rosner6bbca912008-08-13 15:57:28 -07007834}
Dmitry Kravkovf2e08992010-10-06 03:28:26 +00007835static u8 bnx2x_8726_common_init_phy(struct bnx2x *bp,
7836 u32 shmem_base_path[],
7837 u32 shmem2_base_path[], u8 phy_index,
7838 u32 chip_id)
Yaniv Rosnerde6eae12010-09-07 11:41:13 +00007839{
7840 u32 val;
7841 s8 port;
7842 struct bnx2x_phy phy;
7843 /* Use port1 because of the static port-swap */
7844 /* Enable the module detection interrupt */
7845 val = REG_RD(bp, MISC_REG_GPIO_EVENT_EN);
7846 val |= ((1<<MISC_REGISTERS_GPIO_3)|
7847 (1<<(MISC_REGISTERS_GPIO_3 + MISC_REGISTERS_GPIO_PORT_SHIFT)));
7848 REG_WR(bp, MISC_REG_GPIO_EVENT_EN, val);
7849
Yaniv Rosner650154b2010-11-01 05:32:36 +00007850 bnx2x_ext_phy_hw_reset(bp, 0);
Yaniv Rosnerde6eae12010-09-07 11:41:13 +00007851 msleep(5);
7852 for (port = 0; port < PORT_MAX; port++) {
Dmitry Kravkovf2e08992010-10-06 03:28:26 +00007853 u32 shmem_base, shmem2_base;
7854
7855 /* In E2, same phy is using for port0 of the two paths */
7856 if (CHIP_IS_E2(bp)) {
7857 shmem_base = shmem_base_path[port];
7858 shmem2_base = shmem2_base_path[port];
7859 } else {
7860 shmem_base = shmem_base_path[0];
7861 shmem2_base = shmem2_base_path[0];
7862 }
Yaniv Rosnerde6eae12010-09-07 11:41:13 +00007863 /* Extract the ext phy address for the port */
Yaniv Rosnera22f0782010-09-07 11:41:20 +00007864 if (bnx2x_populate_phy(bp, phy_index, shmem_base, shmem2_base,
Yaniv Rosnerde6eae12010-09-07 11:41:13 +00007865 port, &phy) !=
7866 0) {
7867 DP(NETIF_MSG_LINK, "populate phy failed\n");
7868 return -EINVAL;
7869 }
7870
7871 /* Reset phy*/
7872 bnx2x_cl45_write(bp, &phy,
7873 MDIO_PMA_DEVAD, MDIO_PMA_REG_GEN_CTRL, 0x0001);
7874
7875
7876 /* Set fault module detected LED on */
7877 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_0,
7878 MISC_REGISTERS_GPIO_HIGH,
7879 port);
7880 }
7881
7882 return 0;
7883}
Dmitry Kravkovf2e08992010-10-06 03:28:26 +00007884static u8 bnx2x_8727_common_init_phy(struct bnx2x *bp,
7885 u32 shmem_base_path[],
7886 u32 shmem2_base_path[], u8 phy_index,
7887 u32 chip_id)
Eilon Greenstein4d295db2009-07-21 05:47:47 +00007888{
Yaniv Rosnera22f0782010-09-07 11:41:20 +00007889 s8 port;
Eilon Greenstein4d295db2009-07-21 05:47:47 +00007890 u32 swap_val, swap_override;
Yaniv Rosnere10bc842010-09-07 11:40:50 +00007891 struct bnx2x_phy phy[PORT_MAX];
7892 struct bnx2x_phy *phy_blk[PORT_MAX];
Dmitry Kravkovf2e08992010-10-06 03:28:26 +00007893 s8 port_of_path;
Eilon Greenstein4d295db2009-07-21 05:47:47 +00007894 swap_val = REG_RD(bp, NIG_REG_PORT_SWAP);
7895 swap_override = REG_RD(bp, NIG_REG_STRAP_OVERRIDE);
7896
Yaniv Rosnera22f0782010-09-07 11:41:20 +00007897 port = 1;
7898
7899 bnx2x_ext_phy_hw_reset(bp, port ^ (swap_val && swap_override));
7900
7901 /* Calculate the port based on port swap */
7902 port ^= (swap_val && swap_override);
7903
Eilon Greenstein4d295db2009-07-21 05:47:47 +00007904 msleep(5);
7905
7906 /* PART1 - Reset both phys */
Yaniv Rosnera22f0782010-09-07 11:41:20 +00007907 for (port = PORT_MAX - 1; port >= PORT_0; port--) {
Dmitry Kravkovf2e08992010-10-06 03:28:26 +00007908 u32 shmem_base, shmem2_base;
7909
7910 /* In E2, same phy is using for port0 of the two paths */
7911 if (CHIP_IS_E2(bp)) {
7912 shmem_base = shmem_base_path[port];
7913 shmem2_base = shmem2_base_path[port];
7914 port_of_path = 0;
7915 } else {
7916 shmem_base = shmem_base_path[0];
7917 shmem2_base = shmem2_base_path[0];
7918 port_of_path = port;
7919 }
7920
Eilon Greenstein4d295db2009-07-21 05:47:47 +00007921 /* Extract the ext phy address for the port */
Yaniv Rosnera22f0782010-09-07 11:41:20 +00007922 if (bnx2x_populate_phy(bp, phy_index, shmem_base, shmem2_base,
Dmitry Kravkovf2e08992010-10-06 03:28:26 +00007923 port_of_path, &phy[port]) !=
Yaniv Rosnere10bc842010-09-07 11:40:50 +00007924 0) {
7925 DP(NETIF_MSG_LINK, "populate phy failed\n");
7926 return -EINVAL;
7927 }
Eilon Greenstein4d295db2009-07-21 05:47:47 +00007928 /* disable attentions */
Dmitry Kravkovf2e08992010-10-06 03:28:26 +00007929 bnx2x_bits_dis(bp, NIG_REG_MASK_INTERRUPT_PORT0 +
7930 port_of_path*4,
7931 (NIG_MASK_XGXS0_LINK_STATUS |
7932 NIG_MASK_XGXS0_LINK10G |
7933 NIG_MASK_SERDES0_LINK_STATUS |
7934 NIG_MASK_MI_INT));
Eilon Greenstein4d295db2009-07-21 05:47:47 +00007935
Eilon Greenstein4d295db2009-07-21 05:47:47 +00007936
7937 /* Reset the phy */
Yaniv Rosnere10bc842010-09-07 11:40:50 +00007938 bnx2x_cl45_write(bp, &phy[port],
Eilon Greenstein4d295db2009-07-21 05:47:47 +00007939 MDIO_PMA_DEVAD,
7940 MDIO_PMA_REG_CTRL,
7941 1<<15);
7942 }
7943
7944 /* Add delay of 150ms after reset */
7945 msleep(150);
Yaniv Rosnere10bc842010-09-07 11:40:50 +00007946 if (phy[PORT_0].addr & 0x1) {
7947 phy_blk[PORT_0] = &(phy[PORT_1]);
7948 phy_blk[PORT_1] = &(phy[PORT_0]);
7949 } else {
7950 phy_blk[PORT_0] = &(phy[PORT_0]);
7951 phy_blk[PORT_1] = &(phy[PORT_1]);
7952 }
Eilon Greenstein4d295db2009-07-21 05:47:47 +00007953 /* PART2 - Download firmware to both phys */
Yaniv Rosnere10bc842010-09-07 11:40:50 +00007954 for (port = PORT_MAX - 1; port >= PORT_0; port--) {
Dmitry Kravkovf2e08992010-10-06 03:28:26 +00007955 if (CHIP_IS_E2(bp))
7956 port_of_path = 0;
7957 else
7958 port_of_path = port;
7959 DP(NETIF_MSG_LINK, "Loading spirom for phy address 0x%x\n",
7960 phy_blk[port]->addr);
Yaniv Rosner5c99274b2011-01-18 04:33:36 +00007961 if (bnx2x_8073_8727_external_rom_boot(bp, phy_blk[port],
7962 port_of_path))
Eilon Greenstein4d295db2009-07-21 05:47:47 +00007963 return -EINVAL;
Eilon Greenstein4d295db2009-07-21 05:47:47 +00007964
Yaniv Rosner5c99274b2011-01-18 04:33:36 +00007965 }
Eilon Greenstein4d295db2009-07-21 05:47:47 +00007966 return 0;
7967}
7968
Dmitry Kravkovf2e08992010-10-06 03:28:26 +00007969static u8 bnx2x_ext_phy_common_init(struct bnx2x *bp, u32 shmem_base_path[],
7970 u32 shmem2_base_path[], u8 phy_index,
7971 u32 ext_phy_type, u32 chip_id)
Yaniv Rosner6bbca912008-08-13 15:57:28 -07007972{
7973 u8 rc = 0;
Yaniv Rosner6bbca912008-08-13 15:57:28 -07007974
7975 switch (ext_phy_type) {
7976 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073:
Dmitry Kravkovf2e08992010-10-06 03:28:26 +00007977 rc = bnx2x_8073_common_init_phy(bp, shmem_base_path,
7978 shmem2_base_path,
7979 phy_index, chip_id);
Yaniv Rosner6bbca912008-08-13 15:57:28 -07007980 break;
Eilon Greenstein4d295db2009-07-21 05:47:47 +00007981
7982 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727:
7983 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727_NOC:
Dmitry Kravkovf2e08992010-10-06 03:28:26 +00007984 rc = bnx2x_8727_common_init_phy(bp, shmem_base_path,
7985 shmem2_base_path,
7986 phy_index, chip_id);
Eilon Greenstein4d295db2009-07-21 05:47:47 +00007987 break;
7988
Eilon Greenstein589abe32009-02-12 08:36:55 +00007989 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726:
7990 /* GPIO1 affects both ports, so there's need to pull
7991 it for single port alone */
Dmitry Kravkovf2e08992010-10-06 03:28:26 +00007992 rc = bnx2x_8726_common_init_phy(bp, shmem_base_path,
7993 shmem2_base_path,
7994 phy_index, chip_id);
Yaniv Rosnera22f0782010-09-07 11:41:20 +00007995 break;
7996 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE:
7997 rc = -EINVAL;
Yaniv Rosner4f60dab2009-11-05 19:18:23 +02007998 break;
Yaniv Rosner6bbca912008-08-13 15:57:28 -07007999 default:
8000 DP(NETIF_MSG_LINK,
8001 "bnx2x_common_init_phy: ext_phy 0x%x not required\n",
8002 ext_phy_type);
8003 break;
8004 }
8005
8006 return rc;
8007}
8008
Dmitry Kravkovf2e08992010-10-06 03:28:26 +00008009u8 bnx2x_common_init_phy(struct bnx2x *bp, u32 shmem_base_path[],
8010 u32 shmem2_base_path[], u32 chip_id)
Yaniv Rosnera22f0782010-09-07 11:41:20 +00008011{
8012 u8 rc = 0;
Yaniv Rosnerb21a3422011-01-18 04:33:24 +00008013 u32 phy_ver;
Yaniv Rosnera22f0782010-09-07 11:41:20 +00008014 u8 phy_index;
8015 u32 ext_phy_type, ext_phy_config;
8016 DP(NETIF_MSG_LINK, "Begin common phy init\n");
Yaniv Rosnerd90d96b2010-09-07 11:41:04 +00008017
Yaniv Rosnera22f0782010-09-07 11:41:20 +00008018 if (CHIP_REV_IS_EMUL(bp))
8019 return 0;
8020
Yaniv Rosnerb21a3422011-01-18 04:33:24 +00008021 /* Check if common init was already done */
8022 phy_ver = REG_RD(bp, shmem_base_path[0] +
8023 offsetof(struct shmem_region,
8024 port_mb[PORT_0].ext_phy_fw_version));
8025 if (phy_ver) {
8026 DP(NETIF_MSG_LINK, "Not doing common init; phy ver is 0x%x\n",
8027 phy_ver);
8028 return 0;
8029 }
8030
Yaniv Rosnera22f0782010-09-07 11:41:20 +00008031 /* Read the ext_phy_type for arbitrary port(0) */
8032 for (phy_index = EXT_PHY1; phy_index < MAX_PHYS;
8033 phy_index++) {
8034 ext_phy_config = bnx2x_get_ext_phy_config(bp,
Dmitry Kravkovf2e08992010-10-06 03:28:26 +00008035 shmem_base_path[0],
Yaniv Rosnera22f0782010-09-07 11:41:20 +00008036 phy_index, 0);
8037 ext_phy_type = XGXS_EXT_PHY_TYPE(ext_phy_config);
Dmitry Kravkovf2e08992010-10-06 03:28:26 +00008038 rc |= bnx2x_ext_phy_common_init(bp, shmem_base_path,
8039 shmem2_base_path,
8040 phy_index, ext_phy_type,
8041 chip_id);
Yaniv Rosnera22f0782010-09-07 11:41:20 +00008042 }
8043 return rc;
8044}
8045
8046u8 bnx2x_hw_lock_required(struct bnx2x *bp, u32 shmem_base, u32 shmem2_base)
Yaniv Rosnerd90d96b2010-09-07 11:41:04 +00008047{
8048 u8 phy_index;
8049 struct bnx2x_phy phy;
8050 for (phy_index = INT_PHY; phy_index < MAX_PHYS;
8051 phy_index++) {
Yaniv Rosnera22f0782010-09-07 11:41:20 +00008052 if (bnx2x_populate_phy(bp, phy_index, shmem_base, shmem2_base,
Yaniv Rosnerd90d96b2010-09-07 11:41:04 +00008053 0, &phy) != 0) {
8054 DP(NETIF_MSG_LINK, "populate phy failed\n");
8055 return 0;
8056 }
8057
8058 if (phy.flags & FLAGS_HW_LOCK_REQUIRED)
8059 return 1;
8060 }
8061 return 0;
8062}
8063
8064u8 bnx2x_fan_failure_det_req(struct bnx2x *bp,
8065 u32 shmem_base,
Yaniv Rosnera22f0782010-09-07 11:41:20 +00008066 u32 shmem2_base,
Yaniv Rosnerd90d96b2010-09-07 11:41:04 +00008067 u8 port)
8068{
8069 u8 phy_index, fan_failure_det_req = 0;
8070 struct bnx2x_phy phy;
8071 for (phy_index = EXT_PHY1; phy_index < MAX_PHYS;
8072 phy_index++) {
Yaniv Rosnera22f0782010-09-07 11:41:20 +00008073 if (bnx2x_populate_phy(bp, phy_index, shmem_base, shmem2_base,
Yaniv Rosnerd90d96b2010-09-07 11:41:04 +00008074 port, &phy)
8075 != 0) {
8076 DP(NETIF_MSG_LINK, "populate phy failed\n");
8077 return 0;
8078 }
8079 fan_failure_det_req |= (phy.flags &
8080 FLAGS_FAN_FAILURE_DET_REQ);
8081 }
8082 return fan_failure_det_req;
8083}
8084
8085void bnx2x_hw_reset_phy(struct link_params *params)
8086{
8087 u8 phy_index;
8088 for (phy_index = EXT_PHY1; phy_index < MAX_PHYS;
8089 phy_index++) {
8090 if (params->phy[phy_index].hw_reset) {
8091 params->phy[phy_index].hw_reset(
8092 &params->phy[phy_index],
8093 params);
8094 params->phy[phy_index] = phy_null;
8095 }
8096 }
8097}