blob: b292aca0f342d53856ec3eaf982b71fd8b0a7fa8 [file] [log] [blame]
Jerome Glisse771fe6b2009-06-05 14:42:42 +02001/*
2 * Copyright 2009 Jerome Glisse.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sub license, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
12 *
13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
14 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
15 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
16 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
17 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
18 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
19 * USE OR OTHER DEALINGS IN THE SOFTWARE.
20 *
21 * The above copyright notice and this permission notice (including the
22 * next paragraph) shall be included in all copies or substantial portions
23 * of the Software.
24 *
25 */
26/*
27 * Authors:
28 * Jerome Glisse <glisse@freedesktop.org>
29 * Thomas Hellstrom <thomas-at-tungstengraphics-dot-com>
30 * Dave Airlie
31 */
32#include <ttm/ttm_bo_api.h>
33#include <ttm/ttm_bo_driver.h>
34#include <ttm/ttm_placement.h>
35#include <ttm/ttm_module.h>
Pauli Nieminen8d7cddc2010-04-01 12:44:59 +000036#include <ttm/ttm_page_alloc.h>
Jerome Glisse771fe6b2009-06-05 14:42:42 +020037#include <drm/drmP.h>
38#include <drm/radeon_drm.h>
Dave Airliefa8a1232009-08-26 13:13:37 +100039#include <linux/seq_file.h>
Tejun Heo5a0e3ad2010-03-24 17:04:11 +090040#include <linux/slab.h>
Chris Metcalf4cfe7622013-02-01 13:44:33 -050041#include <linux/swiotlb.h>
Christian Königf72a113a2014-08-07 09:36:00 +020042#include <linux/swap.h>
43#include <linux/pagemap.h>
Christian König2014b562013-12-18 21:07:39 +010044#include <linux/debugfs.h>
Jerome Glisse771fe6b2009-06-05 14:42:42 +020045#include "radeon_reg.h"
46#include "radeon.h"
47
48#define DRM_FILE_PAGE_OFFSET (0x100000000ULL >> PAGE_SHIFT)
49
Dave Airliefa8a1232009-08-26 13:13:37 +100050static int radeon_ttm_debugfs_init(struct radeon_device *rdev);
Christian König2014b562013-12-18 21:07:39 +010051static void radeon_ttm_debugfs_fini(struct radeon_device *rdev);
Dave Airliefa8a1232009-08-26 13:13:37 +100052
Jerome Glisse771fe6b2009-06-05 14:42:42 +020053static struct radeon_device *radeon_get_rdev(struct ttm_bo_device *bdev)
54{
55 struct radeon_mman *mman;
56 struct radeon_device *rdev;
57
58 mman = container_of(bdev, struct radeon_mman, bdev);
59 rdev = container_of(mman, struct radeon_device, mman);
60 return rdev;
61}
62
63
64/*
65 * Global memory.
66 */
Dave Airlieba4420c2010-03-09 10:56:52 +100067static int radeon_ttm_mem_global_init(struct drm_global_reference *ref)
Jerome Glisse771fe6b2009-06-05 14:42:42 +020068{
69 return ttm_mem_global_init(ref->object);
70}
71
Dave Airlieba4420c2010-03-09 10:56:52 +100072static void radeon_ttm_mem_global_release(struct drm_global_reference *ref)
Jerome Glisse771fe6b2009-06-05 14:42:42 +020073{
74 ttm_mem_global_release(ref->object);
75}
76
77static int radeon_ttm_global_init(struct radeon_device *rdev)
78{
Dave Airlieba4420c2010-03-09 10:56:52 +100079 struct drm_global_reference *global_ref;
Jerome Glisse771fe6b2009-06-05 14:42:42 +020080 int r;
81
82 rdev->mman.mem_global_referenced = false;
83 global_ref = &rdev->mman.mem_global_ref;
Dave Airlieba4420c2010-03-09 10:56:52 +100084 global_ref->global_type = DRM_GLOBAL_TTM_MEM;
Jerome Glisse771fe6b2009-06-05 14:42:42 +020085 global_ref->size = sizeof(struct ttm_mem_global);
86 global_ref->init = &radeon_ttm_mem_global_init;
87 global_ref->release = &radeon_ttm_mem_global_release;
Dave Airlieba4420c2010-03-09 10:56:52 +100088 r = drm_global_item_ref(global_ref);
Jerome Glisse771fe6b2009-06-05 14:42:42 +020089 if (r != 0) {
Thomas Hellstroma987fca2009-08-18 16:51:56 +020090 DRM_ERROR("Failed setting up TTM memory accounting "
91 "subsystem.\n");
Jerome Glisse771fe6b2009-06-05 14:42:42 +020092 return r;
93 }
Thomas Hellstroma987fca2009-08-18 16:51:56 +020094
95 rdev->mman.bo_global_ref.mem_glob =
96 rdev->mman.mem_global_ref.object;
97 global_ref = &rdev->mman.bo_global_ref.ref;
Dave Airlieba4420c2010-03-09 10:56:52 +100098 global_ref->global_type = DRM_GLOBAL_TTM_BO;
Thomas Hellstrom7f5f4db2009-08-20 10:29:08 +020099 global_ref->size = sizeof(struct ttm_bo_global);
Thomas Hellstroma987fca2009-08-18 16:51:56 +0200100 global_ref->init = &ttm_bo_global_init;
101 global_ref->release = &ttm_bo_global_release;
Dave Airlieba4420c2010-03-09 10:56:52 +1000102 r = drm_global_item_ref(global_ref);
Thomas Hellstroma987fca2009-08-18 16:51:56 +0200103 if (r != 0) {
104 DRM_ERROR("Failed setting up TTM BO subsystem.\n");
Dave Airlieba4420c2010-03-09 10:56:52 +1000105 drm_global_item_unref(&rdev->mman.mem_global_ref);
Thomas Hellstroma987fca2009-08-18 16:51:56 +0200106 return r;
107 }
108
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200109 rdev->mman.mem_global_referenced = true;
110 return 0;
111}
112
113static void radeon_ttm_global_fini(struct radeon_device *rdev)
114{
115 if (rdev->mman.mem_global_referenced) {
Dave Airlieba4420c2010-03-09 10:56:52 +1000116 drm_global_item_unref(&rdev->mman.bo_global_ref.ref);
117 drm_global_item_unref(&rdev->mman.mem_global_ref);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200118 rdev->mman.mem_global_referenced = false;
119 }
120}
121
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200122static int radeon_invalidate_caches(struct ttm_bo_device *bdev, uint32_t flags)
123{
124 return 0;
125}
126
127static int radeon_init_mem_type(struct ttm_bo_device *bdev, uint32_t type,
128 struct ttm_mem_type_manager *man)
129{
130 struct radeon_device *rdev;
131
132 rdev = radeon_get_rdev(bdev);
133
134 switch (type) {
135 case TTM_PL_SYSTEM:
136 /* System memory */
137 man->flags = TTM_MEMTYPE_FLAG_MAPPABLE;
138 man->available_caching = TTM_PL_MASK_CACHING;
139 man->default_caching = TTM_PL_FLAG_CACHED;
140 break;
141 case TTM_PL_TT:
Ben Skeggsd961db72010-08-05 10:48:18 +1000142 man->func = &ttm_bo_manager_func;
Jerome Glissed594e462010-02-17 21:54:29 +0000143 man->gpu_offset = rdev->mc.gtt_start;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200144 man->available_caching = TTM_PL_MASK_CACHING;
145 man->default_caching = TTM_PL_FLAG_CACHED;
Michel Dänzer55c93272009-06-15 16:56:11 +0200146 man->flags = TTM_MEMTYPE_FLAG_MAPPABLE | TTM_MEMTYPE_FLAG_CMA;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200147#if __OS_HAS_AGP
148 if (rdev->flags & RADEON_IS_AGP) {
Daniel Vetterd9906752013-12-11 11:34:35 +0100149 if (!rdev->ddev->agp) {
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200150 DRM_ERROR("AGP is not enabled for memory type %u\n",
151 (unsigned)type);
152 return -EINVAL;
153 }
Michel Dänzer55c93272009-06-15 16:56:11 +0200154 if (!rdev->ddev->agp->cant_use_aperture)
Jerome Glisse0a2d50e2010-04-09 14:39:24 +0200155 man->flags = TTM_MEMTYPE_FLAG_MAPPABLE;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200156 man->available_caching = TTM_PL_FLAG_UNCACHED |
157 TTM_PL_FLAG_WC;
158 man->default_caching = TTM_PL_FLAG_WC;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200159 }
Jerome Glisse0c321c72010-04-07 10:21:27 +0000160#endif
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200161 break;
162 case TTM_PL_VRAM:
163 /* "On-card" video ram */
Ben Skeggsd961db72010-08-05 10:48:18 +1000164 man->func = &ttm_bo_manager_func;
Jerome Glissed594e462010-02-17 21:54:29 +0000165 man->gpu_offset = rdev->mc.vram_start;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200166 man->flags = TTM_MEMTYPE_FLAG_FIXED |
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200167 TTM_MEMTYPE_FLAG_MAPPABLE;
168 man->available_caching = TTM_PL_FLAG_UNCACHED | TTM_PL_FLAG_WC;
169 man->default_caching = TTM_PL_FLAG_WC;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200170 break;
171 default:
172 DRM_ERROR("Unsupported memory type %u\n", (unsigned)type);
173 return -EINVAL;
174 }
175 return 0;
176}
177
Jerome Glisse312ea8d2009-12-07 15:52:58 +0100178static void radeon_evict_flags(struct ttm_buffer_object *bo,
179 struct ttm_placement *placement)
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200180{
Christian Königf1217ed2014-08-27 13:16:04 +0200181 static struct ttm_place placements = {
182 .fpfn = 0,
183 .lpfn = 0,
184 .flags = TTM_PL_MASK_CACHING | TTM_PL_FLAG_SYSTEM
185 };
186
Jerome Glissed03d8582009-12-14 21:02:09 +0100187 struct radeon_bo *rbo;
Jerome Glissed03d8582009-12-14 21:02:09 +0100188
189 if (!radeon_ttm_bo_is_radeon_bo(bo)) {
Jerome Glissed03d8582009-12-14 21:02:09 +0100190 placement->placement = &placements;
191 placement->busy_placement = &placements;
192 placement->num_placement = 1;
193 placement->num_busy_placement = 1;
194 return;
195 }
196 rbo = container_of(bo, struct radeon_bo, tbo);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200197 switch (bo->mem.mem_type) {
Jerome Glisse312ea8d2009-12-07 15:52:58 +0100198 case TTM_PL_VRAM:
Alex Deucher5e5c21c2014-12-03 00:03:49 -0500199 if (rbo->rdev->ring[radeon_copy_ring_index(rbo->rdev)].ready == false)
Dave Airlie9270eb12010-01-13 09:21:49 +1000200 radeon_ttm_placement_from_domain(rbo, RADEON_GEM_DOMAIN_CPU);
Michel Dänzer2a85aed2014-10-09 18:55:04 +0900201 else if (rbo->rdev->mc.visible_vram_size < rbo->rdev->mc.real_vram_size &&
202 bo->mem.start < (rbo->rdev->mc.visible_vram_size >> PAGE_SHIFT)) {
203 unsigned fpfn = rbo->rdev->mc.visible_vram_size >> PAGE_SHIFT;
204 int i;
205
206 /* Try evicting to the CPU inaccessible part of VRAM
207 * first, but only set GTT as busy placement, so this
208 * BO will be evicted to GTT rather than causing other
209 * BOs to be evicted from VRAM
210 */
211 radeon_ttm_placement_from_domain(rbo, RADEON_GEM_DOMAIN_VRAM |
212 RADEON_GEM_DOMAIN_GTT);
213 rbo->placement.num_busy_placement = 0;
214 for (i = 0; i < rbo->placement.num_placement; i++) {
215 if (rbo->placements[i].flags & TTM_PL_FLAG_VRAM) {
216 if (rbo->placements[0].fpfn < fpfn)
217 rbo->placements[0].fpfn = fpfn;
218 } else {
219 rbo->placement.busy_placement =
220 &rbo->placements[i];
221 rbo->placement.num_busy_placement = 1;
222 }
223 }
224 } else
Dave Airlie9270eb12010-01-13 09:21:49 +1000225 radeon_ttm_placement_from_domain(rbo, RADEON_GEM_DOMAIN_GTT);
Jerome Glisse312ea8d2009-12-07 15:52:58 +0100226 break;
227 case TTM_PL_TT:
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200228 default:
Jerome Glisse312ea8d2009-12-07 15:52:58 +0100229 radeon_ttm_placement_from_domain(rbo, RADEON_GEM_DOMAIN_CPU);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200230 }
Jerome Glisseeaa5fd12009-12-09 21:57:37 +0100231 *placement = rbo->placement;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200232}
233
234static int radeon_verify_access(struct ttm_buffer_object *bo, struct file *filp)
235{
David Herrmannacb46522013-08-25 18:28:59 +0200236 struct radeon_bo *rbo = container_of(bo, struct radeon_bo, tbo);
237
238 return drm_vma_node_verify_access(&rbo->gem_base.vma_node, filp);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200239}
240
241static void radeon_move_null(struct ttm_buffer_object *bo,
242 struct ttm_mem_reg *new_mem)
243{
244 struct ttm_mem_reg *old_mem = &bo->mem;
245
246 BUG_ON(old_mem->mm_node != NULL);
247 *old_mem = *new_mem;
248 new_mem->mm_node = NULL;
249}
250
251static int radeon_move_blit(struct ttm_buffer_object *bo,
Maarten Lankhorst97a875c2012-11-28 11:25:44 +0000252 bool evict, bool no_wait_gpu,
Jerome Glisse9d87fa22010-04-07 10:21:19 +0000253 struct ttm_mem_reg *new_mem,
254 struct ttm_mem_reg *old_mem)
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200255{
256 struct radeon_device *rdev;
257 uint64_t old_start, new_start;
Christian König876dc9f2012-05-08 14:24:01 +0200258 struct radeon_fence *fence;
Christian König57d20a42014-09-04 20:01:53 +0200259 unsigned num_pages;
Christian König876dc9f2012-05-08 14:24:01 +0200260 int r, ridx;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200261
262 rdev = radeon_get_rdev(bo->bdev);
Christian König876dc9f2012-05-08 14:24:01 +0200263 ridx = radeon_copy_ring_index(rdev);
Ben Skeggsd961db72010-08-05 10:48:18 +1000264 old_start = old_mem->start << PAGE_SHIFT;
265 new_start = new_mem->start << PAGE_SHIFT;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200266
267 switch (old_mem->mem_type) {
268 case TTM_PL_VRAM:
Jerome Glissed594e462010-02-17 21:54:29 +0000269 old_start += rdev->mc.vram_start;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200270 break;
271 case TTM_PL_TT:
Jerome Glissed594e462010-02-17 21:54:29 +0000272 old_start += rdev->mc.gtt_start;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200273 break;
274 default:
275 DRM_ERROR("Unknown placement %d\n", old_mem->mem_type);
276 return -EINVAL;
277 }
278 switch (new_mem->mem_type) {
279 case TTM_PL_VRAM:
Jerome Glissed594e462010-02-17 21:54:29 +0000280 new_start += rdev->mc.vram_start;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200281 break;
282 case TTM_PL_TT:
Jerome Glissed594e462010-02-17 21:54:29 +0000283 new_start += rdev->mc.gtt_start;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200284 break;
285 default:
286 DRM_ERROR("Unknown placement %d\n", old_mem->mem_type);
287 return -EINVAL;
288 }
Christian König876dc9f2012-05-08 14:24:01 +0200289 if (!rdev->ring[ridx].ready) {
Alex Deucher3000bf32012-01-05 22:11:07 -0500290 DRM_ERROR("Trying to move memory with ring turned off.\n");
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200291 return -EINVAL;
292 }
Alex Deucher003cefe2011-09-16 12:04:08 -0400293
294 BUILD_BUG_ON((PAGE_SIZE % RADEON_GPU_PAGE_SIZE) != 0);
295
Christian König57d20a42014-09-04 20:01:53 +0200296 num_pages = new_mem->num_pages * (PAGE_SIZE / RADEON_GPU_PAGE_SIZE);
297 fence = radeon_copy(rdev, old_start, new_start, num_pages, bo->resv);
298 if (IS_ERR(fence))
299 return PTR_ERR(fence);
300
Maarten Lankhorstf2c24b82014-04-02 17:14:48 +0200301 r = ttm_bo_move_accel_cleanup(bo, &fence->base,
Maarten Lankhorst97a875c2012-11-28 11:25:44 +0000302 evict, no_wait_gpu, new_mem);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200303 radeon_fence_unref(&fence);
304 return r;
305}
306
307static int radeon_move_vram_ram(struct ttm_buffer_object *bo,
Jerome Glisse9d87fa22010-04-07 10:21:19 +0000308 bool evict, bool interruptible,
Maarten Lankhorst97a875c2012-11-28 11:25:44 +0000309 bool no_wait_gpu,
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200310 struct ttm_mem_reg *new_mem)
311{
312 struct radeon_device *rdev;
313 struct ttm_mem_reg *old_mem = &bo->mem;
314 struct ttm_mem_reg tmp_mem;
Christian Königf1217ed2014-08-27 13:16:04 +0200315 struct ttm_place placements;
Jerome Glisse312ea8d2009-12-07 15:52:58 +0100316 struct ttm_placement placement;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200317 int r;
318
319 rdev = radeon_get_rdev(bo->bdev);
320 tmp_mem = *new_mem;
321 tmp_mem.mm_node = NULL;
Jerome Glisse312ea8d2009-12-07 15:52:58 +0100322 placement.num_placement = 1;
323 placement.placement = &placements;
324 placement.num_busy_placement = 1;
325 placement.busy_placement = &placements;
Christian Königf1217ed2014-08-27 13:16:04 +0200326 placements.fpfn = 0;
327 placements.lpfn = 0;
328 placements.flags = TTM_PL_MASK_CACHING | TTM_PL_FLAG_TT;
Jerome Glisse312ea8d2009-12-07 15:52:58 +0100329 r = ttm_bo_mem_space(bo, &placement, &tmp_mem,
Maarten Lankhorst97a875c2012-11-28 11:25:44 +0000330 interruptible, no_wait_gpu);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200331 if (unlikely(r)) {
332 return r;
333 }
Dave Airliedf67bed2009-10-30 13:31:26 +1000334
335 r = ttm_tt_set_placement_caching(bo->ttm, tmp_mem.placement);
336 if (unlikely(r)) {
337 goto out_cleanup;
338 }
339
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200340 r = ttm_tt_bind(bo->ttm, &tmp_mem);
341 if (unlikely(r)) {
342 goto out_cleanup;
343 }
Maarten Lankhorst97a875c2012-11-28 11:25:44 +0000344 r = radeon_move_blit(bo, true, no_wait_gpu, &tmp_mem, old_mem);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200345 if (unlikely(r)) {
346 goto out_cleanup;
347 }
Maarten Lankhorst97a875c2012-11-28 11:25:44 +0000348 r = ttm_bo_move_ttm(bo, true, no_wait_gpu, new_mem);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200349out_cleanup:
Ben Skeggs42311ff2010-08-04 12:07:08 +1000350 ttm_bo_mem_put(bo, &tmp_mem);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200351 return r;
352}
353
354static int radeon_move_ram_vram(struct ttm_buffer_object *bo,
Jerome Glisse9d87fa22010-04-07 10:21:19 +0000355 bool evict, bool interruptible,
Maarten Lankhorst97a875c2012-11-28 11:25:44 +0000356 bool no_wait_gpu,
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200357 struct ttm_mem_reg *new_mem)
358{
359 struct radeon_device *rdev;
360 struct ttm_mem_reg *old_mem = &bo->mem;
361 struct ttm_mem_reg tmp_mem;
Jerome Glisse312ea8d2009-12-07 15:52:58 +0100362 struct ttm_placement placement;
Christian Königf1217ed2014-08-27 13:16:04 +0200363 struct ttm_place placements;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200364 int r;
365
366 rdev = radeon_get_rdev(bo->bdev);
367 tmp_mem = *new_mem;
368 tmp_mem.mm_node = NULL;
Jerome Glisse312ea8d2009-12-07 15:52:58 +0100369 placement.num_placement = 1;
370 placement.placement = &placements;
371 placement.num_busy_placement = 1;
372 placement.busy_placement = &placements;
Christian Königf1217ed2014-08-27 13:16:04 +0200373 placements.fpfn = 0;
374 placements.lpfn = 0;
375 placements.flags = TTM_PL_MASK_CACHING | TTM_PL_FLAG_TT;
Maarten Lankhorst97a875c2012-11-28 11:25:44 +0000376 r = ttm_bo_mem_space(bo, &placement, &tmp_mem,
377 interruptible, no_wait_gpu);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200378 if (unlikely(r)) {
379 return r;
380 }
Maarten Lankhorst97a875c2012-11-28 11:25:44 +0000381 r = ttm_bo_move_ttm(bo, true, no_wait_gpu, &tmp_mem);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200382 if (unlikely(r)) {
383 goto out_cleanup;
384 }
Maarten Lankhorst97a875c2012-11-28 11:25:44 +0000385 r = radeon_move_blit(bo, true, no_wait_gpu, new_mem, old_mem);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200386 if (unlikely(r)) {
387 goto out_cleanup;
388 }
389out_cleanup:
Ben Skeggs42311ff2010-08-04 12:07:08 +1000390 ttm_bo_mem_put(bo, &tmp_mem);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200391 return r;
392}
393
394static int radeon_bo_move(struct ttm_buffer_object *bo,
Jerome Glisse9d87fa22010-04-07 10:21:19 +0000395 bool evict, bool interruptible,
Maarten Lankhorst97a875c2012-11-28 11:25:44 +0000396 bool no_wait_gpu,
Jerome Glisse9d87fa22010-04-07 10:21:19 +0000397 struct ttm_mem_reg *new_mem)
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200398{
399 struct radeon_device *rdev;
400 struct ttm_mem_reg *old_mem = &bo->mem;
401 int r;
402
403 rdev = radeon_get_rdev(bo->bdev);
404 if (old_mem->mem_type == TTM_PL_SYSTEM && bo->ttm == NULL) {
405 radeon_move_null(bo, new_mem);
406 return 0;
407 }
408 if ((old_mem->mem_type == TTM_PL_TT &&
409 new_mem->mem_type == TTM_PL_SYSTEM) ||
410 (old_mem->mem_type == TTM_PL_SYSTEM &&
411 new_mem->mem_type == TTM_PL_TT)) {
André Goddard Rosaaf901ca2009-11-14 13:09:05 -0200412 /* bind is enough */
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200413 radeon_move_null(bo, new_mem);
414 return 0;
415 }
Alex Deucher27cd7762012-02-23 17:53:42 -0500416 if (!rdev->ring[radeon_copy_ring_index(rdev)].ready ||
417 rdev->asic->copy.copy == NULL) {
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200418 /* use memcpy */
Michel Dänzer1ab2e102009-07-28 12:30:56 +0200419 goto memcpy;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200420 }
421
422 if (old_mem->mem_type == TTM_PL_VRAM &&
423 new_mem->mem_type == TTM_PL_SYSTEM) {
Michel Dänzer1ab2e102009-07-28 12:30:56 +0200424 r = radeon_move_vram_ram(bo, evict, interruptible,
Maarten Lankhorst97a875c2012-11-28 11:25:44 +0000425 no_wait_gpu, new_mem);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200426 } else if (old_mem->mem_type == TTM_PL_SYSTEM &&
427 new_mem->mem_type == TTM_PL_VRAM) {
Michel Dänzer1ab2e102009-07-28 12:30:56 +0200428 r = radeon_move_ram_vram(bo, evict, interruptible,
Maarten Lankhorst97a875c2012-11-28 11:25:44 +0000429 no_wait_gpu, new_mem);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200430 } else {
Maarten Lankhorst97a875c2012-11-28 11:25:44 +0000431 r = radeon_move_blit(bo, evict, no_wait_gpu, new_mem, old_mem);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200432 }
Michel Dänzer1ab2e102009-07-28 12:30:56 +0200433
434 if (r) {
435memcpy:
Maarten Lankhorst97a875c2012-11-28 11:25:44 +0000436 r = ttm_bo_move_memcpy(bo, evict, no_wait_gpu, new_mem);
Marek Olšák67e8e3f2014-03-02 00:56:18 +0100437 if (r) {
438 return r;
439 }
Michel Dänzer1ab2e102009-07-28 12:30:56 +0200440 }
Marek Olšák67e8e3f2014-03-02 00:56:18 +0100441
442 /* update statistics */
443 atomic64_add((u64)bo->num_pages << PAGE_SHIFT, &rdev->num_bytes_moved);
444 return 0;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200445}
446
Jerome Glisse0a2d50e2010-04-09 14:39:24 +0200447static int radeon_ttm_io_mem_reserve(struct ttm_bo_device *bdev, struct ttm_mem_reg *mem)
448{
449 struct ttm_mem_type_manager *man = &bdev->man[mem->mem_type];
450 struct radeon_device *rdev = radeon_get_rdev(bdev);
451
452 mem->bus.addr = NULL;
453 mem->bus.offset = 0;
454 mem->bus.size = mem->num_pages << PAGE_SHIFT;
455 mem->bus.base = 0;
456 mem->bus.is_iomem = false;
457 if (!(man->flags & TTM_MEMTYPE_FLAG_MAPPABLE))
458 return -EINVAL;
459 switch (mem->mem_type) {
460 case TTM_PL_SYSTEM:
461 /* system memory */
462 return 0;
463 case TTM_PL_TT:
464#if __OS_HAS_AGP
465 if (rdev->flags & RADEON_IS_AGP) {
466 /* RADEON_IS_AGP is set only if AGP is active */
Ben Skeggsd961db72010-08-05 10:48:18 +1000467 mem->bus.offset = mem->start << PAGE_SHIFT;
Jerome Glisse0a2d50e2010-04-09 14:39:24 +0200468 mem->bus.base = rdev->mc.agp_base;
Michel Dänzer365048f2010-05-19 12:46:22 +0200469 mem->bus.is_iomem = !rdev->ddev->agp->cant_use_aperture;
Jerome Glisse0a2d50e2010-04-09 14:39:24 +0200470 }
471#endif
472 break;
473 case TTM_PL_VRAM:
Ben Skeggsd961db72010-08-05 10:48:18 +1000474 mem->bus.offset = mem->start << PAGE_SHIFT;
Jerome Glisse0a2d50e2010-04-09 14:39:24 +0200475 /* check if it's visible */
476 if ((mem->bus.offset + mem->bus.size) > rdev->mc.visible_vram_size)
477 return -EINVAL;
478 mem->bus.base = rdev->mc.aper_base;
479 mem->bus.is_iomem = true;
Jay Estabrookffb57c42011-07-06 23:57:13 +0000480#ifdef __alpha__
481 /*
482 * Alpha: use bus.addr to hold the ioremap() return,
483 * so we can modify bus.base below.
484 */
485 if (mem->placement & TTM_PL_FLAG_WC)
486 mem->bus.addr =
487 ioremap_wc(mem->bus.base + mem->bus.offset,
488 mem->bus.size);
489 else
490 mem->bus.addr =
491 ioremap_nocache(mem->bus.base + mem->bus.offset,
492 mem->bus.size);
493
494 /*
495 * Alpha: Use just the bus offset plus
496 * the hose/domain memory base for bus.base.
497 * It then can be used to build PTEs for VRAM
498 * access, as done in ttm_bo_vm_fault().
499 */
500 mem->bus.base = (mem->bus.base & 0x0ffffffffUL) +
501 rdev->ddev->hose->dense_mem_base;
502#endif
Jerome Glisse0a2d50e2010-04-09 14:39:24 +0200503 break;
504 default:
505 return -EINVAL;
506 }
507 return 0;
508}
509
510static void radeon_ttm_io_mem_free(struct ttm_bo_device *bdev, struct ttm_mem_reg *mem)
511{
512}
513
Jerome Glisse649bf3c2011-11-01 20:46:13 -0400514/*
515 * TTM backend functions.
516 */
517struct radeon_ttm_tt {
Jerome Glisse8e7e7052011-11-09 17:15:26 -0500518 struct ttm_dma_tt ttm;
Jerome Glisse649bf3c2011-11-01 20:46:13 -0400519 struct radeon_device *rdev;
520 u64 offset;
Christian Königf72a113a2014-08-07 09:36:00 +0200521
522 uint64_t userptr;
523 struct mm_struct *usermm;
524 uint32_t userflags;
Jerome Glisse649bf3c2011-11-01 20:46:13 -0400525};
526
Christian Königf72a113a2014-08-07 09:36:00 +0200527/* prepare the sg table with the user pages */
528static int radeon_ttm_tt_pin_userptr(struct ttm_tt *ttm)
529{
530 struct radeon_device *rdev = radeon_get_rdev(ttm->bdev);
531 struct radeon_ttm_tt *gtt = (void *)ttm;
532 unsigned pinned = 0, nents;
533 int r;
534
535 int write = !(gtt->userflags & RADEON_GEM_USERPTR_READONLY);
536 enum dma_data_direction direction = write ?
537 DMA_BIDIRECTIONAL : DMA_TO_DEVICE;
538
539 if (current->mm != gtt->usermm)
540 return -EPERM;
541
Christian Königddd00e32014-08-07 09:36:01 +0200542 if (gtt->userflags & RADEON_GEM_USERPTR_ANONONLY) {
543 /* check that we only pin down anonymous memory
544 to prevent problems with writeback */
545 unsigned long end = gtt->userptr + ttm->num_pages * PAGE_SIZE;
546 struct vm_area_struct *vma;
547 vma = find_vma(gtt->usermm, gtt->userptr);
548 if (!vma || vma->vm_file || vma->vm_end < end)
549 return -EPERM;
550 }
551
Christian Königf72a113a2014-08-07 09:36:00 +0200552 do {
553 unsigned num_pages = ttm->num_pages - pinned;
554 uint64_t userptr = gtt->userptr + pinned * PAGE_SIZE;
555 struct page **pages = ttm->pages + pinned;
556
557 r = get_user_pages(current, current->mm, userptr, num_pages,
558 write, 0, pages, NULL);
559 if (r < 0)
560 goto release_pages;
561
562 pinned += r;
563
564 } while (pinned < ttm->num_pages);
565
566 r = sg_alloc_table_from_pages(ttm->sg, ttm->pages, ttm->num_pages, 0,
567 ttm->num_pages << PAGE_SHIFT,
568 GFP_KERNEL);
569 if (r)
570 goto release_sg;
571
572 r = -ENOMEM;
573 nents = dma_map_sg(rdev->dev, ttm->sg->sgl, ttm->sg->nents, direction);
574 if (nents != ttm->sg->nents)
575 goto release_sg;
576
577 drm_prime_sg_to_page_addr_arrays(ttm->sg, ttm->pages,
578 gtt->ttm.dma_address, ttm->num_pages);
579
580 return 0;
581
582release_sg:
583 kfree(ttm->sg);
584
585release_pages:
586 release_pages(ttm->pages, pinned, 0);
587 return r;
588}
589
590static void radeon_ttm_tt_unpin_userptr(struct ttm_tt *ttm)
591{
592 struct radeon_device *rdev = radeon_get_rdev(ttm->bdev);
593 struct radeon_ttm_tt *gtt = (void *)ttm;
594 struct scatterlist *sg;
595 int i;
596
597 int write = !(gtt->userflags & RADEON_GEM_USERPTR_READONLY);
598 enum dma_data_direction direction = write ?
599 DMA_BIDIRECTIONAL : DMA_TO_DEVICE;
600
Christian König863653f2015-03-31 17:36:57 +0200601 /* double check that we don't free the table twice */
602 if (!ttm->sg->sgl)
603 return;
604
Christian Königf72a113a2014-08-07 09:36:00 +0200605 /* free the sg table and pages again */
606 dma_unmap_sg(rdev->dev, ttm->sg->sgl, ttm->sg->nents, direction);
607
608 for_each_sg(ttm->sg->sgl, sg, ttm->sg->nents, i) {
609 struct page *page = sg_page(sg);
610
611 if (!(gtt->userflags & RADEON_GEM_USERPTR_READONLY))
612 set_page_dirty(page);
613
614 mark_page_accessed(page);
615 page_cache_release(page);
616 }
617
618 sg_free_table(ttm->sg);
619}
620
Jerome Glisse649bf3c2011-11-01 20:46:13 -0400621static int radeon_ttm_backend_bind(struct ttm_tt *ttm,
622 struct ttm_mem_reg *bo_mem)
623{
Jerome Glisse8e7e7052011-11-09 17:15:26 -0500624 struct radeon_ttm_tt *gtt = (void*)ttm;
Michel Dänzer77497f22014-07-17 19:01:07 +0900625 uint32_t flags = RADEON_GART_PAGE_VALID | RADEON_GART_PAGE_READ |
626 RADEON_GART_PAGE_WRITE;
Jerome Glisse649bf3c2011-11-01 20:46:13 -0400627 int r;
628
Christian Königf72a113a2014-08-07 09:36:00 +0200629 if (gtt->userptr) {
630 radeon_ttm_tt_pin_userptr(ttm);
631 flags &= ~RADEON_GART_PAGE_WRITE;
632 }
633
Jerome Glisse649bf3c2011-11-01 20:46:13 -0400634 gtt->offset = (unsigned long)(bo_mem->start << PAGE_SHIFT);
635 if (!ttm->num_pages) {
636 WARN(1, "nothing to bind %lu pages for mreg %p back %p!\n",
637 ttm->num_pages, bo_mem, ttm);
638 }
Michel Dänzer77497f22014-07-17 19:01:07 +0900639 if (ttm->caching_state == tt_cached)
640 flags |= RADEON_GART_PAGE_SNOOP;
641 r = radeon_gart_bind(gtt->rdev, gtt->offset, ttm->num_pages,
642 ttm->pages, gtt->ttm.dma_address, flags);
Jerome Glisse649bf3c2011-11-01 20:46:13 -0400643 if (r) {
644 DRM_ERROR("failed to bind %lu pages at 0x%08X\n",
645 ttm->num_pages, (unsigned)gtt->offset);
646 return r;
647 }
648 return 0;
649}
650
651static int radeon_ttm_backend_unbind(struct ttm_tt *ttm)
652{
Jerome Glisse8e7e7052011-11-09 17:15:26 -0500653 struct radeon_ttm_tt *gtt = (void *)ttm;
Jerome Glisse649bf3c2011-11-01 20:46:13 -0400654
Jerome Glisse649bf3c2011-11-01 20:46:13 -0400655 radeon_gart_unbind(gtt->rdev, gtt->offset, ttm->num_pages);
Christian Königf72a113a2014-08-07 09:36:00 +0200656
657 if (gtt->userptr)
658 radeon_ttm_tt_unpin_userptr(ttm);
659
Jerome Glisse649bf3c2011-11-01 20:46:13 -0400660 return 0;
661}
662
663static void radeon_ttm_backend_destroy(struct ttm_tt *ttm)
664{
Jerome Glisse8e7e7052011-11-09 17:15:26 -0500665 struct radeon_ttm_tt *gtt = (void *)ttm;
Jerome Glisse649bf3c2011-11-01 20:46:13 -0400666
Jerome Glisse8e7e7052011-11-09 17:15:26 -0500667 ttm_dma_tt_fini(&gtt->ttm);
Jerome Glisse649bf3c2011-11-01 20:46:13 -0400668 kfree(gtt);
669}
670
671static struct ttm_backend_func radeon_backend_func = {
672 .bind = &radeon_ttm_backend_bind,
673 .unbind = &radeon_ttm_backend_unbind,
674 .destroy = &radeon_ttm_backend_destroy,
675};
676
Lauri Kasanen1109ca02012-08-31 13:43:50 -0400677static struct ttm_tt *radeon_ttm_tt_create(struct ttm_bo_device *bdev,
Jerome Glisse649bf3c2011-11-01 20:46:13 -0400678 unsigned long size, uint32_t page_flags,
679 struct page *dummy_read_page)
680{
681 struct radeon_device *rdev;
682 struct radeon_ttm_tt *gtt;
683
684 rdev = radeon_get_rdev(bdev);
685#if __OS_HAS_AGP
686 if (rdev->flags & RADEON_IS_AGP) {
687 return ttm_agp_tt_create(bdev, rdev->ddev->agp->bridge,
688 size, page_flags, dummy_read_page);
689 }
690#endif
691
692 gtt = kzalloc(sizeof(struct radeon_ttm_tt), GFP_KERNEL);
693 if (gtt == NULL) {
694 return NULL;
695 }
Jerome Glisse8e7e7052011-11-09 17:15:26 -0500696 gtt->ttm.ttm.func = &radeon_backend_func;
Jerome Glisse649bf3c2011-11-01 20:46:13 -0400697 gtt->rdev = rdev;
Jerome Glisse8e7e7052011-11-09 17:15:26 -0500698 if (ttm_dma_tt_init(&gtt->ttm, bdev, size, page_flags, dummy_read_page)) {
699 kfree(gtt);
Jerome Glisse649bf3c2011-11-01 20:46:13 -0400700 return NULL;
701 }
Jerome Glisse8e7e7052011-11-09 17:15:26 -0500702 return &gtt->ttm.ttm;
Jerome Glisse649bf3c2011-11-01 20:46:13 -0400703}
704
Christian König3840a652014-09-17 04:00:05 -0600705static struct radeon_ttm_tt *radeon_ttm_tt_to_gtt(struct ttm_tt *ttm)
706{
707 if (!ttm || ttm->func != &radeon_backend_func)
708 return NULL;
709 return (struct radeon_ttm_tt *)ttm;
710}
711
Konrad Rzeszutek Wilkc52494f2011-10-17 17:15:08 -0400712static int radeon_ttm_tt_populate(struct ttm_tt *ttm)
713{
Christian König3840a652014-09-17 04:00:05 -0600714 struct radeon_ttm_tt *gtt = radeon_ttm_tt_to_gtt(ttm);
Konrad Rzeszutek Wilkc52494f2011-10-17 17:15:08 -0400715 struct radeon_device *rdev;
716 unsigned i;
717 int r;
Alex Deucher40f5cf92012-05-10 18:33:13 -0400718 bool slave = !!(ttm->page_flags & TTM_PAGE_FLAG_SG);
Konrad Rzeszutek Wilkc52494f2011-10-17 17:15:08 -0400719
720 if (ttm->state != tt_unpopulated)
721 return 0;
722
Christian König3840a652014-09-17 04:00:05 -0600723 if (gtt && gtt->userptr) {
Christian Königf72a113a2014-08-07 09:36:00 +0200724 ttm->sg = kcalloc(1, sizeof(struct sg_table), GFP_KERNEL);
725 if (!ttm->sg)
726 return -ENOMEM;
727
728 ttm->page_flags |= TTM_PAGE_FLAG_SG;
729 ttm->state = tt_unbound;
730 return 0;
731 }
732
Alex Deucher40f5cf92012-05-10 18:33:13 -0400733 if (slave && ttm->sg) {
734 drm_prime_sg_to_page_addr_arrays(ttm->sg, ttm->pages,
735 gtt->ttm.dma_address, ttm->num_pages);
736 ttm->state = tt_unbound;
737 return 0;
738 }
739
Konrad Rzeszutek Wilkc52494f2011-10-17 17:15:08 -0400740 rdev = radeon_get_rdev(ttm->bdev);
Jerome Glissedea7e0a2012-01-03 17:37:37 -0500741#if __OS_HAS_AGP
742 if (rdev->flags & RADEON_IS_AGP) {
743 return ttm_agp_tt_populate(ttm);
744 }
745#endif
Konrad Rzeszutek Wilkc52494f2011-10-17 17:15:08 -0400746
747#ifdef CONFIG_SWIOTLB
748 if (swiotlb_nr_tbl()) {
Jerome Glisse8e7e7052011-11-09 17:15:26 -0500749 return ttm_dma_populate(&gtt->ttm, rdev->dev);
Konrad Rzeszutek Wilkc52494f2011-10-17 17:15:08 -0400750 }
751#endif
752
753 r = ttm_pool_populate(ttm);
754 if (r) {
755 return r;
756 }
757
758 for (i = 0; i < ttm->num_pages; i++) {
Jerome Glisse8e7e7052011-11-09 17:15:26 -0500759 gtt->ttm.dma_address[i] = pci_map_page(rdev->pdev, ttm->pages[i],
760 0, PAGE_SIZE,
761 PCI_DMA_BIDIRECTIONAL);
762 if (pci_dma_mapping_error(rdev->pdev, gtt->ttm.dma_address[i])) {
Konrad Rzeszutek Wilkc52494f2011-10-17 17:15:08 -0400763 while (--i) {
Jerome Glisse8e7e7052011-11-09 17:15:26 -0500764 pci_unmap_page(rdev->pdev, gtt->ttm.dma_address[i],
Konrad Rzeszutek Wilkc52494f2011-10-17 17:15:08 -0400765 PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
Jerome Glisse8e7e7052011-11-09 17:15:26 -0500766 gtt->ttm.dma_address[i] = 0;
Konrad Rzeszutek Wilkc52494f2011-10-17 17:15:08 -0400767 }
768 ttm_pool_unpopulate(ttm);
769 return -EFAULT;
770 }
771 }
772 return 0;
773}
774
775static void radeon_ttm_tt_unpopulate(struct ttm_tt *ttm)
776{
777 struct radeon_device *rdev;
Christian König3840a652014-09-17 04:00:05 -0600778 struct radeon_ttm_tt *gtt = radeon_ttm_tt_to_gtt(ttm);
Konrad Rzeszutek Wilkc52494f2011-10-17 17:15:08 -0400779 unsigned i;
Alex Deucher40f5cf92012-05-10 18:33:13 -0400780 bool slave = !!(ttm->page_flags & TTM_PAGE_FLAG_SG);
781
Christian König3840a652014-09-17 04:00:05 -0600782 if (gtt && gtt->userptr) {
Christian Königf72a113a2014-08-07 09:36:00 +0200783 kfree(ttm->sg);
784 ttm->page_flags &= ~TTM_PAGE_FLAG_SG;
785 return;
786 }
787
Alex Deucher40f5cf92012-05-10 18:33:13 -0400788 if (slave)
789 return;
Konrad Rzeszutek Wilkc52494f2011-10-17 17:15:08 -0400790
791 rdev = radeon_get_rdev(ttm->bdev);
Jerome Glissedea7e0a2012-01-03 17:37:37 -0500792#if __OS_HAS_AGP
793 if (rdev->flags & RADEON_IS_AGP) {
794 ttm_agp_tt_unpopulate(ttm);
795 return;
796 }
797#endif
Konrad Rzeszutek Wilkc52494f2011-10-17 17:15:08 -0400798
799#ifdef CONFIG_SWIOTLB
800 if (swiotlb_nr_tbl()) {
Jerome Glisse8e7e7052011-11-09 17:15:26 -0500801 ttm_dma_unpopulate(&gtt->ttm, rdev->dev);
Konrad Rzeszutek Wilkc52494f2011-10-17 17:15:08 -0400802 return;
803 }
804#endif
805
806 for (i = 0; i < ttm->num_pages; i++) {
Jerome Glisse8e7e7052011-11-09 17:15:26 -0500807 if (gtt->ttm.dma_address[i]) {
808 pci_unmap_page(rdev->pdev, gtt->ttm.dma_address[i],
Konrad Rzeszutek Wilkc52494f2011-10-17 17:15:08 -0400809 PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
810 }
811 }
812
813 ttm_pool_unpopulate(ttm);
814}
Jerome Glisse649bf3c2011-11-01 20:46:13 -0400815
Christian Königf72a113a2014-08-07 09:36:00 +0200816int radeon_ttm_tt_set_userptr(struct ttm_tt *ttm, uint64_t addr,
817 uint32_t flags)
818{
Christian König3840a652014-09-17 04:00:05 -0600819 struct radeon_ttm_tt *gtt = radeon_ttm_tt_to_gtt(ttm);
Christian Königf72a113a2014-08-07 09:36:00 +0200820
821 if (gtt == NULL)
822 return -EINVAL;
823
824 gtt->userptr = addr;
825 gtt->usermm = current->mm;
826 gtt->userflags = flags;
827 return 0;
828}
829
830bool radeon_ttm_tt_has_userptr(struct ttm_tt *ttm)
831{
Christian König3840a652014-09-17 04:00:05 -0600832 struct radeon_ttm_tt *gtt = radeon_ttm_tt_to_gtt(ttm);
Christian Königf72a113a2014-08-07 09:36:00 +0200833
834 if (gtt == NULL)
835 return false;
836
837 return !!gtt->userptr;
838}
839
840bool radeon_ttm_tt_is_readonly(struct ttm_tt *ttm)
841{
Christian König3840a652014-09-17 04:00:05 -0600842 struct radeon_ttm_tt *gtt = radeon_ttm_tt_to_gtt(ttm);
Christian Königf72a113a2014-08-07 09:36:00 +0200843
844 if (gtt == NULL)
845 return false;
846
847 return !!(gtt->userflags & RADEON_GEM_USERPTR_READONLY);
848}
849
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200850static struct ttm_bo_driver radeon_bo_driver = {
Jerome Glisse649bf3c2011-11-01 20:46:13 -0400851 .ttm_tt_create = &radeon_ttm_tt_create,
Konrad Rzeszutek Wilkc52494f2011-10-17 17:15:08 -0400852 .ttm_tt_populate = &radeon_ttm_tt_populate,
853 .ttm_tt_unpopulate = &radeon_ttm_tt_unpopulate,
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200854 .invalidate_caches = &radeon_invalidate_caches,
855 .init_mem_type = &radeon_init_mem_type,
856 .evict_flags = &radeon_evict_flags,
857 .move = &radeon_bo_move,
858 .verify_access = &radeon_verify_access,
Dave Airliee024e112009-06-24 09:48:08 +1000859 .move_notify = &radeon_bo_move_notify,
860 .fault_reserve_notify = &radeon_bo_fault_reserve_notify,
Jerome Glisse0a2d50e2010-04-09 14:39:24 +0200861 .io_mem_reserve = &radeon_ttm_io_mem_reserve,
862 .io_mem_free = &radeon_ttm_io_mem_free,
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200863};
864
865int radeon_ttm_init(struct radeon_device *rdev)
866{
867 int r;
868
869 r = radeon_ttm_global_init(rdev);
870 if (r) {
871 return r;
872 }
873 /* No others user of address space so set it to 0 */
874 r = ttm_bo_device_init(&rdev->mman.bdev,
Thomas Hellstroma987fca2009-08-18 16:51:56 +0200875 rdev->mman.bo_global_ref.ref.object,
David Herrmann44d847b2013-08-13 19:10:30 +0200876 &radeon_bo_driver,
877 rdev->ddev->anon_inode->i_mapping,
878 DRM_FILE_PAGE_OFFSET,
Dave Airliead49f502009-07-10 22:36:26 +1000879 rdev->need_dma32);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200880 if (r) {
881 DRM_ERROR("failed initializing buffer object driver(%d).\n", r);
882 return r;
883 }
Jerome Glisse0a0c7592009-12-11 20:36:19 +0100884 rdev->mman.initialized = true;
Jerome Glisse4c788672009-11-20 14:29:23 +0100885 r = ttm_bo_init_mm(&rdev->mman.bdev, TTM_PL_VRAM,
Jerome Glisse312ea8d2009-12-07 15:52:58 +0100886 rdev->mc.real_vram_size >> PAGE_SHIFT);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200887 if (r) {
888 DRM_ERROR("Failed initializing VRAM heap.\n");
889 return r;
890 }
Lauri Kasanen14eedc32014-02-28 20:50:23 +0200891 /* Change the size here instead of the init above so only lpfn is affected */
892 radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size);
893
Daniel Vetter441921d2011-02-18 17:59:16 +0100894 r = radeon_bo_create(rdev, 256 * 1024, PAGE_SIZE, true,
Maarten Lankhorst831b6962014-09-18 14:11:56 +0200895 RADEON_GEM_DOMAIN_VRAM, 0, NULL,
Alex Deucher40f5cf92012-05-10 18:33:13 -0400896 NULL, &rdev->stollen_vga_memory);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200897 if (r) {
898 return r;
899 }
Jerome Glisse4c788672009-11-20 14:29:23 +0100900 r = radeon_bo_reserve(rdev->stollen_vga_memory, false);
901 if (r)
902 return r;
903 r = radeon_bo_pin(rdev->stollen_vga_memory, RADEON_GEM_DOMAIN_VRAM, NULL);
904 radeon_bo_unreserve(rdev->stollen_vga_memory);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200905 if (r) {
Jerome Glisse4c788672009-11-20 14:29:23 +0100906 radeon_bo_unref(&rdev->stollen_vga_memory);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200907 return r;
908 }
909 DRM_INFO("radeon: %uM of VRAM memory ready\n",
Niels Ole Salscheiderfc986032013-05-18 21:19:23 +0200910 (unsigned) (rdev->mc.real_vram_size / (1024 * 1024)));
Jerome Glisse4c788672009-11-20 14:29:23 +0100911 r = ttm_bo_init_mm(&rdev->mman.bdev, TTM_PL_TT,
Jerome Glisse312ea8d2009-12-07 15:52:58 +0100912 rdev->mc.gtt_size >> PAGE_SHIFT);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200913 if (r) {
914 DRM_ERROR("Failed initializing GTT heap.\n");
915 return r;
916 }
917 DRM_INFO("radeon: %uM of GTT memory ready.\n",
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000918 (unsigned)(rdev->mc.gtt_size / (1024 * 1024)));
Dave Airliefa8a1232009-08-26 13:13:37 +1000919
920 r = radeon_ttm_debugfs_init(rdev);
921 if (r) {
922 DRM_ERROR("Failed to init debugfs\n");
923 return r;
924 }
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200925 return 0;
926}
927
928void radeon_ttm_fini(struct radeon_device *rdev)
929{
Jerome Glisse4c788672009-11-20 14:29:23 +0100930 int r;
931
Jerome Glisse0a0c7592009-12-11 20:36:19 +0100932 if (!rdev->mman.initialized)
933 return;
Christian König2014b562013-12-18 21:07:39 +0100934 radeon_ttm_debugfs_fini(rdev);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200935 if (rdev->stollen_vga_memory) {
Jerome Glisse4c788672009-11-20 14:29:23 +0100936 r = radeon_bo_reserve(rdev->stollen_vga_memory, false);
937 if (r == 0) {
938 radeon_bo_unpin(rdev->stollen_vga_memory);
939 radeon_bo_unreserve(rdev->stollen_vga_memory);
940 }
941 radeon_bo_unref(&rdev->stollen_vga_memory);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200942 }
943 ttm_bo_clean_mm(&rdev->mman.bdev, TTM_PL_VRAM);
944 ttm_bo_clean_mm(&rdev->mman.bdev, TTM_PL_TT);
945 ttm_bo_device_release(&rdev->mman.bdev);
946 radeon_gart_fini(rdev);
947 radeon_ttm_global_fini(rdev);
Jerome Glisse0a0c7592009-12-11 20:36:19 +0100948 rdev->mman.initialized = false;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200949 DRM_INFO("radeon: ttm finalized\n");
950}
951
Dave Airlie53595332011-03-14 09:47:24 +1000952/* this should only be called at bootup or when userspace
953 * isn't running */
954void radeon_ttm_set_active_vram_size(struct radeon_device *rdev, u64 size)
955{
956 struct ttm_mem_type_manager *man;
957
958 if (!rdev->mman.initialized)
959 return;
960
961 man = &rdev->mman.bdev.man[TTM_PL_VRAM];
962 /* this just adjusts TTM size idea, which sets lpfn to the correct value */
963 man->size = size >> PAGE_SHIFT;
964}
965
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200966static struct vm_operations_struct radeon_ttm_vm_ops;
Alexey Dobriyanf0f37e22009-09-27 22:29:37 +0400967static const struct vm_operations_struct *ttm_vm_ops = NULL;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200968
969static int radeon_ttm_fault(struct vm_area_struct *vma, struct vm_fault *vmf)
970{
971 struct ttm_buffer_object *bo;
Matthew Garrett5876dd22010-04-26 15:52:20 -0400972 struct radeon_device *rdev;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200973 int r;
974
Matthew Garrett5876dd22010-04-26 15:52:20 -0400975 bo = (struct ttm_buffer_object *)vma->vm_private_data;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200976 if (bo == NULL) {
977 return VM_FAULT_NOPAGE;
978 }
Matthew Garrett5876dd22010-04-26 15:52:20 -0400979 rdev = radeon_get_rdev(bo->bdev);
Christian Königdb7fce32012-05-11 14:57:18 +0200980 down_read(&rdev->pm.mclk_lock);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200981 r = ttm_vm_ops->fault(vma, vmf);
Christian Königdb7fce32012-05-11 14:57:18 +0200982 up_read(&rdev->pm.mclk_lock);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200983 return r;
984}
985
986int radeon_mmap(struct file *filp, struct vm_area_struct *vma)
987{
988 struct drm_file *file_priv;
989 struct radeon_device *rdev;
990 int r;
991
992 if (unlikely(vma->vm_pgoff < DRM_FILE_PAGE_OFFSET)) {
Daniel Vetter884c6da2014-09-23 15:46:47 +0200993 return -EINVAL;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200994 }
995
Joe Perches40b3be32010-09-04 18:52:42 -0700996 file_priv = filp->private_data;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200997 rdev = file_priv->minor->dev->dev_private;
998 if (rdev == NULL) {
999 return -EINVAL;
1000 }
1001 r = ttm_bo_mmap(filp, vma, &rdev->mman.bdev);
1002 if (unlikely(r != 0)) {
1003 return r;
1004 }
1005 if (unlikely(ttm_vm_ops == NULL)) {
1006 ttm_vm_ops = vma->vm_ops;
1007 radeon_ttm_vm_ops = *ttm_vm_ops;
1008 radeon_ttm_vm_ops.fault = &radeon_ttm_fault;
1009 }
1010 vma->vm_ops = &radeon_ttm_vm_ops;
1011 return 0;
1012}
1013
Dave Airliefa8a1232009-08-26 13:13:37 +10001014#if defined(CONFIG_DEBUG_FS)
Christian König893d6e62013-12-12 09:42:40 +01001015
Dave Airliefa8a1232009-08-26 13:13:37 +10001016static int radeon_mm_dump_table(struct seq_file *m, void *data)
1017{
1018 struct drm_info_node *node = (struct drm_info_node *)m->private;
Christian König893d6e62013-12-12 09:42:40 +01001019 unsigned ttm_pl = *(int *)node->info_ent->data;
Dave Airliefa8a1232009-08-26 13:13:37 +10001020 struct drm_device *dev = node->minor->dev;
1021 struct radeon_device *rdev = dev->dev_private;
Christian König893d6e62013-12-12 09:42:40 +01001022 struct drm_mm *mm = (struct drm_mm *)rdev->mman.bdev.man[ttm_pl].priv;
Dave Airliefa8a1232009-08-26 13:13:37 +10001023 int ret;
1024 struct ttm_bo_global *glob = rdev->mman.bdev.glob;
1025
1026 spin_lock(&glob->lru_lock);
1027 ret = drm_mm_dump_table(m, mm);
1028 spin_unlock(&glob->lru_lock);
1029 return ret;
1030}
Christian König893d6e62013-12-12 09:42:40 +01001031
1032static int ttm_pl_vram = TTM_PL_VRAM;
1033static int ttm_pl_tt = TTM_PL_TT;
1034
1035static struct drm_info_list radeon_ttm_debugfs_list[] = {
1036 {"radeon_vram_mm", radeon_mm_dump_table, 0, &ttm_pl_vram},
1037 {"radeon_gtt_mm", radeon_mm_dump_table, 0, &ttm_pl_tt},
1038 {"ttm_page_pool", ttm_page_alloc_debugfs, 0, NULL},
1039#ifdef CONFIG_SWIOTLB
1040 {"ttm_dma_page_pool", ttm_dma_page_alloc_debugfs, 0, NULL}
1041#endif
1042};
1043
Christian König2014b562013-12-18 21:07:39 +01001044static int radeon_ttm_vram_open(struct inode *inode, struct file *filep)
1045{
1046 struct radeon_device *rdev = inode->i_private;
1047 i_size_write(inode, rdev->mc.mc_vram_size);
1048 filep->private_data = inode->i_private;
1049 return 0;
1050}
1051
1052static ssize_t radeon_ttm_vram_read(struct file *f, char __user *buf,
1053 size_t size, loff_t *pos)
1054{
1055 struct radeon_device *rdev = f->private_data;
1056 ssize_t result = 0;
1057 int r;
1058
1059 if (size & 0x3 || *pos & 0x3)
1060 return -EINVAL;
1061
1062 while (size) {
1063 unsigned long flags;
1064 uint32_t value;
1065
1066 if (*pos >= rdev->mc.mc_vram_size)
1067 return result;
1068
1069 spin_lock_irqsave(&rdev->mmio_idx_lock, flags);
1070 WREG32(RADEON_MM_INDEX, ((uint32_t)*pos) | 0x80000000);
1071 if (rdev->family >= CHIP_CEDAR)
1072 WREG32(EVERGREEN_MM_INDEX_HI, *pos >> 31);
1073 value = RREG32(RADEON_MM_DATA);
1074 spin_unlock_irqrestore(&rdev->mmio_idx_lock, flags);
1075
1076 r = put_user(value, (uint32_t *)buf);
1077 if (r)
1078 return r;
1079
1080 result += 4;
1081 buf += 4;
1082 *pos += 4;
1083 size -= 4;
1084 }
1085
1086 return result;
1087}
1088
1089static const struct file_operations radeon_ttm_vram_fops = {
1090 .owner = THIS_MODULE,
1091 .open = radeon_ttm_vram_open,
1092 .read = radeon_ttm_vram_read,
1093 .llseek = default_llseek
1094};
1095
Christian Königdd66d202013-12-18 21:07:40 +01001096static int radeon_ttm_gtt_open(struct inode *inode, struct file *filep)
1097{
1098 struct radeon_device *rdev = inode->i_private;
1099 i_size_write(inode, rdev->mc.gtt_size);
1100 filep->private_data = inode->i_private;
1101 return 0;
1102}
1103
1104static ssize_t radeon_ttm_gtt_read(struct file *f, char __user *buf,
1105 size_t size, loff_t *pos)
1106{
1107 struct radeon_device *rdev = f->private_data;
1108 ssize_t result = 0;
1109 int r;
1110
1111 while (size) {
1112 loff_t p = *pos / PAGE_SIZE;
1113 unsigned off = *pos & ~PAGE_MASK;
Paul Bolle0d997b62014-03-04 10:34:48 +01001114 size_t cur_size = min_t(size_t, size, PAGE_SIZE - off);
Christian Königdd66d202013-12-18 21:07:40 +01001115 struct page *page;
1116 void *ptr;
1117
1118 if (p >= rdev->gart.num_cpu_pages)
1119 return result;
1120
1121 page = rdev->gart.pages[p];
1122 if (page) {
1123 ptr = kmap(page);
1124 ptr += off;
1125
1126 r = copy_to_user(buf, ptr, cur_size);
1127 kunmap(rdev->gart.pages[p]);
1128 } else
1129 r = clear_user(buf, cur_size);
1130
1131 if (r)
1132 return -EFAULT;
1133
1134 result += cur_size;
1135 buf += cur_size;
1136 *pos += cur_size;
1137 size -= cur_size;
1138 }
1139
1140 return result;
1141}
1142
1143static const struct file_operations radeon_ttm_gtt_fops = {
1144 .owner = THIS_MODULE,
1145 .open = radeon_ttm_gtt_open,
1146 .read = radeon_ttm_gtt_read,
1147 .llseek = default_llseek
1148};
1149
Dave Airliefa8a1232009-08-26 13:13:37 +10001150#endif
1151
1152static int radeon_ttm_debugfs_init(struct radeon_device *rdev)
1153{
Mikael Petterssonf4e45d02009-09-28 18:27:23 +02001154#if defined(CONFIG_DEBUG_FS)
Christian König2014b562013-12-18 21:07:39 +01001155 unsigned count;
1156
1157 struct drm_minor *minor = rdev->ddev->primary;
1158 struct dentry *ent, *root = minor->debugfs_root;
1159
1160 ent = debugfs_create_file("radeon_vram", S_IFREG | S_IRUGO, root,
1161 rdev, &radeon_ttm_vram_fops);
1162 if (IS_ERR(ent))
1163 return PTR_ERR(ent);
1164 rdev->mman.vram = ent;
1165
Christian Königdd66d202013-12-18 21:07:40 +01001166 ent = debugfs_create_file("radeon_gtt", S_IFREG | S_IRUGO, root,
1167 rdev, &radeon_ttm_gtt_fops);
1168 if (IS_ERR(ent))
1169 return PTR_ERR(ent);
1170 rdev->mman.gtt = ent;
1171
Christian König2014b562013-12-18 21:07:39 +01001172 count = ARRAY_SIZE(radeon_ttm_debugfs_list);
Dave Airliefa8a1232009-08-26 13:13:37 +10001173
Konrad Rzeszutek Wilkc52494f2011-10-17 17:15:08 -04001174#ifdef CONFIG_SWIOTLB
Christian König893d6e62013-12-12 09:42:40 +01001175 if (!swiotlb_nr_tbl())
1176 --count;
Konrad Rzeszutek Wilkc52494f2011-10-17 17:15:08 -04001177#endif
Dave Airliefa8a1232009-08-26 13:13:37 +10001178
Christian König893d6e62013-12-12 09:42:40 +01001179 return radeon_debugfs_add_files(rdev, radeon_ttm_debugfs_list, count);
1180#else
1181
Dave Airliefa8a1232009-08-26 13:13:37 +10001182 return 0;
Christian König893d6e62013-12-12 09:42:40 +01001183#endif
Dave Airliefa8a1232009-08-26 13:13:37 +10001184}
Christian König2014b562013-12-18 21:07:39 +01001185
1186static void radeon_ttm_debugfs_fini(struct radeon_device *rdev)
1187{
1188#if defined(CONFIG_DEBUG_FS)
1189
1190 debugfs_remove(rdev->mman.vram);
1191 rdev->mman.vram = NULL;
Christian Königdd66d202013-12-18 21:07:40 +01001192
1193 debugfs_remove(rdev->mman.gtt);
1194 rdev->mman.gtt = NULL;
Christian König2014b562013-12-18 21:07:39 +01001195#endif
1196}