blob: 83eb9c1fe94cc0065ce7dc2b924df51d36476094 [file] [log] [blame]
Clarence Ipaac9f332016-08-31 15:46:35 -04001/* Copyright (c) 2015-2017, The Linux Foundation. All rights reserved.
Narendra Muppalla1b0b3352015-09-29 10:16:51 -07002 *
3 * This program is free software; you can redistribute it and/or modify
4 * it under the terms of the GNU General Public License version 2 and
5 * only version 2 as published by the Free Software Foundation.
6 *
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
11 */
Alan Kwong1a00e4d2016-07-18 09:42:30 -040012
13#define pr_fmt(fmt) "[drm:%s:%d] " fmt, __func__, __LINE__
14
Clarence Ip4ce59322016-06-26 22:27:51 -040015#include <linux/debugfs.h>
Clarence Ip5e2a9222016-06-26 22:38:24 -040016#include <uapi/drm/sde_drm.h>
Clarence Ipaa0faf42016-05-30 12:07:48 -040017
18#include "msm_prop.h"
19
Narendra Muppalla1b0b3352015-09-29 10:16:51 -070020#include "sde_kms.h"
Clarence Ipae4e60c2016-06-26 22:44:04 -040021#include "sde_fence.h"
Clarence Ipc475b082016-06-26 09:27:23 -040022#include "sde_formats.h"
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -040023#include "sde_hw_sspp.h"
Alan Kwong1a00e4d2016-07-18 09:42:30 -040024#include "sde_trace.h"
Dhaval Patel48c76022016-09-01 17:51:23 -070025#include "sde_crtc.h"
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -040026
Clarence Ip13a8cf42016-09-29 17:27:47 -040027#define SDE_DEBUG_PLANE(pl, fmt, ...) SDE_DEBUG("plane%d " fmt,\
28 (pl) ? (pl)->base.base.id : -1, ##__VA_ARGS__)
29
30#define SDE_ERROR_PLANE(pl, fmt, ...) SDE_ERROR("plane%d " fmt,\
31 (pl) ? (pl)->base.base.id : -1, ##__VA_ARGS__)
32
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -040033#define DECIMATED_DIMENSION(dim, deci) (((dim) + ((1 << (deci)) - 1)) >> (deci))
34#define PHASE_STEP_SHIFT 21
35#define PHASE_STEP_UNIT_SCALE ((int) (1 << PHASE_STEP_SHIFT))
36#define PHASE_RESIDUAL 15
37
Clarence Ipe78efb72016-06-24 18:35:21 -040038#define SHARP_STRENGTH_DEFAULT 32
39#define SHARP_EDGE_THR_DEFAULT 112
40#define SHARP_SMOOTH_THR_DEFAULT 8
41#define SHARP_NOISE_THR_DEFAULT 2
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -040042
Clarence Ip5e2a9222016-06-26 22:38:24 -040043#define SDE_NAME_SIZE 12
Narendra Muppalla1b0b3352015-09-29 10:16:51 -070044
Clarence Ipcae1bb62016-07-07 12:07:13 -040045#define SDE_PLANE_COLOR_FILL_FLAG BIT(31)
46
Clarence Ip282dad62016-09-27 17:07:35 -040047/* dirty bits for update function */
48#define SDE_PLANE_DIRTY_RECTS 0x1
49#define SDE_PLANE_DIRTY_FORMAT 0x2
50#define SDE_PLANE_DIRTY_SHARPEN 0x4
51#define SDE_PLANE_DIRTY_ALL 0xFFFFFFFF
52
Alan Kwong1a00e4d2016-07-18 09:42:30 -040053/**
54 * enum sde_plane_qos - Different qos configurations for each pipe
55 *
56 * @SDE_PLANE_QOS_VBLANK_CTRL: Setup VBLANK qos for the pipe.
57 * @SDE_PLANE_QOS_VBLANK_AMORTIZE: Enables Amortization within pipe.
58 * this configuration is mutually exclusive from VBLANK_CTRL.
59 * @SDE_PLANE_QOS_PANIC_CTRL: Setup panic for the pipe.
60 */
61enum sde_plane_qos {
62 SDE_PLANE_QOS_VBLANK_CTRL = BIT(0),
63 SDE_PLANE_QOS_VBLANK_AMORTIZE = BIT(1),
64 SDE_PLANE_QOS_PANIC_CTRL = BIT(2),
65};
66
Clarence Ip5fc00c52016-09-23 15:03:34 -040067/*
68 * struct sde_plane - local sde plane structure
69 * @csc_cfg: Decoded user configuration for csc
70 * @csc_usr_ptr: Points to csc_cfg if valid user config available
71 * @csc_ptr: Points to sde_csc_cfg structure to use for current
72 */
Narendra Muppalla1b0b3352015-09-29 10:16:51 -070073struct sde_plane {
74 struct drm_plane base;
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -040075
76 int mmu_id;
77
Clarence Ip730e7192016-06-26 22:45:09 -040078 struct mutex lock;
79
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -040080 enum sde_sspp pipe;
81 uint32_t features; /* capabilities from catalog */
Narendra Muppalla1b0b3352015-09-29 10:16:51 -070082 uint32_t nformats;
Lloyd Atkinsonfa2489c2016-05-25 15:16:03 -040083 uint32_t formats[64];
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -040084
85 struct sde_hw_pipe *pipe_hw;
86 struct sde_hw_pipe_cfg pipe_cfg;
Clarence Ipe78efb72016-06-24 18:35:21 -040087 struct sde_hw_sharp_cfg sharp_cfg;
Clarence Ip5e2a9222016-06-26 22:38:24 -040088 struct sde_hw_scaler3_cfg scaler3_cfg;
Alan Kwong1a00e4d2016-07-18 09:42:30 -040089 struct sde_hw_pipe_qos_cfg pipe_qos_cfg;
Clarence Ipcae1bb62016-07-07 12:07:13 -040090 uint32_t color_fill;
91 bool is_error;
Alan Kwong1a00e4d2016-07-18 09:42:30 -040092 bool is_rt_pipe;
Clarence Ip4ce59322016-06-26 22:27:51 -040093
Clarence Ipb43d4592016-09-08 14:21:35 -040094 struct sde_hw_pixel_ext pixel_ext;
95 bool pixel_ext_usr;
96
Clarence Ip373f8592016-05-26 00:58:42 -040097 struct sde_csc_cfg csc_cfg;
Clarence Ip5fc00c52016-09-23 15:03:34 -040098 struct sde_csc_cfg *csc_usr_ptr;
Clarence Ip373f8592016-05-26 00:58:42 -040099 struct sde_csc_cfg *csc_ptr;
100
Clarence Ip4c1d9772016-06-26 09:35:38 -0400101 const struct sde_sspp_sub_blks *pipe_sblk;
102
Clarence Ip5e2a9222016-06-26 22:38:24 -0400103 char pipe_name[SDE_NAME_SIZE];
Clarence Ip4ce59322016-06-26 22:27:51 -0400104
Clarence Ipaa0faf42016-05-30 12:07:48 -0400105 struct msm_property_info property_info;
106 struct msm_property_data property_data[PLANE_PROP_COUNT];
Dhaval Patel4e574842016-08-23 15:11:37 -0700107 struct drm_property_blob *blob_info;
Clarence Ip730e7192016-06-26 22:45:09 -0400108
Clarence Ip4ce59322016-06-26 22:27:51 -0400109 /* debugfs related stuff */
110 struct dentry *debugfs_root;
111 struct sde_debugfs_regset32 debugfs_src;
112 struct sde_debugfs_regset32 debugfs_scaler;
113 struct sde_debugfs_regset32 debugfs_csc;
Narendra Muppalla1b0b3352015-09-29 10:16:51 -0700114};
Dhaval Patel47302cf2016-08-18 15:04:28 -0700115
Narendra Muppalla1b0b3352015-09-29 10:16:51 -0700116#define to_sde_plane(x) container_of(x, struct sde_plane, base)
117
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -0400118static bool sde_plane_enabled(struct drm_plane_state *state)
119{
Clarence Ipdbde9832016-06-26 09:48:36 -0400120 return state && state->fb && state->crtc;
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -0400121}
122
Alan Kwong1a00e4d2016-07-18 09:42:30 -0400123/**
124 * _sde_plane_calc_fill_level - calculate fill level of the given source format
125 * @plane: Pointer to drm plane
126 * @fmt: Pointer to source buffer format
127 * @src_wdith: width of source buffer
128 * Return: fill level corresponding to the source buffer/format or 0 if error
129 */
130static inline int _sde_plane_calc_fill_level(struct drm_plane *plane,
131 const struct sde_format *fmt, u32 src_width)
132{
133 struct sde_plane *psde;
134 u32 fixed_buff_size;
135 u32 total_fl;
136
137 if (!plane || !fmt) {
138 SDE_ERROR("invalid arguments\n");
139 return 0;
140 }
141
142 psde = to_sde_plane(plane);
143 fixed_buff_size = psde->pipe_sblk->pixel_ram_size;
144
145 if (fmt->fetch_planes == SDE_PLANE_PSEUDO_PLANAR) {
146 if (fmt->chroma_sample == SDE_CHROMA_420) {
147 /* NV12 */
148 total_fl = (fixed_buff_size / 2) /
149 ((src_width + 32) * fmt->bpp);
150 } else {
151 /* non NV12 */
152 total_fl = (fixed_buff_size) /
153 ((src_width + 32) * fmt->bpp);
154 }
155 } else {
156 total_fl = (fixed_buff_size * 2) /
157 ((src_width + 32) * fmt->bpp);
158 }
159
160 SDE_DEBUG("plane%u: pnum:%d fmt:%x w:%u fl:%u\n",
161 plane->base.id, psde->pipe - SSPP_VIG0,
162 fmt->base.pixel_format, src_width, total_fl);
163
164 return total_fl;
165}
166
167/**
168 * _sde_plane_get_qos_lut_linear - get linear LUT mapping
169 * @total_fl: fill level
170 * Return: LUT setting corresponding to the fill level
171 */
172static inline u32 _sde_plane_get_qos_lut_linear(u32 total_fl)
173{
174 u32 qos_lut;
175
176 if (total_fl <= 4)
177 qos_lut = 0x1B;
178 else if (total_fl <= 5)
179 qos_lut = 0x5B;
180 else if (total_fl <= 6)
181 qos_lut = 0x15B;
182 else if (total_fl <= 7)
183 qos_lut = 0x55B;
184 else if (total_fl <= 8)
185 qos_lut = 0x155B;
186 else if (total_fl <= 9)
187 qos_lut = 0x555B;
188 else if (total_fl <= 10)
189 qos_lut = 0x1555B;
190 else if (total_fl <= 11)
191 qos_lut = 0x5555B;
192 else if (total_fl <= 12)
193 qos_lut = 0x15555B;
194 else
195 qos_lut = 0x55555B;
196
197 return qos_lut;
198}
199
200/**
201 * _sde_plane_get_qos_lut_macrotile - get macrotile LUT mapping
202 * @total_fl: fill level
203 * Return: LUT setting corresponding to the fill level
204 */
205static inline u32 _sde_plane_get_qos_lut_macrotile(u32 total_fl)
206{
207 u32 qos_lut;
208
209 if (total_fl <= 10)
210 qos_lut = 0x1AAff;
211 else if (total_fl <= 11)
212 qos_lut = 0x5AAFF;
213 else if (total_fl <= 12)
214 qos_lut = 0x15AAFF;
215 else
216 qos_lut = 0x55AAFF;
217
218 return qos_lut;
219}
220
221/**
222 * _sde_plane_is_rt_pipe - check if the given plane requires real-time QoS
223 * @plane: Pointer to drm plane
224 * @crtc: Pointer to drm crtc associated with the given plane
225 */
226static bool _sde_plane_is_rt_pipe(struct drm_plane *plane,
227 struct drm_crtc *crtc)
228{
229 struct sde_plane *psde = to_sde_plane(plane);
230 struct drm_connector *connector;
231 bool is_rt = false;
232
233 /* check if this plane has a physical connector interface */
Alan Kwong894837a2016-09-29 01:15:23 -0400234 mutex_lock(&plane->dev->mode_config.mutex);
Alan Kwong1a00e4d2016-07-18 09:42:30 -0400235 drm_for_each_connector(connector, plane->dev)
236 if (connector->state &&
237 (connector->state->crtc == crtc) &&
238 (connector->connector_type
239 != DRM_MODE_CONNECTOR_VIRTUAL)) {
240 is_rt = true;
241 break;
242 }
Alan Kwong894837a2016-09-29 01:15:23 -0400243 mutex_unlock(&plane->dev->mode_config.mutex);
Alan Kwong1a00e4d2016-07-18 09:42:30 -0400244
245 SDE_DEBUG("plane%u: pnum:%d rt:%d\n",
246 plane->base.id, psde->pipe - SSPP_VIG0, is_rt);
247
248 return is_rt;
249}
250
251/**
252 * _sde_plane_set_qos_lut - set QoS LUT of the given plane
253 * @plane: Pointer to drm plane
254 * @fb: Pointer to framebuffer associated with the given plane
255 */
256static void _sde_plane_set_qos_lut(struct drm_plane *plane,
257 struct drm_framebuffer *fb)
258{
259 struct sde_plane *psde;
260 const struct sde_format *fmt = NULL;
261 u32 qos_lut;
262 u32 total_fl = 0;
263
264 if (!plane || !fb) {
265 SDE_ERROR("invalid arguments plane %d fb %d\n",
266 plane != 0, fb != 0);
267 return;
268 }
269
270 psde = to_sde_plane(plane);
271
272 if (!psde->pipe_hw || !psde->pipe_sblk) {
273 SDE_ERROR("invalid arguments\n");
274 return;
275 } else if (!psde->pipe_hw->ops.setup_creq_lut) {
276 return;
277 }
278
279 if (!psde->is_rt_pipe) {
280 qos_lut = psde->pipe_sblk->creq_lut_nrt;
281 } else {
282 fmt = sde_get_sde_format_ext(
283 fb->pixel_format,
284 fb->modifier,
285 drm_format_num_planes(fb->pixel_format));
286 total_fl = _sde_plane_calc_fill_level(plane, fmt,
287 psde->pipe_cfg.src_rect.w);
288
289 if (SDE_FORMAT_IS_LINEAR(fmt))
290 qos_lut = _sde_plane_get_qos_lut_linear(total_fl);
291 else
292 qos_lut = _sde_plane_get_qos_lut_macrotile(total_fl);
293 }
294
295 psde->pipe_qos_cfg.creq_lut = qos_lut;
296
297 trace_sde_perf_set_qos_luts(psde->pipe - SSPP_VIG0,
298 (fmt) ? fmt->base.pixel_format : 0,
299 psde->is_rt_pipe, total_fl, qos_lut,
300 (fmt) ? SDE_FORMAT_IS_LINEAR(fmt) : 0);
301
302 SDE_DEBUG("plane%u: pnum:%d fmt:%x rt:%d fl:%u lut:0x%x\n",
303 plane->base.id,
304 psde->pipe - SSPP_VIG0,
305 (fmt) ? fmt->base.pixel_format : 0,
306 psde->is_rt_pipe, total_fl, qos_lut);
307
308 psde->pipe_hw->ops.setup_creq_lut(psde->pipe_hw, &psde->pipe_qos_cfg);
309}
310
311/**
312 * _sde_plane_set_panic_lut - set danger/safe LUT of the given plane
313 * @plane: Pointer to drm plane
314 * @fb: Pointer to framebuffer associated with the given plane
315 */
316static void _sde_plane_set_danger_lut(struct drm_plane *plane,
317 struct drm_framebuffer *fb)
318{
319 struct sde_plane *psde;
320 const struct sde_format *fmt = NULL;
321 u32 danger_lut, safe_lut;
322
323 if (!plane || !fb) {
324 SDE_ERROR("invalid arguments\n");
325 return;
326 }
327
328 psde = to_sde_plane(plane);
329
330 if (!psde->pipe_hw || !psde->pipe_sblk) {
331 SDE_ERROR("invalid arguments\n");
332 return;
333 } else if (!psde->pipe_hw->ops.setup_danger_safe_lut) {
334 return;
335 }
336
337 if (!psde->is_rt_pipe) {
338 danger_lut = psde->pipe_sblk->danger_lut_nrt;
339 safe_lut = psde->pipe_sblk->safe_lut_nrt;
340 } else {
341 fmt = sde_get_sde_format_ext(
342 fb->pixel_format,
343 fb->modifier,
344 drm_format_num_planes(fb->pixel_format));
345
346 if (SDE_FORMAT_IS_LINEAR(fmt)) {
347 danger_lut = psde->pipe_sblk->danger_lut_linear;
348 safe_lut = psde->pipe_sblk->safe_lut_linear;
349 } else {
350 danger_lut = psde->pipe_sblk->danger_lut_tile;
351 safe_lut = psde->pipe_sblk->safe_lut_tile;
352 }
353 }
354
355 psde->pipe_qos_cfg.danger_lut = danger_lut;
356 psde->pipe_qos_cfg.safe_lut = safe_lut;
357
358 trace_sde_perf_set_danger_luts(psde->pipe - SSPP_VIG0,
359 (fmt) ? fmt->base.pixel_format : 0,
360 (fmt) ? fmt->fetch_mode : 0,
361 psde->pipe_qos_cfg.danger_lut,
362 psde->pipe_qos_cfg.safe_lut);
363
364 SDE_DEBUG("plane%u: pnum:%d fmt:%x mode:%d luts[0x%x, 0x%x]\n",
365 plane->base.id,
366 psde->pipe - SSPP_VIG0,
367 fmt ? fmt->base.pixel_format : 0,
368 fmt ? fmt->fetch_mode : -1,
369 psde->pipe_qos_cfg.danger_lut,
370 psde->pipe_qos_cfg.safe_lut);
371
372 psde->pipe_hw->ops.setup_danger_safe_lut(psde->pipe_hw,
373 &psde->pipe_qos_cfg);
374}
375
376/**
377 * _sde_plane_set_qos_ctrl - set QoS control of the given plane
378 * @plane: Pointer to drm plane
379 * @enable: true to enable QoS control
380 * @flags: QoS control mode (enum sde_plane_qos)
381 */
382static void _sde_plane_set_qos_ctrl(struct drm_plane *plane,
383 bool enable, u32 flags)
384{
385 struct sde_plane *psde;
386
387 if (!plane) {
388 SDE_ERROR("invalid arguments\n");
389 return;
390 }
391
392 psde = to_sde_plane(plane);
393
394 if (!psde->pipe_hw || !psde->pipe_sblk) {
395 SDE_ERROR("invalid arguments\n");
396 return;
397 } else if (!psde->pipe_hw->ops.setup_qos_ctrl) {
398 return;
399 }
400
401 if (flags & SDE_PLANE_QOS_VBLANK_CTRL) {
402 psde->pipe_qos_cfg.creq_vblank = psde->pipe_sblk->creq_vblank;
403 psde->pipe_qos_cfg.danger_vblank =
404 psde->pipe_sblk->danger_vblank;
405 psde->pipe_qos_cfg.vblank_en = enable;
406 }
407
408 if (flags & SDE_PLANE_QOS_VBLANK_AMORTIZE) {
409 /* this feature overrules previous VBLANK_CTRL */
410 psde->pipe_qos_cfg.vblank_en = false;
411 psde->pipe_qos_cfg.creq_vblank = 0; /* clear vblank bits */
412 }
413
414 if (flags & SDE_PLANE_QOS_PANIC_CTRL)
415 psde->pipe_qos_cfg.danger_safe_en = enable;
416
417 if (!psde->is_rt_pipe) {
418 psde->pipe_qos_cfg.vblank_en = false;
419 psde->pipe_qos_cfg.danger_safe_en = false;
420 }
421
422 SDE_DEBUG("plane%u: pnum:%d ds:%d vb:%d pri[0x%x, 0x%x]\n",
423 plane->base.id,
424 psde->pipe - SSPP_VIG0,
425 psde->pipe_qos_cfg.danger_safe_en,
426 psde->pipe_qos_cfg.vblank_en,
427 psde->pipe_qos_cfg.creq_vblank,
428 psde->pipe_qos_cfg.danger_vblank);
429
430 psde->pipe_hw->ops.setup_qos_ctrl(psde->pipe_hw,
431 &psde->pipe_qos_cfg);
432}
433
Alan Kwong5d324e42016-07-28 22:56:18 -0400434/**
435 * _sde_plane_set_ot_limit - set OT limit for the given plane
436 * @plane: Pointer to drm plane
437 * @crtc: Pointer to drm crtc
438 */
439static void _sde_plane_set_ot_limit(struct drm_plane *plane,
440 struct drm_crtc *crtc)
441{
442 struct sde_plane *psde;
443 struct sde_vbif_set_ot_params ot_params;
444 struct msm_drm_private *priv;
445 struct sde_kms *sde_kms;
446
447 if (!plane || !plane->dev || !crtc) {
448 SDE_ERROR("invalid arguments plane %d crtc %d\n",
449 plane != 0, crtc != 0);
450 return;
451 }
452
453 priv = plane->dev->dev_private;
454 if (!priv || !priv->kms) {
455 SDE_ERROR("invalid KMS reference\n");
456 return;
457 }
458
459 sde_kms = to_sde_kms(priv->kms);
460 psde = to_sde_plane(plane);
461 if (!psde->pipe_hw) {
462 SDE_ERROR("invalid pipe reference\n");
463 return;
464 }
465
466 memset(&ot_params, 0, sizeof(ot_params));
467 ot_params.xin_id = psde->pipe_hw->cap->xin_id;
468 ot_params.num = psde->pipe_hw->idx - SSPP_NONE;
469 ot_params.width = psde->pipe_cfg.src_rect.w;
470 ot_params.height = psde->pipe_cfg.src_rect.h;
471 ot_params.is_wfd = !psde->is_rt_pipe;
472 ot_params.frame_rate = crtc->mode.vrefresh;
473 ot_params.vbif_idx = VBIF_RT;
474 ot_params.clk_ctrl = psde->pipe_hw->cap->clk_ctrl;
475 ot_params.rd = true;
476
477 sde_vbif_set_ot_limit(sde_kms, &ot_params);
478}
479
Clarence Ipcae1bb62016-07-07 12:07:13 -0400480/* helper to update a state's input fence pointer from the property */
Clarence Ip13a8cf42016-09-29 17:27:47 -0400481static void _sde_plane_set_input_fence(struct sde_plane *psde,
Clarence Ipae4e60c2016-06-26 22:44:04 -0400482 struct sde_plane_state *pstate, uint64_t fd)
483{
Clarence Ip13a8cf42016-09-29 17:27:47 -0400484 if (!psde || !pstate) {
485 SDE_ERROR("invalid arg(s), plane %d state %d\n",
486 psde != 0, pstate != 0);
Clarence Ipae4e60c2016-06-26 22:44:04 -0400487 return;
Clarence Ip13a8cf42016-09-29 17:27:47 -0400488 }
Clarence Ipae4e60c2016-06-26 22:44:04 -0400489
490 /* clear previous reference */
Clarence Ipcae1bb62016-07-07 12:07:13 -0400491 if (pstate->input_fence)
492 sde_sync_put(pstate->input_fence);
Clarence Ipae4e60c2016-06-26 22:44:04 -0400493
494 /* get fence pointer for later */
Clarence Ipcae1bb62016-07-07 12:07:13 -0400495 pstate->input_fence = sde_sync_get(fd);
Clarence Ipae4e60c2016-06-26 22:44:04 -0400496
Clarence Ip13a8cf42016-09-29 17:27:47 -0400497 SDE_DEBUG_PLANE(psde, "0x%llX\n", fd);
Clarence Ipae4e60c2016-06-26 22:44:04 -0400498}
499
Clarence Ipcae1bb62016-07-07 12:07:13 -0400500int sde_plane_wait_input_fence(struct drm_plane *plane, uint32_t wait_ms)
Clarence Ipae4e60c2016-06-26 22:44:04 -0400501{
Clarence Ipcae1bb62016-07-07 12:07:13 -0400502 struct sde_plane *psde;
Clarence Ipae4e60c2016-06-26 22:44:04 -0400503 struct sde_plane_state *pstate;
Clarence Ipcae1bb62016-07-07 12:07:13 -0400504 void *input_fence;
Clarence Ipcb410d42016-06-26 22:52:33 -0400505 int ret = -EINVAL;
Clarence Ipae4e60c2016-06-26 22:44:04 -0400506
507 if (!plane) {
Dhaval Patel47302cf2016-08-18 15:04:28 -0700508 SDE_ERROR("invalid plane\n");
Clarence Ipae4e60c2016-06-26 22:44:04 -0400509 } else if (!plane->state) {
Clarence Ip13a8cf42016-09-29 17:27:47 -0400510 SDE_ERROR_PLANE(to_sde_plane(plane), "invalid state\n");
Clarence Ipae4e60c2016-06-26 22:44:04 -0400511 } else {
Clarence Ipcae1bb62016-07-07 12:07:13 -0400512 psde = to_sde_plane(plane);
Clarence Ipae4e60c2016-06-26 22:44:04 -0400513 pstate = to_sde_plane_state(plane->state);
Clarence Ipcae1bb62016-07-07 12:07:13 -0400514 input_fence = pstate->input_fence;
Clarence Ipae4e60c2016-06-26 22:44:04 -0400515
Clarence Ipcae1bb62016-07-07 12:07:13 -0400516 if (input_fence) {
517 ret = sde_sync_wait(input_fence, wait_ms);
518 switch (ret) {
519 case 0:
Clarence Ip13a8cf42016-09-29 17:27:47 -0400520 SDE_DEBUG_PLANE(psde, "signaled\n");
Clarence Ipcae1bb62016-07-07 12:07:13 -0400521 break;
522 case -ETIME:
Clarence Ip13a8cf42016-09-29 17:27:47 -0400523 SDE_ERROR_PLANE(psde, "timeout, %ums\n",
524 wait_ms);
Clarence Ipcae1bb62016-07-07 12:07:13 -0400525 psde->is_error = true;
526 break;
527 default:
Clarence Ip13a8cf42016-09-29 17:27:47 -0400528 SDE_ERROR_PLANE(psde, "error, %d\n", ret);
Clarence Ipcae1bb62016-07-07 12:07:13 -0400529 psde->is_error = true;
530 break;
531 }
Clarence Ipcb410d42016-06-26 22:52:33 -0400532 } else {
533 ret = 0;
534 }
Clarence Ipae4e60c2016-06-26 22:44:04 -0400535 }
Clarence Ipae4e60c2016-06-26 22:44:04 -0400536 return ret;
537}
538
Clarence Ip282dad62016-09-27 17:07:35 -0400539static inline void _sde_plane_set_scanout(struct drm_plane *plane,
Clarence Ip5e2a9222016-06-26 22:38:24 -0400540 struct sde_plane_state *pstate,
Lloyd Atkinsonfa2489c2016-05-25 15:16:03 -0400541 struct sde_hw_pipe_cfg *pipe_cfg,
542 struct drm_framebuffer *fb)
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -0400543{
Clarence Ipae4e60c2016-06-26 22:44:04 -0400544 struct sde_plane *psde;
Clarence Ip282dad62016-09-27 17:07:35 -0400545 int ret;
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -0400546
Clarence Ip13a8cf42016-09-29 17:27:47 -0400547 if (!plane || !pstate || !pipe_cfg || !fb) {
548 SDE_ERROR(
549 "invalid arg(s), plane %d state %d cfg %d fb %d\n",
550 plane != 0, pstate != 0, pipe_cfg != 0, fb != 0);
Clarence Ipae4e60c2016-06-26 22:44:04 -0400551 return;
Clarence Ip13a8cf42016-09-29 17:27:47 -0400552 }
Clarence Ipae4e60c2016-06-26 22:44:04 -0400553
554 psde = to_sde_plane(plane);
Clarence Ipb6eb2362016-09-08 16:18:13 -0400555 if (!psde->pipe_hw) {
556 SDE_ERROR_PLANE(psde, "invalid pipe_hw\n");
Lloyd Atkinsonfa2489c2016-05-25 15:16:03 -0400557 return;
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -0400558 }
Lloyd Atkinsonfa2489c2016-05-25 15:16:03 -0400559
Clarence Ipb6eb2362016-09-08 16:18:13 -0400560 ret = sde_format_populate_layout(psde->mmu_id, fb, &pipe_cfg->layout);
561 if (ret == -EAGAIN)
562 SDE_DEBUG_PLANE(psde, "not updating same src addrs\n");
563 else if (ret)
564 SDE_ERROR_PLANE(psde, "failed to get format layout, %d\n", ret);
565 else if (psde->pipe_hw->ops.setup_sourceaddress)
Lloyd Atkinsonfa2489c2016-05-25 15:16:03 -0400566 psde->pipe_hw->ops.setup_sourceaddress(psde->pipe_hw, pipe_cfg);
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -0400567}
568
Clarence Ipcb410d42016-06-26 22:52:33 -0400569static void _sde_plane_setup_scaler3(struct sde_plane *psde,
Clarence Ip5e2a9222016-06-26 22:38:24 -0400570 uint32_t src_w, uint32_t src_h, uint32_t dst_w, uint32_t dst_h,
571 struct sde_hw_scaler3_cfg *scale_cfg,
Lloyd Atkinson9a673492016-07-05 11:41:57 -0400572 const struct sde_format *fmt,
Clarence Ip5e2a9222016-06-26 22:38:24 -0400573 uint32_t chroma_subsmpl_h, uint32_t chroma_subsmpl_v)
574{
575}
576
Clarence Ipcb410d42016-06-26 22:52:33 -0400577/**
Clarence Ip13a8cf42016-09-29 17:27:47 -0400578 * _sde_plane_setup_scaler2 - determine default scaler phase steps/filter type
Clarence Ipcb410d42016-06-26 22:52:33 -0400579 * @psde: Pointer to SDE plane object
580 * @src: Source size
581 * @dst: Destination size
582 * @phase_steps: Pointer to output array for phase steps
583 * @filter: Pointer to output array for filter type
584 * @fmt: Pointer to format definition
585 * @chroma_subsampling: Subsampling amount for chroma channel
586 *
587 * Returns: 0 on success
588 */
589static int _sde_plane_setup_scaler2(struct sde_plane *psde,
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -0400590 uint32_t src, uint32_t dst, uint32_t *phase_steps,
Lloyd Atkinson9a673492016-07-05 11:41:57 -0400591 enum sde_hw_filter *filter, const struct sde_format *fmt,
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -0400592 uint32_t chroma_subsampling)
593{
Clarence Ipcb410d42016-06-26 22:52:33 -0400594 if (!psde || !phase_steps || !filter || !fmt) {
Clarence Ip13a8cf42016-09-29 17:27:47 -0400595 SDE_ERROR(
596 "invalid arg(s), plane %d phase %d filter %d fmt %d\n",
597 psde != 0, phase_steps != 0, filter != 0, fmt != 0);
Clarence Ipcb410d42016-06-26 22:52:33 -0400598 return -EINVAL;
599 }
600
Clarence Ip4c1d9772016-06-26 09:35:38 -0400601 /* calculate phase steps, leave init phase as zero */
Clarence Ipe78efb72016-06-24 18:35:21 -0400602 phase_steps[SDE_SSPP_COMP_0] =
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -0400603 mult_frac(1 << PHASE_STEP_SHIFT, src, dst);
Clarence Ipe78efb72016-06-24 18:35:21 -0400604 phase_steps[SDE_SSPP_COMP_1_2] =
605 phase_steps[SDE_SSPP_COMP_0] / chroma_subsampling;
606 phase_steps[SDE_SSPP_COMP_2] = phase_steps[SDE_SSPP_COMP_1_2];
607 phase_steps[SDE_SSPP_COMP_3] = phase_steps[SDE_SSPP_COMP_0];
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -0400608
609 /* calculate scaler config, if necessary */
Clarence Ipdbde9832016-06-26 09:48:36 -0400610 if (SDE_FORMAT_IS_YUV(fmt) || src != dst) {
Clarence Ipe78efb72016-06-24 18:35:21 -0400611 filter[SDE_SSPP_COMP_3] =
Lloyd Atkinson9a673492016-07-05 11:41:57 -0400612 (src <= dst) ? SDE_SCALE_FILTER_BIL :
613 SDE_SCALE_FILTER_PCMN;
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -0400614
Clarence Ipdbde9832016-06-26 09:48:36 -0400615 if (SDE_FORMAT_IS_YUV(fmt)) {
Lloyd Atkinson9a673492016-07-05 11:41:57 -0400616 filter[SDE_SSPP_COMP_0] = SDE_SCALE_FILTER_CA;
Clarence Ipe78efb72016-06-24 18:35:21 -0400617 filter[SDE_SSPP_COMP_1_2] = filter[SDE_SSPP_COMP_3];
618 } else {
619 filter[SDE_SSPP_COMP_0] = filter[SDE_SSPP_COMP_3];
620 filter[SDE_SSPP_COMP_1_2] =
Lloyd Atkinson9a673492016-07-05 11:41:57 -0400621 SDE_SCALE_FILTER_NEAREST;
Clarence Ipe78efb72016-06-24 18:35:21 -0400622 }
623 } else {
624 /* disable scaler */
Lloyd Atkinson9a673492016-07-05 11:41:57 -0400625 filter[SDE_SSPP_COMP_0] = SDE_SCALE_FILTER_MAX;
626 filter[SDE_SSPP_COMP_1_2] = SDE_SCALE_FILTER_MAX;
627 filter[SDE_SSPP_COMP_3] = SDE_SCALE_FILTER_MAX;
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -0400628 }
Clarence Ipcb410d42016-06-26 22:52:33 -0400629 return 0;
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -0400630}
631
Clarence Ipcb410d42016-06-26 22:52:33 -0400632/**
633 * _sde_plane_setup_pixel_ext - determine default pixel extension values
634 * @psde: Pointer to SDE plane object
635 * @src: Source size
636 * @dst: Destination size
637 * @decimated_src: Source size after decimation, if any
638 * @phase_steps: Pointer to output array for phase steps
639 * @out_src: Output array for pixel extension values
640 * @out_edge1: Output array for pixel extension first edge
641 * @out_edge2: Output array for pixel extension second edge
642 * @filter: Pointer to array for filter type
643 * @fmt: Pointer to format definition
644 * @chroma_subsampling: Subsampling amount for chroma channel
645 * @post_compare: Whether to chroma subsampled source size for comparisions
646 */
647static void _sde_plane_setup_pixel_ext(struct sde_plane *psde,
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -0400648 uint32_t src, uint32_t dst, uint32_t decimated_src,
649 uint32_t *phase_steps, uint32_t *out_src, int *out_edge1,
Clarence Ipe78efb72016-06-24 18:35:21 -0400650 int *out_edge2, enum sde_hw_filter *filter,
Lloyd Atkinson9a673492016-07-05 11:41:57 -0400651 const struct sde_format *fmt, uint32_t chroma_subsampling,
Clarence Ipe78efb72016-06-24 18:35:21 -0400652 bool post_compare)
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -0400653{
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -0400654 int64_t edge1, edge2, caf;
655 uint32_t src_work;
656 int i, tmp;
657
Clarence Ipcb410d42016-06-26 22:52:33 -0400658 if (psde && phase_steps && out_src && out_edge1 &&
Clarence Ipe78efb72016-06-24 18:35:21 -0400659 out_edge2 && filter && fmt) {
660 /* handle CAF for YUV formats */
Lloyd Atkinson9a673492016-07-05 11:41:57 -0400661 if (SDE_FORMAT_IS_YUV(fmt) && *filter == SDE_SCALE_FILTER_CA)
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -0400662 caf = PHASE_STEP_UNIT_SCALE;
663 else
664 caf = 0;
665
666 for (i = 0; i < SDE_MAX_PLANES; i++) {
667 src_work = decimated_src;
Clarence Ipe78efb72016-06-24 18:35:21 -0400668 if (i == SDE_SSPP_COMP_1_2 || i == SDE_SSPP_COMP_2)
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -0400669 src_work /= chroma_subsampling;
670 if (post_compare)
671 src = src_work;
Clarence Ipdbde9832016-06-26 09:48:36 -0400672 if (!SDE_FORMAT_IS_YUV(fmt) && (src == dst)) {
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -0400673 /* unity */
674 edge1 = 0;
675 edge2 = 0;
676 } else if (dst >= src) {
677 /* upscale */
678 edge1 = (1 << PHASE_RESIDUAL);
679 edge1 -= caf;
680 edge2 = (1 << PHASE_RESIDUAL);
681 edge2 += (dst - 1) * *(phase_steps + i);
682 edge2 -= (src_work - 1) * PHASE_STEP_UNIT_SCALE;
683 edge2 += caf;
684 edge2 = -(edge2);
685 } else {
686 /* downscale */
687 edge1 = 0;
688 edge2 = (dst - 1) * *(phase_steps + i);
689 edge2 -= (src_work - 1) * PHASE_STEP_UNIT_SCALE;
690 edge2 += *(phase_steps + i);
691 edge2 = -(edge2);
692 }
693
694 /* only enable CAF for luma plane */
695 caf = 0;
696
697 /* populate output arrays */
698 *(out_src + i) = src_work;
699
700 /* edge updates taken from __pxl_extn_helper */
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -0400701 if (edge1 >= 0) {
702 tmp = (uint32_t)edge1;
703 tmp >>= PHASE_STEP_SHIFT;
704 *(out_edge1 + i) = -tmp;
705 } else {
706 tmp = (uint32_t)(-edge1);
Clarence Ipe78efb72016-06-24 18:35:21 -0400707 *(out_edge1 + i) =
708 (tmp + PHASE_STEP_UNIT_SCALE - 1) >>
709 PHASE_STEP_SHIFT;
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -0400710 }
711 if (edge2 >= 0) {
712 tmp = (uint32_t)edge2;
713 tmp >>= PHASE_STEP_SHIFT;
714 *(out_edge2 + i) = -tmp;
715 } else {
716 tmp = (uint32_t)(-edge2);
Clarence Ipe78efb72016-06-24 18:35:21 -0400717 *(out_edge2 + i) =
718 (tmp + PHASE_STEP_UNIT_SCALE - 1) >>
719 PHASE_STEP_SHIFT;
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -0400720 }
721 }
722 }
723}
724
Clarence Ip5fc00c52016-09-23 15:03:34 -0400725static inline void _sde_plane_setup_csc(struct sde_plane *psde)
Clarence Ipe78efb72016-06-24 18:35:21 -0400726{
727 static const struct sde_csc_cfg sde_csc_YUV2RGB_601L = {
728 {
Clarence Ip373f8592016-05-26 00:58:42 -0400729 /* S15.16 format */
730 0x00012A00, 0x00000000, 0x00019880,
731 0x00012A00, 0xFFFF9B80, 0xFFFF3000,
732 0x00012A00, 0x00020480, 0x00000000,
Clarence Ipe78efb72016-06-24 18:35:21 -0400733 },
Clarence Ip373f8592016-05-26 00:58:42 -0400734 /* signed bias */
Clarence Ipe78efb72016-06-24 18:35:21 -0400735 { 0xfff0, 0xff80, 0xff80,},
736 { 0x0, 0x0, 0x0,},
Clarence Ip373f8592016-05-26 00:58:42 -0400737 /* unsigned clamp */
Clarence Ipe78efb72016-06-24 18:35:21 -0400738 { 0x10, 0xeb, 0x10, 0xf0, 0x10, 0xf0,},
Clarence Ip373f8592016-05-26 00:58:42 -0400739 { 0x00, 0xff, 0x00, 0xff, 0x00, 0xff,},
Clarence Ipe78efb72016-06-24 18:35:21 -0400740 };
Clarence Ipe78efb72016-06-24 18:35:21 -0400741
Clarence Ip5fc00c52016-09-23 15:03:34 -0400742 if (!psde) {
743 SDE_ERROR("invalid plane\n");
Clarence Ipaa0faf42016-05-30 12:07:48 -0400744 return;
745 }
Clarence Ip5e2a9222016-06-26 22:38:24 -0400746
Clarence Ipcae1bb62016-07-07 12:07:13 -0400747 /* revert to kernel default if override not available */
Clarence Ip5fc00c52016-09-23 15:03:34 -0400748 if (psde->csc_usr_ptr)
749 psde->csc_ptr = psde->csc_usr_ptr;
750 else
Clarence Ip373f8592016-05-26 00:58:42 -0400751 psde->csc_ptr = (struct sde_csc_cfg *)&sde_csc_YUV2RGB_601L;
Clarence Ip5fc00c52016-09-23 15:03:34 -0400752
Clarence Ip13a8cf42016-09-29 17:27:47 -0400753 SDE_DEBUG_PLANE(psde, "using 0x%X 0x%X 0x%X...\n",
Clarence Ip5fc00c52016-09-23 15:03:34 -0400754 psde->csc_ptr->csc_mv[0],
755 psde->csc_ptr->csc_mv[1],
756 psde->csc_ptr->csc_mv[2]);
Clarence Ipe78efb72016-06-24 18:35:21 -0400757}
758
Clarence Ipcb410d42016-06-26 22:52:33 -0400759static void _sde_plane_setup_scaler(struct sde_plane *psde,
Lloyd Atkinson9a673492016-07-05 11:41:57 -0400760 const struct sde_format *fmt,
Clarence Ipcb410d42016-06-26 22:52:33 -0400761 struct sde_plane_state *pstate)
Narendra Muppalla1b0b3352015-09-29 10:16:51 -0700762{
Clarence Ipb43d4592016-09-08 14:21:35 -0400763 struct sde_hw_pixel_ext *pe;
Clarence Ipcb410d42016-06-26 22:52:33 -0400764 uint32_t chroma_subsmpl_h, chroma_subsmpl_v;
Clarence Ipb43d4592016-09-08 14:21:35 -0400765 uint32_t tmp, i;
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -0400766
Clarence Ipb43d4592016-09-08 14:21:35 -0400767 if (!psde || !fmt) {
768 SDE_ERROR("invalid arg(s), plane %d fmt %d state %d\n",
769 psde != 0, fmt != 0, pstate != 0);
Clarence Ipcb410d42016-06-26 22:52:33 -0400770 return;
Clarence Ipb43d4592016-09-08 14:21:35 -0400771 }
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -0400772
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -0400773 pe = &(psde->pixel_ext);
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -0400774
Clarence Ipdedbba92016-09-27 17:43:10 -0400775 psde->pipe_cfg.horz_decimation =
776 sde_plane_get_property(pstate, PLANE_PROP_H_DECIMATE);
777 psde->pipe_cfg.vert_decimation =
778 sde_plane_get_property(pstate, PLANE_PROP_V_DECIMATE);
Clarence Ip04ec67d2016-05-26 01:16:15 -0400779
780 /* don't chroma subsample if decimating */
781 chroma_subsmpl_h = psde->pipe_cfg.horz_decimation ? 1 :
Lloyd Atkinson9a673492016-07-05 11:41:57 -0400782 drm_format_horz_chroma_subsampling(fmt->base.pixel_format);
Clarence Ip04ec67d2016-05-26 01:16:15 -0400783 chroma_subsmpl_v = psde->pipe_cfg.vert_decimation ? 1 :
Lloyd Atkinson9a673492016-07-05 11:41:57 -0400784 drm_format_vert_chroma_subsampling(fmt->base.pixel_format);
Clarence Ip04ec67d2016-05-26 01:16:15 -0400785
Clarence Ip5e2a9222016-06-26 22:38:24 -0400786 /* update scaler */
787 if (psde->features & BIT(SDE_SSPP_SCALER_QSEED3)) {
Clarence Ipb43d4592016-09-08 14:21:35 -0400788 if (!psde->pixel_ext_usr) {
789 /* calculate default config for QSEED3 */
Clarence Ipcb410d42016-06-26 22:52:33 -0400790 _sde_plane_setup_scaler3(psde,
791 psde->pipe_cfg.src_rect.w,
792 psde->pipe_cfg.src_rect.h,
793 psde->pipe_cfg.dst_rect.w,
794 psde->pipe_cfg.dst_rect.h,
795 &psde->scaler3_cfg, fmt,
Clarence Ip5e2a9222016-06-26 22:38:24 -0400796 chroma_subsmpl_h, chroma_subsmpl_v);
Clarence Ip5e2a9222016-06-26 22:38:24 -0400797 }
Clarence Ipb43d4592016-09-08 14:21:35 -0400798 } else if (!psde->pixel_ext_usr) {
799 /* calculate default configuration for QSEED2 */
800 memset(pe, 0, sizeof(struct sde_hw_pixel_ext));
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -0400801
Clarence Ip13a8cf42016-09-29 17:27:47 -0400802 SDE_DEBUG_PLANE(psde, "default config\n");
Clarence Ipb43d4592016-09-08 14:21:35 -0400803 _sde_plane_setup_scaler2(psde,
804 psde->pipe_cfg.src_rect.w,
805 psde->pipe_cfg.dst_rect.w,
806 pe->phase_step_x,
807 pe->horz_filter, fmt, chroma_subsmpl_h);
808 _sde_plane_setup_scaler2(psde,
809 psde->pipe_cfg.src_rect.h,
810 psde->pipe_cfg.dst_rect.h,
811 pe->phase_step_y,
812 pe->vert_filter, fmt, chroma_subsmpl_v);
Clarence Ip5e2a9222016-06-26 22:38:24 -0400813
Clarence Ip5e2a9222016-06-26 22:38:24 -0400814 /* calculate left/right/top/bottom pixel extensions */
Clarence Ipcb410d42016-06-26 22:52:33 -0400815 tmp = DECIMATED_DIMENSION(psde->pipe_cfg.src_rect.w,
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -0400816 psde->pipe_cfg.horz_decimation);
Clarence Ipdbde9832016-06-26 09:48:36 -0400817 if (SDE_FORMAT_IS_YUV(fmt))
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -0400818 tmp &= ~0x1;
Clarence Ipcb410d42016-06-26 22:52:33 -0400819 _sde_plane_setup_pixel_ext(psde, psde->pipe_cfg.src_rect.w,
820 psde->pipe_cfg.dst_rect.w, tmp,
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -0400821 pe->phase_step_x,
822 pe->roi_w,
823 pe->num_ext_pxls_left,
Clarence Ipe78efb72016-06-24 18:35:21 -0400824 pe->num_ext_pxls_right, pe->horz_filter, fmt,
Clarence Ip5e2a9222016-06-26 22:38:24 -0400825 chroma_subsmpl_h, 0);
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -0400826
Clarence Ipcb410d42016-06-26 22:52:33 -0400827 tmp = DECIMATED_DIMENSION(psde->pipe_cfg.src_rect.h,
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -0400828 psde->pipe_cfg.vert_decimation);
Clarence Ipcb410d42016-06-26 22:52:33 -0400829 _sde_plane_setup_pixel_ext(psde, psde->pipe_cfg.src_rect.h,
830 psde->pipe_cfg.dst_rect.h, tmp,
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -0400831 pe->phase_step_y,
832 pe->roi_h,
833 pe->num_ext_pxls_top,
Clarence Ipe78efb72016-06-24 18:35:21 -0400834 pe->num_ext_pxls_btm, pe->vert_filter, fmt,
Clarence Ip5e2a9222016-06-26 22:38:24 -0400835 chroma_subsmpl_v, 1);
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -0400836
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -0400837 for (i = 0; i < SDE_MAX_PLANES; i++) {
838 if (pe->num_ext_pxls_left[i] >= 0)
Clarence Ipb43d4592016-09-08 14:21:35 -0400839 pe->left_rpt[i] = pe->num_ext_pxls_left[i];
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -0400840 else
Clarence Ipb43d4592016-09-08 14:21:35 -0400841 pe->left_ftch[i] = pe->num_ext_pxls_left[i];
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -0400842
843 if (pe->num_ext_pxls_right[i] >= 0)
Clarence Ipb43d4592016-09-08 14:21:35 -0400844 pe->right_rpt[i] = pe->num_ext_pxls_right[i];
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -0400845 else
Clarence Ipb43d4592016-09-08 14:21:35 -0400846 pe->right_ftch[i] = pe->num_ext_pxls_right[i];
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -0400847
848 if (pe->num_ext_pxls_top[i] >= 0)
Clarence Ipb43d4592016-09-08 14:21:35 -0400849 pe->top_rpt[i] = pe->num_ext_pxls_top[i];
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -0400850 else
Clarence Ipb43d4592016-09-08 14:21:35 -0400851 pe->top_ftch[i] = pe->num_ext_pxls_top[i];
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -0400852
853 if (pe->num_ext_pxls_btm[i] >= 0)
Clarence Ipb43d4592016-09-08 14:21:35 -0400854 pe->btm_rpt[i] = pe->num_ext_pxls_btm[i];
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -0400855 else
Clarence Ipb43d4592016-09-08 14:21:35 -0400856 pe->btm_ftch[i] = pe->num_ext_pxls_btm[i];
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -0400857 }
858 }
Clarence Ipcb410d42016-06-26 22:52:33 -0400859}
860
Clarence Ipcae1bb62016-07-07 12:07:13 -0400861/**
862 * _sde_plane_color_fill - enables color fill on plane
Clarence Ip13a8cf42016-09-29 17:27:47 -0400863 * @psde: Pointer to SDE plane object
Clarence Ipcae1bb62016-07-07 12:07:13 -0400864 * @color: RGB fill color value, [23..16] Blue, [15..8] Green, [7..0] Red
865 * @alpha: 8-bit fill alpha value, 255 selects 100% alpha
866 * Returns: 0 on success
867 */
Clarence Ip13a8cf42016-09-29 17:27:47 -0400868static int _sde_plane_color_fill(struct sde_plane *psde,
Clarence Ipcb410d42016-06-26 22:52:33 -0400869 uint32_t color, uint32_t alpha)
870{
Lloyd Atkinson9a673492016-07-05 11:41:57 -0400871 const struct sde_format *fmt;
Clarence Ipcb410d42016-06-26 22:52:33 -0400872
Clarence Ip13a8cf42016-09-29 17:27:47 -0400873 if (!psde) {
Dhaval Patel47302cf2016-08-18 15:04:28 -0700874 SDE_ERROR("invalid plane\n");
Clarence Ipcb410d42016-06-26 22:52:33 -0400875 return -EINVAL;
876 }
877
Clarence Ipcb410d42016-06-26 22:52:33 -0400878 if (!psde->pipe_hw) {
Clarence Ip13a8cf42016-09-29 17:27:47 -0400879 SDE_ERROR_PLANE(psde, "invalid plane h/w pointer\n");
Clarence Ipcb410d42016-06-26 22:52:33 -0400880 return -EINVAL;
881 }
882
Clarence Ip13a8cf42016-09-29 17:27:47 -0400883 SDE_DEBUG_PLANE(psde, "\n");
Clarence Ipcae1bb62016-07-07 12:07:13 -0400884
Clarence Ipcb410d42016-06-26 22:52:33 -0400885 /*
886 * select fill format to match user property expectation,
887 * h/w only supports RGB variants
888 */
Lloyd Atkinson9a673492016-07-05 11:41:57 -0400889 fmt = sde_get_sde_format(DRM_FORMAT_ABGR8888);
Clarence Ipcb410d42016-06-26 22:52:33 -0400890
891 /* update sspp */
892 if (fmt && psde->pipe_hw->ops.setup_solidfill) {
893 psde->pipe_hw->ops.setup_solidfill(psde->pipe_hw,
894 (color & 0xFFFFFF) | ((alpha & 0xFF) << 24));
895
896 /* override scaler/decimation if solid fill */
897 psde->pipe_cfg.src_rect.x = 0;
898 psde->pipe_cfg.src_rect.y = 0;
899 psde->pipe_cfg.src_rect.w = psde->pipe_cfg.dst_rect.w;
900 psde->pipe_cfg.src_rect.h = psde->pipe_cfg.dst_rect.h;
901
902 _sde_plane_setup_scaler(psde, fmt, 0);
903
904 if (psde->pipe_hw->ops.setup_format)
905 psde->pipe_hw->ops.setup_format(psde->pipe_hw,
906 fmt, SDE_SSPP_SOLID_FILL);
907
908 if (psde->pipe_hw->ops.setup_rects)
909 psde->pipe_hw->ops.setup_rects(psde->pipe_hw,
910 &psde->pipe_cfg, &psde->pixel_ext);
911 }
912
913 return 0;
914}
915
916static int _sde_plane_mode_set(struct drm_plane *plane,
Dhaval Patel47302cf2016-08-18 15:04:28 -0700917 struct drm_plane_state *state)
Clarence Ipcb410d42016-06-26 22:52:33 -0400918{
Clarence Ip282dad62016-09-27 17:07:35 -0400919 uint32_t nplanes, src_flags, zpos, split_w;
Clarence Ipcb410d42016-06-26 22:52:33 -0400920 struct sde_plane *psde;
921 struct sde_plane_state *pstate;
Lloyd Atkinson9a673492016-07-05 11:41:57 -0400922 const struct sde_format *fmt;
Dhaval Patel47302cf2016-08-18 15:04:28 -0700923 struct drm_crtc *crtc;
924 struct drm_framebuffer *fb;
925 struct sde_rect src, dst;
926 bool q16_data = true;
Clarence Ip282dad62016-09-27 17:07:35 -0400927 int idx;
Clarence Ipcb410d42016-06-26 22:52:33 -0400928
Clarence Ip13a8cf42016-09-29 17:27:47 -0400929 if (!plane) {
Clarence Ip282dad62016-09-27 17:07:35 -0400930 SDE_ERROR("invalid plane\n");
931 return -EINVAL;
932 } else if (!plane->state) {
933 SDE_ERROR("invalid plane state\n");
Clarence Ipcb410d42016-06-26 22:52:33 -0400934 return -EINVAL;
935 }
936
937 psde = to_sde_plane(plane);
938 pstate = to_sde_plane_state(plane->state);
Clarence Ipcb410d42016-06-26 22:52:33 -0400939
Dhaval Patel47302cf2016-08-18 15:04:28 -0700940 crtc = state->crtc;
941 fb = state->fb;
942 if (!crtc || !fb) {
Clarence Ip13a8cf42016-09-29 17:27:47 -0400943 SDE_ERROR_PLANE(psde, "invalid crtc %d or fb %d\n",
944 crtc != 0, fb != 0);
Dhaval Patel47302cf2016-08-18 15:04:28 -0700945 return -EINVAL;
946 }
Lloyd Atkinson9a673492016-07-05 11:41:57 -0400947 fmt = to_sde_format(msm_framebuffer_format(fb));
Lloyd Atkinsonfa2489c2016-05-25 15:16:03 -0400948 nplanes = fmt->num_planes;
Clarence Ipcb410d42016-06-26 22:52:33 -0400949
Clarence Ip282dad62016-09-27 17:07:35 -0400950 /* determine what needs to be refreshed */
951 while ((idx = msm_property_pop_dirty(&psde->property_info)) >= 0) {
952 switch (idx) {
Clarence Ipb43d4592016-09-08 14:21:35 -0400953 case PLANE_PROP_SCALER_V1:
Clarence Ipdedbba92016-09-27 17:43:10 -0400954 case PLANE_PROP_H_DECIMATE:
955 case PLANE_PROP_V_DECIMATE:
956 case PLANE_PROP_SRC_CONFIG:
957 case PLANE_PROP_ZPOS:
Clarence Ip282dad62016-09-27 17:07:35 -0400958 pstate->dirty |= SDE_PLANE_DIRTY_RECTS;
959 break;
Clarence Ip5fc00c52016-09-23 15:03:34 -0400960 case PLANE_PROP_CSC_V1:
Clarence Ip282dad62016-09-27 17:07:35 -0400961 pstate->dirty |= SDE_PLANE_DIRTY_FORMAT;
962 break;
963 case PLANE_PROP_COLOR_FILL:
964 /* potentially need to refresh everything */
965 pstate->dirty = SDE_PLANE_DIRTY_ALL;
966 break;
967 case PLANE_PROP_ROTATION:
968 pstate->dirty |= SDE_PLANE_DIRTY_FORMAT;
969 break;
Clarence Ip282dad62016-09-27 17:07:35 -0400970 case PLANE_PROP_INFO:
971 case PLANE_PROP_ALPHA:
972 case PLANE_PROP_INPUT_FENCE:
973 case PLANE_PROP_BLEND_OP:
974 /* no special action required */
975 break;
976 default:
977 /* unknown property, refresh everything */
978 pstate->dirty |= SDE_PLANE_DIRTY_ALL;
979 SDE_ERROR("executing full mode set, prp_idx %d\n", idx);
980 break;
981 }
Clarence Ipcb410d42016-06-26 22:52:33 -0400982 }
983
Clarence Ip282dad62016-09-27 17:07:35 -0400984 if (pstate->dirty & SDE_PLANE_DIRTY_RECTS)
985 memset(&(psde->pipe_cfg), 0, sizeof(struct sde_hw_pipe_cfg));
Clarence Ipcb410d42016-06-26 22:52:33 -0400986
987 _sde_plane_set_scanout(plane, pstate, &psde->pipe_cfg, fb);
988
Clarence Ip282dad62016-09-27 17:07:35 -0400989 /* early out if nothing dirty */
990 if (!pstate->dirty)
991 return 0;
992 pstate->pending = true;
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -0400993
Clarence Ip282dad62016-09-27 17:07:35 -0400994 psde->is_rt_pipe = _sde_plane_is_rt_pipe(plane, crtc);
995 _sde_plane_set_qos_ctrl(plane, false, SDE_PLANE_QOS_PANIC_CTRL);
996
997 /* update roi config */
998 if (pstate->dirty & SDE_PLANE_DIRTY_RECTS) {
999 POPULATE_RECT(&src, state->src_x, state->src_y,
1000 state->src_w, state->src_h, q16_data);
1001 POPULATE_RECT(&dst, state->crtc_x, state->crtc_y,
1002 state->crtc_w, state->crtc_h, !q16_data);
1003
Clarence Ip13a8cf42016-09-29 17:27:47 -04001004 SDE_DEBUG_PLANE(psde,
1005 "FB[%u] %u,%u,%ux%u->crtc%u %d,%d,%ux%u, %s ubwc %d\n",
Clarence Ip282dad62016-09-27 17:07:35 -04001006 fb->base.id, src.x, src.y, src.w, src.h,
1007 crtc->base.id, dst.x, dst.y, dst.w, dst.h,
1008 drm_get_format_name(fmt->base.pixel_format),
1009 SDE_FORMAT_IS_UBWC(fmt));
1010
1011 if (sde_plane_get_property(pstate, PLANE_PROP_SRC_CONFIG) &
1012 BIT(SDE_DRM_DEINTERLACE)) {
Clarence Ip13a8cf42016-09-29 17:27:47 -04001013 SDE_DEBUG_PLANE(psde, "deinterlace\n");
Clarence Ip282dad62016-09-27 17:07:35 -04001014 for (idx = 0; idx < SDE_MAX_PLANES; ++idx)
1015 psde->pipe_cfg.layout.plane_pitch[idx] <<= 1;
1016 src.h /= 2;
1017 src.y = DIV_ROUND_UP(src.y, 2);
1018 src.y &= ~0x1;
1019 }
1020
1021 psde->pipe_cfg.src_rect = src;
1022 psde->pipe_cfg.dst_rect = dst;
1023
1024 /* check for color fill */
1025 psde->color_fill = (uint32_t)sde_plane_get_property(pstate,
1026 PLANE_PROP_COLOR_FILL);
1027 if (psde->color_fill & SDE_PLANE_COLOR_FILL_FLAG) {
1028 /* skip remaining processing on color fill */
1029 pstate->dirty = 0x0;
1030 } else if (psde->pipe_hw->ops.setup_rects) {
1031 _sde_plane_setup_scaler(psde, fmt, pstate);
1032
1033 /* base layer source split needs update */
1034 zpos = sde_plane_get_property(pstate, PLANE_PROP_ZPOS);
1035 if (zpos == SDE_STAGE_BASE) {
1036 split_w = get_crtc_split_width(crtc);
1037 if (psde->pipe_cfg.dst_rect.x >= split_w)
1038 psde->pipe_cfg.dst_rect.x -= split_w;
1039 }
1040 psde->pipe_hw->ops.setup_rects(psde->pipe_hw,
1041 &psde->pipe_cfg, &psde->pixel_ext);
1042 }
Dhaval Patel48c76022016-09-01 17:51:23 -07001043 }
1044
Clarence Ip282dad62016-09-27 17:07:35 -04001045 if ((pstate->dirty & SDE_PLANE_DIRTY_FORMAT) &&
1046 psde->pipe_hw->ops.setup_format) {
1047 src_flags = 0x0;
Clarence Ip13a8cf42016-09-29 17:27:47 -04001048 SDE_DEBUG_PLANE(psde, "rotation 0x%llX\n",
Clarence Ip282dad62016-09-27 17:07:35 -04001049 sde_plane_get_property(pstate, PLANE_PROP_ROTATION));
1050 if (sde_plane_get_property(pstate, PLANE_PROP_ROTATION) &
1051 BIT(DRM_REFLECT_X))
1052 src_flags |= SDE_SSPP_FLIP_LR;
1053 if (sde_plane_get_property(pstate, PLANE_PROP_ROTATION) &
1054 BIT(DRM_REFLECT_Y))
1055 src_flags |= SDE_SSPP_FLIP_UD;
1056
1057 /* update format */
1058 psde->pipe_hw->ops.setup_format(psde->pipe_hw, fmt, src_flags);
1059
1060 /* update csc */
1061 if (SDE_FORMAT_IS_YUV(fmt))
Clarence Ip5fc00c52016-09-23 15:03:34 -04001062 _sde_plane_setup_csc(psde);
Clarence Ip282dad62016-09-27 17:07:35 -04001063 else
1064 psde->csc_ptr = 0;
1065 }
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001066
Clarence Ipe78efb72016-06-24 18:35:21 -04001067 /* update sharpening */
Clarence Ip282dad62016-09-27 17:07:35 -04001068 if ((pstate->dirty & SDE_PLANE_DIRTY_SHARPEN) &&
1069 psde->pipe_hw->ops.setup_sharpening) {
1070 psde->sharp_cfg.strength = SHARP_STRENGTH_DEFAULT;
1071 psde->sharp_cfg.edge_thr = SHARP_EDGE_THR_DEFAULT;
1072 psde->sharp_cfg.smooth_thr = SHARP_SMOOTH_THR_DEFAULT;
1073 psde->sharp_cfg.noise_thr = SHARP_NOISE_THR_DEFAULT;
Clarence Ipe78efb72016-06-24 18:35:21 -04001074
Clarence Ipe78efb72016-06-24 18:35:21 -04001075 psde->pipe_hw->ops.setup_sharpening(psde->pipe_hw,
Clarence Ip282dad62016-09-27 17:07:35 -04001076 &psde->sharp_cfg);
1077 }
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001078
Alan Kwong1a00e4d2016-07-18 09:42:30 -04001079 _sde_plane_set_qos_lut(plane, fb);
1080 _sde_plane_set_danger_lut(plane, fb);
1081
Alan Kwong5d324e42016-07-28 22:56:18 -04001082 if (plane->type != DRM_PLANE_TYPE_CURSOR) {
Alan Kwong1a00e4d2016-07-18 09:42:30 -04001083 _sde_plane_set_qos_ctrl(plane, true, SDE_PLANE_QOS_PANIC_CTRL);
Alan Kwong5d324e42016-07-28 22:56:18 -04001084 _sde_plane_set_ot_limit(plane, crtc);
1085 }
Alan Kwong1a00e4d2016-07-18 09:42:30 -04001086
Clarence Ip282dad62016-09-27 17:07:35 -04001087 /* clear dirty */
1088 pstate->dirty = 0x0;
1089
Clarence Ip5e2a9222016-06-26 22:38:24 -04001090 return 0;
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001091}
1092
1093static int sde_plane_prepare_fb(struct drm_plane *plane,
1094 const struct drm_plane_state *new_state)
1095{
1096 struct drm_framebuffer *fb = new_state->fb;
1097 struct sde_plane *psde = to_sde_plane(plane);
1098
1099 if (!new_state->fb)
1100 return 0;
1101
Clarence Ip13a8cf42016-09-29 17:27:47 -04001102 SDE_DEBUG_PLANE(psde, "FB[%u]\n", fb->base.id);
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001103 return msm_framebuffer_prepare(fb, psde->mmu_id);
1104}
1105
1106static void sde_plane_cleanup_fb(struct drm_plane *plane,
1107 const struct drm_plane_state *old_state)
1108{
Clarence Ip13a8cf42016-09-29 17:27:47 -04001109 struct drm_framebuffer *fb = old_state ? old_state->fb : NULL;
1110 struct sde_plane *psde = plane ? to_sde_plane(plane) : NULL;
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001111
1112 if (!fb)
1113 return;
1114
Clarence Ip13a8cf42016-09-29 17:27:47 -04001115 SDE_DEBUG_PLANE(psde, "FB[%u]\n", fb->base.id);
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001116 msm_framebuffer_cleanup(fb, psde->mmu_id);
1117}
1118
Lloyd Atkinsonfa2489c2016-05-25 15:16:03 -04001119static void _sde_plane_atomic_check_mode_changed(struct sde_plane *psde,
1120 struct drm_plane_state *state,
1121 struct drm_plane_state *old_state)
1122{
1123 struct sde_plane_state *pstate = to_sde_plane_state(state);
1124
Dhaval Patel47302cf2016-08-18 15:04:28 -07001125 /* no need to check it again */
Clarence Ip282dad62016-09-27 17:07:35 -04001126 if (pstate->dirty == SDE_PLANE_DIRTY_ALL)
Dhaval Patel47302cf2016-08-18 15:04:28 -07001127 return;
1128
Clarence Ip282dad62016-09-27 17:07:35 -04001129 if (!sde_plane_enabled(state) || !sde_plane_enabled(old_state)
1130 || psde->is_error) {
Clarence Ip13a8cf42016-09-29 17:27:47 -04001131 SDE_DEBUG_PLANE(psde,
1132 "enabling/disabling full modeset required\n");
Clarence Ip282dad62016-09-27 17:07:35 -04001133 pstate->dirty |= SDE_PLANE_DIRTY_ALL;
Lloyd Atkinsonfa2489c2016-05-25 15:16:03 -04001134 } else if (to_sde_plane_state(old_state)->pending) {
Clarence Ip13a8cf42016-09-29 17:27:47 -04001135 SDE_DEBUG_PLANE(psde, "still pending\n");
Clarence Ip282dad62016-09-27 17:07:35 -04001136 pstate->dirty |= SDE_PLANE_DIRTY_ALL;
Lloyd Atkinsonfa2489c2016-05-25 15:16:03 -04001137 } else if (state->src_w != old_state->src_w ||
Dhaval Patel47302cf2016-08-18 15:04:28 -07001138 state->src_h != old_state->src_h ||
1139 state->src_x != old_state->src_x ||
1140 state->src_y != old_state->src_y) {
Clarence Ip13a8cf42016-09-29 17:27:47 -04001141 SDE_DEBUG_PLANE(psde, "src rect updated\n");
Clarence Ip282dad62016-09-27 17:07:35 -04001142 pstate->dirty |= SDE_PLANE_DIRTY_RECTS;
Dhaval Patel47302cf2016-08-18 15:04:28 -07001143 } else if (state->crtc_w != old_state->crtc_w ||
1144 state->crtc_h != old_state->crtc_h ||
1145 state->crtc_x != old_state->crtc_x ||
1146 state->crtc_y != old_state->crtc_y) {
Clarence Ip13a8cf42016-09-29 17:27:47 -04001147 SDE_DEBUG_PLANE(psde, "crtc rect updated\n");
Clarence Ip282dad62016-09-27 17:07:35 -04001148 pstate->dirty |= SDE_PLANE_DIRTY_RECTS;
1149 }
1150
1151 if (!state->fb || !old_state->fb) {
Clarence Ip13a8cf42016-09-29 17:27:47 -04001152 SDE_DEBUG_PLANE(psde, "can't compare fb handles\n");
Lloyd Atkinsonfa2489c2016-05-25 15:16:03 -04001153 } else if (state->fb->pixel_format != old_state->fb->pixel_format) {
Clarence Ip13a8cf42016-09-29 17:27:47 -04001154 SDE_DEBUG_PLANE(psde, "format change\n");
Clarence Ip282dad62016-09-27 17:07:35 -04001155 pstate->dirty |= SDE_PLANE_DIRTY_FORMAT | SDE_PLANE_DIRTY_RECTS;
Dhaval Patel47302cf2016-08-18 15:04:28 -07001156 } else {
Lloyd Atkinsonfa2489c2016-05-25 15:16:03 -04001157 uint64_t *new_mods = state->fb->modifier;
1158 uint64_t *old_mods = old_state->fb->modifier;
Dhaval Patel47302cf2016-08-18 15:04:28 -07001159 uint32_t *new_pitches = state->fb->pitches;
1160 uint32_t *old_pitches = old_state->fb->pitches;
1161 uint32_t *new_offset = state->fb->offsets;
1162 uint32_t *old_offset = old_state->fb->offsets;
Lloyd Atkinsonfa2489c2016-05-25 15:16:03 -04001163 int i;
1164
1165 for (i = 0; i < ARRAY_SIZE(state->fb->modifier); i++) {
1166 if (new_mods[i] != old_mods[i]) {
Clarence Ip13a8cf42016-09-29 17:27:47 -04001167 SDE_DEBUG_PLANE(psde,
1168 "format modifiers change\"\
Dhaval Patel47302cf2016-08-18 15:04:28 -07001169 plane:%d new_mode:%llu old_mode:%llu\n",
Clarence Ip13a8cf42016-09-29 17:27:47 -04001170 i, new_mods[i], old_mods[i]);
Clarence Ip282dad62016-09-27 17:07:35 -04001171 pstate->dirty |= SDE_PLANE_DIRTY_FORMAT |
1172 SDE_PLANE_DIRTY_RECTS;
Lloyd Atkinsonfa2489c2016-05-25 15:16:03 -04001173 break;
1174 }
1175 }
Lloyd Atkinson3ab9ef72016-07-14 17:42:41 -04001176 for (i = 0; i < ARRAY_SIZE(state->fb->pitches); i++) {
1177 if (new_pitches[i] != old_pitches[i]) {
Clarence Ip13a8cf42016-09-29 17:27:47 -04001178 SDE_DEBUG_PLANE(psde,
1179 "pitches change plane:%d\"\
Dhaval Patel47302cf2016-08-18 15:04:28 -07001180 old_pitches:%u new_pitches:%u\n",
Clarence Ip13a8cf42016-09-29 17:27:47 -04001181 i, old_pitches[i], new_pitches[i]);
Clarence Ip282dad62016-09-27 17:07:35 -04001182 pstate->dirty |= SDE_PLANE_DIRTY_RECTS;
Lloyd Atkinson3ab9ef72016-07-14 17:42:41 -04001183 break;
1184 }
1185 }
Dhaval Patel47302cf2016-08-18 15:04:28 -07001186 for (i = 0; i < ARRAY_SIZE(state->fb->offsets); i++) {
1187 if (new_offset[i] != old_offset[i]) {
Clarence Ip13a8cf42016-09-29 17:27:47 -04001188 SDE_DEBUG_PLANE(psde,
1189 "offset change plane:%d\"\
Dhaval Patel47302cf2016-08-18 15:04:28 -07001190 old_offset:%u new_offset:%u\n",
Clarence Ip13a8cf42016-09-29 17:27:47 -04001191 i, old_offset[i], new_offset[i]);
Clarence Ip282dad62016-09-27 17:07:35 -04001192 pstate->dirty |= SDE_PLANE_DIRTY_FORMAT |
1193 SDE_PLANE_DIRTY_RECTS;
Dhaval Patel47302cf2016-08-18 15:04:28 -07001194 break;
1195 }
1196 }
Lloyd Atkinson3ab9ef72016-07-14 17:42:41 -04001197 }
Lloyd Atkinsonfa2489c2016-05-25 15:16:03 -04001198}
1199
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001200static int sde_plane_atomic_check(struct drm_plane *plane,
1201 struct drm_plane_state *state)
1202{
Clarence Ipdedbba92016-09-27 17:43:10 -04001203 int ret = 0;
Clarence Ipdbde9832016-06-26 09:48:36 -04001204 struct sde_plane *psde;
1205 struct sde_plane_state *pstate;
Lloyd Atkinson9a673492016-07-05 11:41:57 -04001206 const struct sde_format *fmt;
Dhaval Patel47302cf2016-08-18 15:04:28 -07001207 struct sde_rect src, dst;
Clarence Ipdbde9832016-06-26 09:48:36 -04001208 uint32_t deci_w, deci_h, src_deci_w, src_deci_h;
Dhaval Patel47302cf2016-08-18 15:04:28 -07001209 uint32_t max_upscale, max_downscale, min_src_size, max_linewidth;
1210 bool q16_data = true;
Clarence Ipdbde9832016-06-26 09:48:36 -04001211
1212 if (!plane || !state) {
Clarence Ip13a8cf42016-09-29 17:27:47 -04001213 SDE_ERROR("invalid arg(s), plane %d state %d\n",
1214 plane != 0, state != 0);
Clarence Ipdbde9832016-06-26 09:48:36 -04001215 ret = -EINVAL;
1216 goto exit;
1217 }
1218
1219 psde = to_sde_plane(plane);
1220 pstate = to_sde_plane_state(state);
Clarence Ipdbde9832016-06-26 09:48:36 -04001221
1222 if (!psde->pipe_sblk) {
Clarence Ip13a8cf42016-09-29 17:27:47 -04001223 SDE_ERROR_PLANE(psde, "invalid catalog\n");
Clarence Ipdbde9832016-06-26 09:48:36 -04001224 ret = -EINVAL;
1225 goto exit;
1226 }
1227
Clarence Ipdedbba92016-09-27 17:43:10 -04001228 deci_w = sde_plane_get_property(pstate, PLANE_PROP_H_DECIMATE);
1229 deci_h = sde_plane_get_property(pstate, PLANE_PROP_V_DECIMATE);
Clarence Ipdbde9832016-06-26 09:48:36 -04001230
1231 /* src values are in Q16 fixed point, convert to integer */
Dhaval Patel47302cf2016-08-18 15:04:28 -07001232 POPULATE_RECT(&src, state->src_x, state->src_y, state->src_w,
1233 state->src_h, q16_data);
1234 POPULATE_RECT(&dst, state->crtc_x, state->crtc_y, state->crtc_w,
1235 state->crtc_h, !q16_data);
Clarence Ipdbde9832016-06-26 09:48:36 -04001236
Dhaval Patel47302cf2016-08-18 15:04:28 -07001237 src_deci_w = DECIMATED_DIMENSION(src.w, deci_w);
1238 src_deci_h = DECIMATED_DIMENSION(src.h, deci_h);
Clarence Ipdbde9832016-06-26 09:48:36 -04001239
Dhaval Patel47302cf2016-08-18 15:04:28 -07001240 max_upscale = psde->pipe_sblk->maxupscale;
1241 max_downscale = psde->pipe_sblk->maxdwnscale;
1242 max_linewidth = psde->pipe_sblk->maxlinewidth;
Clarence Ipdbde9832016-06-26 09:48:36 -04001243
Clarence Ip13a8cf42016-09-29 17:27:47 -04001244 SDE_DEBUG_PLANE(psde, "check %d -> %d\n",
Dhaval Patel47302cf2016-08-18 15:04:28 -07001245 sde_plane_enabled(plane->state), sde_plane_enabled(state));
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001246
Dhaval Patel47302cf2016-08-18 15:04:28 -07001247 if (!sde_plane_enabled(state))
1248 goto modeset_update;
Clarence Ipdbde9832016-06-26 09:48:36 -04001249
Dhaval Patel47302cf2016-08-18 15:04:28 -07001250 fmt = to_sde_format(msm_framebuffer_format(state->fb));
1251
1252 min_src_size = SDE_FORMAT_IS_YUV(fmt) ? 2 : 1;
1253
1254 if (SDE_FORMAT_IS_YUV(fmt) &&
1255 (!(psde->features & SDE_SSPP_SCALER) ||
1256 !(psde->features & BIT(SDE_SSPP_CSC)))) {
Clarence Ip13a8cf42016-09-29 17:27:47 -04001257 SDE_ERROR_PLANE(psde,
1258 "plane doesn't have scaler/csc for yuv\n");
Dhaval Patel47302cf2016-08-18 15:04:28 -07001259 ret = -EINVAL;
1260
1261 /* check src bounds */
1262 } else if (state->fb->width > MAX_IMG_WIDTH ||
1263 state->fb->height > MAX_IMG_HEIGHT ||
1264 src.w < min_src_size || src.h < min_src_size ||
1265 CHECK_LAYER_BOUNDS(src.x, src.w, state->fb->width) ||
1266 CHECK_LAYER_BOUNDS(src.y, src.h, state->fb->height)) {
Clarence Ip13a8cf42016-09-29 17:27:47 -04001267 SDE_ERROR_PLANE(psde, "invalid source %u, %u, %ux%u\n",
Dhaval Patel47302cf2016-08-18 15:04:28 -07001268 src.x, src.y, src.w, src.h);
1269 ret = -E2BIG;
1270
1271 /* valid yuv image */
1272 } else if (SDE_FORMAT_IS_YUV(fmt) && ((src.x & 0x1) || (src.y & 0x1) ||
1273 (src.w & 0x1) || (src.h & 0x1))) {
Clarence Ip13a8cf42016-09-29 17:27:47 -04001274 SDE_ERROR_PLANE(psde, "invalid yuv source %u, %u, %ux%u\n",
Dhaval Patel47302cf2016-08-18 15:04:28 -07001275 src.x, src.y, src.w, src.h);
1276 ret = -EINVAL;
1277
1278 /* min dst support */
1279 } else if (dst.w < 0x1 || dst.h < 0x1) {
Clarence Ip13a8cf42016-09-29 17:27:47 -04001280 SDE_ERROR_PLANE(psde, "invalid dest rect %u, %u, %ux%u\n",
Dhaval Patel47302cf2016-08-18 15:04:28 -07001281 dst.x, dst.y, dst.w, dst.h);
1282 ret = -EINVAL;
1283
1284 /* decimation validation */
1285 } else if (deci_w || deci_h) {
1286 if ((deci_w > psde->pipe_sblk->maxhdeciexp) ||
1287 (deci_h > psde->pipe_sblk->maxvdeciexp)) {
Clarence Ip13a8cf42016-09-29 17:27:47 -04001288 SDE_ERROR_PLANE(psde,
1289 "too much decimation requested\n");
Clarence Ipdbde9832016-06-26 09:48:36 -04001290 ret = -EINVAL;
Dhaval Patel47302cf2016-08-18 15:04:28 -07001291 } else if (fmt->fetch_mode != SDE_FETCH_LINEAR) {
Clarence Ip13a8cf42016-09-29 17:27:47 -04001292 SDE_ERROR_PLANE(psde,
1293 "decimation requires linear fetch\n");
Clarence Ipdbde9832016-06-26 09:48:36 -04001294 ret = -EINVAL;
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001295 }
1296
Dhaval Patel47302cf2016-08-18 15:04:28 -07001297 } else if (!(psde->features & SDE_SSPP_SCALER) &&
1298 ((src.w != dst.w) || (src.h != dst.h))) {
Clarence Ip13a8cf42016-09-29 17:27:47 -04001299 SDE_ERROR_PLANE(psde,
1300 "pipe doesn't support scaling %ux%u->%ux%u\n",
Dhaval Patel47302cf2016-08-18 15:04:28 -07001301 src.w, src.h, dst.w, dst.h);
1302 ret = -EINVAL;
1303
1304 /* check decimated source width */
1305 } else if (src_deci_w > max_linewidth) {
Clarence Ip13a8cf42016-09-29 17:27:47 -04001306 SDE_ERROR_PLANE(psde,
1307 "invalid src w:%u, deci w:%u, line w:%u\n",
Dhaval Patel47302cf2016-08-18 15:04:28 -07001308 src.w, src_deci_w, max_linewidth);
1309 ret = -E2BIG;
1310
1311 /* check max scaler capability */
1312 } else if (((src_deci_w * max_upscale) < dst.w) ||
1313 ((src_deci_h * max_upscale) < dst.h) ||
1314 ((dst.w * max_downscale) < src_deci_w) ||
1315 ((dst.h * max_downscale) < src_deci_h)) {
Clarence Ip13a8cf42016-09-29 17:27:47 -04001316 SDE_ERROR_PLANE(psde,
1317 "too much scaling requested %ux%u->%ux%u\n",
Dhaval Patel47302cf2016-08-18 15:04:28 -07001318 src_deci_w, src_deci_h, dst.w, dst.h);
1319 ret = -E2BIG;
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001320 }
1321
Dhaval Patel47302cf2016-08-18 15:04:28 -07001322modeset_update:
Lloyd Atkinsonfa2489c2016-05-25 15:16:03 -04001323 if (!ret)
Dhaval Patel47302cf2016-08-18 15:04:28 -07001324 _sde_plane_atomic_check_mode_changed(psde, state, plane->state);
Clarence Ipdbde9832016-06-26 09:48:36 -04001325exit:
1326 return ret;
1327}
1328
Clarence Ipcae1bb62016-07-07 12:07:13 -04001329/**
1330 * sde_plane_flush - final plane operations before commit flush
1331 * @plane: Pointer to drm plane structure
1332 */
1333void sde_plane_flush(struct drm_plane *plane)
Clarence Ipdbde9832016-06-26 09:48:36 -04001334{
Clarence Ipcae1bb62016-07-07 12:07:13 -04001335 struct sde_plane *psde;
1336
Clarence Ip13a8cf42016-09-29 17:27:47 -04001337 if (!plane) {
1338 SDE_ERROR("invalid plane\n");
Clarence Ipcae1bb62016-07-07 12:07:13 -04001339 return;
Clarence Ip13a8cf42016-09-29 17:27:47 -04001340 }
Clarence Ipcae1bb62016-07-07 12:07:13 -04001341
1342 psde = to_sde_plane(plane);
1343
1344 /*
1345 * These updates have to be done immediately before the plane flush
1346 * timing, and may not be moved to the atomic_update/mode_set functions.
1347 */
1348 if (psde->is_error)
1349 /* force white frame with 0% alpha pipe output on error */
Clarence Ip13a8cf42016-09-29 17:27:47 -04001350 _sde_plane_color_fill(psde, 0xFFFFFF, 0x0);
Clarence Ipcae1bb62016-07-07 12:07:13 -04001351 else if (psde->color_fill & SDE_PLANE_COLOR_FILL_FLAG)
1352 /* force 100% alpha */
Clarence Ip13a8cf42016-09-29 17:27:47 -04001353 _sde_plane_color_fill(psde, psde->color_fill, 0xFF);
Clarence Ipcae1bb62016-07-07 12:07:13 -04001354 else if (psde->pipe_hw && psde->csc_ptr && psde->pipe_hw->ops.setup_csc)
1355 psde->pipe_hw->ops.setup_csc(psde->pipe_hw, psde->csc_ptr);
1356
1357 /* flag h/w flush complete */
1358 if (plane->state)
Clarence Ipdbde9832016-06-26 09:48:36 -04001359 to_sde_plane_state(plane->state)->pending = false;
Narendra Muppalla1b0b3352015-09-29 10:16:51 -07001360}
1361
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001362static void sde_plane_atomic_update(struct drm_plane *plane,
Clarence Ipe78efb72016-06-24 18:35:21 -04001363 struct drm_plane_state *old_state)
Narendra Muppalla1b0b3352015-09-29 10:16:51 -07001364{
Clarence Ip13a8cf42016-09-29 17:27:47 -04001365 struct sde_plane *psde;
Clarence Ip5e2a9222016-06-26 22:38:24 -04001366 struct drm_plane_state *state;
1367 struct sde_plane_state *pstate;
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001368
Clarence Ip13a8cf42016-09-29 17:27:47 -04001369 if (!plane) {
1370 SDE_ERROR("invalid plane\n");
1371 return;
1372 } else if (!plane->state) {
1373 SDE_ERROR("invalid plane state\n");
Clarence Ip5e2a9222016-06-26 22:38:24 -04001374 return;
1375 }
1376
Clarence Ip13a8cf42016-09-29 17:27:47 -04001377 psde = to_sde_plane(plane);
1378 psde->is_error = false;
Clarence Ip5e2a9222016-06-26 22:38:24 -04001379 state = plane->state;
1380 pstate = to_sde_plane_state(state);
1381
Clarence Ip13a8cf42016-09-29 17:27:47 -04001382 SDE_DEBUG_PLANE(psde, "\n");
Clarence Ipae4e60c2016-06-26 22:44:04 -04001383
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001384 if (!sde_plane_enabled(state)) {
Clarence Ip5e2a9222016-06-26 22:38:24 -04001385 pstate->pending = true;
Clarence Ip282dad62016-09-27 17:07:35 -04001386 } else {
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001387 int ret;
1388
Dhaval Patel47302cf2016-08-18 15:04:28 -07001389 ret = _sde_plane_mode_set(plane, state);
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001390 /* atomic_check should have ensured that this doesn't fail */
1391 WARN_ON(ret < 0);
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001392 }
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001393}
1394
Dhaval Patel47302cf2016-08-18 15:04:28 -07001395
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001396/* helper to install properties which are common to planes and crtcs */
Dhaval Patel47302cf2016-08-18 15:04:28 -07001397static void _sde_plane_install_properties(struct drm_plane *plane,
1398 u32 max_blendstages)
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001399{
Clarence Ip5e2a9222016-06-26 22:38:24 -04001400 static const struct drm_prop_enum_list e_blend_op[] = {
1401 {SDE_DRM_BLEND_OP_NOT_DEFINED, "not_defined"},
1402 {SDE_DRM_BLEND_OP_OPAQUE, "opaque"},
1403 {SDE_DRM_BLEND_OP_PREMULTIPLIED, "premultiplied"},
1404 {SDE_DRM_BLEND_OP_COVERAGE, "coverage"}
1405 };
1406 static const struct drm_prop_enum_list e_src_config[] = {
1407 {SDE_DRM_DEINTERLACE, "deinterlace"}
1408 };
Clarence Ipea3d6262016-07-15 16:20:11 -04001409 const struct sde_format_extended *format_list;
Dhaval Patel4e574842016-08-23 15:11:37 -07001410 struct sde_kms_info *info;
Clarence Ip5e2a9222016-06-26 22:38:24 -04001411 struct sde_plane *psde = to_sde_plane(plane);
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001412
Clarence Ip13a8cf42016-09-29 17:27:47 -04001413 if (!plane || !psde) {
1414 SDE_ERROR("invalid plane\n");
1415 return;
1416 } else if (!psde->pipe_hw || !psde->pipe_sblk) {
1417 SDE_ERROR("invalid plane, pipe_hw %d pipe_sblk %d\n",
1418 psde->pipe_hw != 0, psde->pipe_sblk != 0);
Clarence Ip5e2a9222016-06-26 22:38:24 -04001419 return;
1420 }
1421
Dhaval Patel47302cf2016-08-18 15:04:28 -07001422 msm_property_install_range(&psde->property_info, "zpos", 0x0, 0,
Dhaval Patel48c76022016-09-01 17:51:23 -07001423 max_blendstages, SDE_STAGE_BASE, PLANE_PROP_ZPOS);
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001424
Lloyd Atkinson38ad8c92016-07-06 10:39:32 -04001425 msm_property_install_range(&psde->property_info, "alpha",
Dhaval Patel47302cf2016-08-18 15:04:28 -07001426 0x0, 0, 255, 255, PLANE_PROP_ALPHA);
Clarence Ip5e2a9222016-06-26 22:38:24 -04001427
Dhaval Patel47302cf2016-08-18 15:04:28 -07001428 /* linux default file descriptor range on each process */
Clarence Ipcae1bb62016-07-07 12:07:13 -04001429 msm_property_install_range(&psde->property_info, "input_fence",
Dhaval Patel4e574842016-08-23 15:11:37 -07001430 0x0, 0, INR_OPEN_MAX, 0, PLANE_PROP_INPUT_FENCE);
Clarence Ip5e2a9222016-06-26 22:38:24 -04001431
Clarence Ipdedbba92016-09-27 17:43:10 -04001432 if (psde->pipe_sblk->maxhdeciexp) {
1433 msm_property_install_range(&psde->property_info, "h_decimate",
1434 0x0, 0, psde->pipe_sblk->maxhdeciexp, 0,
1435 PLANE_PROP_H_DECIMATE);
1436 }
1437
1438 if (psde->pipe_sblk->maxvdeciexp) {
1439 msm_property_install_range(&psde->property_info, "v_decimate",
1440 0x0, 0, psde->pipe_sblk->maxvdeciexp, 0,
1441 PLANE_PROP_V_DECIMATE);
1442 }
1443
Clarence Ipb43d4592016-09-08 14:21:35 -04001444 if (psde->features & SDE_SSPP_SCALER) {
1445 msm_property_install_volatile_range(&psde->property_info,
1446 "scaler_v1", 0x0, 0, ~0, 0, PLANE_PROP_SCALER_V1);
1447 }
1448
Clarence Ip5fc00c52016-09-23 15:03:34 -04001449 if (psde->features & BIT(SDE_SSPP_CSC)) {
1450 msm_property_install_volatile_range(&psde->property_info,
1451 "csc_v1", 0x0, 0, ~0, 0, PLANE_PROP_CSC_V1);
1452 }
1453
Clarence Ip5e2a9222016-06-26 22:38:24 -04001454 /* standard properties */
Clarence Ipaa0faf42016-05-30 12:07:48 -04001455 msm_property_install_rotation(&psde->property_info,
Dhaval Patel47302cf2016-08-18 15:04:28 -07001456 BIT(DRM_REFLECT_X) | BIT(DRM_REFLECT_Y), PLANE_PROP_ROTATION);
Clarence Ip5e2a9222016-06-26 22:38:24 -04001457
Lloyd Atkinson38ad8c92016-07-06 10:39:32 -04001458 msm_property_install_enum(&psde->property_info, "blend_op", 0x0, 0,
Dhaval Patel47302cf2016-08-18 15:04:28 -07001459 e_blend_op, ARRAY_SIZE(e_blend_op), PLANE_PROP_BLEND_OP);
Clarence Ip5e2a9222016-06-26 22:38:24 -04001460
Dhaval Patel47302cf2016-08-18 15:04:28 -07001461 msm_property_install_enum(&psde->property_info, "src_config", 0x0, 1,
1462 e_src_config, ARRAY_SIZE(e_src_config), PLANE_PROP_SRC_CONFIG);
1463
1464 if (psde->pipe_hw->ops.setup_solidfill)
1465 msm_property_install_range(&psde->property_info, "color_fill",
1466 0, 0, 0xFFFFFFFF, 0, PLANE_PROP_COLOR_FILL);
1467
Dhaval Patel4e574842016-08-23 15:11:37 -07001468 info = kzalloc(sizeof(struct sde_kms_info), GFP_KERNEL);
Clarence Ip13a8cf42016-09-29 17:27:47 -04001469 if (!info) {
1470 SDE_ERROR("failed to allocate info memory\n");
Dhaval Patel4e574842016-08-23 15:11:37 -07001471 return;
Clarence Ip13a8cf42016-09-29 17:27:47 -04001472 }
Dhaval Patel4e574842016-08-23 15:11:37 -07001473
1474 msm_property_install_blob(&psde->property_info, "capabilities",
1475 DRM_MODE_PROP_IMMUTABLE, PLANE_PROP_INFO);
1476 sde_kms_info_reset(info);
1477
Clarence Ipea3d6262016-07-15 16:20:11 -04001478 format_list = psde->pipe_sblk->format_list;
1479 if (format_list) {
Clarence Ipea3d6262016-07-15 16:20:11 -04001480 sde_kms_info_start(info, "pixel_formats");
1481 while (format_list->fourcc_format) {
1482 sde_kms_info_append_format(info,
1483 format_list->fourcc_format,
1484 format_list->modifier);
1485 ++format_list;
1486 }
1487 sde_kms_info_stop(info);
Clarence Ipea3d6262016-07-15 16:20:11 -04001488 }
Dhaval Patel4e574842016-08-23 15:11:37 -07001489
1490 sde_kms_info_add_keyint(info, "max_linewidth",
1491 psde->pipe_sblk->maxlinewidth);
1492 sde_kms_info_add_keyint(info, "max_upscale",
1493 psde->pipe_sblk->maxupscale);
1494 sde_kms_info_add_keyint(info, "max_downscale",
1495 psde->pipe_sblk->maxdwnscale);
1496 sde_kms_info_add_keyint(info, "max_horizontal_deci",
1497 psde->pipe_sblk->maxhdeciexp);
1498 sde_kms_info_add_keyint(info, "max_vertical_deci",
1499 psde->pipe_sblk->maxvdeciexp);
1500 msm_property_set_blob(&psde->property_info, &psde->blob_info,
1501 info->data, info->len, PLANE_PROP_INFO);
1502
1503 kfree(info);
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001504}
1505
Clarence Ip5fc00c52016-09-23 15:03:34 -04001506static inline void _sde_plane_set_csc_v1(struct sde_plane *psde, void *usr_ptr)
1507{
1508 struct sde_drm_csc_v1 csc_v1;
1509 int i;
1510
1511 if (!psde) {
1512 SDE_ERROR("invalid plane\n");
1513 return;
1514 }
1515
1516 psde->csc_usr_ptr = NULL;
1517 if (!usr_ptr) {
Clarence Ip13a8cf42016-09-29 17:27:47 -04001518 SDE_DEBUG_PLANE(psde, "csc data removed\n");
Clarence Ip5fc00c52016-09-23 15:03:34 -04001519 return;
1520 }
1521
1522 if (copy_from_user(&csc_v1, usr_ptr, sizeof(csc_v1))) {
Clarence Ip13a8cf42016-09-29 17:27:47 -04001523 SDE_ERROR_PLANE(psde, "failed to copy csc data\n");
Clarence Ip5fc00c52016-09-23 15:03:34 -04001524 return;
1525 }
1526
Clarence Ipb43d4592016-09-08 14:21:35 -04001527 /* populate from user space */
Clarence Ip5fc00c52016-09-23 15:03:34 -04001528 for (i = 0; i < SDE_CSC_MATRIX_COEFF_SIZE; ++i)
1529 psde->csc_cfg.csc_mv[i] = csc_v1.ctm_coeff[i] >> 16;
1530 for (i = 0; i < SDE_CSC_BIAS_SIZE; ++i) {
1531 psde->csc_cfg.csc_pre_bv[i] = csc_v1.pre_bias[i];
1532 psde->csc_cfg.csc_post_bv[i] = csc_v1.post_bias[i];
1533 }
1534 for (i = 0; i < SDE_CSC_CLAMP_SIZE; ++i) {
1535 psde->csc_cfg.csc_pre_lv[i] = csc_v1.pre_clamp[i];
1536 psde->csc_cfg.csc_post_lv[i] = csc_v1.post_clamp[i];
1537 }
1538 psde->csc_usr_ptr = &psde->csc_cfg;
1539}
1540
Clarence Ipb43d4592016-09-08 14:21:35 -04001541static inline void _sde_plane_set_scaler_v1(struct sde_plane *psde, void *usr)
1542{
1543 struct sde_drm_scaler_v1 scale_v1;
1544 struct sde_hw_pixel_ext *pe;
1545 int i;
1546
1547 if (!psde) {
1548 SDE_ERROR("invalid plane\n");
1549 return;
1550 }
1551
1552 psde->pixel_ext_usr = false;
1553 if (!usr) {
Clarence Ip13a8cf42016-09-29 17:27:47 -04001554 SDE_DEBUG_PLANE(psde, "scale data removed\n");
Clarence Ipb43d4592016-09-08 14:21:35 -04001555 return;
1556 }
1557
1558 if (copy_from_user(&scale_v1, usr, sizeof(scale_v1))) {
Clarence Ip13a8cf42016-09-29 17:27:47 -04001559 SDE_ERROR_PLANE(psde, "failed to copy scale data\n");
Clarence Ipb43d4592016-09-08 14:21:35 -04001560 return;
1561 }
1562
1563 /* populate from user space */
1564 pe = &(psde->pixel_ext);
1565 memset(pe, 0, sizeof(struct sde_hw_pixel_ext));
1566 for (i = 0; i < SDE_MAX_PLANES; i++) {
1567 pe->init_phase_x[i] = scale_v1.init_phase_x[i];
1568 pe->phase_step_x[i] = scale_v1.phase_step_x[i];
1569 pe->init_phase_y[i] = scale_v1.init_phase_y[i];
1570 pe->phase_step_y[i] = scale_v1.phase_step_y[i];
1571
1572 pe->horz_filter[i] = scale_v1.horz_filter[i];
1573 pe->vert_filter[i] = scale_v1.vert_filter[i];
1574 }
1575 for (i = 0; i < SDE_MAX_PLANES; i++) {
1576 pe->num_ext_pxls_left[i] = scale_v1.lr.num_pxls_start[i];
1577 pe->num_ext_pxls_right[i] = scale_v1.lr.num_pxls_end[i];
1578 pe->left_ftch[i] = scale_v1.lr.ftch_start[i];
1579 pe->right_ftch[i] = scale_v1.lr.ftch_end[i];
1580 pe->left_rpt[i] = scale_v1.lr.rpt_start[i];
1581 pe->right_rpt[i] = scale_v1.lr.rpt_end[i];
1582 pe->roi_w[i] = scale_v1.lr.roi[i];
1583
1584 pe->num_ext_pxls_top[i] = scale_v1.tb.num_pxls_start[i];
1585 pe->num_ext_pxls_btm[i] = scale_v1.tb.num_pxls_end[i];
1586 pe->top_ftch[i] = scale_v1.tb.ftch_start[i];
1587 pe->btm_ftch[i] = scale_v1.tb.ftch_end[i];
1588 pe->top_rpt[i] = scale_v1.tb.rpt_start[i];
1589 pe->btm_rpt[i] = scale_v1.tb.rpt_end[i];
1590 pe->roi_h[i] = scale_v1.tb.roi[i];
1591 }
1592 psde->pixel_ext_usr = true;
1593
Clarence Ip13a8cf42016-09-29 17:27:47 -04001594 SDE_DEBUG_PLANE(psde, "user property data copied\n");
Clarence Ipb43d4592016-09-08 14:21:35 -04001595}
1596
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001597static int sde_plane_atomic_set_property(struct drm_plane *plane,
1598 struct drm_plane_state *state, struct drm_property *property,
1599 uint64_t val)
1600{
Clarence Ip13a8cf42016-09-29 17:27:47 -04001601 struct sde_plane *psde = plane ? to_sde_plane(plane) : NULL;
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001602 struct sde_plane_state *pstate;
Clarence Ipe78efb72016-06-24 18:35:21 -04001603 int idx, ret = -EINVAL;
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001604
Clarence Ip13a8cf42016-09-29 17:27:47 -04001605 SDE_DEBUG_PLANE(psde, "\n");
Clarence Ipaa0faf42016-05-30 12:07:48 -04001606
1607 if (!plane) {
Dhaval Patel47302cf2016-08-18 15:04:28 -07001608 SDE_ERROR("invalid plane\n");
Clarence Ipaa0faf42016-05-30 12:07:48 -04001609 } else if (!state) {
Clarence Ip13a8cf42016-09-29 17:27:47 -04001610 SDE_ERROR_PLANE(psde, "invalid state\n");
Clarence Ip730e7192016-06-26 22:45:09 -04001611 } else {
Clarence Ip4c1d9772016-06-26 09:35:38 -04001612 pstate = to_sde_plane_state(state);
Clarence Ipaa0faf42016-05-30 12:07:48 -04001613 ret = msm_property_atomic_set(&psde->property_info,
1614 pstate->property_values, pstate->property_blobs,
1615 property, val);
1616 if (!ret) {
1617 idx = msm_property_index(&psde->property_info,
1618 property);
Clarence Ip5fc00c52016-09-23 15:03:34 -04001619 switch (idx) {
1620 case PLANE_PROP_INPUT_FENCE:
Clarence Ip13a8cf42016-09-29 17:27:47 -04001621 _sde_plane_set_input_fence(psde, pstate, val);
Clarence Ip5fc00c52016-09-23 15:03:34 -04001622 break;
1623 case PLANE_PROP_CSC_V1:
1624 _sde_plane_set_csc_v1(psde, (void *)val);
1625 break;
Clarence Ipb43d4592016-09-08 14:21:35 -04001626 case PLANE_PROP_SCALER_V1:
1627 _sde_plane_set_scaler_v1(psde, (void *)val);
1628 break;
Clarence Ip5fc00c52016-09-23 15:03:34 -04001629 default:
1630 /* nothing to do */
1631 break;
1632 }
Clarence Ipe78efb72016-06-24 18:35:21 -04001633 }
1634 }
1635
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001636 return ret;
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001637}
1638
1639static int sde_plane_set_property(struct drm_plane *plane,
1640 struct drm_property *property, uint64_t val)
1641{
Clarence Ip13a8cf42016-09-29 17:27:47 -04001642 SDE_DEBUG("\n");
Clarence Ip4c1d9772016-06-26 09:35:38 -04001643
Clarence Ipae4e60c2016-06-26 22:44:04 -04001644 return sde_plane_atomic_set_property(plane,
1645 plane->state, property, val);
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001646}
1647
1648static int sde_plane_atomic_get_property(struct drm_plane *plane,
1649 const struct drm_plane_state *state,
1650 struct drm_property *property, uint64_t *val)
1651{
Clarence Ip13a8cf42016-09-29 17:27:47 -04001652 struct sde_plane *psde = plane ? to_sde_plane(plane) : NULL;
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001653 struct sde_plane_state *pstate;
Clarence Ipaa0faf42016-05-30 12:07:48 -04001654 int ret = -EINVAL;
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001655
Clarence Ipaa0faf42016-05-30 12:07:48 -04001656 if (!plane) {
Dhaval Patel47302cf2016-08-18 15:04:28 -07001657 SDE_ERROR("invalid plane\n");
Clarence Ipaa0faf42016-05-30 12:07:48 -04001658 } else if (!state) {
Dhaval Patel47302cf2016-08-18 15:04:28 -07001659 SDE_ERROR("invalid state\n");
Clarence Ipaa0faf42016-05-30 12:07:48 -04001660 } else {
Clarence Ip13a8cf42016-09-29 17:27:47 -04001661 SDE_DEBUG_PLANE(psde, "\n");
Clarence Ip4c1d9772016-06-26 09:35:38 -04001662 pstate = to_sde_plane_state(state);
Clarence Ipaa0faf42016-05-30 12:07:48 -04001663 ret = msm_property_atomic_get(&psde->property_info,
1664 pstate->property_values, pstate->property_blobs,
1665 property, val);
Clarence Ipe78efb72016-06-24 18:35:21 -04001666 }
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001667
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001668 return ret;
Narendra Muppalla1b0b3352015-09-29 10:16:51 -07001669}
1670
1671static void sde_plane_destroy(struct drm_plane *plane)
1672{
Clarence Ip13a8cf42016-09-29 17:27:47 -04001673 struct sde_plane *psde = plane ? to_sde_plane(plane) : NULL;
Narendra Muppalla1b0b3352015-09-29 10:16:51 -07001674
Clarence Ip13a8cf42016-09-29 17:27:47 -04001675 SDE_DEBUG_PLANE(psde, "\n");
Narendra Muppalla1b0b3352015-09-29 10:16:51 -07001676
Clarence Ip13a8cf42016-09-29 17:27:47 -04001677 if (psde) {
Alan Kwong1a00e4d2016-07-18 09:42:30 -04001678 _sde_plane_set_qos_ctrl(plane, false, SDE_PLANE_QOS_PANIC_CTRL);
1679
Clarence Ip4ce59322016-06-26 22:27:51 -04001680 debugfs_remove_recursive(psde->debugfs_root);
Clarence Ipe78efb72016-06-24 18:35:21 -04001681
Dhaval Patel4e574842016-08-23 15:11:37 -07001682 if (psde->blob_info)
1683 drm_property_unreference_blob(psde->blob_info);
Clarence Ipaa0faf42016-05-30 12:07:48 -04001684 msm_property_destroy(&psde->property_info);
Clarence Ip730e7192016-06-26 22:45:09 -04001685 mutex_destroy(&psde->lock);
1686
Clarence Ip4ce59322016-06-26 22:27:51 -04001687 drm_plane_helper_disable(plane);
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001688
Clarence Ip4ce59322016-06-26 22:27:51 -04001689 /* this will destroy the states as well */
1690 drm_plane_cleanup(plane);
1691
Clarence Ip4c1d9772016-06-26 09:35:38 -04001692 if (psde->pipe_hw)
1693 sde_hw_sspp_destroy(psde->pipe_hw);
1694
Clarence Ip4ce59322016-06-26 22:27:51 -04001695 kfree(psde);
1696 }
Narendra Muppalla1b0b3352015-09-29 10:16:51 -07001697}
1698
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001699static void sde_plane_destroy_state(struct drm_plane *plane,
1700 struct drm_plane_state *state)
Narendra Muppalla1b0b3352015-09-29 10:16:51 -07001701{
Clarence Ipaa0faf42016-05-30 12:07:48 -04001702 struct sde_plane *psde;
Clarence Ipe78efb72016-06-24 18:35:21 -04001703 struct sde_plane_state *pstate;
Clarence Ipe78efb72016-06-24 18:35:21 -04001704
Clarence Ipae4e60c2016-06-26 22:44:04 -04001705 if (!plane || !state) {
Clarence Ip13a8cf42016-09-29 17:27:47 -04001706 SDE_ERROR("invalid arg(s), plane %d state %d\n",
1707 plane != 0, state != 0);
Clarence Ipae4e60c2016-06-26 22:44:04 -04001708 return;
1709 }
1710
Clarence Ipaa0faf42016-05-30 12:07:48 -04001711 psde = to_sde_plane(plane);
Clarence Ip730e7192016-06-26 22:45:09 -04001712 pstate = to_sde_plane_state(state);
1713
Clarence Ip13a8cf42016-09-29 17:27:47 -04001714 SDE_DEBUG_PLANE(psde, "\n");
Clarence Ip730e7192016-06-26 22:45:09 -04001715
Clarence Ipe78efb72016-06-24 18:35:21 -04001716 /* remove ref count for frame buffers */
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001717 if (state->fb)
1718 drm_framebuffer_unreference(state->fb);
1719
Clarence Ipae4e60c2016-06-26 22:44:04 -04001720 /* remove ref count for fence */
Clarence Ipcae1bb62016-07-07 12:07:13 -04001721 if (pstate->input_fence)
1722 sde_sync_put(pstate->input_fence);
Clarence Ipae4e60c2016-06-26 22:44:04 -04001723
Clarence Ipaa0faf42016-05-30 12:07:48 -04001724 /* destroy value helper */
1725 msm_property_destroy_state(&psde->property_info, pstate,
1726 pstate->property_values, pstate->property_blobs);
Narendra Muppalla1b0b3352015-09-29 10:16:51 -07001727}
1728
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001729static struct drm_plane_state *
1730sde_plane_duplicate_state(struct drm_plane *plane)
Narendra Muppalla1b0b3352015-09-29 10:16:51 -07001731{
Clarence Ipaa0faf42016-05-30 12:07:48 -04001732 struct sde_plane *psde;
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001733 struct sde_plane_state *pstate;
Clarence Ip730e7192016-06-26 22:45:09 -04001734 struct sde_plane_state *old_state;
Clarence Ip17e908b2016-09-29 15:58:00 -04001735 uint64_t input_fence_default;
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001736
Clarence Ip13a8cf42016-09-29 17:27:47 -04001737 if (!plane) {
1738 SDE_ERROR("invalid plane\n");
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001739 return NULL;
Clarence Ip13a8cf42016-09-29 17:27:47 -04001740 } else if (!plane->state) {
1741 SDE_ERROR("invalid plane state\n");
1742 return NULL;
1743 }
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001744
Clarence Ip730e7192016-06-26 22:45:09 -04001745 old_state = to_sde_plane_state(plane->state);
Clarence Ipaa0faf42016-05-30 12:07:48 -04001746 psde = to_sde_plane(plane);
1747 pstate = msm_property_alloc_state(&psde->property_info);
Clarence Ip13a8cf42016-09-29 17:27:47 -04001748 if (!pstate) {
1749 SDE_ERROR_PLANE(psde, "failed to allocate state\n");
Clarence Ip730e7192016-06-26 22:45:09 -04001750 return NULL;
Clarence Ip13a8cf42016-09-29 17:27:47 -04001751 }
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001752
Clarence Ip13a8cf42016-09-29 17:27:47 -04001753 SDE_DEBUG_PLANE(psde, "\n");
Clarence Ipaa0faf42016-05-30 12:07:48 -04001754
1755 /* duplicate value helper */
1756 msm_property_duplicate_state(&psde->property_info, old_state, pstate,
1757 pstate->property_values, pstate->property_blobs);
Clarence Ipae4e60c2016-06-26 22:44:04 -04001758
Clarence Ip730e7192016-06-26 22:45:09 -04001759 /* add ref count for frame buffer */
1760 if (pstate->base.fb)
1761 drm_framebuffer_reference(pstate->base.fb);
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001762
Clarence Ip17e908b2016-09-29 15:58:00 -04001763 /* clear out any input fence */
1764 pstate->input_fence = 0;
1765 input_fence_default = msm_property_get_default(
1766 &psde->property_info, PLANE_PROP_INPUT_FENCE);
1767 msm_property_set_property(&psde->property_info, pstate->property_values,
1768 PLANE_PROP_INPUT_FENCE, input_fence_default);
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001769
Clarence Ip282dad62016-09-27 17:07:35 -04001770 pstate->dirty = 0x0;
Clarence Ip730e7192016-06-26 22:45:09 -04001771 pstate->pending = false;
1772
1773 return &pstate->base;
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001774}
1775
1776static void sde_plane_reset(struct drm_plane *plane)
1777{
Clarence Ipae4e60c2016-06-26 22:44:04 -04001778 struct sde_plane *psde;
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001779 struct sde_plane_state *pstate;
1780
Clarence Ipae4e60c2016-06-26 22:44:04 -04001781 if (!plane) {
Dhaval Patel47302cf2016-08-18 15:04:28 -07001782 SDE_ERROR("invalid plane\n");
Clarence Ipae4e60c2016-06-26 22:44:04 -04001783 return;
1784 }
1785
Clarence Ip730e7192016-06-26 22:45:09 -04001786 psde = to_sde_plane(plane);
Clarence Ip13a8cf42016-09-29 17:27:47 -04001787 SDE_DEBUG_PLANE(psde, "\n");
Clarence Ip730e7192016-06-26 22:45:09 -04001788
Clarence Ipae4e60c2016-06-26 22:44:04 -04001789 /* remove previous state, if present */
Clarence Ipaa0faf42016-05-30 12:07:48 -04001790 if (plane->state) {
Clarence Ipae4e60c2016-06-26 22:44:04 -04001791 sde_plane_destroy_state(plane, plane->state);
Clarence Ipaa0faf42016-05-30 12:07:48 -04001792 plane->state = 0;
Clarence Ipae4e60c2016-06-26 22:44:04 -04001793 }
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001794
Clarence Ipaa0faf42016-05-30 12:07:48 -04001795 pstate = msm_property_alloc_state(&psde->property_info);
Clarence Ip13a8cf42016-09-29 17:27:47 -04001796 if (!pstate) {
1797 SDE_ERROR_PLANE(psde, "failed to allocate state\n");
Clarence Ipaa0faf42016-05-30 12:07:48 -04001798 return;
Clarence Ip13a8cf42016-09-29 17:27:47 -04001799 }
Clarence Ip730e7192016-06-26 22:45:09 -04001800
Clarence Ipaa0faf42016-05-30 12:07:48 -04001801 /* reset value helper */
1802 msm_property_reset_state(&psde->property_info, pstate,
1803 pstate->property_values, pstate->property_blobs);
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001804
1805 pstate->base.plane = plane;
1806
1807 plane->state = &pstate->base;
Narendra Muppalla1b0b3352015-09-29 10:16:51 -07001808}
1809
1810static const struct drm_plane_funcs sde_plane_funcs = {
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001811 .update_plane = drm_atomic_helper_update_plane,
1812 .disable_plane = drm_atomic_helper_disable_plane,
Narendra Muppalla1b0b3352015-09-29 10:16:51 -07001813 .destroy = sde_plane_destroy,
1814 .set_property = sde_plane_set_property,
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001815 .atomic_set_property = sde_plane_atomic_set_property,
1816 .atomic_get_property = sde_plane_atomic_get_property,
1817 .reset = sde_plane_reset,
1818 .atomic_duplicate_state = sde_plane_duplicate_state,
1819 .atomic_destroy_state = sde_plane_destroy_state,
Narendra Muppalla1b0b3352015-09-29 10:16:51 -07001820};
1821
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001822static const struct drm_plane_helper_funcs sde_plane_helper_funcs = {
1823 .prepare_fb = sde_plane_prepare_fb,
1824 .cleanup_fb = sde_plane_cleanup_fb,
1825 .atomic_check = sde_plane_atomic_check,
1826 .atomic_update = sde_plane_atomic_update,
1827};
Narendra Muppalla1b0b3352015-09-29 10:16:51 -07001828
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001829enum sde_sspp sde_plane_pipe(struct drm_plane *plane)
Narendra Muppalla1b0b3352015-09-29 10:16:51 -07001830{
Clarence Ip13a8cf42016-09-29 17:27:47 -04001831 return plane ? to_sde_plane(plane)->pipe : SSPP_NONE;
Narendra Muppalla1b0b3352015-09-29 10:16:51 -07001832}
1833
Clarence Ip4ce59322016-06-26 22:27:51 -04001834static void _sde_plane_init_debugfs(struct sde_plane *psde, struct sde_kms *kms)
1835{
1836 const struct sde_sspp_sub_blks *sblk = 0;
1837 const struct sde_sspp_cfg *cfg = 0;
1838
1839 if (psde && psde->pipe_hw)
1840 cfg = psde->pipe_hw->cap;
1841 if (cfg)
1842 sblk = cfg->sblk;
1843
1844 if (kms && sblk) {
1845 /* create overall sub-directory for the pipe */
1846 psde->debugfs_root =
1847 debugfs_create_dir(psde->pipe_name,
1848 sde_debugfs_get_root(kms));
1849 if (psde->debugfs_root) {
1850 /* don't error check these */
Clarence Ip4c1d9772016-06-26 09:35:38 -04001851 debugfs_create_x32("features", 0644,
Clarence Ip4ce59322016-06-26 22:27:51 -04001852 psde->debugfs_root, &psde->features);
1853
1854 /* add register dump support */
1855 sde_debugfs_setup_regset32(&psde->debugfs_src,
1856 sblk->src_blk.base + cfg->base,
1857 sblk->src_blk.len,
Clarence Ipaac9f332016-08-31 15:46:35 -04001858 kms);
Clarence Ip4ce59322016-06-26 22:27:51 -04001859 sde_debugfs_create_regset32("src_blk", 0444,
1860 psde->debugfs_root, &psde->debugfs_src);
1861
1862 sde_debugfs_setup_regset32(&psde->debugfs_scaler,
1863 sblk->scaler_blk.base + cfg->base,
1864 sblk->scaler_blk.len,
Clarence Ipaac9f332016-08-31 15:46:35 -04001865 kms);
Clarence Ip4ce59322016-06-26 22:27:51 -04001866 sde_debugfs_create_regset32("scaler_blk", 0444,
1867 psde->debugfs_root,
1868 &psde->debugfs_scaler);
1869
1870 sde_debugfs_setup_regset32(&psde->debugfs_csc,
1871 sblk->csc_blk.base + cfg->base,
1872 sblk->csc_blk.len,
Clarence Ipaac9f332016-08-31 15:46:35 -04001873 kms);
Clarence Ip4ce59322016-06-26 22:27:51 -04001874 sde_debugfs_create_regset32("csc_blk", 0444,
1875 psde->debugfs_root, &psde->debugfs_csc);
1876 }
1877 }
1878}
1879
Narendra Muppalla1b0b3352015-09-29 10:16:51 -07001880/* initialize plane */
Clarence Ipe78efb72016-06-24 18:35:21 -04001881struct drm_plane *sde_plane_init(struct drm_device *dev,
Clarence Ip4c1d9772016-06-26 09:35:38 -04001882 uint32_t pipe, bool primary_plane)
Narendra Muppalla1b0b3352015-09-29 10:16:51 -07001883{
1884 struct drm_plane *plane = NULL;
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001885 struct sde_plane *psde;
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001886 struct msm_drm_private *priv;
1887 struct sde_kms *kms;
Narendra Muppalla1b0b3352015-09-29 10:16:51 -07001888 enum drm_plane_type type;
Dhaval Patel47302cf2016-08-18 15:04:28 -07001889 int ret = -EINVAL, max_blendstages = 255;
Clarence Ip4c1d9772016-06-26 09:35:38 -04001890
1891 if (!dev) {
Dhaval Patel47302cf2016-08-18 15:04:28 -07001892 SDE_ERROR("[%u]device is NULL\n", pipe);
Clarence Ip4c1d9772016-06-26 09:35:38 -04001893 goto exit;
1894 }
Narendra Muppalla1b0b3352015-09-29 10:16:51 -07001895
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001896 priv = dev->dev_private;
Ben Chan78647cd2016-06-26 22:02:47 -04001897 if (!priv) {
Dhaval Patel47302cf2016-08-18 15:04:28 -07001898 SDE_ERROR("[%u]private data is NULL\n", pipe);
Ben Chan78647cd2016-06-26 22:02:47 -04001899 goto exit;
1900 }
1901
1902 if (!priv->kms) {
Dhaval Patel47302cf2016-08-18 15:04:28 -07001903 SDE_ERROR("[%u]invalid KMS reference\n", pipe);
Ben Chan78647cd2016-06-26 22:02:47 -04001904 goto exit;
1905 }
1906 kms = to_sde_kms(priv->kms);
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001907
Clarence Ip4c1d9772016-06-26 09:35:38 -04001908 if (!kms->catalog) {
Dhaval Patel47302cf2016-08-18 15:04:28 -07001909 SDE_ERROR("[%u]invalid catalog reference\n", pipe);
Clarence Ip4c1d9772016-06-26 09:35:38 -04001910 goto exit;
1911 }
1912
Clarence Ip4ce59322016-06-26 22:27:51 -04001913 /* create and zero local structure */
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001914 psde = kzalloc(sizeof(*psde), GFP_KERNEL);
1915 if (!psde) {
Dhaval Patel47302cf2016-08-18 15:04:28 -07001916 SDE_ERROR("[%u]failed to allocate local plane struct\n", pipe);
Narendra Muppalla1b0b3352015-09-29 10:16:51 -07001917 ret = -ENOMEM;
Clarence Ip4c1d9772016-06-26 09:35:38 -04001918 goto exit;
Narendra Muppalla1b0b3352015-09-29 10:16:51 -07001919 }
1920
Clarence Ip4c1d9772016-06-26 09:35:38 -04001921 /* cache local stuff for later */
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001922 plane = &psde->base;
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001923 psde->pipe = pipe;
Alan Kwong112a84f2016-05-24 20:49:21 -04001924 psde->mmu_id = kms->mmu_id[MSM_SMMU_DOMAIN_UNSECURE];
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001925
Clarence Ip4c1d9772016-06-26 09:35:38 -04001926 /* initialize underlying h/w driver */
1927 psde->pipe_hw = sde_hw_sspp_init(pipe, kms->mmio, kms->catalog);
1928 if (IS_ERR(psde->pipe_hw)) {
Dhaval Patel47302cf2016-08-18 15:04:28 -07001929 SDE_ERROR("[%u]SSPP init failed\n", pipe);
Clarence Ip4c1d9772016-06-26 09:35:38 -04001930 ret = PTR_ERR(psde->pipe_hw);
1931 goto clean_plane;
1932 } else if (!psde->pipe_hw->cap || !psde->pipe_hw->cap->sblk) {
Dhaval Patel47302cf2016-08-18 15:04:28 -07001933 SDE_ERROR("[%u]SSPP init returned invalid cfg\n", pipe);
Clarence Ip4c1d9772016-06-26 09:35:38 -04001934 goto clean_sspp;
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001935 }
Clarence Ip4c1d9772016-06-26 09:35:38 -04001936
1937 /* cache features mask for later */
1938 psde->features = psde->pipe_hw->cap->features;
1939 psde->pipe_sblk = psde->pipe_hw->cap->sblk;
Clarence Ipea3d6262016-07-15 16:20:11 -04001940 if (!psde->pipe_sblk) {
Clarence Ip13a8cf42016-09-29 17:27:47 -04001941 SDE_ERROR("[%u]invalid sblk\n", pipe);
Clarence Ipea3d6262016-07-15 16:20:11 -04001942 goto clean_sspp;
1943 }
Clarence Ip4c1d9772016-06-26 09:35:38 -04001944
Dhaval Patel47302cf2016-08-18 15:04:28 -07001945 if (kms->catalog && kms->catalog->mixer_count && kms->catalog->mixer)
1946 max_blendstages = kms->catalog->mixer[0].sblk->maxblendstages;
1947
Clarence Ip4c1d9772016-06-26 09:35:38 -04001948 /* add plane to DRM framework */
Clarence Ipea3d6262016-07-15 16:20:11 -04001949 psde->nformats = sde_populate_formats(psde->pipe_sblk->format_list,
1950 psde->formats,
1951 0,
1952 ARRAY_SIZE(psde->formats));
Narendra Muppalla1b0b3352015-09-29 10:16:51 -07001953
Clarence Ip4c1d9772016-06-26 09:35:38 -04001954 if (!psde->nformats) {
Dhaval Patel47302cf2016-08-18 15:04:28 -07001955 SDE_ERROR("[%u]no valid formats for plane\n", pipe);
Clarence Ip4c1d9772016-06-26 09:35:38 -04001956 goto clean_sspp;
1957 }
1958
1959 if (psde->features & BIT(SDE_SSPP_CURSOR))
1960 type = DRM_PLANE_TYPE_CURSOR;
1961 else if (primary_plane)
1962 type = DRM_PLANE_TYPE_PRIMARY;
1963 else
1964 type = DRM_PLANE_TYPE_OVERLAY;
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001965 ret = drm_universal_plane_init(dev, plane, 0xff, &sde_plane_funcs,
1966 psde->formats, psde->nformats,
1967 type);
1968 if (ret)
Clarence Ip4c1d9772016-06-26 09:35:38 -04001969 goto clean_sspp;
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001970
Clarence Ip4c1d9772016-06-26 09:35:38 -04001971 /* success! finalize initialization */
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001972 drm_plane_helper_add(plane, &sde_plane_helper_funcs);
Narendra Muppalla1b0b3352015-09-29 10:16:51 -07001973
Clarence Ipaa0faf42016-05-30 12:07:48 -04001974 msm_property_init(&psde->property_info, &plane->base, dev,
1975 priv->plane_property, psde->property_data,
1976 PLANE_PROP_COUNT, PLANE_PROP_BLOBCOUNT,
1977 sizeof(struct sde_plane_state));
1978
Dhaval Patel47302cf2016-08-18 15:04:28 -07001979 _sde_plane_install_properties(plane, max_blendstages);
Clarence Ip5e2a9222016-06-26 22:38:24 -04001980
Clarence Ip4ce59322016-06-26 22:27:51 -04001981 /* save user friendly pipe name for later */
Clarence Ip5e2a9222016-06-26 22:38:24 -04001982 snprintf(psde->pipe_name, SDE_NAME_SIZE, "plane%u", plane->base.id);
Clarence Ip4ce59322016-06-26 22:27:51 -04001983
Clarence Ip730e7192016-06-26 22:45:09 -04001984 mutex_init(&psde->lock);
1985
Clarence Ip4ce59322016-06-26 22:27:51 -04001986 _sde_plane_init_debugfs(psde, kms);
1987
Clarence Ip13a8cf42016-09-29 17:27:47 -04001988 DRM_INFO("%s created for pipe %u\n", psde->pipe_name, pipe);
Narendra Muppalla1b0b3352015-09-29 10:16:51 -07001989 return plane;
1990
Clarence Ip4c1d9772016-06-26 09:35:38 -04001991clean_sspp:
1992 if (psde && psde->pipe_hw)
1993 sde_hw_sspp_destroy(psde->pipe_hw);
1994clean_plane:
1995 kfree(psde);
Ben Chan78647cd2016-06-26 22:02:47 -04001996exit:
Narendra Muppalla1b0b3352015-09-29 10:16:51 -07001997 return ERR_PTR(ret);
1998}