blob: 6570e5753e494eb8e35bb0cd24733806771ae937 [file] [log] [blame]
Jeeja KPa40e6932015-07-09 15:20:08 +05301/*
2 * skl-pcm.c -ASoC HDA Platform driver file implementing PCM functionality
3 *
4 * Copyright (C) 2014-2015 Intel Corp
5 * Author: Jeeja KP <jeeja.kp@intel.com>
6 *
7 * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; version 2 of the License.
12 *
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
16 * General Public License for more details.
17 *
18 * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
19 *
20 */
21
22#include <linux/pci.h>
23#include <linux/pm_runtime.h>
24#include <sound/pcm_params.h>
25#include <sound/soc.h>
26#include "skl.h"
Jeeja KPb663a8c2015-10-07 11:31:57 +010027#include "skl-topology.h"
Jeeja KPa40e6932015-07-09 15:20:08 +053028
29#define HDA_MONO 1
30#define HDA_STEREO 2
Jeeja KP8f35bf32015-11-28 15:01:46 +053031#define HDA_QUAD 4
Jeeja KPa40e6932015-07-09 15:20:08 +053032
33static struct snd_pcm_hardware azx_pcm_hw = {
34 .info = (SNDRV_PCM_INFO_MMAP |
35 SNDRV_PCM_INFO_INTERLEAVED |
36 SNDRV_PCM_INFO_BLOCK_TRANSFER |
37 SNDRV_PCM_INFO_MMAP_VALID |
38 SNDRV_PCM_INFO_PAUSE |
39 SNDRV_PCM_INFO_SYNC_START |
40 SNDRV_PCM_INFO_HAS_WALL_CLOCK | /* legacy */
41 SNDRV_PCM_INFO_HAS_LINK_ATIME |
42 SNDRV_PCM_INFO_NO_PERIOD_WAKEUP),
Jeeja KP06b23d92015-11-23 22:26:26 +053043 .formats = SNDRV_PCM_FMTBIT_S16_LE |
44 SNDRV_PCM_FMTBIT_S32_LE |
45 SNDRV_PCM_FMTBIT_S24_LE,
46 .rates = SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_16000 |
47 SNDRV_PCM_RATE_8000,
48 .rate_min = 8000,
Jeeja KPa40e6932015-07-09 15:20:08 +053049 .rate_max = 48000,
Jeeja KP8f35bf32015-11-28 15:01:46 +053050 .channels_min = 1,
51 .channels_max = HDA_QUAD,
Jeeja KPa40e6932015-07-09 15:20:08 +053052 .buffer_bytes_max = AZX_MAX_BUF_SIZE,
53 .period_bytes_min = 128,
54 .period_bytes_max = AZX_MAX_BUF_SIZE / 2,
55 .periods_min = 2,
56 .periods_max = AZX_MAX_FRAG,
57 .fifo_size = 0,
58};
59
60static inline
61struct hdac_ext_stream *get_hdac_ext_stream(struct snd_pcm_substream *substream)
62{
63 return substream->runtime->private_data;
64}
65
66static struct hdac_ext_bus *get_bus_ctx(struct snd_pcm_substream *substream)
67{
68 struct hdac_ext_stream *stream = get_hdac_ext_stream(substream);
69 struct hdac_stream *hstream = hdac_stream(stream);
70 struct hdac_bus *bus = hstream->bus;
71
72 return hbus_to_ebus(bus);
73}
74
75static int skl_substream_alloc_pages(struct hdac_ext_bus *ebus,
76 struct snd_pcm_substream *substream,
77 size_t size)
78{
79 struct hdac_ext_stream *stream = get_hdac_ext_stream(substream);
80
81 hdac_stream(stream)->bufsize = 0;
82 hdac_stream(stream)->period_bytes = 0;
83 hdac_stream(stream)->format_val = 0;
84
85 return snd_pcm_lib_malloc_pages(substream, size);
86}
87
88static int skl_substream_free_pages(struct hdac_bus *bus,
89 struct snd_pcm_substream *substream)
90{
91 return snd_pcm_lib_free_pages(substream);
92}
93
94static void skl_set_pcm_constrains(struct hdac_ext_bus *ebus,
95 struct snd_pcm_runtime *runtime)
96{
97 snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS);
98
99 /* avoid wrap-around with wall-clock */
100 snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_BUFFER_TIME,
101 20, 178000000);
102}
103
Jeeja KP05057002015-07-09 15:20:11 +0530104static enum hdac_ext_stream_type skl_get_host_stream_type(struct hdac_ext_bus *ebus)
105{
106 if (ebus->ppcap)
107 return HDAC_EXT_STREAM_TYPE_HOST;
108 else
109 return HDAC_EXT_STREAM_TYPE_COUPLED;
110}
111
Jeeja KPa40e6932015-07-09 15:20:08 +0530112static int skl_pcm_open(struct snd_pcm_substream *substream,
113 struct snd_soc_dai *dai)
114{
115 struct hdac_ext_bus *ebus = dev_get_drvdata(dai->dev);
116 struct hdac_ext_stream *stream;
117 struct snd_pcm_runtime *runtime = substream->runtime;
118 struct skl_dma_params *dma_params;
Jeeja KPa40e6932015-07-09 15:20:08 +0530119
120 dev_dbg(dai->dev, "%s: %s\n", __func__, dai->name);
Jeeja KPa40e6932015-07-09 15:20:08 +0530121
122 stream = snd_hdac_ext_stream_assign(ebus, substream,
Jeeja KP05057002015-07-09 15:20:11 +0530123 skl_get_host_stream_type(ebus));
Jeeja KPa40e6932015-07-09 15:20:08 +0530124 if (stream == NULL)
125 return -EBUSY;
126
127 skl_set_pcm_constrains(ebus, runtime);
128
129 /*
130 * disable WALLCLOCK timestamps for capture streams
131 * until we figure out how to handle digital inputs
132 */
133 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) {
134 runtime->hw.info &= ~SNDRV_PCM_INFO_HAS_WALL_CLOCK; /* legacy */
135 runtime->hw.info &= ~SNDRV_PCM_INFO_HAS_LINK_ATIME;
136 }
137
138 runtime->private_data = stream;
139
140 dma_params = kzalloc(sizeof(*dma_params), GFP_KERNEL);
141 if (!dma_params)
142 return -ENOMEM;
143
144 dma_params->stream_tag = hdac_stream(stream)->stream_tag;
145 snd_soc_dai_set_dma_data(dai, substream, dma_params);
146
147 dev_dbg(dai->dev, "stream tag set in dma params=%d\n",
148 dma_params->stream_tag);
149 snd_pcm_set_sync(substream);
150
151 return 0;
152}
153
154static int skl_get_format(struct snd_pcm_substream *substream,
155 struct snd_soc_dai *dai)
156{
157 struct snd_soc_pcm_runtime *rtd = snd_pcm_substream_chip(substream);
158 struct skl_dma_params *dma_params;
Jeeja KP05057002015-07-09 15:20:11 +0530159 struct hdac_ext_bus *ebus = dev_get_drvdata(dai->dev);
Jeeja KPa40e6932015-07-09 15:20:08 +0530160 int format_val = 0;
Jeeja KPa40e6932015-07-09 15:20:08 +0530161
Jeeja KP05057002015-07-09 15:20:11 +0530162 if (ebus->ppcap) {
163 struct snd_pcm_runtime *runtime = substream->runtime;
164
165 format_val = snd_hdac_calc_stream_format(runtime->rate,
166 runtime->channels,
167 runtime->format,
168 32, 0);
169 } else {
170 struct snd_soc_dai *codec_dai = rtd->codec_dai;
171
172 dma_params = snd_soc_dai_get_dma_data(codec_dai, substream);
173 if (dma_params)
174 format_val = dma_params->format;
175 }
Jeeja KPa40e6932015-07-09 15:20:08 +0530176
177 return format_val;
178}
179
180static int skl_pcm_prepare(struct snd_pcm_substream *substream,
181 struct snd_soc_dai *dai)
182{
183 struct hdac_ext_stream *stream = get_hdac_ext_stream(substream);
184 unsigned int format_val;
185 int err;
186
187 dev_dbg(dai->dev, "%s: %s\n", __func__, dai->name);
Jeeja KPa40e6932015-07-09 15:20:08 +0530188
189 format_val = skl_get_format(substream, dai);
190 dev_dbg(dai->dev, "stream_tag=%d formatvalue=%d\n",
191 hdac_stream(stream)->stream_tag, format_val);
192 snd_hdac_stream_reset(hdac_stream(stream));
193
194 err = snd_hdac_stream_set_params(hdac_stream(stream), format_val);
195 if (err < 0)
196 return err;
197
198 err = snd_hdac_stream_setup(hdac_stream(stream));
199 if (err < 0)
200 return err;
201
202 hdac_stream(stream)->prepared = 1;
203
204 return err;
205}
206
207static int skl_pcm_hw_params(struct snd_pcm_substream *substream,
208 struct snd_pcm_hw_params *params,
209 struct snd_soc_dai *dai)
210{
211 struct hdac_ext_bus *ebus = dev_get_drvdata(dai->dev);
Jeeja KP05057002015-07-09 15:20:11 +0530212 struct hdac_ext_stream *stream = get_hdac_ext_stream(substream);
Jeeja KPa40e6932015-07-09 15:20:08 +0530213 struct snd_pcm_runtime *runtime = substream->runtime;
Jeeja KPb663a8c2015-10-07 11:31:57 +0100214 struct skl_pipe_params p_params = {0};
215 struct skl_module_cfg *m_cfg;
Jeeja KP05057002015-07-09 15:20:11 +0530216 int ret, dma_id;
Jeeja KPa40e6932015-07-09 15:20:08 +0530217
218 dev_dbg(dai->dev, "%s: %s\n", __func__, dai->name);
219 ret = skl_substream_alloc_pages(ebus, substream,
220 params_buffer_bytes(params));
221 if (ret < 0)
222 return ret;
223
224 dev_dbg(dai->dev, "format_val, rate=%d, ch=%d, format=%d\n",
225 runtime->rate, runtime->channels, runtime->format);
226
Jeeja KP05057002015-07-09 15:20:11 +0530227 dma_id = hdac_stream(stream)->stream_tag - 1;
228 dev_dbg(dai->dev, "dma_id=%d\n", dma_id);
229
Jeeja KPb663a8c2015-10-07 11:31:57 +0100230 p_params.s_fmt = snd_pcm_format_width(params_format(params));
231 p_params.ch = params_channels(params);
232 p_params.s_freq = params_rate(params);
233 p_params.host_dma_id = dma_id;
234 p_params.stream = substream->stream;
235
236 m_cfg = skl_tplg_fe_get_cpr_module(dai, p_params.stream);
237 if (m_cfg)
238 skl_tplg_update_pipe_params(dai->dev, m_cfg, &p_params);
239
Jeeja KPa40e6932015-07-09 15:20:08 +0530240 return 0;
241}
242
243static void skl_pcm_close(struct snd_pcm_substream *substream,
244 struct snd_soc_dai *dai)
245{
246 struct hdac_ext_stream *stream = get_hdac_ext_stream(substream);
Jeeja KP05057002015-07-09 15:20:11 +0530247 struct hdac_ext_bus *ebus = dev_get_drvdata(dai->dev);
Jeeja KPa40e6932015-07-09 15:20:08 +0530248 struct skl_dma_params *dma_params = NULL;
249
250 dev_dbg(dai->dev, "%s: %s\n", __func__, dai->name);
Jeeja KP05057002015-07-09 15:20:11 +0530251
252 snd_hdac_ext_stream_release(stream, skl_get_host_stream_type(ebus));
Jeeja KPa40e6932015-07-09 15:20:08 +0530253
254 dma_params = snd_soc_dai_get_dma_data(dai, substream);
255 /*
256 * now we should set this to NULL as we are freeing by the
257 * dma_params
258 */
259 snd_soc_dai_set_dma_data(dai, substream, NULL);
260
Jeeja KPa40e6932015-07-09 15:20:08 +0530261 kfree(dma_params);
262}
263
264static int skl_pcm_hw_free(struct snd_pcm_substream *substream,
265 struct snd_soc_dai *dai)
266{
267 struct hdac_ext_bus *ebus = dev_get_drvdata(dai->dev);
268 struct hdac_ext_stream *stream = get_hdac_ext_stream(substream);
269
270 dev_dbg(dai->dev, "%s: %s\n", __func__, dai->name);
271
272 snd_hdac_stream_cleanup(hdac_stream(stream));
273 hdac_stream(stream)->prepared = 0;
274
275 return skl_substream_free_pages(ebus_to_hbus(ebus), substream);
276}
277
Jeeja KPb663a8c2015-10-07 11:31:57 +0100278static int skl_be_hw_params(struct snd_pcm_substream *substream,
279 struct snd_pcm_hw_params *params,
280 struct snd_soc_dai *dai)
281{
282 struct skl_pipe_params p_params = {0};
283
284 p_params.s_fmt = snd_pcm_format_width(params_format(params));
285 p_params.ch = params_channels(params);
286 p_params.s_freq = params_rate(params);
287 p_params.stream = substream->stream;
Jeeja KPb663a8c2015-10-07 11:31:57 +0100288
Jeeja KP4bd073f2015-10-27 09:22:45 +0900289 return skl_tplg_be_update_params(dai, &p_params);
Jeeja KPb663a8c2015-10-07 11:31:57 +0100290}
291
Jeeja KPd1730c32015-10-27 09:22:53 +0900292static int skl_decoupled_trigger(struct snd_pcm_substream *substream,
293 int cmd)
294{
295 struct hdac_ext_bus *ebus = get_bus_ctx(substream);
296 struct hdac_bus *bus = ebus_to_hbus(ebus);
297 struct hdac_ext_stream *stream;
298 int start;
299 unsigned long cookie;
300 struct hdac_stream *hstr;
301
302 stream = get_hdac_ext_stream(substream);
303 hstr = hdac_stream(stream);
304
305 if (!hstr->prepared)
306 return -EPIPE;
307
308 switch (cmd) {
309 case SNDRV_PCM_TRIGGER_START:
310 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
311 case SNDRV_PCM_TRIGGER_RESUME:
312 start = 1;
313 break;
314
315 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
316 case SNDRV_PCM_TRIGGER_SUSPEND:
317 case SNDRV_PCM_TRIGGER_STOP:
318 start = 0;
319 break;
320
321 default:
322 return -EINVAL;
323 }
324
325 spin_lock_irqsave(&bus->reg_lock, cookie);
326
327 if (start) {
328 snd_hdac_stream_start(hdac_stream(stream), true);
329 snd_hdac_stream_timecounter_init(hstr, 0);
330 } else {
331 snd_hdac_stream_stop(hdac_stream(stream));
332 }
333
334 spin_unlock_irqrestore(&bus->reg_lock, cookie);
335
336 return 0;
337}
338
Jeeja KPb663a8c2015-10-07 11:31:57 +0100339static int skl_pcm_trigger(struct snd_pcm_substream *substream, int cmd,
340 struct snd_soc_dai *dai)
341{
342 struct skl *skl = get_skl_ctx(dai->dev);
343 struct skl_sst *ctx = skl->skl_sst;
344 struct skl_module_cfg *mconfig;
Jeeja KP7e3a17d2015-11-23 22:26:24 +0530345 struct hdac_ext_bus *ebus = get_bus_ctx(substream);
346 struct hdac_ext_stream *stream = get_hdac_ext_stream(substream);
Jeeja KPd1730c32015-10-27 09:22:53 +0900347 int ret;
Jeeja KPb663a8c2015-10-07 11:31:57 +0100348
349 mconfig = skl_tplg_fe_get_cpr_module(dai, substream->stream);
350 if (!mconfig)
351 return -EIO;
352
353 switch (cmd) {
Jeeja KP7e3a17d2015-11-23 22:26:24 +0530354 case SNDRV_PCM_TRIGGER_RESUME:
355 skl_pcm_prepare(substream, dai);
Jeeja KPd1730c32015-10-27 09:22:53 +0900356 case SNDRV_PCM_TRIGGER_START:
Jeeja KPb663a8c2015-10-07 11:31:57 +0100357 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
Jeeja KPd1730c32015-10-27 09:22:53 +0900358 /*
359 * Start HOST DMA and Start FE Pipe.This is to make sure that
360 * there are no underrun/overrun in the case when the FE
361 * pipeline is started but there is a delay in starting the
362 * DMA channel on the host.
363 */
Jeeja KP7e3a17d2015-11-23 22:26:24 +0530364 snd_hdac_ext_stream_decouple(ebus, stream, true);
Jeeja KPd1730c32015-10-27 09:22:53 +0900365 ret = skl_decoupled_trigger(substream, cmd);
366 if (ret < 0)
367 return ret;
Jeeja KPb663a8c2015-10-07 11:31:57 +0100368 return skl_run_pipe(ctx, mconfig->pipe);
Jeeja KPd1730c32015-10-27 09:22:53 +0900369 break;
Jeeja KPb663a8c2015-10-07 11:31:57 +0100370
371 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
372 case SNDRV_PCM_TRIGGER_SUSPEND:
Jeeja KPd1730c32015-10-27 09:22:53 +0900373 case SNDRV_PCM_TRIGGER_STOP:
374 /*
375 * Stop FE Pipe first and stop DMA. This is to make sure that
376 * there are no underrun/overrun in the case if there is a delay
377 * between the two operations.
378 */
379 ret = skl_stop_pipe(ctx, mconfig->pipe);
380 if (ret < 0)
381 return ret;
382
383 ret = skl_decoupled_trigger(substream, cmd);
Jeeja KP7e3a17d2015-11-23 22:26:24 +0530384 if (cmd == SNDRV_PCM_TRIGGER_SUSPEND)
385 snd_hdac_ext_stream_decouple(ebus, stream, false);
Jeeja KPd1730c32015-10-27 09:22:53 +0900386 break;
Jeeja KPb663a8c2015-10-07 11:31:57 +0100387
388 default:
Jeeja KPd1730c32015-10-27 09:22:53 +0900389 return -EINVAL;
Jeeja KPb663a8c2015-10-07 11:31:57 +0100390 }
Jeeja KPd1730c32015-10-27 09:22:53 +0900391
392 return 0;
Jeeja KPb663a8c2015-10-07 11:31:57 +0100393}
394
Jeeja KP05057002015-07-09 15:20:11 +0530395static int skl_link_hw_params(struct snd_pcm_substream *substream,
396 struct snd_pcm_hw_params *params,
397 struct snd_soc_dai *dai)
398{
399 struct hdac_ext_bus *ebus = dev_get_drvdata(dai->dev);
400 struct hdac_ext_stream *link_dev;
401 struct snd_soc_pcm_runtime *rtd = snd_pcm_substream_chip(substream);
402 struct skl_dma_params *dma_params;
403 struct snd_soc_dai *codec_dai = rtd->codec_dai;
Jeeja KPb663a8c2015-10-07 11:31:57 +0100404 struct skl_pipe_params p_params = {0};
Jeeja KP05057002015-07-09 15:20:11 +0530405
Jeeja KP05057002015-07-09 15:20:11 +0530406 link_dev = snd_hdac_ext_stream_assign(ebus, substream,
407 HDAC_EXT_STREAM_TYPE_LINK);
408 if (!link_dev)
409 return -EBUSY;
410
411 snd_soc_dai_set_dma_data(dai, substream, (void *)link_dev);
412
413 /* set the stream tag in the codec dai dma params */
414 dma_params = (struct skl_dma_params *)
415 snd_soc_dai_get_dma_data(codec_dai, substream);
416 if (dma_params)
417 dma_params->stream_tag = hdac_stream(link_dev)->stream_tag;
418 snd_soc_dai_set_dma_data(codec_dai, substream, (void *)dma_params);
Jeeja KPb663a8c2015-10-07 11:31:57 +0100419
420 p_params.s_fmt = snd_pcm_format_width(params_format(params));
421 p_params.ch = params_channels(params);
422 p_params.s_freq = params_rate(params);
423 p_params.stream = substream->stream;
424 p_params.link_dma_id = hdac_stream(link_dev)->stream_tag - 1;
425
Jeeja KP4bd073f2015-10-27 09:22:45 +0900426 return skl_tplg_be_update_params(dai, &p_params);
Jeeja KP05057002015-07-09 15:20:11 +0530427}
428
429static int skl_link_pcm_prepare(struct snd_pcm_substream *substream,
430 struct snd_soc_dai *dai)
431{
432 struct snd_soc_pcm_runtime *rtd = snd_pcm_substream_chip(substream);
433 struct hdac_ext_bus *ebus = dev_get_drvdata(dai->dev);
434 struct hdac_ext_stream *link_dev =
435 snd_soc_dai_get_dma_data(dai, substream);
436 unsigned int format_val = 0;
437 struct skl_dma_params *dma_params;
438 struct snd_soc_dai *codec_dai = rtd->codec_dai;
Jeeja KP05057002015-07-09 15:20:11 +0530439 struct hdac_ext_link *link;
440
Jeeja KP05057002015-07-09 15:20:11 +0530441 if (link_dev->link_prepared) {
442 dev_dbg(dai->dev, "already stream is prepared - returning\n");
443 return 0;
444 }
Jeeja KP05057002015-07-09 15:20:11 +0530445
446 dma_params = (struct skl_dma_params *)
447 snd_soc_dai_get_dma_data(codec_dai, substream);
448 if (dma_params)
449 format_val = dma_params->format;
450 dev_dbg(dai->dev, "stream_tag=%d formatvalue=%d codec_dai_name=%s\n",
451 hdac_stream(link_dev)->stream_tag, format_val, codec_dai->name);
452
453 snd_hdac_ext_link_stream_reset(link_dev);
454
455 snd_hdac_ext_link_stream_setup(link_dev, format_val);
456
457 link = snd_hdac_ext_bus_get_link(ebus, rtd->codec->component.name);
458 if (!link)
459 return -EINVAL;
460
461 snd_hdac_ext_link_set_stream_id(link, hdac_stream(link_dev)->stream_tag);
462 link_dev->link_prepared = 1;
463
464 return 0;
465}
466
467static int skl_link_pcm_trigger(struct snd_pcm_substream *substream,
468 int cmd, struct snd_soc_dai *dai)
469{
470 struct hdac_ext_stream *link_dev =
471 snd_soc_dai_get_dma_data(dai, substream);
472
473 dev_dbg(dai->dev, "In %s cmd=%d\n", __func__, cmd);
474 switch (cmd) {
475 case SNDRV_PCM_TRIGGER_START:
476 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
477 case SNDRV_PCM_TRIGGER_RESUME:
478 snd_hdac_ext_link_stream_start(link_dev);
479 break;
480
481 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
482 case SNDRV_PCM_TRIGGER_SUSPEND:
483 case SNDRV_PCM_TRIGGER_STOP:
484 snd_hdac_ext_link_stream_clear(link_dev);
485 break;
486
487 default:
488 return -EINVAL;
489 }
490 return 0;
491}
492
493static int skl_link_hw_free(struct snd_pcm_substream *substream,
494 struct snd_soc_dai *dai)
495{
496 struct hdac_ext_bus *ebus = dev_get_drvdata(dai->dev);
497 struct snd_soc_pcm_runtime *rtd = snd_pcm_substream_chip(substream);
498 struct hdac_ext_stream *link_dev =
499 snd_soc_dai_get_dma_data(dai, substream);
500 struct hdac_ext_link *link;
501
502 dev_dbg(dai->dev, "%s: %s\n", __func__, dai->name);
503
504 link_dev->link_prepared = 0;
505
506 link = snd_hdac_ext_bus_get_link(ebus, rtd->codec->component.name);
507 if (!link)
508 return -EINVAL;
509
510 snd_hdac_ext_link_clear_stream_id(link, hdac_stream(link_dev)->stream_tag);
511 snd_hdac_ext_stream_release(link_dev, HDAC_EXT_STREAM_TYPE_LINK);
512 return 0;
513}
514
Jeeja KPa40e6932015-07-09 15:20:08 +0530515static struct snd_soc_dai_ops skl_pcm_dai_ops = {
516 .startup = skl_pcm_open,
517 .shutdown = skl_pcm_close,
518 .prepare = skl_pcm_prepare,
519 .hw_params = skl_pcm_hw_params,
520 .hw_free = skl_pcm_hw_free,
Jeeja KPb663a8c2015-10-07 11:31:57 +0100521 .trigger = skl_pcm_trigger,
Jeeja KPa40e6932015-07-09 15:20:08 +0530522};
523
Jeeja KP05057002015-07-09 15:20:11 +0530524static struct snd_soc_dai_ops skl_dmic_dai_ops = {
Jeeja KPb663a8c2015-10-07 11:31:57 +0100525 .hw_params = skl_be_hw_params,
Jeeja KPb663a8c2015-10-07 11:31:57 +0100526};
527
528static struct snd_soc_dai_ops skl_be_ssp_dai_ops = {
Jeeja KPb663a8c2015-10-07 11:31:57 +0100529 .hw_params = skl_be_hw_params,
Jeeja KP05057002015-07-09 15:20:11 +0530530};
531
532static struct snd_soc_dai_ops skl_link_dai_ops = {
Jeeja KP05057002015-07-09 15:20:11 +0530533 .prepare = skl_link_pcm_prepare,
534 .hw_params = skl_link_hw_params,
535 .hw_free = skl_link_hw_free,
536 .trigger = skl_link_pcm_trigger,
Jeeja KP05057002015-07-09 15:20:11 +0530537};
538
Jeeja KPa40e6932015-07-09 15:20:08 +0530539static struct snd_soc_dai_driver skl_platform_dai[] = {
540{
541 .name = "System Pin",
542 .ops = &skl_pcm_dai_ops,
543 .playback = {
544 .stream_name = "System Playback",
545 .channels_min = HDA_MONO,
546 .channels_max = HDA_STEREO,
547 .rates = SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_16000 | SNDRV_PCM_RATE_8000,
548 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE,
549 },
550 .capture = {
551 .stream_name = "System Capture",
552 .channels_min = HDA_MONO,
553 .channels_max = HDA_STEREO,
554 .rates = SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_16000,
555 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE,
556 },
557},
558{
Jeeja KP05057002015-07-09 15:20:11 +0530559 .name = "Reference Pin",
560 .ops = &skl_pcm_dai_ops,
561 .capture = {
562 .stream_name = "Reference Capture",
563 .channels_min = HDA_MONO,
Jeeja KP8f35bf32015-11-28 15:01:46 +0530564 .channels_max = HDA_QUAD,
Jeeja KP05057002015-07-09 15:20:11 +0530565 .rates = SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_16000,
566 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE,
567 },
568},
569{
Jeeja KPa40e6932015-07-09 15:20:08 +0530570 .name = "Deepbuffer Pin",
571 .ops = &skl_pcm_dai_ops,
572 .playback = {
573 .stream_name = "Deepbuffer Playback",
574 .channels_min = HDA_STEREO,
575 .channels_max = HDA_STEREO,
576 .rates = SNDRV_PCM_RATE_48000,
577 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE,
578 },
579},
580{
581 .name = "LowLatency Pin",
582 .ops = &skl_pcm_dai_ops,
583 .playback = {
584 .stream_name = "Low Latency Playback",
585 .channels_min = HDA_STEREO,
586 .channels_max = HDA_STEREO,
587 .rates = SNDRV_PCM_RATE_48000,
588 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE,
589 },
590},
Jeeja KP8f35bf32015-11-28 15:01:46 +0530591{
592 .name = "DMIC Pin",
593 .ops = &skl_pcm_dai_ops,
594 .capture = {
595 .stream_name = "DMIC Capture",
596 .channels_min = HDA_MONO,
597 .channels_max = HDA_QUAD,
598 .rates = SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_16000,
599 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE,
600 },
601},
602
Jeeja KP05057002015-07-09 15:20:11 +0530603/* BE CPU Dais */
604{
Jeeja KPb663a8c2015-10-07 11:31:57 +0100605 .name = "SSP0 Pin",
606 .ops = &skl_be_ssp_dai_ops,
607 .playback = {
608 .stream_name = "ssp0 Tx",
609 .channels_min = HDA_STEREO,
610 .channels_max = HDA_STEREO,
611 .rates = SNDRV_PCM_RATE_48000,
612 .formats = SNDRV_PCM_FMTBIT_S16_LE,
613 },
614 .capture = {
615 .stream_name = "ssp0 Rx",
616 .channels_min = HDA_STEREO,
617 .channels_max = HDA_STEREO,
618 .rates = SNDRV_PCM_RATE_48000,
619 .formats = SNDRV_PCM_FMTBIT_S16_LE,
620 },
621},
622{
Jeeja KPc80fd4d2015-11-05 22:53:06 +0530623 .name = "SSP1 Pin",
624 .ops = &skl_be_ssp_dai_ops,
625 .playback = {
626 .stream_name = "ssp1 Tx",
627 .channels_min = HDA_STEREO,
628 .channels_max = HDA_STEREO,
629 .rates = SNDRV_PCM_RATE_48000,
630 .formats = SNDRV_PCM_FMTBIT_S16_LE,
631 },
632 .capture = {
633 .stream_name = "ssp1 Rx",
634 .channels_min = HDA_STEREO,
635 .channels_max = HDA_STEREO,
636 .rates = SNDRV_PCM_RATE_48000,
637 .formats = SNDRV_PCM_FMTBIT_S16_LE,
638 },
639},
640{
Jeeja KP05057002015-07-09 15:20:11 +0530641 .name = "iDisp Pin",
642 .ops = &skl_link_dai_ops,
643 .playback = {
644 .stream_name = "iDisp Tx",
645 .channels_min = HDA_STEREO,
646 .channels_max = HDA_STEREO,
647 .rates = SNDRV_PCM_RATE_8000|SNDRV_PCM_RATE_16000|SNDRV_PCM_RATE_48000,
648 .formats = SNDRV_PCM_FMTBIT_S16_LE,
649 },
650},
651{
652 .name = "DMIC01 Pin",
653 .ops = &skl_dmic_dai_ops,
654 .capture = {
655 .stream_name = "DMIC01 Rx",
Jeeja KP8f35bf32015-11-28 15:01:46 +0530656 .channels_min = HDA_MONO,
657 .channels_max = HDA_QUAD,
Jeeja KP05057002015-07-09 15:20:11 +0530658 .rates = SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_16000,
659 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE,
660 },
661},
662{
Jeeja KP05057002015-07-09 15:20:11 +0530663 .name = "HD-Codec Pin",
664 .ops = &skl_link_dai_ops,
665 .playback = {
666 .stream_name = "HD-Codec Tx",
667 .channels_min = HDA_STEREO,
668 .channels_max = HDA_STEREO,
669 .rates = SNDRV_PCM_RATE_48000,
670 .formats = SNDRV_PCM_FMTBIT_S16_LE,
671 },
672 .capture = {
673 .stream_name = "HD-Codec Rx",
674 .channels_min = HDA_STEREO,
675 .channels_max = HDA_STEREO,
676 .rates = SNDRV_PCM_RATE_48000,
677 .formats = SNDRV_PCM_FMTBIT_S16_LE,
678 },
679},
Jeeja KPa40e6932015-07-09 15:20:08 +0530680};
681
682static int skl_platform_open(struct snd_pcm_substream *substream)
683{
684 struct snd_pcm_runtime *runtime;
685 struct snd_soc_pcm_runtime *rtd = substream->private_data;
686 struct snd_soc_dai_link *dai_link = rtd->dai_link;
687
688 dev_dbg(rtd->cpu_dai->dev, "In %s:%s\n", __func__,
689 dai_link->cpu_dai_name);
690
691 runtime = substream->runtime;
692 snd_soc_set_runtime_hwparams(substream, &azx_pcm_hw);
693
694 return 0;
695}
696
Jeeja KPb663a8c2015-10-07 11:31:57 +0100697static int skl_coupled_trigger(struct snd_pcm_substream *substream,
Jeeja KPa40e6932015-07-09 15:20:08 +0530698 int cmd)
699{
700 struct hdac_ext_bus *ebus = get_bus_ctx(substream);
701 struct hdac_bus *bus = ebus_to_hbus(ebus);
702 struct hdac_ext_stream *stream;
703 struct snd_pcm_substream *s;
704 bool start;
705 int sbits = 0;
706 unsigned long cookie;
707 struct hdac_stream *hstr;
708
709 stream = get_hdac_ext_stream(substream);
710 hstr = hdac_stream(stream);
711
712 dev_dbg(bus->dev, "In %s cmd=%d\n", __func__, cmd);
713
714 if (!hstr->prepared)
715 return -EPIPE;
716
717 switch (cmd) {
718 case SNDRV_PCM_TRIGGER_START:
719 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
720 case SNDRV_PCM_TRIGGER_RESUME:
721 start = true;
722 break;
723
724 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
725 case SNDRV_PCM_TRIGGER_SUSPEND:
726 case SNDRV_PCM_TRIGGER_STOP:
727 start = false;
728 break;
729
730 default:
731 return -EINVAL;
732 }
733
734 snd_pcm_group_for_each_entry(s, substream) {
735 if (s->pcm->card != substream->pcm->card)
736 continue;
737 stream = get_hdac_ext_stream(s);
738 sbits |= 1 << hdac_stream(stream)->index;
739 snd_pcm_trigger_done(s, substream);
740 }
741
742 spin_lock_irqsave(&bus->reg_lock, cookie);
743
744 /* first, set SYNC bits of corresponding streams */
745 snd_hdac_stream_sync_trigger(hstr, true, sbits, AZX_REG_SSYNC);
746
747 snd_pcm_group_for_each_entry(s, substream) {
748 if (s->pcm->card != substream->pcm->card)
749 continue;
750 stream = get_hdac_ext_stream(s);
751 if (start)
752 snd_hdac_stream_start(hdac_stream(stream), true);
753 else
754 snd_hdac_stream_stop(hdac_stream(stream));
755 }
756 spin_unlock_irqrestore(&bus->reg_lock, cookie);
757
758 snd_hdac_stream_sync(hstr, start, sbits);
759
760 spin_lock_irqsave(&bus->reg_lock, cookie);
761
762 /* reset SYNC bits */
763 snd_hdac_stream_sync_trigger(hstr, false, sbits, AZX_REG_SSYNC);
764 if (start)
765 snd_hdac_stream_timecounter_init(hstr, sbits);
766 spin_unlock_irqrestore(&bus->reg_lock, cookie);
767
768 return 0;
769}
770
Jeeja KP05057002015-07-09 15:20:11 +0530771static int skl_platform_pcm_trigger(struct snd_pcm_substream *substream,
772 int cmd)
773{
774 struct hdac_ext_bus *ebus = get_bus_ctx(substream);
775
Jeeja KPd1730c32015-10-27 09:22:53 +0900776 if (!ebus->ppcap)
Jeeja KPb663a8c2015-10-07 11:31:57 +0100777 return skl_coupled_trigger(substream, cmd);
Jeeja KPd1730c32015-10-27 09:22:53 +0900778
779 return 0;
Jeeja KP05057002015-07-09 15:20:11 +0530780}
781
Jeeja KPa40e6932015-07-09 15:20:08 +0530782/* calculate runtime delay from LPIB */
783static int skl_get_delay_from_lpib(struct hdac_ext_bus *ebus,
784 struct hdac_ext_stream *sstream,
785 unsigned int pos)
786{
787 struct hdac_bus *bus = ebus_to_hbus(ebus);
788 struct hdac_stream *hstream = hdac_stream(sstream);
789 struct snd_pcm_substream *substream = hstream->substream;
790 int stream = substream->stream;
791 unsigned int lpib_pos = snd_hdac_stream_get_pos_lpib(hstream);
792 int delay;
793
794 if (stream == SNDRV_PCM_STREAM_PLAYBACK)
795 delay = pos - lpib_pos;
796 else
797 delay = lpib_pos - pos;
798
799 if (delay < 0) {
800 if (delay >= hstream->delay_negative_threshold)
801 delay = 0;
802 else
803 delay += hstream->bufsize;
804 }
805
806 if (delay >= hstream->period_bytes) {
807 dev_info(bus->dev,
808 "Unstable LPIB (%d >= %d); disabling LPIB delay counting\n",
809 delay, hstream->period_bytes);
810 delay = 0;
811 }
812
813 return bytes_to_frames(substream->runtime, delay);
814}
815
816static unsigned int skl_get_position(struct hdac_ext_stream *hstream,
817 int codec_delay)
818{
819 struct hdac_stream *hstr = hdac_stream(hstream);
820 struct snd_pcm_substream *substream = hstr->substream;
Vinod Koulc7b2a442015-10-30 20:34:20 +0530821 struct hdac_ext_bus *ebus;
Jeeja KPa40e6932015-07-09 15:20:08 +0530822 unsigned int pos;
823 int delay;
824
825 /* use the position buffer as default */
826 pos = snd_hdac_stream_get_pos_posbuf(hdac_stream(hstream));
827
828 if (pos >= hdac_stream(hstream)->bufsize)
829 pos = 0;
830
831 if (substream->runtime) {
Vinod Koulc7b2a442015-10-30 20:34:20 +0530832 ebus = get_bus_ctx(substream);
Jeeja KPa40e6932015-07-09 15:20:08 +0530833 delay = skl_get_delay_from_lpib(ebus, hstream, pos)
834 + codec_delay;
835 substream->runtime->delay += delay;
836 }
837
838 return pos;
839}
840
841static snd_pcm_uframes_t skl_platform_pcm_pointer
842 (struct snd_pcm_substream *substream)
843{
844 struct hdac_ext_stream *hstream = get_hdac_ext_stream(substream);
845
846 return bytes_to_frames(substream->runtime,
847 skl_get_position(hstream, 0));
848}
849
850static u64 skl_adjust_codec_delay(struct snd_pcm_substream *substream,
851 u64 nsec)
852{
853 struct snd_soc_pcm_runtime *rtd = snd_pcm_substream_chip(substream);
854 struct snd_soc_dai *codec_dai = rtd->codec_dai;
855 u64 codec_frames, codec_nsecs;
856
857 if (!codec_dai->driver->ops->delay)
858 return nsec;
859
860 codec_frames = codec_dai->driver->ops->delay(substream, codec_dai);
861 codec_nsecs = div_u64(codec_frames * 1000000000LL,
862 substream->runtime->rate);
863
864 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
865 return nsec + codec_nsecs;
866
867 return (nsec > codec_nsecs) ? nsec - codec_nsecs : 0;
868}
869
870static int skl_get_time_info(struct snd_pcm_substream *substream,
871 struct timespec *system_ts, struct timespec *audio_ts,
872 struct snd_pcm_audio_tstamp_config *audio_tstamp_config,
873 struct snd_pcm_audio_tstamp_report *audio_tstamp_report)
874{
875 struct hdac_ext_stream *sstream = get_hdac_ext_stream(substream);
876 struct hdac_stream *hstr = hdac_stream(sstream);
877 u64 nsec;
878
879 if ((substream->runtime->hw.info & SNDRV_PCM_INFO_HAS_LINK_ATIME) &&
880 (audio_tstamp_config->type_requested == SNDRV_PCM_AUDIO_TSTAMP_TYPE_LINK)) {
881
882 snd_pcm_gettime(substream->runtime, system_ts);
883
884 nsec = timecounter_read(&hstr->tc);
885 nsec = div_u64(nsec, 3); /* can be optimized */
886 if (audio_tstamp_config->report_delay)
887 nsec = skl_adjust_codec_delay(substream, nsec);
888
889 *audio_ts = ns_to_timespec(nsec);
890
891 audio_tstamp_report->actual_type = SNDRV_PCM_AUDIO_TSTAMP_TYPE_LINK;
892 audio_tstamp_report->accuracy_report = 1; /* rest of struct is valid */
893 audio_tstamp_report->accuracy = 42; /* 24MHzWallClk == 42ns resolution */
894
895 } else {
896 audio_tstamp_report->actual_type = SNDRV_PCM_AUDIO_TSTAMP_TYPE_DEFAULT;
897 }
898
899 return 0;
900}
901
902static struct snd_pcm_ops skl_platform_ops = {
903 .open = skl_platform_open,
904 .ioctl = snd_pcm_lib_ioctl,
905 .trigger = skl_platform_pcm_trigger,
906 .pointer = skl_platform_pcm_pointer,
907 .get_time_info = skl_get_time_info,
908 .mmap = snd_pcm_lib_default_mmap,
909 .page = snd_pcm_sgbuf_ops_page,
910};
911
912static void skl_pcm_free(struct snd_pcm *pcm)
913{
914 snd_pcm_lib_preallocate_free_for_all(pcm);
915}
916
917#define MAX_PREALLOC_SIZE (32 * 1024 * 1024)
918
919static int skl_pcm_new(struct snd_soc_pcm_runtime *rtd)
920{
921 struct snd_soc_dai *dai = rtd->cpu_dai;
922 struct hdac_ext_bus *ebus = dev_get_drvdata(dai->dev);
923 struct snd_pcm *pcm = rtd->pcm;
924 unsigned int size;
925 int retval = 0;
926 struct skl *skl = ebus_to_skl(ebus);
927
928 if (dai->driver->playback.channels_min ||
929 dai->driver->capture.channels_min) {
930 /* buffer pre-allocation */
931 size = CONFIG_SND_HDA_PREALLOC_SIZE * 1024;
932 if (size > MAX_PREALLOC_SIZE)
933 size = MAX_PREALLOC_SIZE;
934 retval = snd_pcm_lib_preallocate_pages_for_all(pcm,
935 SNDRV_DMA_TYPE_DEV_SG,
936 snd_dma_pci_data(skl->pci),
937 size, MAX_PREALLOC_SIZE);
938 if (retval) {
939 dev_err(dai->dev, "dma buffer allocationf fail\n");
940 return retval;
941 }
942 }
943
944 return retval;
945}
946
Jeeja KPb663a8c2015-10-07 11:31:57 +0100947static int skl_platform_soc_probe(struct snd_soc_platform *platform)
948{
949 struct hdac_ext_bus *ebus = dev_get_drvdata(platform->dev);
950
951 if (ebus->ppcap)
952 return skl_tplg_init(platform, ebus);
953
954 return 0;
955}
Jeeja KPa40e6932015-07-09 15:20:08 +0530956static struct snd_soc_platform_driver skl_platform_drv = {
Jeeja KPb663a8c2015-10-07 11:31:57 +0100957 .probe = skl_platform_soc_probe,
Jeeja KPa40e6932015-07-09 15:20:08 +0530958 .ops = &skl_platform_ops,
959 .pcm_new = skl_pcm_new,
960 .pcm_free = skl_pcm_free,
961};
962
963static const struct snd_soc_component_driver skl_component = {
964 .name = "pcm",
965};
966
967int skl_platform_register(struct device *dev)
968{
969 int ret;
Jeeja KPb663a8c2015-10-07 11:31:57 +0100970 struct hdac_ext_bus *ebus = dev_get_drvdata(dev);
971 struct skl *skl = ebus_to_skl(ebus);
972
973 INIT_LIST_HEAD(&skl->ppl_list);
Jeeja KPa40e6932015-07-09 15:20:08 +0530974
975 ret = snd_soc_register_platform(dev, &skl_platform_drv);
976 if (ret) {
977 dev_err(dev, "soc platform registration failed %d\n", ret);
978 return ret;
979 }
980 ret = snd_soc_register_component(dev, &skl_component,
981 skl_platform_dai,
982 ARRAY_SIZE(skl_platform_dai));
983 if (ret) {
984 dev_err(dev, "soc component registration failed %d\n", ret);
985 snd_soc_unregister_platform(dev);
986 }
987
988 return ret;
989
990}
991
992int skl_platform_unregister(struct device *dev)
993{
994 snd_soc_unregister_component(dev);
995 snd_soc_unregister_platform(dev);
996 return 0;
997}