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gerrit-public.fairphone.software / kernel / msm-4.9 / 9c000586057925ad2e04ffb7b287a721c53730bf / . / drivers / clk / msm / clock-gcc-8952.c
blob: 3c989eb5d949bf5b8e432f3bac3906d65db6219d [file] [log] [blame]
Shefali Jain79729af2018-01-29 15:15:20 +0530[diff] [blame]1/*
2 * Copyright (c) 2014-2018, The Linux Foundation. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 and
6 * only version 2 as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 */
13
14#include <linux/kernel.h>
15#include <linux/init.h>
16#include <linux/err.h>
17#include <linux/ctype.h>
18#include <linux/io.h>
19#include <linux/spinlock.h>
20#include <linux/clk.h>
21#include <linux/regulator/consumer.h>
22#include <linux/platform_device.h>
23#include <linux/module.h>
24#include <linux/of.h>
25#include <linux/of_platform.h>
26#include <soc/qcom/clock-local2.h>
27#include <soc/qcom/clock-pll.h>
28#include <soc/qcom/clock-alpha-pll.h>
29#include <soc/qcom/clock-voter.h>
30#include <soc/qcom/rpm-smd.h>
31#include <soc/qcom/clock-rpm.h>
32
33#include <linux/clk/msm-clock-generic.h>
34#include <linux/regulator/rpm-smd-regulator.h>
35
36#include <dt-bindings/clock/msm-clocks-8952.h>
37#include <dt-bindings/clock/msm-clocks-hwio-8952.h>
38
39#include "clock.h"
40#include "reset.h"
41
42enum {
43 GCC_BASE,
44 APCS_C1_PLL_BASE,
45 APCS_C0_PLL_BASE,
46 APCS_CCI_PLL_BASE,
47 N_BASES,
48};
49
50static void __iomem *virt_bases[N_BASES];
51#define GCC_REG_BASE(x) (void __iomem *)(virt_bases[GCC_BASE] + (x))
52
53static DEFINE_VDD_REGULATORS(vdd_dig, VDD_DIG_NUM, 1, vdd_corner, NULL);
54
55/* SMD clocks */
56DEFINE_CLK_RPM_SMD_BRANCH(xo_clk_src, xo_a_clk_src, RPM_MISC_CLK_TYPE,
57 CXO_CLK_SRC_ID, 19200000);
58DEFINE_CLK_RPM_SMD(pnoc_clk, pnoc_a_clk, RPM_BUS_CLK_TYPE, PNOC_CLK_ID, NULL);
59DEFINE_CLK_RPM_SMD(bimc_clk, bimc_a_clk, RPM_MEM_CLK_TYPE, BIMC_CLK_ID, NULL);
60DEFINE_CLK_RPM_SMD(bimc_gpu_clk, bimc_gpu_a_clk, RPM_MEM_CLK_TYPE,
61 BIMC_GPU_CLK_ID, NULL);
62DEFINE_CLK_RPM_SMD(snoc_clk, snoc_a_clk, RPM_BUS_CLK_TYPE, SNOC_CLK_ID, NULL);
63DEFINE_CLK_RPM_SMD(sysmmnoc_clk, sysmmnoc_a_clk, RPM_BUS_CLK_TYPE,
64 SYSMMNOC_CLK_ID, NULL);
65DEFINE_CLK_RPM_SMD(ipa_clk, ipa_a_clk, RPM_IPA_CLK_TYPE, IPA_CLK_ID, NULL);
66DEFINE_CLK_RPM_SMD_QDSS(qdss_clk, qdss_a_clk, RPM_MISC_CLK_TYPE, QDSS_CLK_ID);
67
68/* SMD_XO_BUFFER */
69DEFINE_CLK_RPM_SMD_XO_BUFFER(bb_clk1, bb_clk1_a, BB_CLK1_ID);
70DEFINE_CLK_RPM_SMD_XO_BUFFER(bb_clk2, bb_clk2_a, BB_CLK2_ID);
71DEFINE_CLK_RPM_SMD_XO_BUFFER(rf_clk2, rf_clk2_a, RF_CLK2_ID);
72DEFINE_CLK_RPM_SMD_XO_BUFFER(div_clk2, div_clk2_a, DIV_CLK2_ID);
73
74DEFINE_CLK_RPM_SMD_XO_BUFFER_PINCTRL(bb_clk1_pin, bb_clk1_a_pin, BB_CLK1_ID);
75DEFINE_CLK_RPM_SMD_XO_BUFFER_PINCTRL(bb_clk2_pin, bb_clk2_a_pin, BB_CLK2_ID);
76
77/* Voter clocks */
78static DEFINE_CLK_VOTER(pnoc_msmbus_clk, &pnoc_clk.c, LONG_MAX);
79static DEFINE_CLK_VOTER(snoc_msmbus_clk, &snoc_clk.c, LONG_MAX);
80static DEFINE_CLK_VOTER(sysmmnoc_msmbus_clk, &sysmmnoc_clk.c, LONG_MAX);
81static DEFINE_CLK_VOTER(bimc_msmbus_clk, &bimc_clk.c, LONG_MAX);
82
83static DEFINE_CLK_VOTER(pnoc_msmbus_a_clk, &pnoc_a_clk.c, LONG_MAX);
84static DEFINE_CLK_VOTER(snoc_msmbus_a_clk, &snoc_a_clk.c, LONG_MAX);
85static DEFINE_CLK_VOTER(sysmmnoc_msmbus_a_clk, &sysmmnoc_a_clk.c, LONG_MAX);
86static DEFINE_CLK_VOTER(bimc_msmbus_a_clk, &bimc_a_clk.c, LONG_MAX);
87static DEFINE_CLK_VOTER(pnoc_keepalive_a_clk, &pnoc_a_clk.c, LONG_MAX);
88
89static DEFINE_CLK_VOTER(pnoc_usb_a_clk, &pnoc_a_clk.c, LONG_MAX);
90static DEFINE_CLK_VOTER(snoc_usb_a_clk, &snoc_a_clk.c, LONG_MAX);
91static DEFINE_CLK_VOTER(bimc_usb_a_clk, &bimc_a_clk.c, LONG_MAX);
92
93static DEFINE_CLK_VOTER(pnoc_usb_clk, &pnoc_clk.c, LONG_MAX);
94static DEFINE_CLK_VOTER(snoc_usb_clk, &snoc_clk.c, LONG_MAX);
95static DEFINE_CLK_VOTER(bimc_usb_clk, &bimc_clk.c, LONG_MAX);
96
97static DEFINE_CLK_VOTER(snoc_wcnss_a_clk, &snoc_a_clk.c, LONG_MAX);
98static DEFINE_CLK_VOTER(bimc_wcnss_a_clk, &bimc_a_clk.c, LONG_MAX);
99
100/* Branch Voter clocks */
101static DEFINE_CLK_BRANCH_VOTER(xo_gcc, &xo_clk_src.c);
102static DEFINE_CLK_BRANCH_VOTER(xo_otg_clk, &xo_clk_src.c);
103static DEFINE_CLK_BRANCH_VOTER(xo_lpm_clk, &xo_clk_src.c);
104static DEFINE_CLK_BRANCH_VOTER(xo_pil_pronto_clk, &xo_clk_src.c);
105static DEFINE_CLK_BRANCH_VOTER(xo_pil_mss_clk, &xo_clk_src.c);
106static DEFINE_CLK_BRANCH_VOTER(xo_wlan_clk, &xo_clk_src.c);
107static DEFINE_CLK_BRANCH_VOTER(xo_pil_lpass_clk, &xo_clk_src.c);
108
109DEFINE_CLK_DUMMY(wcnss_m_clk, 0);
110
111enum vdd_sr2_pll_levels {
112 VDD_SR2_PLL_OFF,
113 VDD_SR2_PLL_SVS,
114 VDD_SR2_PLL_NOM,
115 VDD_SR2_PLL_TUR,
116 VDD_SR2_PLL_SUPER_TUR,
117 VDD_SR2_PLL_NUM,
118};
119
120static int vdd_sr2_levels[] = {
121 0, RPM_REGULATOR_LEVEL_NONE, /* VDD_SR2_PLL_OFF */
122 1800000, RPM_REGULATOR_LEVEL_SVS, /* VDD_SR2_PLL_SVS */
123 1800000, RPM_REGULATOR_LEVEL_NOM, /* VDD_SR2_PLL_NOM */
124 1800000, RPM_REGULATOR_LEVEL_TURBO, /* VDD_SR2_PLL_TUR */
125 1800000, RPM_REGULATOR_LEVEL_BINNING, /* VDD_SR2_PLL_SUPER_TUR */
126};
127
128static DEFINE_VDD_REGULATORS(vdd_sr2_pll, VDD_SR2_PLL_NUM, 2,
129 vdd_sr2_levels, NULL);
130
131enum vdd_hf_pll_levels {
132 VDD_HF_PLL_OFF,
133 VDD_HF_PLL_SVS,
134 VDD_HF_PLL_NOM,
135 VDD_HF_PLL_TUR,
136 VDD_HF_PLL_SUPER_TUR,
137 VDD_HF_PLL_NUM,
138};
139
140static int vdd_hf_levels[] = {
141 0, RPM_REGULATOR_LEVEL_NONE, /* VDD_HF_PLL_OFF */
142 1800000, RPM_REGULATOR_LEVEL_SVS, /* VDD_HF_PLL_SVS */
143 1800000, RPM_REGULATOR_LEVEL_NOM, /* VDD_HF_PLL_NOM */
144 1800000, RPM_REGULATOR_LEVEL_TURBO, /* VDD_HF_PLL_TUR */
145 1800000, RPM_REGULATOR_LEVEL_BINNING, /* VDD_HF_PLL_SUPER_TUR */
146};
147static DEFINE_VDD_REGULATORS(vdd_hf_pll, VDD_HF_PLL_NUM, 2,
148 vdd_hf_levels, NULL);
149
150static struct pll_freq_tbl apcs_cci_pll_freq[] = {
151 F_APCS_PLL(307200000, 16, 0x0, 0x1, 0x0, 0x0, 0x0),
152 F_APCS_PLL(600000000, 31, 0x1, 0x4, 0x0, 0x0, 0x0),
153};
154
155static struct pll_clk a53ss_cci_pll = {
156 .mode_reg = (void __iomem *)APCS_CCI_PLL_MODE,
157 .l_reg = (void __iomem *)APCS_CCI_PLL_L_VAL,
158 .m_reg = (void __iomem *)APCS_CCI_PLL_M_VAL,
159 .n_reg = (void __iomem *)APCS_CCI_PLL_N_VAL,
160 .config_reg = (void __iomem *)APCS_CCI_PLL_USER_CTL,
161 .status_reg = (void __iomem *)APCS_CCI_PLL_STATUS,
162 .freq_tbl = apcs_cci_pll_freq,
163 .masks = {
164 .vco_mask = BM(29, 28),
165 .pre_div_mask = BIT(12),
166 .post_div_mask = BM(9, 8),
167 .mn_en_mask = BIT(24),
168 .main_output_mask = BIT(0),
169 },
170 .base = &virt_bases[APCS_CCI_PLL_BASE],
171 .spm_ctrl = {
172 .offset = 0x40,
173 .event_bit = 0x0,
174 },
175 .c = {
176 .parent = &xo_a_clk_src.c,
177 .dbg_name = "a53ss_cci_pll",
178 .ops = &clk_ops_sr2_pll,
179 .vdd_class = &vdd_sr2_pll,
180 .fmax = (unsigned long [VDD_SR2_PLL_NUM]) {
181 [VDD_SR2_PLL_SVS] = 1000000000,
182 [VDD_SR2_PLL_NOM] = 1900000000,
183 },
184 .num_fmax = VDD_SR2_PLL_NUM,
185 CLK_INIT(a53ss_cci_pll.c),
186 },
187};
188
189static struct pll_freq_tbl apcs_c0_pll_freq[] = {
190 F_APCS_PLL( 249600000, 13, 0x0, 0x1, 0x0, 0x0, 0x0),
191 F_APCS_PLL( 307200000, 16, 0x0, 0x1, 0x0, 0x0, 0x0),
192 F_APCS_PLL( 345600000, 18, 0x0, 0x1, 0x0, 0x0, 0x0),
193 F_APCS_PLL( 384000000, 20, 0x0, 0x1, 0x0, 0x0, 0x0),
194 F_APCS_PLL( 460800000, 24, 0x0, 0x1, 0x0, 0x0, 0x0),
195 F_APCS_PLL( 499200000, 26, 0x0, 0x1, 0x0, 0x0, 0x0),
196 F_APCS_PLL( 518400000, 27, 0x0, 0x1, 0x0, 0x0, 0x0),
197 F_APCS_PLL( 768000000, 40, 0x0, 0x1, 0x0, 0x0, 0x0),
198 F_APCS_PLL( 806400000, 42, 0x0, 0x1, 0x0, 0x0, 0x0),
199 F_APCS_PLL( 844800000, 44, 0x0, 0x1, 0x0, 0x0, 0x0),
200 F_APCS_PLL( 883200000, 46, 0x0, 0x1, 0x0, 0x0, 0x0),
201 F_APCS_PLL( 902400000, 47, 0x0, 0x1, 0x0, 0x0, 0x0),
202 F_APCS_PLL( 921600000, 48, 0x0, 0x1, 0x0, 0x0, 0x0),
203 F_APCS_PLL( 998400000, 52, 0x0, 0x1, 0x0, 0x0, 0x0),
204 F_APCS_PLL(1094400000, 57, 0x0, 0x1, 0x0, 0x0, 0x0),
Odelu Kukatla678382b2018-03-27 22:58:52 +0530[diff] [blame]205 F_APCS_PLL(1171200000, 61, 0x0, 0x1, 0x0, 0x0, 0x0),
Shefali Jain79729af2018-01-29 15:15:20 +0530[diff] [blame]206 F_APCS_PLL(1209600000, 63, 0x0, 0x1, 0x0, 0x0, 0x0),
Odelu Kukatla678382b2018-03-27 22:58:52 +0530[diff] [blame]207 F_APCS_PLL(1305600000, 68, 0x0, 0x1, 0x0, 0x0, 0x0),
208 F_APCS_PLL(1459200000, 76, 0x0, 0x1, 0x0, 0x0, 0x0),
Shefali Jain79729af2018-01-29 15:15:20 +0530[diff] [blame]209};
210
211static struct pll_clk a53ss_c0_pll = {
212 .mode_reg = (void __iomem *)APCS_C0_PLL_MODE,
213 .l_reg = (void __iomem *)APCS_C0_PLL_L_VAL,
214 .m_reg = (void __iomem *)APCS_C0_PLL_M_VAL,
215 .n_reg = (void __iomem *)APCS_C0_PLL_N_VAL,
216 .config_reg = (void __iomem *)APCS_C0_PLL_USER_CTL,
217 .status_reg = (void __iomem *)APCS_C0_PLL_STATUS,
218 .freq_tbl = apcs_c0_pll_freq,
Odelu Kukatla3e82fd32018-06-05 12:08:53 +0530[diff] [blame]219 .config_ctl_reg = (void __iomem *)APCS_C0_PLL_CONFIG_CTL,
Shefali Jain79729af2018-01-29 15:15:20 +0530[diff] [blame]220 .masks = {
221 .vco_mask = BM(29, 28),
222 .pre_div_mask = BIT(12),
223 .post_div_mask = BM(9, 8),
224 .mn_en_mask = BIT(24),
225 .main_output_mask = BIT(0),
226 },
227 .base = &virt_bases[APCS_C0_PLL_BASE],
228 .spm_ctrl = {
229 .offset = 0x50,
230 .event_bit = 0x4,
231 },
232 .c = {
233 .parent = &xo_a_clk_src.c,
234 .dbg_name = "a53ss_c0_pll",
235 .ops = &clk_ops_sr2_pll,
236 .vdd_class = &vdd_sr2_pll,
237 .fmax = (unsigned long [VDD_SR2_PLL_NUM]) {
238 [VDD_SR2_PLL_SVS] = 1000000000,
239 [VDD_SR2_PLL_NOM] = 1900000000,
240 },
241 .num_fmax = VDD_SR2_PLL_NUM,
242 CLK_INIT(a53ss_c0_pll.c),
243 },
244};
245
246static struct pll_freq_tbl apcs_c1_pll_freq[] = {
247 F_APCS_PLL( 345600000, 18, 0x0, 0x1, 0x0, 0x0, 0x0),
248 F_APCS_PLL( 422400000, 22, 0x0, 0x1, 0x0, 0x0, 0x0),
249 F_APCS_PLL( 499200000, 26, 0x0, 0x1, 0x0, 0x0, 0x0),
250 F_APCS_PLL( 652800000, 34, 0x0, 0x1, 0x0, 0x0, 0x0),
251 F_APCS_PLL( 729600000, 38, 0x0, 0x1, 0x0, 0x0, 0x0),
252 F_APCS_PLL( 806400000, 42, 0x0, 0x1, 0x0, 0x0, 0x0),
253 F_APCS_PLL( 844800000, 44, 0x0, 0x1, 0x0, 0x0, 0x0),
254 F_APCS_PLL( 883200000, 46, 0x0, 0x1, 0x0, 0x0, 0x0),
255 F_APCS_PLL( 960000000, 50, 0x0, 0x1, 0x0, 0x0, 0x0),
256 F_APCS_PLL( 998400000, 52, 0x0, 0x1, 0x0, 0x0, 0x0),
257 F_APCS_PLL(1036800000, 54, 0x0, 0x1, 0x0, 0x0, 0x0),
258 F_APCS_PLL(1094400000, 57, 0x0, 0x1, 0x0, 0x0, 0x0),
259 F_APCS_PLL(1113600000, 58, 0x0, 0x1, 0x0, 0x0, 0x0),
260 F_APCS_PLL(1190400000, 62, 0x0, 0x1, 0x0, 0x0, 0x0),
261 F_APCS_PLL(1209600000, 63, 0x0, 0x1, 0x0, 0x0, 0x0),
262 F_APCS_PLL(1248000000, 65, 0x0, 0x1, 0x0, 0x0, 0x0),
263 F_APCS_PLL(1267200000, 66, 0x0, 0x1, 0x0, 0x0, 0x0),
Odelu Kukatla678382b2018-03-27 22:58:52 +0530[diff] [blame]264 F_APCS_PLL(1305600000, 68, 0x0, 0x1, 0x0, 0x0, 0x0),
Shefali Jain79729af2018-01-29 15:15:20 +0530[diff] [blame]265 F_APCS_PLL(1344000000, 70, 0x0, 0x1, 0x0, 0x0, 0x0),
266 F_APCS_PLL(1401000000, 73, 0x0, 0x1, 0x0, 0x0, 0x0),
267 F_APCS_PLL(1420800000, 74, 0x0, 0x1, 0x0, 0x0, 0x0),
268 F_APCS_PLL(1440000000, 75, 0x0, 0x1, 0x0, 0x0, 0x0),
269 F_APCS_PLL(1459200000, 76, 0x0, 0x1, 0x0, 0x0, 0x0),
270 F_APCS_PLL(1497600000, 78, 0x0, 0x1, 0x0, 0x0, 0x0),
271 F_APCS_PLL(1516800000, 79, 0x0, 0x1, 0x0, 0x0, 0x0),
272 F_APCS_PLL(1536000000, 80, 0x0, 0x1, 0x0, 0x0, 0x0),
273 F_APCS_PLL(1651200000, 86, 0x0, 0x1, 0x0, 0x0, 0x0),
Odelu Kukatla678382b2018-03-27 22:58:52 +0530[diff] [blame]274 F_APCS_PLL(1708800000, 89, 0x0, 0x1, 0x0, 0x0, 0x0),
275 F_APCS_PLL(1804800000, 94, 0x0, 0x1, 0x0, 0x0, 0x0),
276 F_APCS_PLL(1958400000, 102, 0x0, 0x1, 0x0, 0x0, 0x0),
Shefali Jain79729af2018-01-29 15:15:20 +0530[diff] [blame]277};
278
279static struct pll_clk a53ss_c1_pll = {
280 .mode_reg = (void __iomem *)APCS_C1_PLL_MODE,
281 .l_reg = (void __iomem *)APCS_C1_PLL_L_VAL,
282 .m_reg = (void __iomem *)APCS_C1_PLL_M_VAL,
283 .n_reg = (void __iomem *)APCS_C1_PLL_N_VAL,
284 .config_reg = (void __iomem *)APCS_C1_PLL_USER_CTL,
285 .status_reg = (void __iomem *)APCS_C1_PLL_STATUS,
286 .freq_tbl = apcs_c1_pll_freq,
Odelu Kukatla3e82fd32018-06-05 12:08:53 +0530[diff] [blame]287 .config_ctl_reg = (void __iomem *)APCS_C1_PLL_CONFIG_CTL,
Shefali Jain79729af2018-01-29 15:15:20 +0530[diff] [blame]288 .masks = {
289 .vco_mask = BM(29, 28),
290 .pre_div_mask = BIT(12),
291 .post_div_mask = BM(9, 8),
292 .mn_en_mask = BIT(24),
293 .main_output_mask = BIT(0),
294 },
295 .base = &virt_bases[APCS_C1_PLL_BASE],
296 .spm_ctrl = {
297 .offset = 0x50,
298 .event_bit = 0x4,
299 },
300 .c = {
301 .parent = &xo_a_clk_src.c,
302 .dbg_name = "a53ss_c1_pll",
303 .ops = &clk_ops_sr2_pll,
304 .vdd_class = &vdd_hf_pll,
305 .fmax = (unsigned long [VDD_HF_PLL_NUM]) {
306 [VDD_HF_PLL_SVS] = 1000000000,
307 [VDD_HF_PLL_NOM] = 2000000000,
308 },
309 .num_fmax = VDD_HF_PLL_NUM,
310 CLK_INIT(a53ss_c1_pll.c),
311 },
312};
313
314static struct pll_vote_clk gpll0_sleep_clk_src = {
315 .en_reg = (void __iomem *)APCS_CLOCK_SLEEP_ENA_VOTE,
316 .en_mask = BIT(23),
317 .status_reg = (void __iomem *)GPLL0_MODE,
318 .status_mask = BIT(30),
319 .base = &virt_bases[GCC_BASE],
320 .c = {
321 .parent = &xo_clk_src.c,
322 .rate = 800000000,
323 .dbg_name = "gpll0_sleep_clk_src",
324 .ops = &clk_ops_pll_sleep_vote,
325 CLK_INIT(gpll0_sleep_clk_src.c),
326 },
327};
328
329static unsigned int soft_vote_gpll0;
330
331/* PLL_ACTIVE_FLAG bit of GCC_GPLL0_MODE register
332 * gets set from PLL voting FSM.It indicates when
333 * FSM has enabled the PLL and PLL should be locked.
334 */
335static struct pll_vote_clk gpll0_clk_src_8952 = {
336 .en_reg = (void __iomem *)APCS_GPLL_ENA_VOTE,
337 .en_mask = BIT(0),
338 .status_reg = (void __iomem *)GPLL0_STATUS,
339 .status_mask = BIT(17),
340 .soft_vote = &soft_vote_gpll0,
341 .soft_vote_mask = PLL_SOFT_VOTE_PRIMARY,
342 .base = &virt_bases[GCC_BASE],
343 .c = {
344 .parent = &xo_clk_src.c,
345 .rate = 800000000,
346 .dbg_name = "gpll0_clk_src_8952",
347 .ops = &clk_ops_pll_acpu_vote,
348 CLK_INIT(gpll0_clk_src_8952.c),
349 },
350};
351
352static struct pll_vote_clk gpll0_clk_src_8937 = {
353 .en_reg = (void __iomem *)APCS_GPLL_ENA_VOTE,
354 .en_mask = BIT(0),
355 .status_reg = (void __iomem *)GPLL0_MODE,
356 .status_mask = BIT(30),
357 .soft_vote = &soft_vote_gpll0,
358 .soft_vote_mask = PLL_SOFT_VOTE_PRIMARY,
359 .base = &virt_bases[GCC_BASE],
360 .c = {
361 .parent = &gpll0_sleep_clk_src.c,
362 .rate = 800000000,
363 .dbg_name = "gpll0_clk_src_8937",
364 .ops = &clk_ops_pll_acpu_vote,
365 CLK_INIT(gpll0_clk_src_8937.c),
366 },
367};
368
369DEFINE_EXT_CLK(gpll0_clk_src, NULL);
370DEFINE_EXT_CLK(gpll0_ao_clk_src, NULL);
371DEFINE_EXT_CLK(gpll0_out_aux_clk_src, &gpll0_clk_src.c);
372DEFINE_EXT_CLK(gpll0_out_main_clk_src, &gpll0_clk_src.c);
373DEFINE_EXT_CLK(ext_pclk0_clk_src, NULL);
374DEFINE_EXT_CLK(ext_byte0_clk_src, NULL);
375DEFINE_EXT_CLK(ext_pclk1_clk_src, NULL);
376DEFINE_EXT_CLK(ext_byte1_clk_src, NULL);
377
378/* Don't vote for xo if using this clock to allow xo shutdown */
379static struct pll_vote_clk gpll0_ao_clk_src_8952 = {
380 .en_reg = (void __iomem *)APCS_GPLL_ENA_VOTE,
381 .en_mask = BIT(0),
382 .status_reg = (void __iomem *)GPLL0_STATUS,
383 .status_mask = BIT(17),
384 .soft_vote = &soft_vote_gpll0,
385 .soft_vote_mask = PLL_SOFT_VOTE_ACPU,
386 .base = &virt_bases[GCC_BASE],
387 .c = {
388 .parent = &xo_a_clk_src.c,
389 .rate = 800000000,
390 .dbg_name = "gpll0_ao_clk_src_8952",
391 .ops = &clk_ops_pll_acpu_vote,
392 CLK_INIT(gpll0_ao_clk_src_8952.c),
393 },
394};
395
396static struct pll_vote_clk gpll0_ao_clk_src_8937 = {
397 .en_reg = (void __iomem *)APCS_GPLL_ENA_VOTE,
398 .en_mask = BIT(0),
399 .status_reg = (void __iomem *)GPLL0_MODE,
400 .status_mask = BIT(30),
401 .soft_vote = &soft_vote_gpll0,
402 .soft_vote_mask = PLL_SOFT_VOTE_ACPU,
403 .base = &virt_bases[GCC_BASE],
404 .c = {
405 .parent = &xo_a_clk_src.c,
406 .rate = 800000000,
407 .dbg_name = "gpll0_ao_clk_src_8937",
408 .ops = &clk_ops_pll_acpu_vote,
409 CLK_INIT(gpll0_ao_clk_src_8937.c),
410 },
411};
412
413static struct pll_vote_clk gpll6_clk_src = {
414 .en_reg = (void __iomem *)APCS_GPLL_ENA_VOTE,
415 .en_mask = BIT(7),
416 .status_reg = (void __iomem *)GPLL6_STATUS,
417 .status_mask = BIT(17),
418 .base = &virt_bases[GCC_BASE],
419 .c = {
420 .parent = &xo_clk_src.c,
421 .rate = 1080000000,
422 .dbg_name = "gpll6_clk_src",
423 .ops = &clk_ops_pll_vote,
424 CLK_INIT(gpll6_clk_src.c),
425 },
426};
427
428DEFINE_EXT_CLK(gpll6_aux_clk_src, &gpll6_clk_src.c);
429DEFINE_EXT_CLK(gpll6_out_main_clk_src, &gpll6_clk_src.c);
430
431static struct alpha_pll_masks pll_masks_p = {
432 .lock_mask = BIT(31),
433 .active_mask = BIT(30),
434 .vco_mask = BM(21, 20) >> 20,
435 .vco_shift = 20,
436 .alpha_en_mask = BIT(24),
437 .output_mask = 0xf,
438 .update_mask = BIT(22),
439 .post_div_mask = BM(11, 8),
440 .test_ctl_lo_mask = BM(31, 0),
441 .test_ctl_hi_mask = BM(31, 0),
442};
443
444/* Slewing plls won't allow to change vco_sel.
445 * Hence will have only one vco table entry
446 */
447static struct alpha_pll_vco_tbl p_vco[] = {
448 VCO(0, 700000000, 1400000000),
449};
450
451/* Slewing plls won't allow to change vco_sel.
452 * Hence will have only one vco table entry
453 */
454static struct alpha_pll_vco_tbl p_vco_8937[] = {
455 VCO(1, 525000000, 1066000000),
456};
457
458static struct alpha_pll_clk gpll3_clk_src = {
459 .masks = &pll_masks_p,
460 .base = &virt_bases[GCC_BASE],
461 .offset = GPLL3_MODE,
462 .vco_tbl = p_vco,
463 .num_vco = ARRAY_SIZE(p_vco),
464 .enable_config = 1,
465 /*
466 * gpll3 is dedicated to oxili and has a fuse implementation for
467 * post divider to limit frequency. HW with fuse blown has a divider
468 * value set to 2. So lets stick to divide by 2 in software to avoid
469 * conflicts.
470 */
471 .post_div_config = 1 << 8,
472 .slew = true,
473 .config_ctl_val = 0x4001055b,
474 .test_ctl_hi_val = 0x40000600,
475 .c = {
476 .rate = 1050000000,
477 .parent = &xo_clk_src.c,
478 .dbg_name = "gpll3_clk_src",
479 .ops = &clk_ops_dyna_alpha_pll,
480 VDD_DIG_FMAX_MAP1(NOMINAL, 1400000000),
481 CLK_INIT(gpll3_clk_src.c),
482 },
483};
484
485static struct pll_vote_clk gpll4_clk_src = {
486 .en_reg = (void __iomem *)APCS_GPLL_ENA_VOTE,
487 .en_mask = BIT(5),
488 .status_reg = (void __iomem *)GPLL4_MODE,
489 .status_mask = BIT(30),
490 .base = &virt_bases[GCC_BASE],
491 .c = {
492 .rate = 1152000000,
493 .parent = &xo_clk_src.c,
494 .dbg_name = "gpll4_clk_src",
495 .ops = &clk_ops_pll_vote,
496 VDD_DIG_FMAX_MAP1(NOMINAL, 1400000000),
497 CLK_INIT(gpll4_clk_src.c),
498 },
499};
500DEFINE_EXT_CLK(gpll4_out_clk_src, &gpll4_clk_src.c);
501
502static struct clk_freq_tbl ftbl_gcc_camss_top_ahb_clk[] = {
503 F( 40000000, gpll0, 10, 1, 2),
504 F( 61540000, gpll0, 13, 0, 0),
505 F( 80000000, gpll0, 10, 0, 0),
506 F_END
507};
508
509static struct rcg_clk camss_top_ahb_clk_src = {
510 .cmd_rcgr_reg = CAMSS_TOP_AHB_CMD_RCGR,
511 .set_rate = set_rate_mnd,
512 .freq_tbl = ftbl_gcc_camss_top_ahb_clk,
513 .current_freq = &rcg_dummy_freq,
514 .base = &virt_bases[GCC_BASE],
515 .c = {
516 .dbg_name = "camss_top_ahb_clk_src",
517 .ops = &clk_ops_rcg_mnd,
518 VDD_DIG_FMAX_MAP3(LOWER, 40000000, LOW, 61540000,
519 NOMINAL, 80000000),
520 CLK_INIT(camss_top_ahb_clk_src.c),
521 },
522};
523
524static struct clk_freq_tbl ftbl_gcc_apss_ahb_clk[] = {
525 F( 19200000, xo_a, 1, 0, 0),
526 F( 50000000, gpll0, 16, 0, 0),
527 F( 100000000, gpll0, 8, 0, 0),
528 F( 133330000, gpll0, 6, 0, 0),
529 F_END
530};
531
532static struct rcg_clk apss_ahb_clk_src = {
533 .cmd_rcgr_reg = APSS_AHB_CMD_RCGR,
534 .set_rate = set_rate_hid,
535 .freq_tbl = ftbl_gcc_apss_ahb_clk,
536 .current_freq = &rcg_dummy_freq,
537 .base = &virt_bases[GCC_BASE],
538 .c = {
539 .dbg_name = "apss_ahb_clk_src",
540 .ops = &clk_ops_rcg,
541 CLK_INIT(apss_ahb_clk_src.c),
542 },
543};
544
545static struct clk_freq_tbl ftbl_gcc_camss_csi0_2_clk[] = {
546 F( 100000000, gpll0, 8, 0, 0),
547 F( 160000000, gpll0, 5, 0, 0),
548 F( 200000000, gpll0, 4, 0, 0),
549 F_END
550};
551
552static struct clk_freq_tbl ftbl_gcc_camss_csi0_2_clk_8937[] = {
553 F( 100000000, gpll0, 8, 0, 0),
554 F( 160000000, gpll0, 5, 0, 0),
555 F( 200000000, gpll0, 4, 0, 0),
556 F( 266670000, gpll0, 3, 0, 0),
557 F_END
558};
559
560
561static struct rcg_clk csi0_clk_src = {
562 .cmd_rcgr_reg = CSI0_CMD_RCGR,
563 .set_rate = set_rate_hid,
564 .freq_tbl = ftbl_gcc_camss_csi0_2_clk,
565 .current_freq = &rcg_dummy_freq,
566 .base = &virt_bases[GCC_BASE],
567 .c = {
568 .dbg_name = "csi0_clk_src",
569 .ops = &clk_ops_rcg,
570 VDD_DIG_FMAX_MAP3(LOWER, 100000000, LOW, 160000000,
571 NOMINAL, 200000000),
572 CLK_INIT(csi0_clk_src.c),
573 },
574};
575
576static struct rcg_clk csi1_clk_src = {
577 .cmd_rcgr_reg = CSI1_CMD_RCGR,
578 .set_rate = set_rate_hid,
579 .freq_tbl = ftbl_gcc_camss_csi0_2_clk,
580 .current_freq = &rcg_dummy_freq,
581 .base = &virt_bases[GCC_BASE],
582 .c = {
583 .dbg_name = "csi1_clk_src",
584 .ops = &clk_ops_rcg,
585 VDD_DIG_FMAX_MAP3(LOWER, 100000000, LOW, 160000000,
586 NOMINAL, 200000000),
587 CLK_INIT(csi1_clk_src.c),
588 },
589};
590
591static struct rcg_clk csi2_clk_src = {
592 .cmd_rcgr_reg = CSI2_CMD_RCGR,
593 .set_rate = set_rate_hid,
594 .freq_tbl = ftbl_gcc_camss_csi0_2_clk,
595 .current_freq = &rcg_dummy_freq,
596 .base = &virt_bases[GCC_BASE],
597 .c = {
598 .dbg_name = "csi2_clk_src",
599 .ops = &clk_ops_rcg,
600 VDD_DIG_FMAX_MAP3(LOWER, 100000000, LOW, 160000000,
601 NOMINAL, 200000000),
602 CLK_INIT(csi2_clk_src.c),
603 },
604};
605
606static struct clk_freq_tbl ftbl_gcc_venus0_vcodec0_clk[] = {
607 F( 133330000, gpll0, 6, 0, 0),
608 F( 180000000, gpll6, 6, 0, 0),
609 F( 228570000, gpll0, 3.5, 0, 0),
610 F( 266670000, gpll0, 3, 0, 0),
611 F( 308570000, gpll6, 3.5, 0, 0),
612 F_END
613};
614
615static struct clk_freq_tbl ftbl_gcc_venus0_vcodec0_clk_8937[] = {
616 F( 166150000, gpll6, 6.5, 0, 0),
617 F( 240000000, gpll6, 4.5, 0, 0),
618 F( 308570000, gpll6, 3.5, 0, 0),
619 F( 320000000, gpll0, 2.5, 0, 0),
620 F( 360000000, gpll6, 3, 0, 0),
621 F_END
622};
623
624static struct clk_freq_tbl ftbl_gcc_venus0_vcodec0_clk_8917[] = {
625 F( 160000000, gpll0, 5, 0, 0),
626 F( 200000000, gpll0, 4, 0, 0),
627 F( 270000000, gpll6, 4, 0, 0),
628 F( 308570000, gpll6, 3.5, 0, 0),
629 F( 329140000, gpll4_out, 3.5, 0, 0),
630 F( 360000000, gpll6, 3, 0, 0),
631 F_END
632};
633
634static struct rcg_clk vcodec0_clk_src = {
635 .cmd_rcgr_reg = VCODEC0_CMD_RCGR,
636 .set_rate = set_rate_mnd,
637 .freq_tbl = ftbl_gcc_venus0_vcodec0_clk,
638 .current_freq = &rcg_dummy_freq,
639 .base = &virt_bases[GCC_BASE],
640 .c = {
641 .dbg_name = "vcodec0_clk_src",
642 .ops = &clk_ops_rcg_mnd,
643 VDD_DIG_FMAX_MAP5(LOWER, 133330000, LOW, 180000000,
644 NOMINAL, 228570000, NOM_PLUS, 266670000,
645 HIGH, 308570000),
646 CLK_INIT(vcodec0_clk_src.c),
647 },
648};
649
650static struct clk_freq_tbl ftbl_gcc_camss_vfe0_1_clk[] = {
651 F( 50000000, gpll0, 16, 0, 0),
652 F( 80000000, gpll0, 10, 0, 0),
653 F( 100000000, gpll0, 8, 0, 0),
654 F( 133330000, gpll0, 6, 0, 0),
655 F( 160000000, gpll0, 5, 0, 0),
656 F( 177780000, gpll0, 4.5, 0, 0),
657 F( 200000000, gpll0, 4, 0, 0),
658 F( 266670000, gpll0, 3, 0, 0),
659 F( 308570000, gpll6, 3.5, 0, 0),
660 F( 320000000, gpll0, 2.5, 0, 0),
661 F( 360000000, gpll6, 3, 0, 0),
662 F_END
663};
664
665static struct clk_freq_tbl ftbl_gcc_camss_vfe0_1_clk_8937[] = {
666 F( 50000000, gpll0, 16, 0, 0),
667 F( 80000000, gpll0, 10, 0, 0),
668 F( 100000000, gpll0, 8, 0, 0),
669 F( 133333333, gpll0, 6, 0, 0),
670 F( 160000000, gpll0, 5, 0, 0),
671 F( 177780000, gpll0, 4.5, 0, 0),
672 F( 200000000, gpll0, 4, 0, 0),
673 F( 266670000, gpll0, 3, 0, 0),
674 F( 308570000, gpll6, 3.5, 0, 0),
675 F( 320000000, gpll0, 2.5, 0, 0),
676 F( 360000000, gpll6, 3, 0, 0),
677 F( 400000000, gpll0, 2, 0, 0),
678 F( 432000000, gpll6, 2.5, 0, 0),
679 F_END
680};
681
682static struct clk_freq_tbl ftbl_gcc_camss_vfe0_1_clk_8917[] = {
683 F( 50000000, gpll0, 16, 0, 0),
684 F( 80000000, gpll0, 10, 0, 0),
685 F( 100000000, gpll0, 8, 0, 0),
686 F( 133333333, gpll0, 6, 0, 0),
687 F( 160000000, gpll0, 5, 0, 0),
688 F( 177780000, gpll0, 4.5, 0, 0),
689 F( 200000000, gpll0, 4, 0, 0),
690 F( 266670000, gpll0, 3, 0, 0),
691 F( 308570000, gpll6, 3.5, 0, 0),
692 F( 320000000, gpll0, 2.5, 0, 0),
693 F( 329140000, gpll4_out, 3.5, 0, 0),
694 F( 360000000, gpll6, 3, 0, 0),
695 F_END
696};
697
698static struct rcg_clk vfe0_clk_src = {
699 .cmd_rcgr_reg = VFE0_CMD_RCGR,
700 .set_rate = set_rate_hid,
701 .freq_tbl = ftbl_gcc_camss_vfe0_1_clk,
702 .current_freq = &rcg_dummy_freq,
703 .base = &virt_bases[GCC_BASE],
704 .c = {
705 .dbg_name = "vfe0_clk_src",
706 .ops = &clk_ops_rcg,
707 VDD_DIG_FMAX_MAP5(LOWER, 133330000, LOW, 266670000,
708 NOMINAL, 308570000, NOM_PLUS, 320000000,
709 HIGH, 360000000),
710 CLK_INIT(vfe0_clk_src.c),
711 },
712};
713
714static struct rcg_clk vfe1_clk_src = {
715 .cmd_rcgr_reg = VFE1_CMD_RCGR,
716 .set_rate = set_rate_hid,
717 .freq_tbl = ftbl_gcc_camss_vfe0_1_clk,
718 .current_freq = &rcg_dummy_freq,
719 .base = &virt_bases[GCC_BASE],
720 .c = {
721 .dbg_name = "vfe1_clk_src",
722 .ops = &clk_ops_rcg,
723 VDD_DIG_FMAX_MAP5(LOWER, 133330000, LOW, 266670000,
724 NOMINAL, 308570000, NOM_PLUS, 320000000,
725 HIGH, 360000000),
726 CLK_INIT(vfe1_clk_src.c),
727 },
728};
729
730static struct clk_freq_tbl ftbl_gcc_oxili_gfx3d_clk[] = {
731 F_SLEW( 19200000, FIXED_CLK_SRC, xo, 1, 0, 0),
732 F_SLEW( 50000000, FIXED_CLK_SRC, gpll0, 16, 0, 0),
733 F_SLEW( 80000000, FIXED_CLK_SRC, gpll0, 10, 0, 0),
734 F_SLEW( 100000000, FIXED_CLK_SRC, gpll0, 8, 0, 0),
735 F_SLEW( 160000000, FIXED_CLK_SRC, gpll0, 5, 0, 0),
736 F_SLEW( 200000000, FIXED_CLK_SRC, gpll0, 4, 0, 0),
737 F_SLEW( 228570000, FIXED_CLK_SRC, gpll0, 3.5, 0, 0),
738 F_SLEW( 240000000, FIXED_CLK_SRC, gpll6_aux, 4.5, 0, 0),
739 F_SLEW( 266670000, FIXED_CLK_SRC, gpll0, 3, 0, 0),
740 F_SLEW( 400000000, FIXED_CLK_SRC, gpll0, 2, 0, 0),
741 F_SLEW( 465000000, 930000000, gpll3, 1, 0, 0),
742 F_SLEW( 500000000, 1000000000, gpll3, 1, 0, 0),
743 F_SLEW( 550000000, 1100000000, gpll3, 1, 0, 0),
744 F_END
745};
746
747static struct clk_freq_tbl ftbl_gcc_oxili_gfx3d_clk_8937[] = {
748 F_SLEW( 19200000, FIXED_CLK_SRC, xo, 1, 0, 0),
749 F_SLEW( 50000000, FIXED_CLK_SRC, gpll0, 16, 0, 0),
750 F_SLEW( 80000000, FIXED_CLK_SRC, gpll0, 10, 0, 0),
751 F_SLEW( 100000000, FIXED_CLK_SRC, gpll0, 8, 0, 0),
752 F_SLEW( 160000000, FIXED_CLK_SRC, gpll0, 5, 0, 0),
753 F_SLEW( 200000000, FIXED_CLK_SRC, gpll0, 4, 0, 0),
754 F_SLEW( 216000000, FIXED_CLK_SRC, gpll6_aux, 5, 0, 0),
755 F_SLEW( 228570000, FIXED_CLK_SRC, gpll0, 3.5, 0, 0),
756 F_SLEW( 240000000, FIXED_CLK_SRC, gpll6_aux, 4.5, 0, 0),
757 F_SLEW( 266670000, FIXED_CLK_SRC, gpll0, 3, 0, 0),
758 F_SLEW( 300000000, 600000000, gpll3, 1, 0, 0),
759 F_SLEW( 320000000, FIXED_CLK_SRC, gpll0, 2.5, 0, 0),
760 F_SLEW( 375000000, 750000000, gpll3, 1, 0, 0),
761 F_SLEW( 400000000, FIXED_CLK_SRC, gpll0, 2, 0, 0),
762 F_SLEW( 450000000, 900000000, gpll3, 1, 0, 0),
763 F_END
764};
765
Odelu Kukatla678382b2018-03-27 22:58:52 +0530[diff] [blame]766static struct clk_freq_tbl ftbl_gcc_oxili_gfx3d_clk_sdm439[] = {
767 F_SLEW( 19200000, FIXED_CLK_SRC, xo, 1, 0, 0),
768 F_SLEW( 50000000, FIXED_CLK_SRC, gpll0, 16, 0, 0),
769 F_SLEW( 80000000, FIXED_CLK_SRC, gpll0, 10, 0, 0),
770 F_SLEW( 100000000, FIXED_CLK_SRC, gpll0, 8, 0, 0),
771 F_SLEW( 160000000, FIXED_CLK_SRC, gpll0, 5, 0, 0),
772 F_SLEW( 200000000, FIXED_CLK_SRC, gpll0, 4, 0, 0),
773 F_SLEW( 216000000, FIXED_CLK_SRC, gpll6_aux, 5, 0, 0),
774 F_SLEW( 228570000, FIXED_CLK_SRC, gpll0, 3.5, 0, 0),
775 F_SLEW( 240000000, FIXED_CLK_SRC, gpll6_aux, 4.5, 0, 0),
776 F_SLEW( 259200000, 1296000000, gpll3, 2.5, 0, 0),
777 F_SLEW( 266670000, FIXED_CLK_SRC, gpll0, 3, 0, 0),
778 F_SLEW( 320000000, FIXED_CLK_SRC, gpll0, 2.5, 0, 0),
779 F_SLEW( 355200000, 710400000, gpll3, 1, 0, 0),
780 F_SLEW( 375000000, 750000000, gpll3, 1, 0, 0),
781 F_SLEW( 400000000, FIXED_CLK_SRC, gpll0, 2, 0, 0),
782 F_SLEW( 450000000, 900000000, gpll3, 1, 0, 0),
783 F_SLEW( 510000000, 1020000000, gpll3, 1, 0, 0),
784 F_SLEW( 560000000, 1120000000, gpll3, 1, 0, 0),
785 F_SLEW( 650000000, 1300000000, gpll3, 1, 0, 0),
786 F_END
787};
788
Shefali Jain79729af2018-01-29 15:15:20 +0530[diff] [blame]789static struct clk_freq_tbl ftbl_gcc_oxili_gfx3d_clk_8937_475MHz[] = {
790 F_SLEW( 19200000, FIXED_CLK_SRC, xo, 1, 0, 0),
791 F_SLEW( 50000000, FIXED_CLK_SRC, gpll0, 16, 0, 0),
792 F_SLEW( 80000000, FIXED_CLK_SRC, gpll0, 10, 0, 0),
793 F_SLEW( 100000000, FIXED_CLK_SRC, gpll0, 8, 0, 0),
794 F_SLEW( 160000000, FIXED_CLK_SRC, gpll0, 5, 0, 0),
795 F_SLEW( 200000000, FIXED_CLK_SRC, gpll0, 4, 0, 0),
796 F_SLEW( 216000000, FIXED_CLK_SRC, gpll6_aux, 5, 0, 0),
797 F_SLEW( 228570000, FIXED_CLK_SRC, gpll0, 3.5, 0, 0),
798 F_SLEW( 240000000, FIXED_CLK_SRC, gpll6_aux, 4.5, 0, 0),
799 F_SLEW( 266670000, FIXED_CLK_SRC, gpll0, 3, 0, 0),
800 F_SLEW( 300000000, 600000000, gpll3, 1, 0, 0),
801 F_SLEW( 320000000, FIXED_CLK_SRC, gpll0, 2.5, 0, 0),
802 F_SLEW( 375000000, 750000000, gpll3, 1, 0, 0),
803 F_SLEW( 400000000, FIXED_CLK_SRC, gpll0, 2, 0, 0),
804 F_SLEW( 450000000, 900000000, gpll3, 1, 0, 0),
805 F_SLEW( 475000000, 950000000, gpll3, 1, 0, 0),
806 F_END
807};
808
809static struct clk_freq_tbl ftbl_gcc_oxili_gfx3d_clk_8940_500MHz[] = {
810 F_SLEW( 19200000, FIXED_CLK_SRC, xo, 1, 0, 0),
811 F_SLEW( 50000000, FIXED_CLK_SRC, gpll0, 16, 0, 0),
812 F_SLEW( 80000000, FIXED_CLK_SRC, gpll0, 10, 0, 0),
813 F_SLEW( 100000000, FIXED_CLK_SRC, gpll0, 8, 0, 0),
814 F_SLEW( 160000000, FIXED_CLK_SRC, gpll0, 5, 0, 0),
815 F_SLEW( 200000000, FIXED_CLK_SRC, gpll0, 4, 0, 0),
816 F_SLEW( 216000000, FIXED_CLK_SRC, gpll6_aux, 5, 0, 0),
817 F_SLEW( 228570000, FIXED_CLK_SRC, gpll0, 3.5, 0, 0),
818 F_SLEW( 240000000, FIXED_CLK_SRC, gpll6_aux, 4.5, 0, 0),
819 F_SLEW( 266670000, FIXED_CLK_SRC, gpll0, 3, 0, 0),
820 F_SLEW( 300000000, 600000000, gpll3, 1, 0, 0),
821 F_SLEW( 320000000, FIXED_CLK_SRC, gpll0, 2.5, 0, 0),
822 F_SLEW( 375000000, 750000000, gpll3, 1, 0, 0),
823 F_SLEW( 400000000, FIXED_CLK_SRC, gpll0, 2, 0, 0),
824 F_SLEW( 450000000, 900000000, gpll3, 1, 0, 0),
825 F_SLEW( 475000000, 950000000, gpll3, 1, 0, 0),
826 F_SLEW( 500000000, 1000000000, gpll3, 1, 0, 0),
827 F_END
828};
829
830static struct clk_freq_tbl ftbl_gcc_oxili_gfx3d_clk_8917[] = {
831 F_SLEW( 19200000, FIXED_CLK_SRC, xo, 1, 0, 0),
832 F_SLEW( 50000000, FIXED_CLK_SRC, gpll0, 16, 0, 0),
833 F_SLEW( 80000000, FIXED_CLK_SRC, gpll0, 10, 0, 0),
834 F_SLEW( 100000000, FIXED_CLK_SRC, gpll0, 8, 0, 0),
835 F_SLEW( 160000000, FIXED_CLK_SRC, gpll0, 5, 0, 0),
836 F_SLEW( 200000000, FIXED_CLK_SRC, gpll0, 4, 0, 0),
837 F_SLEW( 228570000, FIXED_CLK_SRC, gpll0, 3.5, 0, 0),
838 F_SLEW( 240000000, FIXED_CLK_SRC, gpll6_aux, 4.5, 0, 0),
839 F_SLEW( 266670000, FIXED_CLK_SRC, gpll0, 3, 0, 0),
840 F_SLEW( 270000000, FIXED_CLK_SRC, gpll6_aux, 4, 0, 0),
841 F_SLEW( 320000000, FIXED_CLK_SRC, gpll0, 2.5, 0, 0),
842 F_SLEW( 400000000, FIXED_CLK_SRC, gpll0, 2, 0, 0),
Odelu Kukatla9c000582018-09-25 18:55:09 +0530[diff] [blame^]843 F_SLEW( 465000000, 930000000, gpll3, 1, 0, 0),
Shefali Jain79729af2018-01-29 15:15:20 +0530[diff] [blame]844 F_SLEW( 484800000, 969600000, gpll3, 1, 0, 0),
845 F_SLEW( 523200000, 1046400000, gpll3, 1, 0, 0),
846 F_SLEW( 550000000, 1100000000, gpll3, 1, 0, 0),
847 F_SLEW( 598000000, 1196000000, gpll3, 1, 0, 0),
848 F_END
849};
850
851static struct clk_freq_tbl ftbl_gcc_oxili_gfx3d_clk_8917_650MHz[] = {
852 F_SLEW( 19200000, FIXED_CLK_SRC, xo, 1, 0, 0),
853 F_SLEW( 50000000, FIXED_CLK_SRC, gpll0, 16, 0, 0),
854 F_SLEW( 80000000, FIXED_CLK_SRC, gpll0, 10, 0, 0),
855 F_SLEW( 100000000, FIXED_CLK_SRC, gpll0, 8, 0, 0),
856 F_SLEW( 160000000, FIXED_CLK_SRC, gpll0, 5, 0, 0),
857 F_SLEW( 200000000, FIXED_CLK_SRC, gpll0, 4, 0, 0),
858 F_SLEW( 228570000, FIXED_CLK_SRC, gpll0, 3.5, 0, 0),
859 F_SLEW( 240000000, FIXED_CLK_SRC, gpll6_aux, 4.5, 0, 0),
860 F_SLEW( 266670000, FIXED_CLK_SRC, gpll0, 3, 0, 0),
861 F_SLEW( 270000000, FIXED_CLK_SRC, gpll6_aux, 4, 0, 0),
862 F_SLEW( 320000000, FIXED_CLK_SRC, gpll0, 2.5, 0, 0),
863 F_SLEW( 400000000, FIXED_CLK_SRC, gpll0, 2, 0, 0),
Odelu Kukatla9c000582018-09-25 18:55:09 +0530[diff] [blame^]864 F_SLEW( 465000000, 930000000, gpll3, 1, 0, 0),
Shefali Jain79729af2018-01-29 15:15:20 +0530[diff] [blame]865 F_SLEW( 484800000, 969600000, gpll3, 1, 0, 0),
866 F_SLEW( 523200000, 1046400000, gpll3, 1, 0, 0),
867 F_SLEW( 550000000, 1100000000, gpll3, 1, 0, 0),
868 F_SLEW( 598000000, 1196000000, gpll3, 1, 0, 0),
869 F_SLEW( 650000000, 1300000000, gpll3, 1, 0, 0),
870 F_END
871};
872
873static struct rcg_clk gfx3d_clk_src = {
874 .cmd_rcgr_reg = GFX3D_CMD_RCGR,
875 .set_rate = set_rate_hid,
876 .freq_tbl = ftbl_gcc_oxili_gfx3d_clk,
877 .current_freq = &rcg_dummy_freq,
878 .base = &virt_bases[GCC_BASE],
879 .c = {
880 .dbg_name = "gfx3d_clk_src",
881 .ops = &clk_ops_rcg,
882 VDD_DIG_FMAX_MAP5(LOWER, 240000000, LOW, 400000000,
883 NOMINAL, 465000000, NOM_PLUS, 500000000,
884 HIGH, 550000000),
885 CLK_INIT(gfx3d_clk_src.c),
886 },
887};
888
889static struct clk_freq_tbl ftbl_gcc_blsp1_2_qup1_4_i2c_apps_clk[] = {
890 F( 19200000, xo, 1, 0, 0),
891 F( 50000000, gpll0, 16, 0, 0),
892 F_END
893};
894
895static struct rcg_clk blsp1_qup1_i2c_apps_clk_src = {
896 .cmd_rcgr_reg = BLSP1_QUP1_I2C_APPS_CMD_RCGR,
897 .set_rate = set_rate_hid,
898 .freq_tbl = ftbl_gcc_blsp1_2_qup1_4_i2c_apps_clk,
899 .current_freq = &rcg_dummy_freq,
900 .base = &virt_bases[GCC_BASE],
901 .c = {
902 .dbg_name = "blsp1_qup1_i2c_apps_clk_src",
903 .ops = &clk_ops_rcg,
904 VDD_DIG_FMAX_MAP1(LOWER, 50000000),
905 CLK_INIT(blsp1_qup1_i2c_apps_clk_src.c),
906 },
907};
908
909static struct clk_freq_tbl ftbl_gcc_blsp1_2_qup1_4_spi_apps_clk[] = {
910 F( 960000, xo, 10, 1, 2),
911 F( 4800000, xo, 4, 0, 0),
912 F( 9600000, xo, 2, 0, 0),
913 F( 16000000, gpll0, 10, 1, 5),
914 F( 19200000, xo, 1, 0, 0),
915 F( 25000000, gpll0, 16, 1, 2),
916 F( 50000000, gpll0, 16, 0, 0),
917 F_END
918};
919
920static struct clk_freq_tbl ftbl_gcc_blsp1_2_qup1_4_spi_apps_clk_8917[] = {
921 F( 960000, xo, 10, 1, 2),
922 F( 4800000, xo, 4, 0, 0),
923 F( 9600000, xo, 2, 0, 0),
924 F( 16000000, gpll0, 10, 1, 5),
925 F( 19200000, xo, 1, 0, 0),
926 F( 25000000, gpll0, 16, 1, 2),
927 F( 40000000, gpll0, 10, 1, 2),
928 F( 50000000, gpll0, 16, 0, 0),
929 F_END
930};
931
932static struct rcg_clk blsp1_qup1_spi_apps_clk_src = {
933 .cmd_rcgr_reg = BLSP1_QUP1_SPI_APPS_CMD_RCGR,
934 .set_rate = set_rate_mnd,
935 .freq_tbl = ftbl_gcc_blsp1_2_qup1_4_spi_apps_clk,
936 .current_freq = &rcg_dummy_freq,
937 .base = &virt_bases[GCC_BASE],
938 .c = {
939 .dbg_name = "blsp1_qup1_spi_apps_clk_src",
940 .ops = &clk_ops_rcg_mnd,
941 VDD_DIG_FMAX_MAP2(LOWER, 25000000, NOMINAL, 50000000),
942 CLK_INIT(blsp1_qup1_spi_apps_clk_src.c),
943 },
944};
945
946static struct rcg_clk blsp1_qup2_i2c_apps_clk_src = {
947 .cmd_rcgr_reg = BLSP1_QUP2_I2C_APPS_CMD_RCGR,
948 .set_rate = set_rate_hid,
949 .freq_tbl = ftbl_gcc_blsp1_2_qup1_4_i2c_apps_clk,
950 .current_freq = &rcg_dummy_freq,
951 .base = &virt_bases[GCC_BASE],
952 .c = {
953 .dbg_name = "blsp1_qup2_i2c_apps_clk_src",
954 .ops = &clk_ops_rcg,
955 VDD_DIG_FMAX_MAP1(LOWER, 50000000),
956 CLK_INIT(blsp1_qup2_i2c_apps_clk_src.c),
957 },
958};
959
960static struct rcg_clk blsp1_qup2_spi_apps_clk_src = {
961 .cmd_rcgr_reg = BLSP1_QUP2_SPI_APPS_CMD_RCGR,
962 .set_rate = set_rate_mnd,
963 .freq_tbl = ftbl_gcc_blsp1_2_qup1_4_spi_apps_clk,
964 .current_freq = &rcg_dummy_freq,
965 .base = &virt_bases[GCC_BASE],
966 .c = {
967 .dbg_name = "blsp1_qup2_spi_apps_clk_src",
968 .ops = &clk_ops_rcg_mnd,
969 VDD_DIG_FMAX_MAP2(LOWER, 25000000, NOMINAL, 50000000),
970 CLK_INIT(blsp1_qup2_spi_apps_clk_src.c),
971 },
972};
973
974static struct rcg_clk blsp1_qup3_i2c_apps_clk_src = {
975 .cmd_rcgr_reg = BLSP1_QUP3_I2C_APPS_CMD_RCGR,
976 .set_rate = set_rate_hid,
977 .freq_tbl = ftbl_gcc_blsp1_2_qup1_4_i2c_apps_clk,
978 .current_freq = &rcg_dummy_freq,
979 .base = &virt_bases[GCC_BASE],
980 .c = {
981 .dbg_name = "blsp1_qup3_i2c_apps_clk_src",
982 .ops = &clk_ops_rcg,
983 VDD_DIG_FMAX_MAP1(LOWER, 50000000),
984 CLK_INIT(blsp1_qup3_i2c_apps_clk_src.c),
985 },
986};
987
988static struct rcg_clk blsp1_qup3_spi_apps_clk_src = {
989 .cmd_rcgr_reg = BLSP1_QUP3_SPI_APPS_CMD_RCGR,
990 .set_rate = set_rate_mnd,
991 .freq_tbl = ftbl_gcc_blsp1_2_qup1_4_spi_apps_clk,
992 .current_freq = &rcg_dummy_freq,
993 .base = &virt_bases[GCC_BASE],
994 .c = {
995 .dbg_name = "blsp1_qup3_spi_apps_clk_src",
996 .ops = &clk_ops_rcg_mnd,
997 VDD_DIG_FMAX_MAP2(LOWER, 25000000, NOMINAL, 50000000),
998 CLK_INIT(blsp1_qup3_spi_apps_clk_src.c),
999 },
1000};
1001
1002static struct rcg_clk blsp1_qup4_i2c_apps_clk_src = {
1003 .cmd_rcgr_reg = BLSP1_QUP4_I2C_APPS_CMD_RCGR,
1004 .set_rate = set_rate_hid,
1005 .freq_tbl = ftbl_gcc_blsp1_2_qup1_4_i2c_apps_clk,
1006 .current_freq = &rcg_dummy_freq,
1007 .base = &virt_bases[GCC_BASE],
1008 .c = {
1009 .dbg_name = "blsp1_qup4_i2c_apps_clk_src",
1010 .ops = &clk_ops_rcg,
1011 VDD_DIG_FMAX_MAP1(LOWER, 50000000),
1012 CLK_INIT(blsp1_qup4_i2c_apps_clk_src.c),
1013 },
1014};
1015
1016static struct rcg_clk blsp1_qup4_spi_apps_clk_src = {
1017 .cmd_rcgr_reg = BLSP1_QUP4_SPI_APPS_CMD_RCGR,
1018 .set_rate = set_rate_mnd,
1019 .freq_tbl = ftbl_gcc_blsp1_2_qup1_4_spi_apps_clk,
1020 .current_freq = &rcg_dummy_freq,
1021 .base = &virt_bases[GCC_BASE],
1022 .c = {
1023 .dbg_name = "blsp1_qup4_spi_apps_clk_src",
1024 .ops = &clk_ops_rcg_mnd,
1025 VDD_DIG_FMAX_MAP2(LOWER, 25000000, NOMINAL, 50000000),
1026 CLK_INIT(blsp1_qup4_spi_apps_clk_src.c),
1027 },
1028};
1029
1030static struct clk_freq_tbl ftbl_gcc_blsp1_2_uart1_2_apps_clk[] = {
1031 F( 3686400, gpll0, 1, 72, 15625),
1032 F( 7372800, gpll0, 1, 144, 15625),
1033 F( 14745600, gpll0, 1, 288, 15625),
1034 F( 16000000, gpll0, 10, 1, 5),
1035 F( 19200000, xo, 1, 0, 0),
1036 F( 24000000, gpll0, 1, 3, 100),
1037 F( 25000000, gpll0, 16, 1, 2),
1038 F( 32000000, gpll0, 1, 1, 25),
1039 F( 40000000, gpll0, 1, 1, 20),
1040 F( 46400000, gpll0, 1, 29, 500),
1041 F( 48000000, gpll0, 1, 3, 50),
1042 F( 51200000, gpll0, 1, 8, 125),
1043 F( 56000000, gpll0, 1, 7, 100),
1044 F( 58982400, gpll0, 1, 1152, 15625),
1045 F( 60000000, gpll0, 1, 3, 40),
1046 F( 64000000, gpll0, 1, 2, 25),
1047 F_END
1048};
1049
1050static struct rcg_clk blsp1_uart1_apps_clk_src = {
1051 .cmd_rcgr_reg = BLSP1_UART1_APPS_CMD_RCGR,
1052 .set_rate = set_rate_mnd,
1053 .freq_tbl = ftbl_gcc_blsp1_2_uart1_2_apps_clk,
1054 .current_freq = &rcg_dummy_freq,
1055 .base = &virt_bases[GCC_BASE],
1056 .c = {
1057 .dbg_name = "blsp1_uart1_apps_clk_src",
1058 .ops = &clk_ops_rcg_mnd,
1059 VDD_DIG_FMAX_MAP2(LOWER, 32000000, NOMINAL, 64000000),
1060 CLK_INIT(blsp1_uart1_apps_clk_src.c),
1061 },
1062};
1063
1064static struct rcg_clk blsp1_uart2_apps_clk_src = {
1065 .cmd_rcgr_reg = BLSP1_UART2_APPS_CMD_RCGR,
1066 .set_rate = set_rate_mnd,
1067 .freq_tbl = ftbl_gcc_blsp1_2_uart1_2_apps_clk,
1068 .current_freq = &rcg_dummy_freq,
1069 .base = &virt_bases[GCC_BASE],
1070 .c = {
1071 .dbg_name = "blsp1_uart2_apps_clk_src",
1072 .ops = &clk_ops_rcg_mnd,
1073 VDD_DIG_FMAX_MAP2(LOWER, 32000000, NOMINAL, 64000000),
1074 CLK_INIT(blsp1_uart2_apps_clk_src.c),
1075 },
1076};
1077
1078static struct rcg_clk blsp2_qup1_i2c_apps_clk_src = {
1079 .cmd_rcgr_reg = BLSP2_QUP1_I2C_APPS_CMD_RCGR,
1080 .set_rate = set_rate_hid,
1081 .freq_tbl = ftbl_gcc_blsp1_2_qup1_4_i2c_apps_clk,
1082 .current_freq = &rcg_dummy_freq,
1083 .base = &virt_bases[GCC_BASE],
1084 .c = {
1085 .dbg_name = "blsp2_qup1_i2c_apps_clk_src",
1086 .ops = &clk_ops_rcg,
1087 VDD_DIG_FMAX_MAP1(LOWER, 50000000),
1088 CLK_INIT(blsp2_qup1_i2c_apps_clk_src.c),
1089 },
1090};
1091
1092static struct rcg_clk blsp2_qup1_spi_apps_clk_src = {
1093 .cmd_rcgr_reg = BLSP2_QUP1_SPI_APPS_CMD_RCGR,
1094 .set_rate = set_rate_mnd,
1095 .freq_tbl = ftbl_gcc_blsp1_2_qup1_4_spi_apps_clk,
1096 .current_freq = &rcg_dummy_freq,
1097 .base = &virt_bases[GCC_BASE],
1098 .c = {
1099 .dbg_name = "blsp2_qup1_spi_apps_clk_src",
1100 .ops = &clk_ops_rcg_mnd,
1101 VDD_DIG_FMAX_MAP2(LOWER, 25000000, NOMINAL, 50000000),
1102 CLK_INIT(blsp2_qup1_spi_apps_clk_src.c),
1103 },
1104};
1105
1106static struct rcg_clk blsp2_qup2_i2c_apps_clk_src = {
1107 .cmd_rcgr_reg = BLSP2_QUP2_I2C_APPS_CMD_RCGR,
1108 .set_rate = set_rate_hid,
1109 .freq_tbl = ftbl_gcc_blsp1_2_qup1_4_i2c_apps_clk,
1110 .current_freq = &rcg_dummy_freq,
1111 .base = &virt_bases[GCC_BASE],
1112 .c = {
1113 .dbg_name = "blsp2_qup2_i2c_apps_clk_src",
1114 .ops = &clk_ops_rcg,
1115 VDD_DIG_FMAX_MAP1(LOWER, 50000000),
1116 CLK_INIT(blsp2_qup2_i2c_apps_clk_src.c),
1117 },
1118};
1119
1120static struct rcg_clk blsp2_qup2_spi_apps_clk_src = {
1121 .cmd_rcgr_reg = BLSP2_QUP2_SPI_APPS_CMD_RCGR,
1122 .set_rate = set_rate_mnd,
1123 .freq_tbl = ftbl_gcc_blsp1_2_qup1_4_spi_apps_clk,
1124 .current_freq = &rcg_dummy_freq,
1125 .base = &virt_bases[GCC_BASE],
1126 .c = {
1127 .dbg_name = "blsp2_qup2_spi_apps_clk_src",
1128 .ops = &clk_ops_rcg_mnd,
1129 VDD_DIG_FMAX_MAP2(LOWER, 25000000, NOMINAL, 50000000),
1130 CLK_INIT(blsp2_qup2_spi_apps_clk_src.c),
1131 },
1132};
1133
1134static struct rcg_clk blsp2_qup3_i2c_apps_clk_src = {
1135 .cmd_rcgr_reg = BLSP2_QUP3_I2C_APPS_CMD_RCGR,
1136 .set_rate = set_rate_hid,
1137 .freq_tbl = ftbl_gcc_blsp1_2_qup1_4_i2c_apps_clk,
1138 .current_freq = &rcg_dummy_freq,
1139 .base = &virt_bases[GCC_BASE],
1140 .c = {
1141 .dbg_name = "blsp2_qup3_i2c_apps_clk_src",
1142 .ops = &clk_ops_rcg,
1143 VDD_DIG_FMAX_MAP1(LOWER, 50000000),
1144 CLK_INIT(blsp2_qup3_i2c_apps_clk_src.c),
1145 },
1146};
1147
1148static struct rcg_clk blsp2_qup3_spi_apps_clk_src = {
1149 .cmd_rcgr_reg = BLSP2_QUP3_SPI_APPS_CMD_RCGR,
1150 .set_rate = set_rate_mnd,
1151 .freq_tbl = ftbl_gcc_blsp1_2_qup1_4_spi_apps_clk,
1152 .current_freq = &rcg_dummy_freq,
1153 .base = &virt_bases[GCC_BASE],
1154 .c = {
1155 .dbg_name = "blsp2_qup3_spi_apps_clk_src",
1156 .ops = &clk_ops_rcg_mnd,
1157 VDD_DIG_FMAX_MAP2(LOWER, 25000000, NOMINAL, 50000000),
1158 CLK_INIT(blsp2_qup3_spi_apps_clk_src.c),
1159 },
1160};
1161
1162static struct rcg_clk blsp2_qup4_i2c_apps_clk_src = {
1163 .cmd_rcgr_reg = BLSP2_QUP4_I2C_APPS_CMD_RCGR,
1164 .set_rate = set_rate_hid,
1165 .freq_tbl = ftbl_gcc_blsp1_2_qup1_4_i2c_apps_clk,
1166 .current_freq = &rcg_dummy_freq,
1167 .base = &virt_bases[GCC_BASE],
1168 .c = {
1169 .dbg_name = "blsp2_qup4_i2c_apps_clk_src",
1170 .ops = &clk_ops_rcg,
1171 VDD_DIG_FMAX_MAP1(LOWER, 50000000),
1172 CLK_INIT(blsp2_qup4_i2c_apps_clk_src.c),
1173 },
1174};
1175
1176static struct rcg_clk blsp2_qup4_spi_apps_clk_src = {
1177 .cmd_rcgr_reg = BLSP2_QUP4_SPI_APPS_CMD_RCGR,
1178 .set_rate = set_rate_mnd,
1179 .freq_tbl = ftbl_gcc_blsp1_2_qup1_4_spi_apps_clk,
1180 .current_freq = &rcg_dummy_freq,
1181 .base = &virt_bases[GCC_BASE],
1182 .c = {
1183 .dbg_name = "blsp2_qup4_spi_apps_clk_src",
1184 .ops = &clk_ops_rcg_mnd,
1185 VDD_DIG_FMAX_MAP2(LOWER, 25000000, NOMINAL, 50000000),
1186 CLK_INIT(blsp2_qup4_spi_apps_clk_src.c),
1187 },
1188};
1189
1190static struct rcg_clk blsp2_uart1_apps_clk_src = {
1191 .cmd_rcgr_reg = BLSP2_UART1_APPS_CMD_RCGR,
1192 .set_rate = set_rate_mnd,
1193 .freq_tbl = ftbl_gcc_blsp1_2_uart1_2_apps_clk,
1194 .current_freq = &rcg_dummy_freq,
1195 .base = &virt_bases[GCC_BASE],
1196 .c = {
1197 .dbg_name = "blsp2_uart1_apps_clk_src",
1198 .ops = &clk_ops_rcg_mnd,
1199 VDD_DIG_FMAX_MAP2(LOWER, 32000000, NOMINAL, 64000000),
1200 CLK_INIT(blsp2_uart1_apps_clk_src.c),
1201 },
1202};
1203
1204static struct rcg_clk blsp2_uart2_apps_clk_src = {
1205 .cmd_rcgr_reg = BLSP2_UART2_APPS_CMD_RCGR,
1206 .set_rate = set_rate_mnd,
1207 .freq_tbl = ftbl_gcc_blsp1_2_uart1_2_apps_clk,
1208 .current_freq = &rcg_dummy_freq,
1209 .base = &virt_bases[GCC_BASE],
1210 .c = {
1211 .dbg_name = "blsp2_uart2_apps_clk_src",
1212 .ops = &clk_ops_rcg_mnd,
1213 VDD_DIG_FMAX_MAP2(LOWER, 32000000, NOMINAL, 64000000),
1214 CLK_INIT(blsp2_uart2_apps_clk_src.c),
1215 },
1216};
1217
1218static struct clk_freq_tbl ftbl_gcc_camss_cci_clk[] = {
1219 F( 19200000, xo, 1, 0, 0),
1220 F( 37500000, gpll0_out_aux, 1, 3, 64),
1221 F_END
1222};
1223
1224static struct rcg_clk cci_clk_src = {
1225 .cmd_rcgr_reg = CCI_CMD_RCGR,
1226 .set_rate = set_rate_mnd,
1227 .freq_tbl = ftbl_gcc_camss_cci_clk,
1228 .current_freq = &rcg_dummy_freq,
1229 .base = &virt_bases[GCC_BASE],
1230 .c = {
1231 .dbg_name = "cci_clk_src",
1232 .ops = &clk_ops_rcg_mnd,
1233 VDD_DIG_FMAX_MAP2(LOWER, 19200000, LOW, 37500000),
1234 CLK_INIT(cci_clk_src.c),
1235 },
1236};
1237
1238static struct clk_freq_tbl ftbl_gcc_camss_cpp_clk[] = {
1239 F( 133330000, gpll0, 6, 0, 0),
1240 F( 180000000, gpll6, 6, 0, 0),
1241 F( 266670000, gpll0, 3, 0, 0),
1242 F( 308570000, gpll6, 3.5, 0, 0),
1243 F( 320000000, gpll0, 2.5, 0, 0),
1244 F_END
1245};
1246
1247static struct clk_freq_tbl ftbl_gcc_camss_cpp_clk_8937[] = {
1248 F( 133333333, gpll0, 6, 0, 0),
1249 F( 160000000, gpll0, 5, 0, 0),
1250 F( 200000000, gpll0, 4, 0, 0),
1251 F( 266666667, gpll0, 3, 0, 0),
1252 F( 308570000, gpll6, 3.5, 0, 0),
1253 F( 320000000, gpll0, 2.5, 0, 0),
1254 F( 360000000, gpll6, 3, 0, 0),
1255 F_END
1256};
1257
1258static struct clk_freq_tbl ftbl_gcc_camss_cpp_clk_8917[] = {
1259 F( 133330000, gpll0, 6, 0, 0),
1260 F( 160000000, gpll0, 5, 0, 0),
1261 F( 266670000, gpll0, 3, 0, 0),
1262 F( 308570000, gpll6, 3.5, 0, 0),
1263 F( 320000000, gpll0, 2.5, 0, 0),
1264 F( 360000000, gpll6, 3, 0, 0),
1265 F_END
1266};
1267
1268static struct rcg_clk cpp_clk_src = {
1269 .cmd_rcgr_reg = CPP_CMD_RCGR,
1270 .set_rate = set_rate_hid,
1271 .freq_tbl = ftbl_gcc_camss_cpp_clk,
1272 .current_freq = &rcg_dummy_freq,
1273 .base = &virt_bases[GCC_BASE],
1274 .c = {
1275 .dbg_name = "cpp_clk_src",
1276 .ops = &clk_ops_rcg,
1277 VDD_DIG_FMAX_MAP5(LOWER, 133330000, LOW, 180000000,
1278 NOMINAL, 266670000, NOM_PLUS, 308570000,
1279 HIGH, 320000000),
1280 CLK_INIT(cpp_clk_src.c),
1281 },
1282};
1283
1284static struct clk_freq_tbl ftbl_gcc_camss_gp0_1_clk[] = {
1285 F( 100000000, gpll0, 8, 0, 0),
1286 F( 160000000, gpll0, 5, 0, 0),
1287 F( 200000000, gpll0, 4, 0, 0),
1288 F_END
1289};
1290
1291static struct rcg_clk camss_gp0_clk_src = {
1292 .cmd_rcgr_reg = MM_GP0_CMD_RCGR,
1293 .set_rate = set_rate_mnd,
1294 .freq_tbl = ftbl_gcc_camss_gp0_1_clk,
1295 .current_freq = &rcg_dummy_freq,
1296 .base = &virt_bases[GCC_BASE],
1297 .c = {
1298 .dbg_name = "camss_gp0_clk_src",
1299 .ops = &clk_ops_rcg_mnd,
1300 VDD_DIG_FMAX_MAP3(LOWER, 100000000, LOW, 160000000,
1301 NOMINAL, 200000000),
1302 CLK_INIT(camss_gp0_clk_src.c),
1303 },
1304};
1305
1306static struct rcg_clk camss_gp1_clk_src = {
1307 .cmd_rcgr_reg = MM_GP1_CMD_RCGR,
1308 .set_rate = set_rate_mnd,
1309 .freq_tbl = ftbl_gcc_camss_gp0_1_clk,
1310 .current_freq = &rcg_dummy_freq,
1311 .base = &virt_bases[GCC_BASE],
1312 .c = {
1313 .dbg_name = "camss_gp1_clk_src",
1314 .ops = &clk_ops_rcg_mnd,
1315 VDD_DIG_FMAX_MAP3(LOWER, 100000000, LOW, 160000000,
1316 NOMINAL, 200000000),
1317 CLK_INIT(camss_gp1_clk_src.c),
1318 },
1319};
1320
1321static struct clk_freq_tbl ftbl_gcc_camss_jpeg0_clk[] = {
1322 F( 133330000, gpll0, 6, 0, 0),
1323 F( 266670000, gpll0, 3, 0, 0),
1324 F( 320000000, gpll0, 2.5, 0, 0),
1325 F_END
1326};
1327
1328static struct clk_freq_tbl ftbl_gcc_camss_jpeg0_clk_8937[] = {
1329 F( 133333333, gpll0, 6, 0, 0),
1330 F( 200000000, gpll0, 4, 0, 0),
1331 F( 266666667, gpll0, 3, 0, 0),
1332 F( 308570000, gpll6, 3.5, 0, 0),
1333 F( 320000000, gpll0, 2.5, 0, 0),
1334 F_END
1335};
1336
1337static struct rcg_clk jpeg0_clk_src = {
1338 .cmd_rcgr_reg = JPEG0_CMD_RCGR,
1339 .set_rate = set_rate_hid,
1340 .freq_tbl = ftbl_gcc_camss_jpeg0_clk,
1341 .current_freq = &rcg_dummy_freq,
1342 .base = &virt_bases[GCC_BASE],
1343 .c = {
1344 .dbg_name = "jpeg0_clk_src",
1345 .ops = &clk_ops_rcg,
1346 VDD_DIG_FMAX_MAP3(LOWER, 133330000, NOMINAL, 266670000,
1347 HIGH, 320000000),
1348 CLK_INIT(jpeg0_clk_src.c),
1349 },
1350};
1351
1352static struct clk_freq_tbl ftbl_gcc_camss_mclk0_2_clk[] = {
1353 F( 19200000, xo, 1, 0, 0),
1354 F( 24000000, gpll6, 1, 1, 45),
1355 F( 66670000, gpll0, 12, 0, 0),
1356 F_END
1357};
1358
1359static struct rcg_clk mclk0_clk_src = {
1360 .cmd_rcgr_reg = MCLK0_CMD_RCGR,
1361 .set_rate = set_rate_mnd,
1362 .freq_tbl = ftbl_gcc_camss_mclk0_2_clk,
1363 .current_freq = &rcg_dummy_freq,
1364 .base = &virt_bases[GCC_BASE],
1365 .c = {
1366 .dbg_name = "mclk0_clk_src",
1367 .ops = &clk_ops_rcg_mnd,
1368 VDD_DIG_FMAX_MAP1(LOWER, 66670000),
1369 CLK_INIT(mclk0_clk_src.c),
1370 },
1371};
1372
1373static struct rcg_clk mclk1_clk_src = {
1374 .cmd_rcgr_reg = MCLK1_CMD_RCGR,
1375 .set_rate = set_rate_mnd,
1376 .freq_tbl = ftbl_gcc_camss_mclk0_2_clk,
1377 .current_freq = &rcg_dummy_freq,
1378 .base = &virt_bases[GCC_BASE],
1379 .c = {
1380 .dbg_name = "mclk1_clk_src",
1381 .ops = &clk_ops_rcg_mnd,
1382 VDD_DIG_FMAX_MAP1(LOWER, 66670000),
1383 CLK_INIT(mclk1_clk_src.c),
1384 },
1385};
1386
1387static struct rcg_clk mclk2_clk_src = {
1388 .cmd_rcgr_reg = MCLK2_CMD_RCGR,
1389 .set_rate = set_rate_mnd,
1390 .freq_tbl = ftbl_gcc_camss_mclk0_2_clk,
1391 .current_freq = &rcg_dummy_freq,
1392 .base = &virt_bases[GCC_BASE],
1393 .c = {
1394 .dbg_name = "mclk2_clk_src",
1395 .ops = &clk_ops_rcg_mnd,
1396 VDD_DIG_FMAX_MAP1(LOWER, 66670000),
1397 CLK_INIT(mclk2_clk_src.c),
1398 },
1399};
1400
1401static struct clk_freq_tbl ftbl_gcc_camss_csi0_1phytimer_clk[] = {
1402 F( 100000000, gpll0, 8, 0, 0),
1403 F( 160000000, gpll0, 5, 0, 0),
1404 F( 200000000, gpll0, 4, 0, 0),
1405 F_END
1406};
1407
1408static struct clk_freq_tbl ftbl_gcc_camss_csi0_1phytimer_clk_8917[] = {
1409 F( 100000000, gpll0, 8, 0, 0),
1410 F( 160000000, gpll0, 5, 0, 0),
1411 F( 200000000, gpll0, 4, 0, 0),
1412 F( 266670000, gpll0, 3, 0, 0),
1413 F_END
1414};
1415
1416static struct rcg_clk csi0phytimer_clk_src = {
1417 .cmd_rcgr_reg = CSI0PHYTIMER_CMD_RCGR,
1418 .set_rate = set_rate_hid,
1419 .freq_tbl = ftbl_gcc_camss_csi0_1phytimer_clk,
1420 .current_freq = &rcg_dummy_freq,
1421 .base = &virt_bases[GCC_BASE],
1422 .c = {
1423 .dbg_name = "csi0phytimer_clk_src",
1424 .ops = &clk_ops_rcg,
1425 VDD_DIG_FMAX_MAP3(LOWER, 100000000, LOW, 160000000,
1426 NOMINAL, 200000000),
1427 CLK_INIT(csi0phytimer_clk_src.c),
1428 },
1429};
1430
1431static struct rcg_clk csi1phytimer_clk_src = {
1432 .cmd_rcgr_reg = CSI1PHYTIMER_CMD_RCGR,
1433 .set_rate = set_rate_hid,
1434 .freq_tbl = ftbl_gcc_camss_csi0_1phytimer_clk,
1435 .current_freq = &rcg_dummy_freq,
1436 .base = &virt_bases[GCC_BASE],
1437 .c = {
1438 .dbg_name = "csi1phytimer_clk_src",
1439 .ops = &clk_ops_rcg,
1440 VDD_DIG_FMAX_MAP3(LOWER, 100000000, LOW, 160000000,
1441 NOMINAL, 200000000),
1442 CLK_INIT(csi1phytimer_clk_src.c),
1443 },
1444};
1445
1446static struct clk_freq_tbl ftbl_gcc_crypto_clk[] = {
1447 F( 50000000, gpll0, 16, 0, 0),
1448 F( 80000000, gpll0, 10, 0, 0),
1449 F( 100000000, gpll0, 8, 0, 0),
1450 F( 160000000, gpll0, 5, 0, 0),
1451 F_END
1452};
1453
1454static struct rcg_clk crypto_clk_src = {
1455 .cmd_rcgr_reg = CRYPTO_CMD_RCGR,
1456 .set_rate = set_rate_hid,
1457 .freq_tbl = ftbl_gcc_crypto_clk,
1458 .current_freq = &rcg_dummy_freq,
1459 .base = &virt_bases[GCC_BASE],
1460 .c = {
1461 .dbg_name = "crypto_clk_src",
1462 .ops = &clk_ops_rcg,
1463 VDD_DIG_FMAX_MAP2(LOWER, 80000000, NOMINAL, 160000000),
1464 CLK_INIT(crypto_clk_src.c),
1465 },
1466};
1467
1468static struct clk_freq_tbl ftbl_gcc_gp1_3_clk[] = {
1469 F( 19200000, xo, 1, 0, 0),
1470 F_END
1471};
1472
1473static struct rcg_clk gp1_clk_src = {
1474 .cmd_rcgr_reg = GP1_CMD_RCGR,
1475 .set_rate = set_rate_mnd,
1476 .freq_tbl = ftbl_gcc_gp1_3_clk,
1477 .current_freq = &rcg_dummy_freq,
1478 .base = &virt_bases[GCC_BASE],
1479 .c = {
1480 .dbg_name = "gp1_clk_src",
1481 .ops = &clk_ops_rcg_mnd,
1482 VDD_DIG_FMAX_MAP1(LOWER, 19200000),
1483 CLK_INIT(gp1_clk_src.c),
1484 },
1485};
1486
1487static struct rcg_clk gp2_clk_src = {
1488 .cmd_rcgr_reg = GP2_CMD_RCGR,
1489 .set_rate = set_rate_mnd,
1490 .freq_tbl = ftbl_gcc_gp1_3_clk,
1491 .current_freq = &rcg_dummy_freq,
1492 .base = &virt_bases[GCC_BASE],
1493 .c = {
1494 .dbg_name = "gp2_clk_src",
1495 .ops = &clk_ops_rcg_mnd,
1496 VDD_DIG_FMAX_MAP1(LOW, 19200000),
1497 CLK_INIT(gp2_clk_src.c),
1498 },
1499};
1500
1501static struct rcg_clk gp3_clk_src = {
1502 .cmd_rcgr_reg = GP3_CMD_RCGR,
1503 .set_rate = set_rate_mnd,
1504 .freq_tbl = ftbl_gcc_gp1_3_clk,
1505 .current_freq = &rcg_dummy_freq,
1506 .base = &virt_bases[GCC_BASE],
1507 .c = {
1508 .dbg_name = "gp3_clk_src",
1509 .ops = &clk_ops_rcg_mnd,
1510 VDD_DIG_FMAX_MAP1(LOW, 19200000),
1511 CLK_INIT(gp3_clk_src.c),
1512 },
1513};
1514
1515static struct clk_freq_tbl ftbl_gcc_mdss_byte0_clk[] = {
1516 {
1517 .div_src_val = BVAL(10, 8, dsi0_phypll_source_val)
1518 | BVAL(4, 0, 0),
1519 .src_clk = &ext_byte0_clk_src.c,
1520 .freq_hz = 0,
1521 },
1522 F_END
1523};
1524
1525static struct clk_freq_tbl ftbl_gcc_mdss_byte0_clk_8937[] = {
1526 {
1527 .div_src_val = BVAL(10, 8, xo_source_val)
1528 | BVAL(4, 0, 0),
1529 .src_clk = &xo_clk_src.c,
1530 .freq_hz = 0,
1531 },
1532 {
1533 .div_src_val = BVAL(10, 8, dsi0_0phypll_source_val)
1534 | BVAL(4, 0, 0),
1535 .src_clk = &ext_byte0_clk_src.c,
1536 .freq_hz = 0,
1537 },
1538 {
1539 .div_src_val = BVAL(10, 8, dsi1_0phypll_source_val)
1540 | BVAL(4, 0, 0),
1541 .src_clk = &ext_byte1_clk_src.c,
1542 .freq_hz = 0,
1543 },
1544 F_END
1545};
1546
1547static struct rcg_clk byte0_clk_src = {
1548 .cmd_rcgr_reg = BYTE0_CMD_RCGR,
1549 .set_rate = set_rate_hid,
1550 .current_freq = ftbl_gcc_mdss_byte0_clk,
1551 .freq_tbl = ftbl_gcc_mdss_byte0_clk,
1552 .base = &virt_bases[GCC_BASE],
1553 .c = {
1554 .dbg_name = "byte0_clk_src",
1555 .ops = &clk_ops_byte_multiparent,
1556 .flags = CLKFLAG_NO_RATE_CACHE,
1557 VDD_DIG_FMAX_MAP2(LOWER, 120000000, NOMINAL, 187500000),
1558 CLK_INIT(byte0_clk_src.c),
1559 },
1560};
1561
1562static struct clk_freq_tbl ftbl_gcc_mdss_byte1_clk[] = {
1563 {
1564 .div_src_val = BVAL(10, 8, xo_source_val)
1565 | BVAL(4, 0, 0),
1566 .src_clk = &xo_clk_src.c,
1567 .freq_hz = 0,
1568 },
1569 {
1570 .div_src_val = BVAL(10, 8, dsi1_1phypll_source_val)
1571 | BVAL(4, 0, 0),
1572 .src_clk = &ext_byte1_clk_src.c,
1573 .freq_hz = 0,
1574 },
1575 {
1576 .div_src_val = BVAL(10, 8, dsi0_1phypll_source_val)
1577 | BVAL(4, 0, 0),
1578 .src_clk = &ext_byte0_clk_src.c,
1579 .freq_hz = 0,
1580 },
1581 F_END
1582};
1583
1584static struct rcg_clk byte1_clk_src = {
1585 .cmd_rcgr_reg = BYTE1_CMD_RCGR,
1586 .set_rate = set_rate_hid,
1587 .current_freq = ftbl_gcc_mdss_byte1_clk,
1588 .freq_tbl = ftbl_gcc_mdss_byte1_clk,
1589 .base = &virt_bases[GCC_BASE],
1590 .c = {
1591 .dbg_name = "byte1_clk_src",
1592 .ops = &clk_ops_byte_multiparent,
1593 .flags = CLKFLAG_NO_RATE_CACHE,
1594 VDD_DIG_FMAX_MAP2(LOWER, 125000000, NOMINAL, 187500000),
1595 CLK_INIT(byte1_clk_src.c),
1596 },
1597};
1598
1599static struct clk_freq_tbl ftbl_gcc_mdss_esc0_clk[] = {
1600 F( 19200000, xo, 1, 0, 0),
1601 F_END
1602};
1603
1604static struct rcg_clk esc0_clk_src = {
1605 .cmd_rcgr_reg = ESC0_CMD_RCGR,
1606 .set_rate = set_rate_hid,
1607 .freq_tbl = ftbl_gcc_mdss_esc0_clk,
1608 .current_freq = &rcg_dummy_freq,
1609 .base = &virt_bases[GCC_BASE],
1610 .c = {
1611 .dbg_name = "esc0_clk_src",
1612 .ops = &clk_ops_rcg,
1613 VDD_DIG_FMAX_MAP1(LOWER, 19200000),
1614 CLK_INIT(esc0_clk_src.c),
1615 },
1616};
1617
1618static struct clk_freq_tbl ftbl_esc1_clk_src[] = {
1619 F( 19200000, xo, 1, 0, 0),
1620 F_END
1621};
1622
1623static struct rcg_clk esc1_clk_src = {
1624 .cmd_rcgr_reg = ESC1_CMD_RCGR,
1625 .set_rate = set_rate_hid,
1626 .freq_tbl = ftbl_esc1_clk_src,
1627 .current_freq = &rcg_dummy_freq,
1628 .base = &virt_bases[GCC_BASE],
1629 .c = {
1630 .dbg_name = "esc1_clk_src",
1631 .ops = &clk_ops_rcg,
1632 VDD_DIG_FMAX_MAP1(LOWER, 19200000),
1633 CLK_INIT(esc1_clk_src.c),
1634 },
1635};
1636
1637static struct clk_freq_tbl ftbl_gcc_mdss_mdp_clk[] = {
1638 F( 50000000, gpll0, 16, 0, 0),
1639 F( 80000000, gpll0, 10, 0, 0),
1640 F( 100000000, gpll0, 8, 0, 0),
1641 F( 145450000, gpll0, 5.5, 0, 0),
1642 F( 160000000, gpll0, 5, 0, 0),
1643 F( 177780000, gpll0, 4.5, 0, 0),
1644 F( 200000000, gpll0, 4, 0, 0),
1645 F( 266670000, gpll0, 3, 0, 0),
1646 F( 320000000, gpll0, 2.5, 0, 0),
1647 F_END
1648};
1649
1650static struct rcg_clk mdp_clk_src = {
1651 .cmd_rcgr_reg = MDP_CMD_RCGR,
1652 .set_rate = set_rate_hid,
1653 .freq_tbl = ftbl_gcc_mdss_mdp_clk,
1654 .current_freq = &rcg_dummy_freq,
1655 .base = &virt_bases[GCC_BASE],
1656 .c = {
1657 .dbg_name = "mdp_clk_src",
1658 .ops = &clk_ops_rcg,
1659 VDD_DIG_FMAX_MAP3(LOWER, 160000000, NOMINAL, 266670000,
1660 HIGH, 320000000),
1661 CLK_INIT(mdp_clk_src.c),
1662 },
1663};
1664
1665static struct clk_freq_tbl ftbl_gcc_mdss_pclk0_clk[] = {
1666 {
1667 .div_src_val = BVAL(10, 8, dsi0_phypll_source_val)
1668 | BVAL(4, 0, 0),
1669 .src_clk = &ext_pclk0_clk_src.c,
1670 .freq_hz = 0,
1671 },
1672 F_END
1673};
1674
1675static struct clk_freq_tbl ftbl_gcc_mdss_pclk0_clk_8937[] = {
1676 {
1677 .div_src_val = BVAL(10, 8, xo_source_val)
1678 | BVAL(4, 0, 0),
1679 .src_clk = &xo_clk_src.c,
1680 .freq_hz = 0,
1681 },
1682 {
1683 .div_src_val = BVAL(10, 8, dsi0_0phypll_source_val)
1684 | BVAL(4, 0, 0),
1685 .src_clk = &ext_pclk0_clk_src.c,
1686 .freq_hz = 0,
1687 },
1688 {
1689 .div_src_val = BVAL(10, 8, dsi1_0phypll_source_val)
1690 | BVAL(4, 0, 0),
1691 .src_clk = &ext_pclk1_clk_src.c,
1692 .freq_hz = 0,
1693 },
1694 F_END
1695};
1696
1697static struct rcg_clk pclk0_clk_src = {
1698 .cmd_rcgr_reg = PCLK0_CMD_RCGR,
1699 .set_rate = set_rate_mnd,
1700 .current_freq = ftbl_gcc_mdss_pclk0_clk,
1701 .freq_tbl = ftbl_gcc_mdss_pclk0_clk,
1702 .base = &virt_bases[GCC_BASE],
1703 .c = {
1704 .dbg_name = "pclk0_clk_src",
1705 .ops = &clk_ops_pixel_multiparent,
1706 VDD_DIG_FMAX_MAP2(LOWER, 160000000, NOMINAL, 250000000),
1707 .flags = CLKFLAG_NO_RATE_CACHE,
1708 CLK_INIT(pclk0_clk_src.c),
1709 },
1710};
1711
1712static struct clk_freq_tbl ftbl_gcc_mdss_pclk1_clk[] = {
1713 {
1714 .div_src_val = BVAL(10, 8, xo_source_val)
1715 | BVAL(4, 0, 0),
1716 .src_clk = &xo_clk_src.c,
1717 .freq_hz = 0,
1718 },
1719 {
1720 .div_src_val = BVAL(10, 8, dsi1_1phypll_source_val)
1721 | BVAL(4, 0, 0),
1722 .src_clk = &ext_pclk1_clk_src.c,
1723 .freq_hz = 0,
1724 },
1725 {
1726 .div_src_val = BVAL(10, 8, dsi0_1phypll_source_val)
1727 | BVAL(4, 0, 0),
1728 .src_clk = &ext_pclk0_clk_src.c,
1729 .freq_hz = 0,
1730 },
1731 F_END
1732};
1733
1734static struct rcg_clk pclk1_clk_src = {
1735 .cmd_rcgr_reg = PCLK1_CMD_RCGR,
1736 .set_rate = set_rate_mnd,
1737 .current_freq = ftbl_gcc_mdss_pclk1_clk,
1738 .freq_tbl = ftbl_gcc_mdss_pclk1_clk,
1739 .base = &virt_bases[GCC_BASE],
1740 .c = {
1741 .dbg_name = "pclk1_clk_src",
1742 .ops = &clk_ops_pixel_multiparent,
1743 .flags = CLKFLAG_NO_RATE_CACHE,
1744 VDD_DIG_FMAX_MAP2(LOWER, 166670000, NOMINAL, 250000000),
1745 CLK_INIT(pclk1_clk_src.c),
1746 },
1747};
1748
1749static struct clk_freq_tbl ftbl_gcc_mdss_vsync_clk[] = {
1750 F( 19200000, xo, 1, 0, 0),
1751 F_END
1752};
1753
1754static struct rcg_clk vsync_clk_src = {
1755 .cmd_rcgr_reg = VSYNC_CMD_RCGR,
1756 .set_rate = set_rate_hid,
1757 .freq_tbl = ftbl_gcc_mdss_vsync_clk,
1758 .current_freq = &rcg_dummy_freq,
1759 .base = &virt_bases[GCC_BASE],
1760 .c = {
1761 .dbg_name = "vsync_clk_src",
1762 .ops = &clk_ops_rcg,
1763 VDD_DIG_FMAX_MAP1(LOWER, 19200000),
1764 CLK_INIT(vsync_clk_src.c),
1765 },
1766};
1767
1768static struct clk_freq_tbl ftbl_gcc_pdm2_clk[] = {
1769 F( 64000000, gpll0, 12.5, 0, 0),
1770 F_END
1771};
1772
1773static struct rcg_clk pdm2_clk_src = {
1774 .cmd_rcgr_reg = PDM2_CMD_RCGR,
1775 .set_rate = set_rate_hid,
1776 .freq_tbl = ftbl_gcc_pdm2_clk,
1777 .current_freq = &rcg_dummy_freq,
1778 .base = &virt_bases[GCC_BASE],
1779 .c = {
1780 .dbg_name = "pdm2_clk_src",
1781 .ops = &clk_ops_rcg,
1782 VDD_DIG_FMAX_MAP1(LOWER, 64000000),
1783 CLK_INIT(pdm2_clk_src.c),
1784 },
1785};
1786
1787static struct clk_freq_tbl ftbl_gcc_sdcc1_apps_clk[] = {
1788 F( 144000, xo, 16, 3, 25),
1789 F( 400000, xo, 12, 1, 4),
1790 F( 20000000, gpll0, 10, 1, 4),
1791 F( 25000000, gpll0, 16, 1, 2),
1792 F( 50000000, gpll0, 16, 0, 0),
1793 F( 100000000, gpll0, 8, 0, 0),
1794 F( 177770000, gpll0, 4.5, 0, 0),
1795 F( 192000000, gpll4, 6, 0, 0),
1796 F( 200000000, gpll0, 4, 0, 0),
1797 F( 384000000, gpll4, 3, 0, 0),
1798 F_END
1799};
1800
1801static struct rcg_clk sdcc1_apps_clk_src = {
1802 .cmd_rcgr_reg = SDCC1_APPS_CMD_RCGR,
1803 .set_rate = set_rate_mnd,
1804 .freq_tbl = ftbl_gcc_sdcc1_apps_clk,
1805 .current_freq = &rcg_dummy_freq,
1806 .base = &virt_bases[GCC_BASE],
1807 .c = {
1808 .dbg_name = "sdcc1_apps_clk_src",
1809 .ops = &clk_ops_rcg_mnd,
1810 VDD_DIG_FMAX_MAP2(LOWER, 50000000, NOMINAL, 384000000),
1811 CLK_INIT(sdcc1_apps_clk_src.c),
1812 },
1813};
1814
1815static struct clk_freq_tbl ftbl_gcc_sdcc1_ice_core_clk[] = {
1816 F( 100000000, gpll0_out_main, 8, 0, 0),
1817 F( 200000000, gpll0_out_main, 4, 0, 0),
1818 F_END
1819};
1820
1821static struct rcg_clk sdcc1_ice_core_clk_src = {
1822 .cmd_rcgr_reg = SDCC1_ICE_CORE_CMD_RCGR,
1823 .set_rate = set_rate_mnd,
1824 .freq_tbl = ftbl_gcc_sdcc1_ice_core_clk,
1825 .current_freq = &rcg_dummy_freq,
1826 .base = &virt_bases[GCC_BASE],
1827 .c = {
1828 .dbg_name = "sdcc1_ice_core_clk_src",
1829 .ops = &clk_ops_rcg_mnd,
1830 VDD_DIG_FMAX_MAP2(LOWER, 100000000, NOMINAL, 200000000),
1831 CLK_INIT(sdcc1_ice_core_clk_src.c),
1832 },
1833};
1834
1835static struct clk_freq_tbl ftbl_gcc_sdcc2_apps_clk[] = {
1836 F( 144000, xo, 16, 3, 25),
1837 F( 400000, xo, 12, 1, 4),
1838 F( 20000000, gpll0, 10, 1, 4),
1839 F( 25000000, gpll0, 16, 1, 2),
1840 F( 50000000, gpll0, 16, 0, 0),
1841 F( 100000000, gpll0, 8, 0, 0),
1842 F( 177770000, gpll0, 4.5, 0, 0),
1843 F( 200000000, gpll0, 4, 0, 0),
1844 F_END
1845};
1846
1847static struct rcg_clk sdcc2_apps_clk_src = {
1848 .cmd_rcgr_reg = SDCC2_APPS_CMD_RCGR,
1849 .set_rate = set_rate_mnd,
1850 .freq_tbl = ftbl_gcc_sdcc2_apps_clk,
1851 .current_freq = &rcg_dummy_freq,
1852 .base = &virt_bases[GCC_BASE],
1853 .c = {
1854 .dbg_name = "sdcc2_apps_clk_src",
1855 .ops = &clk_ops_rcg_mnd,
1856 VDD_DIG_FMAX_MAP2(LOWER, 100000000, NOMINAL, 200000000),
1857 CLK_INIT(sdcc2_apps_clk_src.c),
1858 },
1859};
1860
1861static struct clk_freq_tbl ftbl_gcc_usb_fs_ic_clk[] = {
1862 F( 60000000, gpll6_out_main, 9, 1, 2),
1863 F_END
1864};
1865
1866static struct rcg_clk usb_fs_ic_clk_src = {
1867 .cmd_rcgr_reg = USB_FS_IC_CMD_RCGR,
1868 .set_rate = set_rate_mnd,
1869 .freq_tbl = ftbl_gcc_usb_fs_ic_clk,
1870 .current_freq = &rcg_dummy_freq,
1871 .base = &virt_bases[GCC_BASE],
1872 .c = {
1873 .dbg_name = "usb_fs_ic_clk_src",
1874 .ops = &clk_ops_rcg_mnd,
1875 VDD_DIG_FMAX_MAP1(LOWER, 60000000),
1876 CLK_INIT(usb_fs_ic_clk_src.c),
1877 },
1878};
1879
1880static struct clk_freq_tbl ftbl_gcc_usb_fs_system_clk[] = {
1881 F( 64000000, gpll0_out_aux, 12.5, 0, 0),
1882 F_END
1883};
1884
1885static struct rcg_clk usb_fs_system_clk_src = {
1886 .cmd_rcgr_reg = USB_FS_SYSTEM_CMD_RCGR,
1887 .set_rate = set_rate_mnd,
1888 .freq_tbl = ftbl_gcc_usb_fs_system_clk,
1889 .current_freq = &rcg_dummy_freq,
1890 .base = &virt_bases[GCC_BASE],
1891 .c = {
1892 .dbg_name = "usb_fs_system_clk_src",
1893 .ops = &clk_ops_rcg_mnd,
1894 VDD_DIG_FMAX_MAP1(LOWER, 64000000),
1895 CLK_INIT(usb_fs_system_clk_src.c),
1896 },
1897};
1898
1899static struct clk_freq_tbl ftbl_gcc_usb_hs_system_clk[] = {
1900 F( 57140000, gpll0, 14, 0, 0),
1901 F( 100000000, gpll0, 8, 0, 0),
1902 F( 133330000, gpll0, 6, 0, 0),
1903 F( 177780000, gpll0, 4.5, 0, 0),
1904 F_END
1905};
1906
1907static struct clk_freq_tbl ftbl_gcc_usb_hs_system_clk_8917[] = {
1908 F( 80000000, gpll0, 10, 0, 0),
1909 F( 100000000, gpll0, 8, 0, 0),
1910 F( 133330000, gpll0, 6, 0, 0),
1911 F( 177780000, gpll0, 4.5, 0, 0),
1912 F_END
1913};
1914
1915static struct rcg_clk usb_hs_system_clk_src = {
1916 .cmd_rcgr_reg = USB_HS_SYSTEM_CMD_RCGR,
1917 .set_rate = set_rate_hid,
1918 .freq_tbl = ftbl_gcc_usb_hs_system_clk,
1919 .current_freq = &rcg_dummy_freq,
1920 .base = &virt_bases[GCC_BASE],
1921 .c = {
1922 .dbg_name = "usb_hs_system_clk_src",
1923 .ops = &clk_ops_rcg,
1924 VDD_DIG_FMAX_MAP3(LOWER, 57140000, NOMINAL, 133330000,
1925 HIGH, 177780000),
1926 CLK_INIT(usb_hs_system_clk_src.c),
1927 },
1928};
1929
1930static struct branch_clk gcc_bimc_gpu_clk = {
1931 .cbcr_reg = BIMC_GPU_CBCR,
1932 .has_sibling = 1,
1933 .base = &virt_bases[GCC_BASE],
1934 .c = {
1935 .dbg_name = "gcc_bimc_gpu_clk",
1936 .ops = &clk_ops_branch,
1937 CLK_INIT(gcc_bimc_gpu_clk.c),
1938 },
1939};
1940
1941static struct branch_clk gcc_dcc_clk = {
1942 .cbcr_reg = DCC_CBCR,
1943 .has_sibling = 1,
1944 .base = &virt_bases[GCC_BASE],
1945 .c = {
1946 .dbg_name = "gcc_dcc_clk",
1947 .ops = &clk_ops_branch,
1948 CLK_INIT(gcc_dcc_clk.c),
1949 },
1950};
1951
1952static struct local_vote_clk gcc_blsp1_ahb_clk = {
1953 .cbcr_reg = BLSP1_AHB_CBCR,
1954 .vote_reg = APCS_CLOCK_BRANCH_ENA_VOTE,
1955 .en_mask = BIT(10),
1956 .base = &virt_bases[GCC_BASE],
1957 .c = {
1958 .dbg_name = "gcc_blsp1_ahb_clk",
1959 .ops = &clk_ops_vote,
1960 CLK_INIT(gcc_blsp1_ahb_clk.c),
1961 },
1962};
1963
1964static struct branch_clk gcc_blsp1_qup1_i2c_apps_clk = {
1965 .cbcr_reg = BLSP1_QUP1_I2C_APPS_CBCR,
1966 .has_sibling = 0,
1967 .base = &virt_bases[GCC_BASE],
1968 .c = {
1969 .dbg_name = "gcc_blsp1_qup1_i2c_apps_clk",
1970 .parent = &blsp1_qup1_i2c_apps_clk_src.c,
1971 .ops = &clk_ops_branch,
1972 CLK_INIT(gcc_blsp1_qup1_i2c_apps_clk.c),
1973 },
1974};
1975
1976static struct branch_clk gcc_blsp1_qup1_spi_apps_clk = {
1977 .cbcr_reg = BLSP1_QUP1_SPI_APPS_CBCR,
1978 .has_sibling = 0,
1979 .base = &virt_bases[GCC_BASE],
1980 .c = {
1981 .dbg_name = "gcc_blsp1_qup1_spi_apps_clk",
1982 .parent = &blsp1_qup1_spi_apps_clk_src.c,
1983 .ops = &clk_ops_branch,
1984 CLK_INIT(gcc_blsp1_qup1_spi_apps_clk.c),
1985 },
1986};
1987
1988static struct branch_clk gcc_blsp1_qup2_i2c_apps_clk = {
1989 .cbcr_reg = BLSP1_QUP2_I2C_APPS_CBCR,
1990 .has_sibling = 0,
1991 .base = &virt_bases[GCC_BASE],
1992 .c = {
1993 .dbg_name = "gcc_blsp1_qup2_i2c_apps_clk",
1994 .parent = &blsp1_qup2_i2c_apps_clk_src.c,
1995 .ops = &clk_ops_branch,
1996 CLK_INIT(gcc_blsp1_qup2_i2c_apps_clk.c),
1997 },
1998};
1999
2000static struct branch_clk gcc_blsp1_qup2_spi_apps_clk = {
2001 .cbcr_reg = BLSP1_QUP2_SPI_APPS_CBCR,
2002 .has_sibling = 0,
2003 .base = &virt_bases[GCC_BASE],
2004 .c = {
2005 .dbg_name = "gcc_blsp1_qup2_spi_apps_clk",
2006 .parent = &blsp1_qup2_spi_apps_clk_src.c,
2007 .ops = &clk_ops_branch,
2008 CLK_INIT(gcc_blsp1_qup2_spi_apps_clk.c),
2009 },
2010};
2011
2012static struct branch_clk gcc_blsp1_qup3_i2c_apps_clk = {
2013 .cbcr_reg = BLSP1_QUP3_I2C_APPS_CBCR,
2014 .has_sibling = 0,
2015 .base = &virt_bases[GCC_BASE],
2016 .c = {
2017 .dbg_name = "gcc_blsp1_qup3_i2c_apps_clk",
2018 .parent = &blsp1_qup3_i2c_apps_clk_src.c,
2019 .ops = &clk_ops_branch,
2020 CLK_INIT(gcc_blsp1_qup3_i2c_apps_clk.c),
2021 },
2022};
2023
2024static struct branch_clk gcc_blsp1_qup3_spi_apps_clk = {
2025 .cbcr_reg = BLSP1_QUP3_SPI_APPS_CBCR,
2026 .has_sibling = 0,
2027 .base = &virt_bases[GCC_BASE],
2028 .c = {
2029 .dbg_name = "gcc_blsp1_qup3_spi_apps_clk",
2030 .parent = &blsp1_qup3_spi_apps_clk_src.c,
2031 .ops = &clk_ops_branch,
2032 CLK_INIT(gcc_blsp1_qup3_spi_apps_clk.c),
2033 },
2034};
2035
2036static struct branch_clk gcc_blsp1_qup4_i2c_apps_clk = {
2037 .cbcr_reg = BLSP1_QUP4_I2C_APPS_CBCR,
2038 .has_sibling = 0,
2039 .base = &virt_bases[GCC_BASE],
2040 .c = {
2041 .dbg_name = "gcc_blsp1_qup4_i2c_apps_clk",
2042 .parent = &blsp1_qup4_i2c_apps_clk_src.c,
2043 .ops = &clk_ops_branch,
2044 CLK_INIT(gcc_blsp1_qup4_i2c_apps_clk.c),
2045 },
2046};
2047
2048static struct branch_clk gcc_blsp1_qup4_spi_apps_clk = {
2049 .cbcr_reg = BLSP1_QUP4_SPI_APPS_CBCR,
2050 .has_sibling = 0,
2051 .base = &virt_bases[GCC_BASE],
2052 .c = {
2053 .dbg_name = "gcc_blsp1_qup4_spi_apps_clk",
2054 .parent = &blsp1_qup4_spi_apps_clk_src.c,
2055 .ops = &clk_ops_branch,
2056 CLK_INIT(gcc_blsp1_qup4_spi_apps_clk.c),
2057 },
2058};
2059
2060static struct branch_clk gcc_blsp1_uart1_apps_clk = {
2061 .cbcr_reg = BLSP1_UART1_APPS_CBCR,
2062 .has_sibling = 0,
2063 .base = &virt_bases[GCC_BASE],
2064 .c = {
2065 .dbg_name = "gcc_blsp1_uart1_apps_clk",
2066 .parent = &blsp1_uart1_apps_clk_src.c,
2067 .ops = &clk_ops_branch,
2068 CLK_INIT(gcc_blsp1_uart1_apps_clk.c),
2069 },
2070};
2071
2072static struct branch_clk gcc_blsp1_uart2_apps_clk = {
2073 .cbcr_reg = BLSP1_UART2_APPS_CBCR,
2074 .has_sibling = 0,
2075 .base = &virt_bases[GCC_BASE],
2076 .c = {
2077 .dbg_name = "gcc_blsp1_uart2_apps_clk",
2078 .parent = &blsp1_uart2_apps_clk_src.c,
2079 .ops = &clk_ops_branch,
2080 CLK_INIT(gcc_blsp1_uart2_apps_clk.c),
2081 },
2082};
2083
2084static struct local_vote_clk gcc_blsp2_ahb_clk = {
2085 .cbcr_reg = BLSP2_AHB_CBCR,
2086 .vote_reg = APCS_CLOCK_BRANCH_ENA_VOTE,
2087 .en_mask = BIT(20),
2088 .base = &virt_bases[GCC_BASE],
2089 .c = {
2090 .dbg_name = "gcc_blsp2_ahb_clk",
2091 .ops = &clk_ops_vote,
2092 CLK_INIT(gcc_blsp2_ahb_clk.c),
2093 },
2094};
2095
2096static struct branch_clk gcc_blsp2_qup1_i2c_apps_clk = {
2097 .cbcr_reg = BLSP2_QUP1_I2C_APPS_CBCR,
2098 .has_sibling = 0,
2099 .base = &virt_bases[GCC_BASE],
2100 .c = {
2101 .dbg_name = "gcc_blsp2_qup1_i2c_apps_clk",
2102 .parent = &blsp2_qup1_i2c_apps_clk_src.c,
2103 .ops = &clk_ops_branch,
2104 CLK_INIT(gcc_blsp2_qup1_i2c_apps_clk.c),
2105 },
2106};
2107
2108static struct branch_clk gcc_blsp2_qup1_spi_apps_clk = {
2109 .cbcr_reg = BLSP2_QUP1_SPI_APPS_CBCR,
2110 .has_sibling = 0,
2111 .base = &virt_bases[GCC_BASE],
2112 .c = {
2113 .dbg_name = "gcc_blsp2_qup1_spi_apps_clk",
2114 .parent = &blsp2_qup1_spi_apps_clk_src.c,
2115 .ops = &clk_ops_branch,
2116 CLK_INIT(gcc_blsp2_qup1_spi_apps_clk.c),
2117 },
2118};
2119
2120static struct branch_clk gcc_blsp2_qup2_i2c_apps_clk = {
2121 .cbcr_reg = BLSP2_QUP2_I2C_APPS_CBCR,
2122 .has_sibling = 0,
2123 .base = &virt_bases[GCC_BASE],
2124 .c = {
2125 .dbg_name = "gcc_blsp2_qup2_i2c_apps_clk",
2126 .parent = &blsp2_qup2_i2c_apps_clk_src.c,
2127 .ops = &clk_ops_branch,
2128 CLK_INIT(gcc_blsp2_qup2_i2c_apps_clk.c),
2129 },
2130};
2131
2132static struct branch_clk gcc_blsp2_qup2_spi_apps_clk = {
2133 .cbcr_reg = BLSP2_QUP2_SPI_APPS_CBCR,
2134 .has_sibling = 0,
2135 .base = &virt_bases[GCC_BASE],
2136 .c = {
2137 .dbg_name = "gcc_blsp2_qup2_spi_apps_clk",
2138 .parent = &blsp2_qup2_spi_apps_clk_src.c,
2139 .ops = &clk_ops_branch,
2140 CLK_INIT(gcc_blsp2_qup2_spi_apps_clk.c),
2141 },
2142};
2143
2144static struct branch_clk gcc_blsp2_qup3_i2c_apps_clk = {
2145 .cbcr_reg = BLSP2_QUP3_I2C_APPS_CBCR,
2146 .has_sibling = 0,
2147 .base = &virt_bases[GCC_BASE],
2148 .c = {
2149 .dbg_name = "gcc_blsp2_qup3_i2c_apps_clk",
2150 .parent = &blsp2_qup3_i2c_apps_clk_src.c,
2151 .ops = &clk_ops_branch,
2152 CLK_INIT(gcc_blsp2_qup3_i2c_apps_clk.c),
2153 },
2154};
2155
2156static struct branch_clk gcc_blsp2_qup3_spi_apps_clk = {
2157 .cbcr_reg = BLSP2_QUP3_SPI_APPS_CBCR,
2158 .has_sibling = 0,
2159 .base = &virt_bases[GCC_BASE],
2160 .c = {
2161 .dbg_name = "gcc_blsp2_qup3_spi_apps_clk",
2162 .parent = &blsp2_qup3_spi_apps_clk_src.c,
2163 .ops = &clk_ops_branch,
2164 CLK_INIT(gcc_blsp2_qup3_spi_apps_clk.c),
2165 },
2166};
2167
2168static struct branch_clk gcc_blsp2_qup4_i2c_apps_clk = {
2169 .cbcr_reg = BLSP2_QUP4_I2C_APPS_CBCR,
2170 .has_sibling = 0,
2171 .base = &virt_bases[GCC_BASE],
2172 .c = {
2173 .dbg_name = "gcc_blsp2_qup4_i2c_apps_clk",
2174 .parent = &blsp2_qup4_i2c_apps_clk_src.c,
2175 .ops = &clk_ops_branch,
2176 CLK_INIT(gcc_blsp2_qup4_i2c_apps_clk.c),
2177 },
2178};
2179
2180static struct branch_clk gcc_blsp2_qup4_spi_apps_clk = {
2181 .cbcr_reg = BLSP2_QUP4_SPI_APPS_CBCR,
2182 .has_sibling = 0,
2183 .base = &virt_bases[GCC_BASE],
2184 .c = {
2185 .dbg_name = "gcc_blsp2_qup4_spi_apps_clk",
2186 .parent = &blsp2_qup4_spi_apps_clk_src.c,
2187 .ops = &clk_ops_branch,
2188 CLK_INIT(gcc_blsp2_qup4_spi_apps_clk.c),
2189 },
2190};
2191
2192static struct branch_clk gcc_blsp2_uart1_apps_clk = {
2193 .cbcr_reg = BLSP2_UART1_APPS_CBCR,
2194 .has_sibling = 0,
2195 .base = &virt_bases[GCC_BASE],
2196 .c = {
2197 .dbg_name = "gcc_blsp2_uart1_apps_clk",
2198 .parent = &blsp2_uart1_apps_clk_src.c,
2199 .ops = &clk_ops_branch,
2200 CLK_INIT(gcc_blsp2_uart1_apps_clk.c),
2201 },
2202};
2203
2204static struct branch_clk gcc_blsp2_uart2_apps_clk = {
2205 .cbcr_reg = BLSP2_UART2_APPS_CBCR,
2206 .has_sibling = 0,
2207 .base = &virt_bases[GCC_BASE],
2208 .c = {
2209 .dbg_name = "gcc_blsp2_uart2_apps_clk",
2210 .parent = &blsp2_uart2_apps_clk_src.c,
2211 .ops = &clk_ops_branch,
2212 CLK_INIT(gcc_blsp2_uart2_apps_clk.c),
2213 },
2214};
2215
2216static struct local_vote_clk gcc_boot_rom_ahb_clk = {
2217 .cbcr_reg = BOOT_ROM_AHB_CBCR,
2218 .vote_reg = APCS_CLOCK_BRANCH_ENA_VOTE,
2219 .en_mask = BIT(7),
2220 .base = &virt_bases[GCC_BASE],
2221 .c = {
2222 .dbg_name = "gcc_boot_rom_ahb_clk",
2223 .ops = &clk_ops_vote,
2224 CLK_INIT(gcc_boot_rom_ahb_clk.c),
2225 },
2226};
2227
2228static struct branch_clk gcc_camss_cci_ahb_clk = {
2229 .cbcr_reg = CAMSS_CCI_AHB_CBCR,
2230 .has_sibling = 1,
2231 .base = &virt_bases[GCC_BASE],
2232 .c = {
2233 .dbg_name = "gcc_camss_cci_ahb_clk",
2234 .parent = &camss_top_ahb_clk_src.c,
2235 .ops = &clk_ops_branch,
2236 CLK_INIT(gcc_camss_cci_ahb_clk.c),
2237 },
2238};
2239
2240static struct branch_clk gcc_camss_cci_clk = {
2241 .cbcr_reg = CAMSS_CCI_CBCR,
2242 .has_sibling = 0,
2243 .base = &virt_bases[GCC_BASE],
2244 .c = {
2245 .dbg_name = "gcc_camss_cci_clk",
2246 .parent = &cci_clk_src.c,
2247 .ops = &clk_ops_branch,
2248 CLK_INIT(gcc_camss_cci_clk.c),
2249 },
2250};
2251
2252static struct branch_clk gcc_camss_cpp_ahb_clk = {
2253 .cbcr_reg = CAMSS_CPP_AHB_CBCR,
2254 .has_sibling = 1,
2255 .base = &virt_bases[GCC_BASE],
2256 .c = {
2257 .dbg_name = "gcc_camss_cpp_ahb_clk",
2258 .parent = &camss_top_ahb_clk_src.c,
2259 .ops = &clk_ops_branch,
2260 CLK_INIT(gcc_camss_cpp_ahb_clk.c),
2261 },
2262};
2263
2264static struct branch_clk gcc_camss_cpp_axi_clk = {
2265 .cbcr_reg = CAMSS_CPP_AXI_CBCR,
2266 .has_sibling = 1,
2267 .base = &virt_bases[GCC_BASE],
2268 .c = {
2269 .dbg_name = "gcc_camss_cpp_axi_clk",
2270 .ops = &clk_ops_branch,
2271 CLK_INIT(gcc_camss_cpp_axi_clk.c),
2272 },
2273};
2274
2275static struct branch_clk gcc_camss_cpp_clk = {
2276 .cbcr_reg = CAMSS_CPP_CBCR,
2277 .has_sibling = 0,
2278 .base = &virt_bases[GCC_BASE],
2279 .c = {
2280 .dbg_name = "gcc_camss_cpp_clk",
2281 .parent = &cpp_clk_src.c,
2282 .ops = &clk_ops_branch,
2283 CLK_INIT(gcc_camss_cpp_clk.c),
2284 },
2285};
2286
2287static struct branch_clk gcc_camss_csi0_ahb_clk = {
2288 .cbcr_reg = CAMSS_CSI0_AHB_CBCR,
2289 .has_sibling = 1,
2290 .base = &virt_bases[GCC_BASE],
2291 .c = {
2292 .dbg_name = "gcc_camss_csi0_ahb_clk",
2293 .parent = &camss_top_ahb_clk_src.c,
2294 .ops = &clk_ops_branch,
2295 CLK_INIT(gcc_camss_csi0_ahb_clk.c),
2296 },
2297};
2298
2299static struct branch_clk gcc_camss_csi0_clk = {
2300 .cbcr_reg = CAMSS_CSI0_CBCR,
2301 .has_sibling = 1,
2302 .base = &virt_bases[GCC_BASE],
2303 .c = {
2304 .dbg_name = "gcc_camss_csi0_clk",
2305 .parent = &csi0_clk_src.c,
2306 .ops = &clk_ops_branch,
2307 CLK_INIT(gcc_camss_csi0_clk.c),
2308 },
2309};
2310
2311static struct branch_clk gcc_camss_csi0phy_clk = {
2312 .cbcr_reg = CAMSS_CSI0PHY_CBCR,
2313 .has_sibling = 1,
2314 .base = &virt_bases[GCC_BASE],
2315 .c = {
2316 .dbg_name = "gcc_camss_csi0phy_clk",
2317 .parent = &csi0_clk_src.c,
2318 .ops = &clk_ops_branch,
2319 CLK_INIT(gcc_camss_csi0phy_clk.c),
2320 },
2321};
2322
2323static struct branch_clk gcc_camss_csi0pix_clk = {
2324 .cbcr_reg = CAMSS_CSI0PIX_CBCR,
2325 .has_sibling = 1,
2326 .base = &virt_bases[GCC_BASE],
2327 .c = {
2328 .dbg_name = "gcc_camss_csi0pix_clk",
2329 .parent = &csi0_clk_src.c,
2330 .ops = &clk_ops_branch,
2331 CLK_INIT(gcc_camss_csi0pix_clk.c),
2332 },
2333};
2334
2335static struct branch_clk gcc_camss_csi0rdi_clk = {
2336 .cbcr_reg = CAMSS_CSI0RDI_CBCR,
2337 .has_sibling = 1,
2338 .base = &virt_bases[GCC_BASE],
2339 .c = {
2340 .dbg_name = "gcc_camss_csi0rdi_clk",
2341 .parent = &csi0_clk_src.c,
2342 .ops = &clk_ops_branch,
2343 CLK_INIT(gcc_camss_csi0rdi_clk.c),
2344 },
2345};
2346
2347static struct branch_clk gcc_camss_csi1_ahb_clk = {
2348 .cbcr_reg = CAMSS_CSI1_AHB_CBCR,
2349 .has_sibling = 1,
2350 .base = &virt_bases[GCC_BASE],
2351 .c = {
2352 .dbg_name = "gcc_camss_csi1_ahb_clk",
2353 .parent = &camss_top_ahb_clk_src.c,
2354 .ops = &clk_ops_branch,
2355 CLK_INIT(gcc_camss_csi1_ahb_clk.c),
2356 },
2357};
2358
2359static struct branch_clk gcc_camss_csi1_clk = {
2360 .cbcr_reg = CAMSS_CSI1_CBCR,
2361 .has_sibling = 1,
2362 .base = &virt_bases[GCC_BASE],
2363 .c = {
2364 .dbg_name = "gcc_camss_csi1_clk",
2365 .parent = &csi1_clk_src.c,
2366 .ops = &clk_ops_branch,
2367 CLK_INIT(gcc_camss_csi1_clk.c),
2368 },
2369};
2370
2371static struct branch_clk gcc_camss_csi1phy_clk = {
2372 .cbcr_reg = CAMSS_CSI1PHY_CBCR,
2373 .has_sibling = 1,
2374 .base = &virt_bases[GCC_BASE],
2375 .c = {
2376 .dbg_name = "gcc_camss_csi1phy_clk",
2377 .parent = &csi1_clk_src.c,
2378 .ops = &clk_ops_branch,
2379 CLK_INIT(gcc_camss_csi1phy_clk.c),
2380 },
2381};
2382
2383static struct branch_clk gcc_camss_csi1pix_clk = {
2384 .cbcr_reg = CAMSS_CSI1PIX_CBCR,
2385 .has_sibling = 1,
2386 .base = &virt_bases[GCC_BASE],
2387 .c = {
2388 .dbg_name = "gcc_camss_csi1pix_clk",
2389 .parent = &csi1_clk_src.c,
2390 .ops = &clk_ops_branch,
2391 CLK_INIT(gcc_camss_csi1pix_clk.c),
2392 },
2393};
2394
2395static struct branch_clk gcc_camss_csi1rdi_clk = {
2396 .cbcr_reg = CAMSS_CSI1RDI_CBCR,
2397 .has_sibling = 1,
2398 .base = &virt_bases[GCC_BASE],
2399 .c = {
2400 .dbg_name = "gcc_camss_csi1rdi_clk",
2401 .parent = &csi1_clk_src.c,
2402 .ops = &clk_ops_branch,
2403 CLK_INIT(gcc_camss_csi1rdi_clk.c),
2404 },
2405};
2406
2407static struct branch_clk gcc_camss_csi2_ahb_clk = {
2408 .cbcr_reg = CAMSS_CSI2_AHB_CBCR,
2409 .has_sibling = 1,
2410 .base = &virt_bases[GCC_BASE],
2411 .c = {
2412 .dbg_name = "gcc_camss_csi2_ahb_clk",
2413 .parent = &camss_top_ahb_clk_src.c,
2414 .ops = &clk_ops_branch,
2415 CLK_INIT(gcc_camss_csi2_ahb_clk.c),
2416 },
2417};
2418
2419static struct branch_clk gcc_camss_csi2_clk = {
2420 .cbcr_reg = CAMSS_CSI2_CBCR,
2421 .has_sibling = 1,
2422 .base = &virt_bases[GCC_BASE],
2423 .c = {
2424 .dbg_name = "gcc_camss_csi2_clk",
2425 .parent = &csi2_clk_src.c,
2426 .ops = &clk_ops_branch,
2427 CLK_INIT(gcc_camss_csi2_clk.c),
2428 },
2429};
2430
2431static struct branch_clk gcc_camss_csi2phy_clk = {
2432 .cbcr_reg = CAMSS_CSI2PHY_CBCR,
2433 .has_sibling = 1,
2434 .base = &virt_bases[GCC_BASE],
2435 .c = {
2436 .dbg_name = "gcc_camss_csi2phy_clk",
2437 .parent = &csi2_clk_src.c,
2438 .ops = &clk_ops_branch,
2439 CLK_INIT(gcc_camss_csi2phy_clk.c),
2440 },
2441};
2442
2443static struct branch_clk gcc_camss_csi2pix_clk = {
2444 .cbcr_reg = CAMSS_CSI2PIX_CBCR,
2445 .has_sibling = 1,
2446 .base = &virt_bases[GCC_BASE],
2447 .c = {
2448 .dbg_name = "gcc_camss_csi2pix_clk",
2449 .parent = &csi2_clk_src.c,
2450 .ops = &clk_ops_branch,
2451 CLK_INIT(gcc_camss_csi2pix_clk.c),
2452 },
2453};
2454
2455static struct branch_clk gcc_camss_csi2rdi_clk = {
2456 .cbcr_reg = CAMSS_CSI2RDI_CBCR,
2457 .has_sibling = 1,
2458 .base = &virt_bases[GCC_BASE],
2459 .c = {
2460 .dbg_name = "gcc_camss_csi2rdi_clk",
2461 .parent = &csi2_clk_src.c,
2462 .ops = &clk_ops_branch,
2463 CLK_INIT(gcc_camss_csi2rdi_clk.c),
2464 },
2465};
2466
2467static struct branch_clk gcc_camss_csi_vfe0_clk = {
2468 .cbcr_reg = CAMSS_CSI_VFE0_CBCR,
2469 .has_sibling = 1,
2470 .base = &virt_bases[GCC_BASE],
2471 .c = {
2472 .dbg_name = "gcc_camss_csi_vfe0_clk",
2473 .parent = &vfe0_clk_src.c,
2474 .ops = &clk_ops_branch,
2475 CLK_INIT(gcc_camss_csi_vfe0_clk.c),
2476 },
2477};
2478
2479static struct branch_clk gcc_camss_csi_vfe1_clk = {
2480 .cbcr_reg = CAMSS_CSI_VFE1_CBCR,
2481 .has_sibling = 1,
2482 .base = &virt_bases[GCC_BASE],
2483 .c = {
2484 .dbg_name = "gcc_camss_csi_vfe1_clk",
2485 .parent = &vfe1_clk_src.c,
2486 .ops = &clk_ops_branch,
2487 CLK_INIT(gcc_camss_csi_vfe1_clk.c),
2488 },
2489};
2490
2491static struct branch_clk gcc_camss_gp0_clk = {
2492 .cbcr_reg = CAMSS_GP0_CBCR,
2493 .has_sibling = 0,
2494 .base = &virt_bases[GCC_BASE],
2495 .c = {
2496 .dbg_name = "gcc_camss_gp0_clk",
2497 .parent = &camss_gp0_clk_src.c,
2498 .ops = &clk_ops_branch,
2499 CLK_INIT(gcc_camss_gp0_clk.c),
2500 },
2501};
2502
2503static struct branch_clk gcc_camss_gp1_clk = {
2504 .cbcr_reg = CAMSS_GP1_CBCR,
2505 .has_sibling = 0,
2506 .base = &virt_bases[GCC_BASE],
2507 .c = {
2508 .dbg_name = "gcc_camss_gp1_clk",
2509 .parent = &camss_gp1_clk_src.c,
2510 .ops = &clk_ops_branch,
2511 CLK_INIT(gcc_camss_gp1_clk.c),
2512 },
2513};
2514
2515static struct branch_clk gcc_camss_ispif_ahb_clk = {
2516 .cbcr_reg = CAMSS_ISPIF_AHB_CBCR,
2517 .has_sibling = 0,
2518 .base = &virt_bases[GCC_BASE],
2519 .c = {
2520 .dbg_name = "gcc_camss_ispif_ahb_clk",
2521 .parent = &camss_top_ahb_clk_src.c,
2522 .ops = &clk_ops_branch,
2523 CLK_INIT(gcc_camss_ispif_ahb_clk.c),
2524 },
2525};
2526
2527static struct branch_clk gcc_camss_jpeg0_clk = {
2528 .cbcr_reg = CAMSS_JPEG0_CBCR,
2529 .has_sibling = 0,
2530 .base = &virt_bases[GCC_BASE],
2531 .c = {
2532 .dbg_name = "gcc_camss_jpeg0_clk",
2533 .parent = &jpeg0_clk_src.c,
2534 .ops = &clk_ops_branch,
2535 CLK_INIT(gcc_camss_jpeg0_clk.c),
2536 },
2537};
2538
2539static struct branch_clk gcc_camss_jpeg_ahb_clk = {
2540 .cbcr_reg = CAMSS_JPEG_AHB_CBCR,
2541 .has_sibling = 1,
2542 .base = &virt_bases[GCC_BASE],
2543 .c = {
2544 .dbg_name = "gcc_camss_jpeg_ahb_clk",
2545 .parent = &camss_top_ahb_clk_src.c,
2546 .ops = &clk_ops_branch,
2547 CLK_INIT(gcc_camss_jpeg_ahb_clk.c),
2548 },
2549};
2550
2551static struct branch_clk gcc_camss_jpeg_axi_clk = {
2552 .cbcr_reg = CAMSS_JPEG_AXI_CBCR,
2553 .has_sibling = 1,
2554 .base = &virt_bases[GCC_BASE],
2555 .c = {
2556 .dbg_name = "gcc_camss_jpeg_axi_clk",
2557 .ops = &clk_ops_branch,
2558 CLK_INIT(gcc_camss_jpeg_axi_clk.c),
2559 },
2560};
2561
2562static struct branch_clk gcc_camss_mclk0_clk = {
2563 .cbcr_reg = CAMSS_MCLK0_CBCR,
2564 .has_sibling = 0,
2565 .base = &virt_bases[GCC_BASE],
2566 .c = {
2567 .dbg_name = "gcc_camss_mclk0_clk",
2568 .parent = &mclk0_clk_src.c,
2569 .ops = &clk_ops_branch,
2570 CLK_INIT(gcc_camss_mclk0_clk.c),
2571 },
2572};
2573
2574static struct branch_clk gcc_camss_mclk1_clk = {
2575 .cbcr_reg = CAMSS_MCLK1_CBCR,
2576 .has_sibling = 0,
2577 .base = &virt_bases[GCC_BASE],
2578 .c = {
2579 .dbg_name = "gcc_camss_mclk1_clk",
2580 .parent = &mclk1_clk_src.c,
2581 .ops = &clk_ops_branch,
2582 CLK_INIT(gcc_camss_mclk1_clk.c),
2583 },
2584};
2585
2586static struct branch_clk gcc_camss_mclk2_clk = {
2587 .cbcr_reg = CAMSS_MCLK2_CBCR,
2588 .has_sibling = 0,
2589 .base = &virt_bases[GCC_BASE],
2590 .c = {
2591 .dbg_name = "gcc_camss_mclk2_clk",
2592 .parent = &mclk2_clk_src.c,
2593 .ops = &clk_ops_branch,
2594 CLK_INIT(gcc_camss_mclk2_clk.c),
2595 },
2596};
2597
2598static struct branch_clk gcc_camss_micro_ahb_clk = {
2599 .cbcr_reg = CAMSS_MICRO_AHB_CBCR,
2600 .bcr_reg = CAMSS_MICRO_BCR,
2601 .has_sibling = 1,
2602 .base = &virt_bases[GCC_BASE],
2603 .c = {
2604 .dbg_name = "gcc_camss_micro_ahb_clk",
2605 .parent = &camss_top_ahb_clk_src.c,
2606 .ops = &clk_ops_branch,
2607 CLK_INIT(gcc_camss_micro_ahb_clk.c),
2608 },
2609};
2610
2611static struct branch_clk gcc_camss_csi0phytimer_clk = {
2612 .cbcr_reg = CAMSS_CSI0PHYTIMER_CBCR,
2613 .has_sibling = 0,
2614 .base = &virt_bases[GCC_BASE],
2615 .c = {
2616 .dbg_name = "gcc_camss_csi0phytimer_clk",
2617 .parent = &csi0phytimer_clk_src.c,
2618 .ops = &clk_ops_branch,
2619 CLK_INIT(gcc_camss_csi0phytimer_clk.c),
2620 },
2621};
2622
2623static struct branch_clk gcc_camss_csi1phytimer_clk = {
2624 .cbcr_reg = CAMSS_CSI1PHYTIMER_CBCR,
2625 .has_sibling = 0,
2626 .base = &virt_bases[GCC_BASE],
2627 .c = {
2628 .dbg_name = "gcc_camss_csi1phytimer_clk",
2629 .parent = &csi1phytimer_clk_src.c,
2630 .ops = &clk_ops_branch,
2631 CLK_INIT(gcc_camss_csi1phytimer_clk.c),
2632 },
2633};
2634
2635static struct branch_clk gcc_camss_ahb_clk = {
2636 .cbcr_reg = CAMSS_AHB_CBCR,
2637 .has_sibling = 1,
2638 .base = &virt_bases[GCC_BASE],
2639 .c = {
2640 .dbg_name = "gcc_camss_ahb_clk",
2641 .ops = &clk_ops_branch,
2642 CLK_INIT(gcc_camss_ahb_clk.c),
2643 },
2644};
2645
2646static struct branch_clk gcc_camss_top_ahb_clk = {
2647 .cbcr_reg = CAMSS_TOP_AHB_CBCR,
2648 .has_sibling = 1,
2649 .base = &virt_bases[GCC_BASE],
2650 .c = {
2651 .dbg_name = "gcc_camss_top_ahb_clk",
2652 .parent = &camss_top_ahb_clk_src.c,
2653 .ops = &clk_ops_branch,
2654 CLK_INIT(gcc_camss_top_ahb_clk.c),
2655 },
2656};
2657
2658static struct branch_clk gcc_camss_vfe0_clk = {
2659 .cbcr_reg = CAMSS_VFE0_CBCR,
2660 .has_sibling = 1,
2661 .base = &virt_bases[GCC_BASE],
2662 .c = {
2663 .dbg_name = "gcc_camss_vfe0_clk",
2664 .parent = &vfe0_clk_src.c,
2665 .ops = &clk_ops_branch,
2666 CLK_INIT(gcc_camss_vfe0_clk.c),
2667 },
2668};
2669
2670static struct branch_clk gcc_camss_vfe_ahb_clk = {
2671 .cbcr_reg = CAMSS_VFE_AHB_CBCR,
2672 .has_sibling = 1,
2673 .base = &virt_bases[GCC_BASE],
2674 .c = {
2675 .dbg_name = "gcc_camss_vfe_ahb_clk",
2676 .ops = &clk_ops_branch,
2677 CLK_INIT(gcc_camss_vfe_ahb_clk.c),
2678 },
2679};
2680
2681static struct branch_clk gcc_camss_vfe_axi_clk = {
2682 .cbcr_reg = CAMSS_VFE_AXI_CBCR,
2683 .has_sibling = 1,
2684 .base = &virt_bases[GCC_BASE],
2685 .c = {
2686 .dbg_name = "gcc_camss_vfe_axi_clk",
2687 .ops = &clk_ops_branch,
2688 CLK_INIT(gcc_camss_vfe_axi_clk.c),
2689 },
2690};
2691
2692static struct branch_clk gcc_camss_vfe1_ahb_clk = {
2693 .cbcr_reg = CAMSS_VFE1_AHB_CBCR,
2694 .has_sibling = 1,
2695 .base = &virt_bases[GCC_BASE],
2696 .c = {
2697 .dbg_name = "gcc_camss_vfe1_ahb_clk",
2698 .parent = &camss_top_ahb_clk_src.c,
2699 .ops = &clk_ops_branch,
2700 CLK_INIT(gcc_camss_vfe1_ahb_clk.c),
2701 },
2702};
2703
2704static struct branch_clk gcc_camss_vfe1_axi_clk = {
2705 .cbcr_reg = CAMSS_VFE1_AXI_CBCR,
2706 .has_sibling = 1,
2707 .base = &virt_bases[GCC_BASE],
2708 .c = {
2709 .dbg_name = "gcc_camss_vfe1_axi_clk",
2710 .ops = &clk_ops_branch,
2711 CLK_INIT(gcc_camss_vfe1_axi_clk.c),
2712 },
2713};
2714
2715static struct branch_clk gcc_camss_vfe1_clk = {
2716 .cbcr_reg = CAMSS_VFE1_CBCR,
2717 .has_sibling = 1,
2718 .base = &virt_bases[GCC_BASE],
2719 .c = {
2720 .dbg_name = "gcc_camss_vfe1_clk",
2721 .parent = &vfe1_clk_src.c,
2722 .ops = &clk_ops_branch,
2723 CLK_INIT(gcc_camss_vfe1_clk.c),
2724 },
2725};
2726
2727static struct local_vote_clk gcc_crypto_ahb_clk = {
2728 .cbcr_reg = CRYPTO_AHB_CBCR,
2729 .vote_reg = APCS_CLOCK_BRANCH_ENA_VOTE,
2730 .en_mask = BIT(0),
2731 .base = &virt_bases[GCC_BASE],
2732 .c = {
2733 .dbg_name = "gcc_crypto_ahb_clk",
2734 .parent = &crypto_clk_src.c,
2735 .ops = &clk_ops_vote,
2736 CLK_INIT(gcc_crypto_ahb_clk.c),
2737 },
2738};
2739
2740static struct local_vote_clk gcc_crypto_axi_clk = {
2741 .cbcr_reg = CRYPTO_AXI_CBCR,
2742 .vote_reg = APCS_CLOCK_BRANCH_ENA_VOTE,
2743 .en_mask = BIT(1),
2744 .base = &virt_bases[GCC_BASE],
2745 .c = {
2746 .dbg_name = "gcc_crypto_axi_clk",
2747 .ops = &clk_ops_vote,
2748 CLK_INIT(gcc_crypto_axi_clk.c),
2749 },
2750};
2751
2752static struct local_vote_clk gcc_crypto_clk = {
2753 .cbcr_reg = CRYPTO_CBCR,
2754 .vote_reg = APCS_CLOCK_BRANCH_ENA_VOTE,
2755 .en_mask = BIT(2),
2756 .base = &virt_bases[GCC_BASE],
2757 .c = {
2758 .dbg_name = "gcc_crypto_clk",
2759 .parent = &crypto_clk_src.c,
2760 .ops = &clk_ops_vote,
2761 CLK_INIT(gcc_crypto_clk.c),
2762 },
2763};
2764
2765static struct gate_clk gcc_oxili_gmem_clk = {
2766 .en_reg = OXILI_GMEM_CBCR,
2767 .en_mask = BIT(0),
2768 .delay_us = 50,
2769 .base = &virt_bases[GCC_BASE],
2770 .c = {
2771 .dbg_name = "gcc_oxili_gmem_clk",
2772 .parent = &gfx3d_clk_src.c,
2773 .ops = &clk_ops_gate,
2774 CLK_INIT(gcc_oxili_gmem_clk.c),
2775 },
2776};
2777
2778static struct branch_clk gcc_gp1_clk = {
2779 .cbcr_reg = GP1_CBCR,
2780 .has_sibling = 0,
2781 .base = &virt_bases[GCC_BASE],
2782 .c = {
2783 .dbg_name = "gcc_gp1_clk",
2784 .parent = &gp1_clk_src.c,
2785 .ops = &clk_ops_branch,
2786 CLK_INIT(gcc_gp1_clk.c),
2787 },
2788};
2789
2790static struct branch_clk gcc_gp2_clk = {
2791 .cbcr_reg = GP2_CBCR,
2792 .has_sibling = 0,
2793 .base = &virt_bases[GCC_BASE],
2794 .c = {
2795 .dbg_name = "gcc_gp2_clk",
2796 .parent = &gp2_clk_src.c,
2797 .ops = &clk_ops_branch,
2798 CLK_INIT(gcc_gp2_clk.c),
2799 },
2800};
2801
2802static struct branch_clk gcc_gp3_clk = {
2803 .cbcr_reg = GP3_CBCR,
2804 .has_sibling = 0,
2805 .base = &virt_bases[GCC_BASE],
2806 .c = {
2807 .dbg_name = "gcc_gp3_clk",
2808 .parent = &gp3_clk_src.c,
2809 .ops = &clk_ops_branch,
2810 CLK_INIT(gcc_gp3_clk.c),
2811 },
2812};
2813
2814static struct branch_clk gcc_mdss_ahb_clk = {
2815 .cbcr_reg = MDSS_AHB_CBCR,
2816 .has_sibling = 1,
2817 .base = &virt_bases[GCC_BASE],
2818 .c = {
2819 .dbg_name = "gcc_mdss_ahb_clk",
2820 .ops = &clk_ops_branch,
2821 CLK_INIT(gcc_mdss_ahb_clk.c),
2822 },
2823};
2824
2825static struct branch_clk gcc_mdss_axi_clk = {
2826 .cbcr_reg = MDSS_AXI_CBCR,
2827 .has_sibling = 1,
2828 .base = &virt_bases[GCC_BASE],
2829 .c = {
2830 .dbg_name = "gcc_mdss_axi_clk",
2831 .ops = &clk_ops_branch,
2832 CLK_INIT(gcc_mdss_axi_clk.c),
2833 },
2834};
2835
2836static struct branch_clk gcc_mdss_byte0_clk = {
2837 .cbcr_reg = MDSS_BYTE0_CBCR,
2838 .has_sibling = 0,
2839 .base = &virt_bases[GCC_BASE],
2840 .c = {
2841 .dbg_name = "gcc_mdss_byte0_clk",
2842 .parent = &byte0_clk_src.c,
2843 .ops = &clk_ops_branch,
2844 .flags = CLKFLAG_NO_RATE_CACHE,
2845 CLK_INIT(gcc_mdss_byte0_clk.c),
2846 },
2847};
2848
2849static struct branch_clk gcc_mdss_byte1_clk = {
2850 .cbcr_reg = MDSS_BYTE1_CBCR,
2851 .has_sibling = 0,
2852 .base = &virt_bases[GCC_BASE],
2853 .c = {
2854 .dbg_name = "gcc_mdss_byte1_clk",
2855 .parent = &byte1_clk_src.c,
2856 .ops = &clk_ops_branch,
2857 .flags = CLKFLAG_NO_RATE_CACHE,
2858 CLK_INIT(gcc_mdss_byte1_clk.c),
2859 },
2860};
2861
2862static struct branch_clk gcc_mdss_esc0_clk = {
2863 .cbcr_reg = MDSS_ESC0_CBCR,
2864 .has_sibling = 0,
2865 .base = &virt_bases[GCC_BASE],
2866 .c = {
2867 .dbg_name = "gcc_mdss_esc0_clk",
2868 .parent = &esc0_clk_src.c,
2869 .ops = &clk_ops_branch,
2870 CLK_INIT(gcc_mdss_esc0_clk.c),
2871 },
2872};
2873
2874static struct branch_clk gcc_mdss_esc1_clk = {
2875 .cbcr_reg = MDSS_ESC1_CBCR,
2876 .has_sibling = 0,
2877 .base = &virt_bases[GCC_BASE],
2878 .c = {
2879 .dbg_name = "gcc_mdss_esc1_clk",
2880 .parent = &esc1_clk_src.c,
2881 .ops = &clk_ops_branch,
2882 CLK_INIT(gcc_mdss_esc1_clk.c),
2883 },
2884};
2885
2886static struct branch_clk gcc_mdss_mdp_clk = {
2887 .cbcr_reg = MDSS_MDP_CBCR,
2888 .has_sibling = 0,
2889 .base = &virt_bases[GCC_BASE],
2890 .c = {
2891 .dbg_name = "gcc_mdss_mdp_clk",
2892 .parent = &mdp_clk_src.c,
2893 .ops = &clk_ops_branch,
2894 CLK_INIT(gcc_mdss_mdp_clk.c),
2895 },
2896};
2897
2898static DEFINE_CLK_VOTER(mdss_mdp_vote_clk, &gcc_mdss_mdp_clk.c, 0);
2899static DEFINE_CLK_VOTER(mdss_rotator_vote_clk, &gcc_mdss_mdp_clk.c, 0);
2900
2901static struct branch_clk gcc_mdss_pclk0_clk = {
2902 .cbcr_reg = MDSS_PCLK0_CBCR,
2903 .has_sibling = 0,
2904 .base = &virt_bases[GCC_BASE],
2905 .c = {
2906 .dbg_name = "gcc_mdss_pclk0_clk",
2907 .parent = &pclk0_clk_src.c,
2908 .ops = &clk_ops_branch,
2909 .flags = CLKFLAG_NO_RATE_CACHE,
2910 CLK_INIT(gcc_mdss_pclk0_clk.c),
2911 },
2912};
2913
2914static struct branch_clk gcc_mdss_pclk1_clk = {
2915 .cbcr_reg = MDSS_PCLK1_CBCR,
2916 .has_sibling = 0,
2917 .base = &virt_bases[GCC_BASE],
2918 .c = {
2919 .dbg_name = "gcc_mdss_pclk1_clk",
2920 .parent = &pclk1_clk_src.c,
2921 .ops = &clk_ops_branch,
2922 .flags = CLKFLAG_NO_RATE_CACHE,
2923 CLK_INIT(gcc_mdss_pclk1_clk.c),
2924 },
2925};
2926
2927static struct branch_clk gcc_mdss_vsync_clk = {
2928 .cbcr_reg = MDSS_VSYNC_CBCR,
2929 .has_sibling = 0,
2930 .base = &virt_bases[GCC_BASE],
2931 .c = {
2932 .dbg_name = "gcc_mdss_vsync_clk",
2933 .parent = &vsync_clk_src.c,
2934 .ops = &clk_ops_branch,
2935 CLK_INIT(gcc_mdss_vsync_clk.c),
2936 },
2937};
2938
2939static struct branch_clk gcc_mss_cfg_ahb_clk = {
2940 .cbcr_reg = MSS_CFG_AHB_CBCR,
2941 .has_sibling = 1,
2942 .base = &virt_bases[GCC_BASE],
2943 .c = {
2944 .dbg_name = "gcc_mss_cfg_ahb_clk",
2945 .ops = &clk_ops_branch,
2946 CLK_INIT(gcc_mss_cfg_ahb_clk.c),
2947 },
2948};
2949
2950static struct branch_clk gcc_mss_q6_bimc_axi_clk = {
2951 .cbcr_reg = MSS_Q6_BIMC_AXI_CBCR,
2952 .has_sibling = 1,
2953 .base = &virt_bases[GCC_BASE],
2954 .c = {
2955 .dbg_name = "gcc_mss_q6_bimc_axi_clk",
2956 .ops = &clk_ops_branch,
2957 CLK_INIT(gcc_mss_q6_bimc_axi_clk.c),
2958 },
2959};
2960
2961static struct local_vote_clk gcc_apss_tcu_clk;
2962static struct branch_clk gcc_bimc_gfx_clk = {
2963 .cbcr_reg = BIMC_GFX_CBCR,
2964 .has_sibling = 1,
2965 .base = &virt_bases[GCC_BASE],
2966 .c = {
2967 .dbg_name = "gcc_bimc_gfx_clk",
2968 .ops = &clk_ops_branch,
2969 CLK_INIT(gcc_bimc_gfx_clk.c),
2970 .depends = &gcc_apss_tcu_clk.c,
2971 },
2972};
2973
2974static struct branch_clk gcc_oxili_ahb_clk = {
2975 .cbcr_reg = OXILI_AHB_CBCR,
2976 .has_sibling = 1,
2977 .base = &virt_bases[GCC_BASE],
2978 .c = {
2979 .dbg_name = "gcc_oxili_ahb_clk",
2980 .ops = &clk_ops_branch,
2981 CLK_INIT(gcc_oxili_ahb_clk.c),
2982 },
2983};
2984
2985static struct branch_clk gcc_oxili_gfx3d_clk = {
2986 .cbcr_reg = OXILI_GFX3D_CBCR,
2987 .has_sibling = 0,
2988 .base = &virt_bases[GCC_BASE],
2989 .c = {
2990 .dbg_name = "gcc_oxili_gfx3d_clk",
2991 .parent = &gfx3d_clk_src.c,
2992 .ops = &clk_ops_branch,
2993 CLK_INIT(gcc_oxili_gfx3d_clk.c),
2994 },
2995};
2996
2997static struct branch_clk gcc_oxili_timer_clk = {
2998 .cbcr_reg = OXILI_TIMER_CBCR,
2999 .has_sibling = 0,
3000 .base = &virt_bases[GCC_BASE],
3001 .c = {
3002 .dbg_name = "gcc_oxili_timer_clk",
3003 .parent = &xo_clk_src.c,
3004 .ops = &clk_ops_branch,
3005 CLK_INIT(gcc_oxili_timer_clk.c),
3006 },
3007};
3008
3009static struct branch_clk gcc_oxili_aon_clk = {
3010 .cbcr_reg = OXILI_AON_CBCR,
3011 .has_sibling = 0,
3012 .base = &virt_bases[GCC_BASE],
3013 .c = {
3014 .dbg_name = "gcc_oxili_aon_clk",
3015 .parent = &gfx3d_clk_src.c,
3016 .ops = &clk_ops_branch,
3017 CLK_INIT(gcc_oxili_aon_clk.c),
3018 },
3019};
3020
3021static struct branch_clk gcc_pdm2_clk = {
3022 .cbcr_reg = PDM2_CBCR,
3023 .has_sibling = 0,
3024 .base = &virt_bases[GCC_BASE],
3025 .c = {
3026 .dbg_name = "gcc_pdm2_clk",
3027 .parent = &pdm2_clk_src.c,
3028 .ops = &clk_ops_branch,
3029 CLK_INIT(gcc_pdm2_clk.c),
3030 },
3031};
3032
3033static struct branch_clk gcc_pdm_ahb_clk = {
3034 .cbcr_reg = PDM_AHB_CBCR,
3035 .has_sibling = 1,
3036 .base = &virt_bases[GCC_BASE],
3037 .c = {
3038 .dbg_name = "gcc_pdm_ahb_clk",
3039 .ops = &clk_ops_branch,
3040 CLK_INIT(gcc_pdm_ahb_clk.c),
3041 },
3042};
3043
3044static struct local_vote_clk gcc_prng_ahb_clk = {
3045 .cbcr_reg = PRNG_AHB_CBCR,
3046 .vote_reg = APCS_CLOCK_BRANCH_ENA_VOTE,
3047 .en_mask = BIT(8),
3048 .base = &virt_bases[GCC_BASE],
3049 .c = {
3050 .dbg_name = "gcc_prng_ahb_clk",
3051 .ops = &clk_ops_vote,
3052 CLK_INIT(gcc_prng_ahb_clk.c),
3053 },
3054};
3055
3056static struct local_vote_clk gcc_qdss_dap_clk = {
3057 .cbcr_reg = QDSS_DAP_CBCR,
3058 .vote_reg = APCS_CLOCK_BRANCH_ENA_VOTE,
3059 .en_mask = BIT(21),
3060 .base = &virt_bases[GCC_BASE],
3061 .c = {
3062 .dbg_name = "gcc_qdss_dap_clk",
3063 .ops = &clk_ops_vote,
3064 CLK_INIT(gcc_qdss_dap_clk.c),
3065 },
3066};
3067
3068static struct branch_clk gcc_sdcc1_ahb_clk = {
3069 .cbcr_reg = SDCC1_AHB_CBCR,
3070 .has_sibling = 1,
3071 .base = &virt_bases[GCC_BASE],
3072 .c = {
3073 .dbg_name = "gcc_sdcc1_ahb_clk",
3074 .ops = &clk_ops_branch,
3075 CLK_INIT(gcc_sdcc1_ahb_clk.c),
3076 },
3077};
3078
3079static struct branch_clk gcc_sdcc1_apps_clk = {
3080 .cbcr_reg = SDCC1_APPS_CBCR,
3081 .has_sibling = 0,
3082 .base = &virt_bases[GCC_BASE],
3083 .c = {
3084 .dbg_name = "gcc_sdcc1_apps_clk",
3085 .parent = &sdcc1_apps_clk_src.c,
3086 .ops = &clk_ops_branch,
3087 CLK_INIT(gcc_sdcc1_apps_clk.c),
3088 },
3089};
3090
3091static struct branch_clk gcc_sdcc1_ice_core_clk = {
3092 .cbcr_reg = SDCC1_ICE_CORE_CBCR,
3093 .has_sibling = 0,
3094 .base = &virt_bases[GCC_BASE],
3095 .c = {
3096 .dbg_name = "gcc_sdcc1_ice_core_clk",
3097 .parent = &sdcc1_ice_core_clk_src.c,
3098 .ops = &clk_ops_branch,
3099 CLK_INIT(gcc_sdcc1_ice_core_clk.c),
3100 }
3101};
3102
3103static struct branch_clk gcc_sdcc2_ahb_clk = {
3104 .cbcr_reg = SDCC2_AHB_CBCR,
3105 .has_sibling = 1,
3106 .base = &virt_bases[GCC_BASE],
3107 .c = {
3108 .dbg_name = "gcc_sdcc2_ahb_clk",
3109 .ops = &clk_ops_branch,
3110 CLK_INIT(gcc_sdcc2_ahb_clk.c),
3111 },
3112};
3113
3114static struct branch_clk gcc_sdcc2_apps_clk = {
3115 .cbcr_reg = SDCC2_APPS_CBCR,
3116 .has_sibling = 0,
3117 .base = &virt_bases[GCC_BASE],
3118 .c = {
3119 .dbg_name = "gcc_sdcc2_apps_clk",
3120 .parent = &sdcc2_apps_clk_src.c,
3121 .ops = &clk_ops_branch,
3122 CLK_INIT(gcc_sdcc2_apps_clk.c),
3123 },
3124};
3125
3126static struct local_vote_clk gcc_cpp_tbu_clk = {
3127 .cbcr_reg = CPP_TBU_CBCR,
3128 .vote_reg = APCS_SMMU_CLOCK_BRANCH_ENA_VOTE,
3129 .en_mask = BIT(14),
3130 .base = &virt_bases[GCC_BASE],
3131 .c = {
3132 .dbg_name = "gcc_cpp_tbu_clk",
3133 .ops = &clk_ops_vote,
3134 CLK_INIT(gcc_cpp_tbu_clk.c),
3135 },
3136};
3137
3138static struct local_vote_clk gcc_gfx_tbu_clk = {
3139 .cbcr_reg = GFX_TBU_CBCR,
3140 .vote_reg = APCS_SMMU_CLOCK_BRANCH_ENA_VOTE,
3141 .en_mask = BIT(3),
3142 .base = &virt_bases[GCC_BASE],
3143 .c = {
3144 .dbg_name = "gcc_gfx_tbu_clk",
3145 .ops = &clk_ops_vote,
3146 CLK_INIT(gcc_gfx_tbu_clk.c),
3147 },
3148};
3149
3150static struct local_vote_clk gcc_gfx_tcu_clk = {
3151 .cbcr_reg = GFX_TCU_CBCR,
3152 .vote_reg = APCS_SMMU_CLOCK_BRANCH_ENA_VOTE,
3153 .en_mask = BIT(2),
3154 .base = &virt_bases[GCC_BASE],
3155 .c = {
3156 .dbg_name = "gcc_gfx_tcu_clk",
3157 .ops = &clk_ops_vote,
3158 CLK_INIT(gcc_gfx_tcu_clk.c),
3159 },
3160};
3161
3162static struct local_vote_clk gcc_apss_tcu_clk = {
3163 .cbcr_reg = APSS_TCU_CBCR,
3164 .vote_reg = APCS_SMMU_CLOCK_BRANCH_ENA_VOTE,
3165 .en_mask = BIT(1),
3166 .base = &virt_bases[GCC_BASE],
3167 .c = {
3168 .dbg_name = "gcc_apss_tcu_clk",
3169 .ops = &clk_ops_vote,
3170 CLK_INIT(gcc_apss_tcu_clk.c),
3171 },
3172};
3173
3174static struct local_vote_clk gcc_gtcu_ahb_clk = {
3175 .cbcr_reg = GTCU_AHB_CBCR,
3176 .vote_reg = APCS_SMMU_CLOCK_BRANCH_ENA_VOTE,
3177 .en_mask = BIT(13),
3178 .base = &virt_bases[GCC_BASE],
3179 .c = {
3180 .dbg_name = "gcc_gtcu_ahb_clk",
3181 .ops = &clk_ops_vote,
3182 CLK_INIT(gcc_gtcu_ahb_clk.c),
3183 },
3184};
3185
3186static struct local_vote_clk gcc_ipa_tbu_clk = {
3187 .cbcr_reg = IPA_TBU_CBCR,
3188 .vote_reg = APCS_SMMU_CLOCK_BRANCH_ENA_VOTE,
3189 .en_mask = BIT(16),
3190 .base = &virt_bases[GCC_BASE],
3191 .c = {
3192 .dbg_name = "gcc_ipa_tbu_clk",
3193 .ops = &clk_ops_vote,
3194 CLK_INIT(gcc_ipa_tbu_clk.c),
3195 },
3196};
3197
3198static struct local_vote_clk gcc_jpeg_tbu_clk = {
3199 .cbcr_reg = JPEG_TBU_CBCR,
3200 .vote_reg = APCS_SMMU_CLOCK_BRANCH_ENA_VOTE,
3201 .en_mask = BIT(10),
3202 .base = &virt_bases[GCC_BASE],
3203 .c = {
3204 .dbg_name = "gcc_jpeg_tbu_clk",
3205 .ops = &clk_ops_vote,
3206 CLK_INIT(gcc_jpeg_tbu_clk.c),
3207 },
3208};
3209
3210static struct local_vote_clk gcc_mdp_tbu_clk = {
3211 .cbcr_reg = MDP_TBU_CBCR,
3212 .vote_reg = APCS_SMMU_CLOCK_BRANCH_ENA_VOTE,
3213 .en_mask = BIT(4),
3214 .base = &virt_bases[GCC_BASE],
3215 .c = {
3216 .dbg_name = "gcc_mdp_tbu_clk",
3217 .ops = &clk_ops_vote,
3218 CLK_INIT(gcc_mdp_tbu_clk.c),
3219 },
3220};
3221
3222static struct local_vote_clk gcc_smmu_cfg_clk = {
3223 .cbcr_reg = SMMU_CFG_CBCR,
3224 .vote_reg = APCS_SMMU_CLOCK_BRANCH_ENA_VOTE,
3225 .en_mask = BIT(12),
3226 .base = &virt_bases[GCC_BASE],
3227 .c = {
3228 .dbg_name = "gcc_smmu_cfg_clk",
3229 .ops = &clk_ops_vote,
3230 CLK_INIT(gcc_smmu_cfg_clk.c),
3231 },
3232};
3233
3234static struct local_vote_clk gcc_venus_tbu_clk = {
3235 .cbcr_reg = VENUS_TBU_CBCR,
3236 .vote_reg = APCS_SMMU_CLOCK_BRANCH_ENA_VOTE,
3237 .en_mask = BIT(5),
3238 .base = &virt_bases[GCC_BASE],
3239 .c = {
3240 .dbg_name = "gcc_venus_tbu_clk",
3241 .ops = &clk_ops_vote,
3242 CLK_INIT(gcc_venus_tbu_clk.c),
3243 },
3244};
3245
3246static struct local_vote_clk gcc_vfe1_tbu_clk = {
3247 .cbcr_reg = VFE1_TBU_CBCR,
3248 .vote_reg = APCS_SMMU_CLOCK_BRANCH_ENA_VOTE,
3249 .en_mask = BIT(17),
3250 .base = &virt_bases[GCC_BASE],
3251 .c = {
3252 .dbg_name = "gcc_vfe1_tbu_clk",
3253 .ops = &clk_ops_vote,
3254 CLK_INIT(gcc_vfe1_tbu_clk.c),
3255 },
3256};
3257
3258static struct local_vote_clk gcc_vfe_tbu_clk = {
3259 .cbcr_reg = VFE_TBU_CBCR,
3260 .vote_reg = APCS_SMMU_CLOCK_BRANCH_ENA_VOTE,
3261 .en_mask = BIT(9),
3262 .base = &virt_bases[GCC_BASE],
3263 .c = {
3264 .dbg_name = "gcc_vfe_tbu_clk",
3265 .ops = &clk_ops_vote,
3266 CLK_INIT(gcc_vfe_tbu_clk.c),
3267 },
3268};
3269
3270static struct branch_clk gcc_usb2a_phy_sleep_clk = {
3271 .cbcr_reg = USB2A_PHY_SLEEP_CBCR,
3272 .has_sibling = 1,
3273 .base = &virt_bases[GCC_BASE],
3274 .c = {
3275 .dbg_name = "gcc_usb2a_phy_sleep_clk",
3276 .ops = &clk_ops_branch,
3277 CLK_INIT(gcc_usb2a_phy_sleep_clk.c),
3278 },
3279};
3280
3281static struct branch_clk gcc_usb_hs_phy_cfg_ahb_clk = {
3282 .cbcr_reg = USB_HS_PHY_CFG_AHB_CBCR,
3283 .has_sibling = 1,
3284 .base = &virt_bases[GCC_BASE],
3285 .c = {
3286 .dbg_name = "gcc_usb_hs_phy_cfg_ahb_clk",
3287 .ops = &clk_ops_branch,
3288 CLK_INIT(gcc_usb_hs_phy_cfg_ahb_clk.c),
3289 },
3290};
3291
3292static struct branch_clk gcc_usb_fs_ahb_clk = {
3293 .cbcr_reg = USB_FS_AHB_CBCR,
3294 .has_sibling = 1,
3295 .base = &virt_bases[GCC_BASE],
3296 .c = {
3297 .dbg_name = "gcc_usb_fs_ahb_clk",
3298 .ops = &clk_ops_branch,
3299 CLK_INIT(gcc_usb_fs_ahb_clk.c),
3300 },
3301};
3302
3303static struct branch_clk gcc_usb_fs_ic_clk = {
3304 .cbcr_reg = USB_FS_IC_CBCR,
3305 .has_sibling = 0,
3306 .base = &virt_bases[GCC_BASE],
3307 .c = {
3308 .dbg_name = "gcc_usb_fs_ic_clk",
3309 .parent = &usb_fs_ic_clk_src.c,
3310 .ops = &clk_ops_branch,
3311 CLK_INIT(gcc_usb_fs_ic_clk.c),
3312 },
3313};
3314
3315static struct branch_clk gcc_usb_fs_system_clk = {
3316 .cbcr_reg = USB_FS_SYSTEM_CBCR,
3317 .bcr_reg = USB_FS_BCR,
3318 .has_sibling = 0,
3319 .base = &virt_bases[GCC_BASE],
3320 .c = {
3321 .dbg_name = "gcc_usb_fs_system_clk",
3322 .parent = &usb_fs_system_clk_src.c,
3323 .ops = &clk_ops_branch,
3324 CLK_INIT(gcc_usb_fs_system_clk.c),
3325 },
3326};
3327
3328static struct branch_clk gcc_usb_hs_ahb_clk = {
3329 .cbcr_reg = USB_HS_AHB_CBCR,
3330 .has_sibling = 1,
3331 .base = &virt_bases[GCC_BASE],
3332 .c = {
3333 .dbg_name = "gcc_usb_hs_ahb_clk",
3334 .ops = &clk_ops_branch,
3335 CLK_INIT(gcc_usb_hs_ahb_clk.c),
3336 },
3337};
3338
3339static struct branch_clk gcc_usb_hs_system_clk = {
3340 .cbcr_reg = USB_HS_SYSTEM_CBCR,
3341 .bcr_reg = USB_HS_BCR,
3342 .has_sibling = 0,
3343 .base = &virt_bases[GCC_BASE],
3344 .c = {
3345 .dbg_name = "gcc_usb_hs_system_clk",
3346 .parent = &usb_hs_system_clk_src.c,
3347 .ops = &clk_ops_branch,
3348 CLK_INIT(gcc_usb_hs_system_clk.c),
3349 },
3350};
3351
3352static struct reset_clk gcc_usb2_hs_phy_only_clk = {
3353 .reset_reg = USB2_HS_PHY_ONLY_BCR,
3354 .base = &virt_bases[GCC_BASE],
3355 .c = {
3356 .dbg_name = "gcc_usb2_hs_phy_only_clk",
3357 .ops = &clk_ops_rst,
3358 CLK_INIT(gcc_usb2_hs_phy_only_clk.c),
3359 },
3360};
3361
3362static struct reset_clk gcc_qusb2_phy_clk = {
3363 .reset_reg = QUSB2_PHY_BCR,
3364 .base = &virt_bases[GCC_BASE],
3365 .c = {
3366 .dbg_name = "gcc_qusb2_phy_clk",
3367 .ops = &clk_ops_rst,
3368 CLK_INIT(gcc_qusb2_phy_clk.c),
3369 },
3370};
3371
3372static struct branch_clk gcc_venus0_ahb_clk = {
3373 .cbcr_reg = VENUS0_AHB_CBCR,
3374 .has_sibling = 1,
3375 .base = &virt_bases[GCC_BASE],
3376 .c = {
3377 .dbg_name = "gcc_venus0_ahb_clk",
3378 .ops = &clk_ops_branch,
3379 CLK_INIT(gcc_venus0_ahb_clk.c),
3380 },
3381};
3382
3383static struct branch_clk gcc_venus0_axi_clk = {
3384 .cbcr_reg = VENUS0_AXI_CBCR,
3385 .has_sibling = 1,
3386 .base = &virt_bases[GCC_BASE],
3387 .c = {
3388 .dbg_name = "gcc_venus0_axi_clk",
3389 .ops = &clk_ops_branch,
3390 CLK_INIT(gcc_venus0_axi_clk.c),
3391 },
3392};
3393
3394static struct branch_clk gcc_venus0_core0_vcodec0_clk = {
3395 .cbcr_reg = VENUS0_CORE0_VCODEC0_CBCR,
3396 .has_sibling = 1,
3397 .base = &virt_bases[GCC_BASE],
3398 .c = {
3399 .dbg_name = "gcc_venus0_core0_vcodec0_clk",
3400 .parent = &vcodec0_clk_src.c,
3401 .ops = &clk_ops_branch,
3402 CLK_INIT(gcc_venus0_core0_vcodec0_clk.c),
3403 },
3404};
3405
3406static struct branch_clk gcc_venus0_core1_vcodec0_clk = {
3407 .cbcr_reg = VENUS0_CORE1_VCODEC0_CBCR,
3408 .has_sibling = 1,
3409 .base = &virt_bases[GCC_BASE],
3410 .c = {
3411 .dbg_name = "gcc_venus0_core1_vcodec0_clk",
3412 .parent = &vcodec0_clk_src.c,
3413 .ops = &clk_ops_branch,
3414 CLK_INIT(gcc_venus0_core1_vcodec0_clk.c),
3415 },
3416};
3417
3418static struct branch_clk gcc_venus0_vcodec0_clk = {
3419 .cbcr_reg = VENUS0_VCODEC0_CBCR,
3420 .has_sibling = 0,
3421 .base = &virt_bases[GCC_BASE],
3422 .c = {
3423 .dbg_name = "gcc_venus0_vcodec0_clk",
3424 .parent = &vcodec0_clk_src.c,
3425 .ops = &clk_ops_branch,
3426 CLK_INIT(gcc_venus0_vcodec0_clk.c),
3427 },
3428};
3429
3430static struct clk_ops clk_ops_debug_mux;
3431
3432static void __iomem *meas_base;
3433
3434static struct measure_clk apc0_m_clk = {
3435 .c = {
3436 .ops = &clk_ops_empty,
3437 .dbg_name = "apc0_m_clk",
3438 CLK_INIT(apc0_m_clk.c),
3439 },
3440};
3441
3442static struct measure_clk apc1_m_clk = {
3443 .c = {
3444 .ops = &clk_ops_empty,
3445 .dbg_name = "apc1_m_clk",
3446 CLK_INIT(apc1_m_clk.c),
3447 },
3448};
3449
3450static struct measure_clk cci_m_clk = {
3451 .c = {
3452 .ops = &clk_ops_empty,
3453 .dbg_name = "cci_m_clk",
3454 CLK_INIT(cci_m_clk.c),
3455 },
3456};
3457
3458static struct mux_clk apss_debug_ter_mux = {
3459 .ops = &mux_reg_ops,
3460 .mask = 0x3,
3461 .shift = 8,
3462 MUX_SRC_LIST(
3463 {&apc0_m_clk.c, 0},
3464 {&apc1_m_clk.c, 1},
3465 {&cci_m_clk.c, 2},
3466 ),
3467 .base = &meas_base,
3468 .c = {
3469 .dbg_name = "apss_debug_ter_mux",
3470 .ops = &clk_ops_gen_mux,
3471 CLK_INIT(apss_debug_ter_mux.c),
3472 },
3473};
3474
3475static struct mux_clk apss_debug_sec_mux = {
3476 .ops = &mux_reg_ops,
3477 .mask = 0x7,
3478 .shift = 12,
3479 MUX_SRC_LIST(
3480 {&apss_debug_ter_mux.c, 0},
3481 ),
3482 MUX_REC_SRC_LIST(
3483 &apss_debug_ter_mux.c,
3484 ),
3485 .base = &meas_base,
3486 .c = {
3487 .dbg_name = "apss_debug_sec_mux",
3488 .ops = &clk_ops_gen_mux,
3489 CLK_INIT(apss_debug_sec_mux.c),
3490 },
3491};
3492
3493static struct mux_clk apss_debug_pri_mux = {
3494 .ops = &mux_reg_ops,
3495 .mask = 0x3,
3496 .shift = 16,
3497 MUX_SRC_LIST(
3498 {&apss_debug_sec_mux.c, 0},
3499 ),
3500 MUX_REC_SRC_LIST(
3501 &apss_debug_sec_mux.c,
3502 ),
3503 .base = &meas_base,
3504 .c = {
3505 .dbg_name = "apss_debug_pri_mux",
3506 .ops = &clk_ops_gen_mux,
3507 CLK_INIT(apss_debug_pri_mux.c),
3508 },
3509};
3510
3511static struct measure_clk_data debug_mux_priv = {
3512 .cxo = &xo_clk_src.c,
3513 .plltest_reg = GCC_PLLTEST_PAD_CFG,
3514 .plltest_val = 0x51A00,
3515 .xo_div4_cbcr = GCC_XO_DIV4_CBCR,
3516 .ctl_reg = CLOCK_FRQ_MEASURE_CTL,
3517 .status_reg = CLOCK_FRQ_MEASURE_STATUS,
3518 .base = &virt_bases[GCC_BASE],
3519};
3520
3521static struct mux_clk gcc_debug_mux = {
3522 .priv = &debug_mux_priv,
3523 .ops = &mux_reg_ops,
3524 .offset = GCC_DEBUG_CLK_CTL,
3525 .mask = 0x1FF,
3526 .en_offset = GCC_DEBUG_CLK_CTL,
3527 .en_mask = BIT(16),
3528 .base = &virt_bases[GCC_BASE],
3529 MUX_REC_SRC_LIST(
3530 &apss_debug_pri_mux.c,
3531 ),
3532 MUX_SRC_LIST(
3533 { &apss_debug_pri_mux.c, 0x016A},
3534 { &snoc_clk.c, 0x0000 },
3535 { &sysmmnoc_clk.c, 0x0001 },
3536 { &pnoc_clk.c, 0x0008 },
3537 { &bimc_clk.c, 0x0154 },
3538 { &gcc_gp1_clk.c, 0x0010 },
3539 { &gcc_gp2_clk.c, 0x0011 },
3540 { &gcc_gp3_clk.c, 0x0012 },
3541 { &gcc_bimc_gfx_clk.c, 0x002d },
3542 { &gcc_mss_cfg_ahb_clk.c, 0x0030 },
3543 { &gcc_mss_q6_bimc_axi_clk.c, 0x0031 },
3544 { &gcc_apss_tcu_clk.c, 0x0050 },
3545 { &gcc_mdp_tbu_clk.c, 0x0051 },
3546 { &gcc_gfx_tbu_clk.c, 0x0052 },
3547 { &gcc_gfx_tcu_clk.c, 0x0053 },
3548 { &gcc_venus_tbu_clk.c, 0x0054 },
3549 { &gcc_gtcu_ahb_clk.c, 0x0058 },
3550 { &gcc_vfe_tbu_clk.c, 0x005a },
3551 { &gcc_smmu_cfg_clk.c, 0x005b },
3552 { &gcc_jpeg_tbu_clk.c, 0x005c },
3553 { &gcc_usb_hs_system_clk.c, 0x0060 },
3554 { &gcc_usb_hs_ahb_clk.c, 0x0061 },
3555 { &gcc_usb2a_phy_sleep_clk.c, 0x0063 },
3556 { &gcc_usb_hs_phy_cfg_ahb_clk.c, 0x0064 },
3557 { &gcc_sdcc1_apps_clk.c, 0x0068 },
3558 { &gcc_sdcc1_ahb_clk.c, 0x0069 },
3559 { &gcc_sdcc1_ice_core_clk.c, 0x006a },
3560 { &gcc_sdcc2_apps_clk.c, 0x0070 },
3561 { &gcc_sdcc2_ahb_clk.c, 0x0071 },
3562 { &gcc_blsp1_ahb_clk.c, 0x0088 },
3563 { &gcc_blsp1_qup1_spi_apps_clk.c, 0x008a },
3564 { &gcc_blsp1_qup1_i2c_apps_clk.c, 0x008b },
3565 { &gcc_blsp1_uart1_apps_clk.c, 0x008c },
3566 { &gcc_blsp1_qup2_spi_apps_clk.c, 0x008e },
3567 { &gcc_blsp1_qup2_i2c_apps_clk.c, 0x0090 },
3568 { &gcc_blsp1_uart2_apps_clk.c, 0x0091 },
3569 { &gcc_blsp1_qup3_spi_apps_clk.c, 0x0093 },
3570 { &gcc_blsp1_qup3_i2c_apps_clk.c, 0x0094 },
3571 { &gcc_blsp1_qup4_spi_apps_clk.c, 0x0095 },
3572 { &gcc_blsp1_qup4_i2c_apps_clk.c, 0x0096 },
3573 { &gcc_blsp2_ahb_clk.c, 0x0098 },
3574 { &gcc_blsp2_qup1_spi_apps_clk.c, 0x009a },
3575 { &gcc_blsp2_qup1_i2c_apps_clk.c, 0x009b },
3576 { &gcc_blsp2_uart1_apps_clk.c, 0x009c },
3577 { &gcc_blsp2_qup2_spi_apps_clk.c, 0x009e },
3578 { &gcc_blsp2_qup2_i2c_apps_clk.c, 0x00a0 },
3579 { &gcc_blsp2_uart2_apps_clk.c, 0x00a1 },
3580 { &gcc_blsp2_qup3_spi_apps_clk.c, 0x00a3 },
3581 { &gcc_blsp2_qup3_i2c_apps_clk.c, 0x00a4 },
3582 { &gcc_blsp2_qup4_spi_apps_clk.c, 0x00a5 },
3583 { &gcc_blsp2_qup4_i2c_apps_clk.c, 0x00a6 },
3584 { &gcc_camss_ahb_clk.c, 0x00a8 },
3585 { &gcc_camss_top_ahb_clk.c, 0x00a9 },
3586 { &gcc_camss_micro_ahb_clk.c, 0x00aa },
3587 { &gcc_camss_gp0_clk.c, 0x00ab },
3588 { &gcc_camss_gp1_clk.c, 0x00ac },
3589 { &gcc_camss_mclk0_clk.c, 0x00ad },
3590 { &gcc_camss_mclk1_clk.c, 0x00ae },
3591 { &gcc_camss_cci_clk.c, 0x00af },
3592 { &gcc_camss_cci_ahb_clk.c, 0x00b0 },
3593 { &gcc_camss_csi0phytimer_clk.c, 0x00b1 },
3594 { &gcc_camss_csi1phytimer_clk.c, 0x00b2 },
3595 { &gcc_camss_jpeg0_clk.c, 0x00b3 },
3596 { &gcc_camss_jpeg_ahb_clk.c, 0x00b4 },
3597 { &gcc_camss_jpeg_axi_clk.c, 0x00b5 },
3598 { &gcc_camss_vfe0_clk.c, 0x00b8 },
3599 { &gcc_camss_cpp_clk.c, 0x00b9 },
3600 { &gcc_camss_cpp_ahb_clk.c, 0x00ba },
3601 { &gcc_camss_vfe_ahb_clk.c, 0x00bb },
3602 { &gcc_camss_vfe_axi_clk.c, 0x00bc },
3603 { &gcc_camss_csi_vfe0_clk.c, 0x00bf },
3604 { &gcc_camss_csi0_clk.c, 0x00c0 },
3605 { &gcc_camss_csi0_ahb_clk.c, 0x00c1 },
3606 { &gcc_camss_csi0phy_clk.c, 0x00c2 },
3607 { &gcc_camss_csi0rdi_clk.c, 0x00c3 },
3608 { &gcc_camss_csi0pix_clk.c, 0x00c4 },
3609 { &gcc_camss_csi1_clk.c, 0x00c5 },
3610 { &gcc_camss_csi1_ahb_clk.c, 0x00c6 },
3611 { &gcc_camss_csi1phy_clk.c, 0x00c7 },
3612 { &gcc_pdm_ahb_clk.c, 0x00d0 },
3613 { &gcc_pdm2_clk.c, 0x00d2 },
3614 { &gcc_prng_ahb_clk.c, 0x00d8 },
3615 { &gcc_camss_csi1rdi_clk.c, 0x00e0 },
3616 { &gcc_camss_csi1pix_clk.c, 0x00e1 },
3617 { &gcc_camss_ispif_ahb_clk.c, 0x00e2 },
3618 { &gcc_camss_csi2_clk.c, 0x00e3 },
3619 { &gcc_camss_csi2_ahb_clk.c, 0x00e4 },
3620 { &gcc_camss_csi2phy_clk.c, 0x00e5 },
3621 { &gcc_camss_csi2rdi_clk.c, 0x00e6 },
3622 { &gcc_camss_csi2pix_clk.c, 0x00e7 },
3623 { &gcc_cpp_tbu_clk.c, 0x00e9 },
3624 { &gcc_boot_rom_ahb_clk.c, 0x00f8 },
3625 { &gcc_usb_fs_ahb_clk.c, 0x00f1 },
3626 { &gcc_usb_fs_ic_clk.c, 0x00f4 },
3627 { &gcc_crypto_clk.c, 0x0138 },
3628 { &gcc_crypto_axi_clk.c, 0x0139 },
3629 { &gcc_crypto_ahb_clk.c, 0x013a },
3630 { &gcc_bimc_gpu_clk.c, 0x0157 },
3631 { &gcc_ipa_tbu_clk.c, 0x0198 },
3632 { &gcc_vfe1_tbu_clk.c, 0x0199 },
3633 { &gcc_camss_csi_vfe1_clk.c, 0x01a0 },
3634 { &gcc_camss_vfe1_clk.c, 0x01a1 },
3635 { &gcc_camss_vfe1_ahb_clk.c, 0x01a2 },
3636 { &gcc_camss_vfe1_axi_clk.c, 0x01a3 },
3637 { &gcc_venus0_core0_vcodec0_clk.c, 0x01b8 },
3638 { &gcc_venus0_core1_vcodec0_clk.c, 0x01b9 },
3639 { &gcc_camss_mclk2_clk.c, 0x01bd },
3640 { &gcc_oxili_timer_clk.c, 0x01e9 },
3641 { &gcc_oxili_gfx3d_clk.c, 0x01ea },
3642 { &gcc_oxili_ahb_clk.c, 0x01eb },
3643 { &gcc_oxili_gmem_clk.c, 0x01f0 },
3644 { &gcc_venus0_vcodec0_clk.c, 0x01f1 },
3645 { &gcc_venus0_axi_clk.c, 0x01f2 },
3646 { &gcc_venus0_ahb_clk.c, 0x01f3 },
3647 { &gcc_mdss_ahb_clk.c, 0x01f6 },
3648 { &gcc_mdss_axi_clk.c, 0x01f7 },
3649 { &gcc_mdss_pclk0_clk.c, 0x01f8 },
3650 { &gcc_mdss_mdp_clk.c, 0x01f9 },
3651 { &gcc_mdss_vsync_clk.c, 0x01fb },
3652 { &gcc_mdss_byte0_clk.c, 0x01fc },
3653 { &gcc_mdss_esc0_clk.c, 0x01fd },
3654 { &wcnss_m_clk.c, 0x0ec },
3655 ),
3656 .c = {
3657 .dbg_name = "gcc_debug_mux",
3658 .ops = &clk_ops_debug_mux,
3659 .flags = CLKFLAG_NO_RATE_CACHE | CLKFLAG_MEASURE,
3660 CLK_INIT(gcc_debug_mux.c),
3661 },
3662};
3663
3664static struct mux_clk gcc_debug_mux_8937 = {
3665 .priv = &debug_mux_priv,
3666 .ops = &mux_reg_ops,
3667 .offset = GCC_DEBUG_CLK_CTL,
3668 .mask = 0x1FF,
3669 .en_offset = GCC_DEBUG_CLK_CTL,
3670 .en_mask = BIT(16),
3671 .base = &virt_bases[GCC_BASE],
3672 MUX_REC_SRC_LIST(
3673 &apss_debug_pri_mux.c,
3674 ),
3675 MUX_SRC_LIST(
3676 { &apss_debug_pri_mux.c, 0x016A},
3677 { &snoc_clk.c, 0x0000 },
3678 { &sysmmnoc_clk.c, 0x0001 },
3679 { &pnoc_clk.c, 0x0008 },
3680 { &bimc_clk.c, 0x015A },
3681 { &ipa_clk.c, 0x1B0 },
3682 { &gcc_gp1_clk.c, 0x0010 },
3683 { &gcc_gp2_clk.c, 0x0011 },
3684 { &gcc_gp3_clk.c, 0x0012 },
3685 { &gcc_bimc_gfx_clk.c, 0x002d },
3686 { &gcc_mss_cfg_ahb_clk.c, 0x0030 },
3687 { &gcc_mss_q6_bimc_axi_clk.c, 0x0031 },
3688 { &gcc_qdss_dap_clk.c, 0x0049 },
3689 { &gcc_apss_tcu_clk.c, 0x0050 },
3690 { &gcc_mdp_tbu_clk.c, 0x0051 },
3691 { &gcc_gfx_tbu_clk.c, 0x0052 },
3692 { &gcc_gfx_tcu_clk.c, 0x0053 },
3693 { &gcc_venus_tbu_clk.c, 0x0054 },
3694 { &gcc_gtcu_ahb_clk.c, 0x0058 },
3695 { &gcc_vfe_tbu_clk.c, 0x005a },
3696 { &gcc_smmu_cfg_clk.c, 0x005b },
3697 { &gcc_jpeg_tbu_clk.c, 0x005c },
3698 { &gcc_usb_hs_system_clk.c, 0x0060 },
3699 { &gcc_usb_hs_ahb_clk.c, 0x0061 },
3700 { &gcc_usb2a_phy_sleep_clk.c, 0x0063 },
3701 { &gcc_usb_hs_phy_cfg_ahb_clk.c, 0x0064 },
3702 { &gcc_sdcc1_apps_clk.c, 0x0068 },
3703 { &gcc_sdcc1_ahb_clk.c, 0x0069 },
3704 { &gcc_sdcc1_ice_core_clk.c, 0x006a },
3705 { &gcc_sdcc2_apps_clk.c, 0x0070 },
3706 { &gcc_sdcc2_ahb_clk.c, 0x0071 },
3707 { &gcc_blsp1_ahb_clk.c, 0x0088 },
3708 { &gcc_blsp1_qup1_spi_apps_clk.c, 0x008a },
3709 { &gcc_blsp1_qup1_i2c_apps_clk.c, 0x008b },
3710 { &gcc_blsp1_uart1_apps_clk.c, 0x008c },
3711 { &gcc_blsp1_qup2_spi_apps_clk.c, 0x008e },
3712 { &gcc_blsp1_qup2_i2c_apps_clk.c, 0x0090 },
3713 { &gcc_blsp1_uart2_apps_clk.c, 0x0091 },
3714 { &gcc_blsp1_qup3_spi_apps_clk.c, 0x0093 },
3715 { &gcc_blsp1_qup3_i2c_apps_clk.c, 0x0094 },
3716 { &gcc_blsp1_qup4_spi_apps_clk.c, 0x0095 },
3717 { &gcc_blsp1_qup4_i2c_apps_clk.c, 0x0096 },
3718 { &gcc_blsp2_ahb_clk.c, 0x0098 },
3719 { &gcc_blsp2_qup1_spi_apps_clk.c, 0x009a },
3720 { &gcc_blsp2_qup1_i2c_apps_clk.c, 0x009b },
3721 { &gcc_blsp2_uart1_apps_clk.c, 0x009c },
3722 { &gcc_blsp2_qup2_spi_apps_clk.c, 0x009e },
3723 { &gcc_blsp2_qup2_i2c_apps_clk.c, 0x00a0 },
3724 { &gcc_blsp2_uart2_apps_clk.c, 0x00a1 },
3725 { &gcc_blsp2_qup3_spi_apps_clk.c, 0x00a3 },
3726 { &gcc_blsp2_qup3_i2c_apps_clk.c, 0x00a4 },
3727 { &gcc_blsp2_qup4_spi_apps_clk.c, 0x00a5 },
3728 { &gcc_blsp2_qup4_i2c_apps_clk.c, 0x00a6 },
3729 { &gcc_camss_ahb_clk.c, 0x00a8 },
3730 { &gcc_camss_top_ahb_clk.c, 0x00a9 },
3731 { &gcc_camss_micro_ahb_clk.c, 0x00aa },
3732 { &gcc_camss_gp0_clk.c, 0x00ab },
3733 { &gcc_camss_gp1_clk.c, 0x00ac },
3734 { &gcc_camss_mclk0_clk.c, 0x00ad },
3735 { &gcc_camss_mclk1_clk.c, 0x00ae },
3736 { &gcc_camss_cci_clk.c, 0x00af },
3737 { &gcc_camss_cci_ahb_clk.c, 0x00b0 },
3738 { &gcc_camss_csi0phytimer_clk.c, 0x00b1 },
3739 { &gcc_camss_csi1phytimer_clk.c, 0x00b2 },
3740 { &gcc_camss_jpeg0_clk.c, 0x00b3 },
3741 { &gcc_camss_jpeg_ahb_clk.c, 0x00b4 },
3742 { &gcc_camss_jpeg_axi_clk.c, 0x00b5 },
3743 { &gcc_camss_vfe0_clk.c, 0x00b8 },
3744 { &gcc_camss_cpp_clk.c, 0x00b9 },
3745 { &gcc_camss_cpp_ahb_clk.c, 0x00ba },
3746 { &gcc_camss_vfe_ahb_clk.c, 0x00bb },
3747 { &gcc_camss_vfe_axi_clk.c, 0x00bc },
3748 { &gcc_camss_csi_vfe0_clk.c, 0x00bf },
3749 { &gcc_camss_csi0_clk.c, 0x00c0 },
3750 { &gcc_camss_csi0_ahb_clk.c, 0x00c1 },
3751 { &gcc_camss_csi0phy_clk.c, 0x00c2 },
3752 { &gcc_camss_csi0rdi_clk.c, 0x00c3 },
3753 { &gcc_camss_csi0pix_clk.c, 0x00c4 },
3754 { &gcc_camss_csi1_clk.c, 0x00c5 },
3755 { &gcc_camss_csi1_ahb_clk.c, 0x00c6 },
3756 { &gcc_camss_csi1phy_clk.c, 0x00c7 },
3757 { &gcc_pdm_ahb_clk.c, 0x00d0 },
3758 { &gcc_pdm2_clk.c, 0x00d2 },
3759 { &gcc_prng_ahb_clk.c, 0x00d8 },
3760 { &gcc_camss_csi1rdi_clk.c, 0x00e0 },
3761 { &gcc_camss_csi1pix_clk.c, 0x00e1 },
3762 { &gcc_camss_ispif_ahb_clk.c, 0x00e2 },
3763 { &gcc_camss_csi2_clk.c, 0x00e3 },
3764 { &gcc_camss_csi2_ahb_clk.c, 0x00e4 },
3765 { &gcc_camss_csi2phy_clk.c, 0x00e5 },
3766 { &gcc_camss_csi2rdi_clk.c, 0x00e6 },
3767 { &gcc_camss_csi2pix_clk.c, 0x00e7 },
3768 { &gcc_cpp_tbu_clk.c, 0x00e9 },
3769 { &gcc_boot_rom_ahb_clk.c, 0x00f8 },
3770 { &gcc_crypto_clk.c, 0x0138 },
3771 { &gcc_crypto_axi_clk.c, 0x0139 },
3772 { &gcc_crypto_ahb_clk.c, 0x013a },
3773 { &gcc_bimc_gpu_clk.c, 0x0157 },
3774 { &gcc_ipa_tbu_clk.c, 0x0198 },
3775 { &gcc_vfe1_tbu_clk.c, 0x0199 },
3776 { &gcc_camss_csi_vfe1_clk.c, 0x01a0 },
3777 { &gcc_camss_vfe1_clk.c, 0x01a1 },
3778 { &gcc_camss_vfe1_ahb_clk.c, 0x01a2 },
3779 { &gcc_camss_vfe1_axi_clk.c, 0x01a3 },
3780 { &gcc_camss_cpp_axi_clk.c, 0x01a4 },
3781 { &gcc_venus0_core0_vcodec0_clk.c, 0x01b8 },
3782 { &gcc_dcc_clk.c, 0x01b9 },
3783 { &gcc_camss_mclk2_clk.c, 0x01bd },
3784 { &gcc_oxili_timer_clk.c, 0x01e9 },
3785 { &gcc_oxili_gfx3d_clk.c, 0x01ea },
3786 { &gcc_oxili_aon_clk.c, 0x00ee },
3787 { &gcc_oxili_ahb_clk.c, 0x01eb },
3788 { &gcc_venus0_vcodec0_clk.c, 0x01f1 },
3789 { &gcc_venus0_axi_clk.c, 0x01f2 },
3790 { &gcc_venus0_ahb_clk.c, 0x01f3 },
3791 { &gcc_mdss_ahb_clk.c, 0x01f6 },
3792 { &gcc_mdss_axi_clk.c, 0x01f7 },
3793 { &gcc_mdss_pclk0_clk.c, 0x01f8 },
3794 { &gcc_mdss_pclk1_clk.c, 0x01e3 },
3795 { &gcc_mdss_mdp_clk.c, 0x01f9 },
3796 { &gcc_mdss_vsync_clk.c, 0x01fb },
3797 { &gcc_mdss_byte0_clk.c, 0x01fc },
3798 { &gcc_mdss_byte1_clk.c, 0x01e4 },
3799 { &gcc_mdss_esc0_clk.c, 0x01fd },
3800 { &gcc_mdss_esc1_clk.c, 0x01e5 },
3801 { &wcnss_m_clk.c, 0x0ec },
3802 ),
3803 .c = {
3804 .dbg_name = "gcc_debug_mux_8937",
3805 .ops = &clk_ops_debug_mux,
3806 .flags = CLKFLAG_NO_RATE_CACHE | CLKFLAG_MEASURE,
3807 CLK_INIT(gcc_debug_mux_8937.c),
3808 },
3809};
3810
3811/* Clock lookup */
3812static struct clk_lookup msm_clocks_lookup_common[] = {
3813 /* RPM clocks */
3814 CLK_LIST(xo_clk_src),
3815 CLK_LIST(xo_a_clk_src),
3816 CLK_LIST(xo_otg_clk),
3817 CLK_LIST(xo_lpm_clk),
3818 CLK_LIST(xo_pil_mss_clk),
3819 CLK_LIST(xo_pil_pronto_clk),
3820 CLK_LIST(xo_wlan_clk),
3821 CLK_LIST(xo_pil_lpass_clk),
3822
3823 CLK_LIST(sysmmnoc_msmbus_clk),
3824 CLK_LIST(snoc_msmbus_clk),
3825 CLK_LIST(snoc_msmbus_a_clk),
3826 CLK_LIST(sysmmnoc_msmbus_a_clk),
3827 CLK_LIST(pnoc_msmbus_clk),
3828 CLK_LIST(pnoc_msmbus_a_clk),
3829 CLK_LIST(bimc_msmbus_clk),
3830 CLK_LIST(bimc_msmbus_a_clk),
3831 CLK_LIST(pnoc_keepalive_a_clk),
3832
3833 CLK_LIST(pnoc_usb_a_clk),
3834 CLK_LIST(snoc_usb_a_clk),
3835 CLK_LIST(bimc_usb_a_clk),
3836 CLK_LIST(pnoc_usb_clk),
3837 CLK_LIST(snoc_usb_clk),
3838 CLK_LIST(bimc_usb_clk),
3839
3840 CLK_LIST(snoc_wcnss_a_clk),
3841 CLK_LIST(bimc_wcnss_a_clk),
3842
3843 CLK_LIST(qdss_clk),
3844 CLK_LIST(qdss_a_clk),
3845
3846 CLK_LIST(snoc_clk),
3847 CLK_LIST(sysmmnoc_clk),
3848 CLK_LIST(pnoc_clk),
3849 CLK_LIST(bimc_clk),
3850 CLK_LIST(snoc_a_clk),
3851 CLK_LIST(sysmmnoc_a_clk),
3852 CLK_LIST(pnoc_a_clk),
3853 CLK_LIST(bimc_a_clk),
3854
3855 CLK_LIST(bb_clk1),
3856 CLK_LIST(bb_clk1_a),
3857 CLK_LIST(bb_clk2),
3858 CLK_LIST(bb_clk2_a),
3859 CLK_LIST(rf_clk2),
3860 CLK_LIST(rf_clk2_a),
3861 CLK_LIST(div_clk2),
3862 CLK_LIST(div_clk2_a),
3863
3864 CLK_LIST(bb_clk1_pin),
3865 CLK_LIST(bb_clk1_a_pin),
3866 CLK_LIST(bb_clk2_pin),
3867 CLK_LIST(bb_clk2_a_pin),
3868
3869 CLK_LIST(gpll0_clk_src),
3870 CLK_LIST(gpll0_ao_clk_src),
3871 CLK_LIST(gpll6_clk_src),
3872 CLK_LIST(gpll4_clk_src),
3873 CLK_LIST(gpll3_clk_src),
3874 CLK_LIST(a53ss_c1_pll),
3875 CLK_LIST(gcc_blsp1_ahb_clk),
3876 CLK_LIST(gcc_blsp2_ahb_clk),
3877 CLK_LIST(gcc_boot_rom_ahb_clk),
3878 CLK_LIST(gcc_crypto_ahb_clk),
3879 CLK_LIST(gcc_crypto_axi_clk),
3880 CLK_LIST(gcc_crypto_clk),
3881 CLK_LIST(gcc_prng_ahb_clk),
3882 CLK_LIST(gcc_cpp_tbu_clk),
3883 CLK_LIST(gcc_apss_tcu_clk),
3884 CLK_LIST(gcc_jpeg_tbu_clk),
3885 CLK_LIST(gcc_mdp_tbu_clk),
3886 CLK_LIST(gcc_smmu_cfg_clk),
3887 CLK_LIST(gcc_venus_tbu_clk),
3888 CLK_LIST(gcc_vfe1_tbu_clk),
3889 CLK_LIST(gcc_vfe_tbu_clk),
3890 CLK_LIST(camss_top_ahb_clk_src),
3891 CLK_LIST(apss_ahb_clk_src),
3892 CLK_LIST(csi0_clk_src),
3893 CLK_LIST(csi1_clk_src),
3894 CLK_LIST(csi2_clk_src),
3895 CLK_LIST(vcodec0_clk_src),
3896 CLK_LIST(vfe0_clk_src),
3897 CLK_LIST(vfe1_clk_src),
3898 CLK_LIST(gfx3d_clk_src),
3899 CLK_LIST(blsp1_qup2_i2c_apps_clk_src),
3900 CLK_LIST(blsp1_qup2_spi_apps_clk_src),
3901 CLK_LIST(blsp1_qup3_i2c_apps_clk_src),
3902 CLK_LIST(blsp1_qup3_spi_apps_clk_src),
3903 CLK_LIST(blsp1_qup4_i2c_apps_clk_src),
3904 CLK_LIST(blsp1_qup4_spi_apps_clk_src),
3905 CLK_LIST(blsp1_uart1_apps_clk_src),
3906 CLK_LIST(blsp1_uart2_apps_clk_src),
3907 CLK_LIST(blsp2_qup1_i2c_apps_clk_src),
3908 CLK_LIST(blsp2_qup1_spi_apps_clk_src),
3909 CLK_LIST(blsp2_qup2_i2c_apps_clk_src),
3910 CLK_LIST(blsp2_qup2_spi_apps_clk_src),
3911 CLK_LIST(blsp2_qup3_i2c_apps_clk_src),
3912 CLK_LIST(blsp2_qup3_spi_apps_clk_src),
3913 CLK_LIST(blsp2_uart1_apps_clk_src),
3914 CLK_LIST(blsp2_uart2_apps_clk_src),
3915 CLK_LIST(cci_clk_src),
3916 CLK_LIST(cpp_clk_src),
3917 CLK_LIST(camss_gp0_clk_src),
3918 CLK_LIST(camss_gp1_clk_src),
3919 CLK_LIST(jpeg0_clk_src),
3920 CLK_LIST(mclk0_clk_src),
3921 CLK_LIST(mclk1_clk_src),
3922 CLK_LIST(mclk2_clk_src),
3923 CLK_LIST(csi0phytimer_clk_src),
3924 CLK_LIST(csi1phytimer_clk_src),
3925 CLK_LIST(crypto_clk_src),
3926 CLK_LIST(gp1_clk_src),
3927 CLK_LIST(gp2_clk_src),
3928 CLK_LIST(gp3_clk_src),
3929 CLK_LIST(esc0_clk_src),
3930 CLK_LIST(mdp_clk_src),
3931 CLK_LIST(vsync_clk_src),
3932 CLK_LIST(pdm2_clk_src),
3933 CLK_LIST(sdcc1_apps_clk_src),
3934 CLK_LIST(sdcc1_ice_core_clk_src),
3935 CLK_LIST(sdcc2_apps_clk_src),
3936 CLK_LIST(usb_hs_system_clk_src),
3937 CLK_LIST(gcc_bimc_gpu_clk),
3938 CLK_LIST(gcc_blsp1_qup2_i2c_apps_clk),
3939 CLK_LIST(gcc_blsp1_qup2_spi_apps_clk),
3940 CLK_LIST(gcc_blsp1_qup3_i2c_apps_clk),
3941 CLK_LIST(gcc_blsp1_qup3_spi_apps_clk),
3942 CLK_LIST(gcc_blsp1_qup4_i2c_apps_clk),
3943 CLK_LIST(gcc_blsp1_qup4_spi_apps_clk),
3944 CLK_LIST(gcc_blsp1_uart1_apps_clk),
3945 CLK_LIST(gcc_blsp1_uart2_apps_clk),
3946 CLK_LIST(gcc_blsp2_qup1_i2c_apps_clk),
3947 CLK_LIST(gcc_blsp2_qup1_spi_apps_clk),
3948 CLK_LIST(gcc_blsp2_qup2_i2c_apps_clk),
3949 CLK_LIST(gcc_blsp2_qup2_spi_apps_clk),
3950 CLK_LIST(gcc_blsp2_qup3_i2c_apps_clk),
3951 CLK_LIST(gcc_blsp2_qup3_spi_apps_clk),
3952 CLK_LIST(gcc_blsp2_uart1_apps_clk),
3953 CLK_LIST(gcc_blsp2_uart2_apps_clk),
3954 CLK_LIST(gcc_camss_cci_ahb_clk),
3955 CLK_LIST(gcc_camss_cci_clk),
3956 CLK_LIST(gcc_camss_cpp_ahb_clk),
3957 CLK_LIST(gcc_camss_cpp_axi_clk),
3958 CLK_LIST(gcc_camss_cpp_clk),
3959 CLK_LIST(gcc_camss_csi0_ahb_clk),
3960 CLK_LIST(gcc_camss_csi0_clk),
3961 CLK_LIST(gcc_camss_csi0phy_clk),
3962 CLK_LIST(gcc_camss_csi0pix_clk),
3963 CLK_LIST(gcc_camss_csi0rdi_clk),
3964 CLK_LIST(gcc_camss_csi1_ahb_clk),
3965 CLK_LIST(gcc_camss_csi1_clk),
3966 CLK_LIST(gcc_camss_csi1phy_clk),
3967 CLK_LIST(gcc_camss_csi1pix_clk),
3968 CLK_LIST(gcc_camss_csi1rdi_clk),
3969 CLK_LIST(gcc_camss_csi2_ahb_clk),
3970 CLK_LIST(gcc_camss_csi2_clk),
3971 CLK_LIST(gcc_camss_csi2phy_clk),
3972 CLK_LIST(gcc_camss_csi2pix_clk),
3973 CLK_LIST(gcc_camss_csi2rdi_clk),
3974 CLK_LIST(gcc_camss_csi_vfe0_clk),
3975 CLK_LIST(gcc_camss_csi_vfe1_clk),
3976 CLK_LIST(gcc_camss_gp0_clk),
3977 CLK_LIST(gcc_camss_gp1_clk),
3978 CLK_LIST(gcc_camss_ispif_ahb_clk),
3979 CLK_LIST(gcc_camss_jpeg0_clk),
3980 CLK_LIST(gcc_camss_jpeg_ahb_clk),
3981 CLK_LIST(gcc_camss_jpeg_axi_clk),
3982 CLK_LIST(gcc_camss_mclk0_clk),
3983 CLK_LIST(gcc_camss_mclk1_clk),
3984 CLK_LIST(gcc_camss_mclk2_clk),
3985 CLK_LIST(gcc_camss_micro_ahb_clk),
3986 CLK_LIST(gcc_camss_csi0phytimer_clk),
3987 CLK_LIST(gcc_camss_csi1phytimer_clk),
3988 CLK_LIST(gcc_camss_ahb_clk),
3989 CLK_LIST(gcc_camss_top_ahb_clk),
3990 CLK_LIST(gcc_camss_vfe0_clk),
3991 CLK_LIST(gcc_camss_vfe_ahb_clk),
3992 CLK_LIST(gcc_camss_vfe_axi_clk),
3993 CLK_LIST(gcc_camss_vfe1_ahb_clk),
3994 CLK_LIST(gcc_camss_vfe1_axi_clk),
3995 CLK_LIST(gcc_camss_vfe1_clk),
3996 CLK_LIST(gcc_gp1_clk),
3997 CLK_LIST(gcc_gp2_clk),
3998 CLK_LIST(gcc_gp3_clk),
3999 CLK_LIST(gcc_mdss_ahb_clk),
4000 CLK_LIST(gcc_mdss_axi_clk),
4001 CLK_LIST(gcc_mdss_esc0_clk),
4002 CLK_LIST(gcc_mdss_mdp_clk),
4003 CLK_LIST(gcc_mdss_vsync_clk),
4004 CLK_LIST(gcc_mss_cfg_ahb_clk),
4005 CLK_LIST(gcc_mss_q6_bimc_axi_clk),
4006 CLK_LIST(gcc_bimc_gfx_clk),
4007 CLK_LIST(gcc_oxili_ahb_clk),
4008 CLK_LIST(gcc_oxili_gfx3d_clk),
4009 CLK_LIST(gcc_pdm2_clk),
4010 CLK_LIST(gcc_pdm_ahb_clk),
4011 CLK_LIST(gcc_sdcc1_ahb_clk),
4012 CLK_LIST(gcc_sdcc1_apps_clk),
4013 CLK_LIST(gcc_sdcc1_ice_core_clk),
4014 CLK_LIST(gcc_sdcc2_ahb_clk),
4015 CLK_LIST(gcc_sdcc2_apps_clk),
4016 CLK_LIST(gcc_usb2a_phy_sleep_clk),
4017 CLK_LIST(gcc_usb_hs_phy_cfg_ahb_clk),
4018 CLK_LIST(gcc_usb_hs_ahb_clk),
4019 CLK_LIST(gcc_usb_hs_system_clk),
4020 CLK_LIST(gcc_venus0_ahb_clk),
4021 CLK_LIST(gcc_venus0_axi_clk),
4022 CLK_LIST(gcc_venus0_core0_vcodec0_clk),
4023 CLK_LIST(gcc_venus0_vcodec0_clk),
4024
4025 /* Reset clks */
4026 CLK_LIST(gcc_usb2_hs_phy_only_clk),
4027 CLK_LIST(gcc_qusb2_phy_clk),
4028
4029 /* WCNSS Debug */
4030 CLK_LIST(wcnss_m_clk),
4031};
4032
4033static struct clk_lookup msm_clocks_lookup_8952[] = {
4034 CLK_LIST(a53ss_c0_pll),
4035 CLK_LIST(a53ss_cci_pll),
4036 CLK_LIST(ipa_clk),
4037 CLK_LIST(ipa_a_clk),
4038 CLK_LIST(gpll0_clk_src_8952),
4039 CLK_LIST(gpll0_ao_clk_src_8952),
4040 CLK_LIST(gcc_oxili_gmem_clk),
4041 CLK_LIST(usb_fs_ic_clk_src),
4042 CLK_LIST(gcc_usb_fs_ic_clk),
4043 CLK_LIST(usb_fs_system_clk_src),
4044 CLK_LIST(gcc_usb_fs_system_clk),
4045 CLK_LIST(gcc_gfx_tcu_clk),
4046 CLK_LIST(gcc_gfx_tbu_clk),
4047 CLK_LIST(gcc_gtcu_ahb_clk),
4048 CLK_LIST(gcc_ipa_tbu_clk),
4049 CLK_LIST(gcc_usb_fs_ahb_clk),
4050 CLK_LIST(gcc_venus0_core1_vcodec0_clk),
4051 CLK_LIST(blsp1_qup1_i2c_apps_clk_src),
4052 CLK_LIST(blsp1_qup1_spi_apps_clk_src),
4053 CLK_LIST(gcc_blsp1_qup1_i2c_apps_clk),
4054 CLK_LIST(gcc_blsp1_qup1_spi_apps_clk),
4055 CLK_LIST(blsp2_qup4_i2c_apps_clk_src),
4056 CLK_LIST(blsp2_qup4_spi_apps_clk_src),
4057 CLK_LIST(gcc_blsp2_qup4_i2c_apps_clk),
4058 CLK_LIST(gcc_blsp2_qup4_spi_apps_clk),
4059 CLK_LIST(gcc_oxili_timer_clk),
4060};
4061
4062static struct clk_lookup msm_clocks_lookup_8937[] = {
4063 CLK_LIST(gpll0_clk_src_8937),
4064 CLK_LIST(gpll0_ao_clk_src_8937),
4065 CLK_LIST(gpll0_sleep_clk_src),
4066 CLK_LIST(a53ss_c0_pll),
4067 CLK_LIST(esc1_clk_src),
4068 CLK_LIST(gcc_mdss_esc1_clk),
4069 CLK_LIST(gcc_dcc_clk),
4070 CLK_LIST(gcc_oxili_aon_clk),
4071 CLK_LIST(gcc_qdss_dap_clk),
4072 CLK_LIST(blsp1_qup1_i2c_apps_clk_src),
4073 CLK_LIST(blsp1_qup1_spi_apps_clk_src),
4074 CLK_LIST(gcc_blsp1_qup1_i2c_apps_clk),
4075 CLK_LIST(gcc_blsp1_qup1_spi_apps_clk),
4076 CLK_LIST(blsp2_qup4_i2c_apps_clk_src),
4077 CLK_LIST(blsp2_qup4_spi_apps_clk_src),
4078 CLK_LIST(gcc_blsp2_qup4_i2c_apps_clk),
4079 CLK_LIST(gcc_blsp2_qup4_spi_apps_clk),
4080 CLK_LIST(gcc_oxili_timer_clk),
4081};
4082
Odelu Kukatla678382b2018-03-27 22:58:52 +0530[diff] [blame]4083static struct clk_lookup msm_clocks_lookup_sdm429[] = {
4084 CLK_LIST(gpll0_clk_src_8937),
4085 CLK_LIST(gpll0_ao_clk_src_8937),
4086 CLK_LIST(gpll0_sleep_clk_src),
4087 CLK_LIST(esc1_clk_src),
4088 CLK_LIST(gcc_mdss_esc1_clk),
4089 CLK_LIST(gcc_dcc_clk),
4090 CLK_LIST(gcc_oxili_aon_clk),
4091 CLK_LIST(gcc_qdss_dap_clk),
4092 CLK_LIST(blsp1_qup1_i2c_apps_clk_src),
4093 CLK_LIST(blsp1_qup1_spi_apps_clk_src),
4094 CLK_LIST(gcc_blsp1_qup1_i2c_apps_clk),
4095 CLK_LIST(gcc_blsp1_qup1_spi_apps_clk),
4096 CLK_LIST(blsp2_qup4_i2c_apps_clk_src),
4097 CLK_LIST(blsp2_qup4_spi_apps_clk_src),
4098 CLK_LIST(gcc_blsp2_qup4_i2c_apps_clk),
4099 CLK_LIST(gcc_blsp2_qup4_spi_apps_clk),
4100 CLK_LIST(gcc_oxili_timer_clk),
4101};
4102
Shefali Jain79729af2018-01-29 15:15:20 +0530[diff] [blame]4103static struct clk_lookup msm_clocks_lookup_8917[] = {
4104 CLK_LIST(gpll0_clk_src_8937),
4105 CLK_LIST(gpll0_ao_clk_src_8937),
4106 CLK_LIST(gpll0_sleep_clk_src),
4107 CLK_LIST(bimc_gpu_clk),
4108 CLK_LIST(bimc_gpu_a_clk),
4109 CLK_LIST(gcc_dcc_clk),
4110 CLK_LIST(gcc_qdss_dap_clk),
4111 CLK_LIST(gcc_gfx_tcu_clk),
4112 CLK_LIST(gcc_gfx_tbu_clk),
4113 CLK_LIST(gcc_gtcu_ahb_clk),
4114};
4115
4116static struct clk_lookup msm_clocks_lookup_8920[] = {
4117 CLK_LIST(gpll0_clk_src_8937),
4118 CLK_LIST(gpll0_ao_clk_src_8937),
4119 CLK_LIST(gpll0_sleep_clk_src),
4120 CLK_LIST(bimc_gpu_clk),
4121 CLK_LIST(bimc_gpu_a_clk),
4122 CLK_LIST(gcc_dcc_clk),
4123 CLK_LIST(gcc_qdss_dap_clk),
4124 CLK_LIST(gcc_gfx_tcu_clk),
4125 CLK_LIST(gcc_gfx_tbu_clk),
4126 CLK_LIST(gcc_gtcu_ahb_clk),
4127 CLK_LIST(ipa_clk),
4128 CLK_LIST(ipa_a_clk),
4129 CLK_LIST(gcc_ipa_tbu_clk),
4130};
4131
4132static struct clk_lookup msm_clocks_lookup_8940[] = {
4133 CLK_LIST(gpll0_clk_src_8937),
4134 CLK_LIST(gpll0_ao_clk_src_8937),
4135 CLK_LIST(gpll0_sleep_clk_src),
4136 CLK_LIST(a53ss_c0_pll),
4137 CLK_LIST(esc1_clk_src),
4138 CLK_LIST(gcc_mdss_esc1_clk),
4139 CLK_LIST(gcc_dcc_clk),
4140 CLK_LIST(gcc_oxili_aon_clk),
4141 CLK_LIST(gcc_qdss_dap_clk),
4142 CLK_LIST(blsp1_qup1_i2c_apps_clk_src),
4143 CLK_LIST(blsp1_qup1_spi_apps_clk_src),
4144 CLK_LIST(gcc_blsp1_qup1_i2c_apps_clk),
4145 CLK_LIST(gcc_blsp1_qup1_spi_apps_clk),
4146 CLK_LIST(blsp2_qup4_i2c_apps_clk_src),
4147 CLK_LIST(blsp2_qup4_spi_apps_clk_src),
4148 CLK_LIST(gcc_blsp2_qup4_i2c_apps_clk),
4149 CLK_LIST(gcc_blsp2_qup4_spi_apps_clk),
4150 CLK_LIST(gcc_oxili_timer_clk),
4151 CLK_LIST(ipa_clk),
4152 CLK_LIST(ipa_a_clk),
4153 CLK_LIST(gcc_ipa_tbu_clk),
4154};
4155
4156/* Please note that the order of reg-names is important */
4157static int get_mmio_addr(struct platform_device *pdev, u32 nbases)
4158{
4159 int i, count;
4160 const char *str;
4161 struct resource *res;
4162 struct device *dev = &pdev->dev;
4163
4164 count = of_property_count_strings(dev->of_node, "reg-names");
4165 if (count < nbases) {
4166 dev_err(dev, "missing reg-names property, expected %d strings\n",
4167 nbases);
4168 return -EINVAL;
4169 }
4170
4171 for (i = 0; i < nbases; i++) {
4172 of_property_read_string_index(dev->of_node, "reg-names", i,
4173 &str);
4174 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, str);
4175 if (!res) {
4176 dev_err(dev, "Unable to retrieve register base.\n");
4177 return -ENOMEM;
4178 }
4179
4180 virt_bases[i] = devm_ioremap(dev, res->start,
4181 resource_size(res));
4182 if (!virt_bases[i]) {
4183 dev_err(dev, "Failed to map in CC registers.\n");
4184 return -ENOMEM;
4185 }
4186 }
4187
4188 return 0;
4189}
4190
4191static const struct msm_reset_map gcc_8952_resets[] = {
4192 [GCC_CAMSS_MICRO_BCR] = {0x56008},
4193 [GCC_USB_FS_BCR] = {0x3F000},
4194 [GCC_USB_HS_BCR] = {0x41000},
4195 [GCC_USB2_HS_PHY_ONLY_BCR] = {0x41034},
4196 [GCC_QUSB2_PHY_BCR] = {0x4103C},
4197};
4198
4199static void override_for_8917(int speed_bin)
4200{
4201 gpll3_clk_src.c.rate = 930000000;
4202
4203 OVERRIDE_FMAX3(csi0,
4204 LOWER, 100000000, LOW, 200000000, NOMINAL, 266670000);
4205 /* Frequency Table same as 8937 */
4206 OVERRIDE_FTABLE(csi0, ftbl_gcc_camss_csi0_2_clk, 8937);
4207 OVERRIDE_FMAX3(csi1,
4208 LOWER, 100000000, LOW, 200000000, NOMINAL, 266670000);
4209 /* Frequency Table same as 8937 */
4210 OVERRIDE_FTABLE(csi1, ftbl_gcc_camss_csi0_2_clk, 8937);
4211 OVERRIDE_FMAX3(csi2,
4212 LOWER, 100000000, LOW, 200000000, NOMINAL, 266670000);
4213 /* Frequency Table same as 8937 */
4214 OVERRIDE_FTABLE(csi2, ftbl_gcc_camss_csi0_2_clk, 8937);
4215
4216 OVERRIDE_FMAX5(vfe0,
4217 LOWER, 160000000, LOW, 266670000, NOMINAL, 320000000,
4218 NOM_PLUS, 329140000, HIGH, 360000000);
4219 OVERRIDE_FTABLE(vfe0, ftbl_gcc_camss_vfe0_1_clk, 8917);
4220 OVERRIDE_FMAX5(vfe1,
4221 LOWER, 160000000, LOW, 266670000, NOMINAL, 320000000,
4222 NOM_PLUS, 329140000, HIGH, 360000000);
4223 OVERRIDE_FTABLE(vfe1, ftbl_gcc_camss_vfe0_1_clk, 8917);
4224 OVERRIDE_FTABLE(vcodec0, ftbl_gcc_venus0_vcodec0_clk, 8917);
4225 OVERRIDE_FMAX5(vcodec0,
4226 LOWER, 200000000, LOW, 270000000, NOMINAL, 308570000,
4227 NOM_PLUS, 329140000, HIGH, 360000000);
4228 OVERRIDE_FMAX4(cpp,
4229 LOWER, 160000000, LOW, 266670000, NOMINAL, 320000000,
4230 NOM_PLUS, 360000000);
4231 OVERRIDE_FTABLE(cpp, ftbl_gcc_camss_cpp_clk, 8917);
4232 OVERRIDE_FMAX5(jpeg0,
4233 LOWER, 133330000, LOW, 200000000, NOMINAL, 266670000,
4234 NOM_PLUS, 308570000, HIGH, 320000000);
4235 /* Frequency Table same as 8937 */
4236 OVERRIDE_FTABLE(jpeg0, ftbl_gcc_camss_jpeg0_clk, 8937);
4237
4238 if (speed_bin) {
4239 OVERRIDE_FMAX5(gfx3d,
4240 LOWER, 270000000, LOW, 400000000, NOMINAL, 484800000,
4241 NOM_PLUS, 523200000, HIGH, 650000000);
4242 OVERRIDE_FTABLE(gfx3d, ftbl_gcc_oxili_gfx3d_clk, 8917_650MHz);
4243 } else {
4244 OVERRIDE_FMAX5(gfx3d,
4245 LOWER, 270000000, LOW, 400000000, NOMINAL, 484800000,
4246 NOM_PLUS, 523200000, HIGH, 598000000);
4247 OVERRIDE_FTABLE(gfx3d, ftbl_gcc_oxili_gfx3d_clk, 8917);
4248 }
4249
4250 OVERRIDE_FMAX1(cci, LOWER, 37500000);
4251
4252 OVERRIDE_FTABLE(csi0phytimer, ftbl_gcc_camss_csi0_1phytimer_clk, 8917);
4253 OVERRIDE_FMAX3(csi0phytimer, LOWER, 100000000, LOW, 200000000,
4254 NOMINAL, 266670000);
4255 OVERRIDE_FTABLE(csi1phytimer, ftbl_gcc_camss_csi0_1phytimer_clk, 8917);
4256 OVERRIDE_FMAX3(csi1phytimer, LOWER, 100000000, LOW, 200000000,
4257 NOMINAL, 266670000);
4258 OVERRIDE_FMAX2(gp1, LOWER, 100000000, NOMINAL, 200000000);
4259 OVERRIDE_FMAX2(gp2, LOWER, 100000000, NOMINAL, 200000000);
4260 OVERRIDE_FMAX2(gp3, LOWER, 100000000, NOMINAL, 200000000);
4261
4262 OVERRIDE_FMAX2(byte0, LOWER, 125000000, NOMINAL, 187500000);
4263 /* Frequency Table same as 8937 */
4264 OVERRIDE_FTABLE(byte0, ftbl_gcc_mdss_byte0_clk, 8937);
4265 byte0_clk_src.current_freq = ftbl_gcc_mdss_pclk0_clk_8937;
4266
4267 OVERRIDE_FMAX2(pclk0, LOWER, 166670000, NOMINAL, 250000000);
4268 /* Frequency Table same as 8937 */
4269 OVERRIDE_FTABLE(pclk0, ftbl_gcc_mdss_pclk0_clk, 8937);
4270 pclk0_clk_src.current_freq = ftbl_gcc_mdss_pclk0_clk_8937;
4271
4272 OVERRIDE_FMAX2(sdcc1_apps, LOWER, 200000000, NOMINAL, 400000000);
4273 OVERRIDE_FTABLE(usb_hs_system, ftbl_gcc_usb_hs_system_clk, 8917);
4274 OVERRIDE_FMAX3(usb_hs_system, LOWER, 800000000, NOMINAL, 133333000,
4275 HIGH, 177780000);
4276}
4277
4278static void override_for_8937(int speed_bin)
4279{
4280 gpll3_clk_src.c.rate = 900000000;
4281 gpll3_clk_src.vco_tbl = p_vco_8937;
4282 gpll3_clk_src.num_vco = ARRAY_SIZE(p_vco_8937);
4283 OVERRIDE_FMAX2(gpll3, LOW, 800000000, NOMINAL, 1066000000);
4284
4285 OVERRIDE_FMAX1(cci, LOWER, 37500000);
4286 OVERRIDE_FMAX3(csi0,
4287 LOWER, 100000000, LOW, 200000000, NOMINAL, 266670000);
4288 OVERRIDE_FTABLE(csi0, ftbl_gcc_camss_csi0_2_clk, 8937);
4289 OVERRIDE_FMAX3(csi1,
4290 LOWER, 100000000, LOW, 200000000, NOMINAL, 266670000);
4291 OVERRIDE_FTABLE(csi1, ftbl_gcc_camss_csi0_2_clk, 8937);
4292 OVERRIDE_FMAX3(csi2,
4293 LOWER, 100000000, LOW, 200000000, NOMINAL, 266670000);
4294 OVERRIDE_FTABLE(csi2, ftbl_gcc_camss_csi0_2_clk, 8937);
4295 OVERRIDE_FMAX4(vfe0,
4296 LOWER, 160000000, LOW, 308570000, NOMINAL, 400000000,
4297 NOM_PLUS, 432000000);
4298 OVERRIDE_FTABLE(vfe0, ftbl_gcc_camss_vfe0_1_clk, 8937);
4299 OVERRIDE_FMAX4(vfe1,
4300 LOWER, 160000000, LOW, 308570000, NOMINAL, 400000000,
4301 NOM_PLUS, 432000000);
4302 OVERRIDE_FTABLE(vfe1, ftbl_gcc_camss_vfe0_1_clk, 8937);
4303
4304 if (speed_bin) {
4305 OVERRIDE_FMAX6(gfx3d,
4306 LOWER, 216000000, LOW, 300000000,
4307 NOMINAL, 375000000, NOM_PLUS, 400000000,
4308 HIGH, 450000000, SUPER_TUR, 475000000);
4309 OVERRIDE_FTABLE(gfx3d, ftbl_gcc_oxili_gfx3d_clk, 8937_475MHz);
4310 } else {
4311 OVERRIDE_FMAX5(gfx3d,
4312 LOWER, 216000000, LOW, 300000000,
4313 NOMINAL, 375000000, NOM_PLUS, 400000000,
4314 HIGH, 450000000);
4315 OVERRIDE_FTABLE(gfx3d, ftbl_gcc_oxili_gfx3d_clk, 8937);
4316 }
4317
4318 OVERRIDE_FMAX5(cpp,
4319 LOWER, 160000000, LOW, 266670000, NOMINAL, 320000000,
4320 NOM_PLUS, 342860000, HIGH, 360000000);
4321 OVERRIDE_FTABLE(cpp, ftbl_gcc_camss_cpp_clk, 8937);
4322 OVERRIDE_FMAX5(jpeg0,
4323 LOWER, 133330000, LOW, 200000000, NOMINAL, 266670000,
4324 NOM_PLUS, 308570000, HIGH, 320000000);
4325 OVERRIDE_FTABLE(jpeg0, ftbl_gcc_camss_jpeg0_clk, 8937);
4326 OVERRIDE_FMAX2(csi0phytimer, LOWER, 100000000, LOW, 200000000);
4327 OVERRIDE_FMAX2(csi1phytimer, LOWER, 100000000, LOW, 200000000);
4328 OVERRIDE_FMAX2(gp1, LOWER, 100000000, NOMINAL, 200000000);
4329 OVERRIDE_FMAX2(gp2, LOWER, 100000000, NOMINAL, 200000000);
4330 OVERRIDE_FMAX2(gp3, LOWER, 100000000, NOMINAL, 200000000);
4331 OVERRIDE_FMAX2(byte0, LOWER, 125000000, NOMINAL, 187500000);
4332 OVERRIDE_FTABLE(byte0, ftbl_gcc_mdss_byte0_clk, 8937);
4333 OVERRIDE_FMAX2(byte1, LOWER, 125000000, NOMINAL, 187500000);
4334 byte0_clk_src.current_freq = ftbl_gcc_mdss_byte0_clk_8937;
4335 OVERRIDE_FMAX2(pclk0, LOWER, 166670000, NOMINAL, 250000000);
4336 OVERRIDE_FTABLE(pclk0, ftbl_gcc_mdss_pclk0_clk, 8937);
4337 OVERRIDE_FMAX2(pclk1, LOWER, 166670000, NOMINAL, 250000000);
4338 pclk0_clk_src.current_freq = ftbl_gcc_mdss_pclk0_clk_8937;
4339 OVERRIDE_FTABLE(vcodec0, ftbl_gcc_venus0_vcodec0_clk, 8937);
4340 OVERRIDE_FMAX5(vcodec0,
4341 LOWER, 166150000, LOW, 240000000, NOMINAL, 308570000,
4342 NOM_PLUS, 320000000, HIGH, 360000000);
4343 OVERRIDE_FMAX2(sdcc1_apps, LOWER, 100000000,
4344 NOMINAL, 400000000);
4345}
4346
4347static void get_speed_bin(struct platform_device *pdev, int *bin)
4348{
4349 struct resource *res;
4350 void __iomem *base;
4351 u32 config_efuse;
4352
4353 *bin = 0;
4354
4355 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "efuse");
4356 if (!res) {
4357 dev_info(&pdev->dev,
4358 "No GPU speed binning available. Defaulting to 0.\n");
4359 return;
4360 }
4361
4362 base = devm_ioremap(&pdev->dev, res->start, resource_size(res));
4363 if (!base) {
4364 dev_warn(&pdev->dev,
4365 "Unable to ioremap efuse reg address. Defaulting to 0.\n");
4366 return;
4367 }
4368
4369 config_efuse = readl_relaxed(base);
4370 devm_iounmap(&pdev->dev, base);
4371 *bin = (config_efuse >> 31) & 0x1;
4372
4373 dev_info(&pdev->dev, "GPU speed bin: %d\n", *bin);
4374}
4375
4376static int msm_gcc_probe(struct platform_device *pdev)
4377{
4378 struct resource *res;
4379 int ret;
4380 int speed_bin;
4381 u32 regval, nbases = N_BASES;
4382 bool compat_bin = false;
4383 bool compat_bin2 = false;
4384 bool compat_bin3 = false;
4385 bool compat_bin4 = false;
Odelu Kukatla678382b2018-03-27 22:58:52 +0530[diff] [blame]4386 bool compat_bin5 = false;
4387 bool compat_bin6 = false;
Shefali Jain79729af2018-01-29 15:15:20 +0530[diff] [blame]4388
4389 compat_bin = of_device_is_compatible(pdev->dev.of_node,
4390 "qcom,gcc-8937");
4391
4392 compat_bin2 = of_device_is_compatible(pdev->dev.of_node,
4393 "qcom,gcc-8917");
4394
4395 compat_bin3 = of_device_is_compatible(pdev->dev.of_node,
4396 "qcom,gcc-8940");
4397
4398 compat_bin4 = of_device_is_compatible(pdev->dev.of_node,
4399 "qcom,gcc-8920");
4400
Odelu Kukatla678382b2018-03-27 22:58:52 +0530[diff] [blame]4401 compat_bin5 = of_device_is_compatible(pdev->dev.of_node,
4402 "qcom,gcc-sdm429");
4403
4404 compat_bin6 = of_device_is_compatible(pdev->dev.of_node,
4405 "qcom,gcc-sdm439");
4406
Shefali Jain79729af2018-01-29 15:15:20 +0530[diff] [blame]4407 ret = vote_bimc(&bimc_clk, INT_MAX);
4408 if (ret < 0)
4409 return ret;
4410
Odelu Kukatla678382b2018-03-27 22:58:52 +0530[diff] [blame]4411 if (compat_bin2 || compat_bin4 || compat_bin5)
Shefali Jain79729af2018-01-29 15:15:20 +0530[diff] [blame]4412 nbases = APCS_C0_PLL_BASE;
4413
Odelu Kukatla3e82fd32018-06-05 12:08:53 +0530[diff] [blame]4414 if (compat_bin5 || compat_bin6) {
4415 a53ss_c0_pll.c.ops = &clk_ops_acpu_pll;
4416 a53ss_c1_pll.c.ops = &clk_ops_acpu_pll;
4417 }
4418
Shefali Jain79729af2018-01-29 15:15:20 +0530[diff] [blame]4419 ret = get_mmio_addr(pdev, nbases);
4420 if (ret)
4421 return ret;
4422
4423 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "cc_base");
4424 if (!res) {
4425 dev_err(&pdev->dev, "Register base not defined\n");
4426 return -ENOMEM;
4427 }
4428
4429 virt_bases[GCC_BASE] = devm_ioremap(&pdev->dev, res->start,
4430 resource_size(res));
4431 if (!virt_bases[GCC_BASE]) {
4432 dev_err(&pdev->dev, "Failed to ioremap CC registers\n");
4433 return -ENOMEM;
4434 }
4435
4436 vdd_dig.regulator[0] = devm_regulator_get(&pdev->dev, "vdd_dig");
4437 if (IS_ERR(vdd_dig.regulator[0])) {
4438 if (!(PTR_ERR(vdd_dig.regulator[0]) == -EPROBE_DEFER))
4439 dev_err(&pdev->dev,
4440 "Unable to get vdd_dig regulator!!!\n");
4441 return PTR_ERR(vdd_dig.regulator[0]);
4442 }
4443
Odelu Kukatla678382b2018-03-27 22:58:52 +0530[diff] [blame]4444 if (!compat_bin2 && !compat_bin4 && !compat_bin5) {
Shefali Jain79729af2018-01-29 15:15:20 +0530[diff] [blame]4445 vdd_sr2_pll.regulator[0] = devm_regulator_get(&pdev->dev,
4446 "vdd_sr2_pll");
4447 if (IS_ERR(vdd_sr2_pll.regulator[0])) {
4448 if (PTR_ERR(vdd_sr2_pll.regulator[0]) != -EPROBE_DEFER)
4449 dev_err(&pdev->dev,
4450 "Unable to get vdd_sr2_pll regulator!!!\n");
4451 return PTR_ERR(vdd_sr2_pll.regulator[0]);
4452 }
4453
4454 vdd_sr2_pll.regulator[1] = devm_regulator_get(&pdev->dev,
4455 "vdd_sr2_dig");
4456 if (IS_ERR(vdd_sr2_pll.regulator[1])) {
4457 if (PTR_ERR(vdd_sr2_pll.regulator[1]) != -EPROBE_DEFER)
4458 dev_err(&pdev->dev,
4459 "Unable to get vdd_sr2_dig regulator!!!\n");
4460 return PTR_ERR(vdd_sr2_pll.regulator[1]);
4461 }
4462 }
4463
4464 vdd_hf_pll.regulator[0] = devm_regulator_get(&pdev->dev,
4465 "vdd_hf_pll");
4466 if (IS_ERR(vdd_hf_pll.regulator[0])) {
4467 if (PTR_ERR(vdd_hf_pll.regulator[0]) != -EPROBE_DEFER)
4468 dev_err(&pdev->dev,
4469 "Unable to get vdd_sr2_pll regulator!!!\n");
4470 return PTR_ERR(vdd_hf_pll.regulator[0]);
4471 }
4472
4473 vdd_hf_pll.regulator[1] = devm_regulator_get(&pdev->dev,
4474 "vdd_hf_dig");
4475 if (IS_ERR(vdd_hf_pll.regulator[1])) {
4476 if (PTR_ERR(vdd_hf_pll.regulator[1]) != -EPROBE_DEFER)
4477 dev_err(&pdev->dev,
4478 "Unable to get vdd_hf_dig regulator!!!\n");
4479 return PTR_ERR(vdd_hf_pll.regulator[1]);
4480 }
4481
4482 /* Vote for GPLL0 to turn on. Needed by acpuclock. */
4483 regval = readl_relaxed(GCC_REG_BASE(APCS_GPLL_ENA_VOTE));
4484 regval |= BIT(0);
4485 writel_relaxed(regval, GCC_REG_BASE(APCS_GPLL_ENA_VOTE));
4486
Odelu Kukatla678382b2018-03-27 22:58:52 +0530[diff] [blame]4487 if (compat_bin || compat_bin3 || compat_bin5 || compat_bin6) {
Shefali Jain79729af2018-01-29 15:15:20 +0530[diff] [blame]4488 gpll0_clk_src.c.parent = &gpll0_clk_src_8937.c;
4489 gpll0_ao_clk_src.c.parent = &gpll0_ao_clk_src_8937.c;
4490 /* Oxili Ocmem in GX rail: OXILI_GMEM_CLAMP_IO */
4491 regval = readl_relaxed(GCC_REG_BASE(GX_DOMAIN_MISC));
4492 regval &= ~BIT(0);
4493 writel_relaxed(regval, GCC_REG_BASE(GX_DOMAIN_MISC));
Odelu Kukatla678382b2018-03-27 22:58:52 +0530[diff] [blame]4494
4495 if (compat_bin5 || compat_bin6)
4496 speed_bin = 0;
4497 else
4498 get_speed_bin(pdev, &speed_bin);
4499
Shefali Jain79729af2018-01-29 15:15:20 +0530[diff] [blame]4500 override_for_8937(speed_bin);
4501
Odelu Kukatla678382b2018-03-27 22:58:52 +0530[diff] [blame]4502 if (compat_bin5 || compat_bin6) {
4503 vdd_dig.num_levels = VDD_DIG_NUM_439;
4504 vdd_dig.cur_level = VDD_DIG_NUM_439;
4505 vdd_sr2_pll.num_levels = VDD_SR2_PLL_NUM_439;
4506 vdd_sr2_pll.cur_level = VDD_SR2_PLL_NUM_439;
4507 vdd_hf_pll.num_levels = VDD_HF_PLL_NUM_439;
4508 vdd_hf_pll.cur_level = VDD_HF_PLL_NUM_439;
4509
Odelu Kukatlaff4c6a02018-06-28 12:45:16 +0530[diff] [blame]4510 gpll3_clk_src.test_ctl_hi_val = 0x400000;
Odelu Kukatla678382b2018-03-27 22:58:52 +0530[diff] [blame]4511 gpll3_clk_src.vco_tbl = p_vco;
4512 gpll3_clk_src.num_vco = ARRAY_SIZE(p_vco);
4513 gpll3_clk_src.c.fmax[VDD_DIG_LOW] = 800000000;
4514 gpll3_clk_src.c.fmax[VDD_DIG_NOMINAL] = 1400000000;
4515 gfx3d_clk_src.freq_tbl =
4516 ftbl_gcc_oxili_gfx3d_clk_sdm439;
4517
4518 gfx3d_clk_src.c.fmax[VDD_DIG_LOWER] = 320000000;
4519 gfx3d_clk_src.c.fmax[VDD_DIG_LOW] = 400000000;
4520 gfx3d_clk_src.c.fmax[VDD_DIG_NOMINAL] = 510000000;
4521 gfx3d_clk_src.c.fmax[VDD_DIG_NOM_PLUS] = 560000000;
4522 gfx3d_clk_src.c.fmax[VDD_DIG_HIGH] = 650000000;
4523 }
4524
Shefali Jain79729af2018-01-29 15:15:20 +0530[diff] [blame]4525 if (compat_bin3) {
4526 if (speed_bin) {
4527 gfx3d_clk_src.freq_tbl =
4528 ftbl_gcc_oxili_gfx3d_clk_8940_500MHz;
4529 gfx3d_clk_src.c.fmax[VDD_DIG_SUPER_TUR] =
4530 500000000;
4531 } else {
4532 gfx3d_clk_src.freq_tbl =
4533 ftbl_gcc_oxili_gfx3d_clk_8937_475MHz;
4534 gfx3d_clk_src.c.fmax[VDD_DIG_SUPER_TUR] =
4535 475000000;
4536 }
4537 }
4538 } else if (compat_bin2 || compat_bin4) {
4539 gpll0_clk_src.c.parent = &gpll0_clk_src_8937.c;
4540 gpll0_ao_clk_src.c.parent = &gpll0_ao_clk_src_8937.c;
4541 vdd_dig.num_levels = VDD_DIG_NUM_8917;
4542 vdd_dig.cur_level = VDD_DIG_NUM_8917;
4543 vdd_hf_pll.num_levels = VDD_HF_PLL_NUM_8917;
4544 vdd_hf_pll.cur_level = VDD_HF_PLL_NUM_8917;
4545 get_speed_bin(pdev, &speed_bin);
4546 override_for_8917(speed_bin);
4547
4548 if (compat_bin2) {
4549 blsp1_qup2_spi_apps_clk_src.freq_tbl =
4550 ftbl_gcc_blsp1_2_qup1_4_spi_apps_clk_8917;
4551 blsp1_qup3_spi_apps_clk_src.freq_tbl =
4552 ftbl_gcc_blsp1_2_qup1_4_spi_apps_clk_8917;
4553 blsp1_qup4_spi_apps_clk_src.freq_tbl =
4554 ftbl_gcc_blsp1_2_qup1_4_spi_apps_clk_8917;
4555 blsp2_qup1_spi_apps_clk_src.freq_tbl =
4556 ftbl_gcc_blsp1_2_qup1_4_spi_apps_clk_8917;
4557 blsp2_qup2_spi_apps_clk_src.freq_tbl =
4558 ftbl_gcc_blsp1_2_qup1_4_spi_apps_clk_8917;
4559 blsp2_qup3_spi_apps_clk_src.freq_tbl =
4560 ftbl_gcc_blsp1_2_qup1_4_spi_apps_clk_8917;
4561 }
4562 } else {
4563 gpll0_clk_src.c.parent = &gpll0_clk_src_8952.c;
4564 gpll0_ao_clk_src.c.parent = &gpll0_ao_clk_src_8952.c;
4565 }
4566
4567 ret = of_msm_clock_register(pdev->dev.of_node,
4568 msm_clocks_lookup_common,
4569 ARRAY_SIZE(msm_clocks_lookup_common));
4570 if (ret)
4571 return ret;
4572
Odelu Kukatla678382b2018-03-27 22:58:52 +0530[diff] [blame]4573 if (compat_bin || compat_bin6)
Shefali Jain79729af2018-01-29 15:15:20 +0530[diff] [blame]4574 ret = of_msm_clock_register(pdev->dev.of_node,
4575 msm_clocks_lookup_8937,
4576 ARRAY_SIZE(msm_clocks_lookup_8937));
4577 else if (compat_bin2)
4578 ret = of_msm_clock_register(pdev->dev.of_node,
4579 msm_clocks_lookup_8917,
4580 ARRAY_SIZE(msm_clocks_lookup_8917));
4581 else if (compat_bin3)
4582 ret = of_msm_clock_register(pdev->dev.of_node,
4583 msm_clocks_lookup_8940,
4584 ARRAY_SIZE(msm_clocks_lookup_8940));
4585 else if (compat_bin4)
4586 ret = of_msm_clock_register(pdev->dev.of_node,
4587 msm_clocks_lookup_8920,
4588 ARRAY_SIZE(msm_clocks_lookup_8920));
Odelu Kukatla678382b2018-03-27 22:58:52 +0530[diff] [blame]4589 else if (compat_bin5)
4590 ret = of_msm_clock_register(pdev->dev.of_node,
4591 msm_clocks_lookup_sdm429,
4592 ARRAY_SIZE(msm_clocks_lookup_sdm429));
Shefali Jain79729af2018-01-29 15:15:20 +0530[diff] [blame]4593 else
4594 ret = of_msm_clock_register(pdev->dev.of_node,
4595 msm_clocks_lookup_8952,
4596 ARRAY_SIZE(msm_clocks_lookup_8952));
4597 if (ret)
4598 return ret;
4599
4600 ret = enable_rpm_scaling();
4601 if (ret)
4602 return ret;
4603
4604 clk_set_rate(&apss_ahb_clk_src.c, 19200000);
4605 clk_prepare_enable(&apss_ahb_clk_src.c);
4606
4607 /*
4608 * Hold an active set vote for PCNOC AHB source. Sleep set vote is 0.
4609 */
4610 clk_set_rate(&pnoc_keepalive_a_clk.c, 19200000);
4611 clk_prepare_enable(&pnoc_keepalive_a_clk.c);
4612
4613 clk_prepare_enable(&xo_a_clk_src.c);
Shefali Jain79729af2018-01-29 15:15:20 +0530[diff] [blame]4614
Odelu Kukatla678382b2018-03-27 22:58:52 +0530[diff] [blame]4615 if (!compat_bin && !compat_bin3 && !compat_bin5 && !compat_bin6) {
Shefali Jain79729af2018-01-29 15:15:20 +0530[diff] [blame]4616 /* Configure Sleep and Wakeup cycles for GMEM clock */
4617 regval = readl_relaxed(GCC_REG_BASE(OXILI_GMEM_CBCR));
4618 regval ^= 0xFF0;
4619 regval |= CLKFLAG_WAKEUP_CYCLES << 8;
4620 regval |= CLKFLAG_SLEEP_CYCLES << 4;
4621 writel_relaxed(regval, GCC_REG_BASE(OXILI_GMEM_CBCR));
4622 } else {
4623 /* Configure Sleep and Wakeup cycles for OXILI clock */
4624 regval = readl_relaxed(GCC_REG_BASE(OXILI_GFX3D_CBCR));
4625 regval &= ~0xF0;
4626 regval |= CLKFLAG_SLEEP_CYCLES << 4;
4627 writel_relaxed(regval, GCC_REG_BASE(OXILI_GFX3D_CBCR));
4628 }
4629
4630 ret = of_platform_populate(pdev->dev.of_node, NULL, NULL, &pdev->dev);
4631 if (ret)
4632 return ret;
4633
4634 msm_reset_controller_register(pdev, gcc_8952_resets,
4635 ARRAY_SIZE(gcc_8952_resets), virt_bases[GCC_BASE]);
4636
4637 dev_info(&pdev->dev, "Registered GCC clocks\n");
4638
4639 return 0;
4640}
4641
4642static const struct of_device_id msm_clock_gcc_match_table[] = {
4643 { .compatible = "qcom,gcc-8952" },
4644 { .compatible = "qcom,gcc-8937" },
4645 { .compatible = "qcom,gcc-8917" },
4646 { .compatible = "qcom,gcc-8940" },
4647 { .compatible = "qcom,gcc-8920" },
Odelu Kukatla678382b2018-03-27 22:58:52 +0530[diff] [blame]4648 { .compatible = "qcom,gcc-sdm439" },
4649 { .compatible = "qcom,gcc-sdm429" },
Shefali Jain79729af2018-01-29 15:15:20 +0530[diff] [blame]4650 {}
4651};
4652
4653static struct platform_driver msm_clock_gcc_driver = {
4654 .probe = msm_gcc_probe,
4655 .driver = {
4656 .name = "qcom,gcc-8952",
4657 .of_match_table = msm_clock_gcc_match_table,
4658 .owner = THIS_MODULE,
4659 },
4660};
4661
4662static int msm_gcc_spm_probe(struct platform_device *pdev)
4663{
4664 struct resource *res = NULL;
4665 bool compat_bin = false;
4666
4667 compat_bin = of_device_is_compatible(pdev->dev.of_node,
4668 "qcom,spm-8952");
4669
4670 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "spm_c0_base");
4671 if (!res) {
4672 dev_err(&pdev->dev, "SPM register base not defined for c0\n");
4673 return -ENOMEM;
4674 }
4675
4676 a53ss_c0_pll.spm_ctrl.spm_base = devm_ioremap(&pdev->dev, res->start,
4677 resource_size(res));
4678 if (!a53ss_c0_pll.spm_ctrl.spm_base) {
4679 dev_err(&pdev->dev, "Failed to ioremap c0 spm registers\n");
4680 return -ENOMEM;
4681 }
4682
4683 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "spm_c1_base");
4684 if (!res) {
4685 dev_err(&pdev->dev, "SPM register base not defined for c1\n");
4686 return -ENOMEM;
4687 }
4688
4689 a53ss_c1_pll.spm_ctrl.spm_base = devm_ioremap(&pdev->dev, res->start,
4690 resource_size(res));
4691 if (!a53ss_c1_pll.spm_ctrl.spm_base) {
4692 dev_err(&pdev->dev, "Failed to ioremap c1 spm registers\n");
4693 return -ENOMEM;
4694 }
4695
4696 if (compat_bin) {
4697 res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
4698 "spm_cci_base");
4699 if (!res) {
4700 dev_err(&pdev->dev, "SPM register base not defined for cci\n");
4701 return -ENOMEM;
4702 }
4703
4704 a53ss_cci_pll.spm_ctrl.spm_base = devm_ioremap(&pdev->dev,
4705 res->start, resource_size(res));
4706 if (!a53ss_cci_pll.spm_ctrl.spm_base) {
4707 dev_err(&pdev->dev, "Failed to ioremap cci spm registers\n");
4708 return -ENOMEM;
4709 }
4710 }
4711
4712 dev_info(&pdev->dev, "Registered GCC SPM clocks\n");
4713
4714 return 0;
4715}
4716
4717static const struct of_device_id msm_clock_spm_match_table[] = {
4718 { .compatible = "qcom,gcc-spm-8952" },
4719 { .compatible = "qcom,gcc-spm-8937" },
4720 {}
4721};
4722
4723static struct platform_driver msm_clock_spm_driver = {
4724 .probe = msm_gcc_spm_probe,
4725 .driver = {
4726 .name = "qcom,gcc-spm-8952",
4727 .of_match_table = msm_clock_spm_match_table,
4728 .owner = THIS_MODULE,
4729 },
4730};
4731
4732static int __init msm_gcc_init(void)
4733{
4734 int ret;
4735
4736 ret = platform_driver_register(&msm_clock_gcc_driver);
4737 if (!ret)
4738 ret = platform_driver_register(&msm_clock_spm_driver);
4739
4740 return ret;
4741}
4742
4743static struct clk_lookup msm_clocks_measure[] = {
4744 CLK_LOOKUP_OF("measure", gcc_debug_mux, "debug"),
4745 CLK_LIST(apss_debug_pri_mux),
4746 CLK_LIST(apc0_m_clk),
4747 CLK_LIST(apc1_m_clk),
4748 CLK_LIST(cci_m_clk),
4749};
4750
4751static struct clk_lookup msm_clocks_measure_8937[] = {
4752 CLK_LOOKUP_OF("measure", gcc_debug_mux_8937, "debug"),
4753 CLK_LIST(apss_debug_pri_mux),
4754 CLK_LIST(apc0_m_clk),
4755 CLK_LIST(apc1_m_clk),
4756 CLK_LIST(cci_m_clk),
4757};
4758
4759static int msm_clock_debug_probe(struct platform_device *pdev)
4760{
4761 int ret;
4762 struct resource *res;
4763 bool compat_bin = false, compat_bin2 = false;
4764 bool compat_bin3 = false;
4765 bool compat_bin4 = false;
4766
4767 compat_bin = of_device_is_compatible(pdev->dev.of_node,
4768 "qcom,cc-debug-8937");
4769
4770 compat_bin2 = of_device_is_compatible(pdev->dev.of_node,
4771 "qcom,cc-debug-8917");
4772
4773 compat_bin3 = of_device_is_compatible(pdev->dev.of_node,
4774 "qcom,cc-debug-8940");
4775
4776 compat_bin4 = of_device_is_compatible(pdev->dev.of_node,
4777 "qcom,cc-debug-8920");
4778
4779 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "meas");
4780 if (!res) {
4781 dev_err(&pdev->dev, "GLB clock diag base not defined.\n");
4782 return -EINVAL;
4783 }
4784
4785 meas_base = devm_ioremap(&pdev->dev, res->start, resource_size(res));
4786 if (!meas_base) {
4787 dev_err(&pdev->dev, "Unable to map GLB clock diag base.\n");
4788 return -ENOMEM;
4789 }
4790
4791 clk_ops_debug_mux = clk_ops_gen_mux;
4792 clk_ops_debug_mux.get_rate = measure_get_rate;
4793
4794 if (compat_bin2)
4795 gcc_debug_mux_8937.post_div = 0x3;
4796
4797 if (!compat_bin && !compat_bin2 && !compat_bin3 && !compat_bin4)
4798 ret = of_msm_clock_register(pdev->dev.of_node,
4799 msm_clocks_measure, ARRAY_SIZE(msm_clocks_measure));
4800 else
4801 ret = of_msm_clock_register(pdev->dev.of_node,
4802 msm_clocks_measure_8937,
4803 ARRAY_SIZE(msm_clocks_measure_8937));
4804 if (ret) {
4805 dev_err(&pdev->dev, "Failed to register debug Mux\n");
4806 return ret;
4807 }
4808
4809 dev_info(&pdev->dev, "Registered Debug Mux successfully\n");
4810 return ret;
4811}
4812
4813static const struct of_device_id msm_clock_debug_match_table[] = {
4814 { .compatible = "qcom,cc-debug-8952" },
4815 { .compatible = "qcom,cc-debug-8937" },
4816 { .compatible = "qcom,cc-debug-8917" },
4817 { .compatible = "qcom,cc-debug-8940" },
4818 { .compatible = "qcom,cc-debug-8920" },
4819 {}
4820};
4821
4822static struct platform_driver msm_clock_debug_driver = {
4823 .probe = msm_clock_debug_probe,
4824 .driver = {
4825 .name = "qcom,cc-debug-8952",
4826 .of_match_table = msm_clock_debug_match_table,
4827 .owner = THIS_MODULE,
4828 },
4829};
4830
4831static int __init msm_clock_debug_init(void)
4832{
4833 return platform_driver_register(&msm_clock_debug_driver);
4834}
4835
4836/* MDSS DSI_PHY_PLL */
4837static struct clk_lookup msm_clocks_gcc_mdss_common[] = {
4838 CLK_LIST(ext_pclk0_clk_src),
4839 CLK_LIST(ext_byte0_clk_src),
4840 CLK_LIST(byte0_clk_src),
4841 CLK_LIST(pclk0_clk_src),
4842 CLK_LIST(gcc_mdss_pclk0_clk),
4843 CLK_LIST(gcc_mdss_byte0_clk),
4844 CLK_LIST(mdss_mdp_vote_clk),
4845 CLK_LIST(mdss_rotator_vote_clk),
4846};
4847
4848static struct clk_lookup msm_clocks_gcc_mdss_8937[] = {
4849 CLK_LIST(ext_pclk1_clk_src),
4850 CLK_LIST(ext_byte1_clk_src),
4851 CLK_LIST(byte1_clk_src),
4852 CLK_LIST(pclk1_clk_src),
4853 CLK_LIST(gcc_mdss_pclk1_clk),
4854 CLK_LIST(gcc_mdss_byte1_clk),
4855};
4856
4857static int msm_gcc_mdss_probe(struct platform_device *pdev)
4858{
4859 int ret = 0;
4860 struct clk *curr_p;
4861 bool compat_bin = false;
4862
4863 compat_bin = of_device_is_compatible(pdev->dev.of_node,
4864 "qcom,gcc-mdss-8937");
4865 if (!compat_bin)
4866 compat_bin = of_device_is_compatible(pdev->dev.of_node,
4867 "qcom,gcc-mdss-8940");
4868
Padmanabhan Komanduru1853d7f2018-04-09 21:50:30 +0530[diff] [blame]4869 if (!compat_bin)
4870 compat_bin = of_device_is_compatible(pdev->dev.of_node,
4871 "qcom,gcc-mdss-sdm439");
4872
4873 if (!compat_bin)
4874 compat_bin = of_device_is_compatible(pdev->dev.of_node,
4875 "qcom,gcc-mdss-sdm429");
4876
Shefali Jain79729af2018-01-29 15:15:20 +0530[diff] [blame]4877 curr_p = ext_pclk0_clk_src.c.parent = devm_clk_get(&pdev->dev,
4878 "pclk0_src");
4879 if (IS_ERR(curr_p)) {
4880 dev_err(&pdev->dev, "Failed to get pclk0 source.\n");
4881 return PTR_ERR(curr_p);
4882 }
4883
4884 curr_p = ext_byte0_clk_src.c.parent = devm_clk_get(&pdev->dev,
4885 "byte0_src");
4886 if (IS_ERR(curr_p)) {
4887 dev_err(&pdev->dev, "Failed to get byte source.\n");
4888 ret = PTR_ERR(curr_p);
4889 goto byte0_fail;
4890 }
4891
4892 ext_pclk0_clk_src.c.flags = CLKFLAG_NO_RATE_CACHE;
4893 ext_byte0_clk_src.c.flags = CLKFLAG_NO_RATE_CACHE;
4894
4895 if (compat_bin) {
4896 curr_p = ext_pclk1_clk_src.c.parent = devm_clk_get(&pdev->dev,
4897 "pclk1_src");
4898 if (IS_ERR(curr_p)) {
4899 dev_err(&pdev->dev, "Failed to get pclk1 source.\n");
4900 ret = PTR_ERR(curr_p);
4901 goto fail;
4902 }
4903
4904 curr_p = ext_byte1_clk_src.c.parent = devm_clk_get(&pdev->dev,
4905 "byte1_src");
4906 if (IS_ERR(curr_p)) {
4907 dev_err(&pdev->dev, "Failed to get byte1 source.\n");
4908 ret = PTR_ERR(curr_p);
4909 goto byte1_fail;
4910 }
4911
4912 ext_pclk1_clk_src.c.flags = CLKFLAG_NO_RATE_CACHE;
4913 ext_byte1_clk_src.c.flags = CLKFLAG_NO_RATE_CACHE;
4914 }
4915
4916 ret = of_msm_clock_register(pdev->dev.of_node,
4917 msm_clocks_gcc_mdss_common,
4918 ARRAY_SIZE(msm_clocks_gcc_mdss_common));
4919 if (ret)
4920 goto fail;
4921
4922 if (compat_bin) {
4923 ret = of_msm_clock_register(pdev->dev.of_node,
4924 msm_clocks_gcc_mdss_8937,
4925 ARRAY_SIZE(msm_clocks_gcc_mdss_8937));
4926 if (ret)
4927 goto fail_8937;
4928 }
4929
4930 dev_info(&pdev->dev, "Registered GCC MDSS clocks.\n");
4931
4932 return ret;
4933fail_8937:
4934 devm_clk_put(&pdev->dev, ext_byte1_clk_src.c.parent);
4935byte1_fail:
4936 devm_clk_put(&pdev->dev, ext_pclk1_clk_src.c.parent);
4937fail:
4938 devm_clk_put(&pdev->dev, ext_byte0_clk_src.c.parent);
4939byte0_fail:
4940 devm_clk_put(&pdev->dev, ext_pclk0_clk_src.c.parent);
4941 return ret;
4942
4943}
4944
4945static const struct of_device_id msm_clock_mdss_match_table[] = {
4946 { .compatible = "qcom,gcc-mdss-8952" },
4947 { .compatible = "qcom,gcc-mdss-8937" },
4948 { .compatible = "qcom,gcc-mdss-8917" },
4949 { .compatible = "qcom,gcc-mdss-8940" },
4950 { .compatible = "qcom,gcc-mdss-8920" },
Padmanabhan Komanduru1853d7f2018-04-09 21:50:30 +0530[diff] [blame]4951 { .compatible = "qcom,gcc-mdss-sdm439" },
4952 { .compatible = "qcom,gcc-mdss-sdm429" },
Shefali Jain79729af2018-01-29 15:15:20 +0530[diff] [blame]4953 {}
4954};
4955
4956static struct platform_driver msm_clock_gcc_mdss_driver = {
4957 .probe = msm_gcc_mdss_probe,
4958 .driver = {
4959 .name = "gcc-mdss-8952",
4960 .of_match_table = msm_clock_mdss_match_table,
4961 .owner = THIS_MODULE,
4962 },
4963};
4964
4965static int __init msm_gcc_mdss_init(void)
4966{
4967 return platform_driver_register(&msm_clock_gcc_mdss_driver);
4968}
4969arch_initcall(msm_gcc_init);
4970fs_initcall_sync(msm_gcc_mdss_init);
4971late_initcall(msm_clock_debug_init);