Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 1 | /* |
Heikki Krogerus | b801479 | 2012-10-18 17:34:08 +0300 | [diff] [blame] | 2 | * Core driver for the Synopsys DesignWare DMA Controller |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 3 | * |
| 4 | * Copyright (C) 2007-2008 Atmel Corporation |
Viresh Kumar | aecb7b6 | 2011-05-24 14:04:09 +0530 | [diff] [blame] | 5 | * Copyright (C) 2010-2011 ST Microelectronics |
Andy Shevchenko | 9cade1a | 2013-06-05 15:26:45 +0300 | [diff] [blame] | 6 | * Copyright (C) 2013 Intel Corporation |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 7 | * |
| 8 | * This program is free software; you can redistribute it and/or modify |
| 9 | * it under the terms of the GNU General Public License version 2 as |
| 10 | * published by the Free Software Foundation. |
| 11 | */ |
Heikki Krogerus | b801479 | 2012-10-18 17:34:08 +0300 | [diff] [blame] | 12 | |
Viresh Kumar | 327e697 | 2012-02-01 16:12:26 +0530 | [diff] [blame] | 13 | #include <linux/bitops.h> |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 14 | #include <linux/clk.h> |
| 15 | #include <linux/delay.h> |
| 16 | #include <linux/dmaengine.h> |
| 17 | #include <linux/dma-mapping.h> |
Andy Shevchenko | f8122a8 | 2013-01-16 15:48:50 +0200 | [diff] [blame] | 18 | #include <linux/dmapool.h> |
Thierry Reding | 7331205 | 2013-01-21 11:09:00 +0100 | [diff] [blame] | 19 | #include <linux/err.h> |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 20 | #include <linux/init.h> |
| 21 | #include <linux/interrupt.h> |
| 22 | #include <linux/io.h> |
| 23 | #include <linux/mm.h> |
| 24 | #include <linux/module.h> |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 25 | #include <linux/slab.h> |
| 26 | |
Andy Shevchenko | 61a7649 | 2013-06-05 15:26:44 +0300 | [diff] [blame] | 27 | #include "../dmaengine.h" |
Andy Shevchenko | 9cade1a | 2013-06-05 15:26:45 +0300 | [diff] [blame] | 28 | #include "internal.h" |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 29 | |
| 30 | /* |
| 31 | * This supports the Synopsys "DesignWare AHB Central DMA Controller", |
| 32 | * (DW_ahb_dmac) which is used with various AMBA 2.0 systems (not all |
| 33 | * of which use ARM any more). See the "Databook" from Synopsys for |
| 34 | * information beyond what licensees probably provide. |
| 35 | * |
Andy Shevchenko | dd5720b | 2014-02-12 11:16:17 +0200 | [diff] [blame] | 36 | * The driver has been tested with the Atmel AT32AP7000, which does not |
| 37 | * support descriptor writeback. |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 38 | */ |
| 39 | |
Andy Shevchenko | 78f3c9d | 2013-07-15 15:04:38 +0300 | [diff] [blame] | 40 | static inline bool is_request_line_unset(struct dw_dma_chan *dwc) |
| 41 | { |
| 42 | return dwc->request_line == (typeof(dwc->request_line))~0; |
| 43 | } |
| 44 | |
Arnd Bergmann | f776076 | 2013-03-26 16:53:57 +0200 | [diff] [blame] | 45 | static inline void dwc_set_masters(struct dw_dma_chan *dwc) |
Andy Shevchenko | 5be10f3 | 2013-01-17 10:03:01 +0200 | [diff] [blame] | 46 | { |
Arnd Bergmann | f776076 | 2013-03-26 16:53:57 +0200 | [diff] [blame] | 47 | struct dw_dma *dw = to_dw_dma(dwc->chan.device); |
| 48 | struct dw_dma_slave *dws = dwc->chan.private; |
| 49 | unsigned char mmax = dw->nr_masters - 1; |
Andy Shevchenko | 5be10f3 | 2013-01-17 10:03:01 +0200 | [diff] [blame] | 50 | |
Andy Shevchenko | 78f3c9d | 2013-07-15 15:04:38 +0300 | [diff] [blame] | 51 | if (!is_request_line_unset(dwc)) |
| 52 | return; |
| 53 | |
| 54 | dwc->src_master = min_t(unsigned char, mmax, dwc_get_sms(dws)); |
| 55 | dwc->dst_master = min_t(unsigned char, mmax, dwc_get_dms(dws)); |
Andy Shevchenko | 5be10f3 | 2013-01-17 10:03:01 +0200 | [diff] [blame] | 56 | } |
| 57 | |
Viresh Kumar | 327e697 | 2012-02-01 16:12:26 +0530 | [diff] [blame] | 58 | #define DWC_DEFAULT_CTLLO(_chan) ({ \ |
Viresh Kumar | 327e697 | 2012-02-01 16:12:26 +0530 | [diff] [blame] | 59 | struct dw_dma_chan *_dwc = to_dw_dma_chan(_chan); \ |
| 60 | struct dma_slave_config *_sconfig = &_dwc->dma_sconfig; \ |
Andy Shevchenko | 495aea4 | 2013-01-10 11:11:41 +0200 | [diff] [blame] | 61 | bool _is_slave = is_slave_direction(_dwc->direction); \ |
Andy Shevchenko | 495aea4 | 2013-01-10 11:11:41 +0200 | [diff] [blame] | 62 | u8 _smsize = _is_slave ? _sconfig->src_maxburst : \ |
Viresh Kumar | 327e697 | 2012-02-01 16:12:26 +0530 | [diff] [blame] | 63 | DW_DMA_MSIZE_16; \ |
Andy Shevchenko | 495aea4 | 2013-01-10 11:11:41 +0200 | [diff] [blame] | 64 | u8 _dmsize = _is_slave ? _sconfig->dst_maxburst : \ |
Viresh Kumar | 327e697 | 2012-02-01 16:12:26 +0530 | [diff] [blame] | 65 | DW_DMA_MSIZE_16; \ |
Jamie Iles | f301c06 | 2011-01-21 14:11:53 +0000 | [diff] [blame] | 66 | \ |
Viresh Kumar | 327e697 | 2012-02-01 16:12:26 +0530 | [diff] [blame] | 67 | (DWC_CTLL_DST_MSIZE(_dmsize) \ |
| 68 | | DWC_CTLL_SRC_MSIZE(_smsize) \ |
Jamie Iles | f301c06 | 2011-01-21 14:11:53 +0000 | [diff] [blame] | 69 | | DWC_CTLL_LLP_D_EN \ |
| 70 | | DWC_CTLL_LLP_S_EN \ |
Arnd Bergmann | f776076 | 2013-03-26 16:53:57 +0200 | [diff] [blame] | 71 | | DWC_CTLL_DMS(_dwc->dst_master) \ |
| 72 | | DWC_CTLL_SMS(_dwc->src_master)); \ |
Jamie Iles | f301c06 | 2011-01-21 14:11:53 +0000 | [diff] [blame] | 73 | }) |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 74 | |
| 75 | /* |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 76 | * Number of descriptors to allocate for each channel. This should be |
| 77 | * made configurable somehow; preferably, the clients (at least the |
| 78 | * ones using slave transfers) should be able to give us a hint. |
| 79 | */ |
| 80 | #define NR_DESCS_PER_CHANNEL 64 |
| 81 | |
| 82 | /*----------------------------------------------------------------------*/ |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 83 | |
Dan Williams | 41d5e59 | 2009-01-06 11:38:21 -0700 | [diff] [blame] | 84 | static struct device *chan2dev(struct dma_chan *chan) |
| 85 | { |
| 86 | return &chan->dev->device; |
| 87 | } |
Dan Williams | 41d5e59 | 2009-01-06 11:38:21 -0700 | [diff] [blame] | 88 | |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 89 | static struct dw_desc *dwc_first_active(struct dw_dma_chan *dwc) |
| 90 | { |
Andy Shevchenko | e63a47a3 | 2012-10-18 17:34:12 +0300 | [diff] [blame] | 91 | return to_dw_desc(dwc->active_list.next); |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 92 | } |
| 93 | |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 94 | static struct dw_desc *dwc_desc_get(struct dw_dma_chan *dwc) |
| 95 | { |
| 96 | struct dw_desc *desc, *_desc; |
| 97 | struct dw_desc *ret = NULL; |
| 98 | unsigned int i = 0; |
Viresh Kumar | 69cea5a | 2011-04-15 16:03:35 +0530 | [diff] [blame] | 99 | unsigned long flags; |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 100 | |
Viresh Kumar | 69cea5a | 2011-04-15 16:03:35 +0530 | [diff] [blame] | 101 | spin_lock_irqsave(&dwc->lock, flags); |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 102 | list_for_each_entry_safe(desc, _desc, &dwc->free_list, desc_node) { |
Andy Shevchenko | 2ab3727 | 2012-06-19 13:34:04 +0300 | [diff] [blame] | 103 | i++; |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 104 | if (async_tx_test_ack(&desc->txd)) { |
| 105 | list_del(&desc->desc_node); |
| 106 | ret = desc; |
| 107 | break; |
| 108 | } |
Dan Williams | 41d5e59 | 2009-01-06 11:38:21 -0700 | [diff] [blame] | 109 | dev_dbg(chan2dev(&dwc->chan), "desc %p not ACKed\n", desc); |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 110 | } |
Viresh Kumar | 69cea5a | 2011-04-15 16:03:35 +0530 | [diff] [blame] | 111 | spin_unlock_irqrestore(&dwc->lock, flags); |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 112 | |
Dan Williams | 41d5e59 | 2009-01-06 11:38:21 -0700 | [diff] [blame] | 113 | dev_vdbg(chan2dev(&dwc->chan), "scanned %u descriptors on freelist\n", i); |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 114 | |
| 115 | return ret; |
| 116 | } |
| 117 | |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 118 | /* |
| 119 | * Move a descriptor, including any children, to the free list. |
| 120 | * `desc' must not be on any lists. |
| 121 | */ |
| 122 | static void dwc_desc_put(struct dw_dma_chan *dwc, struct dw_desc *desc) |
| 123 | { |
Viresh Kumar | 69cea5a | 2011-04-15 16:03:35 +0530 | [diff] [blame] | 124 | unsigned long flags; |
| 125 | |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 126 | if (desc) { |
| 127 | struct dw_desc *child; |
| 128 | |
Viresh Kumar | 69cea5a | 2011-04-15 16:03:35 +0530 | [diff] [blame] | 129 | spin_lock_irqsave(&dwc->lock, flags); |
Dan Williams | e0bd0f8 | 2009-09-08 17:53:02 -0700 | [diff] [blame] | 130 | list_for_each_entry(child, &desc->tx_list, desc_node) |
Dan Williams | 41d5e59 | 2009-01-06 11:38:21 -0700 | [diff] [blame] | 131 | dev_vdbg(chan2dev(&dwc->chan), |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 132 | "moving child desc %p to freelist\n", |
| 133 | child); |
Dan Williams | e0bd0f8 | 2009-09-08 17:53:02 -0700 | [diff] [blame] | 134 | list_splice_init(&desc->tx_list, &dwc->free_list); |
Dan Williams | 41d5e59 | 2009-01-06 11:38:21 -0700 | [diff] [blame] | 135 | dev_vdbg(chan2dev(&dwc->chan), "moving desc %p to freelist\n", desc); |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 136 | list_add(&desc->desc_node, &dwc->free_list); |
Viresh Kumar | 69cea5a | 2011-04-15 16:03:35 +0530 | [diff] [blame] | 137 | spin_unlock_irqrestore(&dwc->lock, flags); |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 138 | } |
| 139 | } |
| 140 | |
Viresh Kumar | 61e183f | 2011-11-17 16:01:29 +0530 | [diff] [blame] | 141 | static void dwc_initialize(struct dw_dma_chan *dwc) |
| 142 | { |
| 143 | struct dw_dma *dw = to_dw_dma(dwc->chan.device); |
| 144 | struct dw_dma_slave *dws = dwc->chan.private; |
| 145 | u32 cfghi = DWC_CFGH_FIFO_MODE; |
| 146 | u32 cfglo = DWC_CFGL_CH_PRIOR(dwc->priority); |
| 147 | |
| 148 | if (dwc->initialized == true) |
| 149 | return; |
| 150 | |
Arnd Bergmann | f776076 | 2013-03-26 16:53:57 +0200 | [diff] [blame] | 151 | if (dws) { |
Viresh Kumar | 61e183f | 2011-11-17 16:01:29 +0530 | [diff] [blame] | 152 | /* |
| 153 | * We need controller-specific data to set up slave |
| 154 | * transfers. |
| 155 | */ |
| 156 | BUG_ON(!dws->dma_dev || dws->dma_dev != dw->dma.dev); |
| 157 | |
| 158 | cfghi = dws->cfg_hi; |
| 159 | cfglo |= dws->cfg_lo & ~DWC_CFGL_CH_PRIOR_MASK; |
Andy Shevchenko | 8fccc5b | 2012-09-03 13:46:19 +0300 | [diff] [blame] | 160 | } else { |
Andy Shevchenko | 0fdb567 | 2013-01-10 10:53:03 +0200 | [diff] [blame] | 161 | if (dwc->direction == DMA_MEM_TO_DEV) |
Arnd Bergmann | f776076 | 2013-03-26 16:53:57 +0200 | [diff] [blame] | 162 | cfghi = DWC_CFGH_DST_PER(dwc->request_line); |
Andy Shevchenko | 0fdb567 | 2013-01-10 10:53:03 +0200 | [diff] [blame] | 163 | else if (dwc->direction == DMA_DEV_TO_MEM) |
Arnd Bergmann | f776076 | 2013-03-26 16:53:57 +0200 | [diff] [blame] | 164 | cfghi = DWC_CFGH_SRC_PER(dwc->request_line); |
Viresh Kumar | 61e183f | 2011-11-17 16:01:29 +0530 | [diff] [blame] | 165 | } |
| 166 | |
| 167 | channel_writel(dwc, CFG_LO, cfglo); |
| 168 | channel_writel(dwc, CFG_HI, cfghi); |
| 169 | |
| 170 | /* Enable interrupts */ |
| 171 | channel_set_bit(dw, MASK.XFER, dwc->mask); |
Viresh Kumar | 61e183f | 2011-11-17 16:01:29 +0530 | [diff] [blame] | 172 | channel_set_bit(dw, MASK.ERROR, dwc->mask); |
| 173 | |
| 174 | dwc->initialized = true; |
| 175 | } |
| 176 | |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 177 | /*----------------------------------------------------------------------*/ |
| 178 | |
Andy Shevchenko | 4c2d56c | 2012-06-19 13:34:08 +0300 | [diff] [blame] | 179 | static inline unsigned int dwc_fast_fls(unsigned long long v) |
| 180 | { |
| 181 | /* |
| 182 | * We can be a lot more clever here, but this should take care |
| 183 | * of the most common optimization. |
| 184 | */ |
| 185 | if (!(v & 7)) |
| 186 | return 3; |
| 187 | else if (!(v & 3)) |
| 188 | return 2; |
| 189 | else if (!(v & 1)) |
| 190 | return 1; |
| 191 | return 0; |
| 192 | } |
| 193 | |
Andy Shevchenko | f52b36d | 2012-09-21 15:05:44 +0300 | [diff] [blame] | 194 | static inline void dwc_dump_chan_regs(struct dw_dma_chan *dwc) |
Andy Shevchenko | 1d45543 | 2012-06-19 13:34:03 +0300 | [diff] [blame] | 195 | { |
| 196 | dev_err(chan2dev(&dwc->chan), |
| 197 | " SAR: 0x%x DAR: 0x%x LLP: 0x%x CTL: 0x%x:%08x\n", |
| 198 | channel_readl(dwc, SAR), |
| 199 | channel_readl(dwc, DAR), |
| 200 | channel_readl(dwc, LLP), |
| 201 | channel_readl(dwc, CTL_HI), |
| 202 | channel_readl(dwc, CTL_LO)); |
| 203 | } |
| 204 | |
Andy Shevchenko | 3f936207 | 2012-06-19 13:46:32 +0300 | [diff] [blame] | 205 | static inline void dwc_chan_disable(struct dw_dma *dw, struct dw_dma_chan *dwc) |
| 206 | { |
| 207 | channel_clear_bit(dw, CH_EN, dwc->mask); |
| 208 | while (dma_readl(dw, CH_EN) & dwc->mask) |
| 209 | cpu_relax(); |
| 210 | } |
| 211 | |
Andy Shevchenko | 1d45543 | 2012-06-19 13:34:03 +0300 | [diff] [blame] | 212 | /*----------------------------------------------------------------------*/ |
| 213 | |
Andy Shevchenko | fed2574 | 2012-09-21 15:05:49 +0300 | [diff] [blame] | 214 | /* Perform single block transfer */ |
| 215 | static inline void dwc_do_single_block(struct dw_dma_chan *dwc, |
| 216 | struct dw_desc *desc) |
| 217 | { |
| 218 | struct dw_dma *dw = to_dw_dma(dwc->chan.device); |
| 219 | u32 ctllo; |
| 220 | |
Andy Shevchenko | 1d566f1 | 2014-01-13 14:04:48 +0200 | [diff] [blame] | 221 | /* |
| 222 | * Software emulation of LLP mode relies on interrupts to continue |
| 223 | * multi block transfer. |
| 224 | */ |
Andy Shevchenko | fed2574 | 2012-09-21 15:05:49 +0300 | [diff] [blame] | 225 | ctllo = desc->lli.ctllo | DWC_CTLL_INT_EN; |
| 226 | |
| 227 | channel_writel(dwc, SAR, desc->lli.sar); |
| 228 | channel_writel(dwc, DAR, desc->lli.dar); |
| 229 | channel_writel(dwc, CTL_LO, ctllo); |
| 230 | channel_writel(dwc, CTL_HI, desc->lli.ctlhi); |
| 231 | channel_set_bit(dw, CH_EN, dwc->mask); |
Andy Shevchenko | f5c6a7d | 2013-01-09 10:17:13 +0200 | [diff] [blame] | 232 | |
| 233 | /* Move pointer to next descriptor */ |
| 234 | dwc->tx_node_active = dwc->tx_node_active->next; |
Andy Shevchenko | fed2574 | 2012-09-21 15:05:49 +0300 | [diff] [blame] | 235 | } |
| 236 | |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 237 | /* Called with dwc->lock held and bh disabled */ |
| 238 | static void dwc_dostart(struct dw_dma_chan *dwc, struct dw_desc *first) |
| 239 | { |
| 240 | struct dw_dma *dw = to_dw_dma(dwc->chan.device); |
Andy Shevchenko | fed2574 | 2012-09-21 15:05:49 +0300 | [diff] [blame] | 241 | unsigned long was_soft_llp; |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 242 | |
| 243 | /* ASSERT: channel is idle */ |
| 244 | if (dma_readl(dw, CH_EN) & dwc->mask) { |
Dan Williams | 41d5e59 | 2009-01-06 11:38:21 -0700 | [diff] [blame] | 245 | dev_err(chan2dev(&dwc->chan), |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 246 | "BUG: Attempted to start non-idle channel\n"); |
Andy Shevchenko | 1d45543 | 2012-06-19 13:34:03 +0300 | [diff] [blame] | 247 | dwc_dump_chan_regs(dwc); |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 248 | |
| 249 | /* The tasklet will hopefully advance the queue... */ |
| 250 | return; |
| 251 | } |
| 252 | |
Andy Shevchenko | fed2574 | 2012-09-21 15:05:49 +0300 | [diff] [blame] | 253 | if (dwc->nollp) { |
| 254 | was_soft_llp = test_and_set_bit(DW_DMA_IS_SOFT_LLP, |
| 255 | &dwc->flags); |
| 256 | if (was_soft_llp) { |
| 257 | dev_err(chan2dev(&dwc->chan), |
Andy Shevchenko | fc61f6b | 2014-01-13 14:04:49 +0200 | [diff] [blame] | 258 | "BUG: Attempted to start new LLP transfer inside ongoing one\n"); |
Andy Shevchenko | fed2574 | 2012-09-21 15:05:49 +0300 | [diff] [blame] | 259 | return; |
| 260 | } |
| 261 | |
| 262 | dwc_initialize(dwc); |
| 263 | |
Andy Shevchenko | 4702d52 | 2013-01-25 11:48:03 +0200 | [diff] [blame] | 264 | dwc->residue = first->total_len; |
Andy Shevchenko | f5c6a7d | 2013-01-09 10:17:13 +0200 | [diff] [blame] | 265 | dwc->tx_node_active = &first->tx_list; |
Andy Shevchenko | fed2574 | 2012-09-21 15:05:49 +0300 | [diff] [blame] | 266 | |
Andy Shevchenko | fdf475f | 2013-01-25 11:48:00 +0200 | [diff] [blame] | 267 | /* Submit first block */ |
Andy Shevchenko | fed2574 | 2012-09-21 15:05:49 +0300 | [diff] [blame] | 268 | dwc_do_single_block(dwc, first); |
| 269 | |
| 270 | return; |
| 271 | } |
| 272 | |
Viresh Kumar | 61e183f | 2011-11-17 16:01:29 +0530 | [diff] [blame] | 273 | dwc_initialize(dwc); |
| 274 | |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 275 | channel_writel(dwc, LLP, first->txd.phys); |
| 276 | channel_writel(dwc, CTL_LO, |
| 277 | DWC_CTLL_LLP_D_EN | DWC_CTLL_LLP_S_EN); |
| 278 | channel_writel(dwc, CTL_HI, 0); |
| 279 | channel_set_bit(dw, CH_EN, dwc->mask); |
| 280 | } |
| 281 | |
Andy Shevchenko | e7637c6 | 2014-06-18 12:15:36 +0300 | [diff] [blame] | 282 | static void dwc_dostart_first_queued(struct dw_dma_chan *dwc) |
| 283 | { |
Andy Shevchenko | cba1561 | 2014-06-18 12:15:37 +0300 | [diff] [blame] | 284 | struct dw_desc *desc; |
| 285 | |
Andy Shevchenko | e7637c6 | 2014-06-18 12:15:36 +0300 | [diff] [blame] | 286 | if (list_empty(&dwc->queue)) |
| 287 | return; |
| 288 | |
| 289 | list_move(dwc->queue.next, &dwc->active_list); |
Andy Shevchenko | cba1561 | 2014-06-18 12:15:37 +0300 | [diff] [blame] | 290 | desc = dwc_first_active(dwc); |
| 291 | dev_vdbg(chan2dev(&dwc->chan), "%s: started %u\n", __func__, desc->txd.cookie); |
| 292 | dwc_dostart(dwc, desc); |
Andy Shevchenko | e7637c6 | 2014-06-18 12:15:36 +0300 | [diff] [blame] | 293 | } |
| 294 | |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 295 | /*----------------------------------------------------------------------*/ |
| 296 | |
| 297 | static void |
Viresh Kumar | 5fedefb | 2011-04-15 16:03:35 +0530 | [diff] [blame] | 298 | dwc_descriptor_complete(struct dw_dma_chan *dwc, struct dw_desc *desc, |
| 299 | bool callback_required) |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 300 | { |
Viresh Kumar | 5fedefb | 2011-04-15 16:03:35 +0530 | [diff] [blame] | 301 | dma_async_tx_callback callback = NULL; |
| 302 | void *param = NULL; |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 303 | struct dma_async_tx_descriptor *txd = &desc->txd; |
Viresh Kumar | e518076 | 2011-03-03 15:47:20 +0530 | [diff] [blame] | 304 | struct dw_desc *child; |
Viresh Kumar | 69cea5a | 2011-04-15 16:03:35 +0530 | [diff] [blame] | 305 | unsigned long flags; |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 306 | |
Dan Williams | 41d5e59 | 2009-01-06 11:38:21 -0700 | [diff] [blame] | 307 | dev_vdbg(chan2dev(&dwc->chan), "descriptor %u complete\n", txd->cookie); |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 308 | |
Viresh Kumar | 69cea5a | 2011-04-15 16:03:35 +0530 | [diff] [blame] | 309 | spin_lock_irqsave(&dwc->lock, flags); |
Russell King - ARM Linux | f7fbce0 | 2012-03-06 22:35:07 +0000 | [diff] [blame] | 310 | dma_cookie_complete(txd); |
Viresh Kumar | 5fedefb | 2011-04-15 16:03:35 +0530 | [diff] [blame] | 311 | if (callback_required) { |
| 312 | callback = txd->callback; |
| 313 | param = txd->callback_param; |
| 314 | } |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 315 | |
Viresh Kumar | e518076 | 2011-03-03 15:47:20 +0530 | [diff] [blame] | 316 | /* async_tx_ack */ |
| 317 | list_for_each_entry(child, &desc->tx_list, desc_node) |
| 318 | async_tx_ack(&child->txd); |
| 319 | async_tx_ack(&desc->txd); |
| 320 | |
Dan Williams | e0bd0f8 | 2009-09-08 17:53:02 -0700 | [diff] [blame] | 321 | list_splice_init(&desc->tx_list, &dwc->free_list); |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 322 | list_move(&desc->desc_node, &dwc->free_list); |
| 323 | |
Dan Williams | d38a8c6 | 2013-10-18 19:35:23 +0200 | [diff] [blame] | 324 | dma_descriptor_unmap(txd); |
Viresh Kumar | 69cea5a | 2011-04-15 16:03:35 +0530 | [diff] [blame] | 325 | spin_unlock_irqrestore(&dwc->lock, flags); |
| 326 | |
Andy Shevchenko | 21e93c1 | 2013-01-09 10:17:12 +0200 | [diff] [blame] | 327 | if (callback) |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 328 | callback(param); |
| 329 | } |
| 330 | |
| 331 | static void dwc_complete_all(struct dw_dma *dw, struct dw_dma_chan *dwc) |
| 332 | { |
| 333 | struct dw_desc *desc, *_desc; |
| 334 | LIST_HEAD(list); |
Viresh Kumar | 69cea5a | 2011-04-15 16:03:35 +0530 | [diff] [blame] | 335 | unsigned long flags; |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 336 | |
Viresh Kumar | 69cea5a | 2011-04-15 16:03:35 +0530 | [diff] [blame] | 337 | spin_lock_irqsave(&dwc->lock, flags); |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 338 | if (dma_readl(dw, CH_EN) & dwc->mask) { |
Dan Williams | 41d5e59 | 2009-01-06 11:38:21 -0700 | [diff] [blame] | 339 | dev_err(chan2dev(&dwc->chan), |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 340 | "BUG: XFER bit set, but channel not idle!\n"); |
| 341 | |
| 342 | /* Try to continue after resetting the channel... */ |
Andy Shevchenko | 3f936207 | 2012-06-19 13:46:32 +0300 | [diff] [blame] | 343 | dwc_chan_disable(dw, dwc); |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 344 | } |
| 345 | |
| 346 | /* |
| 347 | * Submit queued descriptors ASAP, i.e. before we go through |
| 348 | * the completed ones. |
| 349 | */ |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 350 | list_splice_init(&dwc->active_list, &list); |
Andy Shevchenko | e7637c6 | 2014-06-18 12:15:36 +0300 | [diff] [blame] | 351 | dwc_dostart_first_queued(dwc); |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 352 | |
Viresh Kumar | 69cea5a | 2011-04-15 16:03:35 +0530 | [diff] [blame] | 353 | spin_unlock_irqrestore(&dwc->lock, flags); |
| 354 | |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 355 | list_for_each_entry_safe(desc, _desc, &list, desc_node) |
Viresh Kumar | 5fedefb | 2011-04-15 16:03:35 +0530 | [diff] [blame] | 356 | dwc_descriptor_complete(dwc, desc, true); |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 357 | } |
| 358 | |
Andy Shevchenko | 4702d52 | 2013-01-25 11:48:03 +0200 | [diff] [blame] | 359 | /* Returns how many bytes were already received from source */ |
| 360 | static inline u32 dwc_get_sent(struct dw_dma_chan *dwc) |
| 361 | { |
| 362 | u32 ctlhi = channel_readl(dwc, CTL_HI); |
| 363 | u32 ctllo = channel_readl(dwc, CTL_LO); |
| 364 | |
| 365 | return (ctlhi & DWC_CTLH_BLOCK_TS_MASK) * (1 << (ctllo >> 4 & 7)); |
| 366 | } |
| 367 | |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 368 | static void dwc_scan_descriptors(struct dw_dma *dw, struct dw_dma_chan *dwc) |
| 369 | { |
| 370 | dma_addr_t llp; |
| 371 | struct dw_desc *desc, *_desc; |
| 372 | struct dw_desc *child; |
| 373 | u32 status_xfer; |
Viresh Kumar | 69cea5a | 2011-04-15 16:03:35 +0530 | [diff] [blame] | 374 | unsigned long flags; |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 375 | |
Viresh Kumar | 69cea5a | 2011-04-15 16:03:35 +0530 | [diff] [blame] | 376 | spin_lock_irqsave(&dwc->lock, flags); |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 377 | llp = channel_readl(dwc, LLP); |
| 378 | status_xfer = dma_readl(dw, RAW.XFER); |
| 379 | |
| 380 | if (status_xfer & dwc->mask) { |
| 381 | /* Everything we've submitted is done */ |
| 382 | dma_writel(dw, CLEAR.XFER, dwc->mask); |
Andy Shevchenko | 77bcc497 | 2013-01-18 14:14:15 +0200 | [diff] [blame] | 383 | |
| 384 | if (test_bit(DW_DMA_IS_SOFT_LLP, &dwc->flags)) { |
Andy Shevchenko | fdf475f | 2013-01-25 11:48:00 +0200 | [diff] [blame] | 385 | struct list_head *head, *active = dwc->tx_node_active; |
| 386 | |
| 387 | /* |
| 388 | * We are inside first active descriptor. |
| 389 | * Otherwise something is really wrong. |
| 390 | */ |
| 391 | desc = dwc_first_active(dwc); |
| 392 | |
| 393 | head = &desc->tx_list; |
| 394 | if (active != head) { |
Andy Shevchenko | 4702d52 | 2013-01-25 11:48:03 +0200 | [diff] [blame] | 395 | /* Update desc to reflect last sent one */ |
| 396 | if (active != head->next) |
| 397 | desc = to_dw_desc(active->prev); |
| 398 | |
| 399 | dwc->residue -= desc->len; |
| 400 | |
Andy Shevchenko | fdf475f | 2013-01-25 11:48:00 +0200 | [diff] [blame] | 401 | child = to_dw_desc(active); |
Andy Shevchenko | 77bcc497 | 2013-01-18 14:14:15 +0200 | [diff] [blame] | 402 | |
| 403 | /* Submit next block */ |
Andy Shevchenko | fdf475f | 2013-01-25 11:48:00 +0200 | [diff] [blame] | 404 | dwc_do_single_block(dwc, child); |
Andy Shevchenko | 77bcc497 | 2013-01-18 14:14:15 +0200 | [diff] [blame] | 405 | |
Andy Shevchenko | fdf475f | 2013-01-25 11:48:00 +0200 | [diff] [blame] | 406 | spin_unlock_irqrestore(&dwc->lock, flags); |
Andy Shevchenko | 77bcc497 | 2013-01-18 14:14:15 +0200 | [diff] [blame] | 407 | return; |
| 408 | } |
Andy Shevchenko | fdf475f | 2013-01-25 11:48:00 +0200 | [diff] [blame] | 409 | |
Andy Shevchenko | 77bcc497 | 2013-01-18 14:14:15 +0200 | [diff] [blame] | 410 | /* We are done here */ |
| 411 | clear_bit(DW_DMA_IS_SOFT_LLP, &dwc->flags); |
| 412 | } |
Andy Shevchenko | 4702d52 | 2013-01-25 11:48:03 +0200 | [diff] [blame] | 413 | |
| 414 | dwc->residue = 0; |
| 415 | |
Viresh Kumar | 69cea5a | 2011-04-15 16:03:35 +0530 | [diff] [blame] | 416 | spin_unlock_irqrestore(&dwc->lock, flags); |
| 417 | |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 418 | dwc_complete_all(dw, dwc); |
| 419 | return; |
| 420 | } |
| 421 | |
Viresh Kumar | 69cea5a | 2011-04-15 16:03:35 +0530 | [diff] [blame] | 422 | if (list_empty(&dwc->active_list)) { |
Andy Shevchenko | 4702d52 | 2013-01-25 11:48:03 +0200 | [diff] [blame] | 423 | dwc->residue = 0; |
Viresh Kumar | 69cea5a | 2011-04-15 16:03:35 +0530 | [diff] [blame] | 424 | spin_unlock_irqrestore(&dwc->lock, flags); |
Jamie Iles | 087809f | 2011-01-21 14:11:52 +0000 | [diff] [blame] | 425 | return; |
Viresh Kumar | 69cea5a | 2011-04-15 16:03:35 +0530 | [diff] [blame] | 426 | } |
Jamie Iles | 087809f | 2011-01-21 14:11:52 +0000 | [diff] [blame] | 427 | |
Andy Shevchenko | 77bcc497 | 2013-01-18 14:14:15 +0200 | [diff] [blame] | 428 | if (test_bit(DW_DMA_IS_SOFT_LLP, &dwc->flags)) { |
| 429 | dev_vdbg(chan2dev(&dwc->chan), "%s: soft LLP mode\n", __func__); |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 430 | spin_unlock_irqrestore(&dwc->lock, flags); |
Dan Williams | 41d5e59 | 2009-01-06 11:38:21 -0700 | [diff] [blame] | 431 | return; |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 432 | } |
| 433 | |
Andy Shevchenko | 5a87f0e | 2014-01-13 14:04:50 +0200 | [diff] [blame] | 434 | dev_vdbg(chan2dev(&dwc->chan), "%s: llp=%pad\n", __func__, &llp); |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 435 | |
| 436 | list_for_each_entry_safe(desc, _desc, &dwc->active_list, desc_node) { |
Andy Shevchenko | 75c6122 | 2013-03-26 16:53:54 +0200 | [diff] [blame] | 437 | /* Initial residue value */ |
Andy Shevchenko | 4702d52 | 2013-01-25 11:48:03 +0200 | [diff] [blame] | 438 | dwc->residue = desc->total_len; |
| 439 | |
Andy Shevchenko | 75c6122 | 2013-03-26 16:53:54 +0200 | [diff] [blame] | 440 | /* Check first descriptors addr */ |
Viresh Kumar | 69cea5a | 2011-04-15 16:03:35 +0530 | [diff] [blame] | 441 | if (desc->txd.phys == llp) { |
| 442 | spin_unlock_irqrestore(&dwc->lock, flags); |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 443 | return; |
Viresh Kumar | 69cea5a | 2011-04-15 16:03:35 +0530 | [diff] [blame] | 444 | } |
Viresh Kumar | 84adccf | 2011-03-24 11:32:15 +0530 | [diff] [blame] | 445 | |
Andy Shevchenko | 75c6122 | 2013-03-26 16:53:54 +0200 | [diff] [blame] | 446 | /* Check first descriptors llp */ |
Viresh Kumar | 69cea5a | 2011-04-15 16:03:35 +0530 | [diff] [blame] | 447 | if (desc->lli.llp == llp) { |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 448 | /* This one is currently in progress */ |
Andy Shevchenko | 4702d52 | 2013-01-25 11:48:03 +0200 | [diff] [blame] | 449 | dwc->residue -= dwc_get_sent(dwc); |
Viresh Kumar | 69cea5a | 2011-04-15 16:03:35 +0530 | [diff] [blame] | 450 | spin_unlock_irqrestore(&dwc->lock, flags); |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 451 | return; |
Viresh Kumar | 69cea5a | 2011-04-15 16:03:35 +0530 | [diff] [blame] | 452 | } |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 453 | |
Andy Shevchenko | 4702d52 | 2013-01-25 11:48:03 +0200 | [diff] [blame] | 454 | dwc->residue -= desc->len; |
| 455 | list_for_each_entry(child, &desc->tx_list, desc_node) { |
Viresh Kumar | 69cea5a | 2011-04-15 16:03:35 +0530 | [diff] [blame] | 456 | if (child->lli.llp == llp) { |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 457 | /* Currently in progress */ |
Andy Shevchenko | 4702d52 | 2013-01-25 11:48:03 +0200 | [diff] [blame] | 458 | dwc->residue -= dwc_get_sent(dwc); |
Viresh Kumar | 69cea5a | 2011-04-15 16:03:35 +0530 | [diff] [blame] | 459 | spin_unlock_irqrestore(&dwc->lock, flags); |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 460 | return; |
Viresh Kumar | 69cea5a | 2011-04-15 16:03:35 +0530 | [diff] [blame] | 461 | } |
Andy Shevchenko | 4702d52 | 2013-01-25 11:48:03 +0200 | [diff] [blame] | 462 | dwc->residue -= child->len; |
| 463 | } |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 464 | |
| 465 | /* |
| 466 | * No descriptors so far seem to be in progress, i.e. |
| 467 | * this one must be done. |
| 468 | */ |
Viresh Kumar | 69cea5a | 2011-04-15 16:03:35 +0530 | [diff] [blame] | 469 | spin_unlock_irqrestore(&dwc->lock, flags); |
Viresh Kumar | 5fedefb | 2011-04-15 16:03:35 +0530 | [diff] [blame] | 470 | dwc_descriptor_complete(dwc, desc, true); |
Viresh Kumar | 69cea5a | 2011-04-15 16:03:35 +0530 | [diff] [blame] | 471 | spin_lock_irqsave(&dwc->lock, flags); |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 472 | } |
| 473 | |
Dan Williams | 41d5e59 | 2009-01-06 11:38:21 -0700 | [diff] [blame] | 474 | dev_err(chan2dev(&dwc->chan), |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 475 | "BUG: All descriptors done, but channel not idle!\n"); |
| 476 | |
| 477 | /* Try to continue after resetting the channel... */ |
Andy Shevchenko | 3f936207 | 2012-06-19 13:46:32 +0300 | [diff] [blame] | 478 | dwc_chan_disable(dw, dwc); |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 479 | |
Andy Shevchenko | e7637c6 | 2014-06-18 12:15:36 +0300 | [diff] [blame] | 480 | dwc_dostart_first_queued(dwc); |
Viresh Kumar | 69cea5a | 2011-04-15 16:03:35 +0530 | [diff] [blame] | 481 | spin_unlock_irqrestore(&dwc->lock, flags); |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 482 | } |
| 483 | |
Andy Shevchenko | 93aad1b | 2012-07-13 11:09:32 +0300 | [diff] [blame] | 484 | static inline void dwc_dump_lli(struct dw_dma_chan *dwc, struct dw_lli *lli) |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 485 | { |
Andy Shevchenko | 21d43f4 | 2012-10-18 17:34:09 +0300 | [diff] [blame] | 486 | dev_crit(chan2dev(&dwc->chan), " desc: s0x%x d0x%x l0x%x c0x%x:%x\n", |
| 487 | lli->sar, lli->dar, lli->llp, lli->ctlhi, lli->ctllo); |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 488 | } |
| 489 | |
| 490 | static void dwc_handle_error(struct dw_dma *dw, struct dw_dma_chan *dwc) |
| 491 | { |
| 492 | struct dw_desc *bad_desc; |
| 493 | struct dw_desc *child; |
Viresh Kumar | 69cea5a | 2011-04-15 16:03:35 +0530 | [diff] [blame] | 494 | unsigned long flags; |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 495 | |
| 496 | dwc_scan_descriptors(dw, dwc); |
| 497 | |
Viresh Kumar | 69cea5a | 2011-04-15 16:03:35 +0530 | [diff] [blame] | 498 | spin_lock_irqsave(&dwc->lock, flags); |
| 499 | |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 500 | /* |
| 501 | * The descriptor currently at the head of the active list is |
| 502 | * borked. Since we don't have any way to report errors, we'll |
| 503 | * just have to scream loudly and try to carry on. |
| 504 | */ |
| 505 | bad_desc = dwc_first_active(dwc); |
| 506 | list_del_init(&bad_desc->desc_node); |
Viresh Kumar | f336e42 | 2011-03-03 15:47:16 +0530 | [diff] [blame] | 507 | list_move(dwc->queue.next, dwc->active_list.prev); |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 508 | |
| 509 | /* Clear the error flag and try to restart the controller */ |
| 510 | dma_writel(dw, CLEAR.ERROR, dwc->mask); |
| 511 | if (!list_empty(&dwc->active_list)) |
| 512 | dwc_dostart(dwc, dwc_first_active(dwc)); |
| 513 | |
| 514 | /* |
Andy Shevchenko | ba84bd7 | 2012-10-18 17:34:11 +0300 | [diff] [blame] | 515 | * WARN may seem harsh, but since this only happens |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 516 | * when someone submits a bad physical address in a |
| 517 | * descriptor, we should consider ourselves lucky that the |
| 518 | * controller flagged an error instead of scribbling over |
| 519 | * random memory locations. |
| 520 | */ |
Andy Shevchenko | ba84bd7 | 2012-10-18 17:34:11 +0300 | [diff] [blame] | 521 | dev_WARN(chan2dev(&dwc->chan), "Bad descriptor submitted for DMA!\n" |
| 522 | " cookie: %d\n", bad_desc->txd.cookie); |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 523 | dwc_dump_lli(dwc, &bad_desc->lli); |
Dan Williams | e0bd0f8 | 2009-09-08 17:53:02 -0700 | [diff] [blame] | 524 | list_for_each_entry(child, &bad_desc->tx_list, desc_node) |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 525 | dwc_dump_lli(dwc, &child->lli); |
| 526 | |
Viresh Kumar | 69cea5a | 2011-04-15 16:03:35 +0530 | [diff] [blame] | 527 | spin_unlock_irqrestore(&dwc->lock, flags); |
| 528 | |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 529 | /* Pretend the descriptor completed successfully */ |
Viresh Kumar | 5fedefb | 2011-04-15 16:03:35 +0530 | [diff] [blame] | 530 | dwc_descriptor_complete(dwc, bad_desc, true); |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 531 | } |
| 532 | |
Hans-Christian Egtvedt | d9de451 | 2009-04-01 15:47:02 +0200 | [diff] [blame] | 533 | /* --------------------- Cyclic DMA API extensions -------------------- */ |
| 534 | |
Denis Efremov | 8004cbb | 2013-05-09 13:19:40 +0400 | [diff] [blame] | 535 | dma_addr_t dw_dma_get_src_addr(struct dma_chan *chan) |
Hans-Christian Egtvedt | d9de451 | 2009-04-01 15:47:02 +0200 | [diff] [blame] | 536 | { |
| 537 | struct dw_dma_chan *dwc = to_dw_dma_chan(chan); |
| 538 | return channel_readl(dwc, SAR); |
| 539 | } |
| 540 | EXPORT_SYMBOL(dw_dma_get_src_addr); |
| 541 | |
Denis Efremov | 8004cbb | 2013-05-09 13:19:40 +0400 | [diff] [blame] | 542 | dma_addr_t dw_dma_get_dst_addr(struct dma_chan *chan) |
Hans-Christian Egtvedt | d9de451 | 2009-04-01 15:47:02 +0200 | [diff] [blame] | 543 | { |
| 544 | struct dw_dma_chan *dwc = to_dw_dma_chan(chan); |
| 545 | return channel_readl(dwc, DAR); |
| 546 | } |
| 547 | EXPORT_SYMBOL(dw_dma_get_dst_addr); |
| 548 | |
Andy Shevchenko | 75c6122 | 2013-03-26 16:53:54 +0200 | [diff] [blame] | 549 | /* Called with dwc->lock held and all DMAC interrupts disabled */ |
Hans-Christian Egtvedt | d9de451 | 2009-04-01 15:47:02 +0200 | [diff] [blame] | 550 | static void dwc_handle_cyclic(struct dw_dma *dw, struct dw_dma_chan *dwc, |
Viresh Kumar | ff7b05f | 2012-02-01 16:12:23 +0530 | [diff] [blame] | 551 | u32 status_err, u32 status_xfer) |
Hans-Christian Egtvedt | d9de451 | 2009-04-01 15:47:02 +0200 | [diff] [blame] | 552 | { |
Viresh Kumar | 69cea5a | 2011-04-15 16:03:35 +0530 | [diff] [blame] | 553 | unsigned long flags; |
| 554 | |
Viresh Kumar | ff7b05f | 2012-02-01 16:12:23 +0530 | [diff] [blame] | 555 | if (dwc->mask) { |
Hans-Christian Egtvedt | d9de451 | 2009-04-01 15:47:02 +0200 | [diff] [blame] | 556 | void (*callback)(void *param); |
| 557 | void *callback_param; |
| 558 | |
| 559 | dev_vdbg(chan2dev(&dwc->chan), "new cyclic period llp 0x%08x\n", |
| 560 | channel_readl(dwc, LLP)); |
Hans-Christian Egtvedt | d9de451 | 2009-04-01 15:47:02 +0200 | [diff] [blame] | 561 | |
| 562 | callback = dwc->cdesc->period_callback; |
| 563 | callback_param = dwc->cdesc->period_callback_param; |
Viresh Kumar | 69cea5a | 2011-04-15 16:03:35 +0530 | [diff] [blame] | 564 | |
| 565 | if (callback) |
Hans-Christian Egtvedt | d9de451 | 2009-04-01 15:47:02 +0200 | [diff] [blame] | 566 | callback(callback_param); |
Hans-Christian Egtvedt | d9de451 | 2009-04-01 15:47:02 +0200 | [diff] [blame] | 567 | } |
| 568 | |
| 569 | /* |
| 570 | * Error and transfer complete are highly unlikely, and will most |
| 571 | * likely be due to a configuration error by the user. |
| 572 | */ |
| 573 | if (unlikely(status_err & dwc->mask) || |
| 574 | unlikely(status_xfer & dwc->mask)) { |
| 575 | int i; |
| 576 | |
Andy Shevchenko | fc61f6b | 2014-01-13 14:04:49 +0200 | [diff] [blame] | 577 | dev_err(chan2dev(&dwc->chan), |
| 578 | "cyclic DMA unexpected %s interrupt, stopping DMA transfer\n", |
| 579 | status_xfer ? "xfer" : "error"); |
Viresh Kumar | 69cea5a | 2011-04-15 16:03:35 +0530 | [diff] [blame] | 580 | |
| 581 | spin_lock_irqsave(&dwc->lock, flags); |
| 582 | |
Andy Shevchenko | 1d45543 | 2012-06-19 13:34:03 +0300 | [diff] [blame] | 583 | dwc_dump_chan_regs(dwc); |
Hans-Christian Egtvedt | d9de451 | 2009-04-01 15:47:02 +0200 | [diff] [blame] | 584 | |
Andy Shevchenko | 3f936207 | 2012-06-19 13:46:32 +0300 | [diff] [blame] | 585 | dwc_chan_disable(dw, dwc); |
Hans-Christian Egtvedt | d9de451 | 2009-04-01 15:47:02 +0200 | [diff] [blame] | 586 | |
Andy Shevchenko | 75c6122 | 2013-03-26 16:53:54 +0200 | [diff] [blame] | 587 | /* Make sure DMA does not restart by loading a new list */ |
Hans-Christian Egtvedt | d9de451 | 2009-04-01 15:47:02 +0200 | [diff] [blame] | 588 | channel_writel(dwc, LLP, 0); |
| 589 | channel_writel(dwc, CTL_LO, 0); |
| 590 | channel_writel(dwc, CTL_HI, 0); |
| 591 | |
Hans-Christian Egtvedt | d9de451 | 2009-04-01 15:47:02 +0200 | [diff] [blame] | 592 | dma_writel(dw, CLEAR.ERROR, dwc->mask); |
| 593 | dma_writel(dw, CLEAR.XFER, dwc->mask); |
| 594 | |
| 595 | for (i = 0; i < dwc->cdesc->periods; i++) |
| 596 | dwc_dump_lli(dwc, &dwc->cdesc->desc[i]->lli); |
Viresh Kumar | 69cea5a | 2011-04-15 16:03:35 +0530 | [diff] [blame] | 597 | |
| 598 | spin_unlock_irqrestore(&dwc->lock, flags); |
Hans-Christian Egtvedt | d9de451 | 2009-04-01 15:47:02 +0200 | [diff] [blame] | 599 | } |
| 600 | } |
| 601 | |
| 602 | /* ------------------------------------------------------------------------- */ |
| 603 | |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 604 | static void dw_dma_tasklet(unsigned long data) |
| 605 | { |
| 606 | struct dw_dma *dw = (struct dw_dma *)data; |
| 607 | struct dw_dma_chan *dwc; |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 608 | u32 status_xfer; |
| 609 | u32 status_err; |
| 610 | int i; |
| 611 | |
Haavard Skinnemoen | 7fe7b2f | 2008-10-03 15:23:46 -0700 | [diff] [blame] | 612 | status_xfer = dma_readl(dw, RAW.XFER); |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 613 | status_err = dma_readl(dw, RAW.ERROR); |
| 614 | |
Andy Shevchenko | 2e4c364 | 2012-06-19 13:34:05 +0300 | [diff] [blame] | 615 | dev_vdbg(dw->dma.dev, "%s: status_err=%x\n", __func__, status_err); |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 616 | |
| 617 | for (i = 0; i < dw->dma.chancnt; i++) { |
| 618 | dwc = &dw->chan[i]; |
Hans-Christian Egtvedt | d9de451 | 2009-04-01 15:47:02 +0200 | [diff] [blame] | 619 | if (test_bit(DW_DMA_IS_CYCLIC, &dwc->flags)) |
Viresh Kumar | ff7b05f | 2012-02-01 16:12:23 +0530 | [diff] [blame] | 620 | dwc_handle_cyclic(dw, dwc, status_err, status_xfer); |
Hans-Christian Egtvedt | d9de451 | 2009-04-01 15:47:02 +0200 | [diff] [blame] | 621 | else if (status_err & (1 << i)) |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 622 | dwc_handle_error(dw, dwc); |
Andy Shevchenko | 77bcc497 | 2013-01-18 14:14:15 +0200 | [diff] [blame] | 623 | else if (status_xfer & (1 << i)) |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 624 | dwc_scan_descriptors(dw, dwc); |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 625 | } |
| 626 | |
| 627 | /* |
Viresh Kumar | ff7b05f | 2012-02-01 16:12:23 +0530 | [diff] [blame] | 628 | * Re-enable interrupts. |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 629 | */ |
| 630 | channel_set_bit(dw, MASK.XFER, dw->all_chan_mask); |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 631 | channel_set_bit(dw, MASK.ERROR, dw->all_chan_mask); |
| 632 | } |
| 633 | |
| 634 | static irqreturn_t dw_dma_interrupt(int irq, void *dev_id) |
| 635 | { |
| 636 | struct dw_dma *dw = dev_id; |
Andy Shevchenko | 3783cef | 2013-07-15 15:04:39 +0300 | [diff] [blame] | 637 | u32 status = dma_readl(dw, STATUS_INT); |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 638 | |
Andy Shevchenko | 3783cef | 2013-07-15 15:04:39 +0300 | [diff] [blame] | 639 | dev_vdbg(dw->dma.dev, "%s: status=0x%x\n", __func__, status); |
| 640 | |
| 641 | /* Check if we have any interrupt from the DMAC */ |
| 642 | if (!status) |
| 643 | return IRQ_NONE; |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 644 | |
| 645 | /* |
| 646 | * Just disable the interrupts. We'll turn them back on in the |
| 647 | * softirq handler. |
| 648 | */ |
| 649 | channel_clear_bit(dw, MASK.XFER, dw->all_chan_mask); |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 650 | channel_clear_bit(dw, MASK.ERROR, dw->all_chan_mask); |
| 651 | |
| 652 | status = dma_readl(dw, STATUS_INT); |
| 653 | if (status) { |
| 654 | dev_err(dw->dma.dev, |
| 655 | "BUG: Unexpected interrupts pending: 0x%x\n", |
| 656 | status); |
| 657 | |
| 658 | /* Try to recover */ |
| 659 | channel_clear_bit(dw, MASK.XFER, (1 << 8) - 1); |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 660 | channel_clear_bit(dw, MASK.SRC_TRAN, (1 << 8) - 1); |
| 661 | channel_clear_bit(dw, MASK.DST_TRAN, (1 << 8) - 1); |
| 662 | channel_clear_bit(dw, MASK.ERROR, (1 << 8) - 1); |
| 663 | } |
| 664 | |
| 665 | tasklet_schedule(&dw->tasklet); |
| 666 | |
| 667 | return IRQ_HANDLED; |
| 668 | } |
| 669 | |
| 670 | /*----------------------------------------------------------------------*/ |
| 671 | |
| 672 | static dma_cookie_t dwc_tx_submit(struct dma_async_tx_descriptor *tx) |
| 673 | { |
| 674 | struct dw_desc *desc = txd_to_dw_desc(tx); |
| 675 | struct dw_dma_chan *dwc = to_dw_dma_chan(tx->chan); |
| 676 | dma_cookie_t cookie; |
Viresh Kumar | 69cea5a | 2011-04-15 16:03:35 +0530 | [diff] [blame] | 677 | unsigned long flags; |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 678 | |
Viresh Kumar | 69cea5a | 2011-04-15 16:03:35 +0530 | [diff] [blame] | 679 | spin_lock_irqsave(&dwc->lock, flags); |
Russell King - ARM Linux | 884485e | 2012-03-06 22:34:46 +0000 | [diff] [blame] | 680 | cookie = dma_cookie_assign(tx); |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 681 | |
| 682 | /* |
| 683 | * REVISIT: We should attempt to chain as many descriptors as |
| 684 | * possible, perhaps even appending to those already submitted |
| 685 | * for DMA. But this is hard to do in a race-free manner. |
| 686 | */ |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 687 | |
Andy Shevchenko | dd8ecfca | 2014-06-18 12:15:38 +0300 | [diff] [blame] | 688 | dev_vdbg(chan2dev(tx->chan), "%s: queued %u\n", __func__, desc->txd.cookie); |
| 689 | list_add_tail(&desc->desc_node, &dwc->queue); |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 690 | |
Viresh Kumar | 69cea5a | 2011-04-15 16:03:35 +0530 | [diff] [blame] | 691 | spin_unlock_irqrestore(&dwc->lock, flags); |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 692 | |
| 693 | return cookie; |
| 694 | } |
| 695 | |
| 696 | static struct dma_async_tx_descriptor * |
| 697 | dwc_prep_dma_memcpy(struct dma_chan *chan, dma_addr_t dest, dma_addr_t src, |
| 698 | size_t len, unsigned long flags) |
| 699 | { |
| 700 | struct dw_dma_chan *dwc = to_dw_dma_chan(chan); |
Arnd Bergmann | f776076 | 2013-03-26 16:53:57 +0200 | [diff] [blame] | 701 | struct dw_dma *dw = to_dw_dma(chan->device); |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 702 | struct dw_desc *desc; |
| 703 | struct dw_desc *first; |
| 704 | struct dw_desc *prev; |
| 705 | size_t xfer_count; |
| 706 | size_t offset; |
| 707 | unsigned int src_width; |
| 708 | unsigned int dst_width; |
Andy Shevchenko | 3d4f860 | 2012-10-01 13:06:25 +0300 | [diff] [blame] | 709 | unsigned int data_width; |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 710 | u32 ctllo; |
| 711 | |
Andy Shevchenko | 2f45d61 | 2012-06-19 13:34:02 +0300 | [diff] [blame] | 712 | dev_vdbg(chan2dev(chan), |
Andy Shevchenko | 5a87f0e | 2014-01-13 14:04:50 +0200 | [diff] [blame] | 713 | "%s: d%pad s%pad l0x%zx f0x%lx\n", __func__, |
| 714 | &dest, &src, len, flags); |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 715 | |
| 716 | if (unlikely(!len)) { |
Andy Shevchenko | 2e4c364 | 2012-06-19 13:34:05 +0300 | [diff] [blame] | 717 | dev_dbg(chan2dev(chan), "%s: length is zero!\n", __func__); |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 718 | return NULL; |
| 719 | } |
| 720 | |
Andy Shevchenko | 0fdb567 | 2013-01-10 10:53:03 +0200 | [diff] [blame] | 721 | dwc->direction = DMA_MEM_TO_MEM; |
| 722 | |
Arnd Bergmann | f776076 | 2013-03-26 16:53:57 +0200 | [diff] [blame] | 723 | data_width = min_t(unsigned int, dw->data_width[dwc->src_master], |
| 724 | dw->data_width[dwc->dst_master]); |
Andy Shevchenko | a098200 | 2012-09-21 15:05:48 +0300 | [diff] [blame] | 725 | |
Andy Shevchenko | 3d4f860 | 2012-10-01 13:06:25 +0300 | [diff] [blame] | 726 | src_width = dst_width = min_t(unsigned int, data_width, |
| 727 | dwc_fast_fls(src | dest | len)); |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 728 | |
Viresh Kumar | 327e697 | 2012-02-01 16:12:26 +0530 | [diff] [blame] | 729 | ctllo = DWC_DEFAULT_CTLLO(chan) |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 730 | | DWC_CTLL_DST_WIDTH(dst_width) |
| 731 | | DWC_CTLL_SRC_WIDTH(src_width) |
| 732 | | DWC_CTLL_DST_INC |
| 733 | | DWC_CTLL_SRC_INC |
| 734 | | DWC_CTLL_FC_M2M; |
| 735 | prev = first = NULL; |
| 736 | |
| 737 | for (offset = 0; offset < len; offset += xfer_count << src_width) { |
| 738 | xfer_count = min_t(size_t, (len - offset) >> src_width, |
Andy Shevchenko | 4a63a8b | 2012-09-21 15:05:47 +0300 | [diff] [blame] | 739 | dwc->block_size); |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 740 | |
| 741 | desc = dwc_desc_get(dwc); |
| 742 | if (!desc) |
| 743 | goto err_desc_get; |
| 744 | |
| 745 | desc->lli.sar = src + offset; |
| 746 | desc->lli.dar = dest + offset; |
| 747 | desc->lli.ctllo = ctllo; |
| 748 | desc->lli.ctlhi = xfer_count; |
Andy Shevchenko | 176dcec | 2013-01-25 11:48:02 +0200 | [diff] [blame] | 749 | desc->len = xfer_count << src_width; |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 750 | |
| 751 | if (!first) { |
| 752 | first = desc; |
| 753 | } else { |
| 754 | prev->lli.llp = desc->txd.phys; |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 755 | list_add_tail(&desc->desc_node, |
Dan Williams | e0bd0f8 | 2009-09-08 17:53:02 -0700 | [diff] [blame] | 756 | &first->tx_list); |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 757 | } |
| 758 | prev = desc; |
| 759 | } |
| 760 | |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 761 | if (flags & DMA_PREP_INTERRUPT) |
| 762 | /* Trigger interrupt after last block */ |
| 763 | prev->lli.ctllo |= DWC_CTLL_INT_EN; |
| 764 | |
| 765 | prev->lli.llp = 0; |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 766 | first->txd.flags = flags; |
Andy Shevchenko | 30d38a3 | 2013-01-25 11:48:01 +0200 | [diff] [blame] | 767 | first->total_len = len; |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 768 | |
| 769 | return &first->txd; |
| 770 | |
| 771 | err_desc_get: |
| 772 | dwc_desc_put(dwc, first); |
| 773 | return NULL; |
| 774 | } |
| 775 | |
| 776 | static struct dma_async_tx_descriptor * |
| 777 | dwc_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl, |
Vinod Koul | db8196d | 2011-10-13 22:34:23 +0530 | [diff] [blame] | 778 | unsigned int sg_len, enum dma_transfer_direction direction, |
Alexandre Bounine | 185ecb5 | 2012-03-08 15:35:13 -0500 | [diff] [blame] | 779 | unsigned long flags, void *context) |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 780 | { |
| 781 | struct dw_dma_chan *dwc = to_dw_dma_chan(chan); |
Arnd Bergmann | f776076 | 2013-03-26 16:53:57 +0200 | [diff] [blame] | 782 | struct dw_dma *dw = to_dw_dma(chan->device); |
Viresh Kumar | 327e697 | 2012-02-01 16:12:26 +0530 | [diff] [blame] | 783 | struct dma_slave_config *sconfig = &dwc->dma_sconfig; |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 784 | struct dw_desc *prev; |
| 785 | struct dw_desc *first; |
| 786 | u32 ctllo; |
| 787 | dma_addr_t reg; |
| 788 | unsigned int reg_width; |
| 789 | unsigned int mem_width; |
Andy Shevchenko | a098200 | 2012-09-21 15:05:48 +0300 | [diff] [blame] | 790 | unsigned int data_width; |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 791 | unsigned int i; |
| 792 | struct scatterlist *sg; |
| 793 | size_t total_len = 0; |
| 794 | |
Andy Shevchenko | 2e4c364 | 2012-06-19 13:34:05 +0300 | [diff] [blame] | 795 | dev_vdbg(chan2dev(chan), "%s\n", __func__); |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 796 | |
Andy Shevchenko | 495aea4 | 2013-01-10 11:11:41 +0200 | [diff] [blame] | 797 | if (unlikely(!is_slave_direction(direction) || !sg_len)) |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 798 | return NULL; |
| 799 | |
Andy Shevchenko | 0fdb567 | 2013-01-10 10:53:03 +0200 | [diff] [blame] | 800 | dwc->direction = direction; |
| 801 | |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 802 | prev = first = NULL; |
| 803 | |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 804 | switch (direction) { |
Vinod Koul | db8196d | 2011-10-13 22:34:23 +0530 | [diff] [blame] | 805 | case DMA_MEM_TO_DEV: |
Viresh Kumar | 327e697 | 2012-02-01 16:12:26 +0530 | [diff] [blame] | 806 | reg_width = __fls(sconfig->dst_addr_width); |
| 807 | reg = sconfig->dst_addr; |
| 808 | ctllo = (DWC_DEFAULT_CTLLO(chan) |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 809 | | DWC_CTLL_DST_WIDTH(reg_width) |
| 810 | | DWC_CTLL_DST_FIX |
Viresh Kumar | 327e697 | 2012-02-01 16:12:26 +0530 | [diff] [blame] | 811 | | DWC_CTLL_SRC_INC); |
| 812 | |
| 813 | ctllo |= sconfig->device_fc ? DWC_CTLL_FC(DW_DMA_FC_P_M2P) : |
| 814 | DWC_CTLL_FC(DW_DMA_FC_D_M2P); |
| 815 | |
Arnd Bergmann | f776076 | 2013-03-26 16:53:57 +0200 | [diff] [blame] | 816 | data_width = dw->data_width[dwc->src_master]; |
Andy Shevchenko | a098200 | 2012-09-21 15:05:48 +0300 | [diff] [blame] | 817 | |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 818 | for_each_sg(sgl, sg, sg_len, i) { |
| 819 | struct dw_desc *desc; |
Viresh Kumar | 69dc14b | 2011-04-18 14:54:56 +0530 | [diff] [blame] | 820 | u32 len, dlen, mem; |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 821 | |
Lars-Peter Clausen | cbb796c | 2012-04-25 20:50:51 +0200 | [diff] [blame] | 822 | mem = sg_dma_address(sg); |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 823 | len = sg_dma_len(sg); |
Viresh Kumar | 6bc711f | 2012-02-01 16:12:25 +0530 | [diff] [blame] | 824 | |
Andy Shevchenko | a098200 | 2012-09-21 15:05:48 +0300 | [diff] [blame] | 825 | mem_width = min_t(unsigned int, |
| 826 | data_width, dwc_fast_fls(mem | len)); |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 827 | |
Viresh Kumar | 69dc14b | 2011-04-18 14:54:56 +0530 | [diff] [blame] | 828 | slave_sg_todev_fill_desc: |
| 829 | desc = dwc_desc_get(dwc); |
| 830 | if (!desc) { |
| 831 | dev_err(chan2dev(chan), |
| 832 | "not enough descriptors available\n"); |
| 833 | goto err_desc_get; |
| 834 | } |
| 835 | |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 836 | desc->lli.sar = mem; |
| 837 | desc->lli.dar = reg; |
| 838 | desc->lli.ctllo = ctllo | DWC_CTLL_SRC_WIDTH(mem_width); |
Andy Shevchenko | 4a63a8b | 2012-09-21 15:05:47 +0300 | [diff] [blame] | 839 | if ((len >> mem_width) > dwc->block_size) { |
| 840 | dlen = dwc->block_size << mem_width; |
Viresh Kumar | 69dc14b | 2011-04-18 14:54:56 +0530 | [diff] [blame] | 841 | mem += dlen; |
| 842 | len -= dlen; |
| 843 | } else { |
| 844 | dlen = len; |
| 845 | len = 0; |
| 846 | } |
| 847 | |
| 848 | desc->lli.ctlhi = dlen >> mem_width; |
Andy Shevchenko | 176dcec | 2013-01-25 11:48:02 +0200 | [diff] [blame] | 849 | desc->len = dlen; |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 850 | |
| 851 | if (!first) { |
| 852 | first = desc; |
| 853 | } else { |
| 854 | prev->lli.llp = desc->txd.phys; |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 855 | list_add_tail(&desc->desc_node, |
Dan Williams | e0bd0f8 | 2009-09-08 17:53:02 -0700 | [diff] [blame] | 856 | &first->tx_list); |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 857 | } |
| 858 | prev = desc; |
Viresh Kumar | 69dc14b | 2011-04-18 14:54:56 +0530 | [diff] [blame] | 859 | total_len += dlen; |
| 860 | |
| 861 | if (len) |
| 862 | goto slave_sg_todev_fill_desc; |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 863 | } |
| 864 | break; |
Vinod Koul | db8196d | 2011-10-13 22:34:23 +0530 | [diff] [blame] | 865 | case DMA_DEV_TO_MEM: |
Viresh Kumar | 327e697 | 2012-02-01 16:12:26 +0530 | [diff] [blame] | 866 | reg_width = __fls(sconfig->src_addr_width); |
| 867 | reg = sconfig->src_addr; |
| 868 | ctllo = (DWC_DEFAULT_CTLLO(chan) |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 869 | | DWC_CTLL_SRC_WIDTH(reg_width) |
| 870 | | DWC_CTLL_DST_INC |
Viresh Kumar | 327e697 | 2012-02-01 16:12:26 +0530 | [diff] [blame] | 871 | | DWC_CTLL_SRC_FIX); |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 872 | |
Viresh Kumar | 327e697 | 2012-02-01 16:12:26 +0530 | [diff] [blame] | 873 | ctllo |= sconfig->device_fc ? DWC_CTLL_FC(DW_DMA_FC_P_P2M) : |
| 874 | DWC_CTLL_FC(DW_DMA_FC_D_P2M); |
| 875 | |
Arnd Bergmann | f776076 | 2013-03-26 16:53:57 +0200 | [diff] [blame] | 876 | data_width = dw->data_width[dwc->dst_master]; |
Andy Shevchenko | a098200 | 2012-09-21 15:05:48 +0300 | [diff] [blame] | 877 | |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 878 | for_each_sg(sgl, sg, sg_len, i) { |
| 879 | struct dw_desc *desc; |
Viresh Kumar | 69dc14b | 2011-04-18 14:54:56 +0530 | [diff] [blame] | 880 | u32 len, dlen, mem; |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 881 | |
Lars-Peter Clausen | cbb796c | 2012-04-25 20:50:51 +0200 | [diff] [blame] | 882 | mem = sg_dma_address(sg); |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 883 | len = sg_dma_len(sg); |
Viresh Kumar | 6bc711f | 2012-02-01 16:12:25 +0530 | [diff] [blame] | 884 | |
Andy Shevchenko | a098200 | 2012-09-21 15:05:48 +0300 | [diff] [blame] | 885 | mem_width = min_t(unsigned int, |
| 886 | data_width, dwc_fast_fls(mem | len)); |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 887 | |
Viresh Kumar | 69dc14b | 2011-04-18 14:54:56 +0530 | [diff] [blame] | 888 | slave_sg_fromdev_fill_desc: |
| 889 | desc = dwc_desc_get(dwc); |
| 890 | if (!desc) { |
| 891 | dev_err(chan2dev(chan), |
| 892 | "not enough descriptors available\n"); |
| 893 | goto err_desc_get; |
| 894 | } |
| 895 | |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 896 | desc->lli.sar = reg; |
| 897 | desc->lli.dar = mem; |
| 898 | desc->lli.ctllo = ctllo | DWC_CTLL_DST_WIDTH(mem_width); |
Andy Shevchenko | 4a63a8b | 2012-09-21 15:05:47 +0300 | [diff] [blame] | 899 | if ((len >> reg_width) > dwc->block_size) { |
| 900 | dlen = dwc->block_size << reg_width; |
Viresh Kumar | 69dc14b | 2011-04-18 14:54:56 +0530 | [diff] [blame] | 901 | mem += dlen; |
| 902 | len -= dlen; |
| 903 | } else { |
| 904 | dlen = len; |
| 905 | len = 0; |
| 906 | } |
| 907 | desc->lli.ctlhi = dlen >> reg_width; |
Andy Shevchenko | 176dcec | 2013-01-25 11:48:02 +0200 | [diff] [blame] | 908 | desc->len = dlen; |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 909 | |
| 910 | if (!first) { |
| 911 | first = desc; |
| 912 | } else { |
| 913 | prev->lli.llp = desc->txd.phys; |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 914 | list_add_tail(&desc->desc_node, |
Dan Williams | e0bd0f8 | 2009-09-08 17:53:02 -0700 | [diff] [blame] | 915 | &first->tx_list); |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 916 | } |
| 917 | prev = desc; |
Viresh Kumar | 69dc14b | 2011-04-18 14:54:56 +0530 | [diff] [blame] | 918 | total_len += dlen; |
| 919 | |
| 920 | if (len) |
| 921 | goto slave_sg_fromdev_fill_desc; |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 922 | } |
| 923 | break; |
| 924 | default: |
| 925 | return NULL; |
| 926 | } |
| 927 | |
| 928 | if (flags & DMA_PREP_INTERRUPT) |
| 929 | /* Trigger interrupt after last block */ |
| 930 | prev->lli.ctllo |= DWC_CTLL_INT_EN; |
| 931 | |
| 932 | prev->lli.llp = 0; |
Andy Shevchenko | 30d38a3 | 2013-01-25 11:48:01 +0200 | [diff] [blame] | 933 | first->total_len = total_len; |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 934 | |
| 935 | return &first->txd; |
| 936 | |
| 937 | err_desc_get: |
| 938 | dwc_desc_put(dwc, first); |
| 939 | return NULL; |
| 940 | } |
| 941 | |
Viresh Kumar | 327e697 | 2012-02-01 16:12:26 +0530 | [diff] [blame] | 942 | /* |
| 943 | * Fix sconfig's burst size according to dw_dmac. We need to convert them as: |
| 944 | * 1 -> 0, 4 -> 1, 8 -> 2, 16 -> 3. |
| 945 | * |
| 946 | * NOTE: burst size 2 is not supported by controller. |
| 947 | * |
| 948 | * This can be done by finding least significant bit set: n & (n - 1) |
| 949 | */ |
| 950 | static inline void convert_burst(u32 *maxburst) |
| 951 | { |
| 952 | if (*maxburst > 1) |
| 953 | *maxburst = fls(*maxburst) - 2; |
| 954 | else |
| 955 | *maxburst = 0; |
| 956 | } |
| 957 | |
| 958 | static int |
| 959 | set_runtime_config(struct dma_chan *chan, struct dma_slave_config *sconfig) |
| 960 | { |
| 961 | struct dw_dma_chan *dwc = to_dw_dma_chan(chan); |
| 962 | |
Andy Shevchenko | 495aea4 | 2013-01-10 11:11:41 +0200 | [diff] [blame] | 963 | /* Check if chan will be configured for slave transfers */ |
| 964 | if (!is_slave_direction(sconfig->direction)) |
Viresh Kumar | 327e697 | 2012-02-01 16:12:26 +0530 | [diff] [blame] | 965 | return -EINVAL; |
| 966 | |
| 967 | memcpy(&dwc->dma_sconfig, sconfig, sizeof(*sconfig)); |
Andy Shevchenko | 0fdb567 | 2013-01-10 10:53:03 +0200 | [diff] [blame] | 968 | dwc->direction = sconfig->direction; |
Viresh Kumar | 327e697 | 2012-02-01 16:12:26 +0530 | [diff] [blame] | 969 | |
Arnd Bergmann | f776076 | 2013-03-26 16:53:57 +0200 | [diff] [blame] | 970 | /* Take the request line from slave_id member */ |
Andy Shevchenko | 78f3c9d | 2013-07-15 15:04:38 +0300 | [diff] [blame] | 971 | if (is_request_line_unset(dwc)) |
Arnd Bergmann | f776076 | 2013-03-26 16:53:57 +0200 | [diff] [blame] | 972 | dwc->request_line = sconfig->slave_id; |
| 973 | |
Viresh Kumar | 327e697 | 2012-02-01 16:12:26 +0530 | [diff] [blame] | 974 | convert_burst(&dwc->dma_sconfig.src_maxburst); |
| 975 | convert_burst(&dwc->dma_sconfig.dst_maxburst); |
| 976 | |
| 977 | return 0; |
| 978 | } |
| 979 | |
Andy Shevchenko | 21fe3c5 | 2013-01-09 10:17:14 +0200 | [diff] [blame] | 980 | static inline void dwc_chan_pause(struct dw_dma_chan *dwc) |
| 981 | { |
| 982 | u32 cfglo = channel_readl(dwc, CFG_LO); |
Andy Shevchenko | 123b69a | 2013-03-21 11:49:17 +0200 | [diff] [blame] | 983 | unsigned int count = 20; /* timeout iterations */ |
Andy Shevchenko | 21fe3c5 | 2013-01-09 10:17:14 +0200 | [diff] [blame] | 984 | |
| 985 | channel_writel(dwc, CFG_LO, cfglo | DWC_CFGL_CH_SUSP); |
Andy Shevchenko | 123b69a | 2013-03-21 11:49:17 +0200 | [diff] [blame] | 986 | while (!(channel_readl(dwc, CFG_LO) & DWC_CFGL_FIFO_EMPTY) && count--) |
| 987 | udelay(2); |
Andy Shevchenko | 21fe3c5 | 2013-01-09 10:17:14 +0200 | [diff] [blame] | 988 | |
| 989 | dwc->paused = true; |
| 990 | } |
| 991 | |
| 992 | static inline void dwc_chan_resume(struct dw_dma_chan *dwc) |
| 993 | { |
| 994 | u32 cfglo = channel_readl(dwc, CFG_LO); |
| 995 | |
| 996 | channel_writel(dwc, CFG_LO, cfglo & ~DWC_CFGL_CH_SUSP); |
| 997 | |
| 998 | dwc->paused = false; |
| 999 | } |
| 1000 | |
Linus Walleij | 0582763 | 2010-05-17 16:30:42 -0700 | [diff] [blame] | 1001 | static int dwc_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd, |
| 1002 | unsigned long arg) |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 1003 | { |
| 1004 | struct dw_dma_chan *dwc = to_dw_dma_chan(chan); |
| 1005 | struct dw_dma *dw = to_dw_dma(chan->device); |
| 1006 | struct dw_desc *desc, *_desc; |
Viresh Kumar | 69cea5a | 2011-04-15 16:03:35 +0530 | [diff] [blame] | 1007 | unsigned long flags; |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 1008 | LIST_HEAD(list); |
| 1009 | |
Linus Walleij | a7c57cf | 2011-04-19 08:31:32 +0800 | [diff] [blame] | 1010 | if (cmd == DMA_PAUSE) { |
| 1011 | spin_lock_irqsave(&dwc->lock, flags); |
| 1012 | |
Andy Shevchenko | 21fe3c5 | 2013-01-09 10:17:14 +0200 | [diff] [blame] | 1013 | dwc_chan_pause(dwc); |
Linus Walleij | a7c57cf | 2011-04-19 08:31:32 +0800 | [diff] [blame] | 1014 | |
Linus Walleij | a7c57cf | 2011-04-19 08:31:32 +0800 | [diff] [blame] | 1015 | spin_unlock_irqrestore(&dwc->lock, flags); |
| 1016 | } else if (cmd == DMA_RESUME) { |
| 1017 | if (!dwc->paused) |
| 1018 | return 0; |
| 1019 | |
| 1020 | spin_lock_irqsave(&dwc->lock, flags); |
| 1021 | |
Andy Shevchenko | 21fe3c5 | 2013-01-09 10:17:14 +0200 | [diff] [blame] | 1022 | dwc_chan_resume(dwc); |
Linus Walleij | a7c57cf | 2011-04-19 08:31:32 +0800 | [diff] [blame] | 1023 | |
| 1024 | spin_unlock_irqrestore(&dwc->lock, flags); |
| 1025 | } else if (cmd == DMA_TERMINATE_ALL) { |
| 1026 | spin_lock_irqsave(&dwc->lock, flags); |
| 1027 | |
Andy Shevchenko | fed2574 | 2012-09-21 15:05:49 +0300 | [diff] [blame] | 1028 | clear_bit(DW_DMA_IS_SOFT_LLP, &dwc->flags); |
| 1029 | |
Andy Shevchenko | 3f936207 | 2012-06-19 13:46:32 +0300 | [diff] [blame] | 1030 | dwc_chan_disable(dw, dwc); |
Linus Walleij | a7c57cf | 2011-04-19 08:31:32 +0800 | [diff] [blame] | 1031 | |
Heikki Krogerus | a5dbff1 | 2013-01-10 10:53:06 +0200 | [diff] [blame] | 1032 | dwc_chan_resume(dwc); |
Linus Walleij | a7c57cf | 2011-04-19 08:31:32 +0800 | [diff] [blame] | 1033 | |
| 1034 | /* active_list entries will end up before queued entries */ |
| 1035 | list_splice_init(&dwc->queue, &list); |
| 1036 | list_splice_init(&dwc->active_list, &list); |
| 1037 | |
| 1038 | spin_unlock_irqrestore(&dwc->lock, flags); |
| 1039 | |
| 1040 | /* Flush all pending and queued descriptors */ |
| 1041 | list_for_each_entry_safe(desc, _desc, &list, desc_node) |
| 1042 | dwc_descriptor_complete(dwc, desc, false); |
Viresh Kumar | 327e697 | 2012-02-01 16:12:26 +0530 | [diff] [blame] | 1043 | } else if (cmd == DMA_SLAVE_CONFIG) { |
| 1044 | return set_runtime_config(chan, (struct dma_slave_config *)arg); |
| 1045 | } else { |
Linus Walleij | c3635c7 | 2010-03-26 16:44:01 -0700 | [diff] [blame] | 1046 | return -ENXIO; |
Viresh Kumar | 327e697 | 2012-02-01 16:12:26 +0530 | [diff] [blame] | 1047 | } |
Linus Walleij | c3635c7 | 2010-03-26 16:44:01 -0700 | [diff] [blame] | 1048 | |
Linus Walleij | c3635c7 | 2010-03-26 16:44:01 -0700 | [diff] [blame] | 1049 | return 0; |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 1050 | } |
| 1051 | |
Andy Shevchenko | 4702d52 | 2013-01-25 11:48:03 +0200 | [diff] [blame] | 1052 | static inline u32 dwc_get_residue(struct dw_dma_chan *dwc) |
| 1053 | { |
| 1054 | unsigned long flags; |
| 1055 | u32 residue; |
| 1056 | |
| 1057 | spin_lock_irqsave(&dwc->lock, flags); |
| 1058 | |
| 1059 | residue = dwc->residue; |
| 1060 | if (test_bit(DW_DMA_IS_SOFT_LLP, &dwc->flags) && residue) |
| 1061 | residue -= dwc_get_sent(dwc); |
| 1062 | |
| 1063 | spin_unlock_irqrestore(&dwc->lock, flags); |
| 1064 | return residue; |
| 1065 | } |
| 1066 | |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 1067 | static enum dma_status |
Linus Walleij | 0793448 | 2010-03-26 16:50:49 -0700 | [diff] [blame] | 1068 | dwc_tx_status(struct dma_chan *chan, |
| 1069 | dma_cookie_t cookie, |
| 1070 | struct dma_tx_state *txstate) |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 1071 | { |
| 1072 | struct dw_dma_chan *dwc = to_dw_dma_chan(chan); |
Russell King - ARM Linux | 96a2af4 | 2012-03-06 22:35:27 +0000 | [diff] [blame] | 1073 | enum dma_status ret; |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 1074 | |
Russell King - ARM Linux | 96a2af4 | 2012-03-06 22:35:27 +0000 | [diff] [blame] | 1075 | ret = dma_cookie_status(chan, cookie, txstate); |
Vinod Koul | 2c40410 | 2013-10-16 13:41:15 +0530 | [diff] [blame] | 1076 | if (ret == DMA_COMPLETE) |
Andy Shevchenko | 12381dc | 2013-07-15 15:04:40 +0300 | [diff] [blame] | 1077 | return ret; |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 1078 | |
Andy Shevchenko | 12381dc | 2013-07-15 15:04:40 +0300 | [diff] [blame] | 1079 | dwc_scan_descriptors(to_dw_dma(chan->device), dwc); |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 1080 | |
Andy Shevchenko | 12381dc | 2013-07-15 15:04:40 +0300 | [diff] [blame] | 1081 | ret = dma_cookie_status(chan, cookie, txstate); |
Vinod Koul | 2c40410 | 2013-10-16 13:41:15 +0530 | [diff] [blame] | 1082 | if (ret != DMA_COMPLETE) |
Andy Shevchenko | 4702d52 | 2013-01-25 11:48:03 +0200 | [diff] [blame] | 1083 | dma_set_residue(txstate, dwc_get_residue(dwc)); |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 1084 | |
Andy Shevchenko | effd5cf | 2013-07-15 15:04:41 +0300 | [diff] [blame] | 1085 | if (dwc->paused && ret == DMA_IN_PROGRESS) |
Linus Walleij | a7c57cf | 2011-04-19 08:31:32 +0800 | [diff] [blame] | 1086 | return DMA_PAUSED; |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 1087 | |
| 1088 | return ret; |
| 1089 | } |
| 1090 | |
| 1091 | static void dwc_issue_pending(struct dma_chan *chan) |
| 1092 | { |
| 1093 | struct dw_dma_chan *dwc = to_dw_dma_chan(chan); |
Andy Shevchenko | dd8ecfca | 2014-06-18 12:15:38 +0300 | [diff] [blame] | 1094 | unsigned long flags; |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 1095 | |
Andy Shevchenko | dd8ecfca | 2014-06-18 12:15:38 +0300 | [diff] [blame] | 1096 | spin_lock_irqsave(&dwc->lock, flags); |
| 1097 | if (list_empty(&dwc->active_list)) |
| 1098 | dwc_dostart_first_queued(dwc); |
| 1099 | spin_unlock_irqrestore(&dwc->lock, flags); |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 1100 | } |
| 1101 | |
Dan Williams | aa1e6f1 | 2009-01-06 11:38:17 -0700 | [diff] [blame] | 1102 | static int dwc_alloc_chan_resources(struct dma_chan *chan) |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 1103 | { |
| 1104 | struct dw_dma_chan *dwc = to_dw_dma_chan(chan); |
| 1105 | struct dw_dma *dw = to_dw_dma(chan->device); |
| 1106 | struct dw_desc *desc; |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 1107 | int i; |
Viresh Kumar | 69cea5a | 2011-04-15 16:03:35 +0530 | [diff] [blame] | 1108 | unsigned long flags; |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 1109 | |
Andy Shevchenko | 2e4c364 | 2012-06-19 13:34:05 +0300 | [diff] [blame] | 1110 | dev_vdbg(chan2dev(chan), "%s\n", __func__); |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 1111 | |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 1112 | /* ASSERT: channel is idle */ |
| 1113 | if (dma_readl(dw, CH_EN) & dwc->mask) { |
Dan Williams | 41d5e59 | 2009-01-06 11:38:21 -0700 | [diff] [blame] | 1114 | dev_dbg(chan2dev(chan), "DMA channel not idle?\n"); |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 1115 | return -EIO; |
| 1116 | } |
| 1117 | |
Russell King - ARM Linux | d3ee98cdc | 2012-03-06 22:35:47 +0000 | [diff] [blame] | 1118 | dma_cookie_init(chan); |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 1119 | |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 1120 | /* |
| 1121 | * NOTE: some controllers may have additional features that we |
| 1122 | * need to initialize here, like "scatter-gather" (which |
| 1123 | * doesn't mean what you think it means), and status writeback. |
| 1124 | */ |
| 1125 | |
Arnd Bergmann | f776076 | 2013-03-26 16:53:57 +0200 | [diff] [blame] | 1126 | dwc_set_masters(dwc); |
| 1127 | |
Viresh Kumar | 69cea5a | 2011-04-15 16:03:35 +0530 | [diff] [blame] | 1128 | spin_lock_irqsave(&dwc->lock, flags); |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 1129 | i = dwc->descs_allocated; |
| 1130 | while (dwc->descs_allocated < NR_DESCS_PER_CHANNEL) { |
Andy Shevchenko | f8122a8 | 2013-01-16 15:48:50 +0200 | [diff] [blame] | 1131 | dma_addr_t phys; |
| 1132 | |
Viresh Kumar | 69cea5a | 2011-04-15 16:03:35 +0530 | [diff] [blame] | 1133 | spin_unlock_irqrestore(&dwc->lock, flags); |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 1134 | |
Andy Shevchenko | f8122a8 | 2013-01-16 15:48:50 +0200 | [diff] [blame] | 1135 | desc = dma_pool_alloc(dw->desc_pool, GFP_ATOMIC, &phys); |
Andy Shevchenko | cbd6531 | 2013-01-09 10:17:11 +0200 | [diff] [blame] | 1136 | if (!desc) |
| 1137 | goto err_desc_alloc; |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 1138 | |
Andy Shevchenko | f8122a8 | 2013-01-16 15:48:50 +0200 | [diff] [blame] | 1139 | memset(desc, 0, sizeof(struct dw_desc)); |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 1140 | |
Dan Williams | e0bd0f8 | 2009-09-08 17:53:02 -0700 | [diff] [blame] | 1141 | INIT_LIST_HEAD(&desc->tx_list); |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 1142 | dma_async_tx_descriptor_init(&desc->txd, chan); |
| 1143 | desc->txd.tx_submit = dwc_tx_submit; |
| 1144 | desc->txd.flags = DMA_CTRL_ACK; |
Andy Shevchenko | f8122a8 | 2013-01-16 15:48:50 +0200 | [diff] [blame] | 1145 | desc->txd.phys = phys; |
Andy Shevchenko | cbd6531 | 2013-01-09 10:17:11 +0200 | [diff] [blame] | 1146 | |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 1147 | dwc_desc_put(dwc, desc); |
| 1148 | |
Viresh Kumar | 69cea5a | 2011-04-15 16:03:35 +0530 | [diff] [blame] | 1149 | spin_lock_irqsave(&dwc->lock, flags); |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 1150 | i = ++dwc->descs_allocated; |
| 1151 | } |
| 1152 | |
Viresh Kumar | 69cea5a | 2011-04-15 16:03:35 +0530 | [diff] [blame] | 1153 | spin_unlock_irqrestore(&dwc->lock, flags); |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 1154 | |
Andy Shevchenko | 2e4c364 | 2012-06-19 13:34:05 +0300 | [diff] [blame] | 1155 | dev_dbg(chan2dev(chan), "%s: allocated %d descriptors\n", __func__, i); |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 1156 | |
| 1157 | return i; |
Andy Shevchenko | cbd6531 | 2013-01-09 10:17:11 +0200 | [diff] [blame] | 1158 | |
| 1159 | err_desc_alloc: |
Andy Shevchenko | cbd6531 | 2013-01-09 10:17:11 +0200 | [diff] [blame] | 1160 | dev_info(chan2dev(chan), "only allocated %d descriptors\n", i); |
| 1161 | |
| 1162 | return i; |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 1163 | } |
| 1164 | |
| 1165 | static void dwc_free_chan_resources(struct dma_chan *chan) |
| 1166 | { |
| 1167 | struct dw_dma_chan *dwc = to_dw_dma_chan(chan); |
| 1168 | struct dw_dma *dw = to_dw_dma(chan->device); |
| 1169 | struct dw_desc *desc, *_desc; |
Viresh Kumar | 69cea5a | 2011-04-15 16:03:35 +0530 | [diff] [blame] | 1170 | unsigned long flags; |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 1171 | LIST_HEAD(list); |
| 1172 | |
Andy Shevchenko | 2e4c364 | 2012-06-19 13:34:05 +0300 | [diff] [blame] | 1173 | dev_dbg(chan2dev(chan), "%s: descs allocated=%u\n", __func__, |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 1174 | dwc->descs_allocated); |
| 1175 | |
| 1176 | /* ASSERT: channel is idle */ |
| 1177 | BUG_ON(!list_empty(&dwc->active_list)); |
| 1178 | BUG_ON(!list_empty(&dwc->queue)); |
| 1179 | BUG_ON(dma_readl(to_dw_dma(chan->device), CH_EN) & dwc->mask); |
| 1180 | |
Viresh Kumar | 69cea5a | 2011-04-15 16:03:35 +0530 | [diff] [blame] | 1181 | spin_lock_irqsave(&dwc->lock, flags); |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 1182 | list_splice_init(&dwc->free_list, &list); |
| 1183 | dwc->descs_allocated = 0; |
Viresh Kumar | 61e183f | 2011-11-17 16:01:29 +0530 | [diff] [blame] | 1184 | dwc->initialized = false; |
Arnd Bergmann | f776076 | 2013-03-26 16:53:57 +0200 | [diff] [blame] | 1185 | dwc->request_line = ~0; |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 1186 | |
| 1187 | /* Disable interrupts */ |
| 1188 | channel_clear_bit(dw, MASK.XFER, dwc->mask); |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 1189 | channel_clear_bit(dw, MASK.ERROR, dwc->mask); |
| 1190 | |
Viresh Kumar | 69cea5a | 2011-04-15 16:03:35 +0530 | [diff] [blame] | 1191 | spin_unlock_irqrestore(&dwc->lock, flags); |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 1192 | |
| 1193 | list_for_each_entry_safe(desc, _desc, &list, desc_node) { |
Dan Williams | 41d5e59 | 2009-01-06 11:38:21 -0700 | [diff] [blame] | 1194 | dev_vdbg(chan2dev(chan), " freeing descriptor %p\n", desc); |
Andy Shevchenko | f8122a8 | 2013-01-16 15:48:50 +0200 | [diff] [blame] | 1195 | dma_pool_free(dw->desc_pool, desc, desc->txd.phys); |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 1196 | } |
| 1197 | |
Andy Shevchenko | 2e4c364 | 2012-06-19 13:34:05 +0300 | [diff] [blame] | 1198 | dev_vdbg(chan2dev(chan), "%s: done\n", __func__); |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 1199 | } |
| 1200 | |
Hans-Christian Egtvedt | d9de451 | 2009-04-01 15:47:02 +0200 | [diff] [blame] | 1201 | /* --------------------- Cyclic DMA API extensions -------------------- */ |
| 1202 | |
| 1203 | /** |
| 1204 | * dw_dma_cyclic_start - start the cyclic DMA transfer |
| 1205 | * @chan: the DMA channel to start |
| 1206 | * |
| 1207 | * Must be called with soft interrupts disabled. Returns zero on success or |
| 1208 | * -errno on failure. |
| 1209 | */ |
| 1210 | int dw_dma_cyclic_start(struct dma_chan *chan) |
| 1211 | { |
| 1212 | struct dw_dma_chan *dwc = to_dw_dma_chan(chan); |
| 1213 | struct dw_dma *dw = to_dw_dma(dwc->chan.device); |
Viresh Kumar | 69cea5a | 2011-04-15 16:03:35 +0530 | [diff] [blame] | 1214 | unsigned long flags; |
Hans-Christian Egtvedt | d9de451 | 2009-04-01 15:47:02 +0200 | [diff] [blame] | 1215 | |
| 1216 | if (!test_bit(DW_DMA_IS_CYCLIC, &dwc->flags)) { |
| 1217 | dev_err(chan2dev(&dwc->chan), "missing prep for cyclic DMA\n"); |
| 1218 | return -ENODEV; |
| 1219 | } |
| 1220 | |
Viresh Kumar | 69cea5a | 2011-04-15 16:03:35 +0530 | [diff] [blame] | 1221 | spin_lock_irqsave(&dwc->lock, flags); |
Hans-Christian Egtvedt | d9de451 | 2009-04-01 15:47:02 +0200 | [diff] [blame] | 1222 | |
Andy Shevchenko | 75c6122 | 2013-03-26 16:53:54 +0200 | [diff] [blame] | 1223 | /* Assert channel is idle */ |
Hans-Christian Egtvedt | d9de451 | 2009-04-01 15:47:02 +0200 | [diff] [blame] | 1224 | if (dma_readl(dw, CH_EN) & dwc->mask) { |
| 1225 | dev_err(chan2dev(&dwc->chan), |
| 1226 | "BUG: Attempted to start non-idle channel\n"); |
Andy Shevchenko | 1d45543 | 2012-06-19 13:34:03 +0300 | [diff] [blame] | 1227 | dwc_dump_chan_regs(dwc); |
Viresh Kumar | 69cea5a | 2011-04-15 16:03:35 +0530 | [diff] [blame] | 1228 | spin_unlock_irqrestore(&dwc->lock, flags); |
Hans-Christian Egtvedt | d9de451 | 2009-04-01 15:47:02 +0200 | [diff] [blame] | 1229 | return -EBUSY; |
| 1230 | } |
| 1231 | |
Hans-Christian Egtvedt | d9de451 | 2009-04-01 15:47:02 +0200 | [diff] [blame] | 1232 | dma_writel(dw, CLEAR.ERROR, dwc->mask); |
| 1233 | dma_writel(dw, CLEAR.XFER, dwc->mask); |
| 1234 | |
Andy Shevchenko | 75c6122 | 2013-03-26 16:53:54 +0200 | [diff] [blame] | 1235 | /* Setup DMAC channel registers */ |
Hans-Christian Egtvedt | d9de451 | 2009-04-01 15:47:02 +0200 | [diff] [blame] | 1236 | channel_writel(dwc, LLP, dwc->cdesc->desc[0]->txd.phys); |
| 1237 | channel_writel(dwc, CTL_LO, DWC_CTLL_LLP_D_EN | DWC_CTLL_LLP_S_EN); |
| 1238 | channel_writel(dwc, CTL_HI, 0); |
| 1239 | |
| 1240 | channel_set_bit(dw, CH_EN, dwc->mask); |
| 1241 | |
Viresh Kumar | 69cea5a | 2011-04-15 16:03:35 +0530 | [diff] [blame] | 1242 | spin_unlock_irqrestore(&dwc->lock, flags); |
Hans-Christian Egtvedt | d9de451 | 2009-04-01 15:47:02 +0200 | [diff] [blame] | 1243 | |
| 1244 | return 0; |
| 1245 | } |
| 1246 | EXPORT_SYMBOL(dw_dma_cyclic_start); |
| 1247 | |
| 1248 | /** |
| 1249 | * dw_dma_cyclic_stop - stop the cyclic DMA transfer |
| 1250 | * @chan: the DMA channel to stop |
| 1251 | * |
| 1252 | * Must be called with soft interrupts disabled. |
| 1253 | */ |
| 1254 | void dw_dma_cyclic_stop(struct dma_chan *chan) |
| 1255 | { |
| 1256 | struct dw_dma_chan *dwc = to_dw_dma_chan(chan); |
| 1257 | struct dw_dma *dw = to_dw_dma(dwc->chan.device); |
Viresh Kumar | 69cea5a | 2011-04-15 16:03:35 +0530 | [diff] [blame] | 1258 | unsigned long flags; |
Hans-Christian Egtvedt | d9de451 | 2009-04-01 15:47:02 +0200 | [diff] [blame] | 1259 | |
Viresh Kumar | 69cea5a | 2011-04-15 16:03:35 +0530 | [diff] [blame] | 1260 | spin_lock_irqsave(&dwc->lock, flags); |
Hans-Christian Egtvedt | d9de451 | 2009-04-01 15:47:02 +0200 | [diff] [blame] | 1261 | |
Andy Shevchenko | 3f936207 | 2012-06-19 13:46:32 +0300 | [diff] [blame] | 1262 | dwc_chan_disable(dw, dwc); |
Hans-Christian Egtvedt | d9de451 | 2009-04-01 15:47:02 +0200 | [diff] [blame] | 1263 | |
Viresh Kumar | 69cea5a | 2011-04-15 16:03:35 +0530 | [diff] [blame] | 1264 | spin_unlock_irqrestore(&dwc->lock, flags); |
Hans-Christian Egtvedt | d9de451 | 2009-04-01 15:47:02 +0200 | [diff] [blame] | 1265 | } |
| 1266 | EXPORT_SYMBOL(dw_dma_cyclic_stop); |
| 1267 | |
| 1268 | /** |
| 1269 | * dw_dma_cyclic_prep - prepare the cyclic DMA transfer |
| 1270 | * @chan: the DMA channel to prepare |
| 1271 | * @buf_addr: physical DMA address where the buffer starts |
| 1272 | * @buf_len: total number of bytes for the entire buffer |
| 1273 | * @period_len: number of bytes for each period |
| 1274 | * @direction: transfer direction, to or from device |
| 1275 | * |
| 1276 | * Must be called before trying to start the transfer. Returns a valid struct |
| 1277 | * dw_cyclic_desc if successful or an ERR_PTR(-errno) if not successful. |
| 1278 | */ |
| 1279 | struct dw_cyclic_desc *dw_dma_cyclic_prep(struct dma_chan *chan, |
| 1280 | dma_addr_t buf_addr, size_t buf_len, size_t period_len, |
Vinod Koul | db8196d | 2011-10-13 22:34:23 +0530 | [diff] [blame] | 1281 | enum dma_transfer_direction direction) |
Hans-Christian Egtvedt | d9de451 | 2009-04-01 15:47:02 +0200 | [diff] [blame] | 1282 | { |
| 1283 | struct dw_dma_chan *dwc = to_dw_dma_chan(chan); |
Viresh Kumar | 327e697 | 2012-02-01 16:12:26 +0530 | [diff] [blame] | 1284 | struct dma_slave_config *sconfig = &dwc->dma_sconfig; |
Hans-Christian Egtvedt | d9de451 | 2009-04-01 15:47:02 +0200 | [diff] [blame] | 1285 | struct dw_cyclic_desc *cdesc; |
| 1286 | struct dw_cyclic_desc *retval = NULL; |
| 1287 | struct dw_desc *desc; |
| 1288 | struct dw_desc *last = NULL; |
Hans-Christian Egtvedt | d9de451 | 2009-04-01 15:47:02 +0200 | [diff] [blame] | 1289 | unsigned long was_cyclic; |
| 1290 | unsigned int reg_width; |
| 1291 | unsigned int periods; |
| 1292 | unsigned int i; |
Viresh Kumar | 69cea5a | 2011-04-15 16:03:35 +0530 | [diff] [blame] | 1293 | unsigned long flags; |
Hans-Christian Egtvedt | d9de451 | 2009-04-01 15:47:02 +0200 | [diff] [blame] | 1294 | |
Viresh Kumar | 69cea5a | 2011-04-15 16:03:35 +0530 | [diff] [blame] | 1295 | spin_lock_irqsave(&dwc->lock, flags); |
Andy Shevchenko | fed2574 | 2012-09-21 15:05:49 +0300 | [diff] [blame] | 1296 | if (dwc->nollp) { |
| 1297 | spin_unlock_irqrestore(&dwc->lock, flags); |
| 1298 | dev_dbg(chan2dev(&dwc->chan), |
| 1299 | "channel doesn't support LLP transfers\n"); |
| 1300 | return ERR_PTR(-EINVAL); |
| 1301 | } |
| 1302 | |
Hans-Christian Egtvedt | d9de451 | 2009-04-01 15:47:02 +0200 | [diff] [blame] | 1303 | if (!list_empty(&dwc->queue) || !list_empty(&dwc->active_list)) { |
Viresh Kumar | 69cea5a | 2011-04-15 16:03:35 +0530 | [diff] [blame] | 1304 | spin_unlock_irqrestore(&dwc->lock, flags); |
Hans-Christian Egtvedt | d9de451 | 2009-04-01 15:47:02 +0200 | [diff] [blame] | 1305 | dev_dbg(chan2dev(&dwc->chan), |
| 1306 | "queue and/or active list are not empty\n"); |
| 1307 | return ERR_PTR(-EBUSY); |
| 1308 | } |
| 1309 | |
| 1310 | was_cyclic = test_and_set_bit(DW_DMA_IS_CYCLIC, &dwc->flags); |
Viresh Kumar | 69cea5a | 2011-04-15 16:03:35 +0530 | [diff] [blame] | 1311 | spin_unlock_irqrestore(&dwc->lock, flags); |
Hans-Christian Egtvedt | d9de451 | 2009-04-01 15:47:02 +0200 | [diff] [blame] | 1312 | if (was_cyclic) { |
| 1313 | dev_dbg(chan2dev(&dwc->chan), |
| 1314 | "channel already prepared for cyclic DMA\n"); |
| 1315 | return ERR_PTR(-EBUSY); |
| 1316 | } |
| 1317 | |
| 1318 | retval = ERR_PTR(-EINVAL); |
Viresh Kumar | 327e697 | 2012-02-01 16:12:26 +0530 | [diff] [blame] | 1319 | |
Andy Shevchenko | f44b92f | 2013-01-10 10:52:58 +0200 | [diff] [blame] | 1320 | if (unlikely(!is_slave_direction(direction))) |
| 1321 | goto out_err; |
| 1322 | |
Andy Shevchenko | 0fdb567 | 2013-01-10 10:53:03 +0200 | [diff] [blame] | 1323 | dwc->direction = direction; |
| 1324 | |
Viresh Kumar | 327e697 | 2012-02-01 16:12:26 +0530 | [diff] [blame] | 1325 | if (direction == DMA_MEM_TO_DEV) |
| 1326 | reg_width = __ffs(sconfig->dst_addr_width); |
| 1327 | else |
| 1328 | reg_width = __ffs(sconfig->src_addr_width); |
| 1329 | |
Hans-Christian Egtvedt | d9de451 | 2009-04-01 15:47:02 +0200 | [diff] [blame] | 1330 | periods = buf_len / period_len; |
| 1331 | |
| 1332 | /* Check for too big/unaligned periods and unaligned DMA buffer. */ |
Andy Shevchenko | 4a63a8b | 2012-09-21 15:05:47 +0300 | [diff] [blame] | 1333 | if (period_len > (dwc->block_size << reg_width)) |
Hans-Christian Egtvedt | d9de451 | 2009-04-01 15:47:02 +0200 | [diff] [blame] | 1334 | goto out_err; |
| 1335 | if (unlikely(period_len & ((1 << reg_width) - 1))) |
| 1336 | goto out_err; |
| 1337 | if (unlikely(buf_addr & ((1 << reg_width) - 1))) |
| 1338 | goto out_err; |
Hans-Christian Egtvedt | d9de451 | 2009-04-01 15:47:02 +0200 | [diff] [blame] | 1339 | |
| 1340 | retval = ERR_PTR(-ENOMEM); |
| 1341 | |
| 1342 | if (periods > NR_DESCS_PER_CHANNEL) |
| 1343 | goto out_err; |
| 1344 | |
| 1345 | cdesc = kzalloc(sizeof(struct dw_cyclic_desc), GFP_KERNEL); |
| 1346 | if (!cdesc) |
| 1347 | goto out_err; |
| 1348 | |
| 1349 | cdesc->desc = kzalloc(sizeof(struct dw_desc *) * periods, GFP_KERNEL); |
| 1350 | if (!cdesc->desc) |
| 1351 | goto out_err_alloc; |
| 1352 | |
| 1353 | for (i = 0; i < periods; i++) { |
| 1354 | desc = dwc_desc_get(dwc); |
| 1355 | if (!desc) |
| 1356 | goto out_err_desc_get; |
| 1357 | |
| 1358 | switch (direction) { |
Vinod Koul | db8196d | 2011-10-13 22:34:23 +0530 | [diff] [blame] | 1359 | case DMA_MEM_TO_DEV: |
Viresh Kumar | 327e697 | 2012-02-01 16:12:26 +0530 | [diff] [blame] | 1360 | desc->lli.dar = sconfig->dst_addr; |
Hans-Christian Egtvedt | d9de451 | 2009-04-01 15:47:02 +0200 | [diff] [blame] | 1361 | desc->lli.sar = buf_addr + (period_len * i); |
Viresh Kumar | 327e697 | 2012-02-01 16:12:26 +0530 | [diff] [blame] | 1362 | desc->lli.ctllo = (DWC_DEFAULT_CTLLO(chan) |
Hans-Christian Egtvedt | d9de451 | 2009-04-01 15:47:02 +0200 | [diff] [blame] | 1363 | | DWC_CTLL_DST_WIDTH(reg_width) |
| 1364 | | DWC_CTLL_SRC_WIDTH(reg_width) |
| 1365 | | DWC_CTLL_DST_FIX |
| 1366 | | DWC_CTLL_SRC_INC |
Hans-Christian Egtvedt | d9de451 | 2009-04-01 15:47:02 +0200 | [diff] [blame] | 1367 | | DWC_CTLL_INT_EN); |
Viresh Kumar | 327e697 | 2012-02-01 16:12:26 +0530 | [diff] [blame] | 1368 | |
| 1369 | desc->lli.ctllo |= sconfig->device_fc ? |
| 1370 | DWC_CTLL_FC(DW_DMA_FC_P_M2P) : |
| 1371 | DWC_CTLL_FC(DW_DMA_FC_D_M2P); |
| 1372 | |
Hans-Christian Egtvedt | d9de451 | 2009-04-01 15:47:02 +0200 | [diff] [blame] | 1373 | break; |
Vinod Koul | db8196d | 2011-10-13 22:34:23 +0530 | [diff] [blame] | 1374 | case DMA_DEV_TO_MEM: |
Hans-Christian Egtvedt | d9de451 | 2009-04-01 15:47:02 +0200 | [diff] [blame] | 1375 | desc->lli.dar = buf_addr + (period_len * i); |
Viresh Kumar | 327e697 | 2012-02-01 16:12:26 +0530 | [diff] [blame] | 1376 | desc->lli.sar = sconfig->src_addr; |
| 1377 | desc->lli.ctllo = (DWC_DEFAULT_CTLLO(chan) |
Hans-Christian Egtvedt | d9de451 | 2009-04-01 15:47:02 +0200 | [diff] [blame] | 1378 | | DWC_CTLL_SRC_WIDTH(reg_width) |
| 1379 | | DWC_CTLL_DST_WIDTH(reg_width) |
| 1380 | | DWC_CTLL_DST_INC |
| 1381 | | DWC_CTLL_SRC_FIX |
Hans-Christian Egtvedt | d9de451 | 2009-04-01 15:47:02 +0200 | [diff] [blame] | 1382 | | DWC_CTLL_INT_EN); |
Viresh Kumar | 327e697 | 2012-02-01 16:12:26 +0530 | [diff] [blame] | 1383 | |
| 1384 | desc->lli.ctllo |= sconfig->device_fc ? |
| 1385 | DWC_CTLL_FC(DW_DMA_FC_P_P2M) : |
| 1386 | DWC_CTLL_FC(DW_DMA_FC_D_P2M); |
| 1387 | |
Hans-Christian Egtvedt | d9de451 | 2009-04-01 15:47:02 +0200 | [diff] [blame] | 1388 | break; |
| 1389 | default: |
| 1390 | break; |
| 1391 | } |
| 1392 | |
| 1393 | desc->lli.ctlhi = (period_len >> reg_width); |
| 1394 | cdesc->desc[i] = desc; |
| 1395 | |
Andy Shevchenko | f8122a8 | 2013-01-16 15:48:50 +0200 | [diff] [blame] | 1396 | if (last) |
Hans-Christian Egtvedt | d9de451 | 2009-04-01 15:47:02 +0200 | [diff] [blame] | 1397 | last->lli.llp = desc->txd.phys; |
Hans-Christian Egtvedt | d9de451 | 2009-04-01 15:47:02 +0200 | [diff] [blame] | 1398 | |
| 1399 | last = desc; |
| 1400 | } |
| 1401 | |
Andy Shevchenko | 75c6122 | 2013-03-26 16:53:54 +0200 | [diff] [blame] | 1402 | /* Let's make a cyclic list */ |
Hans-Christian Egtvedt | d9de451 | 2009-04-01 15:47:02 +0200 | [diff] [blame] | 1403 | last->lli.llp = cdesc->desc[0]->txd.phys; |
Hans-Christian Egtvedt | d9de451 | 2009-04-01 15:47:02 +0200 | [diff] [blame] | 1404 | |
Andy Shevchenko | 5a87f0e | 2014-01-13 14:04:50 +0200 | [diff] [blame] | 1405 | dev_dbg(chan2dev(&dwc->chan), |
| 1406 | "cyclic prepared buf %pad len %zu period %zu periods %d\n", |
| 1407 | &buf_addr, buf_len, period_len, periods); |
Hans-Christian Egtvedt | d9de451 | 2009-04-01 15:47:02 +0200 | [diff] [blame] | 1408 | |
| 1409 | cdesc->periods = periods; |
| 1410 | dwc->cdesc = cdesc; |
| 1411 | |
| 1412 | return cdesc; |
| 1413 | |
| 1414 | out_err_desc_get: |
| 1415 | while (i--) |
| 1416 | dwc_desc_put(dwc, cdesc->desc[i]); |
| 1417 | out_err_alloc: |
| 1418 | kfree(cdesc); |
| 1419 | out_err: |
| 1420 | clear_bit(DW_DMA_IS_CYCLIC, &dwc->flags); |
| 1421 | return (struct dw_cyclic_desc *)retval; |
| 1422 | } |
| 1423 | EXPORT_SYMBOL(dw_dma_cyclic_prep); |
| 1424 | |
| 1425 | /** |
| 1426 | * dw_dma_cyclic_free - free a prepared cyclic DMA transfer |
| 1427 | * @chan: the DMA channel to free |
| 1428 | */ |
| 1429 | void dw_dma_cyclic_free(struct dma_chan *chan) |
| 1430 | { |
| 1431 | struct dw_dma_chan *dwc = to_dw_dma_chan(chan); |
| 1432 | struct dw_dma *dw = to_dw_dma(dwc->chan.device); |
| 1433 | struct dw_cyclic_desc *cdesc = dwc->cdesc; |
| 1434 | int i; |
Viresh Kumar | 69cea5a | 2011-04-15 16:03:35 +0530 | [diff] [blame] | 1435 | unsigned long flags; |
Hans-Christian Egtvedt | d9de451 | 2009-04-01 15:47:02 +0200 | [diff] [blame] | 1436 | |
Andy Shevchenko | 2e4c364 | 2012-06-19 13:34:05 +0300 | [diff] [blame] | 1437 | dev_dbg(chan2dev(&dwc->chan), "%s\n", __func__); |
Hans-Christian Egtvedt | d9de451 | 2009-04-01 15:47:02 +0200 | [diff] [blame] | 1438 | |
| 1439 | if (!cdesc) |
| 1440 | return; |
| 1441 | |
Viresh Kumar | 69cea5a | 2011-04-15 16:03:35 +0530 | [diff] [blame] | 1442 | spin_lock_irqsave(&dwc->lock, flags); |
Hans-Christian Egtvedt | d9de451 | 2009-04-01 15:47:02 +0200 | [diff] [blame] | 1443 | |
Andy Shevchenko | 3f936207 | 2012-06-19 13:46:32 +0300 | [diff] [blame] | 1444 | dwc_chan_disable(dw, dwc); |
Hans-Christian Egtvedt | d9de451 | 2009-04-01 15:47:02 +0200 | [diff] [blame] | 1445 | |
Hans-Christian Egtvedt | d9de451 | 2009-04-01 15:47:02 +0200 | [diff] [blame] | 1446 | dma_writel(dw, CLEAR.ERROR, dwc->mask); |
| 1447 | dma_writel(dw, CLEAR.XFER, dwc->mask); |
| 1448 | |
Viresh Kumar | 69cea5a | 2011-04-15 16:03:35 +0530 | [diff] [blame] | 1449 | spin_unlock_irqrestore(&dwc->lock, flags); |
Hans-Christian Egtvedt | d9de451 | 2009-04-01 15:47:02 +0200 | [diff] [blame] | 1450 | |
| 1451 | for (i = 0; i < cdesc->periods; i++) |
| 1452 | dwc_desc_put(dwc, cdesc->desc[i]); |
| 1453 | |
| 1454 | kfree(cdesc->desc); |
| 1455 | kfree(cdesc); |
| 1456 | |
| 1457 | clear_bit(DW_DMA_IS_CYCLIC, &dwc->flags); |
| 1458 | } |
| 1459 | EXPORT_SYMBOL(dw_dma_cyclic_free); |
| 1460 | |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 1461 | /*----------------------------------------------------------------------*/ |
| 1462 | |
| 1463 | static void dw_dma_off(struct dw_dma *dw) |
| 1464 | { |
Viresh Kumar | 61e183f | 2011-11-17 16:01:29 +0530 | [diff] [blame] | 1465 | int i; |
| 1466 | |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 1467 | dma_writel(dw, CFG, 0); |
| 1468 | |
| 1469 | channel_clear_bit(dw, MASK.XFER, dw->all_chan_mask); |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 1470 | channel_clear_bit(dw, MASK.SRC_TRAN, dw->all_chan_mask); |
| 1471 | channel_clear_bit(dw, MASK.DST_TRAN, dw->all_chan_mask); |
| 1472 | channel_clear_bit(dw, MASK.ERROR, dw->all_chan_mask); |
| 1473 | |
| 1474 | while (dma_readl(dw, CFG) & DW_CFG_DMA_EN) |
| 1475 | cpu_relax(); |
Viresh Kumar | 61e183f | 2011-11-17 16:01:29 +0530 | [diff] [blame] | 1476 | |
| 1477 | for (i = 0; i < dw->dma.chancnt; i++) |
| 1478 | dw->chan[i].initialized = false; |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 1479 | } |
| 1480 | |
Andy Shevchenko | 9cade1a | 2013-06-05 15:26:45 +0300 | [diff] [blame] | 1481 | int dw_dma_probe(struct dw_dma_chip *chip, struct dw_dma_platform_data *pdata) |
Viresh Kumar | a9ddb57 | 2012-10-16 09:49:17 +0530 | [diff] [blame] | 1482 | { |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 1483 | struct dw_dma *dw; |
Andy Shevchenko | 482c67e | 2012-09-21 15:05:46 +0300 | [diff] [blame] | 1484 | bool autocfg; |
| 1485 | unsigned int dw_params; |
| 1486 | unsigned int nr_channels; |
Andy Shevchenko | 4a63a8b | 2012-09-21 15:05:47 +0300 | [diff] [blame] | 1487 | unsigned int max_blk_size = 0; |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 1488 | int err; |
| 1489 | int i; |
| 1490 | |
Andy Shevchenko | 000871c | 2014-03-05 15:48:12 +0200 | [diff] [blame] | 1491 | dw = devm_kzalloc(chip->dev, sizeof(*dw), GFP_KERNEL); |
| 1492 | if (!dw) |
| 1493 | return -ENOMEM; |
| 1494 | |
| 1495 | dw->regs = chip->regs; |
| 1496 | chip->dw = dw; |
| 1497 | |
Andy Shevchenko | d2f78e9 | 2014-05-08 12:01:48 +0300 | [diff] [blame] | 1498 | dw->clk = devm_clk_get(chip->dev, "hclk"); |
| 1499 | if (IS_ERR(dw->clk)) |
| 1500 | return PTR_ERR(dw->clk); |
Andy Shevchenko | 8be4f52 | 2014-05-08 12:01:49 +0300 | [diff] [blame] | 1501 | err = clk_prepare_enable(dw->clk); |
| 1502 | if (err) |
| 1503 | return err; |
Andy Shevchenko | d2f78e9 | 2014-05-08 12:01:48 +0300 | [diff] [blame] | 1504 | |
Andy Shevchenko | 9cade1a | 2013-06-05 15:26:45 +0300 | [diff] [blame] | 1505 | dw_params = dma_read_byaddr(chip->regs, DW_PARAMS); |
Andy Shevchenko | 482c67e | 2012-09-21 15:05:46 +0300 | [diff] [blame] | 1506 | autocfg = dw_params >> DW_PARAMS_EN & 0x1; |
| 1507 | |
Andy Shevchenko | 9cade1a | 2013-06-05 15:26:45 +0300 | [diff] [blame] | 1508 | dev_dbg(chip->dev, "DW_PARAMS: 0x%08x\n", dw_params); |
Andy Shevchenko | 123de54 | 2013-01-09 10:17:01 +0200 | [diff] [blame] | 1509 | |
| 1510 | if (!pdata && autocfg) { |
Andy Shevchenko | 9cade1a | 2013-06-05 15:26:45 +0300 | [diff] [blame] | 1511 | pdata = devm_kzalloc(chip->dev, sizeof(*pdata), GFP_KERNEL); |
Andy Shevchenko | 8be4f52 | 2014-05-08 12:01:49 +0300 | [diff] [blame] | 1512 | if (!pdata) { |
| 1513 | err = -ENOMEM; |
| 1514 | goto err_pdata; |
| 1515 | } |
Andy Shevchenko | 123de54 | 2013-01-09 10:17:01 +0200 | [diff] [blame] | 1516 | |
| 1517 | /* Fill platform data with the default values */ |
| 1518 | pdata->is_private = true; |
| 1519 | pdata->chan_allocation_order = CHAN_ALLOCATION_ASCENDING; |
| 1520 | pdata->chan_priority = CHAN_PRIORITY_ASCENDING; |
Andy Shevchenko | 8be4f52 | 2014-05-08 12:01:49 +0300 | [diff] [blame] | 1521 | } else if (!pdata || pdata->nr_channels > DW_DMA_MAX_NR_CHANNELS) { |
| 1522 | err = -EINVAL; |
| 1523 | goto err_pdata; |
| 1524 | } |
Andy Shevchenko | 123de54 | 2013-01-09 10:17:01 +0200 | [diff] [blame] | 1525 | |
Andy Shevchenko | 482c67e | 2012-09-21 15:05:46 +0300 | [diff] [blame] | 1526 | if (autocfg) |
| 1527 | nr_channels = (dw_params >> DW_PARAMS_NR_CHAN & 0x7) + 1; |
| 1528 | else |
| 1529 | nr_channels = pdata->nr_channels; |
| 1530 | |
Andy Shevchenko | 000871c | 2014-03-05 15:48:12 +0200 | [diff] [blame] | 1531 | dw->chan = devm_kcalloc(chip->dev, nr_channels, sizeof(*dw->chan), |
| 1532 | GFP_KERNEL); |
Andy Shevchenko | 8be4f52 | 2014-05-08 12:01:49 +0300 | [diff] [blame] | 1533 | if (!dw->chan) { |
| 1534 | err = -ENOMEM; |
| 1535 | goto err_pdata; |
| 1536 | } |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 1537 | |
Andy Shevchenko | 75c6122 | 2013-03-26 16:53:54 +0200 | [diff] [blame] | 1538 | /* Get hardware configuration parameters */ |
Andy Shevchenko | a098200 | 2012-09-21 15:05:48 +0300 | [diff] [blame] | 1539 | if (autocfg) { |
Andy Shevchenko | 4a63a8b | 2012-09-21 15:05:47 +0300 | [diff] [blame] | 1540 | max_blk_size = dma_readl(dw, MAX_BLK_SIZE); |
| 1541 | |
Andy Shevchenko | a098200 | 2012-09-21 15:05:48 +0300 | [diff] [blame] | 1542 | dw->nr_masters = (dw_params >> DW_PARAMS_NR_MASTER & 3) + 1; |
| 1543 | for (i = 0; i < dw->nr_masters; i++) { |
| 1544 | dw->data_width[i] = |
| 1545 | (dw_params >> DW_PARAMS_DATA_WIDTH(i) & 3) + 2; |
| 1546 | } |
| 1547 | } else { |
| 1548 | dw->nr_masters = pdata->nr_masters; |
| 1549 | memcpy(dw->data_width, pdata->data_width, 4); |
| 1550 | } |
| 1551 | |
Andy Shevchenko | 11f932e | 2012-06-19 13:34:06 +0300 | [diff] [blame] | 1552 | /* Calculate all channel mask before DMA setup */ |
Andy Shevchenko | 482c67e | 2012-09-21 15:05:46 +0300 | [diff] [blame] | 1553 | dw->all_chan_mask = (1 << nr_channels) - 1; |
Andy Shevchenko | 11f932e | 2012-06-19 13:34:06 +0300 | [diff] [blame] | 1554 | |
Andy Shevchenko | 75c6122 | 2013-03-26 16:53:54 +0200 | [diff] [blame] | 1555 | /* Force dma off, just in case */ |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 1556 | dw_dma_off(dw); |
| 1557 | |
Andy Shevchenko | 75c6122 | 2013-03-26 16:53:54 +0200 | [diff] [blame] | 1558 | /* Disable BLOCK interrupts as well */ |
Andy Shevchenko | 236b106 | 2012-06-19 13:34:07 +0300 | [diff] [blame] | 1559 | channel_clear_bit(dw, MASK.BLOCK, dw->all_chan_mask); |
| 1560 | |
Andy Shevchenko | 75c6122 | 2013-03-26 16:53:54 +0200 | [diff] [blame] | 1561 | /* Create a pool of consistent memory blocks for hardware descriptors */ |
Andy Shevchenko | 9cade1a | 2013-06-05 15:26:45 +0300 | [diff] [blame] | 1562 | dw->desc_pool = dmam_pool_create("dw_dmac_desc_pool", chip->dev, |
Andy Shevchenko | f8122a8 | 2013-01-16 15:48:50 +0200 | [diff] [blame] | 1563 | sizeof(struct dw_desc), 4, 0); |
| 1564 | if (!dw->desc_pool) { |
Andy Shevchenko | 9cade1a | 2013-06-05 15:26:45 +0300 | [diff] [blame] | 1565 | dev_err(chip->dev, "No memory for descriptors dma pool\n"); |
Andy Shevchenko | 8be4f52 | 2014-05-08 12:01:49 +0300 | [diff] [blame] | 1566 | err = -ENOMEM; |
| 1567 | goto err_pdata; |
Andy Shevchenko | f8122a8 | 2013-01-16 15:48:50 +0200 | [diff] [blame] | 1568 | } |
| 1569 | |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 1570 | tasklet_init(&dw->tasklet, dw_dma_tasklet, (unsigned long)dw); |
| 1571 | |
Andy Shevchenko | 97977f7 | 2014-05-07 10:56:24 +0300 | [diff] [blame] | 1572 | err = request_irq(chip->irq, dw_dma_interrupt, IRQF_SHARED, |
| 1573 | "dw_dmac", dw); |
| 1574 | if (err) |
Andy Shevchenko | 8be4f52 | 2014-05-08 12:01:49 +0300 | [diff] [blame] | 1575 | goto err_pdata; |
Andy Shevchenko | 97977f7 | 2014-05-07 10:56:24 +0300 | [diff] [blame] | 1576 | |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 1577 | INIT_LIST_HEAD(&dw->dma.channels); |
Andy Shevchenko | 482c67e | 2012-09-21 15:05:46 +0300 | [diff] [blame] | 1578 | for (i = 0; i < nr_channels; i++) { |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 1579 | struct dw_dma_chan *dwc = &dw->chan[i]; |
Andy Shevchenko | fed2574 | 2012-09-21 15:05:49 +0300 | [diff] [blame] | 1580 | int r = nr_channels - i - 1; |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 1581 | |
| 1582 | dwc->chan.device = &dw->dma; |
Russell King - ARM Linux | d3ee98cdc | 2012-03-06 22:35:47 +0000 | [diff] [blame] | 1583 | dma_cookie_init(&dwc->chan); |
Viresh Kumar | b0c3130 | 2011-03-03 15:47:21 +0530 | [diff] [blame] | 1584 | if (pdata->chan_allocation_order == CHAN_ALLOCATION_ASCENDING) |
| 1585 | list_add_tail(&dwc->chan.device_node, |
| 1586 | &dw->dma.channels); |
| 1587 | else |
| 1588 | list_add(&dwc->chan.device_node, &dw->dma.channels); |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 1589 | |
Viresh Kumar | 93317e8 | 2011-03-03 15:47:22 +0530 | [diff] [blame] | 1590 | /* 7 is highest priority & 0 is lowest. */ |
| 1591 | if (pdata->chan_priority == CHAN_PRIORITY_ASCENDING) |
Andy Shevchenko | fed2574 | 2012-09-21 15:05:49 +0300 | [diff] [blame] | 1592 | dwc->priority = r; |
Viresh Kumar | 93317e8 | 2011-03-03 15:47:22 +0530 | [diff] [blame] | 1593 | else |
| 1594 | dwc->priority = i; |
| 1595 | |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 1596 | dwc->ch_regs = &__dw_regs(dw)->CHAN[i]; |
| 1597 | spin_lock_init(&dwc->lock); |
| 1598 | dwc->mask = 1 << i; |
| 1599 | |
| 1600 | INIT_LIST_HEAD(&dwc->active_list); |
| 1601 | INIT_LIST_HEAD(&dwc->queue); |
| 1602 | INIT_LIST_HEAD(&dwc->free_list); |
| 1603 | |
| 1604 | channel_clear_bit(dw, CH_EN, dwc->mask); |
Andy Shevchenko | 4a63a8b | 2012-09-21 15:05:47 +0300 | [diff] [blame] | 1605 | |
Andy Shevchenko | 0fdb567 | 2013-01-10 10:53:03 +0200 | [diff] [blame] | 1606 | dwc->direction = DMA_TRANS_NONE; |
Arnd Bergmann | f776076 | 2013-03-26 16:53:57 +0200 | [diff] [blame] | 1607 | dwc->request_line = ~0; |
Andy Shevchenko | a098200 | 2012-09-21 15:05:48 +0300 | [diff] [blame] | 1608 | |
Andy Shevchenko | 75c6122 | 2013-03-26 16:53:54 +0200 | [diff] [blame] | 1609 | /* Hardware configuration */ |
Andy Shevchenko | fed2574 | 2012-09-21 15:05:49 +0300 | [diff] [blame] | 1610 | if (autocfg) { |
| 1611 | unsigned int dwc_params; |
Andy Shevchenko | 9cade1a | 2013-06-05 15:26:45 +0300 | [diff] [blame] | 1612 | void __iomem *addr = chip->regs + r * sizeof(u32); |
Andy Shevchenko | fed2574 | 2012-09-21 15:05:49 +0300 | [diff] [blame] | 1613 | |
Andy Shevchenko | 9cade1a | 2013-06-05 15:26:45 +0300 | [diff] [blame] | 1614 | dwc_params = dma_read_byaddr(addr, DWC_PARAMS); |
Andy Shevchenko | fed2574 | 2012-09-21 15:05:49 +0300 | [diff] [blame] | 1615 | |
Andy Shevchenko | 9cade1a | 2013-06-05 15:26:45 +0300 | [diff] [blame] | 1616 | dev_dbg(chip->dev, "DWC_PARAMS[%d]: 0x%08x\n", i, |
| 1617 | dwc_params); |
Andy Shevchenko | 985a6c7 | 2013-01-18 17:10:59 +0200 | [diff] [blame] | 1618 | |
Andy Shevchenko | 1d566f1 | 2014-01-13 14:04:48 +0200 | [diff] [blame] | 1619 | /* |
| 1620 | * Decode maximum block size for given channel. The |
Andy Shevchenko | 4a63a8b | 2012-09-21 15:05:47 +0300 | [diff] [blame] | 1621 | * stored 4 bit value represents blocks from 0x00 for 3 |
Andy Shevchenko | 1d566f1 | 2014-01-13 14:04:48 +0200 | [diff] [blame] | 1622 | * up to 0x0a for 4095. |
| 1623 | */ |
Andy Shevchenko | 4a63a8b | 2012-09-21 15:05:47 +0300 | [diff] [blame] | 1624 | dwc->block_size = |
| 1625 | (4 << ((max_blk_size >> 4 * i) & 0xf)) - 1; |
Andy Shevchenko | fed2574 | 2012-09-21 15:05:49 +0300 | [diff] [blame] | 1626 | dwc->nollp = |
| 1627 | (dwc_params >> DWC_PARAMS_MBLK_EN & 0x1) == 0; |
| 1628 | } else { |
Andy Shevchenko | 4a63a8b | 2012-09-21 15:05:47 +0300 | [diff] [blame] | 1629 | dwc->block_size = pdata->block_size; |
Andy Shevchenko | fed2574 | 2012-09-21 15:05:49 +0300 | [diff] [blame] | 1630 | |
| 1631 | /* Check if channel supports multi block transfer */ |
| 1632 | channel_writel(dwc, LLP, 0xfffffffc); |
| 1633 | dwc->nollp = |
| 1634 | (channel_readl(dwc, LLP) & 0xfffffffc) == 0; |
| 1635 | channel_writel(dwc, LLP, 0); |
| 1636 | } |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 1637 | } |
| 1638 | |
Andy Shevchenko | 11f932e | 2012-06-19 13:34:06 +0300 | [diff] [blame] | 1639 | /* Clear all interrupts on all channels. */ |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 1640 | dma_writel(dw, CLEAR.XFER, dw->all_chan_mask); |
Andy Shevchenko | 236b106 | 2012-06-19 13:34:07 +0300 | [diff] [blame] | 1641 | dma_writel(dw, CLEAR.BLOCK, dw->all_chan_mask); |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 1642 | dma_writel(dw, CLEAR.SRC_TRAN, dw->all_chan_mask); |
| 1643 | dma_writel(dw, CLEAR.DST_TRAN, dw->all_chan_mask); |
| 1644 | dma_writel(dw, CLEAR.ERROR, dw->all_chan_mask); |
| 1645 | |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 1646 | dma_cap_set(DMA_MEMCPY, dw->dma.cap_mask); |
| 1647 | dma_cap_set(DMA_SLAVE, dw->dma.cap_mask); |
Jamie Iles | 95ea759 | 2011-01-21 14:11:54 +0000 | [diff] [blame] | 1648 | if (pdata->is_private) |
| 1649 | dma_cap_set(DMA_PRIVATE, dw->dma.cap_mask); |
Andy Shevchenko | 9cade1a | 2013-06-05 15:26:45 +0300 | [diff] [blame] | 1650 | dw->dma.dev = chip->dev; |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 1651 | dw->dma.device_alloc_chan_resources = dwc_alloc_chan_resources; |
| 1652 | dw->dma.device_free_chan_resources = dwc_free_chan_resources; |
| 1653 | |
| 1654 | dw->dma.device_prep_dma_memcpy = dwc_prep_dma_memcpy; |
| 1655 | |
| 1656 | dw->dma.device_prep_slave_sg = dwc_prep_slave_sg; |
Linus Walleij | c3635c7 | 2010-03-26 16:44:01 -0700 | [diff] [blame] | 1657 | dw->dma.device_control = dwc_control; |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 1658 | |
Linus Walleij | 0793448 | 2010-03-26 16:50:49 -0700 | [diff] [blame] | 1659 | dw->dma.device_tx_status = dwc_tx_status; |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 1660 | dw->dma.device_issue_pending = dwc_issue_pending; |
| 1661 | |
| 1662 | dma_writel(dw, CFG, DW_CFG_DMA_EN); |
| 1663 | |
Andy Shevchenko | 1222934 | 2014-05-08 12:01:50 +0300 | [diff] [blame] | 1664 | err = dma_async_device_register(&dw->dma); |
| 1665 | if (err) |
| 1666 | goto err_dma_register; |
| 1667 | |
Andy Shevchenko | 9cade1a | 2013-06-05 15:26:45 +0300 | [diff] [blame] | 1668 | dev_info(chip->dev, "DesignWare DMA Controller, %d channels\n", |
Andy Shevchenko | 21d43f4 | 2012-10-18 17:34:09 +0300 | [diff] [blame] | 1669 | nr_channels); |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 1670 | |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 1671 | return 0; |
Andy Shevchenko | 8be4f52 | 2014-05-08 12:01:49 +0300 | [diff] [blame] | 1672 | |
Andy Shevchenko | 1222934 | 2014-05-08 12:01:50 +0300 | [diff] [blame] | 1673 | err_dma_register: |
| 1674 | free_irq(chip->irq, dw); |
Andy Shevchenko | 8be4f52 | 2014-05-08 12:01:49 +0300 | [diff] [blame] | 1675 | err_pdata: |
| 1676 | clk_disable_unprepare(dw->clk); |
| 1677 | return err; |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 1678 | } |
Andy Shevchenko | 9cade1a | 2013-06-05 15:26:45 +0300 | [diff] [blame] | 1679 | EXPORT_SYMBOL_GPL(dw_dma_probe); |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 1680 | |
Andy Shevchenko | 9cade1a | 2013-06-05 15:26:45 +0300 | [diff] [blame] | 1681 | int dw_dma_remove(struct dw_dma_chip *chip) |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 1682 | { |
Andy Shevchenko | 9cade1a | 2013-06-05 15:26:45 +0300 | [diff] [blame] | 1683 | struct dw_dma *dw = chip->dw; |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 1684 | struct dw_dma_chan *dwc, *_dwc; |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 1685 | |
| 1686 | dw_dma_off(dw); |
| 1687 | dma_async_device_unregister(&dw->dma); |
| 1688 | |
Andy Shevchenko | 97977f7 | 2014-05-07 10:56:24 +0300 | [diff] [blame] | 1689 | free_irq(chip->irq, dw); |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 1690 | tasklet_kill(&dw->tasklet); |
| 1691 | |
| 1692 | list_for_each_entry_safe(dwc, _dwc, &dw->dma.channels, |
| 1693 | chan.device_node) { |
| 1694 | list_del(&dwc->chan.device_node); |
| 1695 | channel_clear_bit(dw, CH_EN, dwc->mask); |
| 1696 | } |
| 1697 | |
Andy Shevchenko | 8be4f52 | 2014-05-08 12:01:49 +0300 | [diff] [blame] | 1698 | clk_disable_unprepare(dw->clk); |
| 1699 | |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 1700 | return 0; |
| 1701 | } |
Andy Shevchenko | 9cade1a | 2013-06-05 15:26:45 +0300 | [diff] [blame] | 1702 | EXPORT_SYMBOL_GPL(dw_dma_remove); |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 1703 | |
Andy Shevchenko | 9cade1a | 2013-06-05 15:26:45 +0300 | [diff] [blame] | 1704 | void dw_dma_shutdown(struct dw_dma_chip *chip) |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 1705 | { |
Andy Shevchenko | 9cade1a | 2013-06-05 15:26:45 +0300 | [diff] [blame] | 1706 | struct dw_dma *dw = chip->dw; |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 1707 | |
Andy Shevchenko | 6168d56 | 2012-10-18 17:34:10 +0300 | [diff] [blame] | 1708 | dw_dma_off(dw); |
Viresh Kumar | 3075528 | 2012-04-17 17:10:07 +0530 | [diff] [blame] | 1709 | clk_disable_unprepare(dw->clk); |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 1710 | } |
Andy Shevchenko | 9cade1a | 2013-06-05 15:26:45 +0300 | [diff] [blame] | 1711 | EXPORT_SYMBOL_GPL(dw_dma_shutdown); |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 1712 | |
Andy Shevchenko | 9cade1a | 2013-06-05 15:26:45 +0300 | [diff] [blame] | 1713 | #ifdef CONFIG_PM_SLEEP |
| 1714 | |
| 1715 | int dw_dma_suspend(struct dw_dma_chip *chip) |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 1716 | { |
Andy Shevchenko | 9cade1a | 2013-06-05 15:26:45 +0300 | [diff] [blame] | 1717 | struct dw_dma *dw = chip->dw; |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 1718 | |
Andy Shevchenko | 6168d56 | 2012-10-18 17:34:10 +0300 | [diff] [blame] | 1719 | dw_dma_off(dw); |
Viresh Kumar | 3075528 | 2012-04-17 17:10:07 +0530 | [diff] [blame] | 1720 | clk_disable_unprepare(dw->clk); |
Viresh Kumar | 61e183f | 2011-11-17 16:01:29 +0530 | [diff] [blame] | 1721 | |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 1722 | return 0; |
| 1723 | } |
Andy Shevchenko | 9cade1a | 2013-06-05 15:26:45 +0300 | [diff] [blame] | 1724 | EXPORT_SYMBOL_GPL(dw_dma_suspend); |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 1725 | |
Andy Shevchenko | 9cade1a | 2013-06-05 15:26:45 +0300 | [diff] [blame] | 1726 | int dw_dma_resume(struct dw_dma_chip *chip) |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 1727 | { |
Andy Shevchenko | 9cade1a | 2013-06-05 15:26:45 +0300 | [diff] [blame] | 1728 | struct dw_dma *dw = chip->dw; |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 1729 | |
Viresh Kumar | 3075528 | 2012-04-17 17:10:07 +0530 | [diff] [blame] | 1730 | clk_prepare_enable(dw->clk); |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 1731 | dma_writel(dw, CFG, DW_CFG_DMA_EN); |
Heikki Krogerus | b801479 | 2012-10-18 17:34:08 +0300 | [diff] [blame] | 1732 | |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 1733 | return 0; |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 1734 | } |
Andy Shevchenko | 9cade1a | 2013-06-05 15:26:45 +0300 | [diff] [blame] | 1735 | EXPORT_SYMBOL_GPL(dw_dma_resume); |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 1736 | |
Andy Shevchenko | 9cade1a | 2013-06-05 15:26:45 +0300 | [diff] [blame] | 1737 | #endif /* CONFIG_PM_SLEEP */ |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 1738 | |
| 1739 | MODULE_LICENSE("GPL v2"); |
Andy Shevchenko | 9cade1a | 2013-06-05 15:26:45 +0300 | [diff] [blame] | 1740 | MODULE_DESCRIPTION("Synopsys DesignWare DMA Controller core driver"); |
Jean Delvare | e05503e | 2011-05-18 16:49:24 +0200 | [diff] [blame] | 1741 | MODULE_AUTHOR("Haavard Skinnemoen (Atmel)"); |
Viresh Kumar | 10d8935 | 2012-06-20 12:53:02 -0700 | [diff] [blame] | 1742 | MODULE_AUTHOR("Viresh Kumar <viresh.linux@gmail.com>"); |