blob: 8105e32117f67d8ce60317fb9a4151b305773434 [file] [log] [blame]
Linus Torvalds1da177e2005-04-16 15:20:36 -07001/*
2 * probe.c - PCI detection and setup code
3 */
4
5#include <linux/kernel.h>
6#include <linux/delay.h>
7#include <linux/init.h>
8#include <linux/pci.h>
9#include <linux/slab.h>
10#include <linux/module.h>
11#include <linux/cpumask.h>
Shaohua Li7d715a62008-02-25 09:46:41 +080012#include <linux/pci-aspm.h>
Greg KHbc56b9e2005-04-08 14:53:31 +090013#include "pci.h"
Linus Torvalds1da177e2005-04-16 15:20:36 -070014
15#define CARDBUS_LATENCY_TIMER 176 /* secondary latency timer */
16#define CARDBUS_RESERVE_BUSNR 3
Linus Torvalds1da177e2005-04-16 15:20:36 -070017
18/* Ugh. Need to stop exporting this to modules. */
19LIST_HEAD(pci_root_buses);
20EXPORT_SYMBOL(pci_root_buses);
21
Greg Kroah-Hartman70308922008-02-13 22:30:39 -080022
23static int find_anything(struct device *dev, void *data)
24{
25 return 1;
26}
Linus Torvalds1da177e2005-04-16 15:20:36 -070027
Zhang, Yanmined4aaad2007-07-15 23:39:39 -070028/*
29 * Some device drivers need know if pci is initiated.
30 * Basically, we think pci is not initiated when there
Greg Kroah-Hartman70308922008-02-13 22:30:39 -080031 * is no device to be found on the pci_bus_type.
Zhang, Yanmined4aaad2007-07-15 23:39:39 -070032 */
33int no_pci_devices(void)
34{
Greg Kroah-Hartman70308922008-02-13 22:30:39 -080035 struct device *dev;
36 int no_devices;
Zhang, Yanmined4aaad2007-07-15 23:39:39 -070037
Greg Kroah-Hartman70308922008-02-13 22:30:39 -080038 dev = bus_find_device(&pci_bus_type, NULL, NULL, find_anything);
39 no_devices = (dev == NULL);
40 put_device(dev);
41 return no_devices;
42}
Zhang, Yanmined4aaad2007-07-15 23:39:39 -070043EXPORT_SYMBOL(no_pci_devices);
44
Linus Torvalds1da177e2005-04-16 15:20:36 -070045/*
46 * PCI Bus Class Devices
47 */
Greg Kroah-Hartmanfd7d1ce2007-05-22 22:47:54 -040048static ssize_t pci_bus_show_cpuaffinity(struct device *dev,
Mike Travis39106dc2008-04-08 11:43:03 -070049 int type,
Greg Kroah-Hartmanfd7d1ce2007-05-22 22:47:54 -040050 struct device_attribute *attr,
Alan Cox4327edf2005-09-10 00:25:49 -070051 char *buf)
Linus Torvalds1da177e2005-04-16 15:20:36 -070052{
Linus Torvalds1da177e2005-04-16 15:20:36 -070053 int ret;
Mike Travis588235b2009-01-04 05:18:02 -080054 const struct cpumask *cpumask;
Linus Torvalds1da177e2005-04-16 15:20:36 -070055
Mike Travis588235b2009-01-04 05:18:02 -080056 cpumask = cpumask_of_pcibus(to_pci_bus(dev));
Mike Travis39106dc2008-04-08 11:43:03 -070057 ret = type?
Mike Travis588235b2009-01-04 05:18:02 -080058 cpulist_scnprintf(buf, PAGE_SIZE-2, cpumask) :
59 cpumask_scnprintf(buf, PAGE_SIZE-2, cpumask);
Mike Travis39106dc2008-04-08 11:43:03 -070060 buf[ret++] = '\n';
61 buf[ret] = '\0';
Linus Torvalds1da177e2005-04-16 15:20:36 -070062 return ret;
63}
Mike Travis39106dc2008-04-08 11:43:03 -070064
65static ssize_t inline pci_bus_show_cpumaskaffinity(struct device *dev,
66 struct device_attribute *attr,
67 char *buf)
68{
69 return pci_bus_show_cpuaffinity(dev, 0, attr, buf);
70}
71
72static ssize_t inline pci_bus_show_cpulistaffinity(struct device *dev,
73 struct device_attribute *attr,
74 char *buf)
75{
76 return pci_bus_show_cpuaffinity(dev, 1, attr, buf);
77}
78
79DEVICE_ATTR(cpuaffinity, S_IRUGO, pci_bus_show_cpumaskaffinity, NULL);
80DEVICE_ATTR(cpulistaffinity, S_IRUGO, pci_bus_show_cpulistaffinity, NULL);
Linus Torvalds1da177e2005-04-16 15:20:36 -070081
82/*
83 * PCI Bus Class
84 */
Greg Kroah-Hartmanfd7d1ce2007-05-22 22:47:54 -040085static void release_pcibus_dev(struct device *dev)
Linus Torvalds1da177e2005-04-16 15:20:36 -070086{
Greg Kroah-Hartmanfd7d1ce2007-05-22 22:47:54 -040087 struct pci_bus *pci_bus = to_pci_bus(dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -070088
89 if (pci_bus->bridge)
90 put_device(pci_bus->bridge);
91 kfree(pci_bus);
92}
93
94static struct class pcibus_class = {
95 .name = "pci_bus",
Greg Kroah-Hartmanfd7d1ce2007-05-22 22:47:54 -040096 .dev_release = &release_pcibus_dev,
Linus Torvalds1da177e2005-04-16 15:20:36 -070097};
98
99static int __init pcibus_class_init(void)
100{
101 return class_register(&pcibus_class);
102}
103postcore_initcall(pcibus_class_init);
104
105/*
106 * Translate the low bits of the PCI base
107 * to the resource type
108 */
109static inline unsigned int pci_calc_resource_flags(unsigned int flags)
110{
111 if (flags & PCI_BASE_ADDRESS_SPACE_IO)
112 return IORESOURCE_IO;
113
114 if (flags & PCI_BASE_ADDRESS_MEM_PREFETCH)
115 return IORESOURCE_MEM | IORESOURCE_PREFETCH;
116
117 return IORESOURCE_MEM;
118}
119
Matthew Wilcox6ac665c2008-07-28 13:38:59 -0400120static u64 pci_size(u64 base, u64 maxbase, u64 mask)
Yinghai Lu07eddf32006-11-29 13:53:10 -0800121{
122 u64 size = mask & maxbase; /* Find the significant bits */
123 if (!size)
124 return 0;
125
126 /* Get the lowest of them to find the decode size, and
127 from that the extent. */
128 size = (size & ~(size-1)) - 1;
129
130 /* base == maxbase can be valid only if the BAR has
131 already been programmed with all 1s. */
132 if (base == maxbase && ((base | size) & mask) != mask)
133 return 0;
134
135 return size;
136}
137
Matthew Wilcox6ac665c2008-07-28 13:38:59 -0400138static inline enum pci_bar_type decode_bar(struct resource *res, u32 bar)
Yinghai Lu07eddf32006-11-29 13:53:10 -0800139{
Matthew Wilcox6ac665c2008-07-28 13:38:59 -0400140 if ((bar & PCI_BASE_ADDRESS_SPACE) == PCI_BASE_ADDRESS_SPACE_IO) {
141 res->flags = bar & ~PCI_BASE_ADDRESS_IO_MASK;
142 return pci_bar_io;
143 }
144
145 res->flags = bar & ~PCI_BASE_ADDRESS_MEM_MASK;
146
Peter Chubbe3545972008-10-13 11:49:04 +1100147 if (res->flags & PCI_BASE_ADDRESS_MEM_TYPE_64)
Matthew Wilcox6ac665c2008-07-28 13:38:59 -0400148 return pci_bar_mem64;
149 return pci_bar_mem32;
150}
151
Yu Zhao0b400c72008-11-22 02:40:40 +0800152/**
153 * pci_read_base - read a PCI BAR
154 * @dev: the PCI device
155 * @type: type of the BAR
156 * @res: resource buffer to be filled in
157 * @pos: BAR position in the config space
158 *
159 * Returns 1 if the BAR is 64-bit, or 0 if 32-bit.
Matthew Wilcox6ac665c2008-07-28 13:38:59 -0400160 */
Yu Zhao0b400c72008-11-22 02:40:40 +0800161int __pci_read_base(struct pci_dev *dev, enum pci_bar_type type,
Matthew Wilcox6ac665c2008-07-28 13:38:59 -0400162 struct resource *res, unsigned int pos)
163{
164 u32 l, sz, mask;
165
166 mask = type ? ~PCI_ROM_ADDRESS_ENABLE : ~0;
167
168 res->name = pci_name(dev);
169
170 pci_read_config_dword(dev, pos, &l);
171 pci_write_config_dword(dev, pos, mask);
172 pci_read_config_dword(dev, pos, &sz);
173 pci_write_config_dword(dev, pos, l);
174
175 /*
176 * All bits set in sz means the device isn't working properly.
177 * If the BAR isn't implemented, all bits must be 0. If it's a
178 * memory BAR or a ROM, bit 0 must be clear; if it's an io BAR, bit
179 * 1 must be clear.
180 */
181 if (!sz || sz == 0xffffffff)
182 goto fail;
183
184 /*
185 * I don't know how l can have all bits set. Copied from old code.
186 * Maybe it fixes a bug on some ancient platform.
187 */
188 if (l == 0xffffffff)
189 l = 0;
190
191 if (type == pci_bar_unknown) {
192 type = decode_bar(res, l);
193 res->flags |= pci_calc_resource_flags(l) | IORESOURCE_SIZEALIGN;
194 if (type == pci_bar_io) {
195 l &= PCI_BASE_ADDRESS_IO_MASK;
Yinghai Lu1f82de12009-04-23 20:48:32 -0700196 mask = PCI_BASE_ADDRESS_IO_MASK & IO_SPACE_LIMIT;
Matthew Wilcox6ac665c2008-07-28 13:38:59 -0400197 } else {
198 l &= PCI_BASE_ADDRESS_MEM_MASK;
199 mask = (u32)PCI_BASE_ADDRESS_MEM_MASK;
200 }
201 } else {
202 res->flags |= (l & IORESOURCE_ROM_ENABLE);
203 l &= PCI_ROM_ADDRESS_MASK;
204 mask = (u32)PCI_ROM_ADDRESS_MASK;
205 }
206
207 if (type == pci_bar_mem64) {
208 u64 l64 = l;
209 u64 sz64 = sz;
210 u64 mask64 = mask | (u64)~0 << 32;
211
212 pci_read_config_dword(dev, pos + 4, &l);
213 pci_write_config_dword(dev, pos + 4, ~0);
214 pci_read_config_dword(dev, pos + 4, &sz);
215 pci_write_config_dword(dev, pos + 4, l);
216
217 l64 |= ((u64)l << 32);
218 sz64 |= ((u64)sz << 32);
219
220 sz64 = pci_size(l64, sz64, mask64);
221
222 if (!sz64)
223 goto fail;
224
Matthew Wilcoxcc5499c2008-07-28 13:39:00 -0400225 if ((sizeof(resource_size_t) < 8) && (sz64 > 0x100000000ULL)) {
Matthew Wilcox6ac665c2008-07-28 13:38:59 -0400226 dev_err(&dev->dev, "can't handle 64-bit BAR\n");
227 goto fail;
Matthew Wilcoxcc5499c2008-07-28 13:39:00 -0400228 } else if ((sizeof(resource_size_t) < 8) && l) {
Matthew Wilcox6ac665c2008-07-28 13:38:59 -0400229 /* Address above 32-bit boundary; disable the BAR */
230 pci_write_config_dword(dev, pos, 0);
231 pci_write_config_dword(dev, pos + 4, 0);
232 res->start = 0;
233 res->end = sz64;
234 } else {
235 res->start = l64;
236 res->end = l64 + sz64;
Vincent Legollf393d9b2008-10-12 12:26:12 +0200237 dev_printk(KERN_DEBUG, &dev->dev,
Yinghai Lud0b8cbe2009-08-07 03:53:34 -0700238 "reg %x %s: %pR\n", pos,
239 (res->flags & IORESOURCE_PREFETCH) ?
240 "64bit mmio pref" : "64bit mmio",
241 res);
Matthew Wilcox6ac665c2008-07-28 13:38:59 -0400242 }
Yinghai Lu1f82de12009-04-23 20:48:32 -0700243
244 res->flags |= IORESOURCE_MEM_64;
Matthew Wilcox6ac665c2008-07-28 13:38:59 -0400245 } else {
246 sz = pci_size(l, sz, mask);
247
248 if (!sz)
249 goto fail;
250
251 res->start = l;
252 res->end = l + sz;
Vincent Legollf393d9b2008-10-12 12:26:12 +0200253
254 dev_printk(KERN_DEBUG, &dev->dev, "reg %x %s: %pR\n", pos,
Yinghai Lud0b8cbe2009-08-07 03:53:34 -0700255 (res->flags & IORESOURCE_IO) ? "io port" :
256 ((res->flags & IORESOURCE_PREFETCH) ?
257 "32bit mmio pref" : "32bit mmio"),
Vincent Legollf393d9b2008-10-12 12:26:12 +0200258 res);
Matthew Wilcox6ac665c2008-07-28 13:38:59 -0400259 }
260
261 out:
262 return (type == pci_bar_mem64) ? 1 : 0;
263 fail:
264 res->flags = 0;
265 goto out;
Yinghai Lu07eddf32006-11-29 13:53:10 -0800266}
267
Linus Torvalds1da177e2005-04-16 15:20:36 -0700268static void pci_read_bases(struct pci_dev *dev, unsigned int howmany, int rom)
269{
Matthew Wilcox6ac665c2008-07-28 13:38:59 -0400270 unsigned int pos, reg;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700271
Matthew Wilcox6ac665c2008-07-28 13:38:59 -0400272 for (pos = 0; pos < howmany; pos++) {
273 struct resource *res = &dev->resource[pos];
Linus Torvalds1da177e2005-04-16 15:20:36 -0700274 reg = PCI_BASE_ADDRESS_0 + (pos << 2);
Matthew Wilcox6ac665c2008-07-28 13:38:59 -0400275 pos += __pci_read_base(dev, pci_bar_unknown, res, reg);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700276 }
Matthew Wilcox6ac665c2008-07-28 13:38:59 -0400277
Linus Torvalds1da177e2005-04-16 15:20:36 -0700278 if (rom) {
Matthew Wilcox6ac665c2008-07-28 13:38:59 -0400279 struct resource *res = &dev->resource[PCI_ROM_RESOURCE];
Linus Torvalds1da177e2005-04-16 15:20:36 -0700280 dev->rom_base_reg = rom;
Matthew Wilcox6ac665c2008-07-28 13:38:59 -0400281 res->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH |
282 IORESOURCE_READONLY | IORESOURCE_CACHEABLE |
283 IORESOURCE_SIZEALIGN;
284 __pci_read_base(dev, pci_bar_mem32, res, rom);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700285 }
286}
287
Sam Ravnborg0ab2b572008-02-17 10:45:28 +0100288void __devinit pci_read_bridge_bases(struct pci_bus *child)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700289{
290 struct pci_dev *dev = child->self;
291 u8 io_base_lo, io_limit_lo;
292 u16 mem_base_lo, mem_limit_lo;
293 unsigned long base, limit;
294 struct resource *res;
295 int i;
296
Kenji Kaneshige9fc39252009-05-26 16:06:48 +0900297 if (pci_is_root_bus(child)) /* It's a host bus, nothing to read */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700298 return;
299
300 if (dev->transparent) {
Bjorn Helgaas80ccba12008-06-13 10:52:11 -0600301 dev_info(&dev->dev, "transparent bridge\n");
Ivan Kokshaysky90b54922005-06-07 04:07:02 +0400302 for(i = 3; i < PCI_BUS_NUM_RESOURCES; i++)
303 child->resource[i] = child->parent->resource[i - 3];
Linus Torvalds1da177e2005-04-16 15:20:36 -0700304 }
305
Linus Torvalds1da177e2005-04-16 15:20:36 -0700306 res = child->resource[0];
307 pci_read_config_byte(dev, PCI_IO_BASE, &io_base_lo);
308 pci_read_config_byte(dev, PCI_IO_LIMIT, &io_limit_lo);
309 base = (io_base_lo & PCI_IO_RANGE_MASK) << 8;
310 limit = (io_limit_lo & PCI_IO_RANGE_MASK) << 8;
311
312 if ((io_base_lo & PCI_IO_RANGE_TYPE_MASK) == PCI_IO_RANGE_TYPE_32) {
313 u16 io_base_hi, io_limit_hi;
314 pci_read_config_word(dev, PCI_IO_BASE_UPPER16, &io_base_hi);
315 pci_read_config_word(dev, PCI_IO_LIMIT_UPPER16, &io_limit_hi);
316 base |= (io_base_hi << 16);
317 limit |= (io_limit_hi << 16);
318 }
319
320 if (base <= limit) {
321 res->flags = (io_base_lo & PCI_IO_RANGE_TYPE_MASK) | IORESOURCE_IO;
Daniel Yeisley9d265122005-12-05 07:06:43 -0500322 if (!res->start)
323 res->start = base;
324 if (!res->end)
325 res->end = limit + 0xfff;
Vincent Legollf393d9b2008-10-12 12:26:12 +0200326 dev_printk(KERN_DEBUG, &dev->dev, "bridge io port: %pR\n", res);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700327 }
328
329 res = child->resource[1];
330 pci_read_config_word(dev, PCI_MEMORY_BASE, &mem_base_lo);
331 pci_read_config_word(dev, PCI_MEMORY_LIMIT, &mem_limit_lo);
332 base = (mem_base_lo & PCI_MEMORY_RANGE_MASK) << 16;
333 limit = (mem_limit_lo & PCI_MEMORY_RANGE_MASK) << 16;
334 if (base <= limit) {
335 res->flags = (mem_base_lo & PCI_MEMORY_RANGE_TYPE_MASK) | IORESOURCE_MEM;
336 res->start = base;
337 res->end = limit + 0xfffff;
Vincent Legollf393d9b2008-10-12 12:26:12 +0200338 dev_printk(KERN_DEBUG, &dev->dev, "bridge 32bit mmio: %pR\n",
339 res);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700340 }
341
342 res = child->resource[2];
343 pci_read_config_word(dev, PCI_PREF_MEMORY_BASE, &mem_base_lo);
344 pci_read_config_word(dev, PCI_PREF_MEMORY_LIMIT, &mem_limit_lo);
345 base = (mem_base_lo & PCI_PREF_RANGE_MASK) << 16;
346 limit = (mem_limit_lo & PCI_PREF_RANGE_MASK) << 16;
347
348 if ((mem_base_lo & PCI_PREF_RANGE_TYPE_MASK) == PCI_PREF_RANGE_TYPE_64) {
349 u32 mem_base_hi, mem_limit_hi;
350 pci_read_config_dword(dev, PCI_PREF_BASE_UPPER32, &mem_base_hi);
351 pci_read_config_dword(dev, PCI_PREF_LIMIT_UPPER32, &mem_limit_hi);
352
353 /*
354 * Some bridges set the base > limit by default, and some
355 * (broken) BIOSes do not initialize them. If we find
356 * this, just assume they are not being used.
357 */
358 if (mem_base_hi <= mem_limit_hi) {
359#if BITS_PER_LONG == 64
360 base |= ((long) mem_base_hi) << 32;
361 limit |= ((long) mem_limit_hi) << 32;
362#else
363 if (mem_base_hi || mem_limit_hi) {
Bjorn Helgaas80ccba12008-06-13 10:52:11 -0600364 dev_err(&dev->dev, "can't handle 64-bit "
365 "address space for bridge\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -0700366 return;
367 }
368#endif
369 }
370 }
371 if (base <= limit) {
Yinghai Lu1f82de12009-04-23 20:48:32 -0700372 res->flags = (mem_base_lo & PCI_PREF_RANGE_TYPE_MASK) |
373 IORESOURCE_MEM | IORESOURCE_PREFETCH;
374 if (res->flags & PCI_PREF_RANGE_TYPE_64)
375 res->flags |= IORESOURCE_MEM_64;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700376 res->start = base;
377 res->end = limit + 0xfffff;
Vincent Legollf393d9b2008-10-12 12:26:12 +0200378 dev_printk(KERN_DEBUG, &dev->dev, "bridge %sbit mmio pref: %pR\n",
379 (res->flags & PCI_PREF_RANGE_TYPE_64) ? "64" : "32",
380 res);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700381 }
382}
383
Sam Ravnborg96bde062007-03-26 21:53:30 -0800384static struct pci_bus * pci_alloc_bus(void)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700385{
386 struct pci_bus *b;
387
Eric Sesterhennf5afe802006-02-28 15:34:49 +0100388 b = kzalloc(sizeof(*b), GFP_KERNEL);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700389 if (b) {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700390 INIT_LIST_HEAD(&b->node);
391 INIT_LIST_HEAD(&b->children);
392 INIT_LIST_HEAD(&b->devices);
Alex Chiangf46753c2008-06-10 15:28:50 -0600393 INIT_LIST_HEAD(&b->slots);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700394 }
395 return b;
396}
397
Adrian Bunkcbd4e052008-04-18 13:53:55 -0700398static struct pci_bus *pci_alloc_child_bus(struct pci_bus *parent,
399 struct pci_dev *bridge, int busnr)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700400{
401 struct pci_bus *child;
402 int i;
403
404 /*
405 * Allocate a new bus, and inherit stuff from the parent..
406 */
407 child = pci_alloc_bus();
408 if (!child)
409 return NULL;
410
Linus Torvalds1da177e2005-04-16 15:20:36 -0700411 child->parent = parent;
412 child->ops = parent->ops;
413 child->sysdata = parent->sysdata;
Michael S. Tsirkin6e325a62006-02-14 18:52:22 +0200414 child->bus_flags = parent->bus_flags;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700415
Greg Kroah-Hartmanfd7d1ce2007-05-22 22:47:54 -0400416 /* initialize some portions of the bus device, but don't register it
417 * now as the parent is not properly set up yet. This device will get
418 * registered later in pci_bus_add_devices()
419 */
420 child->dev.class = &pcibus_class;
Kay Sievers1a927132008-10-30 02:17:49 +0100421 dev_set_name(&child->dev, "%04x:%02x", pci_domain_nr(child), busnr);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700422
423 /*
424 * Set up the primary, secondary and subordinate
425 * bus numbers.
426 */
427 child->number = child->secondary = busnr;
428 child->primary = parent->secondary;
429 child->subordinate = 0xff;
430
Yu Zhao3789fa82008-11-22 02:41:07 +0800431 if (!bridge)
432 return child;
433
434 child->self = bridge;
435 child->bridge = get_device(&bridge->dev);
436
Linus Torvalds1da177e2005-04-16 15:20:36 -0700437 /* Set up default resource pointers and names.. */
Yu Zhaofde09c62008-11-22 02:39:32 +0800438 for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; i++) {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700439 child->resource[i] = &bridge->resource[PCI_BRIDGE_RESOURCES+i];
440 child->resource[i]->name = child->name;
441 }
442 bridge->subordinate = child;
443
444 return child;
445}
446
Sam Ravnborg451124a2008-02-02 22:33:43 +0100447struct pci_bus *__ref pci_add_new_bus(struct pci_bus *parent, struct pci_dev *dev, int busnr)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700448{
449 struct pci_bus *child;
450
451 child = pci_alloc_child_bus(parent, dev, busnr);
Rajesh Shahe4ea9bb2005-04-28 00:25:48 -0700452 if (child) {
Zhang Yanmind71374d2006-06-02 12:35:43 +0800453 down_write(&pci_bus_sem);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700454 list_add_tail(&child->node, &parent->children);
Zhang Yanmind71374d2006-06-02 12:35:43 +0800455 up_write(&pci_bus_sem);
Rajesh Shahe4ea9bb2005-04-28 00:25:48 -0700456 }
Linus Torvalds1da177e2005-04-16 15:20:36 -0700457 return child;
458}
459
Sam Ravnborg96bde062007-03-26 21:53:30 -0800460static void pci_fixup_parent_subordinate_busnr(struct pci_bus *child, int max)
Greg Kroah-Hartman26f674a2005-06-02 15:41:48 -0700461{
462 struct pci_bus *parent = child->parent;
Ivan Kokshaysky12f44f42005-09-22 21:06:31 -0700463
464 /* Attempts to fix that up are really dangerous unless
465 we're going to re-assign all bus numbers. */
466 if (!pcibios_assign_all_busses())
467 return;
468
Greg Kroah-Hartman26f674a2005-06-02 15:41:48 -0700469 while (parent->parent && parent->subordinate < max) {
470 parent->subordinate = max;
471 pci_write_config_byte(parent->self, PCI_SUBORDINATE_BUS, max);
472 parent = parent->parent;
473 }
474}
475
Linus Torvalds1da177e2005-04-16 15:20:36 -0700476/*
477 * If it's a bridge, configure it and scan the bus behind it.
478 * For CardBus bridges, we don't scan behind as the devices will
479 * be handled by the bridge driver itself.
480 *
481 * We need to process bridges in two passes -- first we scan those
482 * already configured by the BIOS and after we are done with all of
483 * them, we proceed to assigning numbers to the remaining buses in
484 * order to avoid overlaps between old and new bus numbers.
485 */
Sam Ravnborg0ab2b572008-02-17 10:45:28 +0100486int __devinit pci_scan_bridge(struct pci_bus *bus, struct pci_dev *dev, int max, int pass)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700487{
488 struct pci_bus *child;
489 int is_cardbus = (dev->hdr_type == PCI_HEADER_TYPE_CARDBUS);
Dominik Brodowski49887942005-12-08 16:53:12 +0100490 u32 buses, i, j = 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700491 u16 bctl;
Benjamin Herrenschmidta1c19892008-10-21 10:06:29 +1100492 int broken = 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700493
494 pci_read_config_dword(dev, PCI_PRIMARY_BUS, &buses);
495
Bjorn Helgaas80ccba12008-06-13 10:52:11 -0600496 dev_dbg(&dev->dev, "scanning behind bridge, config %06x, pass %d\n",
497 buses & 0xffffff, pass);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700498
Benjamin Herrenschmidta1c19892008-10-21 10:06:29 +1100499 /* Check if setup is sensible at all */
500 if (!pass &&
501 ((buses & 0xff) != bus->number || ((buses >> 8) & 0xff) <= bus->number)) {
502 dev_dbg(&dev->dev, "bus configuration invalid, reconfiguring\n");
503 broken = 1;
504 }
505
Linus Torvalds1da177e2005-04-16 15:20:36 -0700506 /* Disable MasterAbortMode during probing to avoid reporting
507 of bus errors (in some architectures) */
508 pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &bctl);
509 pci_write_config_word(dev, PCI_BRIDGE_CONTROL,
510 bctl & ~PCI_BRIDGE_CTL_MASTER_ABORT);
511
Benjamin Herrenschmidta1c19892008-10-21 10:06:29 +1100512 if ((buses & 0xffff00) && !pcibios_assign_all_busses() && !is_cardbus && !broken) {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700513 unsigned int cmax, busnr;
514 /*
515 * Bus already configured by firmware, process it in the first
516 * pass and just note the configuration.
517 */
518 if (pass)
Ralf Baechlebbe8f9a2006-02-14 16:23:57 +0000519 goto out;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700520 busnr = (buses >> 8) & 0xFF;
521
522 /*
523 * If we already got to this bus through a different bridge,
Alex Chiang74710de2009-03-20 14:56:10 -0600524 * don't re-add it. This can happen with the i450NX chipset.
525 *
526 * However, we continue to descend down the hierarchy and
527 * scan remaining child buses.
Linus Torvalds1da177e2005-04-16 15:20:36 -0700528 */
Alex Chiang74710de2009-03-20 14:56:10 -0600529 child = pci_find_bus(pci_domain_nr(bus), busnr);
530 if (!child) {
531 child = pci_add_new_bus(bus, dev, busnr);
532 if (!child)
533 goto out;
534 child->primary = buses & 0xFF;
535 child->subordinate = (buses >> 16) & 0xFF;
536 child->bridge_ctl = bctl;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700537 }
538
Linus Torvalds1da177e2005-04-16 15:20:36 -0700539 cmax = pci_scan_child_bus(child);
540 if (cmax > max)
541 max = cmax;
542 if (child->subordinate > max)
543 max = child->subordinate;
544 } else {
545 /*
546 * We need to assign a number to this bus which we always
547 * do in the second pass.
548 */
Ivan Kokshaysky12f44f42005-09-22 21:06:31 -0700549 if (!pass) {
Benjamin Herrenschmidta1c19892008-10-21 10:06:29 +1100550 if (pcibios_assign_all_busses() || broken)
Ivan Kokshaysky12f44f42005-09-22 21:06:31 -0700551 /* Temporarily disable forwarding of the
552 configuration cycles on all bridges in
553 this bus segment to avoid possible
554 conflicts in the second pass between two
555 bridges programmed with overlapping
556 bus ranges. */
557 pci_write_config_dword(dev, PCI_PRIMARY_BUS,
558 buses & ~0xffffff);
Ralf Baechlebbe8f9a2006-02-14 16:23:57 +0000559 goto out;
Ivan Kokshaysky12f44f42005-09-22 21:06:31 -0700560 }
Linus Torvalds1da177e2005-04-16 15:20:36 -0700561
562 /* Clear errors */
563 pci_write_config_word(dev, PCI_STATUS, 0xffff);
564
Rajesh Shahcc574502005-04-28 00:25:47 -0700565 /* Prevent assigning a bus number that already exists.
566 * This can happen when a bridge is hot-plugged */
567 if (pci_find_bus(pci_domain_nr(bus), max+1))
Ralf Baechlebbe8f9a2006-02-14 16:23:57 +0000568 goto out;
Rajesh Shah6ef6f0e2005-04-28 00:25:49 -0700569 child = pci_add_new_bus(bus, dev, ++max);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700570 buses = (buses & 0xff000000)
571 | ((unsigned int)(child->primary) << 0)
572 | ((unsigned int)(child->secondary) << 8)
573 | ((unsigned int)(child->subordinate) << 16);
574
575 /*
576 * yenta.c forces a secondary latency timer of 176.
577 * Copy that behaviour here.
578 */
579 if (is_cardbus) {
580 buses &= ~0xff000000;
581 buses |= CARDBUS_LATENCY_TIMER << 24;
582 }
583
584 /*
585 * We need to blast all three values with a single write.
586 */
587 pci_write_config_dword(dev, PCI_PRIMARY_BUS, buses);
588
589 if (!is_cardbus) {
Gary Hade11949252007-10-08 16:24:16 -0700590 child->bridge_ctl = bctl;
Greg Kroah-Hartman26f674a2005-06-02 15:41:48 -0700591 /*
592 * Adjust subordinate busnr in parent buses.
593 * We do this before scanning for children because
594 * some devices may not be detected if the bios
595 * was lazy.
596 */
597 pci_fixup_parent_subordinate_busnr(child, max);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700598 /* Now we can scan all subordinate buses... */
599 max = pci_scan_child_bus(child);
Kristen Accardie3ac86d2006-01-17 16:57:01 -0800600 /*
601 * now fix it up again since we have found
602 * the real value of max.
603 */
604 pci_fixup_parent_subordinate_busnr(child, max);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700605 } else {
606 /*
607 * For CardBus bridges, we leave 4 bus numbers
608 * as cards with a PCI-to-PCI bridge can be
609 * inserted later.
610 */
Dominik Brodowski49887942005-12-08 16:53:12 +0100611 for (i=0; i<CARDBUS_RESERVE_BUSNR; i++) {
612 struct pci_bus *parent = bus;
Rajesh Shahcc574502005-04-28 00:25:47 -0700613 if (pci_find_bus(pci_domain_nr(bus),
614 max+i+1))
615 break;
Dominik Brodowski49887942005-12-08 16:53:12 +0100616 while (parent->parent) {
617 if ((!pcibios_assign_all_busses()) &&
618 (parent->subordinate > max) &&
619 (parent->subordinate <= max+i)) {
620 j = 1;
621 }
622 parent = parent->parent;
623 }
624 if (j) {
625 /*
626 * Often, there are two cardbus bridges
627 * -- try to leave one valid bus number
628 * for each one.
629 */
630 i /= 2;
631 break;
632 }
633 }
Rajesh Shahcc574502005-04-28 00:25:47 -0700634 max += i;
Greg Kroah-Hartman26f674a2005-06-02 15:41:48 -0700635 pci_fixup_parent_subordinate_busnr(child, max);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700636 }
637 /*
638 * Set the subordinate bus number to its real value.
639 */
640 child->subordinate = max;
641 pci_write_config_byte(dev, PCI_SUBORDINATE_BUS, max);
642 }
643
Gary Hadecb3576f2008-02-08 14:00:52 -0800644 sprintf(child->name,
645 (is_cardbus ? "PCI CardBus %04x:%02x" : "PCI Bus %04x:%02x"),
646 pci_domain_nr(bus), child->number);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700647
Bernhard Kaindld55bef52007-07-30 20:35:13 +0200648 /* Has only triggered on CardBus, fixup is in yenta_socket */
Dominik Brodowski49887942005-12-08 16:53:12 +0100649 while (bus->parent) {
650 if ((child->subordinate > bus->subordinate) ||
651 (child->number > bus->subordinate) ||
652 (child->number < bus->number) ||
653 (child->subordinate < bus->number)) {
Joe Perchesa6f29a92007-11-19 17:48:29 -0800654 pr_debug("PCI: Bus #%02x (-#%02x) is %s "
Bernhard Kaindld55bef52007-07-30 20:35:13 +0200655 "hidden behind%s bridge #%02x (-#%02x)\n",
656 child->number, child->subordinate,
657 (bus->number > child->subordinate &&
658 bus->subordinate < child->number) ?
Joe Perchesa6f29a92007-11-19 17:48:29 -0800659 "wholly" : "partially",
660 bus->self->transparent ? " transparent" : "",
Bernhard Kaindld55bef52007-07-30 20:35:13 +0200661 bus->number, bus->subordinate);
Dominik Brodowski49887942005-12-08 16:53:12 +0100662 }
663 bus = bus->parent;
664 }
665
Ralf Baechlebbe8f9a2006-02-14 16:23:57 +0000666out:
667 pci_write_config_word(dev, PCI_BRIDGE_CONTROL, bctl);
668
Linus Torvalds1da177e2005-04-16 15:20:36 -0700669 return max;
670}
671
672/*
673 * Read interrupt line and base address registers.
674 * The architecture-dependent code can tweak these, of course.
675 */
676static void pci_read_irq(struct pci_dev *dev)
677{
678 unsigned char irq;
679
680 pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &irq);
Kristen Accardiffeff782005-11-02 16:24:32 -0800681 dev->pin = irq;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700682 if (irq)
683 pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq);
684 dev->irq = irq;
685}
686
Yu Zhao480b93b2009-03-20 11:25:14 +0800687static void set_pcie_port_type(struct pci_dev *pdev)
688{
689 int pos;
690 u16 reg16;
691
692 pos = pci_find_capability(pdev, PCI_CAP_ID_EXP);
693 if (!pos)
694 return;
695 pdev->is_pcie = 1;
696 pci_read_config_word(pdev, pos + PCI_EXP_FLAGS, &reg16);
697 pdev->pcie_type = (reg16 & PCI_EXP_FLAGS_TYPE) >> 4;
698}
699
Eric W. Biederman28760482009-09-09 14:09:24 -0700700static void set_pcie_hotplug_bridge(struct pci_dev *pdev)
701{
702 int pos;
703 u16 reg16;
704 u32 reg32;
705
706 pos = pci_find_capability(pdev, PCI_CAP_ID_EXP);
707 if (!pos)
708 return;
709 pci_read_config_word(pdev, pos + PCI_EXP_FLAGS, &reg16);
710 if (!(reg16 & PCI_EXP_FLAGS_SLOT))
711 return;
712 pci_read_config_dword(pdev, pos + PCI_EXP_SLTCAP, &reg32);
713 if (reg32 & PCI_EXP_SLTCAP_HPC)
714 pdev->is_hotplug_bridge = 1;
715}
716
Bartlomiej Zolnierkiewicz01abc2a2007-04-23 23:19:36 +0200717#define LEGACY_IO_RESOURCE (IORESOURCE_IO | IORESOURCE_PCI_FIXED)
Randy Dunlap76e6a1d2006-12-29 16:47:29 -0800718
Linus Torvalds1da177e2005-04-16 15:20:36 -0700719/**
720 * pci_setup_device - fill in class and map information of a device
721 * @dev: the device structure to fill
722 *
723 * Initialize the device structure with information about the device's
724 * vendor,class,memory and IO-space addresses,IRQ lines etc.
725 * Called at initialisation of the PCI subsystem and by CardBus services.
Yu Zhao480b93b2009-03-20 11:25:14 +0800726 * Returns 0 on success and negative if unknown type of device (not normal,
727 * bridge or CardBus).
Linus Torvalds1da177e2005-04-16 15:20:36 -0700728 */
Yu Zhao480b93b2009-03-20 11:25:14 +0800729int pci_setup_device(struct pci_dev *dev)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700730{
731 u32 class;
Yu Zhao480b93b2009-03-20 11:25:14 +0800732 u8 hdr_type;
733 struct pci_slot *slot;
734
735 if (pci_read_config_byte(dev, PCI_HEADER_TYPE, &hdr_type))
736 return -EIO;
737
738 dev->sysdata = dev->bus->sysdata;
739 dev->dev.parent = dev->bus->bridge;
740 dev->dev.bus = &pci_bus_type;
741 dev->hdr_type = hdr_type & 0x7f;
742 dev->multifunction = !!(hdr_type & 0x80);
Yu Zhao480b93b2009-03-20 11:25:14 +0800743 dev->error_state = pci_channel_io_normal;
744 set_pcie_port_type(dev);
745
746 list_for_each_entry(slot, &dev->bus->slots, list)
747 if (PCI_SLOT(dev->devfn) == slot->number)
748 dev->slot = slot;
749
750 /* Assume 32-bit PCI; let 64-bit PCI cards (which are far rarer)
751 set this higher, assuming the system even supports it. */
752 dev->dma_mask = 0xffffffff;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700753
Greg Kroah-Hartmaneebfcfb2008-07-02 13:24:49 -0700754 dev_set_name(&dev->dev, "%04x:%02x:%02x.%d", pci_domain_nr(dev->bus),
755 dev->bus->number, PCI_SLOT(dev->devfn),
756 PCI_FUNC(dev->devfn));
Linus Torvalds1da177e2005-04-16 15:20:36 -0700757
758 pci_read_config_dword(dev, PCI_CLASS_REVISION, &class);
Auke Kokb8a3a522007-06-08 15:46:30 -0700759 dev->revision = class & 0xff;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700760 class >>= 8; /* upper 3 bytes */
761 dev->class = class;
762 class >>= 8;
763
Bjorn Helgaas34a2e152008-08-25 15:45:20 -0600764 dev_dbg(&dev->dev, "found [%04x:%04x] class %06x header type %02x\n",
Linus Torvalds1da177e2005-04-16 15:20:36 -0700765 dev->vendor, dev->device, class, dev->hdr_type);
766
Yu Zhao853346e2009-03-21 22:05:11 +0800767 /* need to have dev->class ready */
768 dev->cfg_size = pci_cfg_space_size(dev);
769
Linus Torvalds1da177e2005-04-16 15:20:36 -0700770 /* "Unknown power state" */
Daniel Ritz3fe9d192005-08-17 15:32:19 -0700771 dev->current_state = PCI_UNKNOWN;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700772
773 /* Early fixups, before probing the BARs */
774 pci_fixup_device(pci_fixup_early, dev);
Yu Zhaof79b1b12009-05-28 00:25:05 +0800775 /* device class may be changed after fixup */
776 class = dev->class >> 8;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700777
778 switch (dev->hdr_type) { /* header type */
779 case PCI_HEADER_TYPE_NORMAL: /* standard header */
780 if (class == PCI_CLASS_BRIDGE_PCI)
781 goto bad;
782 pci_read_irq(dev);
783 pci_read_bases(dev, 6, PCI_ROM_ADDRESS);
784 pci_read_config_word(dev, PCI_SUBSYSTEM_VENDOR_ID, &dev->subsystem_vendor);
785 pci_read_config_word(dev, PCI_SUBSYSTEM_ID, &dev->subsystem_device);
Alan Cox368c73d2006-10-04 00:41:26 +0100786
787 /*
788 * Do the ugly legacy mode stuff here rather than broken chip
789 * quirk code. Legacy mode ATA controllers have fixed
790 * addresses. These are not always echoed in BAR0-3, and
791 * BAR0-3 in a few cases contain junk!
792 */
793 if (class == PCI_CLASS_STORAGE_IDE) {
794 u8 progif;
795 pci_read_config_byte(dev, PCI_CLASS_PROG, &progif);
796 if ((progif & 1) == 0) {
Linus Torvaldsaf1bff42007-12-10 07:40:54 -0800797 dev->resource[0].start = 0x1F0;
798 dev->resource[0].end = 0x1F7;
799 dev->resource[0].flags = LEGACY_IO_RESOURCE;
800 dev->resource[1].start = 0x3F6;
801 dev->resource[1].end = 0x3F6;
802 dev->resource[1].flags = LEGACY_IO_RESOURCE;
Alan Cox368c73d2006-10-04 00:41:26 +0100803 }
804 if ((progif & 4) == 0) {
Linus Torvaldsaf1bff42007-12-10 07:40:54 -0800805 dev->resource[2].start = 0x170;
806 dev->resource[2].end = 0x177;
807 dev->resource[2].flags = LEGACY_IO_RESOURCE;
808 dev->resource[3].start = 0x376;
809 dev->resource[3].end = 0x376;
810 dev->resource[3].flags = LEGACY_IO_RESOURCE;
Alan Cox368c73d2006-10-04 00:41:26 +0100811 }
812 }
Linus Torvalds1da177e2005-04-16 15:20:36 -0700813 break;
814
815 case PCI_HEADER_TYPE_BRIDGE: /* bridge header */
816 if (class != PCI_CLASS_BRIDGE_PCI)
817 goto bad;
818 /* The PCI-to-PCI bridge spec requires that subtractive
819 decoding (i.e. transparent) bridge must have programming
820 interface code of 0x01. */
Kristen Accardi3efd2732005-11-02 16:55:49 -0800821 pci_read_irq(dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700822 dev->transparent = ((dev->class & 0xff) == 1);
823 pci_read_bases(dev, 2, PCI_ROM_ADDRESS1);
Eric W. Biederman28760482009-09-09 14:09:24 -0700824 set_pcie_hotplug_bridge(dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700825 break;
826
827 case PCI_HEADER_TYPE_CARDBUS: /* CardBus bridge header */
828 if (class != PCI_CLASS_BRIDGE_CARDBUS)
829 goto bad;
830 pci_read_irq(dev);
831 pci_read_bases(dev, 1, 0);
832 pci_read_config_word(dev, PCI_CB_SUBSYSTEM_VENDOR_ID, &dev->subsystem_vendor);
833 pci_read_config_word(dev, PCI_CB_SUBSYSTEM_ID, &dev->subsystem_device);
834 break;
835
836 default: /* unknown header */
Bjorn Helgaas80ccba12008-06-13 10:52:11 -0600837 dev_err(&dev->dev, "unknown header type %02x, "
838 "ignoring device\n", dev->hdr_type);
Yu Zhao480b93b2009-03-20 11:25:14 +0800839 return -EIO;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700840
841 bad:
Bjorn Helgaas80ccba12008-06-13 10:52:11 -0600842 dev_err(&dev->dev, "ignoring class %02x (doesn't match header "
843 "type %02x)\n", class, dev->hdr_type);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700844 dev->class = PCI_CLASS_NOT_DEFINED;
845 }
846
847 /* We found a fine healthy device, go go go... */
848 return 0;
849}
850
Zhao, Yu201de562008-10-13 19:49:55 +0800851static void pci_release_capabilities(struct pci_dev *dev)
852{
853 pci_vpd_release(dev);
Yu Zhaod1b054d2009-03-20 11:25:11 +0800854 pci_iov_release(dev);
Zhao, Yu201de562008-10-13 19:49:55 +0800855}
856
Linus Torvalds1da177e2005-04-16 15:20:36 -0700857/**
858 * pci_release_dev - free a pci device structure when all users of it are finished.
859 * @dev: device that's been disconnected
860 *
861 * Will be called only by the device core when all users of this pci device are
862 * done.
863 */
864static void pci_release_dev(struct device *dev)
865{
866 struct pci_dev *pci_dev;
867
868 pci_dev = to_pci_dev(dev);
Zhao, Yu201de562008-10-13 19:49:55 +0800869 pci_release_capabilities(pci_dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700870 kfree(pci_dev);
871}
872
873/**
874 * pci_cfg_space_size - get the configuration space size of the PCI device.
Randy Dunlap8f7020d2005-10-23 11:57:38 -0700875 * @dev: PCI device
Linus Torvalds1da177e2005-04-16 15:20:36 -0700876 *
877 * Regular PCI devices have 256 bytes, but PCI-X 2 and PCI Express devices
878 * have 4096 bytes. Even if the device is capable, that doesn't mean we can
879 * access it. Maybe we don't have a way to generate extended config space
880 * accesses, or the device is behind a reverse Express bridge. So we try
881 * reading the dword at 0x100 which must either be 0 or a valid extended
882 * capability header.
883 */
Yinghai Lu70b9f7d2008-04-28 16:27:23 -0700884int pci_cfg_space_size_ext(struct pci_dev *dev)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700885{
Linus Torvalds1da177e2005-04-16 15:20:36 -0700886 u32 status;
Zhao, Yu557848c2008-10-13 19:18:07 +0800887 int pos = PCI_CFG_SPACE_SIZE;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700888
Zhao, Yu557848c2008-10-13 19:18:07 +0800889 if (pci_read_config_dword(dev, pos, &status) != PCIBIOS_SUCCESSFUL)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700890 goto fail;
891 if (status == 0xffffffff)
892 goto fail;
893
894 return PCI_CFG_SPACE_EXP_SIZE;
895
896 fail:
897 return PCI_CFG_SPACE_SIZE;
898}
899
Yinghai Lu57741a72008-02-15 01:32:50 -0800900int pci_cfg_space_size(struct pci_dev *dev)
901{
Yinghai Lu70b9f7d2008-04-28 16:27:23 -0700902 int pos;
903 u32 status;
Yinghai Ludfadd9ed2009-03-08 21:35:37 -0700904 u16 class;
905
906 class = dev->class >> 8;
907 if (class == PCI_CLASS_BRIDGE_HOST)
908 return pci_cfg_space_size_ext(dev);
Yinghai Lu70b9f7d2008-04-28 16:27:23 -0700909
910 pos = pci_find_capability(dev, PCI_CAP_ID_EXP);
911 if (!pos) {
912 pos = pci_find_capability(dev, PCI_CAP_ID_PCIX);
913 if (!pos)
914 goto fail;
915
916 pci_read_config_dword(dev, pos + PCI_X_STATUS, &status);
917 if (!(status & (PCI_X_STATUS_266MHZ | PCI_X_STATUS_533MHZ)))
918 goto fail;
919 }
920
921 return pci_cfg_space_size_ext(dev);
922
923 fail:
924 return PCI_CFG_SPACE_SIZE;
Yinghai Lu57741a72008-02-15 01:32:50 -0800925}
926
Linus Torvalds1da177e2005-04-16 15:20:36 -0700927static void pci_release_bus_bridge_dev(struct device *dev)
928{
929 kfree(dev);
930}
931
Michael Ellerman65891212007-04-05 17:19:08 +1000932struct pci_dev *alloc_pci_dev(void)
933{
934 struct pci_dev *dev;
935
936 dev = kzalloc(sizeof(struct pci_dev), GFP_KERNEL);
937 if (!dev)
938 return NULL;
939
Michael Ellerman65891212007-04-05 17:19:08 +1000940 INIT_LIST_HEAD(&dev->bus_list);
941
942 return dev;
943}
944EXPORT_SYMBOL(alloc_pci_dev);
945
Linus Torvalds1da177e2005-04-16 15:20:36 -0700946/*
947 * Read the config data for a PCI device, sanity-check it
948 * and fill in the dev structure...
949 */
Adrian Bunk7f7b5de2008-04-18 13:53:55 -0700950static struct pci_dev *pci_scan_device(struct pci_bus *bus, int devfn)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700951{
952 struct pci_dev *dev;
953 u32 l;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700954 int delay = 1;
955
956 if (pci_bus_read_config_dword(bus, devfn, PCI_VENDOR_ID, &l))
957 return NULL;
958
959 /* some broken boards return 0 or ~0 if a slot is empty: */
960 if (l == 0xffffffff || l == 0x00000000 ||
961 l == 0x0000ffff || l == 0xffff0000)
962 return NULL;
963
964 /* Configuration request Retry Status */
965 while (l == 0xffff0001) {
966 msleep(delay);
967 delay *= 2;
968 if (pci_bus_read_config_dword(bus, devfn, PCI_VENDOR_ID, &l))
969 return NULL;
970 /* Card hasn't responded in 60 seconds? Must be stuck. */
971 if (delay > 60 * 1000) {
Bjorn Helgaas80ccba12008-06-13 10:52:11 -0600972 printk(KERN_WARNING "pci %04x:%02x:%02x.%d: not "
Linus Torvalds1da177e2005-04-16 15:20:36 -0700973 "responding\n", pci_domain_nr(bus),
974 bus->number, PCI_SLOT(devfn),
975 PCI_FUNC(devfn));
976 return NULL;
977 }
978 }
979
Michael Ellermanbab41e92007-04-05 17:19:09 +1000980 dev = alloc_pci_dev();
Linus Torvalds1da177e2005-04-16 15:20:36 -0700981 if (!dev)
982 return NULL;
983
Linus Torvalds1da177e2005-04-16 15:20:36 -0700984 dev->bus = bus;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700985 dev->devfn = devfn;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700986 dev->vendor = l & 0xffff;
987 dev->device = (l >> 16) & 0xffff;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700988
Yu Zhao480b93b2009-03-20 11:25:14 +0800989 if (pci_setup_device(dev)) {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700990 kfree(dev);
991 return NULL;
992 }
Paul Mackerrascdb9b9f2005-09-06 09:31:03 +1000993
994 return dev;
995}
996
Zhao, Yu201de562008-10-13 19:49:55 +0800997static void pci_init_capabilities(struct pci_dev *dev)
998{
999 /* MSI/MSI-X list */
1000 pci_msi_init_pci_dev(dev);
1001
Rafael J. Wysocki63f48982008-12-07 22:02:58 +01001002 /* Buffers for saving PCIe and PCI-X capabilities */
1003 pci_allocate_cap_save_buffers(dev);
1004
Zhao, Yu201de562008-10-13 19:49:55 +08001005 /* Power Management */
1006 pci_pm_init(dev);
Jesse Barneseb9c39d2008-12-17 12:10:05 -08001007 platform_pci_wakeup_init(dev);
Zhao, Yu201de562008-10-13 19:49:55 +08001008
1009 /* Vital Product Data */
1010 pci_vpd_pci22_init(dev);
Yu Zhao58c3a722008-10-14 14:02:53 +08001011
1012 /* Alternative Routing-ID Forwarding */
1013 pci_enable_ari(dev);
Yu Zhaod1b054d2009-03-20 11:25:11 +08001014
1015 /* Single Root I/O Virtualization */
1016 pci_iov_init(dev);
Zhao, Yu201de562008-10-13 19:49:55 +08001017}
1018
Sam Ravnborg96bde062007-03-26 21:53:30 -08001019void pci_device_add(struct pci_dev *dev, struct pci_bus *bus)
Paul Mackerrascdb9b9f2005-09-06 09:31:03 +10001020{
Linus Torvalds1da177e2005-04-16 15:20:36 -07001021 device_initialize(&dev->dev);
1022 dev->dev.release = pci_release_dev;
1023 pci_dev_get(dev);
1024
Linus Torvalds1da177e2005-04-16 15:20:36 -07001025 dev->dev.dma_mask = &dev->dma_mask;
FUJITA Tomonori4d57cdf2008-02-04 22:27:55 -08001026 dev->dev.dma_parms = &dev->dma_parms;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001027 dev->dev.coherent_dma_mask = 0xffffffffull;
1028
FUJITA Tomonori4d57cdf2008-02-04 22:27:55 -08001029 pci_set_dma_max_seg_size(dev, 65536);
FUJITA Tomonori59fc67d2008-02-04 22:28:14 -08001030 pci_set_dma_seg_boundary(dev, 0xffffffff);
FUJITA Tomonori4d57cdf2008-02-04 22:27:55 -08001031
Linus Torvalds1da177e2005-04-16 15:20:36 -07001032 /* Fix up broken headers */
1033 pci_fixup_device(pci_fixup_header, dev);
1034
Rafael J. Wysocki4b77b0a2009-09-09 23:49:59 +02001035 /* Clear the state_saved flag. */
1036 dev->state_saved = false;
1037
Zhao, Yu201de562008-10-13 19:49:55 +08001038 /* Initialize various capabilities */
1039 pci_init_capabilities(dev);
Rafael J. Wysockieb9d0fe2008-07-07 03:34:48 +02001040
Linus Torvalds1da177e2005-04-16 15:20:36 -07001041 /*
1042 * Add the device to our list of discovered devices
1043 * and the bus list for fixup functions, etc.
1044 */
Zhang Yanmind71374d2006-06-02 12:35:43 +08001045 down_write(&pci_bus_sem);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001046 list_add_tail(&dev->bus_list, &bus->devices);
Zhang Yanmind71374d2006-06-02 12:35:43 +08001047 up_write(&pci_bus_sem);
Paul Mackerrascdb9b9f2005-09-06 09:31:03 +10001048}
1049
Sam Ravnborg451124a2008-02-02 22:33:43 +01001050struct pci_dev *__ref pci_scan_single_device(struct pci_bus *bus, int devfn)
Paul Mackerrascdb9b9f2005-09-06 09:31:03 +10001051{
1052 struct pci_dev *dev;
1053
Trent Piepho90bdb312009-03-20 14:56:00 -06001054 dev = pci_get_slot(bus, devfn);
1055 if (dev) {
1056 pci_dev_put(dev);
1057 return dev;
1058 }
1059
Paul Mackerrascdb9b9f2005-09-06 09:31:03 +10001060 dev = pci_scan_device(bus, devfn);
1061 if (!dev)
1062 return NULL;
1063
1064 pci_device_add(dev, bus);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001065
1066 return dev;
1067}
Adrian Bunkb73e9682007-11-21 15:07:11 -08001068EXPORT_SYMBOL(pci_scan_single_device);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001069
1070/**
1071 * pci_scan_slot - scan a PCI slot on a bus for devices.
1072 * @bus: PCI bus to scan
1073 * @devfn: slot number to scan (must have zero function.)
1074 *
1075 * Scan a PCI slot on the specified PCI bus for devices, adding
1076 * discovered devices to the @bus->devices list. New devices
Greg Kroah-Hartman8a1bc902008-02-14 14:56:56 -08001077 * will not have is_added set.
Trent Piepho1b69dfc2009-03-20 14:56:05 -06001078 *
1079 * Returns the number of new devices found.
Linus Torvalds1da177e2005-04-16 15:20:36 -07001080 */
Sam Ravnborg96bde062007-03-26 21:53:30 -08001081int pci_scan_slot(struct pci_bus *bus, int devfn)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001082{
Trent Piepho1b69dfc2009-03-20 14:56:05 -06001083 int fn, nr = 0;
1084 struct pci_dev *dev;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001085
Trent Piepho1b69dfc2009-03-20 14:56:05 -06001086 dev = pci_scan_single_device(bus, devfn);
1087 if (dev && !dev->is_added) /* new device? */
1088 nr++;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001089
Alex Chianga7db5042009-06-22 08:08:07 -06001090 if (dev && dev->multifunction) {
Trent Piepho1b69dfc2009-03-20 14:56:05 -06001091 for (fn = 1; fn < 8; fn++) {
1092 dev = pci_scan_single_device(bus, devfn + fn);
1093 if (dev) {
1094 if (!dev->is_added)
1095 nr++;
1096 dev->multifunction = 1;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001097 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07001098 }
1099 }
Shaohua Li7d715a62008-02-25 09:46:41 +08001100
Shaohua Li149e1632008-07-23 10:32:31 +08001101 /* only one slot has pcie device */
1102 if (bus->self && nr)
Shaohua Li7d715a62008-02-25 09:46:41 +08001103 pcie_aspm_init_link_state(bus->self);
1104
Linus Torvalds1da177e2005-04-16 15:20:36 -07001105 return nr;
1106}
1107
Sam Ravnborg0ab2b572008-02-17 10:45:28 +01001108unsigned int __devinit pci_scan_child_bus(struct pci_bus *bus)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001109{
1110 unsigned int devfn, pass, max = bus->secondary;
1111 struct pci_dev *dev;
1112
1113 pr_debug("PCI: Scanning bus %04x:%02x\n", pci_domain_nr(bus), bus->number);
1114
1115 /* Go find them, Rover! */
1116 for (devfn = 0; devfn < 0x100; devfn += 8)
1117 pci_scan_slot(bus, devfn);
1118
Yu Zhaoa28724b2009-03-20 11:25:13 +08001119 /* Reserve buses for SR-IOV capability. */
1120 max += pci_iov_bus_range(bus);
1121
Linus Torvalds1da177e2005-04-16 15:20:36 -07001122 /*
1123 * After performing arch-dependent fixup of the bus, look behind
1124 * all PCI-to-PCI bridges on this bus.
1125 */
Alex Chiang74710de2009-03-20 14:56:10 -06001126 if (!bus->is_added) {
1127 pr_debug("PCI: Fixups for bus %04x:%02x\n",
1128 pci_domain_nr(bus), bus->number);
1129 pcibios_fixup_bus(bus);
1130 if (pci_is_root_bus(bus))
1131 bus->is_added = 1;
1132 }
1133
Linus Torvalds1da177e2005-04-16 15:20:36 -07001134 for (pass=0; pass < 2; pass++)
1135 list_for_each_entry(dev, &bus->devices, bus_list) {
1136 if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE ||
1137 dev->hdr_type == PCI_HEADER_TYPE_CARDBUS)
1138 max = pci_scan_bridge(bus, dev, max, pass);
1139 }
1140
1141 /*
1142 * We've scanned the bus and so we know all about what's on
1143 * the other side of any bridges that may be on this bus plus
1144 * any devices.
1145 *
1146 * Return how far we've got finding sub-buses.
1147 */
1148 pr_debug("PCI: Bus scan for %04x:%02x returning with max=%02x\n",
1149 pci_domain_nr(bus), bus->number, max);
1150 return max;
1151}
1152
Sam Ravnborg96bde062007-03-26 21:53:30 -08001153struct pci_bus * pci_create_bus(struct device *parent,
Paul Mackerrascdb9b9f2005-09-06 09:31:03 +10001154 int bus, struct pci_ops *ops, void *sysdata)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001155{
1156 int error;
1157 struct pci_bus *b;
1158 struct device *dev;
1159
1160 b = pci_alloc_bus();
1161 if (!b)
1162 return NULL;
1163
Geert Uytterhoeven6a3b3e22009-03-15 20:14:37 +01001164 dev = kzalloc(sizeof(*dev), GFP_KERNEL);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001165 if (!dev){
1166 kfree(b);
1167 return NULL;
1168 }
1169
1170 b->sysdata = sysdata;
1171 b->ops = ops;
1172
1173 if (pci_find_bus(pci_domain_nr(b), bus)) {
1174 /* If we already got to this bus through a different bridge, ignore it */
1175 pr_debug("PCI: Bus %04x:%02x already known\n", pci_domain_nr(b), bus);
1176 goto err_out;
1177 }
Zhang Yanmind71374d2006-06-02 12:35:43 +08001178
1179 down_write(&pci_bus_sem);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001180 list_add_tail(&b->node, &pci_root_buses);
Zhang Yanmind71374d2006-06-02 12:35:43 +08001181 up_write(&pci_bus_sem);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001182
Linus Torvalds1da177e2005-04-16 15:20:36 -07001183 dev->parent = parent;
1184 dev->release = pci_release_bus_bridge_dev;
Kay Sievers1a927132008-10-30 02:17:49 +01001185 dev_set_name(dev, "pci%04x:%02x", pci_domain_nr(b), bus);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001186 error = device_register(dev);
1187 if (error)
1188 goto dev_reg_err;
1189 b->bridge = get_device(dev);
1190
Yinghai Lu0d358f22008-02-19 03:20:41 -08001191 if (!parent)
1192 set_dev_node(b->bridge, pcibus_to_node(b));
1193
Greg Kroah-Hartmanfd7d1ce2007-05-22 22:47:54 -04001194 b->dev.class = &pcibus_class;
1195 b->dev.parent = b->bridge;
Kay Sievers1a927132008-10-30 02:17:49 +01001196 dev_set_name(&b->dev, "%04x:%02x", pci_domain_nr(b), bus);
Greg Kroah-Hartmanfd7d1ce2007-05-22 22:47:54 -04001197 error = device_register(&b->dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001198 if (error)
1199 goto class_dev_reg_err;
Greg Kroah-Hartmanfd7d1ce2007-05-22 22:47:54 -04001200 error = device_create_file(&b->dev, &dev_attr_cpuaffinity);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001201 if (error)
Greg Kroah-Hartmanfd7d1ce2007-05-22 22:47:54 -04001202 goto dev_create_file_err;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001203
1204 /* Create legacy_io and legacy_mem files for this bus */
1205 pci_create_legacy_files(b);
1206
Linus Torvalds1da177e2005-04-16 15:20:36 -07001207 b->number = b->secondary = bus;
1208 b->resource[0] = &ioport_resource;
1209 b->resource[1] = &iomem_resource;
1210
Linus Torvalds1da177e2005-04-16 15:20:36 -07001211 return b;
1212
Greg Kroah-Hartmanfd7d1ce2007-05-22 22:47:54 -04001213dev_create_file_err:
1214 device_unregister(&b->dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001215class_dev_reg_err:
1216 device_unregister(dev);
1217dev_reg_err:
Zhang Yanmind71374d2006-06-02 12:35:43 +08001218 down_write(&pci_bus_sem);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001219 list_del(&b->node);
Zhang Yanmind71374d2006-06-02 12:35:43 +08001220 up_write(&pci_bus_sem);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001221err_out:
1222 kfree(dev);
1223 kfree(b);
1224 return NULL;
1225}
Paul Mackerrascdb9b9f2005-09-06 09:31:03 +10001226
Sam Ravnborg0ab2b572008-02-17 10:45:28 +01001227struct pci_bus * __devinit pci_scan_bus_parented(struct device *parent,
Paul Mackerrascdb9b9f2005-09-06 09:31:03 +10001228 int bus, struct pci_ops *ops, void *sysdata)
1229{
1230 struct pci_bus *b;
1231
1232 b = pci_create_bus(parent, bus, ops, sysdata);
1233 if (b)
1234 b->subordinate = pci_scan_child_bus(b);
1235 return b;
1236}
Linus Torvalds1da177e2005-04-16 15:20:36 -07001237EXPORT_SYMBOL(pci_scan_bus_parented);
1238
1239#ifdef CONFIG_HOTPLUG
Alex Chiang3ed4fd92009-03-20 14:56:25 -06001240/**
1241 * pci_rescan_bus - scan a PCI bus for devices.
1242 * @bus: PCI bus to scan
1243 *
1244 * Scan a PCI bus and child buses for new devices, adds them,
1245 * and enables them.
1246 *
1247 * Returns the max number of subordinate bus discovered.
1248 */
Alex Chiang5446a6b2009-04-01 18:24:12 -06001249unsigned int __ref pci_rescan_bus(struct pci_bus *bus)
Alex Chiang3ed4fd92009-03-20 14:56:25 -06001250{
1251 unsigned int max;
1252 struct pci_dev *dev;
1253
1254 max = pci_scan_child_bus(bus);
1255
Alex Chiang705b1aa2009-03-20 14:56:31 -06001256 down_read(&pci_bus_sem);
Alex Chiang3ed4fd92009-03-20 14:56:25 -06001257 list_for_each_entry(dev, &bus->devices, bus_list)
1258 if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE ||
1259 dev->hdr_type == PCI_HEADER_TYPE_CARDBUS)
1260 if (dev->subordinate)
1261 pci_bus_size_bridges(dev->subordinate);
Alex Chiang705b1aa2009-03-20 14:56:31 -06001262 up_read(&pci_bus_sem);
Alex Chiang3ed4fd92009-03-20 14:56:25 -06001263
1264 pci_bus_assign_resources(bus);
1265 pci_enable_bridges(bus);
1266 pci_bus_add_devices(bus);
1267
1268 return max;
1269}
1270EXPORT_SYMBOL_GPL(pci_rescan_bus);
1271
Linus Torvalds1da177e2005-04-16 15:20:36 -07001272EXPORT_SYMBOL(pci_add_new_bus);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001273EXPORT_SYMBOL(pci_scan_slot);
1274EXPORT_SYMBOL(pci_scan_bridge);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001275EXPORT_SYMBOL_GPL(pci_scan_child_bus);
1276#endif
Matt Domsch6b4b78f2006-09-29 15:23:23 -05001277
Greg Kroah-Hartman99178b02008-08-26 11:00:57 -05001278static int __init pci_sort_bf_cmp(const struct device *d_a, const struct device *d_b)
Matt Domsch6b4b78f2006-09-29 15:23:23 -05001279{
Greg Kroah-Hartman99178b02008-08-26 11:00:57 -05001280 const struct pci_dev *a = to_pci_dev(d_a);
1281 const struct pci_dev *b = to_pci_dev(d_b);
1282
Matt Domsch6b4b78f2006-09-29 15:23:23 -05001283 if (pci_domain_nr(a->bus) < pci_domain_nr(b->bus)) return -1;
1284 else if (pci_domain_nr(a->bus) > pci_domain_nr(b->bus)) return 1;
1285
1286 if (a->bus->number < b->bus->number) return -1;
1287 else if (a->bus->number > b->bus->number) return 1;
1288
1289 if (a->devfn < b->devfn) return -1;
1290 else if (a->devfn > b->devfn) return 1;
1291
1292 return 0;
1293}
1294
Greg Kroah-Hartman5ff580c2008-02-14 14:56:56 -08001295void __init pci_sort_breadthfirst(void)
Matt Domsch6b4b78f2006-09-29 15:23:23 -05001296{
Greg Kroah-Hartman99178b02008-08-26 11:00:57 -05001297 bus_sort_breadthfirst(&pci_bus_type, &pci_sort_bf_cmp);
Matt Domsch6b4b78f2006-09-29 15:23:23 -05001298}