PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 1 | /******************************************************************************* |
| 2 | |
| 3 | Intel 10 Gigabit PCI Express Linux driver |
Shannon Nelson | 8c47eaa | 2010-01-13 01:49:34 +0000 | [diff] [blame] | 4 | Copyright(c) 1999 - 2010 Intel Corporation. |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 5 | |
| 6 | This program is free software; you can redistribute it and/or modify it |
| 7 | under the terms and conditions of the GNU General Public License, |
| 8 | version 2, as published by the Free Software Foundation. |
| 9 | |
| 10 | This program is distributed in the hope it will be useful, but WITHOUT |
| 11 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
| 12 | FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for |
| 13 | more details. |
| 14 | |
| 15 | You should have received a copy of the GNU General Public License along with |
| 16 | this program; if not, write to the Free Software Foundation, Inc., |
| 17 | 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. |
| 18 | |
| 19 | The full GNU General Public License is included in this distribution in |
| 20 | the file called "COPYING". |
| 21 | |
| 22 | Contact Information: |
| 23 | e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> |
| 24 | Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 |
| 25 | |
| 26 | *******************************************************************************/ |
| 27 | |
| 28 | #include <linux/pci.h> |
| 29 | #include <linux/delay.h> |
| 30 | #include <linux/sched.h> |
| 31 | |
| 32 | #include "ixgbe.h" |
| 33 | #include "ixgbe_phy.h" |
Greg Rose | 096a58f | 2010-01-09 02:26:26 +0000 | [diff] [blame] | 34 | #include "ixgbe_mbx.h" |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 35 | |
| 36 | #define IXGBE_82599_MAX_TX_QUEUES 128 |
| 37 | #define IXGBE_82599_MAX_RX_QUEUES 128 |
| 38 | #define IXGBE_82599_RAR_ENTRIES 128 |
| 39 | #define IXGBE_82599_MC_TBL_SIZE 128 |
| 40 | #define IXGBE_82599_VFT_TBL_SIZE 128 |
| 41 | |
Emil Tantilov | 5d5b7c3 | 2010-10-12 22:20:59 +0000 | [diff] [blame] | 42 | static void ixgbe_disable_tx_laser_multispeed_fiber(struct ixgbe_hw *hw); |
| 43 | static void ixgbe_enable_tx_laser_multispeed_fiber(struct ixgbe_hw *hw); |
| 44 | static void ixgbe_flap_tx_laser_multispeed_fiber(struct ixgbe_hw *hw); |
| 45 | static s32 ixgbe_setup_mac_link_multispeed_fiber(struct ixgbe_hw *hw, |
| 46 | ixgbe_link_speed speed, |
| 47 | bool autoneg, |
| 48 | bool autoneg_wait_to_complete); |
Don Skidmore | cd7e1f0 | 2009-10-08 15:36:22 +0000 | [diff] [blame] | 49 | static s32 ixgbe_setup_mac_link_smartspeed(struct ixgbe_hw *hw, |
| 50 | ixgbe_link_speed speed, |
| 51 | bool autoneg, |
| 52 | bool autoneg_wait_to_complete); |
Emil Tantilov | 5d5b7c3 | 2010-10-12 22:20:59 +0000 | [diff] [blame] | 53 | static s32 ixgbe_start_mac_link_82599(struct ixgbe_hw *hw, |
| 54 | bool autoneg_wait_to_complete); |
| 55 | static s32 ixgbe_setup_mac_link_82599(struct ixgbe_hw *hw, |
Mallikarjuna R Chilakala | 8620a10 | 2009-09-01 13:49:35 +0000 | [diff] [blame] | 56 | ixgbe_link_speed speed, |
| 57 | bool autoneg, |
| 58 | bool autoneg_wait_to_complete); |
Mallikarjuna R Chilakala | 8620a10 | 2009-09-01 13:49:35 +0000 | [diff] [blame] | 59 | static s32 ixgbe_setup_copper_link_82599(struct ixgbe_hw *hw, |
| 60 | ixgbe_link_speed speed, |
| 61 | bool autoneg, |
| 62 | bool autoneg_wait_to_complete); |
Peter P Waskiewicz Jr | 794caeb | 2009-06-04 16:02:24 +0000 | [diff] [blame] | 63 | static s32 ixgbe_verify_fw_version_82599(struct ixgbe_hw *hw); |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 64 | |
Don Skidmore | 7b25cdb | 2009-08-25 04:47:32 +0000 | [diff] [blame] | 65 | static void ixgbe_init_mac_link_ops_82599(struct ixgbe_hw *hw) |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 66 | { |
| 67 | struct ixgbe_mac_info *mac = &hw->mac; |
Don Skidmore | c6ecf39 | 2010-12-03 03:31:51 +0000 | [diff] [blame] | 68 | |
| 69 | /* enable the laser control functions for SFP+ fiber */ |
| 70 | if (mac->ops.get_media_type(hw) == ixgbe_media_type_fiber) { |
Peter Waskiewicz | 61fac74 | 2010-04-27 00:38:15 +0000 | [diff] [blame] | 71 | mac->ops.disable_tx_laser = |
| 72 | &ixgbe_disable_tx_laser_multispeed_fiber; |
| 73 | mac->ops.enable_tx_laser = |
| 74 | &ixgbe_enable_tx_laser_multispeed_fiber; |
Mallikarjuna R Chilakala | 1097cd1 | 2010-03-18 14:34:52 +0000 | [diff] [blame] | 75 | mac->ops.flap_tx_laser = &ixgbe_flap_tx_laser_multispeed_fiber; |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 76 | } else { |
Peter Waskiewicz | 61fac74 | 2010-04-27 00:38:15 +0000 | [diff] [blame] | 77 | mac->ops.disable_tx_laser = NULL; |
| 78 | mac->ops.enable_tx_laser = NULL; |
Mallikarjuna R Chilakala | 1097cd1 | 2010-03-18 14:34:52 +0000 | [diff] [blame] | 79 | mac->ops.flap_tx_laser = NULL; |
Don Skidmore | c6ecf39 | 2010-12-03 03:31:51 +0000 | [diff] [blame] | 80 | } |
| 81 | |
| 82 | if (hw->phy.multispeed_fiber) { |
| 83 | /* Set up dual speed SFP+ support */ |
| 84 | mac->ops.setup_link = &ixgbe_setup_mac_link_multispeed_fiber; |
| 85 | } else { |
Don Skidmore | cd7e1f0 | 2009-10-08 15:36:22 +0000 | [diff] [blame] | 86 | if ((mac->ops.get_media_type(hw) == |
| 87 | ixgbe_media_type_backplane) && |
| 88 | (hw->phy.smart_speed == ixgbe_smart_speed_auto || |
| 89 | hw->phy.smart_speed == ixgbe_smart_speed_on)) |
| 90 | mac->ops.setup_link = &ixgbe_setup_mac_link_smartspeed; |
| 91 | else |
| 92 | mac->ops.setup_link = &ixgbe_setup_mac_link_82599; |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 93 | } |
| 94 | } |
| 95 | |
Don Skidmore | 7b25cdb | 2009-08-25 04:47:32 +0000 | [diff] [blame] | 96 | static s32 ixgbe_setup_sfp_modules_82599(struct ixgbe_hw *hw) |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 97 | { |
| 98 | s32 ret_val = 0; |
Don Skidmore | a7f5a5f | 2010-12-03 13:23:30 +0000 | [diff] [blame] | 99 | u32 reg_anlp1 = 0; |
| 100 | u32 i = 0; |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 101 | u16 list_offset, data_offset, data_value; |
| 102 | |
| 103 | if (hw->phy.sfp_type != ixgbe_sfp_type_unknown) { |
| 104 | ixgbe_init_mac_link_ops_82599(hw); |
PJ Waskiewicz | 553b449 | 2009-04-09 22:28:15 +0000 | [diff] [blame] | 105 | |
| 106 | hw->phy.ops.reset = NULL; |
| 107 | |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 108 | ret_val = ixgbe_get_sfp_init_sequence_offsets(hw, &list_offset, |
| 109 | &data_offset); |
| 110 | |
| 111 | if (ret_val != 0) |
| 112 | goto setup_sfp_out; |
| 113 | |
Peter P Waskiewicz Jr | aa5aec8 | 2009-05-19 09:18:34 +0000 | [diff] [blame] | 114 | /* PHY config will finish before releasing the semaphore */ |
| 115 | ret_val = ixgbe_acquire_swfw_sync(hw, IXGBE_GSSR_MAC_CSR_SM); |
| 116 | if (ret_val != 0) { |
| 117 | ret_val = IXGBE_ERR_SWFW_SYNC; |
| 118 | goto setup_sfp_out; |
| 119 | } |
| 120 | |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 121 | hw->eeprom.ops.read(hw, ++data_offset, &data_value); |
| 122 | while (data_value != 0xffff) { |
| 123 | IXGBE_WRITE_REG(hw, IXGBE_CORECTL, data_value); |
| 124 | IXGBE_WRITE_FLUSH(hw); |
| 125 | hw->eeprom.ops.read(hw, ++data_offset, &data_value); |
| 126 | } |
Peter P Waskiewicz Jr | aa5aec8 | 2009-05-19 09:18:34 +0000 | [diff] [blame] | 127 | |
| 128 | /* Release the semaphore */ |
| 129 | ixgbe_release_swfw_sync(hw, IXGBE_GSSR_MAC_CSR_SM); |
| 130 | /* Delay obtaining semaphore again to allow FW access */ |
| 131 | msleep(hw->eeprom.semaphore_delay); |
Don Skidmore | a7f5a5f | 2010-12-03 13:23:30 +0000 | [diff] [blame] | 132 | |
| 133 | /* Now restart DSP by setting Restart_AN and clearing LMS */ |
| 134 | IXGBE_WRITE_REG(hw, IXGBE_AUTOC, ((IXGBE_READ_REG(hw, |
| 135 | IXGBE_AUTOC) & ~IXGBE_AUTOC_LMS_MASK) | |
| 136 | IXGBE_AUTOC_AN_RESTART)); |
| 137 | |
| 138 | /* Wait for AN to leave state 0 */ |
| 139 | for (i = 0; i < 10; i++) { |
| 140 | msleep(4); |
| 141 | reg_anlp1 = IXGBE_READ_REG(hw, IXGBE_ANLP1); |
| 142 | if (reg_anlp1 & IXGBE_ANLP1_AN_STATE_MASK) |
| 143 | break; |
| 144 | } |
| 145 | if (!(reg_anlp1 & IXGBE_ANLP1_AN_STATE_MASK)) { |
| 146 | hw_dbg(hw, "sfp module setup not complete\n"); |
| 147 | ret_val = IXGBE_ERR_SFP_SETUP_NOT_COMPLETE; |
| 148 | goto setup_sfp_out; |
| 149 | } |
| 150 | |
| 151 | /* Restart DSP by setting Restart_AN and return to SFI mode */ |
| 152 | IXGBE_WRITE_REG(hw, IXGBE_AUTOC, (IXGBE_READ_REG(hw, |
| 153 | IXGBE_AUTOC) | IXGBE_AUTOC_LMS_10G_SERIAL | |
| 154 | IXGBE_AUTOC_AN_RESTART)); |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 155 | } |
| 156 | |
| 157 | setup_sfp_out: |
| 158 | return ret_val; |
| 159 | } |
| 160 | |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 161 | static s32 ixgbe_get_invariants_82599(struct ixgbe_hw *hw) |
| 162 | { |
| 163 | struct ixgbe_mac_info *mac = &hw->mac; |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 164 | |
| 165 | ixgbe_init_mac_link_ops_82599(hw); |
| 166 | |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 167 | mac->mcft_size = IXGBE_82599_MC_TBL_SIZE; |
| 168 | mac->vft_size = IXGBE_82599_VFT_TBL_SIZE; |
| 169 | mac->num_rar_entries = IXGBE_82599_RAR_ENTRIES; |
| 170 | mac->max_rx_queues = IXGBE_82599_MAX_RX_QUEUES; |
| 171 | mac->max_tx_queues = IXGBE_82599_MAX_TX_QUEUES; |
Mallikarjuna R Chilakala | 21ce849 | 2010-05-13 17:33:41 +0000 | [diff] [blame] | 172 | mac->max_msix_vectors = ixgbe_get_pcie_msix_count_generic(hw); |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 173 | |
PJ Waskiewicz | 04f165e | 2009-04-09 22:27:57 +0000 | [diff] [blame] | 174 | return 0; |
| 175 | } |
| 176 | |
| 177 | /** |
| 178 | * ixgbe_init_phy_ops_82599 - PHY/SFP specific init |
| 179 | * @hw: pointer to hardware structure |
| 180 | * |
| 181 | * Initialize any function pointers that were not able to be |
| 182 | * set during get_invariants because the PHY/SFP type was |
| 183 | * not known. Perform the SFP init if necessary. |
| 184 | * |
| 185 | **/ |
Don Skidmore | 7b25cdb | 2009-08-25 04:47:32 +0000 | [diff] [blame] | 186 | static s32 ixgbe_init_phy_ops_82599(struct ixgbe_hw *hw) |
PJ Waskiewicz | 04f165e | 2009-04-09 22:27:57 +0000 | [diff] [blame] | 187 | { |
| 188 | struct ixgbe_mac_info *mac = &hw->mac; |
| 189 | struct ixgbe_phy_info *phy = &hw->phy; |
| 190 | s32 ret_val = 0; |
| 191 | |
| 192 | /* Identify the PHY or SFP module */ |
| 193 | ret_val = phy->ops.identify(hw); |
| 194 | |
| 195 | /* Setup function pointers based on detected SFP module and speeds */ |
| 196 | ixgbe_init_mac_link_ops_82599(hw); |
| 197 | |
| 198 | /* If copper media, overwrite with copper function pointers */ |
| 199 | if (mac->ops.get_media_type(hw) == ixgbe_media_type_copper) { |
| 200 | mac->ops.setup_link = &ixgbe_setup_copper_link_82599; |
PJ Waskiewicz | 04f165e | 2009-04-09 22:27:57 +0000 | [diff] [blame] | 201 | mac->ops.get_link_capabilities = |
Don Skidmore | a391f1d | 2010-11-16 19:27:15 -0800 | [diff] [blame] | 202 | &ixgbe_get_copper_link_capabilities_generic; |
PJ Waskiewicz | 04f165e | 2009-04-09 22:27:57 +0000 | [diff] [blame] | 203 | } |
| 204 | |
| 205 | /* Set necessary function pointers based on phy type */ |
| 206 | switch (hw->phy.type) { |
| 207 | case ixgbe_phy_tn: |
| 208 | phy->ops.check_link = &ixgbe_check_phy_link_tnx; |
| 209 | phy->ops.get_firmware_version = |
| 210 | &ixgbe_get_phy_firmware_version_tnx; |
| 211 | break; |
Don Skidmore | fe15e8e | 2010-11-16 19:27:16 -0800 | [diff] [blame] | 212 | case ixgbe_phy_aq: |
| 213 | phy->ops.get_firmware_version = |
| 214 | &ixgbe_get_phy_firmware_version_generic; |
| 215 | break; |
PJ Waskiewicz | 04f165e | 2009-04-09 22:27:57 +0000 | [diff] [blame] | 216 | default: |
| 217 | break; |
| 218 | } |
| 219 | |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 220 | return ret_val; |
| 221 | } |
| 222 | |
| 223 | /** |
| 224 | * ixgbe_get_link_capabilities_82599 - Determines link capabilities |
| 225 | * @hw: pointer to hardware structure |
| 226 | * @speed: pointer to link speed |
| 227 | * @negotiation: true when autoneg or autotry is enabled |
| 228 | * |
| 229 | * Determines the link capabilities by reading the AUTOC register. |
| 230 | **/ |
Don Skidmore | 7b25cdb | 2009-08-25 04:47:32 +0000 | [diff] [blame] | 231 | static s32 ixgbe_get_link_capabilities_82599(struct ixgbe_hw *hw, |
| 232 | ixgbe_link_speed *speed, |
| 233 | bool *negotiation) |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 234 | { |
| 235 | s32 status = 0; |
PJ Waskiewicz | 1eb99d5 | 2009-04-09 22:28:33 +0000 | [diff] [blame] | 236 | u32 autoc = 0; |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 237 | |
Don Skidmore | cb836a9 | 2010-06-29 18:30:59 +0000 | [diff] [blame] | 238 | /* Determine 1G link capabilities off of SFP+ type */ |
| 239 | if (hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0 || |
| 240 | hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1) { |
| 241 | *speed = IXGBE_LINK_SPEED_1GB_FULL; |
| 242 | *negotiation = true; |
| 243 | goto out; |
| 244 | } |
| 245 | |
PJ Waskiewicz | 1eb99d5 | 2009-04-09 22:28:33 +0000 | [diff] [blame] | 246 | /* |
| 247 | * Determine link capabilities based on the stored value of AUTOC, |
| 248 | * which represents EEPROM defaults. If AUTOC value has not been |
| 249 | * stored, use the current register value. |
| 250 | */ |
| 251 | if (hw->mac.orig_link_settings_stored) |
| 252 | autoc = hw->mac.orig_autoc; |
| 253 | else |
| 254 | autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC); |
| 255 | |
| 256 | switch (autoc & IXGBE_AUTOC_LMS_MASK) { |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 257 | case IXGBE_AUTOC_LMS_1G_LINK_NO_AN: |
| 258 | *speed = IXGBE_LINK_SPEED_1GB_FULL; |
| 259 | *negotiation = false; |
| 260 | break; |
| 261 | |
| 262 | case IXGBE_AUTOC_LMS_10G_LINK_NO_AN: |
| 263 | *speed = IXGBE_LINK_SPEED_10GB_FULL; |
| 264 | *negotiation = false; |
| 265 | break; |
| 266 | |
| 267 | case IXGBE_AUTOC_LMS_1G_AN: |
| 268 | *speed = IXGBE_LINK_SPEED_1GB_FULL; |
| 269 | *negotiation = true; |
| 270 | break; |
| 271 | |
| 272 | case IXGBE_AUTOC_LMS_10G_SERIAL: |
| 273 | *speed = IXGBE_LINK_SPEED_10GB_FULL; |
| 274 | *negotiation = false; |
| 275 | break; |
| 276 | |
| 277 | case IXGBE_AUTOC_LMS_KX4_KX_KR: |
| 278 | case IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN: |
| 279 | *speed = IXGBE_LINK_SPEED_UNKNOWN; |
PJ Waskiewicz | 1eb99d5 | 2009-04-09 22:28:33 +0000 | [diff] [blame] | 280 | if (autoc & IXGBE_AUTOC_KR_SUPP) |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 281 | *speed |= IXGBE_LINK_SPEED_10GB_FULL; |
PJ Waskiewicz | 1eb99d5 | 2009-04-09 22:28:33 +0000 | [diff] [blame] | 282 | if (autoc & IXGBE_AUTOC_KX4_SUPP) |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 283 | *speed |= IXGBE_LINK_SPEED_10GB_FULL; |
PJ Waskiewicz | 1eb99d5 | 2009-04-09 22:28:33 +0000 | [diff] [blame] | 284 | if (autoc & IXGBE_AUTOC_KX_SUPP) |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 285 | *speed |= IXGBE_LINK_SPEED_1GB_FULL; |
| 286 | *negotiation = true; |
| 287 | break; |
| 288 | |
| 289 | case IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII: |
| 290 | *speed = IXGBE_LINK_SPEED_100_FULL; |
PJ Waskiewicz | 1eb99d5 | 2009-04-09 22:28:33 +0000 | [diff] [blame] | 291 | if (autoc & IXGBE_AUTOC_KR_SUPP) |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 292 | *speed |= IXGBE_LINK_SPEED_10GB_FULL; |
PJ Waskiewicz | 1eb99d5 | 2009-04-09 22:28:33 +0000 | [diff] [blame] | 293 | if (autoc & IXGBE_AUTOC_KX4_SUPP) |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 294 | *speed |= IXGBE_LINK_SPEED_10GB_FULL; |
PJ Waskiewicz | 1eb99d5 | 2009-04-09 22:28:33 +0000 | [diff] [blame] | 295 | if (autoc & IXGBE_AUTOC_KX_SUPP) |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 296 | *speed |= IXGBE_LINK_SPEED_1GB_FULL; |
| 297 | *negotiation = true; |
| 298 | break; |
| 299 | |
| 300 | case IXGBE_AUTOC_LMS_SGMII_1G_100M: |
| 301 | *speed = IXGBE_LINK_SPEED_1GB_FULL | IXGBE_LINK_SPEED_100_FULL; |
| 302 | *negotiation = false; |
| 303 | break; |
| 304 | |
| 305 | default: |
| 306 | status = IXGBE_ERR_LINK_SETUP; |
| 307 | goto out; |
| 308 | break; |
| 309 | } |
| 310 | |
| 311 | if (hw->phy.multispeed_fiber) { |
| 312 | *speed |= IXGBE_LINK_SPEED_10GB_FULL | |
| 313 | IXGBE_LINK_SPEED_1GB_FULL; |
| 314 | *negotiation = true; |
| 315 | } |
| 316 | |
| 317 | out: |
| 318 | return status; |
| 319 | } |
| 320 | |
| 321 | /** |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 322 | * ixgbe_get_media_type_82599 - Get media type |
| 323 | * @hw: pointer to hardware structure |
| 324 | * |
| 325 | * Returns the media type (fiber, copper, backplane) |
| 326 | **/ |
Don Skidmore | 7b25cdb | 2009-08-25 04:47:32 +0000 | [diff] [blame] | 327 | static enum ixgbe_media_type ixgbe_get_media_type_82599(struct ixgbe_hw *hw) |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 328 | { |
| 329 | enum ixgbe_media_type media_type; |
| 330 | |
| 331 | /* Detect if there is a copper PHY attached. */ |
Emil Tantilov | 21cc5b4 | 2011-02-12 10:52:07 +0000 | [diff] [blame] | 332 | switch (hw->phy.type) { |
| 333 | case ixgbe_phy_cu_unknown: |
| 334 | case ixgbe_phy_tn: |
| 335 | case ixgbe_phy_aq: |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 336 | media_type = ixgbe_media_type_copper; |
| 337 | goto out; |
Emil Tantilov | 21cc5b4 | 2011-02-12 10:52:07 +0000 | [diff] [blame] | 338 | default: |
| 339 | break; |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 340 | } |
| 341 | |
| 342 | switch (hw->device_id) { |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 343 | case IXGBE_DEV_ID_82599_KX4: |
Don Skidmore | dbfec66 | 2009-10-02 08:58:25 +0000 | [diff] [blame] | 344 | case IXGBE_DEV_ID_82599_KX4_MEZZ: |
Don Skidmore | 312eb93 | 2009-10-02 08:58:04 +0000 | [diff] [blame] | 345 | case IXGBE_DEV_ID_82599_COMBO_BACKPLANE: |
Don Skidmore | 74757d4 | 2009-12-08 07:22:23 +0000 | [diff] [blame] | 346 | case IXGBE_DEV_ID_82599_KR: |
Don Skidmore | dbffcb2 | 2010-12-03 03:32:34 +0000 | [diff] [blame] | 347 | case IXGBE_DEV_ID_82599_BACKPLANE_FCOE: |
Peter P Waskiewicz Jr | 1fcf03e | 2009-05-17 20:58:04 +0000 | [diff] [blame] | 348 | case IXGBE_DEV_ID_82599_XAUI_LOM: |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 349 | /* Default device ID is mezzanine card KX/KX4 */ |
| 350 | media_type = ixgbe_media_type_backplane; |
| 351 | break; |
| 352 | case IXGBE_DEV_ID_82599_SFP: |
Don Skidmore | dbffcb2 | 2010-12-03 03:32:34 +0000 | [diff] [blame] | 353 | case IXGBE_DEV_ID_82599_SFP_FCOE: |
Don Skidmore | 38ad1c8 | 2009-10-08 15:35:58 +0000 | [diff] [blame] | 354 | case IXGBE_DEV_ID_82599_SFP_EM: |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 355 | media_type = ixgbe_media_type_fiber; |
| 356 | break; |
Peter P Waskiewicz Jr | 8911184 | 2009-09-14 07:47:49 +0000 | [diff] [blame] | 357 | case IXGBE_DEV_ID_82599_CX4: |
Peter P Waskiewicz Jr | 6b1be19 | 2009-09-14 07:48:10 +0000 | [diff] [blame] | 358 | media_type = ixgbe_media_type_cx4; |
Peter P Waskiewicz Jr | 8911184 | 2009-09-14 07:47:49 +0000 | [diff] [blame] | 359 | break; |
Emil Tantilov | 21cc5b4 | 2011-02-12 10:52:07 +0000 | [diff] [blame] | 360 | case IXGBE_DEV_ID_82599_T3_LOM: |
| 361 | media_type = ixgbe_media_type_copper; |
| 362 | break; |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 363 | default: |
| 364 | media_type = ixgbe_media_type_unknown; |
| 365 | break; |
| 366 | } |
| 367 | out: |
| 368 | return media_type; |
| 369 | } |
| 370 | |
| 371 | /** |
Mallikarjuna R Chilakala | 8620a10 | 2009-09-01 13:49:35 +0000 | [diff] [blame] | 372 | * ixgbe_start_mac_link_82599 - Setup MAC link settings |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 373 | * @hw: pointer to hardware structure |
Mallikarjuna R Chilakala | 8620a10 | 2009-09-01 13:49:35 +0000 | [diff] [blame] | 374 | * @autoneg_wait_to_complete: true when waiting for completion is needed |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 375 | * |
| 376 | * Configures link settings based on values in the ixgbe_hw struct. |
| 377 | * Restarts the link. Performs autonegotiation if needed. |
| 378 | **/ |
Emil Tantilov | 5d5b7c3 | 2010-10-12 22:20:59 +0000 | [diff] [blame] | 379 | static s32 ixgbe_start_mac_link_82599(struct ixgbe_hw *hw, |
Mallikarjuna R Chilakala | 8620a10 | 2009-09-01 13:49:35 +0000 | [diff] [blame] | 380 | bool autoneg_wait_to_complete) |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 381 | { |
| 382 | u32 autoc_reg; |
| 383 | u32 links_reg; |
| 384 | u32 i; |
| 385 | s32 status = 0; |
| 386 | |
| 387 | /* Restart link */ |
| 388 | autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC); |
| 389 | autoc_reg |= IXGBE_AUTOC_AN_RESTART; |
| 390 | IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc_reg); |
| 391 | |
| 392 | /* Only poll for autoneg to complete if specified to do so */ |
Mallikarjuna R Chilakala | 8620a10 | 2009-09-01 13:49:35 +0000 | [diff] [blame] | 393 | if (autoneg_wait_to_complete) { |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 394 | if ((autoc_reg & IXGBE_AUTOC_LMS_MASK) == |
| 395 | IXGBE_AUTOC_LMS_KX4_KX_KR || |
| 396 | (autoc_reg & IXGBE_AUTOC_LMS_MASK) == |
| 397 | IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN || |
| 398 | (autoc_reg & IXGBE_AUTOC_LMS_MASK) == |
| 399 | IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII) { |
| 400 | links_reg = 0; /* Just in case Autoneg time = 0 */ |
| 401 | for (i = 0; i < IXGBE_AUTO_NEG_TIME; i++) { |
| 402 | links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS); |
| 403 | if (links_reg & IXGBE_LINKS_KX_AN_COMP) |
| 404 | break; |
| 405 | msleep(100); |
| 406 | } |
| 407 | if (!(links_reg & IXGBE_LINKS_KX_AN_COMP)) { |
| 408 | status = IXGBE_ERR_AUTONEG_NOT_COMPLETE; |
| 409 | hw_dbg(hw, "Autoneg did not complete.\n"); |
| 410 | } |
| 411 | } |
| 412 | } |
| 413 | |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 414 | /* Add delay to filter out noises during initial link setup */ |
| 415 | msleep(50); |
| 416 | |
| 417 | return status; |
| 418 | } |
| 419 | |
Peter Waskiewicz | 61fac74 | 2010-04-27 00:38:15 +0000 | [diff] [blame] | 420 | /** |
| 421 | * ixgbe_disable_tx_laser_multispeed_fiber - Disable Tx laser |
| 422 | * @hw: pointer to hardware structure |
| 423 | * |
| 424 | * The base drivers may require better control over SFP+ module |
| 425 | * PHY states. This includes selectively shutting down the Tx |
| 426 | * laser on the PHY, effectively halting physical link. |
| 427 | **/ |
Emil Tantilov | 5d5b7c3 | 2010-10-12 22:20:59 +0000 | [diff] [blame] | 428 | static void ixgbe_disable_tx_laser_multispeed_fiber(struct ixgbe_hw *hw) |
Peter Waskiewicz | 61fac74 | 2010-04-27 00:38:15 +0000 | [diff] [blame] | 429 | { |
| 430 | u32 esdp_reg = IXGBE_READ_REG(hw, IXGBE_ESDP); |
| 431 | |
| 432 | /* Disable tx laser; allow 100us to go dark per spec */ |
| 433 | esdp_reg |= IXGBE_ESDP_SDP3; |
| 434 | IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg); |
| 435 | IXGBE_WRITE_FLUSH(hw); |
| 436 | udelay(100); |
| 437 | } |
| 438 | |
| 439 | /** |
| 440 | * ixgbe_enable_tx_laser_multispeed_fiber - Enable Tx laser |
| 441 | * @hw: pointer to hardware structure |
| 442 | * |
| 443 | * The base drivers may require better control over SFP+ module |
| 444 | * PHY states. This includes selectively turning on the Tx |
| 445 | * laser on the PHY, effectively starting physical link. |
| 446 | **/ |
Emil Tantilov | 5d5b7c3 | 2010-10-12 22:20:59 +0000 | [diff] [blame] | 447 | static void ixgbe_enable_tx_laser_multispeed_fiber(struct ixgbe_hw *hw) |
Peter Waskiewicz | 61fac74 | 2010-04-27 00:38:15 +0000 | [diff] [blame] | 448 | { |
| 449 | u32 esdp_reg = IXGBE_READ_REG(hw, IXGBE_ESDP); |
| 450 | |
| 451 | /* Enable tx laser; allow 100ms to light up */ |
| 452 | esdp_reg &= ~IXGBE_ESDP_SDP3; |
| 453 | IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg); |
| 454 | IXGBE_WRITE_FLUSH(hw); |
| 455 | msleep(100); |
| 456 | } |
| 457 | |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 458 | /** |
Mallikarjuna R Chilakala | 1097cd1 | 2010-03-18 14:34:52 +0000 | [diff] [blame] | 459 | * ixgbe_flap_tx_laser_multispeed_fiber - Flap Tx laser |
| 460 | * @hw: pointer to hardware structure |
| 461 | * |
| 462 | * When the driver changes the link speeds that it can support, |
| 463 | * it sets autotry_restart to true to indicate that we need to |
| 464 | * initiate a new autotry session with the link partner. To do |
| 465 | * so, we set the speed then disable and re-enable the tx laser, to |
| 466 | * alert the link partner that it also needs to restart autotry on its |
| 467 | * end. This is consistent with true clause 37 autoneg, which also |
| 468 | * involves a loss of signal. |
| 469 | **/ |
Emil Tantilov | 5d5b7c3 | 2010-10-12 22:20:59 +0000 | [diff] [blame] | 470 | static void ixgbe_flap_tx_laser_multispeed_fiber(struct ixgbe_hw *hw) |
Mallikarjuna R Chilakala | 1097cd1 | 2010-03-18 14:34:52 +0000 | [diff] [blame] | 471 | { |
Mallikarjuna R Chilakala | 1097cd1 | 2010-03-18 14:34:52 +0000 | [diff] [blame] | 472 | hw_dbg(hw, "ixgbe_flap_tx_laser_multispeed_fiber\n"); |
| 473 | |
| 474 | if (hw->mac.autotry_restart) { |
Peter Waskiewicz | 61fac74 | 2010-04-27 00:38:15 +0000 | [diff] [blame] | 475 | ixgbe_disable_tx_laser_multispeed_fiber(hw); |
| 476 | ixgbe_enable_tx_laser_multispeed_fiber(hw); |
Mallikarjuna R Chilakala | 1097cd1 | 2010-03-18 14:34:52 +0000 | [diff] [blame] | 477 | hw->mac.autotry_restart = false; |
| 478 | } |
| 479 | } |
| 480 | |
| 481 | /** |
Mallikarjuna R Chilakala | 8620a10 | 2009-09-01 13:49:35 +0000 | [diff] [blame] | 482 | * ixgbe_setup_mac_link_multispeed_fiber - Set MAC link speed |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 483 | * @hw: pointer to hardware structure |
| 484 | * @speed: new link speed |
| 485 | * @autoneg: true if autonegotiation enabled |
| 486 | * @autoneg_wait_to_complete: true when waiting for completion is needed |
| 487 | * |
| 488 | * Set the link speed in the AUTOC register and restarts link. |
| 489 | **/ |
Mallikarjuna R Chilakala | 8620a10 | 2009-09-01 13:49:35 +0000 | [diff] [blame] | 490 | s32 ixgbe_setup_mac_link_multispeed_fiber(struct ixgbe_hw *hw, |
| 491 | ixgbe_link_speed speed, |
| 492 | bool autoneg, |
| 493 | bool autoneg_wait_to_complete) |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 494 | { |
| 495 | s32 status = 0; |
| 496 | ixgbe_link_speed phy_link_speed; |
| 497 | ixgbe_link_speed highest_link_speed = IXGBE_LINK_SPEED_UNKNOWN; |
| 498 | u32 speedcnt = 0; |
| 499 | u32 esdp_reg = IXGBE_READ_REG(hw, IXGBE_ESDP); |
| 500 | bool link_up = false; |
| 501 | bool negotiation; |
Peter P Waskiewicz Jr | 50ac58b | 2009-06-04 11:10:53 +0000 | [diff] [blame] | 502 | int i; |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 503 | |
| 504 | /* Mask off requested but non-supported speeds */ |
| 505 | hw->mac.ops.get_link_capabilities(hw, &phy_link_speed, &negotiation); |
| 506 | speed &= phy_link_speed; |
| 507 | |
| 508 | /* |
| 509 | * Try each speed one by one, highest priority first. We do this in |
| 510 | * software because 10gb fiber doesn't support speed autonegotiation. |
| 511 | */ |
| 512 | if (speed & IXGBE_LINK_SPEED_10GB_FULL) { |
| 513 | speedcnt++; |
| 514 | highest_link_speed = IXGBE_LINK_SPEED_10GB_FULL; |
| 515 | |
Peter P Waskiewicz Jr | 50ac58b | 2009-06-04 11:10:53 +0000 | [diff] [blame] | 516 | /* If we already have link at this speed, just jump out */ |
| 517 | hw->mac.ops.check_link(hw, &phy_link_speed, &link_up, false); |
| 518 | |
| 519 | if ((phy_link_speed == IXGBE_LINK_SPEED_10GB_FULL) && link_up) |
| 520 | goto out; |
| 521 | |
| 522 | /* Set the module link speed */ |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 523 | esdp_reg |= (IXGBE_ESDP_SDP5_DIR | IXGBE_ESDP_SDP5); |
| 524 | IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg); |
Mallikarjuna R Chilakala | 1097cd1 | 2010-03-18 14:34:52 +0000 | [diff] [blame] | 525 | IXGBE_WRITE_FLUSH(hw); |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 526 | |
Peter P Waskiewicz Jr | 50ac58b | 2009-06-04 11:10:53 +0000 | [diff] [blame] | 527 | /* Allow module to change analog characteristics (1G->10G) */ |
| 528 | msleep(40); |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 529 | |
Mallikarjuna R Chilakala | 8620a10 | 2009-09-01 13:49:35 +0000 | [diff] [blame] | 530 | status = ixgbe_setup_mac_link_82599(hw, |
| 531 | IXGBE_LINK_SPEED_10GB_FULL, |
| 532 | autoneg, |
| 533 | autoneg_wait_to_complete); |
Peter P Waskiewicz Jr | 50ac58b | 2009-06-04 11:10:53 +0000 | [diff] [blame] | 534 | if (status != 0) |
Mallikarjuna R Chilakala | c3c7432 | 2009-09-01 13:50:14 +0000 | [diff] [blame] | 535 | return status; |
Peter P Waskiewicz Jr | 50ac58b | 2009-06-04 11:10:53 +0000 | [diff] [blame] | 536 | |
| 537 | /* Flap the tx laser if it has not already been done */ |
Mallikarjuna R Chilakala | 1097cd1 | 2010-03-18 14:34:52 +0000 | [diff] [blame] | 538 | hw->mac.ops.flap_tx_laser(hw); |
Peter P Waskiewicz Jr | 50ac58b | 2009-06-04 11:10:53 +0000 | [diff] [blame] | 539 | |
Don Skidmore | cd7e1f0 | 2009-10-08 15:36:22 +0000 | [diff] [blame] | 540 | /* |
| 541 | * Wait for the controller to acquire link. Per IEEE 802.3ap, |
| 542 | * Section 73.10.2, we may have to wait up to 500ms if KR is |
| 543 | * attempted. 82599 uses the same timing for 10g SFI. |
| 544 | */ |
| 545 | |
Peter P Waskiewicz Jr | 50ac58b | 2009-06-04 11:10:53 +0000 | [diff] [blame] | 546 | for (i = 0; i < 5; i++) { |
| 547 | /* Wait for the link partner to also set speed */ |
| 548 | msleep(100); |
| 549 | |
| 550 | /* If we have link, just jump out */ |
| 551 | hw->mac.ops.check_link(hw, &phy_link_speed, |
| 552 | &link_up, false); |
| 553 | if (link_up) |
| 554 | goto out; |
| 555 | } |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 556 | } |
| 557 | |
| 558 | if (speed & IXGBE_LINK_SPEED_1GB_FULL) { |
| 559 | speedcnt++; |
| 560 | if (highest_link_speed == IXGBE_LINK_SPEED_UNKNOWN) |
| 561 | highest_link_speed = IXGBE_LINK_SPEED_1GB_FULL; |
| 562 | |
Peter P Waskiewicz Jr | 50ac58b | 2009-06-04 11:10:53 +0000 | [diff] [blame] | 563 | /* If we already have link at this speed, just jump out */ |
| 564 | hw->mac.ops.check_link(hw, &phy_link_speed, &link_up, false); |
| 565 | |
| 566 | if ((phy_link_speed == IXGBE_LINK_SPEED_1GB_FULL) && link_up) |
| 567 | goto out; |
| 568 | |
| 569 | /* Set the module link speed */ |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 570 | esdp_reg &= ~IXGBE_ESDP_SDP5; |
| 571 | esdp_reg |= IXGBE_ESDP_SDP5_DIR; |
| 572 | IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg); |
Mallikarjuna R Chilakala | 1097cd1 | 2010-03-18 14:34:52 +0000 | [diff] [blame] | 573 | IXGBE_WRITE_FLUSH(hw); |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 574 | |
Peter P Waskiewicz Jr | 50ac58b | 2009-06-04 11:10:53 +0000 | [diff] [blame] | 575 | /* Allow module to change analog characteristics (10G->1G) */ |
| 576 | msleep(40); |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 577 | |
Mallikarjuna R Chilakala | 8620a10 | 2009-09-01 13:49:35 +0000 | [diff] [blame] | 578 | status = ixgbe_setup_mac_link_82599(hw, |
Peter P Waskiewicz Jr | 50ac58b | 2009-06-04 11:10:53 +0000 | [diff] [blame] | 579 | IXGBE_LINK_SPEED_1GB_FULL, |
| 580 | autoneg, |
| 581 | autoneg_wait_to_complete); |
| 582 | if (status != 0) |
Mallikarjuna R Chilakala | c3c7432 | 2009-09-01 13:50:14 +0000 | [diff] [blame] | 583 | return status; |
Peter P Waskiewicz Jr | 50ac58b | 2009-06-04 11:10:53 +0000 | [diff] [blame] | 584 | |
| 585 | /* Flap the tx laser if it has not already been done */ |
Mallikarjuna R Chilakala | 1097cd1 | 2010-03-18 14:34:52 +0000 | [diff] [blame] | 586 | hw->mac.ops.flap_tx_laser(hw); |
Peter P Waskiewicz Jr | 50ac58b | 2009-06-04 11:10:53 +0000 | [diff] [blame] | 587 | |
| 588 | /* Wait for the link partner to also set speed */ |
| 589 | msleep(100); |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 590 | |
| 591 | /* If we have link, just jump out */ |
| 592 | hw->mac.ops.check_link(hw, &phy_link_speed, &link_up, false); |
| 593 | if (link_up) |
| 594 | goto out; |
| 595 | } |
| 596 | |
| 597 | /* |
| 598 | * We didn't get link. Configure back to the highest speed we tried, |
| 599 | * (if there was more than one). We call ourselves back with just the |
| 600 | * single highest speed that the user requested. |
| 601 | */ |
| 602 | if (speedcnt > 1) |
Mallikarjuna R Chilakala | 8620a10 | 2009-09-01 13:49:35 +0000 | [diff] [blame] | 603 | status = ixgbe_setup_mac_link_multispeed_fiber(hw, |
| 604 | highest_link_speed, |
| 605 | autoneg, |
| 606 | autoneg_wait_to_complete); |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 607 | |
| 608 | out: |
Mallikarjuna R Chilakala | c3c7432 | 2009-09-01 13:50:14 +0000 | [diff] [blame] | 609 | /* Set autoneg_advertised value based on input link speed */ |
| 610 | hw->phy.autoneg_advertised = 0; |
| 611 | |
| 612 | if (speed & IXGBE_LINK_SPEED_10GB_FULL) |
| 613 | hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL; |
| 614 | |
| 615 | if (speed & IXGBE_LINK_SPEED_1GB_FULL) |
| 616 | hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL; |
| 617 | |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 618 | return status; |
| 619 | } |
| 620 | |
| 621 | /** |
Don Skidmore | cd7e1f0 | 2009-10-08 15:36:22 +0000 | [diff] [blame] | 622 | * ixgbe_setup_mac_link_smartspeed - Set MAC link speed using SmartSpeed |
| 623 | * @hw: pointer to hardware structure |
| 624 | * @speed: new link speed |
| 625 | * @autoneg: true if autonegotiation enabled |
| 626 | * @autoneg_wait_to_complete: true when waiting for completion is needed |
| 627 | * |
| 628 | * Implements the Intel SmartSpeed algorithm. |
| 629 | **/ |
| 630 | static s32 ixgbe_setup_mac_link_smartspeed(struct ixgbe_hw *hw, |
| 631 | ixgbe_link_speed speed, bool autoneg, |
| 632 | bool autoneg_wait_to_complete) |
| 633 | { |
| 634 | s32 status = 0; |
| 635 | ixgbe_link_speed link_speed; |
| 636 | s32 i, j; |
| 637 | bool link_up = false; |
| 638 | u32 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC); |
Anjali Singhai | c4ee6a5 | 2010-04-27 11:31:25 +0000 | [diff] [blame] | 639 | struct ixgbe_adapter *adapter = hw->back; |
Don Skidmore | cd7e1f0 | 2009-10-08 15:36:22 +0000 | [diff] [blame] | 640 | |
| 641 | hw_dbg(hw, "ixgbe_setup_mac_link_smartspeed.\n"); |
| 642 | |
| 643 | /* Set autoneg_advertised value based on input link speed */ |
| 644 | hw->phy.autoneg_advertised = 0; |
| 645 | |
| 646 | if (speed & IXGBE_LINK_SPEED_10GB_FULL) |
| 647 | hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL; |
| 648 | |
| 649 | if (speed & IXGBE_LINK_SPEED_1GB_FULL) |
| 650 | hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL; |
| 651 | |
| 652 | if (speed & IXGBE_LINK_SPEED_100_FULL) |
| 653 | hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_100_FULL; |
| 654 | |
| 655 | /* |
| 656 | * Implement Intel SmartSpeed algorithm. SmartSpeed will reduce the |
| 657 | * autoneg advertisement if link is unable to be established at the |
| 658 | * highest negotiated rate. This can sometimes happen due to integrity |
| 659 | * issues with the physical media connection. |
| 660 | */ |
| 661 | |
| 662 | /* First, try to get link with full advertisement */ |
| 663 | hw->phy.smart_speed_active = false; |
| 664 | for (j = 0; j < IXGBE_SMARTSPEED_MAX_RETRIES; j++) { |
| 665 | status = ixgbe_setup_mac_link_82599(hw, speed, autoneg, |
| 666 | autoneg_wait_to_complete); |
| 667 | if (status) |
| 668 | goto out; |
| 669 | |
| 670 | /* |
| 671 | * Wait for the controller to acquire link. Per IEEE 802.3ap, |
| 672 | * Section 73.10.2, we may have to wait up to 500ms if KR is |
| 673 | * attempted, or 200ms if KX/KX4/BX/BX4 is attempted, per |
| 674 | * Table 9 in the AN MAS. |
| 675 | */ |
| 676 | for (i = 0; i < 5; i++) { |
| 677 | mdelay(100); |
| 678 | |
| 679 | /* If we have link, just jump out */ |
| 680 | hw->mac.ops.check_link(hw, &link_speed, |
| 681 | &link_up, false); |
| 682 | if (link_up) |
| 683 | goto out; |
| 684 | } |
| 685 | } |
| 686 | |
| 687 | /* |
| 688 | * We didn't get link. If we advertised KR plus one of KX4/KX |
| 689 | * (or BX4/BX), then disable KR and try again. |
| 690 | */ |
| 691 | if (((autoc_reg & IXGBE_AUTOC_KR_SUPP) == 0) || |
| 692 | ((autoc_reg & IXGBE_AUTOC_KX4_KX_SUPP_MASK) == 0)) |
| 693 | goto out; |
| 694 | |
| 695 | /* Turn SmartSpeed on to disable KR support */ |
| 696 | hw->phy.smart_speed_active = true; |
| 697 | status = ixgbe_setup_mac_link_82599(hw, speed, autoneg, |
| 698 | autoneg_wait_to_complete); |
| 699 | if (status) |
| 700 | goto out; |
| 701 | |
| 702 | /* |
| 703 | * Wait for the controller to acquire link. 600ms will allow for |
| 704 | * the AN link_fail_inhibit_timer as well for multiple cycles of |
| 705 | * parallel detect, both 10g and 1g. This allows for the maximum |
| 706 | * connect attempts as defined in the AN MAS table 73-7. |
| 707 | */ |
| 708 | for (i = 0; i < 6; i++) { |
| 709 | mdelay(100); |
| 710 | |
| 711 | /* If we have link, just jump out */ |
| 712 | hw->mac.ops.check_link(hw, &link_speed, |
| 713 | &link_up, false); |
| 714 | if (link_up) |
| 715 | goto out; |
| 716 | } |
| 717 | |
| 718 | /* We didn't get link. Turn SmartSpeed back off. */ |
| 719 | hw->phy.smart_speed_active = false; |
| 720 | status = ixgbe_setup_mac_link_82599(hw, speed, autoneg, |
| 721 | autoneg_wait_to_complete); |
| 722 | |
| 723 | out: |
Anjali Singhai | c4ee6a5 | 2010-04-27 11:31:25 +0000 | [diff] [blame] | 724 | if (link_up && (link_speed == IXGBE_LINK_SPEED_1GB_FULL)) |
Emil Tantilov | 396e799 | 2010-07-01 20:05:12 +0000 | [diff] [blame] | 725 | e_info(hw, "Smartspeed has downgraded the link speed from " |
Emil Tantilov | 849c454 | 2010-06-03 16:53:41 +0000 | [diff] [blame] | 726 | "the maximum advertised\n"); |
Don Skidmore | cd7e1f0 | 2009-10-08 15:36:22 +0000 | [diff] [blame] | 727 | return status; |
| 728 | } |
| 729 | |
| 730 | /** |
Mallikarjuna R Chilakala | 8620a10 | 2009-09-01 13:49:35 +0000 | [diff] [blame] | 731 | * ixgbe_setup_mac_link_82599 - Set MAC link speed |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 732 | * @hw: pointer to hardware structure |
| 733 | * @speed: new link speed |
| 734 | * @autoneg: true if autonegotiation enabled |
| 735 | * @autoneg_wait_to_complete: true when waiting for completion is needed |
| 736 | * |
| 737 | * Set the link speed in the AUTOC register and restarts link. |
| 738 | **/ |
Emil Tantilov | 5d5b7c3 | 2010-10-12 22:20:59 +0000 | [diff] [blame] | 739 | static s32 ixgbe_setup_mac_link_82599(struct ixgbe_hw *hw, |
Mallikarjuna R Chilakala | 8620a10 | 2009-09-01 13:49:35 +0000 | [diff] [blame] | 740 | ixgbe_link_speed speed, bool autoneg, |
| 741 | bool autoneg_wait_to_complete) |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 742 | { |
| 743 | s32 status = 0; |
| 744 | u32 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC); |
| 745 | u32 autoc2 = IXGBE_READ_REG(hw, IXGBE_AUTOC2); |
Peter P Waskiewicz Jr | 50ac58b | 2009-06-04 11:10:53 +0000 | [diff] [blame] | 746 | u32 start_autoc = autoc; |
PJ Waskiewicz | 1eb99d5 | 2009-04-09 22:28:33 +0000 | [diff] [blame] | 747 | u32 orig_autoc = 0; |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 748 | u32 link_mode = autoc & IXGBE_AUTOC_LMS_MASK; |
| 749 | u32 pma_pmd_1g = autoc & IXGBE_AUTOC_1G_PMA_PMD_MASK; |
| 750 | u32 pma_pmd_10g_serial = autoc2 & IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_MASK; |
| 751 | u32 links_reg; |
| 752 | u32 i; |
| 753 | ixgbe_link_speed link_capabilities = IXGBE_LINK_SPEED_UNKNOWN; |
| 754 | |
| 755 | /* Check to see if speed passed in is supported. */ |
| 756 | hw->mac.ops.get_link_capabilities(hw, &link_capabilities, &autoneg); |
| 757 | speed &= link_capabilities; |
| 758 | |
Peter P Waskiewicz Jr | 50ac58b | 2009-06-04 11:10:53 +0000 | [diff] [blame] | 759 | if (speed == IXGBE_LINK_SPEED_UNKNOWN) { |
| 760 | status = IXGBE_ERR_LINK_SETUP; |
| 761 | goto out; |
| 762 | } |
| 763 | |
PJ Waskiewicz | 1eb99d5 | 2009-04-09 22:28:33 +0000 | [diff] [blame] | 764 | /* Use stored value (EEPROM defaults) of AUTOC to find KR/KX4 support*/ |
| 765 | if (hw->mac.orig_link_settings_stored) |
| 766 | orig_autoc = hw->mac.orig_autoc; |
| 767 | else |
| 768 | orig_autoc = autoc; |
| 769 | |
| 770 | |
Peter P Waskiewicz Jr | 50ac58b | 2009-06-04 11:10:53 +0000 | [diff] [blame] | 771 | if (link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR || |
| 772 | link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN || |
| 773 | link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII) { |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 774 | /* Set KX4/KX/KR support according to speed requested */ |
| 775 | autoc &= ~(IXGBE_AUTOC_KX4_KX_SUPP_MASK | IXGBE_AUTOC_KR_SUPP); |
| 776 | if (speed & IXGBE_LINK_SPEED_10GB_FULL) |
PJ Waskiewicz | 1eb99d5 | 2009-04-09 22:28:33 +0000 | [diff] [blame] | 777 | if (orig_autoc & IXGBE_AUTOC_KX4_SUPP) |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 778 | autoc |= IXGBE_AUTOC_KX4_SUPP; |
Don Skidmore | cd7e1f0 | 2009-10-08 15:36:22 +0000 | [diff] [blame] | 779 | if ((orig_autoc & IXGBE_AUTOC_KR_SUPP) && |
| 780 | (hw->phy.smart_speed_active == false)) |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 781 | autoc |= IXGBE_AUTOC_KR_SUPP; |
| 782 | if (speed & IXGBE_LINK_SPEED_1GB_FULL) |
| 783 | autoc |= IXGBE_AUTOC_KX_SUPP; |
| 784 | } else if ((pma_pmd_1g == IXGBE_AUTOC_1G_SFI) && |
| 785 | (link_mode == IXGBE_AUTOC_LMS_1G_LINK_NO_AN || |
| 786 | link_mode == IXGBE_AUTOC_LMS_1G_AN)) { |
| 787 | /* Switch from 1G SFI to 10G SFI if requested */ |
| 788 | if ((speed == IXGBE_LINK_SPEED_10GB_FULL) && |
| 789 | (pma_pmd_10g_serial == IXGBE_AUTOC2_10G_SFI)) { |
| 790 | autoc &= ~IXGBE_AUTOC_LMS_MASK; |
| 791 | autoc |= IXGBE_AUTOC_LMS_10G_SERIAL; |
| 792 | } |
| 793 | } else if ((pma_pmd_10g_serial == IXGBE_AUTOC2_10G_SFI) && |
| 794 | (link_mode == IXGBE_AUTOC_LMS_10G_SERIAL)) { |
| 795 | /* Switch from 10G SFI to 1G SFI if requested */ |
| 796 | if ((speed == IXGBE_LINK_SPEED_1GB_FULL) && |
| 797 | (pma_pmd_1g == IXGBE_AUTOC_1G_SFI)) { |
| 798 | autoc &= ~IXGBE_AUTOC_LMS_MASK; |
| 799 | if (autoneg) |
| 800 | autoc |= IXGBE_AUTOC_LMS_1G_AN; |
| 801 | else |
| 802 | autoc |= IXGBE_AUTOC_LMS_1G_LINK_NO_AN; |
| 803 | } |
| 804 | } |
| 805 | |
Peter P Waskiewicz Jr | 50ac58b | 2009-06-04 11:10:53 +0000 | [diff] [blame] | 806 | if (autoc != start_autoc) { |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 807 | /* Restart link */ |
| 808 | autoc |= IXGBE_AUTOC_AN_RESTART; |
| 809 | IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc); |
| 810 | |
| 811 | /* Only poll for autoneg to complete if specified to do so */ |
| 812 | if (autoneg_wait_to_complete) { |
| 813 | if (link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR || |
| 814 | link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN || |
| 815 | link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII) { |
| 816 | links_reg = 0; /*Just in case Autoneg time=0*/ |
| 817 | for (i = 0; i < IXGBE_AUTO_NEG_TIME; i++) { |
| 818 | links_reg = |
| 819 | IXGBE_READ_REG(hw, IXGBE_LINKS); |
| 820 | if (links_reg & IXGBE_LINKS_KX_AN_COMP) |
| 821 | break; |
| 822 | msleep(100); |
| 823 | } |
| 824 | if (!(links_reg & IXGBE_LINKS_KX_AN_COMP)) { |
| 825 | status = |
| 826 | IXGBE_ERR_AUTONEG_NOT_COMPLETE; |
| 827 | hw_dbg(hw, "Autoneg did not " |
| 828 | "complete.\n"); |
| 829 | } |
| 830 | } |
| 831 | } |
| 832 | |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 833 | /* Add delay to filter out noises during initial link setup */ |
| 834 | msleep(50); |
| 835 | } |
| 836 | |
Peter P Waskiewicz Jr | 50ac58b | 2009-06-04 11:10:53 +0000 | [diff] [blame] | 837 | out: |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 838 | return status; |
| 839 | } |
| 840 | |
| 841 | /** |
Mallikarjuna R Chilakala | 8620a10 | 2009-09-01 13:49:35 +0000 | [diff] [blame] | 842 | * ixgbe_setup_copper_link_82599 - Set the PHY autoneg advertised field |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 843 | * @hw: pointer to hardware structure |
| 844 | * @speed: new link speed |
| 845 | * @autoneg: true if autonegotiation enabled |
| 846 | * @autoneg_wait_to_complete: true if waiting is needed to complete |
| 847 | * |
| 848 | * Restarts link on PHY and MAC based on settings passed in. |
| 849 | **/ |
Mallikarjuna R Chilakala | 8620a10 | 2009-09-01 13:49:35 +0000 | [diff] [blame] | 850 | static s32 ixgbe_setup_copper_link_82599(struct ixgbe_hw *hw, |
| 851 | ixgbe_link_speed speed, |
| 852 | bool autoneg, |
| 853 | bool autoneg_wait_to_complete) |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 854 | { |
| 855 | s32 status; |
| 856 | |
| 857 | /* Setup the PHY according to input speed */ |
| 858 | status = hw->phy.ops.setup_link_speed(hw, speed, autoneg, |
| 859 | autoneg_wait_to_complete); |
| 860 | /* Set up MAC */ |
Mallikarjuna R Chilakala | 8620a10 | 2009-09-01 13:49:35 +0000 | [diff] [blame] | 861 | ixgbe_start_mac_link_82599(hw, autoneg_wait_to_complete); |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 862 | |
| 863 | return status; |
| 864 | } |
| 865 | |
| 866 | /** |
| 867 | * ixgbe_reset_hw_82599 - Perform hardware reset |
| 868 | * @hw: pointer to hardware structure |
| 869 | * |
| 870 | * Resets the hardware by resetting the transmit and receive units, masks |
| 871 | * and clears all interrupts, perform a PHY reset, and perform a link (MAC) |
| 872 | * reset. |
| 873 | **/ |
Don Skidmore | 7b25cdb | 2009-08-25 04:47:32 +0000 | [diff] [blame] | 874 | static s32 ixgbe_reset_hw_82599(struct ixgbe_hw *hw) |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 875 | { |
| 876 | s32 status = 0; |
Greg Rose | c920569 | 2010-01-22 22:46:22 +0000 | [diff] [blame] | 877 | u32 ctrl; |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 878 | u32 i; |
| 879 | u32 autoc; |
| 880 | u32 autoc2; |
| 881 | |
| 882 | /* Call adapter stop to disable tx/rx and clear interrupts */ |
| 883 | hw->mac.ops.stop_adapter(hw); |
| 884 | |
PJ Waskiewicz | 553b449 | 2009-04-09 22:28:15 +0000 | [diff] [blame] | 885 | /* PHY ops must be identified and initialized prior to reset */ |
PJ Waskiewicz | 04f165e | 2009-04-09 22:27:57 +0000 | [diff] [blame] | 886 | |
PJ Waskiewicz | 553b449 | 2009-04-09 22:28:15 +0000 | [diff] [blame] | 887 | /* Init PHY and function pointers, perform SFP setup */ |
| 888 | status = hw->phy.ops.init(hw); |
PJ Waskiewicz | 04f165e | 2009-04-09 22:27:57 +0000 | [diff] [blame] | 889 | |
PJ Waskiewicz | 553b449 | 2009-04-09 22:28:15 +0000 | [diff] [blame] | 890 | if (status == IXGBE_ERR_SFP_NOT_SUPPORTED) |
| 891 | goto reset_hw_out; |
PJ Waskiewicz | 04f165e | 2009-04-09 22:27:57 +0000 | [diff] [blame] | 892 | |
PJ Waskiewicz | 553b449 | 2009-04-09 22:28:15 +0000 | [diff] [blame] | 893 | /* Setup SFP module if there is one present. */ |
| 894 | if (hw->phy.sfp_setup_needed) { |
| 895 | status = hw->mac.ops.setup_sfp(hw); |
| 896 | hw->phy.sfp_setup_needed = false; |
PJ Waskiewicz | 04f165e | 2009-04-09 22:27:57 +0000 | [diff] [blame] | 897 | } |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 898 | |
PJ Waskiewicz | 553b449 | 2009-04-09 22:28:15 +0000 | [diff] [blame] | 899 | /* Reset PHY */ |
| 900 | if (hw->phy.reset_disable == false && hw->phy.ops.reset != NULL) |
| 901 | hw->phy.ops.reset(hw); |
| 902 | |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 903 | /* |
| 904 | * Prevent the PCI-E bus from from hanging by disabling PCI-E master |
| 905 | * access and verify no pending requests before reset |
| 906 | */ |
Emil Tantilov | a4297dc | 2011-02-14 08:45:13 +0000 | [diff] [blame^] | 907 | ixgbe_disable_pcie_master(hw); |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 908 | |
Emil Tantilov | a4297dc | 2011-02-14 08:45:13 +0000 | [diff] [blame^] | 909 | mac_reset_top: |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 910 | /* |
| 911 | * Issue global reset to the MAC. This needs to be a SW reset. |
| 912 | * If link reset is used, it might reset the MAC when mng is using it |
| 913 | */ |
| 914 | ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL); |
| 915 | IXGBE_WRITE_REG(hw, IXGBE_CTRL, (ctrl | IXGBE_CTRL_RST)); |
| 916 | IXGBE_WRITE_FLUSH(hw); |
| 917 | |
| 918 | /* Poll for reset bit to self-clear indicating reset is complete */ |
| 919 | for (i = 0; i < 10; i++) { |
| 920 | udelay(1); |
| 921 | ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL); |
| 922 | if (!(ctrl & IXGBE_CTRL_RST)) |
| 923 | break; |
| 924 | } |
| 925 | if (ctrl & IXGBE_CTRL_RST) { |
| 926 | status = IXGBE_ERR_RESET_FAILED; |
| 927 | hw_dbg(hw, "Reset polling failed to complete.\n"); |
| 928 | } |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 929 | |
Emil Tantilov | a4297dc | 2011-02-14 08:45:13 +0000 | [diff] [blame^] | 930 | /* |
| 931 | * Double resets are required for recovery from certain error |
| 932 | * conditions. Between resets, it is necessary to stall to allow time |
| 933 | * for any pending HW events to complete. We use 1usec since that is |
| 934 | * what is needed for ixgbe_disable_pcie_master(). The second reset |
| 935 | * then clears out any effects of those events. |
| 936 | */ |
| 937 | if (hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED) { |
| 938 | hw->mac.flags &= ~IXGBE_FLAGS_DOUBLE_RESET_REQUIRED; |
| 939 | udelay(1); |
| 940 | goto mac_reset_top; |
| 941 | } |
| 942 | |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 943 | msleep(50); |
| 944 | |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 945 | /* |
| 946 | * Store the original AUTOC/AUTOC2 values if they have not been |
| 947 | * stored off yet. Otherwise restore the stored original |
| 948 | * values since the reset operation sets back to defaults. |
| 949 | */ |
| 950 | autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC); |
| 951 | autoc2 = IXGBE_READ_REG(hw, IXGBE_AUTOC2); |
| 952 | if (hw->mac.orig_link_settings_stored == false) { |
| 953 | hw->mac.orig_autoc = autoc; |
| 954 | hw->mac.orig_autoc2 = autoc2; |
| 955 | hw->mac.orig_link_settings_stored = true; |
Jesse Brandeburg | 4df1046 | 2009-03-13 22:15:31 +0000 | [diff] [blame] | 956 | } else { |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 957 | if (autoc != hw->mac.orig_autoc) |
| 958 | IXGBE_WRITE_REG(hw, IXGBE_AUTOC, (hw->mac.orig_autoc | |
| 959 | IXGBE_AUTOC_AN_RESTART)); |
| 960 | |
| 961 | if ((autoc2 & IXGBE_AUTOC2_UPPER_MASK) != |
| 962 | (hw->mac.orig_autoc2 & IXGBE_AUTOC2_UPPER_MASK)) { |
| 963 | autoc2 &= ~IXGBE_AUTOC2_UPPER_MASK; |
| 964 | autoc2 |= (hw->mac.orig_autoc2 & |
| 965 | IXGBE_AUTOC2_UPPER_MASK); |
| 966 | IXGBE_WRITE_REG(hw, IXGBE_AUTOC2, autoc2); |
| 967 | } |
| 968 | } |
| 969 | |
Waskiewicz Jr, Peter P | aca6bee | 2009-05-17 12:32:48 +0000 | [diff] [blame] | 970 | /* |
| 971 | * Store MAC address from RAR0, clear receive address registers, and |
| 972 | * clear the multicast table. Also reset num_rar_entries to 128, |
| 973 | * since we modify this value when programming the SAN MAC address. |
| 974 | */ |
| 975 | hw->mac.num_rar_entries = 128; |
| 976 | hw->mac.ops.init_rx_addrs(hw); |
| 977 | |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 978 | /* Store the permanent mac address */ |
| 979 | hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr); |
| 980 | |
PJ Waskiewicz | 0365e6e | 2009-05-17 12:32:25 +0000 | [diff] [blame] | 981 | /* Store the permanent SAN mac address */ |
| 982 | hw->mac.ops.get_san_mac_addr(hw, hw->mac.san_addr); |
| 983 | |
Waskiewicz Jr, Peter P | aca6bee | 2009-05-17 12:32:48 +0000 | [diff] [blame] | 984 | /* Add the SAN MAC address to the RAR only if it's a valid address */ |
| 985 | if (ixgbe_validate_mac_addr(hw->mac.san_addr) == 0) { |
| 986 | hw->mac.ops.set_rar(hw, hw->mac.num_rar_entries - 1, |
| 987 | hw->mac.san_addr, 0, IXGBE_RAH_AV); |
| 988 | |
| 989 | /* Reserve the last RAR for the SAN MAC address */ |
| 990 | hw->mac.num_rar_entries--; |
| 991 | } |
| 992 | |
Yi Zou | 383ff34 | 2009-10-28 18:23:57 +0000 | [diff] [blame] | 993 | /* Store the alternative WWNN/WWPN prefix */ |
| 994 | hw->mac.ops.get_wwn_prefix(hw, &hw->mac.wwnn_prefix, |
| 995 | &hw->mac.wwpn_prefix); |
| 996 | |
PJ Waskiewicz | 04f165e | 2009-04-09 22:27:57 +0000 | [diff] [blame] | 997 | reset_hw_out: |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 998 | return status; |
| 999 | } |
| 1000 | |
| 1001 | /** |
Peter P Waskiewicz Jr | ffff477 | 2009-06-04 16:01:25 +0000 | [diff] [blame] | 1002 | * ixgbe_reinit_fdir_tables_82599 - Reinitialize Flow Director tables. |
| 1003 | * @hw: pointer to hardware structure |
| 1004 | **/ |
| 1005 | s32 ixgbe_reinit_fdir_tables_82599(struct ixgbe_hw *hw) |
| 1006 | { |
| 1007 | int i; |
| 1008 | u32 fdirctrl = IXGBE_READ_REG(hw, IXGBE_FDIRCTRL); |
| 1009 | fdirctrl &= ~IXGBE_FDIRCTRL_INIT_DONE; |
| 1010 | |
| 1011 | /* |
| 1012 | * Before starting reinitialization process, |
| 1013 | * FDIRCMD.CMD must be zero. |
| 1014 | */ |
| 1015 | for (i = 0; i < IXGBE_FDIRCMD_CMD_POLL; i++) { |
| 1016 | if (!(IXGBE_READ_REG(hw, IXGBE_FDIRCMD) & |
| 1017 | IXGBE_FDIRCMD_CMD_MASK)) |
| 1018 | break; |
| 1019 | udelay(10); |
| 1020 | } |
| 1021 | if (i >= IXGBE_FDIRCMD_CMD_POLL) { |
Alexander Duyck | 905e4a4 | 2011-01-06 14:29:57 +0000 | [diff] [blame] | 1022 | hw_dbg(hw, "Flow Director previous command isn't complete, " |
Frans Pop | d6dbee8 | 2010-03-24 07:57:35 +0000 | [diff] [blame] | 1023 | "aborting table re-initialization.\n"); |
Peter P Waskiewicz Jr | ffff477 | 2009-06-04 16:01:25 +0000 | [diff] [blame] | 1024 | return IXGBE_ERR_FDIR_REINIT_FAILED; |
| 1025 | } |
| 1026 | |
| 1027 | IXGBE_WRITE_REG(hw, IXGBE_FDIRFREE, 0); |
| 1028 | IXGBE_WRITE_FLUSH(hw); |
| 1029 | /* |
| 1030 | * 82599 adapters flow director init flow cannot be restarted, |
| 1031 | * Workaround 82599 silicon errata by performing the following steps |
| 1032 | * before re-writing the FDIRCTRL control register with the same value. |
| 1033 | * - write 1 to bit 8 of FDIRCMD register & |
| 1034 | * - write 0 to bit 8 of FDIRCMD register |
| 1035 | */ |
| 1036 | IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD, |
| 1037 | (IXGBE_READ_REG(hw, IXGBE_FDIRCMD) | |
| 1038 | IXGBE_FDIRCMD_CLEARHT)); |
| 1039 | IXGBE_WRITE_FLUSH(hw); |
| 1040 | IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD, |
| 1041 | (IXGBE_READ_REG(hw, IXGBE_FDIRCMD) & |
| 1042 | ~IXGBE_FDIRCMD_CLEARHT)); |
| 1043 | IXGBE_WRITE_FLUSH(hw); |
| 1044 | /* |
| 1045 | * Clear FDIR Hash register to clear any leftover hashes |
| 1046 | * waiting to be programmed. |
| 1047 | */ |
| 1048 | IXGBE_WRITE_REG(hw, IXGBE_FDIRHASH, 0x00); |
| 1049 | IXGBE_WRITE_FLUSH(hw); |
| 1050 | |
| 1051 | IXGBE_WRITE_REG(hw, IXGBE_FDIRCTRL, fdirctrl); |
| 1052 | IXGBE_WRITE_FLUSH(hw); |
| 1053 | |
| 1054 | /* Poll init-done after we write FDIRCTRL register */ |
| 1055 | for (i = 0; i < IXGBE_FDIR_INIT_DONE_POLL; i++) { |
| 1056 | if (IXGBE_READ_REG(hw, IXGBE_FDIRCTRL) & |
| 1057 | IXGBE_FDIRCTRL_INIT_DONE) |
| 1058 | break; |
| 1059 | udelay(10); |
| 1060 | } |
| 1061 | if (i >= IXGBE_FDIR_INIT_DONE_POLL) { |
| 1062 | hw_dbg(hw, "Flow Director Signature poll time exceeded!\n"); |
| 1063 | return IXGBE_ERR_FDIR_REINIT_FAILED; |
| 1064 | } |
| 1065 | |
| 1066 | /* Clear FDIR statistics registers (read to clear) */ |
| 1067 | IXGBE_READ_REG(hw, IXGBE_FDIRUSTAT); |
| 1068 | IXGBE_READ_REG(hw, IXGBE_FDIRFSTAT); |
| 1069 | IXGBE_READ_REG(hw, IXGBE_FDIRMATCH); |
| 1070 | IXGBE_READ_REG(hw, IXGBE_FDIRMISS); |
| 1071 | IXGBE_READ_REG(hw, IXGBE_FDIRLEN); |
| 1072 | |
| 1073 | return 0; |
| 1074 | } |
| 1075 | |
| 1076 | /** |
| 1077 | * ixgbe_init_fdir_signature_82599 - Initialize Flow Director signature filters |
| 1078 | * @hw: pointer to hardware structure |
| 1079 | * @pballoc: which mode to allocate filters with |
| 1080 | **/ |
| 1081 | s32 ixgbe_init_fdir_signature_82599(struct ixgbe_hw *hw, u32 pballoc) |
| 1082 | { |
| 1083 | u32 fdirctrl = 0; |
| 1084 | u32 pbsize; |
| 1085 | int i; |
| 1086 | |
| 1087 | /* |
| 1088 | * Before enabling Flow Director, the Rx Packet Buffer size |
| 1089 | * must be reduced. The new value is the current size minus |
| 1090 | * flow director memory usage size. |
| 1091 | */ |
| 1092 | pbsize = (1 << (IXGBE_FDIR_PBALLOC_SIZE_SHIFT + pballoc)); |
| 1093 | IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(0), |
| 1094 | (IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(0)) - pbsize)); |
| 1095 | |
| 1096 | /* |
| 1097 | * The defaults in the HW for RX PB 1-7 are not zero and so should be |
Uwe Kleine-König | b595076 | 2010-11-01 15:38:34 -0400 | [diff] [blame] | 1098 | * initialized to zero for non DCB mode otherwise actual total RX PB |
Peter P Waskiewicz Jr | ffff477 | 2009-06-04 16:01:25 +0000 | [diff] [blame] | 1099 | * would be bigger than programmed and filter space would run into |
| 1100 | * the PB 0 region. |
| 1101 | */ |
| 1102 | for (i = 1; i < 8; i++) |
| 1103 | IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), 0); |
| 1104 | |
| 1105 | /* Send interrupt when 64 filters are left */ |
| 1106 | fdirctrl |= 4 << IXGBE_FDIRCTRL_FULL_THRESH_SHIFT; |
| 1107 | |
| 1108 | /* Set the maximum length per hash bucket to 0xA filters */ |
| 1109 | fdirctrl |= 0xA << IXGBE_FDIRCTRL_MAX_LENGTH_SHIFT; |
| 1110 | |
| 1111 | switch (pballoc) { |
| 1112 | case IXGBE_FDIR_PBALLOC_64K: |
| 1113 | /* 8k - 1 signature filters */ |
| 1114 | fdirctrl |= IXGBE_FDIRCTRL_PBALLOC_64K; |
| 1115 | break; |
| 1116 | case IXGBE_FDIR_PBALLOC_128K: |
| 1117 | /* 16k - 1 signature filters */ |
| 1118 | fdirctrl |= IXGBE_FDIRCTRL_PBALLOC_128K; |
| 1119 | break; |
| 1120 | case IXGBE_FDIR_PBALLOC_256K: |
| 1121 | /* 32k - 1 signature filters */ |
| 1122 | fdirctrl |= IXGBE_FDIRCTRL_PBALLOC_256K; |
| 1123 | break; |
| 1124 | default: |
| 1125 | /* bad value */ |
| 1126 | return IXGBE_ERR_CONFIG; |
| 1127 | }; |
| 1128 | |
| 1129 | /* Move the flexible bytes to use the ethertype - shift 6 words */ |
| 1130 | fdirctrl |= (0x6 << IXGBE_FDIRCTRL_FLEX_SHIFT); |
| 1131 | |
Peter P Waskiewicz Jr | ffff477 | 2009-06-04 16:01:25 +0000 | [diff] [blame] | 1132 | |
| 1133 | /* Prime the keys for hashing */ |
Alexander Duyck | 905e4a4 | 2011-01-06 14:29:57 +0000 | [diff] [blame] | 1134 | IXGBE_WRITE_REG(hw, IXGBE_FDIRHKEY, IXGBE_ATR_BUCKET_HASH_KEY); |
| 1135 | IXGBE_WRITE_REG(hw, IXGBE_FDIRSKEY, IXGBE_ATR_SIGNATURE_HASH_KEY); |
Peter P Waskiewicz Jr | ffff477 | 2009-06-04 16:01:25 +0000 | [diff] [blame] | 1136 | |
| 1137 | /* |
| 1138 | * Poll init-done after we write the register. Estimated times: |
| 1139 | * 10G: PBALLOC = 11b, timing is 60us |
| 1140 | * 1G: PBALLOC = 11b, timing is 600us |
| 1141 | * 100M: PBALLOC = 11b, timing is 6ms |
| 1142 | * |
| 1143 | * Multiple these timings by 4 if under full Rx load |
| 1144 | * |
| 1145 | * So we'll poll for IXGBE_FDIR_INIT_DONE_POLL times, sleeping for |
| 1146 | * 1 msec per poll time. If we're at line rate and drop to 100M, then |
| 1147 | * this might not finish in our poll time, but we can live with that |
| 1148 | * for now. |
| 1149 | */ |
| 1150 | IXGBE_WRITE_REG(hw, IXGBE_FDIRCTRL, fdirctrl); |
| 1151 | IXGBE_WRITE_FLUSH(hw); |
| 1152 | for (i = 0; i < IXGBE_FDIR_INIT_DONE_POLL; i++) { |
| 1153 | if (IXGBE_READ_REG(hw, IXGBE_FDIRCTRL) & |
| 1154 | IXGBE_FDIRCTRL_INIT_DONE) |
| 1155 | break; |
| 1156 | msleep(1); |
| 1157 | } |
| 1158 | if (i >= IXGBE_FDIR_INIT_DONE_POLL) |
| 1159 | hw_dbg(hw, "Flow Director Signature poll time exceeded!\n"); |
| 1160 | |
| 1161 | return 0; |
| 1162 | } |
| 1163 | |
| 1164 | /** |
| 1165 | * ixgbe_init_fdir_perfect_82599 - Initialize Flow Director perfect filters |
| 1166 | * @hw: pointer to hardware structure |
| 1167 | * @pballoc: which mode to allocate filters with |
| 1168 | **/ |
| 1169 | s32 ixgbe_init_fdir_perfect_82599(struct ixgbe_hw *hw, u32 pballoc) |
| 1170 | { |
| 1171 | u32 fdirctrl = 0; |
| 1172 | u32 pbsize; |
| 1173 | int i; |
| 1174 | |
| 1175 | /* |
| 1176 | * Before enabling Flow Director, the Rx Packet Buffer size |
| 1177 | * must be reduced. The new value is the current size minus |
| 1178 | * flow director memory usage size. |
| 1179 | */ |
| 1180 | pbsize = (1 << (IXGBE_FDIR_PBALLOC_SIZE_SHIFT + pballoc)); |
| 1181 | IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(0), |
| 1182 | (IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(0)) - pbsize)); |
| 1183 | |
| 1184 | /* |
| 1185 | * The defaults in the HW for RX PB 1-7 are not zero and so should be |
Uwe Kleine-König | b595076 | 2010-11-01 15:38:34 -0400 | [diff] [blame] | 1186 | * initialized to zero for non DCB mode otherwise actual total RX PB |
Peter P Waskiewicz Jr | ffff477 | 2009-06-04 16:01:25 +0000 | [diff] [blame] | 1187 | * would be bigger than programmed and filter space would run into |
| 1188 | * the PB 0 region. |
| 1189 | */ |
| 1190 | for (i = 1; i < 8; i++) |
| 1191 | IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), 0); |
| 1192 | |
| 1193 | /* Send interrupt when 64 filters are left */ |
| 1194 | fdirctrl |= 4 << IXGBE_FDIRCTRL_FULL_THRESH_SHIFT; |
| 1195 | |
Peter Waskiewicz | 9a713e7 | 2010-02-10 16:07:54 +0000 | [diff] [blame] | 1196 | /* Initialize the drop queue to Rx queue 127 */ |
| 1197 | fdirctrl |= (127 << IXGBE_FDIRCTRL_DROP_Q_SHIFT); |
| 1198 | |
Peter P Waskiewicz Jr | ffff477 | 2009-06-04 16:01:25 +0000 | [diff] [blame] | 1199 | switch (pballoc) { |
| 1200 | case IXGBE_FDIR_PBALLOC_64K: |
| 1201 | /* 2k - 1 perfect filters */ |
| 1202 | fdirctrl |= IXGBE_FDIRCTRL_PBALLOC_64K; |
| 1203 | break; |
| 1204 | case IXGBE_FDIR_PBALLOC_128K: |
| 1205 | /* 4k - 1 perfect filters */ |
| 1206 | fdirctrl |= IXGBE_FDIRCTRL_PBALLOC_128K; |
| 1207 | break; |
| 1208 | case IXGBE_FDIR_PBALLOC_256K: |
| 1209 | /* 8k - 1 perfect filters */ |
| 1210 | fdirctrl |= IXGBE_FDIRCTRL_PBALLOC_256K; |
| 1211 | break; |
| 1212 | default: |
| 1213 | /* bad value */ |
| 1214 | return IXGBE_ERR_CONFIG; |
| 1215 | }; |
| 1216 | |
| 1217 | /* Turn perfect match filtering on */ |
| 1218 | fdirctrl |= IXGBE_FDIRCTRL_PERFECT_MATCH; |
| 1219 | fdirctrl |= IXGBE_FDIRCTRL_REPORT_STATUS; |
| 1220 | |
| 1221 | /* Move the flexible bytes to use the ethertype - shift 6 words */ |
| 1222 | fdirctrl |= (0x6 << IXGBE_FDIRCTRL_FLEX_SHIFT); |
| 1223 | |
| 1224 | /* Prime the keys for hashing */ |
Alexander Duyck | 905e4a4 | 2011-01-06 14:29:57 +0000 | [diff] [blame] | 1225 | IXGBE_WRITE_REG(hw, IXGBE_FDIRHKEY, IXGBE_ATR_BUCKET_HASH_KEY); |
| 1226 | IXGBE_WRITE_REG(hw, IXGBE_FDIRSKEY, IXGBE_ATR_SIGNATURE_HASH_KEY); |
Peter P Waskiewicz Jr | ffff477 | 2009-06-04 16:01:25 +0000 | [diff] [blame] | 1227 | |
| 1228 | /* |
| 1229 | * Poll init-done after we write the register. Estimated times: |
| 1230 | * 10G: PBALLOC = 11b, timing is 60us |
| 1231 | * 1G: PBALLOC = 11b, timing is 600us |
| 1232 | * 100M: PBALLOC = 11b, timing is 6ms |
| 1233 | * |
| 1234 | * Multiple these timings by 4 if under full Rx load |
| 1235 | * |
| 1236 | * So we'll poll for IXGBE_FDIR_INIT_DONE_POLL times, sleeping for |
| 1237 | * 1 msec per poll time. If we're at line rate and drop to 100M, then |
| 1238 | * this might not finish in our poll time, but we can live with that |
| 1239 | * for now. |
| 1240 | */ |
| 1241 | |
| 1242 | /* Set the maximum length per hash bucket to 0xA filters */ |
| 1243 | fdirctrl |= (0xA << IXGBE_FDIRCTRL_MAX_LENGTH_SHIFT); |
| 1244 | |
| 1245 | IXGBE_WRITE_REG(hw, IXGBE_FDIRCTRL, fdirctrl); |
| 1246 | IXGBE_WRITE_FLUSH(hw); |
| 1247 | for (i = 0; i < IXGBE_FDIR_INIT_DONE_POLL; i++) { |
| 1248 | if (IXGBE_READ_REG(hw, IXGBE_FDIRCTRL) & |
| 1249 | IXGBE_FDIRCTRL_INIT_DONE) |
| 1250 | break; |
| 1251 | msleep(1); |
| 1252 | } |
| 1253 | if (i >= IXGBE_FDIR_INIT_DONE_POLL) |
| 1254 | hw_dbg(hw, "Flow Director Perfect poll time exceeded!\n"); |
| 1255 | |
| 1256 | return 0; |
| 1257 | } |
| 1258 | |
| 1259 | |
| 1260 | /** |
| 1261 | * ixgbe_atr_compute_hash_82599 - Compute the hashes for SW ATR |
| 1262 | * @stream: input bitstream to compute the hash on |
| 1263 | * @key: 32-bit hash key |
| 1264 | **/ |
Alexander Duyck | 905e4a4 | 2011-01-06 14:29:57 +0000 | [diff] [blame] | 1265 | static u32 ixgbe_atr_compute_hash_82599(union ixgbe_atr_input *atr_input, |
| 1266 | u32 key) |
Peter P Waskiewicz Jr | ffff477 | 2009-06-04 16:01:25 +0000 | [diff] [blame] | 1267 | { |
| 1268 | /* |
| 1269 | * The algorithm is as follows: |
| 1270 | * Hash[15:0] = Sum { S[n] x K[n+16] }, n = 0...350 |
| 1271 | * where Sum {A[n]}, n = 0...n is bitwise XOR of A[0], A[1]...A[n] |
| 1272 | * and A[n] x B[n] is bitwise AND between same length strings |
| 1273 | * |
| 1274 | * K[n] is 16 bits, defined as: |
| 1275 | * for n modulo 32 >= 15, K[n] = K[n % 32 : (n % 32) - 15] |
| 1276 | * for n modulo 32 < 15, K[n] = |
| 1277 | * K[(n % 32:0) | (31:31 - (14 - (n % 32)))] |
| 1278 | * |
| 1279 | * S[n] is 16 bits, defined as: |
| 1280 | * for n >= 15, S[n] = S[n:n - 15] |
| 1281 | * for n < 15, S[n] = S[(n:0) | (350:350 - (14 - n))] |
| 1282 | * |
| 1283 | * To simplify for programming, the algorithm is implemented |
| 1284 | * in software this way: |
| 1285 | * |
Alexander Duyck | 905e4a4 | 2011-01-06 14:29:57 +0000 | [diff] [blame] | 1286 | * key[31:0], hi_hash_dword[31:0], lo_hash_dword[31:0], hash[15:0] |
Peter P Waskiewicz Jr | ffff477 | 2009-06-04 16:01:25 +0000 | [diff] [blame] | 1287 | * |
Alexander Duyck | 905e4a4 | 2011-01-06 14:29:57 +0000 | [diff] [blame] | 1288 | * for (i = 0; i < 352; i+=32) |
| 1289 | * hi_hash_dword[31:0] ^= Stream[(i+31):i]; |
Peter P Waskiewicz Jr | ffff477 | 2009-06-04 16:01:25 +0000 | [diff] [blame] | 1290 | * |
Alexander Duyck | 905e4a4 | 2011-01-06 14:29:57 +0000 | [diff] [blame] | 1291 | * lo_hash_dword[15:0] ^= Stream[15:0]; |
| 1292 | * lo_hash_dword[15:0] ^= hi_hash_dword[31:16]; |
| 1293 | * lo_hash_dword[31:16] ^= hi_hash_dword[15:0]; |
| 1294 | * |
| 1295 | * hi_hash_dword[31:0] ^= Stream[351:320]; |
| 1296 | * |
| 1297 | * if(key[0]) |
| 1298 | * hash[15:0] ^= Stream[15:0]; |
| 1299 | * |
| 1300 | * for (i = 0; i < 16; i++) { |
| 1301 | * if (key[i]) |
| 1302 | * hash[15:0] ^= lo_hash_dword[(i+15):i]; |
| 1303 | * if (key[i + 16]) |
| 1304 | * hash[15:0] ^= hi_hash_dword[(i+15):i]; |
Peter P Waskiewicz Jr | ffff477 | 2009-06-04 16:01:25 +0000 | [diff] [blame] | 1305 | * } |
Alexander Duyck | 905e4a4 | 2011-01-06 14:29:57 +0000 | [diff] [blame] | 1306 | * |
Peter P Waskiewicz Jr | ffff477 | 2009-06-04 16:01:25 +0000 | [diff] [blame] | 1307 | */ |
Alexander Duyck | 905e4a4 | 2011-01-06 14:29:57 +0000 | [diff] [blame] | 1308 | __be32 common_hash_dword = 0; |
| 1309 | u32 hi_hash_dword, lo_hash_dword, flow_vm_vlan; |
| 1310 | u32 hash_result = 0; |
| 1311 | u8 i; |
Peter P Waskiewicz Jr | ffff477 | 2009-06-04 16:01:25 +0000 | [diff] [blame] | 1312 | |
Alexander Duyck | 905e4a4 | 2011-01-06 14:29:57 +0000 | [diff] [blame] | 1313 | /* record the flow_vm_vlan bits as they are a key part to the hash */ |
| 1314 | flow_vm_vlan = ntohl(atr_input->dword_stream[0]); |
Peter P Waskiewicz Jr | ffff477 | 2009-06-04 16:01:25 +0000 | [diff] [blame] | 1315 | |
Alexander Duyck | 905e4a4 | 2011-01-06 14:29:57 +0000 | [diff] [blame] | 1316 | /* generate common hash dword */ |
| 1317 | for (i = 10; i; i -= 2) |
| 1318 | common_hash_dword ^= atr_input->dword_stream[i] ^ |
| 1319 | atr_input->dword_stream[i - 1]; |
| 1320 | |
| 1321 | hi_hash_dword = ntohl(common_hash_dword); |
| 1322 | |
| 1323 | /* low dword is word swapped version of common */ |
| 1324 | lo_hash_dword = (hi_hash_dword >> 16) | (hi_hash_dword << 16); |
| 1325 | |
| 1326 | /* apply flow ID/VM pool/VLAN ID bits to hash words */ |
| 1327 | hi_hash_dword ^= flow_vm_vlan ^ (flow_vm_vlan >> 16); |
| 1328 | |
| 1329 | /* Process bits 0 and 16 */ |
| 1330 | if (key & 0x0001) hash_result ^= lo_hash_dword; |
| 1331 | if (key & 0x00010000) hash_result ^= hi_hash_dword; |
Peter P Waskiewicz Jr | ffff477 | 2009-06-04 16:01:25 +0000 | [diff] [blame] | 1332 | |
| 1333 | /* |
Alexander Duyck | 905e4a4 | 2011-01-06 14:29:57 +0000 | [diff] [blame] | 1334 | * apply flow ID/VM pool/VLAN ID bits to lo hash dword, we had to |
| 1335 | * delay this because bit 0 of the stream should not be processed |
| 1336 | * so we do not add the vlan until after bit 0 was processed |
Peter P Waskiewicz Jr | ffff477 | 2009-06-04 16:01:25 +0000 | [diff] [blame] | 1337 | */ |
Alexander Duyck | 905e4a4 | 2011-01-06 14:29:57 +0000 | [diff] [blame] | 1338 | lo_hash_dword ^= flow_vm_vlan ^ (flow_vm_vlan << 16); |
Peter P Waskiewicz Jr | ffff477 | 2009-06-04 16:01:25 +0000 | [diff] [blame] | 1339 | |
Alexander Duyck | 905e4a4 | 2011-01-06 14:29:57 +0000 | [diff] [blame] | 1340 | |
| 1341 | /* process the remaining 30 bits in the key 2 bits at a time */ |
| 1342 | for (i = 15; i; i-- ) { |
| 1343 | if (key & (0x0001 << i)) hash_result ^= lo_hash_dword >> i; |
| 1344 | if (key & (0x00010000 << i)) hash_result ^= hi_hash_dword >> i; |
Peter P Waskiewicz Jr | ffff477 | 2009-06-04 16:01:25 +0000 | [diff] [blame] | 1345 | } |
| 1346 | |
Alexander Duyck | 905e4a4 | 2011-01-06 14:29:57 +0000 | [diff] [blame] | 1347 | return hash_result & IXGBE_ATR_HASH_MASK; |
Peter P Waskiewicz Jr | ffff477 | 2009-06-04 16:01:25 +0000 | [diff] [blame] | 1348 | } |
| 1349 | |
Alexander Duyck | 6983052 | 2011-01-06 14:29:58 +0000 | [diff] [blame] | 1350 | /* |
| 1351 | * These defines allow us to quickly generate all of the necessary instructions |
| 1352 | * in the function below by simply calling out IXGBE_COMPUTE_SIG_HASH_ITERATION |
| 1353 | * for values 0 through 15 |
| 1354 | */ |
| 1355 | #define IXGBE_ATR_COMMON_HASH_KEY \ |
| 1356 | (IXGBE_ATR_BUCKET_HASH_KEY & IXGBE_ATR_SIGNATURE_HASH_KEY) |
| 1357 | #define IXGBE_COMPUTE_SIG_HASH_ITERATION(_n) \ |
| 1358 | do { \ |
| 1359 | u32 n = (_n); \ |
| 1360 | if (IXGBE_ATR_COMMON_HASH_KEY & (0x01 << n)) \ |
| 1361 | common_hash ^= lo_hash_dword >> n; \ |
| 1362 | else if (IXGBE_ATR_BUCKET_HASH_KEY & (0x01 << n)) \ |
| 1363 | bucket_hash ^= lo_hash_dword >> n; \ |
| 1364 | else if (IXGBE_ATR_SIGNATURE_HASH_KEY & (0x01 << n)) \ |
| 1365 | sig_hash ^= lo_hash_dword << (16 - n); \ |
| 1366 | if (IXGBE_ATR_COMMON_HASH_KEY & (0x01 << (n + 16))) \ |
| 1367 | common_hash ^= hi_hash_dword >> n; \ |
| 1368 | else if (IXGBE_ATR_BUCKET_HASH_KEY & (0x01 << (n + 16))) \ |
| 1369 | bucket_hash ^= hi_hash_dword >> n; \ |
| 1370 | else if (IXGBE_ATR_SIGNATURE_HASH_KEY & (0x01 << (n + 16))) \ |
| 1371 | sig_hash ^= hi_hash_dword << (16 - n); \ |
| 1372 | } while (0); |
| 1373 | |
| 1374 | /** |
| 1375 | * ixgbe_atr_compute_sig_hash_82599 - Compute the signature hash |
| 1376 | * @stream: input bitstream to compute the hash on |
| 1377 | * |
| 1378 | * This function is almost identical to the function above but contains |
| 1379 | * several optomizations such as unwinding all of the loops, letting the |
| 1380 | * compiler work out all of the conditional ifs since the keys are static |
| 1381 | * defines, and computing two keys at once since the hashed dword stream |
| 1382 | * will be the same for both keys. |
| 1383 | **/ |
| 1384 | static u32 ixgbe_atr_compute_sig_hash_82599(union ixgbe_atr_hash_dword input, |
| 1385 | union ixgbe_atr_hash_dword common) |
| 1386 | { |
| 1387 | u32 hi_hash_dword, lo_hash_dword, flow_vm_vlan; |
| 1388 | u32 sig_hash = 0, bucket_hash = 0, common_hash = 0; |
| 1389 | |
| 1390 | /* record the flow_vm_vlan bits as they are a key part to the hash */ |
| 1391 | flow_vm_vlan = ntohl(input.dword); |
| 1392 | |
| 1393 | /* generate common hash dword */ |
| 1394 | hi_hash_dword = ntohl(common.dword); |
| 1395 | |
| 1396 | /* low dword is word swapped version of common */ |
| 1397 | lo_hash_dword = (hi_hash_dword >> 16) | (hi_hash_dword << 16); |
| 1398 | |
| 1399 | /* apply flow ID/VM pool/VLAN ID bits to hash words */ |
| 1400 | hi_hash_dword ^= flow_vm_vlan ^ (flow_vm_vlan >> 16); |
| 1401 | |
| 1402 | /* Process bits 0 and 16 */ |
| 1403 | IXGBE_COMPUTE_SIG_HASH_ITERATION(0); |
| 1404 | |
| 1405 | /* |
| 1406 | * apply flow ID/VM pool/VLAN ID bits to lo hash dword, we had to |
| 1407 | * delay this because bit 0 of the stream should not be processed |
| 1408 | * so we do not add the vlan until after bit 0 was processed |
| 1409 | */ |
| 1410 | lo_hash_dword ^= flow_vm_vlan ^ (flow_vm_vlan << 16); |
| 1411 | |
| 1412 | /* Process remaining 30 bit of the key */ |
| 1413 | IXGBE_COMPUTE_SIG_HASH_ITERATION(1); |
| 1414 | IXGBE_COMPUTE_SIG_HASH_ITERATION(2); |
| 1415 | IXGBE_COMPUTE_SIG_HASH_ITERATION(3); |
| 1416 | IXGBE_COMPUTE_SIG_HASH_ITERATION(4); |
| 1417 | IXGBE_COMPUTE_SIG_HASH_ITERATION(5); |
| 1418 | IXGBE_COMPUTE_SIG_HASH_ITERATION(6); |
| 1419 | IXGBE_COMPUTE_SIG_HASH_ITERATION(7); |
| 1420 | IXGBE_COMPUTE_SIG_HASH_ITERATION(8); |
| 1421 | IXGBE_COMPUTE_SIG_HASH_ITERATION(9); |
| 1422 | IXGBE_COMPUTE_SIG_HASH_ITERATION(10); |
| 1423 | IXGBE_COMPUTE_SIG_HASH_ITERATION(11); |
| 1424 | IXGBE_COMPUTE_SIG_HASH_ITERATION(12); |
| 1425 | IXGBE_COMPUTE_SIG_HASH_ITERATION(13); |
| 1426 | IXGBE_COMPUTE_SIG_HASH_ITERATION(14); |
| 1427 | IXGBE_COMPUTE_SIG_HASH_ITERATION(15); |
| 1428 | |
| 1429 | /* combine common_hash result with signature and bucket hashes */ |
| 1430 | bucket_hash ^= common_hash; |
| 1431 | bucket_hash &= IXGBE_ATR_HASH_MASK; |
| 1432 | |
| 1433 | sig_hash ^= common_hash << 16; |
| 1434 | sig_hash &= IXGBE_ATR_HASH_MASK << 16; |
| 1435 | |
| 1436 | /* return completed signature hash */ |
| 1437 | return sig_hash ^ bucket_hash; |
| 1438 | } |
| 1439 | |
Peter P Waskiewicz Jr | ffff477 | 2009-06-04 16:01:25 +0000 | [diff] [blame] | 1440 | /** |
Peter P Waskiewicz Jr | ffff477 | 2009-06-04 16:01:25 +0000 | [diff] [blame] | 1441 | * ixgbe_atr_add_signature_filter_82599 - Adds a signature hash filter |
| 1442 | * @hw: pointer to hardware structure |
Alexander Duyck | 6983052 | 2011-01-06 14:29:58 +0000 | [diff] [blame] | 1443 | * @input: unique input dword |
| 1444 | * @common: compressed common input dword |
Peter P Waskiewicz Jr | ffff477 | 2009-06-04 16:01:25 +0000 | [diff] [blame] | 1445 | * @queue: queue index to direct traffic to |
| 1446 | **/ |
| 1447 | s32 ixgbe_fdir_add_signature_filter_82599(struct ixgbe_hw *hw, |
Alexander Duyck | 6983052 | 2011-01-06 14:29:58 +0000 | [diff] [blame] | 1448 | union ixgbe_atr_hash_dword input, |
| 1449 | union ixgbe_atr_hash_dword common, |
Peter P Waskiewicz Jr | ffff477 | 2009-06-04 16:01:25 +0000 | [diff] [blame] | 1450 | u8 queue) |
| 1451 | { |
| 1452 | u64 fdirhashcmd; |
Alexander Duyck | 905e4a4 | 2011-01-06 14:29:57 +0000 | [diff] [blame] | 1453 | u32 fdircmd; |
Peter P Waskiewicz Jr | ffff477 | 2009-06-04 16:01:25 +0000 | [diff] [blame] | 1454 | |
Alexander Duyck | 905e4a4 | 2011-01-06 14:29:57 +0000 | [diff] [blame] | 1455 | /* |
| 1456 | * Get the flow_type in order to program FDIRCMD properly |
| 1457 | * lowest 2 bits are FDIRCMD.L4TYPE, third lowest bit is FDIRCMD.IPV6 |
| 1458 | */ |
Alexander Duyck | 6983052 | 2011-01-06 14:29:58 +0000 | [diff] [blame] | 1459 | switch (input.formatted.flow_type) { |
Alexander Duyck | 905e4a4 | 2011-01-06 14:29:57 +0000 | [diff] [blame] | 1460 | case IXGBE_ATR_FLOW_TYPE_TCPV4: |
| 1461 | case IXGBE_ATR_FLOW_TYPE_UDPV4: |
| 1462 | case IXGBE_ATR_FLOW_TYPE_SCTPV4: |
| 1463 | case IXGBE_ATR_FLOW_TYPE_TCPV6: |
| 1464 | case IXGBE_ATR_FLOW_TYPE_UDPV6: |
| 1465 | case IXGBE_ATR_FLOW_TYPE_SCTPV6: |
| 1466 | break; |
| 1467 | default: |
| 1468 | hw_dbg(hw, " Error on flow type input\n"); |
| 1469 | return IXGBE_ERR_CONFIG; |
| 1470 | } |
Peter P Waskiewicz Jr | ffff477 | 2009-06-04 16:01:25 +0000 | [diff] [blame] | 1471 | |
Alexander Duyck | 905e4a4 | 2011-01-06 14:29:57 +0000 | [diff] [blame] | 1472 | /* configure FDIRCMD register */ |
| 1473 | fdircmd = IXGBE_FDIRCMD_CMD_ADD_FLOW | IXGBE_FDIRCMD_FILTER_UPDATE | |
| 1474 | IXGBE_FDIRCMD_LAST | IXGBE_FDIRCMD_QUEUE_EN; |
Alexander Duyck | 6983052 | 2011-01-06 14:29:58 +0000 | [diff] [blame] | 1475 | fdircmd |= input.formatted.flow_type << IXGBE_FDIRCMD_FLOW_TYPE_SHIFT; |
Alexander Duyck | 905e4a4 | 2011-01-06 14:29:57 +0000 | [diff] [blame] | 1476 | fdircmd |= (u32)queue << IXGBE_FDIRCMD_RX_QUEUE_SHIFT; |
Peter P Waskiewicz Jr | ffff477 | 2009-06-04 16:01:25 +0000 | [diff] [blame] | 1477 | |
| 1478 | /* |
| 1479 | * The lower 32-bits of fdirhashcmd is for FDIRHASH, the upper 32-bits |
| 1480 | * is for FDIRCMD. Then do a 64-bit register write from FDIRHASH. |
| 1481 | */ |
Alexander Duyck | 905e4a4 | 2011-01-06 14:29:57 +0000 | [diff] [blame] | 1482 | fdirhashcmd = (u64)fdircmd << 32; |
Alexander Duyck | 6983052 | 2011-01-06 14:29:58 +0000 | [diff] [blame] | 1483 | fdirhashcmd |= ixgbe_atr_compute_sig_hash_82599(input, common); |
Peter P Waskiewicz Jr | ffff477 | 2009-06-04 16:01:25 +0000 | [diff] [blame] | 1484 | |
| 1485 | IXGBE_WRITE_REG64(hw, IXGBE_FDIRHASH, fdirhashcmd); |
| 1486 | |
Alexander Duyck | 6983052 | 2011-01-06 14:29:58 +0000 | [diff] [blame] | 1487 | hw_dbg(hw, "Tx Queue=%x hash=%x\n", queue, (u32)fdirhashcmd); |
| 1488 | |
Peter P Waskiewicz Jr | ffff477 | 2009-06-04 16:01:25 +0000 | [diff] [blame] | 1489 | return 0; |
| 1490 | } |
| 1491 | |
| 1492 | /** |
Alexander Duyck | 45b9f50 | 2011-01-06 14:29:59 +0000 | [diff] [blame] | 1493 | * ixgbe_get_fdirtcpm_82599 - generate a tcp port from atr_input_masks |
| 1494 | * @input_mask: mask to be bit swapped |
| 1495 | * |
| 1496 | * The source and destination port masks for flow director are bit swapped |
| 1497 | * in that bit 15 effects bit 0, 14 effects 1, 13, 2 etc. In order to |
| 1498 | * generate a correctly swapped value we need to bit swap the mask and that |
| 1499 | * is what is accomplished by this function. |
| 1500 | **/ |
| 1501 | static u32 ixgbe_get_fdirtcpm_82599(struct ixgbe_atr_input_masks *input_masks) |
| 1502 | { |
| 1503 | u32 mask = ntohs(input_masks->dst_port_mask); |
| 1504 | mask <<= IXGBE_FDIRTCPM_DPORTM_SHIFT; |
| 1505 | mask |= ntohs(input_masks->src_port_mask); |
| 1506 | mask = ((mask & 0x55555555) << 1) | ((mask & 0xAAAAAAAA) >> 1); |
| 1507 | mask = ((mask & 0x33333333) << 2) | ((mask & 0xCCCCCCCC) >> 2); |
| 1508 | mask = ((mask & 0x0F0F0F0F) << 4) | ((mask & 0xF0F0F0F0) >> 4); |
| 1509 | return ((mask & 0x00FF00FF) << 8) | ((mask & 0xFF00FF00) >> 8); |
| 1510 | } |
| 1511 | |
| 1512 | /* |
| 1513 | * These two macros are meant to address the fact that we have registers |
| 1514 | * that are either all or in part big-endian. As a result on big-endian |
| 1515 | * systems we will end up byte swapping the value to little-endian before |
| 1516 | * it is byte swapped again and written to the hardware in the original |
| 1517 | * big-endian format. |
| 1518 | */ |
| 1519 | #define IXGBE_STORE_AS_BE32(_value) \ |
| 1520 | (((u32)(_value) >> 24) | (((u32)(_value) & 0x00FF0000) >> 8) | \ |
| 1521 | (((u32)(_value) & 0x0000FF00) << 8) | ((u32)(_value) << 24)) |
| 1522 | |
| 1523 | #define IXGBE_WRITE_REG_BE32(a, reg, value) \ |
| 1524 | IXGBE_WRITE_REG((a), (reg), IXGBE_STORE_AS_BE32(ntohl(value))) |
| 1525 | |
| 1526 | #define IXGBE_STORE_AS_BE16(_value) \ |
| 1527 | (((u16)(_value) >> 8) | ((u16)(_value) << 8)) |
| 1528 | |
| 1529 | /** |
Peter P Waskiewicz Jr | ffff477 | 2009-06-04 16:01:25 +0000 | [diff] [blame] | 1530 | * ixgbe_fdir_add_perfect_filter_82599 - Adds a perfect filter |
| 1531 | * @hw: pointer to hardware structure |
| 1532 | * @input: input bitstream |
Peter Waskiewicz | 9a713e7 | 2010-02-10 16:07:54 +0000 | [diff] [blame] | 1533 | * @input_masks: bitwise masks for relevant fields |
| 1534 | * @soft_id: software index into the silicon hash tables for filter storage |
Peter P Waskiewicz Jr | ffff477 | 2009-06-04 16:01:25 +0000 | [diff] [blame] | 1535 | * @queue: queue index to direct traffic to |
| 1536 | * |
| 1537 | * Note that the caller to this function must lock before calling, since the |
| 1538 | * hardware writes must be protected from one another. |
| 1539 | **/ |
| 1540 | s32 ixgbe_fdir_add_perfect_filter_82599(struct ixgbe_hw *hw, |
Alexander Duyck | 905e4a4 | 2011-01-06 14:29:57 +0000 | [diff] [blame] | 1541 | union ixgbe_atr_input *input, |
Peter Waskiewicz | 9a713e7 | 2010-02-10 16:07:54 +0000 | [diff] [blame] | 1542 | struct ixgbe_atr_input_masks *input_masks, |
| 1543 | u16 soft_id, u8 queue) |
Peter P Waskiewicz Jr | ffff477 | 2009-06-04 16:01:25 +0000 | [diff] [blame] | 1544 | { |
Peter P Waskiewicz Jr | ffff477 | 2009-06-04 16:01:25 +0000 | [diff] [blame] | 1545 | u32 fdirhash; |
Alexander Duyck | 45b9f50 | 2011-01-06 14:29:59 +0000 | [diff] [blame] | 1546 | u32 fdircmd; |
| 1547 | u32 fdirport, fdirtcpm; |
| 1548 | u32 fdirvlan; |
| 1549 | /* start with VLAN, flex bytes, VM pool, and IPv6 destination masked */ |
| 1550 | u32 fdirm = IXGBE_FDIRM_VLANID | IXGBE_FDIRM_VLANP | IXGBE_FDIRM_FLEX | |
| 1551 | IXGBE_FDIRM_POOL | IXGBE_FDIRM_DIPv6; |
Peter P Waskiewicz Jr | ffff477 | 2009-06-04 16:01:25 +0000 | [diff] [blame] | 1552 | |
| 1553 | /* |
Alexander Duyck | 45b9f50 | 2011-01-06 14:29:59 +0000 | [diff] [blame] | 1554 | * Check flow_type formatting, and bail out before we touch the hardware |
Peter P Waskiewicz Jr | ffff477 | 2009-06-04 16:01:25 +0000 | [diff] [blame] | 1555 | * if there's a configuration issue |
| 1556 | */ |
Alexander Duyck | 45b9f50 | 2011-01-06 14:29:59 +0000 | [diff] [blame] | 1557 | switch (input->formatted.flow_type) { |
| 1558 | case IXGBE_ATR_FLOW_TYPE_IPV4: |
| 1559 | /* use the L4 protocol mask for raw IPv4/IPv6 traffic */ |
| 1560 | fdirm |= IXGBE_FDIRM_L4P; |
| 1561 | case IXGBE_ATR_FLOW_TYPE_SCTPV4: |
| 1562 | if (input_masks->dst_port_mask || input_masks->src_port_mask) { |
| 1563 | hw_dbg(hw, " Error on src/dst port mask\n"); |
| 1564 | return IXGBE_ERR_CONFIG; |
| 1565 | } |
| 1566 | case IXGBE_ATR_FLOW_TYPE_TCPV4: |
| 1567 | case IXGBE_ATR_FLOW_TYPE_UDPV4: |
Peter P Waskiewicz Jr | ffff477 | 2009-06-04 16:01:25 +0000 | [diff] [blame] | 1568 | break; |
| 1569 | default: |
Alexander Duyck | 45b9f50 | 2011-01-06 14:29:59 +0000 | [diff] [blame] | 1570 | hw_dbg(hw, " Error on flow type input\n"); |
Peter P Waskiewicz Jr | ffff477 | 2009-06-04 16:01:25 +0000 | [diff] [blame] | 1571 | return IXGBE_ERR_CONFIG; |
| 1572 | } |
| 1573 | |
Peter Waskiewicz | 9a713e7 | 2010-02-10 16:07:54 +0000 | [diff] [blame] | 1574 | /* |
Alexander Duyck | 45b9f50 | 2011-01-06 14:29:59 +0000 | [diff] [blame] | 1575 | * Program the relevant mask registers. If src/dst_port or src/dst_addr |
| 1576 | * are zero, then assume a full mask for that field. Also assume that |
| 1577 | * a VLAN of 0 is unspecified, so mask that out as well. L4type |
| 1578 | * cannot be masked out in this implementation. |
Peter Waskiewicz | 9a713e7 | 2010-02-10 16:07:54 +0000 | [diff] [blame] | 1579 | * |
| 1580 | * This also assumes IPv4 only. IPv6 masking isn't supported at this |
| 1581 | * point in time. |
| 1582 | */ |
Peter Waskiewicz | 9a713e7 | 2010-02-10 16:07:54 +0000 | [diff] [blame] | 1583 | |
Alexander Duyck | 45b9f50 | 2011-01-06 14:29:59 +0000 | [diff] [blame] | 1584 | /* Program FDIRM */ |
| 1585 | switch (ntohs(input_masks->vlan_id_mask) & 0xEFFF) { |
| 1586 | case 0xEFFF: |
| 1587 | /* Unmask VLAN ID - bit 0 and fall through to unmask prio */ |
| 1588 | fdirm &= ~IXGBE_FDIRM_VLANID; |
| 1589 | case 0xE000: |
| 1590 | /* Unmask VLAN prio - bit 1 */ |
| 1591 | fdirm &= ~IXGBE_FDIRM_VLANP; |
Peter Waskiewicz | 9a713e7 | 2010-02-10 16:07:54 +0000 | [diff] [blame] | 1592 | break; |
Alexander Duyck | 45b9f50 | 2011-01-06 14:29:59 +0000 | [diff] [blame] | 1593 | case 0x0FFF: |
| 1594 | /* Unmask VLAN ID - bit 0 */ |
| 1595 | fdirm &= ~IXGBE_FDIRM_VLANID; |
| 1596 | break; |
| 1597 | case 0x0000: |
| 1598 | /* do nothing, vlans already masked */ |
Peter Waskiewicz | 9a713e7 | 2010-02-10 16:07:54 +0000 | [diff] [blame] | 1599 | break; |
| 1600 | default: |
Alexander Duyck | 45b9f50 | 2011-01-06 14:29:59 +0000 | [diff] [blame] | 1601 | hw_dbg(hw, " Error on VLAN mask\n"); |
| 1602 | return IXGBE_ERR_CONFIG; |
Peter Waskiewicz | 9a713e7 | 2010-02-10 16:07:54 +0000 | [diff] [blame] | 1603 | } |
| 1604 | |
Alexander Duyck | 45b9f50 | 2011-01-06 14:29:59 +0000 | [diff] [blame] | 1605 | if (input_masks->flex_mask & 0xFFFF) { |
| 1606 | if ((input_masks->flex_mask & 0xFFFF) != 0xFFFF) { |
| 1607 | hw_dbg(hw, " Error on flexible byte mask\n"); |
| 1608 | return IXGBE_ERR_CONFIG; |
| 1609 | } |
| 1610 | /* Unmask Flex Bytes - bit 4 */ |
| 1611 | fdirm &= ~IXGBE_FDIRM_FLEX; |
| 1612 | } |
Peter Waskiewicz | 9a713e7 | 2010-02-10 16:07:54 +0000 | [diff] [blame] | 1613 | |
| 1614 | /* Now mask VM pool and destination IPv6 - bits 5 and 2 */ |
Peter Waskiewicz | 9a713e7 | 2010-02-10 16:07:54 +0000 | [diff] [blame] | 1615 | IXGBE_WRITE_REG(hw, IXGBE_FDIRM, fdirm); |
Peter P Waskiewicz Jr | ffff477 | 2009-06-04 16:01:25 +0000 | [diff] [blame] | 1616 | |
Alexander Duyck | 45b9f50 | 2011-01-06 14:29:59 +0000 | [diff] [blame] | 1617 | /* store the TCP/UDP port masks, bit reversed from port layout */ |
| 1618 | fdirtcpm = ixgbe_get_fdirtcpm_82599(input_masks); |
| 1619 | |
| 1620 | /* write both the same so that UDP and TCP use the same mask */ |
| 1621 | IXGBE_WRITE_REG(hw, IXGBE_FDIRTCPM, ~fdirtcpm); |
| 1622 | IXGBE_WRITE_REG(hw, IXGBE_FDIRUDPM, ~fdirtcpm); |
| 1623 | |
| 1624 | /* store source and destination IP masks (big-enian) */ |
| 1625 | IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRSIP4M, |
| 1626 | ~input_masks->src_ip_mask[0]); |
| 1627 | IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRDIP4M, |
| 1628 | ~input_masks->dst_ip_mask[0]); |
| 1629 | |
| 1630 | /* Apply masks to input data */ |
| 1631 | input->formatted.vlan_id &= input_masks->vlan_id_mask; |
| 1632 | input->formatted.flex_bytes &= input_masks->flex_mask; |
| 1633 | input->formatted.src_port &= input_masks->src_port_mask; |
| 1634 | input->formatted.dst_port &= input_masks->dst_port_mask; |
| 1635 | input->formatted.src_ip[0] &= input_masks->src_ip_mask[0]; |
| 1636 | input->formatted.dst_ip[0] &= input_masks->dst_ip_mask[0]; |
| 1637 | |
| 1638 | /* record vlan (little-endian) and flex_bytes(big-endian) */ |
| 1639 | fdirvlan = |
| 1640 | IXGBE_STORE_AS_BE16(ntohs(input->formatted.flex_bytes)); |
| 1641 | fdirvlan <<= IXGBE_FDIRVLAN_FLEX_SHIFT; |
| 1642 | fdirvlan |= ntohs(input->formatted.vlan_id); |
| 1643 | IXGBE_WRITE_REG(hw, IXGBE_FDIRVLAN, fdirvlan); |
| 1644 | |
| 1645 | /* record source and destination port (little-endian)*/ |
| 1646 | fdirport = ntohs(input->formatted.dst_port); |
| 1647 | fdirport <<= IXGBE_FDIRPORT_DESTINATION_SHIFT; |
| 1648 | fdirport |= ntohs(input->formatted.src_port); |
| 1649 | IXGBE_WRITE_REG(hw, IXGBE_FDIRPORT, fdirport); |
| 1650 | |
| 1651 | /* record the first 32 bits of the destination address (big-endian) */ |
| 1652 | IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRIPDA, input->formatted.dst_ip[0]); |
| 1653 | |
| 1654 | /* record the source address (big-endian) */ |
| 1655 | IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRIPSA, input->formatted.src_ip[0]); |
| 1656 | |
| 1657 | /* configure FDIRCMD register */ |
| 1658 | fdircmd = IXGBE_FDIRCMD_CMD_ADD_FLOW | IXGBE_FDIRCMD_FILTER_UPDATE | |
| 1659 | IXGBE_FDIRCMD_LAST | IXGBE_FDIRCMD_QUEUE_EN; |
| 1660 | fdircmd |= input->formatted.flow_type << IXGBE_FDIRCMD_FLOW_TYPE_SHIFT; |
| 1661 | fdircmd |= (u32)queue << IXGBE_FDIRCMD_RX_QUEUE_SHIFT; |
| 1662 | |
| 1663 | /* we only want the bucket hash so drop the upper 16 bits */ |
| 1664 | fdirhash = ixgbe_atr_compute_hash_82599(input, |
| 1665 | IXGBE_ATR_BUCKET_HASH_KEY); |
| 1666 | fdirhash |= soft_id << IXGBE_FDIRHASH_SIG_SW_INDEX_SHIFT; |
Peter P Waskiewicz Jr | ffff477 | 2009-06-04 16:01:25 +0000 | [diff] [blame] | 1667 | |
| 1668 | IXGBE_WRITE_REG(hw, IXGBE_FDIRHASH, fdirhash); |
| 1669 | IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD, fdircmd); |
| 1670 | |
| 1671 | return 0; |
| 1672 | } |
Alexander Duyck | 45b9f50 | 2011-01-06 14:29:59 +0000 | [diff] [blame] | 1673 | |
Peter P Waskiewicz Jr | ffff477 | 2009-06-04 16:01:25 +0000 | [diff] [blame] | 1674 | /** |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 1675 | * ixgbe_read_analog_reg8_82599 - Reads 8 bit Omer analog register |
| 1676 | * @hw: pointer to hardware structure |
| 1677 | * @reg: analog register to read |
| 1678 | * @val: read value |
| 1679 | * |
| 1680 | * Performs read operation to Omer analog register specified. |
| 1681 | **/ |
Don Skidmore | 7b25cdb | 2009-08-25 04:47:32 +0000 | [diff] [blame] | 1682 | static s32 ixgbe_read_analog_reg8_82599(struct ixgbe_hw *hw, u32 reg, u8 *val) |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 1683 | { |
| 1684 | u32 core_ctl; |
| 1685 | |
| 1686 | IXGBE_WRITE_REG(hw, IXGBE_CORECTL, IXGBE_CORECTL_WRITE_CMD | |
| 1687 | (reg << 8)); |
| 1688 | IXGBE_WRITE_FLUSH(hw); |
| 1689 | udelay(10); |
| 1690 | core_ctl = IXGBE_READ_REG(hw, IXGBE_CORECTL); |
| 1691 | *val = (u8)core_ctl; |
| 1692 | |
| 1693 | return 0; |
| 1694 | } |
| 1695 | |
| 1696 | /** |
| 1697 | * ixgbe_write_analog_reg8_82599 - Writes 8 bit Omer analog register |
| 1698 | * @hw: pointer to hardware structure |
| 1699 | * @reg: atlas register to write |
| 1700 | * @val: value to write |
| 1701 | * |
| 1702 | * Performs write operation to Omer analog register specified. |
| 1703 | **/ |
Don Skidmore | 7b25cdb | 2009-08-25 04:47:32 +0000 | [diff] [blame] | 1704 | static s32 ixgbe_write_analog_reg8_82599(struct ixgbe_hw *hw, u32 reg, u8 val) |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 1705 | { |
| 1706 | u32 core_ctl; |
| 1707 | |
| 1708 | core_ctl = (reg << 8) | val; |
| 1709 | IXGBE_WRITE_REG(hw, IXGBE_CORECTL, core_ctl); |
| 1710 | IXGBE_WRITE_FLUSH(hw); |
| 1711 | udelay(10); |
| 1712 | |
| 1713 | return 0; |
| 1714 | } |
| 1715 | |
| 1716 | /** |
| 1717 | * ixgbe_start_hw_82599 - Prepare hardware for Tx/Rx |
| 1718 | * @hw: pointer to hardware structure |
| 1719 | * |
| 1720 | * Starts the hardware using the generic start_hw function. |
| 1721 | * Then performs device-specific: |
| 1722 | * Clears the rate limiter registers. |
| 1723 | **/ |
Don Skidmore | 7b25cdb | 2009-08-25 04:47:32 +0000 | [diff] [blame] | 1724 | static s32 ixgbe_start_hw_82599(struct ixgbe_hw *hw) |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 1725 | { |
| 1726 | u32 q_num; |
Peter P Waskiewicz Jr | 794caeb | 2009-06-04 16:02:24 +0000 | [diff] [blame] | 1727 | s32 ret_val; |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 1728 | |
Peter P Waskiewicz Jr | 794caeb | 2009-06-04 16:02:24 +0000 | [diff] [blame] | 1729 | ret_val = ixgbe_start_hw_generic(hw); |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 1730 | |
| 1731 | /* Clear the rate limiters */ |
| 1732 | for (q_num = 0; q_num < hw->mac.max_tx_queues; q_num++) { |
| 1733 | IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, q_num); |
| 1734 | IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, 0); |
| 1735 | } |
| 1736 | IXGBE_WRITE_FLUSH(hw); |
| 1737 | |
Peter P Waskiewicz Jr | 50ac58b | 2009-06-04 11:10:53 +0000 | [diff] [blame] | 1738 | /* We need to run link autotry after the driver loads */ |
| 1739 | hw->mac.autotry_restart = true; |
| 1740 | |
Peter P Waskiewicz Jr | 794caeb | 2009-06-04 16:02:24 +0000 | [diff] [blame] | 1741 | if (ret_val == 0) |
| 1742 | ret_val = ixgbe_verify_fw_version_82599(hw); |
| 1743 | |
| 1744 | return ret_val; |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 1745 | } |
| 1746 | |
| 1747 | /** |
| 1748 | * ixgbe_identify_phy_82599 - Get physical layer module |
| 1749 | * @hw: pointer to hardware structure |
| 1750 | * |
| 1751 | * Determines the physical layer module found on the current adapter. |
Emil Tantilov | 21cc5b4 | 2011-02-12 10:52:07 +0000 | [diff] [blame] | 1752 | * If PHY already detected, maintains current PHY type in hw struct, |
| 1753 | * otherwise executes the PHY detection routine. |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 1754 | **/ |
Emil Tantilov | 21cc5b4 | 2011-02-12 10:52:07 +0000 | [diff] [blame] | 1755 | s32 ixgbe_identify_phy_82599(struct ixgbe_hw *hw) |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 1756 | { |
| 1757 | s32 status = IXGBE_ERR_PHY_ADDR_INVALID; |
Emil Tantilov | 21cc5b4 | 2011-02-12 10:52:07 +0000 | [diff] [blame] | 1758 | |
| 1759 | /* Detect PHY if not unknown - returns success if already detected. */ |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 1760 | status = ixgbe_identify_phy_generic(hw); |
Emil Tantilov | 21cc5b4 | 2011-02-12 10:52:07 +0000 | [diff] [blame] | 1761 | if (status != 0) { |
| 1762 | /* 82599 10GBASE-T requires an external PHY */ |
| 1763 | if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) |
| 1764 | goto out; |
| 1765 | else |
| 1766 | status = ixgbe_identify_sfp_module_generic(hw); |
| 1767 | } |
| 1768 | |
| 1769 | /* Set PHY type none if no PHY detected */ |
| 1770 | if (hw->phy.type == ixgbe_phy_unknown) { |
| 1771 | hw->phy.type = ixgbe_phy_none; |
| 1772 | status = 0; |
| 1773 | } |
| 1774 | |
| 1775 | /* Return error if SFP module has been detected but is not supported */ |
| 1776 | if (hw->phy.type == ixgbe_phy_sfp_unsupported) |
| 1777 | status = IXGBE_ERR_SFP_NOT_SUPPORTED; |
| 1778 | |
| 1779 | out: |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 1780 | return status; |
| 1781 | } |
| 1782 | |
| 1783 | /** |
| 1784 | * ixgbe_get_supported_physical_layer_82599 - Returns physical layer type |
| 1785 | * @hw: pointer to hardware structure |
| 1786 | * |
| 1787 | * Determines physical layer capabilities of the current configuration. |
| 1788 | **/ |
Don Skidmore | 7b25cdb | 2009-08-25 04:47:32 +0000 | [diff] [blame] | 1789 | static u32 ixgbe_get_supported_physical_layer_82599(struct ixgbe_hw *hw) |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 1790 | { |
| 1791 | u32 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN; |
Peter P Waskiewicz Jr | 0419305 | 2009-04-09 22:28:50 +0000 | [diff] [blame] | 1792 | u32 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC); |
| 1793 | u32 autoc2 = IXGBE_READ_REG(hw, IXGBE_AUTOC2); |
| 1794 | u32 pma_pmd_10g_serial = autoc2 & IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_MASK; |
| 1795 | u32 pma_pmd_10g_parallel = autoc & IXGBE_AUTOC_10G_PMA_PMD_MASK; |
| 1796 | u32 pma_pmd_1g = autoc & IXGBE_AUTOC_1G_PMA_PMD_MASK; |
| 1797 | u16 ext_ability = 0; |
PJ Waskiewicz | 1339b9e | 2009-03-13 22:12:29 +0000 | [diff] [blame] | 1798 | u8 comp_codes_10g = 0; |
Don Skidmore | cb836a9 | 2010-06-29 18:30:59 +0000 | [diff] [blame] | 1799 | u8 comp_codes_1g = 0; |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 1800 | |
Peter P Waskiewicz Jr | 0419305 | 2009-04-09 22:28:50 +0000 | [diff] [blame] | 1801 | hw->phy.ops.identify(hw); |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 1802 | |
Emil Tantilov | 21cc5b4 | 2011-02-12 10:52:07 +0000 | [diff] [blame] | 1803 | switch (hw->phy.type) { |
| 1804 | case ixgbe_phy_tn: |
| 1805 | case ixgbe_phy_aq: |
| 1806 | case ixgbe_phy_cu_unknown: |
Ben Hutchings | 6b73e10 | 2009-04-29 08:08:58 +0000 | [diff] [blame] | 1807 | hw->phy.ops.read_reg(hw, MDIO_PMA_EXTABLE, MDIO_MMD_PMAPMD, |
Emil Tantilov | 21cc5b4 | 2011-02-12 10:52:07 +0000 | [diff] [blame] | 1808 | &ext_ability); |
Ben Hutchings | 6b73e10 | 2009-04-29 08:08:58 +0000 | [diff] [blame] | 1809 | if (ext_ability & MDIO_PMA_EXTABLE_10GBT) |
Peter P Waskiewicz Jr | 0419305 | 2009-04-09 22:28:50 +0000 | [diff] [blame] | 1810 | physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_T; |
Ben Hutchings | 6b73e10 | 2009-04-29 08:08:58 +0000 | [diff] [blame] | 1811 | if (ext_ability & MDIO_PMA_EXTABLE_1000BT) |
Peter P Waskiewicz Jr | 0419305 | 2009-04-09 22:28:50 +0000 | [diff] [blame] | 1812 | physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_T; |
Ben Hutchings | 6b73e10 | 2009-04-29 08:08:58 +0000 | [diff] [blame] | 1813 | if (ext_ability & MDIO_PMA_EXTABLE_100BTX) |
Peter P Waskiewicz Jr | 0419305 | 2009-04-09 22:28:50 +0000 | [diff] [blame] | 1814 | physical_layer |= IXGBE_PHYSICAL_LAYER_100BASE_TX; |
| 1815 | goto out; |
Emil Tantilov | 21cc5b4 | 2011-02-12 10:52:07 +0000 | [diff] [blame] | 1816 | default: |
| 1817 | break; |
Peter P Waskiewicz Jr | 0419305 | 2009-04-09 22:28:50 +0000 | [diff] [blame] | 1818 | } |
| 1819 | |
| 1820 | switch (autoc & IXGBE_AUTOC_LMS_MASK) { |
| 1821 | case IXGBE_AUTOC_LMS_1G_AN: |
| 1822 | case IXGBE_AUTOC_LMS_1G_LINK_NO_AN: |
| 1823 | if (pma_pmd_1g == IXGBE_AUTOC_1G_KX_BX) { |
| 1824 | physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_KX | |
| 1825 | IXGBE_PHYSICAL_LAYER_1000BASE_BX; |
| 1826 | goto out; |
| 1827 | } else |
| 1828 | /* SFI mode so read SFP module */ |
| 1829 | goto sfp_check; |
| 1830 | break; |
| 1831 | case IXGBE_AUTOC_LMS_10G_LINK_NO_AN: |
| 1832 | if (pma_pmd_10g_parallel == IXGBE_AUTOC_10G_CX4) |
| 1833 | physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_CX4; |
| 1834 | else if (pma_pmd_10g_parallel == IXGBE_AUTOC_10G_KX4) |
| 1835 | physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KX4; |
Peter P Waskiewicz Jr | 1fcf03e | 2009-05-17 20:58:04 +0000 | [diff] [blame] | 1836 | else if (pma_pmd_10g_parallel == IXGBE_AUTOC_10G_XAUI) |
| 1837 | physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_XAUI; |
Peter P Waskiewicz Jr | 0419305 | 2009-04-09 22:28:50 +0000 | [diff] [blame] | 1838 | goto out; |
| 1839 | break; |
| 1840 | case IXGBE_AUTOC_LMS_10G_SERIAL: |
| 1841 | if (pma_pmd_10g_serial == IXGBE_AUTOC2_10G_KR) { |
| 1842 | physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KR; |
| 1843 | goto out; |
| 1844 | } else if (pma_pmd_10g_serial == IXGBE_AUTOC2_10G_SFI) |
| 1845 | goto sfp_check; |
| 1846 | break; |
| 1847 | case IXGBE_AUTOC_LMS_KX4_KX_KR: |
| 1848 | case IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN: |
| 1849 | if (autoc & IXGBE_AUTOC_KX_SUPP) |
| 1850 | physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_KX; |
| 1851 | if (autoc & IXGBE_AUTOC_KX4_SUPP) |
| 1852 | physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_KX4; |
| 1853 | if (autoc & IXGBE_AUTOC_KR_SUPP) |
| 1854 | physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_KR; |
| 1855 | goto out; |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 1856 | break; |
| 1857 | default: |
Peter P Waskiewicz Jr | 0419305 | 2009-04-09 22:28:50 +0000 | [diff] [blame] | 1858 | goto out; |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 1859 | break; |
| 1860 | } |
| 1861 | |
Peter P Waskiewicz Jr | 0419305 | 2009-04-09 22:28:50 +0000 | [diff] [blame] | 1862 | sfp_check: |
| 1863 | /* SFP check must be done last since DA modules are sometimes used to |
| 1864 | * test KR mode - we need to id KR mode correctly before SFP module. |
| 1865 | * Call identify_sfp because the pluggable module may have changed */ |
| 1866 | hw->phy.ops.identify_sfp(hw); |
| 1867 | if (hw->phy.sfp_type == ixgbe_sfp_type_not_present) |
| 1868 | goto out; |
| 1869 | |
| 1870 | switch (hw->phy.type) { |
Don Skidmore | ea0a04d | 2010-05-18 16:00:13 +0000 | [diff] [blame] | 1871 | case ixgbe_phy_sfp_passive_tyco: |
| 1872 | case ixgbe_phy_sfp_passive_unknown: |
Peter P Waskiewicz Jr | 0419305 | 2009-04-09 22:28:50 +0000 | [diff] [blame] | 1873 | physical_layer = IXGBE_PHYSICAL_LAYER_SFP_PLUS_CU; |
| 1874 | break; |
Don Skidmore | ea0a04d | 2010-05-18 16:00:13 +0000 | [diff] [blame] | 1875 | case ixgbe_phy_sfp_ftl_active: |
| 1876 | case ixgbe_phy_sfp_active_unknown: |
| 1877 | physical_layer = IXGBE_PHYSICAL_LAYER_SFP_ACTIVE_DA; |
| 1878 | break; |
Peter P Waskiewicz Jr | 0419305 | 2009-04-09 22:28:50 +0000 | [diff] [blame] | 1879 | case ixgbe_phy_sfp_avago: |
| 1880 | case ixgbe_phy_sfp_ftl: |
| 1881 | case ixgbe_phy_sfp_intel: |
| 1882 | case ixgbe_phy_sfp_unknown: |
| 1883 | hw->phy.ops.read_i2c_eeprom(hw, |
Don Skidmore | cb836a9 | 2010-06-29 18:30:59 +0000 | [diff] [blame] | 1884 | IXGBE_SFF_1GBE_COMP_CODES, &comp_codes_1g); |
| 1885 | hw->phy.ops.read_i2c_eeprom(hw, |
Peter P Waskiewicz Jr | 0419305 | 2009-04-09 22:28:50 +0000 | [diff] [blame] | 1886 | IXGBE_SFF_10GBE_COMP_CODES, &comp_codes_10g); |
| 1887 | if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE) |
| 1888 | physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_SR; |
| 1889 | else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE) |
| 1890 | physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_LR; |
Don Skidmore | cb836a9 | 2010-06-29 18:30:59 +0000 | [diff] [blame] | 1891 | else if (comp_codes_1g & IXGBE_SFF_1GBASET_CAPABLE) |
| 1892 | physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_T; |
Peter P Waskiewicz Jr | 0419305 | 2009-04-09 22:28:50 +0000 | [diff] [blame] | 1893 | break; |
| 1894 | default: |
| 1895 | break; |
| 1896 | } |
| 1897 | |
| 1898 | out: |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 1899 | return physical_layer; |
| 1900 | } |
| 1901 | |
| 1902 | /** |
| 1903 | * ixgbe_enable_rx_dma_82599 - Enable the Rx DMA unit on 82599 |
| 1904 | * @hw: pointer to hardware structure |
| 1905 | * @regval: register value to write to RXCTRL |
| 1906 | * |
| 1907 | * Enables the Rx DMA unit for 82599 |
| 1908 | **/ |
Don Skidmore | 7b25cdb | 2009-08-25 04:47:32 +0000 | [diff] [blame] | 1909 | static s32 ixgbe_enable_rx_dma_82599(struct ixgbe_hw *hw, u32 regval) |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 1910 | { |
| 1911 | #define IXGBE_MAX_SECRX_POLL 30 |
| 1912 | int i; |
| 1913 | int secrxreg; |
| 1914 | |
| 1915 | /* |
| 1916 | * Workaround for 82599 silicon errata when enabling the Rx datapath. |
| 1917 | * If traffic is incoming before we enable the Rx unit, it could hang |
| 1918 | * the Rx DMA unit. Therefore, make sure the security engine is |
| 1919 | * completely disabled prior to enabling the Rx unit. |
| 1920 | */ |
| 1921 | secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL); |
| 1922 | secrxreg |= IXGBE_SECRXCTRL_RX_DIS; |
| 1923 | IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, secrxreg); |
| 1924 | for (i = 0; i < IXGBE_MAX_SECRX_POLL; i++) { |
| 1925 | secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXSTAT); |
| 1926 | if (secrxreg & IXGBE_SECRXSTAT_SECRX_RDY) |
| 1927 | break; |
| 1928 | else |
| 1929 | udelay(10); |
| 1930 | } |
| 1931 | |
| 1932 | /* For informational purposes only */ |
| 1933 | if (i >= IXGBE_MAX_SECRX_POLL) |
| 1934 | hw_dbg(hw, "Rx unit being enabled before security " |
| 1935 | "path fully disabled. Continuing with init.\n"); |
| 1936 | |
| 1937 | IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, regval); |
| 1938 | secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL); |
| 1939 | secrxreg &= ~IXGBE_SECRXCTRL_RX_DIS; |
| 1940 | IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, secrxreg); |
| 1941 | IXGBE_WRITE_FLUSH(hw); |
| 1942 | |
| 1943 | return 0; |
| 1944 | } |
| 1945 | |
Peter P Waskiewicz Jr | 0419305 | 2009-04-09 22:28:50 +0000 | [diff] [blame] | 1946 | /** |
| 1947 | * ixgbe_get_device_caps_82599 - Get additional device capabilities |
| 1948 | * @hw: pointer to hardware structure |
| 1949 | * @device_caps: the EEPROM word with the extra device capabilities |
| 1950 | * |
| 1951 | * This function will read the EEPROM location for the device capabilities, |
| 1952 | * and return the word through device_caps. |
| 1953 | **/ |
Don Skidmore | 7b25cdb | 2009-08-25 04:47:32 +0000 | [diff] [blame] | 1954 | static s32 ixgbe_get_device_caps_82599(struct ixgbe_hw *hw, u16 *device_caps) |
Peter P Waskiewicz Jr | 0419305 | 2009-04-09 22:28:50 +0000 | [diff] [blame] | 1955 | { |
| 1956 | hw->eeprom.ops.read(hw, IXGBE_DEVICE_CAPS, device_caps); |
| 1957 | |
| 1958 | return 0; |
| 1959 | } |
| 1960 | |
PJ Waskiewicz | 0365e6e | 2009-05-17 12:32:25 +0000 | [diff] [blame] | 1961 | /** |
Peter P Waskiewicz Jr | 794caeb | 2009-06-04 16:02:24 +0000 | [diff] [blame] | 1962 | * ixgbe_verify_fw_version_82599 - verify fw version for 82599 |
| 1963 | * @hw: pointer to hardware structure |
| 1964 | * |
| 1965 | * Verifies that installed the firmware version is 0.6 or higher |
| 1966 | * for SFI devices. All 82599 SFI devices should have version 0.6 or higher. |
| 1967 | * |
| 1968 | * Returns IXGBE_ERR_EEPROM_VERSION if the FW is not present or |
| 1969 | * if the FW version is not supported. |
| 1970 | **/ |
| 1971 | static s32 ixgbe_verify_fw_version_82599(struct ixgbe_hw *hw) |
| 1972 | { |
| 1973 | s32 status = IXGBE_ERR_EEPROM_VERSION; |
| 1974 | u16 fw_offset, fw_ptp_cfg_offset; |
| 1975 | u16 fw_version = 0; |
| 1976 | |
| 1977 | /* firmware check is only necessary for SFI devices */ |
| 1978 | if (hw->phy.media_type != ixgbe_media_type_fiber) { |
| 1979 | status = 0; |
| 1980 | goto fw_version_out; |
| 1981 | } |
| 1982 | |
| 1983 | /* get the offset to the Firmware Module block */ |
| 1984 | hw->eeprom.ops.read(hw, IXGBE_FW_PTR, &fw_offset); |
| 1985 | |
| 1986 | if ((fw_offset == 0) || (fw_offset == 0xFFFF)) |
| 1987 | goto fw_version_out; |
| 1988 | |
| 1989 | /* get the offset to the Pass Through Patch Configuration block */ |
| 1990 | hw->eeprom.ops.read(hw, (fw_offset + |
| 1991 | IXGBE_FW_PASSTHROUGH_PATCH_CONFIG_PTR), |
| 1992 | &fw_ptp_cfg_offset); |
| 1993 | |
| 1994 | if ((fw_ptp_cfg_offset == 0) || (fw_ptp_cfg_offset == 0xFFFF)) |
| 1995 | goto fw_version_out; |
| 1996 | |
| 1997 | /* get the firmware version */ |
| 1998 | hw->eeprom.ops.read(hw, (fw_ptp_cfg_offset + |
| 1999 | IXGBE_FW_PATCH_VERSION_4), |
| 2000 | &fw_version); |
| 2001 | |
| 2002 | if (fw_version > 0x5) |
| 2003 | status = 0; |
| 2004 | |
| 2005 | fw_version_out: |
| 2006 | return status; |
| 2007 | } |
| 2008 | |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 2009 | static struct ixgbe_mac_operations mac_ops_82599 = { |
| 2010 | .init_hw = &ixgbe_init_hw_generic, |
| 2011 | .reset_hw = &ixgbe_reset_hw_82599, |
| 2012 | .start_hw = &ixgbe_start_hw_82599, |
| 2013 | .clear_hw_cntrs = &ixgbe_clear_hw_cntrs_generic, |
| 2014 | .get_media_type = &ixgbe_get_media_type_82599, |
| 2015 | .get_supported_physical_layer = &ixgbe_get_supported_physical_layer_82599, |
| 2016 | .enable_rx_dma = &ixgbe_enable_rx_dma_82599, |
| 2017 | .get_mac_addr = &ixgbe_get_mac_addr_generic, |
Mallikarjuna R Chilakala | 21ce849 | 2010-05-13 17:33:41 +0000 | [diff] [blame] | 2018 | .get_san_mac_addr = &ixgbe_get_san_mac_addr_generic, |
Peter P Waskiewicz Jr | 0419305 | 2009-04-09 22:28:50 +0000 | [diff] [blame] | 2019 | .get_device_caps = &ixgbe_get_device_caps_82599, |
Don Skidmore | a391f1d | 2010-11-16 19:27:15 -0800 | [diff] [blame] | 2020 | .get_wwn_prefix = &ixgbe_get_wwn_prefix_generic, |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 2021 | .stop_adapter = &ixgbe_stop_adapter_generic, |
| 2022 | .get_bus_info = &ixgbe_get_bus_info_generic, |
| 2023 | .set_lan_id = &ixgbe_set_lan_id_multi_port_pcie, |
| 2024 | .read_analog_reg8 = &ixgbe_read_analog_reg8_82599, |
| 2025 | .write_analog_reg8 = &ixgbe_write_analog_reg8_82599, |
| 2026 | .setup_link = &ixgbe_setup_mac_link_82599, |
Mallikarjuna R Chilakala | 21ce849 | 2010-05-13 17:33:41 +0000 | [diff] [blame] | 2027 | .check_link = &ixgbe_check_mac_link_generic, |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 2028 | .get_link_capabilities = &ixgbe_get_link_capabilities_82599, |
| 2029 | .led_on = &ixgbe_led_on_generic, |
| 2030 | .led_off = &ixgbe_led_off_generic, |
PJ Waskiewicz | 87c1201 | 2009-04-08 13:20:31 +0000 | [diff] [blame] | 2031 | .blink_led_start = &ixgbe_blink_led_start_generic, |
| 2032 | .blink_led_stop = &ixgbe_blink_led_stop_generic, |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 2033 | .set_rar = &ixgbe_set_rar_generic, |
| 2034 | .clear_rar = &ixgbe_clear_rar_generic, |
Mallikarjuna R Chilakala | 21ce849 | 2010-05-13 17:33:41 +0000 | [diff] [blame] | 2035 | .set_vmdq = &ixgbe_set_vmdq_generic, |
| 2036 | .clear_vmdq = &ixgbe_clear_vmdq_generic, |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 2037 | .init_rx_addrs = &ixgbe_init_rx_addrs_generic, |
| 2038 | .update_uc_addr_list = &ixgbe_update_uc_addr_list_generic, |
| 2039 | .update_mc_addr_list = &ixgbe_update_mc_addr_list_generic, |
| 2040 | .enable_mc = &ixgbe_enable_mc_generic, |
| 2041 | .disable_mc = &ixgbe_disable_mc_generic, |
Mallikarjuna R Chilakala | 21ce849 | 2010-05-13 17:33:41 +0000 | [diff] [blame] | 2042 | .clear_vfta = &ixgbe_clear_vfta_generic, |
| 2043 | .set_vfta = &ixgbe_set_vfta_generic, |
| 2044 | .fc_enable = &ixgbe_fc_enable_generic, |
| 2045 | .init_uta_tables = &ixgbe_init_uta_tables_generic, |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 2046 | .setup_sfp = &ixgbe_setup_sfp_modules_82599, |
Greg Rose | a985b6c3 | 2010-11-18 03:02:52 +0000 | [diff] [blame] | 2047 | .set_mac_anti_spoofing = &ixgbe_set_mac_anti_spoofing, |
| 2048 | .set_vlan_anti_spoofing = &ixgbe_set_vlan_anti_spoofing, |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 2049 | }; |
| 2050 | |
| 2051 | static struct ixgbe_eeprom_operations eeprom_ops_82599 = { |
| 2052 | .init_params = &ixgbe_init_eeprom_params_generic, |
Mallikarjuna R Chilakala | 21ce849 | 2010-05-13 17:33:41 +0000 | [diff] [blame] | 2053 | .read = &ixgbe_read_eerd_generic, |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 2054 | .write = &ixgbe_write_eeprom_generic, |
Don Skidmore | a391f1d | 2010-11-16 19:27:15 -0800 | [diff] [blame] | 2055 | .calc_checksum = &ixgbe_calc_eeprom_checksum_generic, |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 2056 | .validate_checksum = &ixgbe_validate_eeprom_checksum_generic, |
| 2057 | .update_checksum = &ixgbe_update_eeprom_checksum_generic, |
| 2058 | }; |
| 2059 | |
| 2060 | static struct ixgbe_phy_operations phy_ops_82599 = { |
| 2061 | .identify = &ixgbe_identify_phy_82599, |
| 2062 | .identify_sfp = &ixgbe_identify_sfp_module_generic, |
Mallikarjuna R Chilakala | 21ce849 | 2010-05-13 17:33:41 +0000 | [diff] [blame] | 2063 | .init = &ixgbe_init_phy_ops_82599, |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 2064 | .reset = &ixgbe_reset_phy_generic, |
| 2065 | .read_reg = &ixgbe_read_phy_reg_generic, |
| 2066 | .write_reg = &ixgbe_write_phy_reg_generic, |
| 2067 | .setup_link = &ixgbe_setup_phy_link_generic, |
| 2068 | .setup_link_speed = &ixgbe_setup_phy_link_speed_generic, |
| 2069 | .read_i2c_byte = &ixgbe_read_i2c_byte_generic, |
| 2070 | .write_i2c_byte = &ixgbe_write_i2c_byte_generic, |
| 2071 | .read_i2c_eeprom = &ixgbe_read_i2c_eeprom_generic, |
| 2072 | .write_i2c_eeprom = &ixgbe_write_i2c_eeprom_generic, |
Mallikarjuna R Chilakala | 119fc60 | 2010-05-20 23:07:06 -0700 | [diff] [blame] | 2073 | .check_overtemp = &ixgbe_tn_check_overtemp, |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 2074 | }; |
| 2075 | |
| 2076 | struct ixgbe_info ixgbe_82599_info = { |
| 2077 | .mac = ixgbe_mac_82599EB, |
| 2078 | .get_invariants = &ixgbe_get_invariants_82599, |
| 2079 | .mac_ops = &mac_ops_82599, |
| 2080 | .eeprom_ops = &eeprom_ops_82599, |
| 2081 | .phy_ops = &phy_ops_82599, |
Don Skidmore | a391f1d | 2010-11-16 19:27:15 -0800 | [diff] [blame] | 2082 | .mbx_ops = &mbx_ops_generic, |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 2083 | }; |