Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1 | /* linux/drivers/mtd/nand/s3c2410.c |
| 2 | * |
Ben Dooks | 7e74a50 | 2008-05-20 17:32:27 +0100 | [diff] [blame] | 3 | * Copyright © 2004-2008 Simtec Electronics |
| 4 | * http://armlinux.simtec.co.uk/ |
Ben Dooks | fdf2fd5 | 2005-02-18 14:46:15 +0000 | [diff] [blame] | 5 | * Ben Dooks <ben@simtec.co.uk> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 6 | * |
Ben Dooks | 7e74a50 | 2008-05-20 17:32:27 +0100 | [diff] [blame] | 7 | * Samsung S3C2410/S3C2440/S3C2412 NAND driver |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 8 | * |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 9 | * This program is free software; you can redistribute it and/or modify |
| 10 | * it under the terms of the GNU General Public License as published by |
| 11 | * the Free Software Foundation; either version 2 of the License, or |
| 12 | * (at your option) any later version. |
| 13 | * |
| 14 | * This program is distributed in the hope that it will be useful, |
| 15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 17 | * GNU General Public License for more details. |
| 18 | * |
| 19 | * You should have received a copy of the GNU General Public License |
| 20 | * along with this program; if not, write to the Free Software |
| 21 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
| 22 | */ |
| 23 | |
Sachin Kamat | 92aeb5d | 2012-07-16 16:02:23 +0530 | [diff] [blame] | 24 | #define pr_fmt(fmt) "nand-s3c2410: " fmt |
| 25 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 26 | #ifdef CONFIG_MTD_NAND_S3C2410_DEBUG |
| 27 | #define DEBUG |
| 28 | #endif |
| 29 | |
| 30 | #include <linux/module.h> |
| 31 | #include <linux/types.h> |
| 32 | #include <linux/init.h> |
| 33 | #include <linux/kernel.h> |
| 34 | #include <linux/string.h> |
Sachin Kamat | d2a89be | 2012-07-16 16:02:24 +0530 | [diff] [blame] | 35 | #include <linux/io.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 36 | #include <linux/ioport.h> |
Russell King | d052d1b | 2005-10-29 19:07:23 +0100 | [diff] [blame] | 37 | #include <linux/platform_device.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 38 | #include <linux/delay.h> |
| 39 | #include <linux/err.h> |
Tim Schmielau | 4e57b68 | 2005-10-30 15:03:48 -0800 | [diff] [blame] | 40 | #include <linux/slab.h> |
Russell King | f8ce254 | 2006-01-07 16:15:52 +0000 | [diff] [blame] | 41 | #include <linux/clk.h> |
Ben Dooks | 30821fe | 2008-07-15 11:58:31 +0100 | [diff] [blame] | 42 | #include <linux/cpufreq.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 43 | |
| 44 | #include <linux/mtd/mtd.h> |
| 45 | #include <linux/mtd/nand.h> |
| 46 | #include <linux/mtd/nand_ecc.h> |
| 47 | #include <linux/mtd/partitions.h> |
| 48 | |
Ben Dooks | 7926b5a | 2008-10-30 10:14:35 +0000 | [diff] [blame] | 49 | #include <plat/regs-nand.h> |
| 50 | #include <plat/nand.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 51 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 52 | /* new oob placement block for use with hardware ecc generation |
| 53 | */ |
| 54 | |
Thomas Gleixner | 5bd34c0 | 2006-05-27 22:16:10 +0200 | [diff] [blame] | 55 | static struct nand_ecclayout nand_hw_eccoob = { |
David Woodhouse | e0c7d76 | 2006-05-13 18:07:53 +0100 | [diff] [blame] | 56 | .eccbytes = 3, |
| 57 | .eccpos = {0, 1, 2}, |
| 58 | .oobfree = {{8, 8}} |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 59 | }; |
| 60 | |
| 61 | /* controller and mtd information */ |
| 62 | |
| 63 | struct s3c2410_nand_info; |
| 64 | |
Ben Dooks | 3db7215 | 2009-05-30 17:18:15 +0100 | [diff] [blame] | 65 | /** |
| 66 | * struct s3c2410_nand_mtd - driver MTD structure |
| 67 | * @mtd: The MTD instance to pass to the MTD layer. |
| 68 | * @chip: The NAND chip information. |
| 69 | * @set: The platform information supplied for this set of NAND chips. |
| 70 | * @info: Link back to the hardware information. |
| 71 | * @scan_res: The result from calling nand_scan_ident(). |
| 72 | */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 73 | struct s3c2410_nand_mtd { |
| 74 | struct mtd_info mtd; |
| 75 | struct nand_chip chip; |
| 76 | struct s3c2410_nand_set *set; |
| 77 | struct s3c2410_nand_info *info; |
| 78 | int scan_res; |
| 79 | }; |
| 80 | |
Ben Dooks | 2c06a08 | 2006-06-27 14:35:46 +0100 | [diff] [blame] | 81 | enum s3c_cpu_type { |
| 82 | TYPE_S3C2410, |
| 83 | TYPE_S3C2412, |
| 84 | TYPE_S3C2440, |
| 85 | }; |
| 86 | |
Jiri Pinkava | ac497c1 | 2011-04-13 11:59:30 +0200 | [diff] [blame] | 87 | enum s3c_nand_clk_state { |
| 88 | CLOCK_DISABLE = 0, |
| 89 | CLOCK_ENABLE, |
| 90 | CLOCK_SUSPEND, |
| 91 | }; |
| 92 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 93 | /* overview of the s3c2410 nand state */ |
| 94 | |
Ben Dooks | 3db7215 | 2009-05-30 17:18:15 +0100 | [diff] [blame] | 95 | /** |
| 96 | * struct s3c2410_nand_info - NAND controller state. |
| 97 | * @mtds: An array of MTD instances on this controoler. |
| 98 | * @platform: The platform data for this board. |
| 99 | * @device: The platform device we bound to. |
| 100 | * @area: The IO area resource that came from request_mem_region(). |
| 101 | * @clk: The clock resource for this controller. |
| 102 | * @regs: The area mapped for the hardware registers described by @area. |
| 103 | * @sel_reg: Pointer to the register controlling the NAND selection. |
| 104 | * @sel_bit: The bit in @sel_reg to select the NAND chip. |
| 105 | * @mtd_count: The number of MTDs created from this controller. |
| 106 | * @save_sel: The contents of @sel_reg to be saved over suspend. |
| 107 | * @clk_rate: The clock rate from @clk. |
Jiri Pinkava | ac497c1 | 2011-04-13 11:59:30 +0200 | [diff] [blame] | 108 | * @clk_state: The current clock state. |
Ben Dooks | 3db7215 | 2009-05-30 17:18:15 +0100 | [diff] [blame] | 109 | * @cpu_type: The exact type of this controller. |
| 110 | */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 111 | struct s3c2410_nand_info { |
| 112 | /* mtd info */ |
| 113 | struct nand_hw_control controller; |
| 114 | struct s3c2410_nand_mtd *mtds; |
| 115 | struct s3c2410_platform_nand *platform; |
| 116 | |
| 117 | /* device info */ |
| 118 | struct device *device; |
| 119 | struct resource *area; |
| 120 | struct clk *clk; |
Ben Dooks | fdf2fd5 | 2005-02-18 14:46:15 +0000 | [diff] [blame] | 121 | void __iomem *regs; |
Ben Dooks | 2c06a08 | 2006-06-27 14:35:46 +0100 | [diff] [blame] | 122 | void __iomem *sel_reg; |
| 123 | int sel_bit; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 124 | int mtd_count; |
Ben Dooks | 0916083 | 2008-04-15 11:36:18 +0100 | [diff] [blame] | 125 | unsigned long save_sel; |
Ben Dooks | 30821fe | 2008-07-15 11:58:31 +0100 | [diff] [blame] | 126 | unsigned long clk_rate; |
Jiri Pinkava | ac497c1 | 2011-04-13 11:59:30 +0200 | [diff] [blame] | 127 | enum s3c_nand_clk_state clk_state; |
Ben Dooks | 03680b1 | 2007-11-19 23:28:07 +0000 | [diff] [blame] | 128 | |
Ben Dooks | 2c06a08 | 2006-06-27 14:35:46 +0100 | [diff] [blame] | 129 | enum s3c_cpu_type cpu_type; |
Ben Dooks | 30821fe | 2008-07-15 11:58:31 +0100 | [diff] [blame] | 130 | |
| 131 | #ifdef CONFIG_CPU_FREQ |
| 132 | struct notifier_block freq_transition; |
| 133 | #endif |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 134 | }; |
| 135 | |
| 136 | /* conversion functions */ |
| 137 | |
| 138 | static struct s3c2410_nand_mtd *s3c2410_nand_mtd_toours(struct mtd_info *mtd) |
| 139 | { |
| 140 | return container_of(mtd, struct s3c2410_nand_mtd, mtd); |
| 141 | } |
| 142 | |
| 143 | static struct s3c2410_nand_info *s3c2410_nand_mtd_toinfo(struct mtd_info *mtd) |
| 144 | { |
| 145 | return s3c2410_nand_mtd_toours(mtd)->info; |
| 146 | } |
| 147 | |
Russell King | 3ae5eae | 2005-11-09 22:32:44 +0000 | [diff] [blame] | 148 | static struct s3c2410_nand_info *to_nand_info(struct platform_device *dev) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 149 | { |
Russell King | 3ae5eae | 2005-11-09 22:32:44 +0000 | [diff] [blame] | 150 | return platform_get_drvdata(dev); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 151 | } |
| 152 | |
Russell King | 3ae5eae | 2005-11-09 22:32:44 +0000 | [diff] [blame] | 153 | static struct s3c2410_platform_nand *to_nand_plat(struct platform_device *dev) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 154 | { |
Russell King | 3ae5eae | 2005-11-09 22:32:44 +0000 | [diff] [blame] | 155 | return dev->dev.platform_data; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 156 | } |
| 157 | |
Jiri Pinkava | ac497c1 | 2011-04-13 11:59:30 +0200 | [diff] [blame] | 158 | static inline int allow_clk_suspend(struct s3c2410_nand_info *info) |
Ben Dooks | d1fef3c | 2006-06-19 09:29:38 +0100 | [diff] [blame] | 159 | { |
Sachin Kamat | a68c5ec | 2012-07-16 16:02:25 +0530 | [diff] [blame^] | 160 | #ifdef CONFIG_MTD_NAND_S3C2410_CLKSTOP |
| 161 | return 1; |
| 162 | #else |
| 163 | return 0; |
| 164 | #endif |
Ben Dooks | d1fef3c | 2006-06-19 09:29:38 +0100 | [diff] [blame] | 165 | } |
| 166 | |
Jiri Pinkava | ac497c1 | 2011-04-13 11:59:30 +0200 | [diff] [blame] | 167 | /** |
| 168 | * s3c2410_nand_clk_set_state - Enable, disable or suspend NAND clock. |
| 169 | * @info: The controller instance. |
| 170 | * @new_state: State to which clock should be set. |
| 171 | */ |
| 172 | static void s3c2410_nand_clk_set_state(struct s3c2410_nand_info *info, |
| 173 | enum s3c_nand_clk_state new_state) |
| 174 | { |
| 175 | if (!allow_clk_suspend(info) && new_state == CLOCK_SUSPEND) |
| 176 | return; |
| 177 | |
| 178 | if (info->clk_state == CLOCK_ENABLE) { |
| 179 | if (new_state != CLOCK_ENABLE) |
| 180 | clk_disable(info->clk); |
| 181 | } else { |
| 182 | if (new_state == CLOCK_ENABLE) |
| 183 | clk_enable(info->clk); |
| 184 | } |
| 185 | |
| 186 | info->clk_state = new_state; |
| 187 | } |
| 188 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 189 | /* timing calculations */ |
| 190 | |
Ben Dooks | cfd320f | 2005-10-20 22:22:58 +0100 | [diff] [blame] | 191 | #define NS_IN_KHZ 1000000 |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 192 | |
Ben Dooks | 3db7215 | 2009-05-30 17:18:15 +0100 | [diff] [blame] | 193 | /** |
| 194 | * s3c_nand_calc_rate - calculate timing data. |
| 195 | * @wanted: The cycle time in nanoseconds. |
| 196 | * @clk: The clock rate in kHz. |
| 197 | * @max: The maximum divider value. |
| 198 | * |
| 199 | * Calculate the timing value from the given parameters. |
| 200 | */ |
Ben Dooks | 2c06a08 | 2006-06-27 14:35:46 +0100 | [diff] [blame] | 201 | static int s3c_nand_calc_rate(int wanted, unsigned long clk, int max) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 202 | { |
| 203 | int result; |
| 204 | |
Ben Dooks | 947391c | 2009-05-30 18:34:16 +0100 | [diff] [blame] | 205 | result = DIV_ROUND_UP((wanted * clk), NS_IN_KHZ); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 206 | |
| 207 | pr_debug("result %d from %ld, %d\n", result, clk, wanted); |
| 208 | |
| 209 | if (result > max) { |
Sachin Kamat | 92aeb5d | 2012-07-16 16:02:23 +0530 | [diff] [blame] | 210 | pr_err("%d ns is too big for current clock rate %ld\n", |
| 211 | wanted, clk); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 212 | return -1; |
| 213 | } |
| 214 | |
| 215 | if (result < 1) |
| 216 | result = 1; |
| 217 | |
| 218 | return result; |
| 219 | } |
| 220 | |
Ben Dooks | cfd320f | 2005-10-20 22:22:58 +0100 | [diff] [blame] | 221 | #define to_ns(ticks,clk) (((ticks) * NS_IN_KHZ) / (unsigned int)(clk)) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 222 | |
| 223 | /* controller setup */ |
| 224 | |
Ben Dooks | 3db7215 | 2009-05-30 17:18:15 +0100 | [diff] [blame] | 225 | /** |
| 226 | * s3c2410_nand_setrate - setup controller timing information. |
| 227 | * @info: The controller instance. |
| 228 | * |
| 229 | * Given the information supplied by the platform, calculate and set |
| 230 | * the necessary timing registers in the hardware to generate the |
| 231 | * necessary timing cycles to the hardware. |
| 232 | */ |
Ben Dooks | 30821fe | 2008-07-15 11:58:31 +0100 | [diff] [blame] | 233 | static int s3c2410_nand_setrate(struct s3c2410_nand_info *info) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 234 | { |
Ben Dooks | 30821fe | 2008-07-15 11:58:31 +0100 | [diff] [blame] | 235 | struct s3c2410_platform_nand *plat = info->platform; |
Ben Dooks | 2c06a08 | 2006-06-27 14:35:46 +0100 | [diff] [blame] | 236 | int tacls_max = (info->cpu_type == TYPE_S3C2412) ? 8 : 4; |
Ben Dooks | cfd320f | 2005-10-20 22:22:58 +0100 | [diff] [blame] | 237 | int tacls, twrph0, twrph1; |
Ben Dooks | 30821fe | 2008-07-15 11:58:31 +0100 | [diff] [blame] | 238 | unsigned long clkrate = clk_get_rate(info->clk); |
Nelson Castillo | 2612e52 | 2009-05-10 15:41:54 -0500 | [diff] [blame] | 239 | unsigned long uninitialized_var(set), cfg, uninitialized_var(mask); |
Ben Dooks | 30821fe | 2008-07-15 11:58:31 +0100 | [diff] [blame] | 240 | unsigned long flags; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 241 | |
| 242 | /* calculate the timing information for the controller */ |
| 243 | |
Ben Dooks | 30821fe | 2008-07-15 11:58:31 +0100 | [diff] [blame] | 244 | info->clk_rate = clkrate; |
Ben Dooks | cfd320f | 2005-10-20 22:22:58 +0100 | [diff] [blame] | 245 | clkrate /= 1000; /* turn clock into kHz for ease of use */ |
| 246 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 247 | if (plat != NULL) { |
Ben Dooks | 2c06a08 | 2006-06-27 14:35:46 +0100 | [diff] [blame] | 248 | tacls = s3c_nand_calc_rate(plat->tacls, clkrate, tacls_max); |
| 249 | twrph0 = s3c_nand_calc_rate(plat->twrph0, clkrate, 8); |
| 250 | twrph1 = s3c_nand_calc_rate(plat->twrph1, clkrate, 8); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 251 | } else { |
| 252 | /* default timings */ |
Ben Dooks | 2c06a08 | 2006-06-27 14:35:46 +0100 | [diff] [blame] | 253 | tacls = tacls_max; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 254 | twrph0 = 8; |
| 255 | twrph1 = 8; |
| 256 | } |
Thomas Gleixner | 61b03bd | 2005-11-07 11:15:49 +0000 | [diff] [blame] | 257 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 258 | if (tacls < 0 || twrph0 < 0 || twrph1 < 0) { |
Ben Dooks | 99974c6 | 2006-06-21 15:43:05 +0100 | [diff] [blame] | 259 | dev_err(info->device, "cannot get suitable timings\n"); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 260 | return -EINVAL; |
| 261 | } |
| 262 | |
Ben Dooks | 99974c6 | 2006-06-21 15:43:05 +0100 | [diff] [blame] | 263 | dev_info(info->device, "Tacls=%d, %dns Twrph0=%d %dns, Twrph1=%d %dns\n", |
David Woodhouse | e0c7d76 | 2006-05-13 18:07:53 +0100 | [diff] [blame] | 264 | tacls, to_ns(tacls, clkrate), twrph0, to_ns(twrph0, clkrate), twrph1, to_ns(twrph1, clkrate)); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 265 | |
Ben Dooks | 30821fe | 2008-07-15 11:58:31 +0100 | [diff] [blame] | 266 | switch (info->cpu_type) { |
| 267 | case TYPE_S3C2410: |
| 268 | mask = (S3C2410_NFCONF_TACLS(3) | |
| 269 | S3C2410_NFCONF_TWRPH0(7) | |
| 270 | S3C2410_NFCONF_TWRPH1(7)); |
| 271 | set = S3C2410_NFCONF_EN; |
| 272 | set |= S3C2410_NFCONF_TACLS(tacls - 1); |
| 273 | set |= S3C2410_NFCONF_TWRPH0(twrph0 - 1); |
| 274 | set |= S3C2410_NFCONF_TWRPH1(twrph1 - 1); |
| 275 | break; |
| 276 | |
| 277 | case TYPE_S3C2440: |
| 278 | case TYPE_S3C2412: |
Peter Korsgaard | a755a38 | 2009-06-03 13:46:54 +0200 | [diff] [blame] | 279 | mask = (S3C2440_NFCONF_TACLS(tacls_max - 1) | |
| 280 | S3C2440_NFCONF_TWRPH0(7) | |
| 281 | S3C2440_NFCONF_TWRPH1(7)); |
Ben Dooks | 30821fe | 2008-07-15 11:58:31 +0100 | [diff] [blame] | 282 | |
| 283 | set = S3C2440_NFCONF_TACLS(tacls - 1); |
| 284 | set |= S3C2440_NFCONF_TWRPH0(twrph0 - 1); |
| 285 | set |= S3C2440_NFCONF_TWRPH1(twrph1 - 1); |
| 286 | break; |
| 287 | |
| 288 | default: |
Ben Dooks | 30821fe | 2008-07-15 11:58:31 +0100 | [diff] [blame] | 289 | BUG(); |
| 290 | } |
| 291 | |
Ben Dooks | 30821fe | 2008-07-15 11:58:31 +0100 | [diff] [blame] | 292 | local_irq_save(flags); |
| 293 | |
| 294 | cfg = readl(info->regs + S3C2410_NFCONF); |
| 295 | cfg &= ~mask; |
| 296 | cfg |= set; |
| 297 | writel(cfg, info->regs + S3C2410_NFCONF); |
| 298 | |
| 299 | local_irq_restore(flags); |
| 300 | |
Andy Green | ae7304e | 2009-05-10 15:42:02 -0500 | [diff] [blame] | 301 | dev_dbg(info->device, "NF_CONF is 0x%lx\n", cfg); |
| 302 | |
Ben Dooks | 30821fe | 2008-07-15 11:58:31 +0100 | [diff] [blame] | 303 | return 0; |
| 304 | } |
| 305 | |
Ben Dooks | 3db7215 | 2009-05-30 17:18:15 +0100 | [diff] [blame] | 306 | /** |
| 307 | * s3c2410_nand_inithw - basic hardware initialisation |
| 308 | * @info: The hardware state. |
| 309 | * |
| 310 | * Do the basic initialisation of the hardware, using s3c2410_nand_setrate() |
| 311 | * to setup the hardware access speeds and set the controller to be enabled. |
| 312 | */ |
Ben Dooks | 30821fe | 2008-07-15 11:58:31 +0100 | [diff] [blame] | 313 | static int s3c2410_nand_inithw(struct s3c2410_nand_info *info) |
| 314 | { |
| 315 | int ret; |
| 316 | |
| 317 | ret = s3c2410_nand_setrate(info); |
| 318 | if (ret < 0) |
| 319 | return ret; |
| 320 | |
Ben Dooks | 2c06a08 | 2006-06-27 14:35:46 +0100 | [diff] [blame] | 321 | switch (info->cpu_type) { |
| 322 | case TYPE_S3C2410: |
Ben Dooks | 30821fe | 2008-07-15 11:58:31 +0100 | [diff] [blame] | 323 | default: |
Ben Dooks | 2c06a08 | 2006-06-27 14:35:46 +0100 | [diff] [blame] | 324 | break; |
| 325 | |
| 326 | case TYPE_S3C2440: |
| 327 | case TYPE_S3C2412: |
Ben Dooks | d1fef3c | 2006-06-19 09:29:38 +0100 | [diff] [blame] | 328 | /* enable the controller and de-assert nFCE */ |
| 329 | |
Ben Dooks | 2c06a08 | 2006-06-27 14:35:46 +0100 | [diff] [blame] | 330 | writel(S3C2440_NFCONT_ENABLE, info->regs + S3C2440_NFCONT); |
Ben Dooks | a4f957f | 2005-06-20 12:48:25 +0100 | [diff] [blame] | 331 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 332 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 333 | return 0; |
| 334 | } |
| 335 | |
Ben Dooks | 3db7215 | 2009-05-30 17:18:15 +0100 | [diff] [blame] | 336 | /** |
| 337 | * s3c2410_nand_select_chip - select the given nand chip |
| 338 | * @mtd: The MTD instance for this chip. |
| 339 | * @chip: The chip number. |
| 340 | * |
| 341 | * This is called by the MTD layer to either select a given chip for the |
| 342 | * @mtd instance, or to indicate that the access has finished and the |
| 343 | * chip can be de-selected. |
| 344 | * |
| 345 | * The routine ensures that the nFCE line is correctly setup, and any |
| 346 | * platform specific selection code is called to route nFCE to the specific |
| 347 | * chip. |
| 348 | */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 349 | static void s3c2410_nand_select_chip(struct mtd_info *mtd, int chip) |
| 350 | { |
| 351 | struct s3c2410_nand_info *info; |
Thomas Gleixner | 61b03bd | 2005-11-07 11:15:49 +0000 | [diff] [blame] | 352 | struct s3c2410_nand_mtd *nmtd; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 353 | struct nand_chip *this = mtd->priv; |
| 354 | unsigned long cur; |
| 355 | |
| 356 | nmtd = this->priv; |
| 357 | info = nmtd->info; |
| 358 | |
Jiri Pinkava | ac497c1 | 2011-04-13 11:59:30 +0200 | [diff] [blame] | 359 | if (chip != -1) |
| 360 | s3c2410_nand_clk_set_state(info, CLOCK_ENABLE); |
Ben Dooks | d1fef3c | 2006-06-19 09:29:38 +0100 | [diff] [blame] | 361 | |
Ben Dooks | 2c06a08 | 2006-06-27 14:35:46 +0100 | [diff] [blame] | 362 | cur = readl(info->sel_reg); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 363 | |
| 364 | if (chip == -1) { |
Ben Dooks | 2c06a08 | 2006-06-27 14:35:46 +0100 | [diff] [blame] | 365 | cur |= info->sel_bit; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 366 | } else { |
Ben Dooks | fb8d82a | 2005-07-06 21:05:10 +0100 | [diff] [blame] | 367 | if (nmtd->set != NULL && chip > nmtd->set->nr_chips) { |
Ben Dooks | 99974c6 | 2006-06-21 15:43:05 +0100 | [diff] [blame] | 368 | dev_err(info->device, "invalid chip %d\n", chip); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 369 | return; |
| 370 | } |
| 371 | |
| 372 | if (info->platform != NULL) { |
| 373 | if (info->platform->select_chip != NULL) |
David Woodhouse | e0c7d76 | 2006-05-13 18:07:53 +0100 | [diff] [blame] | 374 | (info->platform->select_chip) (nmtd->set, chip); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 375 | } |
| 376 | |
Ben Dooks | 2c06a08 | 2006-06-27 14:35:46 +0100 | [diff] [blame] | 377 | cur &= ~info->sel_bit; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 378 | } |
| 379 | |
Ben Dooks | 2c06a08 | 2006-06-27 14:35:46 +0100 | [diff] [blame] | 380 | writel(cur, info->sel_reg); |
Ben Dooks | d1fef3c | 2006-06-19 09:29:38 +0100 | [diff] [blame] | 381 | |
Jiri Pinkava | ac497c1 | 2011-04-13 11:59:30 +0200 | [diff] [blame] | 382 | if (chip == -1) |
| 383 | s3c2410_nand_clk_set_state(info, CLOCK_SUSPEND); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 384 | } |
| 385 | |
Ben Dooks | ad3b5fb | 2006-06-19 09:43:23 +0100 | [diff] [blame] | 386 | /* s3c2410_nand_hwcontrol |
Ben Dooks | a4f957f | 2005-06-20 12:48:25 +0100 | [diff] [blame] | 387 | * |
Ben Dooks | ad3b5fb | 2006-06-19 09:43:23 +0100 | [diff] [blame] | 388 | * Issue command and address cycles to the chip |
Ben Dooks | a4f957f | 2005-06-20 12:48:25 +0100 | [diff] [blame] | 389 | */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 390 | |
Thomas Gleixner | 7abd3ef | 2006-05-23 23:25:53 +0200 | [diff] [blame] | 391 | static void s3c2410_nand_hwcontrol(struct mtd_info *mtd, int cmd, |
David Woodhouse | f906887 | 2006-06-10 00:53:16 +0100 | [diff] [blame] | 392 | unsigned int ctrl) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 393 | { |
| 394 | struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd); |
David Woodhouse | c9ac597 | 2006-11-30 08:17:38 +0000 | [diff] [blame] | 395 | |
Thomas Gleixner | 7abd3ef | 2006-05-23 23:25:53 +0200 | [diff] [blame] | 396 | if (cmd == NAND_CMD_NONE) |
| 397 | return; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 398 | |
David Woodhouse | f906887 | 2006-06-10 00:53:16 +0100 | [diff] [blame] | 399 | if (ctrl & NAND_CLE) |
Thomas Gleixner | 7abd3ef | 2006-05-23 23:25:53 +0200 | [diff] [blame] | 400 | writeb(cmd, info->regs + S3C2410_NFCMD); |
| 401 | else |
| 402 | writeb(cmd, info->regs + S3C2410_NFADDR); |
Ben Dooks | a4f957f | 2005-06-20 12:48:25 +0100 | [diff] [blame] | 403 | } |
| 404 | |
| 405 | /* command and control functions */ |
| 406 | |
David Woodhouse | f906887 | 2006-06-10 00:53:16 +0100 | [diff] [blame] | 407 | static void s3c2440_nand_hwcontrol(struct mtd_info *mtd, int cmd, |
| 408 | unsigned int ctrl) |
Ben Dooks | a4f957f | 2005-06-20 12:48:25 +0100 | [diff] [blame] | 409 | { |
| 410 | struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd); |
Ben Dooks | a4f957f | 2005-06-20 12:48:25 +0100 | [diff] [blame] | 411 | |
Thomas Gleixner | 7abd3ef | 2006-05-23 23:25:53 +0200 | [diff] [blame] | 412 | if (cmd == NAND_CMD_NONE) |
| 413 | return; |
Ben Dooks | a4f957f | 2005-06-20 12:48:25 +0100 | [diff] [blame] | 414 | |
David Woodhouse | f906887 | 2006-06-10 00:53:16 +0100 | [diff] [blame] | 415 | if (ctrl & NAND_CLE) |
Thomas Gleixner | 7abd3ef | 2006-05-23 23:25:53 +0200 | [diff] [blame] | 416 | writeb(cmd, info->regs + S3C2440_NFCMD); |
| 417 | else |
| 418 | writeb(cmd, info->regs + S3C2440_NFADDR); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 419 | } |
| 420 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 421 | /* s3c2410_nand_devready() |
| 422 | * |
| 423 | * returns 0 if the nand is busy, 1 if it is ready |
| 424 | */ |
| 425 | |
| 426 | static int s3c2410_nand_devready(struct mtd_info *mtd) |
| 427 | { |
| 428 | struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 429 | return readb(info->regs + S3C2410_NFSTAT) & S3C2410_NFSTAT_BUSY; |
| 430 | } |
| 431 | |
Ben Dooks | 2c06a08 | 2006-06-27 14:35:46 +0100 | [diff] [blame] | 432 | static int s3c2440_nand_devready(struct mtd_info *mtd) |
| 433 | { |
| 434 | struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd); |
| 435 | return readb(info->regs + S3C2440_NFSTAT) & S3C2440_NFSTAT_READY; |
| 436 | } |
| 437 | |
| 438 | static int s3c2412_nand_devready(struct mtd_info *mtd) |
| 439 | { |
| 440 | struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd); |
| 441 | return readb(info->regs + S3C2412_NFSTAT) & S3C2412_NFSTAT_READY; |
| 442 | } |
| 443 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 444 | /* ECC handling functions */ |
| 445 | |
Ben Dooks | 2c06a08 | 2006-06-27 14:35:46 +0100 | [diff] [blame] | 446 | static int s3c2410_nand_correct_data(struct mtd_info *mtd, u_char *dat, |
| 447 | u_char *read_ecc, u_char *calc_ecc) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 448 | { |
Ben Dooks | a259324 | 2007-02-02 16:59:33 +0000 | [diff] [blame] | 449 | struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd); |
| 450 | unsigned int diff0, diff1, diff2; |
| 451 | unsigned int bit, byte; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 452 | |
Ben Dooks | a259324 | 2007-02-02 16:59:33 +0000 | [diff] [blame] | 453 | pr_debug("%s(%p,%p,%p,%p)\n", __func__, mtd, dat, read_ecc, calc_ecc); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 454 | |
Ben Dooks | a259324 | 2007-02-02 16:59:33 +0000 | [diff] [blame] | 455 | diff0 = read_ecc[0] ^ calc_ecc[0]; |
| 456 | diff1 = read_ecc[1] ^ calc_ecc[1]; |
| 457 | diff2 = read_ecc[2] ^ calc_ecc[2]; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 458 | |
Ben Dooks | a259324 | 2007-02-02 16:59:33 +0000 | [diff] [blame] | 459 | pr_debug("%s: rd %02x%02x%02x calc %02x%02x%02x diff %02x%02x%02x\n", |
| 460 | __func__, |
| 461 | read_ecc[0], read_ecc[1], read_ecc[2], |
| 462 | calc_ecc[0], calc_ecc[1], calc_ecc[2], |
| 463 | diff0, diff1, diff2); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 464 | |
Ben Dooks | a259324 | 2007-02-02 16:59:33 +0000 | [diff] [blame] | 465 | if (diff0 == 0 && diff1 == 0 && diff2 == 0) |
| 466 | return 0; /* ECC is ok */ |
| 467 | |
Ben Dooks | c45c6c6 | 2008-04-15 11:36:20 +0100 | [diff] [blame] | 468 | /* sometimes people do not think about using the ECC, so check |
| 469 | * to see if we have an 0xff,0xff,0xff read ECC and then ignore |
| 470 | * the error, on the assumption that this is an un-eccd page. |
| 471 | */ |
| 472 | if (read_ecc[0] == 0xff && read_ecc[1] == 0xff && read_ecc[2] == 0xff |
| 473 | && info->platform->ignore_unset_ecc) |
| 474 | return 0; |
| 475 | |
Ben Dooks | a259324 | 2007-02-02 16:59:33 +0000 | [diff] [blame] | 476 | /* Can we correct this ECC (ie, one row and column change). |
| 477 | * Note, this is similar to the 256 error code on smartmedia */ |
| 478 | |
| 479 | if (((diff0 ^ (diff0 >> 1)) & 0x55) == 0x55 && |
| 480 | ((diff1 ^ (diff1 >> 1)) & 0x55) == 0x55 && |
| 481 | ((diff2 ^ (diff2 >> 1)) & 0x55) == 0x55) { |
| 482 | /* calculate the bit position of the error */ |
| 483 | |
Matt Reimer | d0bf379 | 2007-10-18 18:02:43 -0700 | [diff] [blame] | 484 | bit = ((diff2 >> 3) & 1) | |
| 485 | ((diff2 >> 4) & 2) | |
| 486 | ((diff2 >> 5) & 4); |
Ben Dooks | a259324 | 2007-02-02 16:59:33 +0000 | [diff] [blame] | 487 | |
| 488 | /* calculate the byte position of the error */ |
| 489 | |
Matt Reimer | d0bf379 | 2007-10-18 18:02:43 -0700 | [diff] [blame] | 490 | byte = ((diff2 << 7) & 0x100) | |
| 491 | ((diff1 << 0) & 0x80) | |
| 492 | ((diff1 << 1) & 0x40) | |
| 493 | ((diff1 << 2) & 0x20) | |
| 494 | ((diff1 << 3) & 0x10) | |
| 495 | ((diff0 >> 4) & 0x08) | |
| 496 | ((diff0 >> 3) & 0x04) | |
| 497 | ((diff0 >> 2) & 0x02) | |
| 498 | ((diff0 >> 1) & 0x01); |
Ben Dooks | a259324 | 2007-02-02 16:59:33 +0000 | [diff] [blame] | 499 | |
| 500 | dev_dbg(info->device, "correcting error bit %d, byte %d\n", |
| 501 | bit, byte); |
| 502 | |
| 503 | dat[byte] ^= (1 << bit); |
| 504 | return 1; |
| 505 | } |
| 506 | |
| 507 | /* if there is only one bit difference in the ECC, then |
| 508 | * one of only a row or column parity has changed, which |
| 509 | * means the error is most probably in the ECC itself */ |
| 510 | |
| 511 | diff0 |= (diff1 << 8); |
| 512 | diff0 |= (diff2 << 16); |
| 513 | |
| 514 | if ((diff0 & ~(1<<fls(diff0))) == 0) |
| 515 | return 1; |
| 516 | |
Matt Reimer | 4fac9f6 | 2007-10-18 18:02:44 -0700 | [diff] [blame] | 517 | return -1; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 518 | } |
| 519 | |
Ben Dooks | a4f957f | 2005-06-20 12:48:25 +0100 | [diff] [blame] | 520 | /* ECC functions |
| 521 | * |
| 522 | * These allow the s3c2410 and s3c2440 to use the controller's ECC |
| 523 | * generator block to ECC the data as it passes through] |
| 524 | */ |
| 525 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 526 | static void s3c2410_nand_enable_hwecc(struct mtd_info *mtd, int mode) |
| 527 | { |
| 528 | struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd); |
| 529 | unsigned long ctrl; |
| 530 | |
| 531 | ctrl = readl(info->regs + S3C2410_NFCONF); |
| 532 | ctrl |= S3C2410_NFCONF_INITECC; |
| 533 | writel(ctrl, info->regs + S3C2410_NFCONF); |
| 534 | } |
| 535 | |
Matthieu CASTET | 4f65992 | 2007-02-13 12:30:38 +0100 | [diff] [blame] | 536 | static void s3c2412_nand_enable_hwecc(struct mtd_info *mtd, int mode) |
| 537 | { |
| 538 | struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd); |
| 539 | unsigned long ctrl; |
| 540 | |
| 541 | ctrl = readl(info->regs + S3C2440_NFCONT); |
| 542 | writel(ctrl | S3C2412_NFCONT_INIT_MAIN_ECC, info->regs + S3C2440_NFCONT); |
| 543 | } |
| 544 | |
Ben Dooks | a4f957f | 2005-06-20 12:48:25 +0100 | [diff] [blame] | 545 | static void s3c2440_nand_enable_hwecc(struct mtd_info *mtd, int mode) |
| 546 | { |
| 547 | struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd); |
| 548 | unsigned long ctrl; |
| 549 | |
| 550 | ctrl = readl(info->regs + S3C2440_NFCONT); |
| 551 | writel(ctrl | S3C2440_NFCONT_INITECC, info->regs + S3C2440_NFCONT); |
| 552 | } |
| 553 | |
David Woodhouse | e0c7d76 | 2006-05-13 18:07:53 +0100 | [diff] [blame] | 554 | static int s3c2410_nand_calculate_ecc(struct mtd_info *mtd, const u_char *dat, u_char *ecc_code) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 555 | { |
| 556 | struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd); |
| 557 | |
| 558 | ecc_code[0] = readb(info->regs + S3C2410_NFECC + 0); |
| 559 | ecc_code[1] = readb(info->regs + S3C2410_NFECC + 1); |
| 560 | ecc_code[2] = readb(info->regs + S3C2410_NFECC + 2); |
| 561 | |
Ben Dooks | a259324 | 2007-02-02 16:59:33 +0000 | [diff] [blame] | 562 | pr_debug("%s: returning ecc %02x%02x%02x\n", __func__, |
| 563 | ecc_code[0], ecc_code[1], ecc_code[2]); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 564 | |
| 565 | return 0; |
| 566 | } |
| 567 | |
Matthieu CASTET | 4f65992 | 2007-02-13 12:30:38 +0100 | [diff] [blame] | 568 | static int s3c2412_nand_calculate_ecc(struct mtd_info *mtd, const u_char *dat, u_char *ecc_code) |
| 569 | { |
| 570 | struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd); |
| 571 | unsigned long ecc = readl(info->regs + S3C2412_NFMECC0); |
| 572 | |
| 573 | ecc_code[0] = ecc; |
| 574 | ecc_code[1] = ecc >> 8; |
| 575 | ecc_code[2] = ecc >> 16; |
| 576 | |
| 577 | pr_debug("calculate_ecc: returning ecc %02x,%02x,%02x\n", ecc_code[0], ecc_code[1], ecc_code[2]); |
| 578 | |
| 579 | return 0; |
| 580 | } |
| 581 | |
David Woodhouse | e0c7d76 | 2006-05-13 18:07:53 +0100 | [diff] [blame] | 582 | static int s3c2440_nand_calculate_ecc(struct mtd_info *mtd, const u_char *dat, u_char *ecc_code) |
Ben Dooks | a4f957f | 2005-06-20 12:48:25 +0100 | [diff] [blame] | 583 | { |
| 584 | struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd); |
| 585 | unsigned long ecc = readl(info->regs + S3C2440_NFMECC0); |
| 586 | |
| 587 | ecc_code[0] = ecc; |
| 588 | ecc_code[1] = ecc >> 8; |
| 589 | ecc_code[2] = ecc >> 16; |
| 590 | |
Ben Dooks | 71d54f3 | 2008-04-15 11:36:19 +0100 | [diff] [blame] | 591 | pr_debug("%s: returning ecc %06lx\n", __func__, ecc & 0xffffff); |
Ben Dooks | a4f957f | 2005-06-20 12:48:25 +0100 | [diff] [blame] | 592 | |
| 593 | return 0; |
| 594 | } |
| 595 | |
Ben Dooks | a4f957f | 2005-06-20 12:48:25 +0100 | [diff] [blame] | 596 | /* over-ride the standard functions for a little more speed. We can |
| 597 | * use read/write block to move the data buffers to/from the controller |
| 598 | */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 599 | |
| 600 | static void s3c2410_nand_read_buf(struct mtd_info *mtd, u_char *buf, int len) |
| 601 | { |
| 602 | struct nand_chip *this = mtd->priv; |
| 603 | readsb(this->IO_ADDR_R, buf, len); |
| 604 | } |
| 605 | |
Matt Reimer | b773bb2 | 2007-10-18 17:43:07 -0700 | [diff] [blame] | 606 | static void s3c2440_nand_read_buf(struct mtd_info *mtd, u_char *buf, int len) |
| 607 | { |
| 608 | struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd); |
Ben Dooks | dea2aa6 | 2009-05-30 18:30:18 +0100 | [diff] [blame] | 609 | |
| 610 | readsl(info->regs + S3C2440_NFDATA, buf, len >> 2); |
| 611 | |
| 612 | /* cleanup if we've got less than a word to do */ |
| 613 | if (len & 3) { |
| 614 | buf += len & ~3; |
| 615 | |
| 616 | for (; len & 3; len--) |
| 617 | *buf++ = readb(info->regs + S3C2440_NFDATA); |
| 618 | } |
Matt Reimer | b773bb2 | 2007-10-18 17:43:07 -0700 | [diff] [blame] | 619 | } |
| 620 | |
David Woodhouse | e0c7d76 | 2006-05-13 18:07:53 +0100 | [diff] [blame] | 621 | static void s3c2410_nand_write_buf(struct mtd_info *mtd, const u_char *buf, int len) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 622 | { |
| 623 | struct nand_chip *this = mtd->priv; |
| 624 | writesb(this->IO_ADDR_W, buf, len); |
| 625 | } |
| 626 | |
Matt Reimer | b773bb2 | 2007-10-18 17:43:07 -0700 | [diff] [blame] | 627 | static void s3c2440_nand_write_buf(struct mtd_info *mtd, const u_char *buf, int len) |
| 628 | { |
| 629 | struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd); |
Ben Dooks | dea2aa6 | 2009-05-30 18:30:18 +0100 | [diff] [blame] | 630 | |
| 631 | writesl(info->regs + S3C2440_NFDATA, buf, len >> 2); |
| 632 | |
| 633 | /* cleanup any fractional write */ |
| 634 | if (len & 3) { |
| 635 | buf += len & ~3; |
| 636 | |
| 637 | for (; len & 3; len--, buf++) |
| 638 | writeb(*buf, info->regs + S3C2440_NFDATA); |
| 639 | } |
Matt Reimer | b773bb2 | 2007-10-18 17:43:07 -0700 | [diff] [blame] | 640 | } |
| 641 | |
Ben Dooks | 30821fe | 2008-07-15 11:58:31 +0100 | [diff] [blame] | 642 | /* cpufreq driver support */ |
| 643 | |
| 644 | #ifdef CONFIG_CPU_FREQ |
| 645 | |
| 646 | static int s3c2410_nand_cpufreq_transition(struct notifier_block *nb, |
| 647 | unsigned long val, void *data) |
| 648 | { |
| 649 | struct s3c2410_nand_info *info; |
| 650 | unsigned long newclk; |
| 651 | |
| 652 | info = container_of(nb, struct s3c2410_nand_info, freq_transition); |
| 653 | newclk = clk_get_rate(info->clk); |
| 654 | |
| 655 | if ((val == CPUFREQ_POSTCHANGE && newclk < info->clk_rate) || |
| 656 | (val == CPUFREQ_PRECHANGE && newclk > info->clk_rate)) { |
| 657 | s3c2410_nand_setrate(info); |
| 658 | } |
| 659 | |
| 660 | return 0; |
| 661 | } |
| 662 | |
| 663 | static inline int s3c2410_nand_cpufreq_register(struct s3c2410_nand_info *info) |
| 664 | { |
| 665 | info->freq_transition.notifier_call = s3c2410_nand_cpufreq_transition; |
| 666 | |
| 667 | return cpufreq_register_notifier(&info->freq_transition, |
| 668 | CPUFREQ_TRANSITION_NOTIFIER); |
| 669 | } |
| 670 | |
| 671 | static inline void s3c2410_nand_cpufreq_deregister(struct s3c2410_nand_info *info) |
| 672 | { |
| 673 | cpufreq_unregister_notifier(&info->freq_transition, |
| 674 | CPUFREQ_TRANSITION_NOTIFIER); |
| 675 | } |
| 676 | |
| 677 | #else |
| 678 | static inline int s3c2410_nand_cpufreq_register(struct s3c2410_nand_info *info) |
| 679 | { |
| 680 | return 0; |
| 681 | } |
| 682 | |
| 683 | static inline void s3c2410_nand_cpufreq_deregister(struct s3c2410_nand_info *info) |
| 684 | { |
| 685 | } |
| 686 | #endif |
| 687 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 688 | /* device management functions */ |
| 689 | |
Ben Dooks | ec0482e | 2009-05-30 16:55:29 +0100 | [diff] [blame] | 690 | static int s3c24xx_nand_remove(struct platform_device *pdev) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 691 | { |
Russell King | 3ae5eae | 2005-11-09 22:32:44 +0000 | [diff] [blame] | 692 | struct s3c2410_nand_info *info = to_nand_info(pdev); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 693 | |
Russell King | 3ae5eae | 2005-11-09 22:32:44 +0000 | [diff] [blame] | 694 | platform_set_drvdata(pdev, NULL); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 695 | |
Thomas Gleixner | 61b03bd | 2005-11-07 11:15:49 +0000 | [diff] [blame] | 696 | if (info == NULL) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 697 | return 0; |
| 698 | |
Ben Dooks | 30821fe | 2008-07-15 11:58:31 +0100 | [diff] [blame] | 699 | s3c2410_nand_cpufreq_deregister(info); |
| 700 | |
| 701 | /* Release all our mtds and their partitions, then go through |
| 702 | * freeing the resources used |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 703 | */ |
Thomas Gleixner | 61b03bd | 2005-11-07 11:15:49 +0000 | [diff] [blame] | 704 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 705 | if (info->mtds != NULL) { |
| 706 | struct s3c2410_nand_mtd *ptr = info->mtds; |
| 707 | int mtdno; |
| 708 | |
| 709 | for (mtdno = 0; mtdno < info->mtd_count; mtdno++, ptr++) { |
| 710 | pr_debug("releasing mtd %d (%p)\n", mtdno, ptr); |
| 711 | nand_release(&ptr->mtd); |
| 712 | } |
| 713 | |
| 714 | kfree(info->mtds); |
| 715 | } |
| 716 | |
| 717 | /* free the common resources */ |
| 718 | |
Jonghwan Choi | 4aa1062 | 2011-07-21 15:33:58 +0900 | [diff] [blame] | 719 | if (!IS_ERR(info->clk)) { |
Jiri Pinkava | ac497c1 | 2011-04-13 11:59:30 +0200 | [diff] [blame] | 720 | s3c2410_nand_clk_set_state(info, CLOCK_DISABLE); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 721 | clk_put(info->clk); |
| 722 | } |
| 723 | |
| 724 | if (info->regs != NULL) { |
| 725 | iounmap(info->regs); |
| 726 | info->regs = NULL; |
| 727 | } |
| 728 | |
| 729 | if (info->area != NULL) { |
| 730 | release_resource(info->area); |
| 731 | kfree(info->area); |
| 732 | info->area = NULL; |
| 733 | } |
| 734 | |
| 735 | kfree(info); |
| 736 | |
| 737 | return 0; |
| 738 | } |
| 739 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 740 | static int s3c2410_nand_add_partition(struct s3c2410_nand_info *info, |
| 741 | struct s3c2410_nand_mtd *mtd, |
| 742 | struct s3c2410_nand_set *set) |
| 743 | { |
Dmitry Eremin-Solenikov | 599501a | 2011-06-02 18:01:02 +0400 | [diff] [blame] | 744 | if (set) |
| 745 | mtd->mtd.name = set->name; |
Andy Green | ed27f02 | 2009-05-10 15:42:09 -0500 | [diff] [blame] | 746 | |
Artem Bityutskiy | 42d7fbe | 2012-03-09 19:24:26 +0200 | [diff] [blame] | 747 | return mtd_device_parse_register(&mtd->mtd, NULL, NULL, |
| 748 | set->partitions, set->nr_partitions); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 749 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 750 | |
Ben Dooks | 3db7215 | 2009-05-30 17:18:15 +0100 | [diff] [blame] | 751 | /** |
| 752 | * s3c2410_nand_init_chip - initialise a single instance of an chip |
| 753 | * @info: The base NAND controller the chip is on. |
| 754 | * @nmtd: The new controller MTD instance to fill in. |
| 755 | * @set: The information passed from the board specific platform data. |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 756 | * |
Ben Dooks | 3db7215 | 2009-05-30 17:18:15 +0100 | [diff] [blame] | 757 | * Initialise the given @nmtd from the information in @info and @set. This |
| 758 | * readies the structure for use with the MTD layer functions by ensuring |
| 759 | * all pointers are setup and the necessary control routines selected. |
| 760 | */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 761 | static void s3c2410_nand_init_chip(struct s3c2410_nand_info *info, |
| 762 | struct s3c2410_nand_mtd *nmtd, |
| 763 | struct s3c2410_nand_set *set) |
| 764 | { |
| 765 | struct nand_chip *chip = &nmtd->chip; |
Ben Dooks | 2c06a08 | 2006-06-27 14:35:46 +0100 | [diff] [blame] | 766 | void __iomem *regs = info->regs; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 767 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 768 | chip->write_buf = s3c2410_nand_write_buf; |
| 769 | chip->read_buf = s3c2410_nand_read_buf; |
| 770 | chip->select_chip = s3c2410_nand_select_chip; |
| 771 | chip->chip_delay = 50; |
| 772 | chip->priv = nmtd; |
Ben Dooks | 74218fe | 2009-11-02 18:12:51 +0000 | [diff] [blame] | 773 | chip->options = set->options; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 774 | chip->controller = &info->controller; |
| 775 | |
Ben Dooks | 2c06a08 | 2006-06-27 14:35:46 +0100 | [diff] [blame] | 776 | switch (info->cpu_type) { |
| 777 | case TYPE_S3C2410: |
| 778 | chip->IO_ADDR_W = regs + S3C2410_NFDATA; |
| 779 | info->sel_reg = regs + S3C2410_NFCONF; |
| 780 | info->sel_bit = S3C2410_NFCONF_nFCE; |
| 781 | chip->cmd_ctrl = s3c2410_nand_hwcontrol; |
| 782 | chip->dev_ready = s3c2410_nand_devready; |
| 783 | break; |
| 784 | |
| 785 | case TYPE_S3C2440: |
| 786 | chip->IO_ADDR_W = regs + S3C2440_NFDATA; |
| 787 | info->sel_reg = regs + S3C2440_NFCONT; |
| 788 | info->sel_bit = S3C2440_NFCONT_nFCE; |
| 789 | chip->cmd_ctrl = s3c2440_nand_hwcontrol; |
| 790 | chip->dev_ready = s3c2440_nand_devready; |
Matt Reimer | b773bb2 | 2007-10-18 17:43:07 -0700 | [diff] [blame] | 791 | chip->read_buf = s3c2440_nand_read_buf; |
| 792 | chip->write_buf = s3c2440_nand_write_buf; |
Ben Dooks | 2c06a08 | 2006-06-27 14:35:46 +0100 | [diff] [blame] | 793 | break; |
| 794 | |
| 795 | case TYPE_S3C2412: |
| 796 | chip->IO_ADDR_W = regs + S3C2440_NFDATA; |
| 797 | info->sel_reg = regs + S3C2440_NFCONT; |
| 798 | info->sel_bit = S3C2412_NFCONT_nFCE0; |
| 799 | chip->cmd_ctrl = s3c2440_nand_hwcontrol; |
| 800 | chip->dev_ready = s3c2412_nand_devready; |
| 801 | |
| 802 | if (readl(regs + S3C2410_NFCONF) & S3C2412_NFCONF_NANDBOOT) |
| 803 | dev_info(info->device, "System booted from NAND\n"); |
| 804 | |
| 805 | break; |
| 806 | } |
| 807 | |
| 808 | chip->IO_ADDR_R = chip->IO_ADDR_W; |
Ben Dooks | a4f957f | 2005-06-20 12:48:25 +0100 | [diff] [blame] | 809 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 810 | nmtd->info = info; |
| 811 | nmtd->mtd.priv = chip; |
David Woodhouse | 552d920 | 2006-05-14 01:20:46 +0100 | [diff] [blame] | 812 | nmtd->mtd.owner = THIS_MODULE; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 813 | nmtd->set = set; |
| 814 | |
Sachin Kamat | a68c5ec | 2012-07-16 16:02:25 +0530 | [diff] [blame^] | 815 | #ifdef CONFIG_MTD_NAND_S3C2410_HWECC |
| 816 | chip->ecc.calculate = s3c2410_nand_calculate_ecc; |
| 817 | chip->ecc.correct = s3c2410_nand_correct_data; |
| 818 | chip->ecc.mode = NAND_ECC_HW; |
| 819 | chip->ecc.strength = 1; |
| 820 | |
| 821 | switch (info->cpu_type) { |
| 822 | case TYPE_S3C2410: |
| 823 | chip->ecc.hwctl = s3c2410_nand_enable_hwecc; |
Thomas Gleixner | 6dfc6d2 | 2006-05-23 12:00:46 +0200 | [diff] [blame] | 824 | chip->ecc.calculate = s3c2410_nand_calculate_ecc; |
Sachin Kamat | a68c5ec | 2012-07-16 16:02:25 +0530 | [diff] [blame^] | 825 | break; |
Ben Dooks | a4f957f | 2005-06-20 12:48:25 +0100 | [diff] [blame] | 826 | |
Sachin Kamat | a68c5ec | 2012-07-16 16:02:25 +0530 | [diff] [blame^] | 827 | case TYPE_S3C2412: |
| 828 | chip->ecc.hwctl = s3c2412_nand_enable_hwecc; |
| 829 | chip->ecc.calculate = s3c2412_nand_calculate_ecc; |
| 830 | break; |
Ben Dooks | 2c06a08 | 2006-06-27 14:35:46 +0100 | [diff] [blame] | 831 | |
Sachin Kamat | a68c5ec | 2012-07-16 16:02:25 +0530 | [diff] [blame^] | 832 | case TYPE_S3C2440: |
| 833 | chip->ecc.hwctl = s3c2440_nand_enable_hwecc; |
| 834 | chip->ecc.calculate = s3c2440_nand_calculate_ecc; |
| 835 | break; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 836 | } |
Sachin Kamat | a68c5ec | 2012-07-16 16:02:25 +0530 | [diff] [blame^] | 837 | #else |
| 838 | chip->ecc.mode = NAND_ECC_SOFT; |
| 839 | #endif |
Ben Dooks | 1c21ab6 | 2008-04-15 11:36:21 +0100 | [diff] [blame] | 840 | |
| 841 | if (set->ecc_layout != NULL) |
| 842 | chip->ecc.layout = set->ecc_layout; |
Ben Dooks | 37e5ffa | 2008-04-15 11:36:22 +0100 | [diff] [blame] | 843 | |
| 844 | if (set->disable_ecc) |
| 845 | chip->ecc.mode = NAND_ECC_NONE; |
Andy Green | 8c3e843 | 2009-05-10 15:41:25 -0500 | [diff] [blame] | 846 | |
| 847 | switch (chip->ecc.mode) { |
| 848 | case NAND_ECC_NONE: |
| 849 | dev_info(info->device, "NAND ECC disabled\n"); |
| 850 | break; |
| 851 | case NAND_ECC_SOFT: |
| 852 | dev_info(info->device, "NAND soft ECC\n"); |
| 853 | break; |
| 854 | case NAND_ECC_HW: |
| 855 | dev_info(info->device, "NAND hardware ECC\n"); |
| 856 | break; |
| 857 | default: |
| 858 | dev_info(info->device, "NAND ECC UNKNOWN\n"); |
| 859 | break; |
| 860 | } |
Michel Pollet | 9db41f9 | 2009-05-13 16:54:14 +0100 | [diff] [blame] | 861 | |
| 862 | /* If you use u-boot BBT creation code, specifying this flag will |
| 863 | * let the kernel fish out the BBT from the NAND, and also skip the |
| 864 | * full NAND scan that can take 1/2s or so. Little things... */ |
Brian Norris | a40f734 | 2011-05-31 16:31:22 -0700 | [diff] [blame] | 865 | if (set->flash_bbt) { |
Brian Norris | bb9ebd4 | 2011-05-31 16:31:23 -0700 | [diff] [blame] | 866 | chip->bbt_options |= NAND_BBT_USE_FLASH; |
Brian Norris | a40f734 | 2011-05-31 16:31:22 -0700 | [diff] [blame] | 867 | chip->options |= NAND_SKIP_BBTSCAN; |
| 868 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 869 | } |
| 870 | |
Ben Dooks | 3db7215 | 2009-05-30 17:18:15 +0100 | [diff] [blame] | 871 | /** |
| 872 | * s3c2410_nand_update_chip - post probe update |
| 873 | * @info: The controller instance. |
| 874 | * @nmtd: The driver version of the MTD instance. |
Ben Dooks | 71d54f3 | 2008-04-15 11:36:19 +0100 | [diff] [blame] | 875 | * |
André Goddard Rosa | af901ca | 2009-11-14 13:09:05 -0200 | [diff] [blame] | 876 | * This routine is called after the chip probe has successfully completed |
Ben Dooks | 3db7215 | 2009-05-30 17:18:15 +0100 | [diff] [blame] | 877 | * and the relevant per-chip information updated. This call ensure that |
| 878 | * we update the internal state accordingly. |
| 879 | * |
| 880 | * The internal state is currently limited to the ECC state information. |
| 881 | */ |
Ben Dooks | 71d54f3 | 2008-04-15 11:36:19 +0100 | [diff] [blame] | 882 | static void s3c2410_nand_update_chip(struct s3c2410_nand_info *info, |
| 883 | struct s3c2410_nand_mtd *nmtd) |
| 884 | { |
| 885 | struct nand_chip *chip = &nmtd->chip; |
| 886 | |
Ben Dooks | 451d339 | 2008-05-20 17:32:14 +0100 | [diff] [blame] | 887 | dev_dbg(info->device, "chip %p => page shift %d\n", |
| 888 | chip, chip->page_shift); |
Ben Dooks | 71d54f3 | 2008-04-15 11:36:19 +0100 | [diff] [blame] | 889 | |
Andy Green | 8c3e843 | 2009-05-10 15:41:25 -0500 | [diff] [blame] | 890 | if (chip->ecc.mode != NAND_ECC_HW) |
| 891 | return; |
| 892 | |
Ben Dooks | 71d54f3 | 2008-04-15 11:36:19 +0100 | [diff] [blame] | 893 | /* change the behaviour depending on wether we are using |
| 894 | * the large or small page nand device */ |
| 895 | |
Andy Green | 8c3e843 | 2009-05-10 15:41:25 -0500 | [diff] [blame] | 896 | if (chip->page_shift > 10) { |
| 897 | chip->ecc.size = 256; |
| 898 | chip->ecc.bytes = 3; |
| 899 | } else { |
| 900 | chip->ecc.size = 512; |
| 901 | chip->ecc.bytes = 3; |
| 902 | chip->ecc.layout = &nand_hw_eccoob; |
Ben Dooks | 71d54f3 | 2008-04-15 11:36:19 +0100 | [diff] [blame] | 903 | } |
| 904 | } |
| 905 | |
Ben Dooks | ec0482e | 2009-05-30 16:55:29 +0100 | [diff] [blame] | 906 | /* s3c24xx_nand_probe |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 907 | * |
| 908 | * called by device layer when it finds a device matching |
| 909 | * one our driver can handled. This code checks to see if |
| 910 | * it can allocate all necessary resources then calls the |
| 911 | * nand layer to look for devices |
| 912 | */ |
Ben Dooks | ec0482e | 2009-05-30 16:55:29 +0100 | [diff] [blame] | 913 | static int s3c24xx_nand_probe(struct platform_device *pdev) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 914 | { |
Russell King | 3ae5eae | 2005-11-09 22:32:44 +0000 | [diff] [blame] | 915 | struct s3c2410_platform_nand *plat = to_nand_plat(pdev); |
Ben Dooks | ec0482e | 2009-05-30 16:55:29 +0100 | [diff] [blame] | 916 | enum s3c_cpu_type cpu_type; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 917 | struct s3c2410_nand_info *info; |
| 918 | struct s3c2410_nand_mtd *nmtd; |
| 919 | struct s3c2410_nand_set *sets; |
| 920 | struct resource *res; |
| 921 | int err = 0; |
| 922 | int size; |
| 923 | int nr_sets; |
| 924 | int setno; |
| 925 | |
Ben Dooks | ec0482e | 2009-05-30 16:55:29 +0100 | [diff] [blame] | 926 | cpu_type = platform_get_device_id(pdev)->driver_data; |
| 927 | |
Russell King | 3ae5eae | 2005-11-09 22:32:44 +0000 | [diff] [blame] | 928 | pr_debug("s3c2410_nand_probe(%p)\n", pdev); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 929 | |
Julia Lawall | ecce2a6 | 2010-05-13 22:07:46 +0200 | [diff] [blame] | 930 | info = kzalloc(sizeof(*info), GFP_KERNEL); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 931 | if (info == NULL) { |
Russell King | 3ae5eae | 2005-11-09 22:32:44 +0000 | [diff] [blame] | 932 | dev_err(&pdev->dev, "no memory for flash info\n"); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 933 | err = -ENOMEM; |
| 934 | goto exit_error; |
| 935 | } |
| 936 | |
Russell King | 3ae5eae | 2005-11-09 22:32:44 +0000 | [diff] [blame] | 937 | platform_set_drvdata(pdev, info); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 938 | |
| 939 | spin_lock_init(&info->controller.lock); |
Ben Dooks | a4f957f | 2005-06-20 12:48:25 +0100 | [diff] [blame] | 940 | init_waitqueue_head(&info->controller.wq); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 941 | |
| 942 | /* get the clock source and enable it */ |
| 943 | |
Russell King | 3ae5eae | 2005-11-09 22:32:44 +0000 | [diff] [blame] | 944 | info->clk = clk_get(&pdev->dev, "nand"); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 945 | if (IS_ERR(info->clk)) { |
Joe Perches | 898eb71 | 2007-10-18 03:06:30 -0700 | [diff] [blame] | 946 | dev_err(&pdev->dev, "failed to get clock\n"); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 947 | err = -ENOENT; |
| 948 | goto exit_error; |
| 949 | } |
| 950 | |
Jiri Pinkava | ac497c1 | 2011-04-13 11:59:30 +0200 | [diff] [blame] | 951 | s3c2410_nand_clk_set_state(info, CLOCK_ENABLE); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 952 | |
| 953 | /* allocate and map the resource */ |
| 954 | |
Ben Dooks | a4f957f | 2005-06-20 12:48:25 +0100 | [diff] [blame] | 955 | /* currently we assume we have the one resource */ |
| 956 | res = pdev->resource; |
H Hartley Sweeten | fc161c4 | 2009-12-14 16:56:22 -0500 | [diff] [blame] | 957 | size = resource_size(res); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 958 | |
| 959 | info->area = request_mem_region(res->start, size, pdev->name); |
| 960 | |
| 961 | if (info->area == NULL) { |
Russell King | 3ae5eae | 2005-11-09 22:32:44 +0000 | [diff] [blame] | 962 | dev_err(&pdev->dev, "cannot reserve register region\n"); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 963 | err = -ENOENT; |
| 964 | goto exit_error; |
| 965 | } |
| 966 | |
Russell King | 3ae5eae | 2005-11-09 22:32:44 +0000 | [diff] [blame] | 967 | info->device = &pdev->dev; |
Ben Dooks | a4f957f | 2005-06-20 12:48:25 +0100 | [diff] [blame] | 968 | info->platform = plat; |
| 969 | info->regs = ioremap(res->start, size); |
Ben Dooks | 2c06a08 | 2006-06-27 14:35:46 +0100 | [diff] [blame] | 970 | info->cpu_type = cpu_type; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 971 | |
| 972 | if (info->regs == NULL) { |
Russell King | 3ae5eae | 2005-11-09 22:32:44 +0000 | [diff] [blame] | 973 | dev_err(&pdev->dev, "cannot reserve register region\n"); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 974 | err = -EIO; |
| 975 | goto exit_error; |
Thomas Gleixner | 61b03bd | 2005-11-07 11:15:49 +0000 | [diff] [blame] | 976 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 977 | |
Russell King | 3ae5eae | 2005-11-09 22:32:44 +0000 | [diff] [blame] | 978 | dev_dbg(&pdev->dev, "mapped registers at %p\n", info->regs); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 979 | |
| 980 | /* initialise the hardware */ |
| 981 | |
Ben Dooks | 30821fe | 2008-07-15 11:58:31 +0100 | [diff] [blame] | 982 | err = s3c2410_nand_inithw(info); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 983 | if (err != 0) |
| 984 | goto exit_error; |
| 985 | |
| 986 | sets = (plat != NULL) ? plat->sets : NULL; |
| 987 | nr_sets = (plat != NULL) ? plat->nr_sets : 1; |
| 988 | |
| 989 | info->mtd_count = nr_sets; |
| 990 | |
| 991 | /* allocate our information */ |
| 992 | |
| 993 | size = nr_sets * sizeof(*info->mtds); |
Julia Lawall | ecce2a6 | 2010-05-13 22:07:46 +0200 | [diff] [blame] | 994 | info->mtds = kzalloc(size, GFP_KERNEL); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 995 | if (info->mtds == NULL) { |
Russell King | 3ae5eae | 2005-11-09 22:32:44 +0000 | [diff] [blame] | 996 | dev_err(&pdev->dev, "failed to allocate mtd storage\n"); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 997 | err = -ENOMEM; |
| 998 | goto exit_error; |
| 999 | } |
| 1000 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1001 | /* initialise all possible chips */ |
| 1002 | |
| 1003 | nmtd = info->mtds; |
| 1004 | |
| 1005 | for (setno = 0; setno < nr_sets; setno++, nmtd++) { |
David Woodhouse | e0c7d76 | 2006-05-13 18:07:53 +0100 | [diff] [blame] | 1006 | pr_debug("initialising set %d (%p, info %p)\n", setno, nmtd, info); |
Thomas Gleixner | 61b03bd | 2005-11-07 11:15:49 +0000 | [diff] [blame] | 1007 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1008 | s3c2410_nand_init_chip(info, nmtd, sets); |
| 1009 | |
Ben Dooks | 71d54f3 | 2008-04-15 11:36:19 +0100 | [diff] [blame] | 1010 | nmtd->scan_res = nand_scan_ident(&nmtd->mtd, |
David Woodhouse | 5e81e88 | 2010-02-26 18:32:56 +0000 | [diff] [blame] | 1011 | (sets) ? sets->nr_chips : 1, |
| 1012 | NULL); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1013 | |
| 1014 | if (nmtd->scan_res == 0) { |
Ben Dooks | 71d54f3 | 2008-04-15 11:36:19 +0100 | [diff] [blame] | 1015 | s3c2410_nand_update_chip(info, nmtd); |
| 1016 | nand_scan_tail(&nmtd->mtd); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1017 | s3c2410_nand_add_partition(info, nmtd, sets); |
| 1018 | } |
| 1019 | |
| 1020 | if (sets != NULL) |
| 1021 | sets++; |
| 1022 | } |
Thomas Gleixner | 61b03bd | 2005-11-07 11:15:49 +0000 | [diff] [blame] | 1023 | |
Ben Dooks | 30821fe | 2008-07-15 11:58:31 +0100 | [diff] [blame] | 1024 | err = s3c2410_nand_cpufreq_register(info); |
| 1025 | if (err < 0) { |
| 1026 | dev_err(&pdev->dev, "failed to init cpufreq support\n"); |
| 1027 | goto exit_error; |
| 1028 | } |
| 1029 | |
Jiri Pinkava | ac497c1 | 2011-04-13 11:59:30 +0200 | [diff] [blame] | 1030 | if (allow_clk_suspend(info)) { |
Ben Dooks | d1fef3c | 2006-06-19 09:29:38 +0100 | [diff] [blame] | 1031 | dev_info(&pdev->dev, "clock idle support enabled\n"); |
Jiri Pinkava | ac497c1 | 2011-04-13 11:59:30 +0200 | [diff] [blame] | 1032 | s3c2410_nand_clk_set_state(info, CLOCK_SUSPEND); |
Ben Dooks | d1fef3c | 2006-06-19 09:29:38 +0100 | [diff] [blame] | 1033 | } |
| 1034 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1035 | pr_debug("initialised ok\n"); |
| 1036 | return 0; |
| 1037 | |
| 1038 | exit_error: |
Ben Dooks | ec0482e | 2009-05-30 16:55:29 +0100 | [diff] [blame] | 1039 | s3c24xx_nand_remove(pdev); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1040 | |
| 1041 | if (err == 0) |
| 1042 | err = -EINVAL; |
| 1043 | return err; |
| 1044 | } |
| 1045 | |
Ben Dooks | d1fef3c | 2006-06-19 09:29:38 +0100 | [diff] [blame] | 1046 | /* PM Support */ |
| 1047 | #ifdef CONFIG_PM |
| 1048 | |
| 1049 | static int s3c24xx_nand_suspend(struct platform_device *dev, pm_message_t pm) |
| 1050 | { |
| 1051 | struct s3c2410_nand_info *info = platform_get_drvdata(dev); |
| 1052 | |
| 1053 | if (info) { |
Ben Dooks | 0916083 | 2008-04-15 11:36:18 +0100 | [diff] [blame] | 1054 | info->save_sel = readl(info->sel_reg); |
Ben Dooks | 03680b1 | 2007-11-19 23:28:07 +0000 | [diff] [blame] | 1055 | |
| 1056 | /* For the moment, we must ensure nFCE is high during |
| 1057 | * the time we are suspended. This really should be |
| 1058 | * handled by suspending the MTDs we are using, but |
| 1059 | * that is currently not the case. */ |
| 1060 | |
Ben Dooks | 0916083 | 2008-04-15 11:36:18 +0100 | [diff] [blame] | 1061 | writel(info->save_sel | info->sel_bit, info->sel_reg); |
Ben Dooks | 03680b1 | 2007-11-19 23:28:07 +0000 | [diff] [blame] | 1062 | |
Jiri Pinkava | ac497c1 | 2011-04-13 11:59:30 +0200 | [diff] [blame] | 1063 | s3c2410_nand_clk_set_state(info, CLOCK_DISABLE); |
Ben Dooks | d1fef3c | 2006-06-19 09:29:38 +0100 | [diff] [blame] | 1064 | } |
| 1065 | |
| 1066 | return 0; |
| 1067 | } |
| 1068 | |
| 1069 | static int s3c24xx_nand_resume(struct platform_device *dev) |
| 1070 | { |
| 1071 | struct s3c2410_nand_info *info = platform_get_drvdata(dev); |
Ben Dooks | 0916083 | 2008-04-15 11:36:18 +0100 | [diff] [blame] | 1072 | unsigned long sel; |
Ben Dooks | d1fef3c | 2006-06-19 09:29:38 +0100 | [diff] [blame] | 1073 | |
| 1074 | if (info) { |
Jiri Pinkava | ac497c1 | 2011-04-13 11:59:30 +0200 | [diff] [blame] | 1075 | s3c2410_nand_clk_set_state(info, CLOCK_ENABLE); |
Ben Dooks | 30821fe | 2008-07-15 11:58:31 +0100 | [diff] [blame] | 1076 | s3c2410_nand_inithw(info); |
Ben Dooks | d1fef3c | 2006-06-19 09:29:38 +0100 | [diff] [blame] | 1077 | |
Ben Dooks | 03680b1 | 2007-11-19 23:28:07 +0000 | [diff] [blame] | 1078 | /* Restore the state of the nFCE line. */ |
| 1079 | |
Ben Dooks | 0916083 | 2008-04-15 11:36:18 +0100 | [diff] [blame] | 1080 | sel = readl(info->sel_reg); |
| 1081 | sel &= ~info->sel_bit; |
| 1082 | sel |= info->save_sel & info->sel_bit; |
| 1083 | writel(sel, info->sel_reg); |
Ben Dooks | 03680b1 | 2007-11-19 23:28:07 +0000 | [diff] [blame] | 1084 | |
Jiri Pinkava | ac497c1 | 2011-04-13 11:59:30 +0200 | [diff] [blame] | 1085 | s3c2410_nand_clk_set_state(info, CLOCK_SUSPEND); |
Ben Dooks | d1fef3c | 2006-06-19 09:29:38 +0100 | [diff] [blame] | 1086 | } |
| 1087 | |
| 1088 | return 0; |
| 1089 | } |
| 1090 | |
| 1091 | #else |
| 1092 | #define s3c24xx_nand_suspend NULL |
| 1093 | #define s3c24xx_nand_resume NULL |
| 1094 | #endif |
| 1095 | |
Ben Dooks | a4f957f | 2005-06-20 12:48:25 +0100 | [diff] [blame] | 1096 | /* driver device registration */ |
| 1097 | |
Ben Dooks | ec0482e | 2009-05-30 16:55:29 +0100 | [diff] [blame] | 1098 | static struct platform_device_id s3c24xx_driver_ids[] = { |
| 1099 | { |
| 1100 | .name = "s3c2410-nand", |
| 1101 | .driver_data = TYPE_S3C2410, |
| 1102 | }, { |
| 1103 | .name = "s3c2440-nand", |
| 1104 | .driver_data = TYPE_S3C2440, |
| 1105 | }, { |
| 1106 | .name = "s3c2412-nand", |
| 1107 | .driver_data = TYPE_S3C2412, |
Peter Korsgaard | 9dbc090 | 2009-06-07 06:04:23 -0700 | [diff] [blame] | 1108 | }, { |
| 1109 | .name = "s3c6400-nand", |
| 1110 | .driver_data = TYPE_S3C2412, /* compatible with 2412 */ |
Russell King | 3ae5eae | 2005-11-09 22:32:44 +0000 | [diff] [blame] | 1111 | }, |
Ben Dooks | ec0482e | 2009-05-30 16:55:29 +0100 | [diff] [blame] | 1112 | { } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1113 | }; |
| 1114 | |
Ben Dooks | ec0482e | 2009-05-30 16:55:29 +0100 | [diff] [blame] | 1115 | MODULE_DEVICE_TABLE(platform, s3c24xx_driver_ids); |
Ben Dooks | a4f957f | 2005-06-20 12:48:25 +0100 | [diff] [blame] | 1116 | |
Ben Dooks | ec0482e | 2009-05-30 16:55:29 +0100 | [diff] [blame] | 1117 | static struct platform_driver s3c24xx_nand_driver = { |
| 1118 | .probe = s3c24xx_nand_probe, |
| 1119 | .remove = s3c24xx_nand_remove, |
Ben Dooks | 2c06a08 | 2006-06-27 14:35:46 +0100 | [diff] [blame] | 1120 | .suspend = s3c24xx_nand_suspend, |
| 1121 | .resume = s3c24xx_nand_resume, |
Ben Dooks | ec0482e | 2009-05-30 16:55:29 +0100 | [diff] [blame] | 1122 | .id_table = s3c24xx_driver_ids, |
Ben Dooks | 2c06a08 | 2006-06-27 14:35:46 +0100 | [diff] [blame] | 1123 | .driver = { |
Ben Dooks | ec0482e | 2009-05-30 16:55:29 +0100 | [diff] [blame] | 1124 | .name = "s3c24xx-nand", |
Ben Dooks | 2c06a08 | 2006-06-27 14:35:46 +0100 | [diff] [blame] | 1125 | .owner = THIS_MODULE, |
| 1126 | }, |
| 1127 | }; |
| 1128 | |
Sachin Kamat | 056fcab | 2012-07-16 16:02:22 +0530 | [diff] [blame] | 1129 | module_platform_driver(s3c24xx_nand_driver); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1130 | |
| 1131 | MODULE_LICENSE("GPL"); |
| 1132 | MODULE_AUTHOR("Ben Dooks <ben@simtec.co.uk>"); |
Ben Dooks | a4f957f | 2005-06-20 12:48:25 +0100 | [diff] [blame] | 1133 | MODULE_DESCRIPTION("S3C24XX MTD NAND driver"); |