Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 1 | /* |
Pierre Ossman | 70f1048 | 2007-07-11 20:04:50 +0200 | [diff] [blame] | 2 | * linux/drivers/mmc/host/sdhci.h - Secure Digital Host Controller Interface driver |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 3 | * |
Giuseppe Cavallaro | 1978fda | 2010-09-28 10:41:29 +0200 | [diff] [blame] | 4 | * Header file for Host Controller registers and I/O accessors. |
| 5 | * |
Pierre Ossman | b69c905 | 2008-03-08 23:44:25 +0100 | [diff] [blame] | 6 | * Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved. |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 7 | * |
| 8 | * This program is free software; you can redistribute it and/or modify |
Pierre Ossman | 643f720 | 2006-09-30 23:27:52 -0700 | [diff] [blame] | 9 | * it under the terms of the GNU General Public License as published by |
| 10 | * the Free Software Foundation; either version 2 of the License, or (at |
| 11 | * your option) any later version. |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 12 | */ |
Giuseppe Cavallaro | 1978fda | 2010-09-28 10:41:29 +0200 | [diff] [blame] | 13 | #ifndef __SDHCI_HW_H |
| 14 | #define __SDHCI_HW_H |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 15 | |
Andrew Morton | 0c7ad10 | 2008-07-25 19:44:35 -0700 | [diff] [blame] | 16 | #include <linux/scatterlist.h> |
Anton Vorontsov | 4e4141a | 2009-03-17 00:13:46 +0300 | [diff] [blame] | 17 | #include <linux/compiler.h> |
| 18 | #include <linux/types.h> |
| 19 | #include <linux/io.h> |
Andrew Morton | 0c7ad10 | 2008-07-25 19:44:35 -0700 | [diff] [blame] | 20 | |
Giuseppe Cavallaro | 1978fda | 2010-09-28 10:41:29 +0200 | [diff] [blame] | 21 | #include <linux/mmc/sdhci.h> |
| 22 | |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 23 | /* |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 24 | * Controller registers |
| 25 | */ |
| 26 | |
| 27 | #define SDHCI_DMA_ADDRESS 0x00 |
Andrei Warkentin | 8edf6371 | 2011-05-23 15:06:39 -0500 | [diff] [blame] | 28 | #define SDHCI_ARGUMENT2 SDHCI_DMA_ADDRESS |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 29 | |
| 30 | #define SDHCI_BLOCK_SIZE 0x04 |
Pierre Ossman | bab7696 | 2006-07-02 16:51:35 +0100 | [diff] [blame] | 31 | #define SDHCI_MAKE_BLKSZ(dma, blksz) (((dma & 0x7) << 12) | (blksz & 0xFFF)) |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 32 | |
| 33 | #define SDHCI_BLOCK_COUNT 0x06 |
| 34 | |
| 35 | #define SDHCI_ARGUMENT 0x08 |
| 36 | |
| 37 | #define SDHCI_TRANSFER_MODE 0x0C |
| 38 | #define SDHCI_TRNS_DMA 0x01 |
| 39 | #define SDHCI_TRNS_BLK_CNT_EN 0x02 |
Andrei Warkentin | e89d456 | 2011-05-23 15:06:37 -0500 | [diff] [blame] | 40 | #define SDHCI_TRNS_AUTO_CMD12 0x04 |
Andrei Warkentin | 8edf6371 | 2011-05-23 15:06:39 -0500 | [diff] [blame] | 41 | #define SDHCI_TRNS_AUTO_CMD23 0x08 |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 42 | #define SDHCI_TRNS_READ 0x10 |
| 43 | #define SDHCI_TRNS_MULTI 0x20 |
| 44 | |
| 45 | #define SDHCI_COMMAND 0x0E |
| 46 | #define SDHCI_CMD_RESP_MASK 0x03 |
| 47 | #define SDHCI_CMD_CRC 0x08 |
| 48 | #define SDHCI_CMD_INDEX 0x10 |
| 49 | #define SDHCI_CMD_DATA 0x20 |
Richard Zhu | 574e3f5 | 2011-03-21 13:22:14 +0800 | [diff] [blame] | 50 | #define SDHCI_CMD_ABORTCMD 0xC0 |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 51 | |
| 52 | #define SDHCI_CMD_RESP_NONE 0x00 |
| 53 | #define SDHCI_CMD_RESP_LONG 0x01 |
| 54 | #define SDHCI_CMD_RESP_SHORT 0x02 |
| 55 | #define SDHCI_CMD_RESP_SHORT_BUSY 0x03 |
| 56 | |
| 57 | #define SDHCI_MAKE_CMD(c, f) (((c & 0xff) << 8) | (f & 0xff)) |
Aries Lee | 22113ef | 2010-12-15 08:14:24 +0100 | [diff] [blame] | 58 | #define SDHCI_GET_CMD(c) ((c>>8) & 0x3f) |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 59 | |
| 60 | #define SDHCI_RESPONSE 0x10 |
| 61 | |
| 62 | #define SDHCI_BUFFER 0x20 |
| 63 | |
| 64 | #define SDHCI_PRESENT_STATE 0x24 |
| 65 | #define SDHCI_CMD_INHIBIT 0x00000001 |
| 66 | #define SDHCI_DATA_INHIBIT 0x00000002 |
| 67 | #define SDHCI_DOING_WRITE 0x00000100 |
| 68 | #define SDHCI_DOING_READ 0x00000200 |
| 69 | #define SDHCI_SPACE_AVAILABLE 0x00000400 |
| 70 | #define SDHCI_DATA_AVAILABLE 0x00000800 |
| 71 | #define SDHCI_CARD_PRESENT 0x00010000 |
| 72 | #define SDHCI_WRITE_PROTECT 0x00080000 |
Arindam Nath | f2119df | 2011-05-05 12:18:57 +0530 | [diff] [blame] | 73 | #define SDHCI_DATA_LVL_MASK 0x00F00000 |
| 74 | #define SDHCI_DATA_LVL_SHIFT 20 |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 75 | |
Arindam Nath | d6d50a1 | 2011-05-05 12:18:59 +0530 | [diff] [blame] | 76 | #define SDHCI_HOST_CONTROL 0x28 |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 77 | #define SDHCI_CTRL_LED 0x01 |
| 78 | #define SDHCI_CTRL_4BITBUS 0x02 |
Pierre Ossman | 077df88 | 2006-11-08 23:06:35 +0100 | [diff] [blame] | 79 | #define SDHCI_CTRL_HISPD 0x04 |
Pierre Ossman | 2134a92 | 2008-06-28 18:28:51 +0200 | [diff] [blame] | 80 | #define SDHCI_CTRL_DMA_MASK 0x18 |
| 81 | #define SDHCI_CTRL_SDMA 0x00 |
| 82 | #define SDHCI_CTRL_ADMA1 0x08 |
| 83 | #define SDHCI_CTRL_ADMA32 0x10 |
| 84 | #define SDHCI_CTRL_ADMA64 0x18 |
Philip Rakity | 15ec446 | 2010-11-19 16:48:39 -0500 | [diff] [blame] | 85 | #define SDHCI_CTRL_8BITBUS 0x20 |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 86 | |
| 87 | #define SDHCI_POWER_CONTROL 0x29 |
Pierre Ossman | 146ad66 | 2006-06-30 02:22:23 -0700 | [diff] [blame] | 88 | #define SDHCI_POWER_ON 0x01 |
| 89 | #define SDHCI_POWER_180 0x0A |
| 90 | #define SDHCI_POWER_300 0x0C |
| 91 | #define SDHCI_POWER_330 0x0E |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 92 | |
| 93 | #define SDHCI_BLOCK_GAP_CONTROL 0x2A |
| 94 | |
Nicolas Pitre | 2df3b71 | 2007-09-29 10:46:20 -0400 | [diff] [blame] | 95 | #define SDHCI_WAKE_UP_CONTROL 0x2B |
Daniel Drake | 5f61970 | 2010-11-04 22:20:39 +0000 | [diff] [blame] | 96 | #define SDHCI_WAKE_ON_INT 0x01 |
| 97 | #define SDHCI_WAKE_ON_INSERT 0x02 |
| 98 | #define SDHCI_WAKE_ON_REMOVE 0x04 |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 99 | |
| 100 | #define SDHCI_CLOCK_CONTROL 0x2C |
| 101 | #define SDHCI_DIVIDER_SHIFT 8 |
Zhangfei Gao | 85105c5 | 2010-08-06 07:10:01 +0800 | [diff] [blame] | 102 | #define SDHCI_DIVIDER_HI_SHIFT 6 |
| 103 | #define SDHCI_DIV_MASK 0xFF |
| 104 | #define SDHCI_DIV_MASK_LEN 8 |
| 105 | #define SDHCI_DIV_HI_MASK 0x300 |
Arindam Nath | c3ed387 | 2011-05-05 12:19:06 +0530 | [diff] [blame] | 106 | #define SDHCI_PROG_CLOCK_MODE 0x0020 |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 107 | #define SDHCI_CLOCK_CARD_EN 0x0004 |
| 108 | #define SDHCI_CLOCK_INT_STABLE 0x0002 |
| 109 | #define SDHCI_CLOCK_INT_EN 0x0001 |
| 110 | |
| 111 | #define SDHCI_TIMEOUT_CONTROL 0x2E |
| 112 | |
| 113 | #define SDHCI_SOFTWARE_RESET 0x2F |
| 114 | #define SDHCI_RESET_ALL 0x01 |
| 115 | #define SDHCI_RESET_CMD 0x02 |
| 116 | #define SDHCI_RESET_DATA 0x04 |
| 117 | |
| 118 | #define SDHCI_INT_STATUS 0x30 |
| 119 | #define SDHCI_INT_ENABLE 0x34 |
| 120 | #define SDHCI_SIGNAL_ENABLE 0x38 |
| 121 | #define SDHCI_INT_RESPONSE 0x00000001 |
| 122 | #define SDHCI_INT_DATA_END 0x00000002 |
Haijun Zhang | a4071fb | 2012-12-04 10:41:28 +0800 | [diff] [blame] | 123 | #define SDHCI_INT_BLK_GAP 0x00000004 |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 124 | #define SDHCI_INT_DMA_END 0x00000008 |
Pierre Ossman | a406f5a | 2006-07-02 16:50:59 +0100 | [diff] [blame] | 125 | #define SDHCI_INT_SPACE_AVAIL 0x00000010 |
| 126 | #define SDHCI_INT_DATA_AVAIL 0x00000020 |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 127 | #define SDHCI_INT_CARD_INSERT 0x00000040 |
| 128 | #define SDHCI_INT_CARD_REMOVE 0x00000080 |
| 129 | #define SDHCI_INT_CARD_INT 0x00000100 |
Pierre Ossman | 964f9ce | 2007-07-20 18:20:36 +0200 | [diff] [blame] | 130 | #define SDHCI_INT_ERROR 0x00008000 |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 131 | #define SDHCI_INT_TIMEOUT 0x00010000 |
| 132 | #define SDHCI_INT_CRC 0x00020000 |
| 133 | #define SDHCI_INT_END_BIT 0x00040000 |
| 134 | #define SDHCI_INT_INDEX 0x00080000 |
| 135 | #define SDHCI_INT_DATA_TIMEOUT 0x00100000 |
| 136 | #define SDHCI_INT_DATA_CRC 0x00200000 |
| 137 | #define SDHCI_INT_DATA_END_BIT 0x00400000 |
| 138 | #define SDHCI_INT_BUS_POWER 0x00800000 |
| 139 | #define SDHCI_INT_ACMD12ERR 0x01000000 |
Pierre Ossman | 2134a92 | 2008-06-28 18:28:51 +0200 | [diff] [blame] | 140 | #define SDHCI_INT_ADMA_ERROR 0x02000000 |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 141 | |
| 142 | #define SDHCI_INT_NORMAL_MASK 0x00007FFF |
| 143 | #define SDHCI_INT_ERROR_MASK 0xFFFF8000 |
| 144 | |
| 145 | #define SDHCI_INT_CMD_MASK (SDHCI_INT_RESPONSE | SDHCI_INT_TIMEOUT | \ |
| 146 | SDHCI_INT_CRC | SDHCI_INT_END_BIT | SDHCI_INT_INDEX) |
| 147 | #define SDHCI_INT_DATA_MASK (SDHCI_INT_DATA_END | SDHCI_INT_DMA_END | \ |
Pierre Ossman | a406f5a | 2006-07-02 16:50:59 +0100 | [diff] [blame] | 148 | SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL | \ |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 149 | SDHCI_INT_DATA_TIMEOUT | SDHCI_INT_DATA_CRC | \ |
Haijun Zhang | a4071fb | 2012-12-04 10:41:28 +0800 | [diff] [blame] | 150 | SDHCI_INT_DATA_END_BIT | SDHCI_INT_ADMA_ERROR | \ |
| 151 | SDHCI_INT_BLK_GAP) |
Anton Vorontsov | 7260cf5 | 2009-03-17 00:13:48 +0300 | [diff] [blame] | 152 | #define SDHCI_INT_ALL_MASK ((unsigned int)-1) |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 153 | |
| 154 | #define SDHCI_ACMD12_ERR 0x3C |
| 155 | |
Arindam Nath | f2119df | 2011-05-05 12:18:57 +0530 | [diff] [blame] | 156 | #define SDHCI_HOST_CONTROL2 0x3E |
Arindam Nath | 49c468f | 2011-05-05 12:19:01 +0530 | [diff] [blame] | 157 | #define SDHCI_CTRL_UHS_MASK 0x0007 |
| 158 | #define SDHCI_CTRL_UHS_SDR12 0x0000 |
| 159 | #define SDHCI_CTRL_UHS_SDR25 0x0001 |
| 160 | #define SDHCI_CTRL_UHS_SDR50 0x0002 |
| 161 | #define SDHCI_CTRL_UHS_SDR104 0x0003 |
| 162 | #define SDHCI_CTRL_UHS_DDR50 0x0004 |
Girish K S | 069c9f1 | 2012-01-06 09:56:39 +0530 | [diff] [blame] | 163 | #define SDHCI_CTRL_HS_SDR200 0x0005 /* reserved value in SDIO spec */ |
Arindam Nath | f2119df | 2011-05-05 12:18:57 +0530 | [diff] [blame] | 164 | #define SDHCI_CTRL_VDD_180 0x0008 |
Arindam Nath | d6d50a1 | 2011-05-05 12:18:59 +0530 | [diff] [blame] | 165 | #define SDHCI_CTRL_DRV_TYPE_MASK 0x0030 |
| 166 | #define SDHCI_CTRL_DRV_TYPE_B 0x0000 |
| 167 | #define SDHCI_CTRL_DRV_TYPE_A 0x0010 |
| 168 | #define SDHCI_CTRL_DRV_TYPE_C 0x0020 |
| 169 | #define SDHCI_CTRL_DRV_TYPE_D 0x0030 |
Arindam Nath | b513ea2 | 2011-05-05 12:19:04 +0530 | [diff] [blame] | 170 | #define SDHCI_CTRL_EXEC_TUNING 0x0040 |
| 171 | #define SDHCI_CTRL_TUNED_CLK 0x0080 |
Arindam Nath | d6d50a1 | 2011-05-05 12:18:59 +0530 | [diff] [blame] | 172 | #define SDHCI_CTRL_PRESET_VAL_ENABLE 0x8000 |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 173 | |
| 174 | #define SDHCI_CAPABILITIES 0x40 |
Pierre Ossman | 1c8cde9 | 2006-06-30 02:22:25 -0700 | [diff] [blame] | 175 | #define SDHCI_TIMEOUT_CLK_MASK 0x0000003F |
| 176 | #define SDHCI_TIMEOUT_CLK_SHIFT 0 |
| 177 | #define SDHCI_TIMEOUT_CLK_UNIT 0x00000080 |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 178 | #define SDHCI_CLOCK_BASE_MASK 0x00003F00 |
Zhangfei Gao | c4687d5 | 2010-08-20 14:02:36 -0400 | [diff] [blame] | 179 | #define SDHCI_CLOCK_V3_BASE_MASK 0x0000FF00 |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 180 | #define SDHCI_CLOCK_BASE_SHIFT 8 |
Pierre Ossman | 1d676e0 | 2006-07-02 16:52:10 +0100 | [diff] [blame] | 181 | #define SDHCI_MAX_BLOCK_MASK 0x00030000 |
| 182 | #define SDHCI_MAX_BLOCK_SHIFT 16 |
Philip Rakity | 15ec446 | 2010-11-19 16:48:39 -0500 | [diff] [blame] | 183 | #define SDHCI_CAN_DO_8BIT 0x00040000 |
Pierre Ossman | 2134a92 | 2008-06-28 18:28:51 +0200 | [diff] [blame] | 184 | #define SDHCI_CAN_DO_ADMA2 0x00080000 |
| 185 | #define SDHCI_CAN_DO_ADMA1 0x00100000 |
Pierre Ossman | 077df88 | 2006-11-08 23:06:35 +0100 | [diff] [blame] | 186 | #define SDHCI_CAN_DO_HISPD 0x00200000 |
Richard Röjfors | a13abc7 | 2009-09-22 16:45:30 -0700 | [diff] [blame] | 187 | #define SDHCI_CAN_DO_SDMA 0x00400000 |
Pierre Ossman | 146ad66 | 2006-06-30 02:22:23 -0700 | [diff] [blame] | 188 | #define SDHCI_CAN_VDD_330 0x01000000 |
| 189 | #define SDHCI_CAN_VDD_300 0x02000000 |
| 190 | #define SDHCI_CAN_VDD_180 0x04000000 |
Pierre Ossman | 2134a92 | 2008-06-28 18:28:51 +0200 | [diff] [blame] | 191 | #define SDHCI_CAN_64BIT 0x10000000 |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 192 | |
Arindam Nath | f2119df | 2011-05-05 12:18:57 +0530 | [diff] [blame] | 193 | #define SDHCI_SUPPORT_SDR50 0x00000001 |
| 194 | #define SDHCI_SUPPORT_SDR104 0x00000002 |
| 195 | #define SDHCI_SUPPORT_DDR50 0x00000004 |
Arindam Nath | d6d50a1 | 2011-05-05 12:18:59 +0530 | [diff] [blame] | 196 | #define SDHCI_DRIVER_TYPE_A 0x00000010 |
| 197 | #define SDHCI_DRIVER_TYPE_C 0x00000020 |
| 198 | #define SDHCI_DRIVER_TYPE_D 0x00000040 |
Arindam Nath | cf2b5ee | 2011-05-05 12:19:07 +0530 | [diff] [blame] | 199 | #define SDHCI_RETUNING_TIMER_COUNT_MASK 0x00000F00 |
| 200 | #define SDHCI_RETUNING_TIMER_COUNT_SHIFT 8 |
| 201 | #define SDHCI_USE_SDR50_TUNING 0x00002000 |
| 202 | #define SDHCI_RETUNING_MODE_MASK 0x0000C000 |
| 203 | #define SDHCI_RETUNING_MODE_SHIFT 14 |
Arindam Nath | c3ed387 | 2011-05-05 12:19:06 +0530 | [diff] [blame] | 204 | #define SDHCI_CLOCK_MUL_MASK 0x00FF0000 |
| 205 | #define SDHCI_CLOCK_MUL_SHIFT 16 |
Arindam Nath | f2119df | 2011-05-05 12:18:57 +0530 | [diff] [blame] | 206 | |
Philip Rakity | e8120ad | 2010-11-30 00:55:23 -0500 | [diff] [blame] | 207 | #define SDHCI_CAPABILITIES_1 0x44 |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 208 | |
Arindam Nath | f2119df | 2011-05-05 12:18:57 +0530 | [diff] [blame] | 209 | #define SDHCI_MAX_CURRENT 0x48 |
Philip Rakity | bad37e1 | 2012-05-27 18:36:44 -0700 | [diff] [blame] | 210 | #define SDHCI_MAX_CURRENT_LIMIT 0xFF |
Arindam Nath | f2119df | 2011-05-05 12:18:57 +0530 | [diff] [blame] | 211 | #define SDHCI_MAX_CURRENT_330_MASK 0x0000FF |
| 212 | #define SDHCI_MAX_CURRENT_330_SHIFT 0 |
| 213 | #define SDHCI_MAX_CURRENT_300_MASK 0x00FF00 |
| 214 | #define SDHCI_MAX_CURRENT_300_SHIFT 8 |
| 215 | #define SDHCI_MAX_CURRENT_180_MASK 0xFF0000 |
| 216 | #define SDHCI_MAX_CURRENT_180_SHIFT 16 |
| 217 | #define SDHCI_MAX_CURRENT_MULTIPLIER 4 |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 218 | |
| 219 | /* 4C-4F reserved for more max current */ |
| 220 | |
Pierre Ossman | 2134a92 | 2008-06-28 18:28:51 +0200 | [diff] [blame] | 221 | #define SDHCI_SET_ACMD12_ERROR 0x50 |
| 222 | #define SDHCI_SET_INT_ERROR 0x52 |
| 223 | |
| 224 | #define SDHCI_ADMA_ERROR 0x54 |
| 225 | |
| 226 | /* 55-57 reserved */ |
| 227 | |
| 228 | #define SDHCI_ADMA_ADDRESS 0x58 |
| 229 | |
| 230 | /* 60-FB reserved */ |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 231 | |
Kevin Liu | 5298338 | 2013-01-31 11:31:37 +0800 | [diff] [blame] | 232 | #define SDHCI_PRESET_FOR_SDR12 0x66 |
| 233 | #define SDHCI_PRESET_FOR_SDR25 0x68 |
| 234 | #define SDHCI_PRESET_FOR_SDR50 0x6A |
| 235 | #define SDHCI_PRESET_FOR_SDR104 0x6C |
| 236 | #define SDHCI_PRESET_FOR_DDR50 0x6E |
| 237 | #define SDHCI_PRESET_DRV_MASK 0xC000 |
| 238 | #define SDHCI_PRESET_DRV_SHIFT 14 |
| 239 | #define SDHCI_PRESET_CLKGEN_SEL_MASK 0x400 |
| 240 | #define SDHCI_PRESET_CLKGEN_SEL_SHIFT 10 |
| 241 | #define SDHCI_PRESET_SDCLK_FREQ_MASK 0x3FF |
| 242 | #define SDHCI_PRESET_SDCLK_FREQ_SHIFT 0 |
| 243 | |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 244 | #define SDHCI_SLOT_INT_STATUS 0xFC |
| 245 | |
| 246 | #define SDHCI_HOST_VERSION 0xFE |
Pierre Ossman | 4a96550 | 2006-06-30 02:22:29 -0700 | [diff] [blame] | 247 | #define SDHCI_VENDOR_VER_MASK 0xFF00 |
| 248 | #define SDHCI_VENDOR_VER_SHIFT 8 |
| 249 | #define SDHCI_SPEC_VER_MASK 0x00FF |
| 250 | #define SDHCI_SPEC_VER_SHIFT 0 |
Pierre Ossman | 2134a92 | 2008-06-28 18:28:51 +0200 | [diff] [blame] | 251 | #define SDHCI_SPEC_100 0 |
| 252 | #define SDHCI_SPEC_200 1 |
Zhangfei Gao | 85105c5 | 2010-08-06 07:10:01 +0800 | [diff] [blame] | 253 | #define SDHCI_SPEC_300 2 |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 254 | |
Zhangfei Gao | 0397526 | 2010-09-20 15:15:18 -0400 | [diff] [blame] | 255 | /* |
| 256 | * End of controller registers. |
| 257 | */ |
| 258 | |
| 259 | #define SDHCI_MAX_DIV_SPEC_200 256 |
| 260 | #define SDHCI_MAX_DIV_SPEC_300 2046 |
| 261 | |
Mikko Vinni | f6a03cb | 2011-04-12 09:36:18 -0400 | [diff] [blame] | 262 | /* |
| 263 | * Host SDMA buffer boundary. Valid values from 4K to 512K in powers of 2. |
| 264 | */ |
| 265 | #define SDHCI_DEFAULT_BOUNDARY_SIZE (512 * 1024) |
| 266 | #define SDHCI_DEFAULT_BOUNDARY_ARG (ilog2(SDHCI_DEFAULT_BOUNDARY_SIZE) - 12) |
| 267 | |
Pierre Ossman | b8c86fc | 2008-03-18 17:35:49 +0100 | [diff] [blame] | 268 | struct sdhci_ops { |
Anton Vorontsov | 4e4141a | 2009-03-17 00:13:46 +0300 | [diff] [blame] | 269 | #ifdef CONFIG_MMC_SDHCI_IO_ACCESSORS |
Matt Fleming | dc297c9 | 2010-05-26 14:42:03 -0700 | [diff] [blame] | 270 | u32 (*read_l)(struct sdhci_host *host, int reg); |
| 271 | u16 (*read_w)(struct sdhci_host *host, int reg); |
| 272 | u8 (*read_b)(struct sdhci_host *host, int reg); |
| 273 | void (*write_l)(struct sdhci_host *host, u32 val, int reg); |
| 274 | void (*write_w)(struct sdhci_host *host, u16 val, int reg); |
| 275 | void (*write_b)(struct sdhci_host *host, u8 val, int reg); |
Anton Vorontsov | 4e4141a | 2009-03-17 00:13:46 +0300 | [diff] [blame] | 276 | #endif |
| 277 | |
Anton Vorontsov | 8114634 | 2009-03-17 00:13:59 +0300 | [diff] [blame] | 278 | void (*set_clock)(struct sdhci_host *host, unsigned int clock); |
| 279 | |
Pierre Ossman | b8c86fc | 2008-03-18 17:35:49 +0100 | [diff] [blame] | 280 | int (*enable_dma)(struct sdhci_host *host); |
Ben Dooks | 4240ff0 | 2009-03-17 00:13:57 +0300 | [diff] [blame] | 281 | unsigned int (*get_max_clock)(struct sdhci_host *host); |
Anton Vorontsov | a9e58f2 | 2009-07-29 15:04:16 -0700 | [diff] [blame] | 282 | unsigned int (*get_min_clock)(struct sdhci_host *host); |
Ben Dooks | 4240ff0 | 2009-03-17 00:13:57 +0300 | [diff] [blame] | 283 | unsigned int (*get_timeout_clock)(struct sdhci_host *host); |
Aisheng Dong | a6ff5ae | 2014-08-27 15:26:27 +0800 | [diff] [blame^] | 284 | unsigned int (*get_max_timeout_count)(struct sdhci_host *host); |
Russell King | 2317f56 | 2014-04-25 12:57:07 +0100 | [diff] [blame] | 285 | void (*set_bus_width)(struct sdhci_host *host, int width); |
Philip Rakity | 643a81f | 2010-09-23 08:24:32 -0700 | [diff] [blame] | 286 | void (*platform_send_init_74_clocks)(struct sdhci_host *host, |
| 287 | u8 power_mode); |
Wolfram Sang | 2dfb579 | 2010-10-15 12:21:01 +0200 | [diff] [blame] | 288 | unsigned int (*get_ro)(struct sdhci_host *host); |
Russell King | 03231f9 | 2014-04-25 12:57:12 +0100 | [diff] [blame] | 289 | void (*reset)(struct sdhci_host *host, u8 mask); |
Dong Aisheng | 4525181 | 2013-09-13 19:11:30 +0800 | [diff] [blame] | 290 | int (*platform_execute_tuning)(struct sdhci_host *host, u32 opcode); |
Russell King | 13e6450 | 2014-04-25 12:59:20 +0100 | [diff] [blame] | 291 | void (*set_uhs_signaling)(struct sdhci_host *host, unsigned int uhs); |
Adrian Hunter | 20758b6 | 2011-08-29 16:42:12 +0300 | [diff] [blame] | 292 | void (*hw_reset)(struct sdhci_host *host); |
Haijun Zhang | a4071fb | 2012-12-04 10:41:28 +0800 | [diff] [blame] | 293 | void (*adma_workaround)(struct sdhci_host *host, u32 intmask); |
Jerry Huang | 63ef5d8 | 2012-10-25 13:47:19 +0800 | [diff] [blame] | 294 | void (*platform_init)(struct sdhci_host *host); |
Christian Daudt | 722e128 | 2013-06-20 14:26:36 -0700 | [diff] [blame] | 295 | void (*card_event)(struct sdhci_host *host); |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 296 | }; |
Pierre Ossman | b8c86fc | 2008-03-18 17:35:49 +0100 | [diff] [blame] | 297 | |
Anton Vorontsov | 4e4141a | 2009-03-17 00:13:46 +0300 | [diff] [blame] | 298 | #ifdef CONFIG_MMC_SDHCI_IO_ACCESSORS |
| 299 | |
| 300 | static inline void sdhci_writel(struct sdhci_host *host, u32 val, int reg) |
| 301 | { |
Matt Fleming | dc297c9 | 2010-05-26 14:42:03 -0700 | [diff] [blame] | 302 | if (unlikely(host->ops->write_l)) |
| 303 | host->ops->write_l(host, val, reg); |
Anton Vorontsov | 4e4141a | 2009-03-17 00:13:46 +0300 | [diff] [blame] | 304 | else |
| 305 | writel(val, host->ioaddr + reg); |
| 306 | } |
| 307 | |
| 308 | static inline void sdhci_writew(struct sdhci_host *host, u16 val, int reg) |
| 309 | { |
Matt Fleming | dc297c9 | 2010-05-26 14:42:03 -0700 | [diff] [blame] | 310 | if (unlikely(host->ops->write_w)) |
| 311 | host->ops->write_w(host, val, reg); |
Anton Vorontsov | 4e4141a | 2009-03-17 00:13:46 +0300 | [diff] [blame] | 312 | else |
| 313 | writew(val, host->ioaddr + reg); |
| 314 | } |
| 315 | |
| 316 | static inline void sdhci_writeb(struct sdhci_host *host, u8 val, int reg) |
| 317 | { |
Matt Fleming | dc297c9 | 2010-05-26 14:42:03 -0700 | [diff] [blame] | 318 | if (unlikely(host->ops->write_b)) |
| 319 | host->ops->write_b(host, val, reg); |
Anton Vorontsov | 4e4141a | 2009-03-17 00:13:46 +0300 | [diff] [blame] | 320 | else |
| 321 | writeb(val, host->ioaddr + reg); |
| 322 | } |
| 323 | |
| 324 | static inline u32 sdhci_readl(struct sdhci_host *host, int reg) |
| 325 | { |
Matt Fleming | dc297c9 | 2010-05-26 14:42:03 -0700 | [diff] [blame] | 326 | if (unlikely(host->ops->read_l)) |
| 327 | return host->ops->read_l(host, reg); |
Anton Vorontsov | 4e4141a | 2009-03-17 00:13:46 +0300 | [diff] [blame] | 328 | else |
| 329 | return readl(host->ioaddr + reg); |
| 330 | } |
| 331 | |
| 332 | static inline u16 sdhci_readw(struct sdhci_host *host, int reg) |
| 333 | { |
Matt Fleming | dc297c9 | 2010-05-26 14:42:03 -0700 | [diff] [blame] | 334 | if (unlikely(host->ops->read_w)) |
| 335 | return host->ops->read_w(host, reg); |
Anton Vorontsov | 4e4141a | 2009-03-17 00:13:46 +0300 | [diff] [blame] | 336 | else |
| 337 | return readw(host->ioaddr + reg); |
| 338 | } |
| 339 | |
| 340 | static inline u8 sdhci_readb(struct sdhci_host *host, int reg) |
| 341 | { |
Matt Fleming | dc297c9 | 2010-05-26 14:42:03 -0700 | [diff] [blame] | 342 | if (unlikely(host->ops->read_b)) |
| 343 | return host->ops->read_b(host, reg); |
Anton Vorontsov | 4e4141a | 2009-03-17 00:13:46 +0300 | [diff] [blame] | 344 | else |
| 345 | return readb(host->ioaddr + reg); |
| 346 | } |
| 347 | |
| 348 | #else |
| 349 | |
| 350 | static inline void sdhci_writel(struct sdhci_host *host, u32 val, int reg) |
| 351 | { |
| 352 | writel(val, host->ioaddr + reg); |
| 353 | } |
| 354 | |
| 355 | static inline void sdhci_writew(struct sdhci_host *host, u16 val, int reg) |
| 356 | { |
| 357 | writew(val, host->ioaddr + reg); |
| 358 | } |
| 359 | |
| 360 | static inline void sdhci_writeb(struct sdhci_host *host, u8 val, int reg) |
| 361 | { |
| 362 | writeb(val, host->ioaddr + reg); |
| 363 | } |
| 364 | |
| 365 | static inline u32 sdhci_readl(struct sdhci_host *host, int reg) |
| 366 | { |
| 367 | return readl(host->ioaddr + reg); |
| 368 | } |
| 369 | |
| 370 | static inline u16 sdhci_readw(struct sdhci_host *host, int reg) |
| 371 | { |
| 372 | return readw(host->ioaddr + reg); |
| 373 | } |
| 374 | |
| 375 | static inline u8 sdhci_readb(struct sdhci_host *host, int reg) |
| 376 | { |
| 377 | return readb(host->ioaddr + reg); |
| 378 | } |
| 379 | |
| 380 | #endif /* CONFIG_MMC_SDHCI_IO_ACCESSORS */ |
Pierre Ossman | b8c86fc | 2008-03-18 17:35:49 +0100 | [diff] [blame] | 381 | |
| 382 | extern struct sdhci_host *sdhci_alloc_host(struct device *dev, |
| 383 | size_t priv_size); |
| 384 | extern void sdhci_free_host(struct sdhci_host *host); |
| 385 | |
| 386 | static inline void *sdhci_priv(struct sdhci_host *host) |
| 387 | { |
| 388 | return (void *)host->private; |
| 389 | } |
| 390 | |
Marek Szyprowski | 17866e1 | 2010-08-10 18:01:58 -0700 | [diff] [blame] | 391 | extern void sdhci_card_detect(struct sdhci_host *host); |
Pierre Ossman | b8c86fc | 2008-03-18 17:35:49 +0100 | [diff] [blame] | 392 | extern int sdhci_add_host(struct sdhci_host *host); |
Pierre Ossman | 1e72859 | 2008-04-16 19:13:13 +0200 | [diff] [blame] | 393 | extern void sdhci_remove_host(struct sdhci_host *host, int dead); |
Dong Aisheng | c0e55129 | 2013-09-13 19:11:31 +0800 | [diff] [blame] | 394 | extern void sdhci_send_command(struct sdhci_host *host, |
| 395 | struct mmc_command *cmd); |
Pierre Ossman | b8c86fc | 2008-03-18 17:35:49 +0100 | [diff] [blame] | 396 | |
Russell King | be13855 | 2014-04-25 12:55:56 +0100 | [diff] [blame] | 397 | static inline bool sdhci_sdio_irq_enabled(struct sdhci_host *host) |
| 398 | { |
| 399 | return !!(host->flags & SDHCI_SDIO_IRQ_ENABLED); |
| 400 | } |
| 401 | |
Russell King | 1771059 | 2014-04-25 12:58:55 +0100 | [diff] [blame] | 402 | void sdhci_set_clock(struct sdhci_host *host, unsigned int clock); |
Russell King | 2317f56 | 2014-04-25 12:57:07 +0100 | [diff] [blame] | 403 | void sdhci_set_bus_width(struct sdhci_host *host, int width); |
Russell King | 03231f9 | 2014-04-25 12:57:12 +0100 | [diff] [blame] | 404 | void sdhci_reset(struct sdhci_host *host, u8 mask); |
Russell King | 96d7b78 | 2014-04-25 12:59:26 +0100 | [diff] [blame] | 405 | void sdhci_set_uhs_signaling(struct sdhci_host *host, unsigned timing); |
Russell King | 2317f56 | 2014-04-25 12:57:07 +0100 | [diff] [blame] | 406 | |
Pierre Ossman | b8c86fc | 2008-03-18 17:35:49 +0100 | [diff] [blame] | 407 | #ifdef CONFIG_PM |
Manuel Lauss | 29495aa | 2011-11-03 11:09:45 +0100 | [diff] [blame] | 408 | extern int sdhci_suspend_host(struct sdhci_host *host); |
Pierre Ossman | b8c86fc | 2008-03-18 17:35:49 +0100 | [diff] [blame] | 409 | extern int sdhci_resume_host(struct sdhci_host *host); |
Daniel Drake | 5f61970 | 2010-11-04 22:20:39 +0000 | [diff] [blame] | 410 | extern void sdhci_enable_irq_wakeups(struct sdhci_host *host); |
Pierre Ossman | b8c86fc | 2008-03-18 17:35:49 +0100 | [diff] [blame] | 411 | #endif |
Albert Herranz | c0bba0d | 2009-12-17 15:27:19 -0800 | [diff] [blame] | 412 | |
Adrian Hunter | 66fd8ad | 2011-10-03 15:33:34 +0300 | [diff] [blame] | 413 | #ifdef CONFIG_PM_RUNTIME |
| 414 | extern int sdhci_runtime_suspend_host(struct sdhci_host *host); |
| 415 | extern int sdhci_runtime_resume_host(struct sdhci_host *host); |
| 416 | #endif |
| 417 | |
Giuseppe Cavallaro | 1978fda | 2010-09-28 10:41:29 +0200 | [diff] [blame] | 418 | #endif /* __SDHCI_HW_H */ |