Yusuke Goda | fdc50a9 | 2010-05-26 14:41:59 -0700 | [diff] [blame] | 1 | /* |
| 2 | * MMCIF eMMC driver. |
| 3 | * |
| 4 | * Copyright (C) 2010 Renesas Solutions Corp. |
| 5 | * Yusuke Goda <yusuke.goda.sx@renesas.com> |
| 6 | * |
| 7 | * This program is free software; you can redistribute it and/or modify |
| 8 | * it under the terms of the GNU General Public License as published by |
| 9 | * the Free Software Foundation; either version 2 of the License. |
| 10 | * |
| 11 | * |
| 12 | * TODO |
| 13 | * 1. DMA |
| 14 | * 2. Power management |
| 15 | * 3. Handle MMC errors better |
| 16 | * |
| 17 | */ |
| 18 | |
Guennadi Liakhovetski | f985da1 | 2011-12-25 21:07:52 +0100 | [diff] [blame] | 19 | /* |
| 20 | * The MMCIF driver is now processing MMC requests asynchronously, according |
| 21 | * to the Linux MMC API requirement. |
| 22 | * |
| 23 | * The MMCIF driver processes MMC requests in up to 3 stages: command, optional |
| 24 | * data, and optional stop. To achieve asynchronous processing each of these |
| 25 | * stages is split into two halves: a top and a bottom half. The top half |
| 26 | * initialises the hardware, installs a timeout handler to handle completion |
| 27 | * timeouts, and returns. In case of the command stage this immediately returns |
| 28 | * control to the caller, leaving all further processing to run asynchronously. |
| 29 | * All further request processing is performed by the bottom halves. |
| 30 | * |
| 31 | * The bottom half further consists of a "hard" IRQ handler, an IRQ handler |
| 32 | * thread, a DMA completion callback, if DMA is used, a timeout work, and |
| 33 | * request- and stage-specific handler methods. |
| 34 | * |
| 35 | * Each bottom half run begins with either a hardware interrupt, a DMA callback |
| 36 | * invocation, or a timeout work run. In case of an error or a successful |
| 37 | * processing completion, the MMC core is informed and the request processing is |
| 38 | * finished. In case processing has to continue, i.e., if data has to be read |
| 39 | * from or written to the card, or if a stop command has to be sent, the next |
| 40 | * top half is called, which performs the necessary hardware handling and |
| 41 | * reschedules the timeout work. This returns the driver state machine into the |
| 42 | * bottom half waiting state. |
| 43 | */ |
| 44 | |
Guennadi Liakhovetski | 86df174 | 2011-11-23 15:52:30 +0100 | [diff] [blame] | 45 | #include <linux/bitops.h> |
Guennadi Liakhovetski | aa0787a | 2010-11-24 10:05:12 +0000 | [diff] [blame] | 46 | #include <linux/clk.h> |
| 47 | #include <linux/completion.h> |
Guennadi Liakhovetski | e47bf32 | 2010-11-24 10:05:18 +0000 | [diff] [blame] | 48 | #include <linux/delay.h> |
Yusuke Goda | fdc50a9 | 2010-05-26 14:41:59 -0700 | [diff] [blame] | 49 | #include <linux/dma-mapping.h> |
Guennadi Liakhovetski | a782d68 | 2010-11-24 10:05:22 +0000 | [diff] [blame] | 50 | #include <linux/dmaengine.h> |
Yusuke Goda | fdc50a9 | 2010-05-26 14:41:59 -0700 | [diff] [blame] | 51 | #include <linux/mmc/card.h> |
| 52 | #include <linux/mmc/core.h> |
Guennadi Liakhovetski | e47bf32 | 2010-11-24 10:05:18 +0000 | [diff] [blame] | 53 | #include <linux/mmc/host.h> |
Yusuke Goda | fdc50a9 | 2010-05-26 14:41:59 -0700 | [diff] [blame] | 54 | #include <linux/mmc/mmc.h> |
| 55 | #include <linux/mmc/sdio.h> |
Yusuke Goda | fdc50a9 | 2010-05-26 14:41:59 -0700 | [diff] [blame] | 56 | #include <linux/mmc/sh_mmcif.h> |
Guennadi Liakhovetski | e480606 | 2012-06-14 14:24:35 +0200 | [diff] [blame] | 57 | #include <linux/mmc/slot-gpio.h> |
Guennadi Liakhovetski | bf68a81 | 2012-05-01 18:18:16 +0200 | [diff] [blame] | 58 | #include <linux/mod_devicetable.h> |
Guennadi Liakhovetski | 8047310 | 2012-12-12 15:38:14 +0100 | [diff] [blame] | 59 | #include <linux/mutex.h> |
Guennadi Liakhovetski | a782d68 | 2010-11-24 10:05:22 +0000 | [diff] [blame] | 60 | #include <linux/pagemap.h> |
Guennadi Liakhovetski | e47bf32 | 2010-11-24 10:05:18 +0000 | [diff] [blame] | 61 | #include <linux/platform_device.h> |
Rafael J. Wysocki | efe6a8a | 2012-03-13 01:02:15 +0100 | [diff] [blame] | 62 | #include <linux/pm_qos.h> |
Guennadi Liakhovetski | faca664 | 2011-05-05 16:20:48 +0000 | [diff] [blame] | 63 | #include <linux/pm_runtime.h> |
Guennadi Liakhovetski | d00cada | 2013-08-02 14:48:02 +0200 | [diff] [blame] | 64 | #include <linux/sh_dma.h> |
Guennadi Liakhovetski | 3b0beaf | 2011-04-15 18:30:47 +0000 | [diff] [blame] | 65 | #include <linux/spinlock.h> |
Paul Gortmaker | 88b4767 | 2011-07-03 15:15:51 -0400 | [diff] [blame] | 66 | #include <linux/module.h> |
Yusuke Goda | fdc50a9 | 2010-05-26 14:41:59 -0700 | [diff] [blame] | 67 | |
| 68 | #define DRIVER_NAME "sh_mmcif" |
| 69 | #define DRIVER_VERSION "2010-04-28" |
| 70 | |
Yusuke Goda | fdc50a9 | 2010-05-26 14:41:59 -0700 | [diff] [blame] | 71 | /* CE_CMD_SET */ |
| 72 | #define CMD_MASK 0x3f000000 |
| 73 | #define CMD_SET_RTYP_NO ((0 << 23) | (0 << 22)) |
| 74 | #define CMD_SET_RTYP_6B ((0 << 23) | (1 << 22)) /* R1/R1b/R3/R4/R5 */ |
| 75 | #define CMD_SET_RTYP_17B ((1 << 23) | (0 << 22)) /* R2 */ |
| 76 | #define CMD_SET_RBSY (1 << 21) /* R1b */ |
| 77 | #define CMD_SET_CCSEN (1 << 20) |
| 78 | #define CMD_SET_WDAT (1 << 19) /* 1: on data, 0: no data */ |
| 79 | #define CMD_SET_DWEN (1 << 18) /* 1: write, 0: read */ |
| 80 | #define CMD_SET_CMLTE (1 << 17) /* 1: multi block trans, 0: single */ |
| 81 | #define CMD_SET_CMD12EN (1 << 16) /* 1: CMD12 auto issue */ |
| 82 | #define CMD_SET_RIDXC_INDEX ((0 << 15) | (0 << 14)) /* index check */ |
| 83 | #define CMD_SET_RIDXC_BITS ((0 << 15) | (1 << 14)) /* check bits check */ |
| 84 | #define CMD_SET_RIDXC_NO ((1 << 15) | (0 << 14)) /* no check */ |
| 85 | #define CMD_SET_CRC7C ((0 << 13) | (0 << 12)) /* CRC7 check*/ |
| 86 | #define CMD_SET_CRC7C_BITS ((0 << 13) | (1 << 12)) /* check bits check*/ |
| 87 | #define CMD_SET_CRC7C_INTERNAL ((1 << 13) | (0 << 12)) /* internal CRC7 check*/ |
| 88 | #define CMD_SET_CRC16C (1 << 10) /* 0: CRC16 check*/ |
| 89 | #define CMD_SET_CRCSTE (1 << 8) /* 1: not receive CRC status */ |
| 90 | #define CMD_SET_TBIT (1 << 7) /* 1: tran mission bit "Low" */ |
| 91 | #define CMD_SET_OPDM (1 << 6) /* 1: open/drain */ |
| 92 | #define CMD_SET_CCSH (1 << 5) |
Teppei Kamijou | 555061f | 2012-12-12 15:38:08 +0100 | [diff] [blame] | 93 | #define CMD_SET_DARS (1 << 2) /* Dual Data Rate */ |
Yusuke Goda | fdc50a9 | 2010-05-26 14:41:59 -0700 | [diff] [blame] | 94 | #define CMD_SET_DATW_1 ((0 << 1) | (0 << 0)) /* 1bit */ |
| 95 | #define CMD_SET_DATW_4 ((0 << 1) | (1 << 0)) /* 4bit */ |
| 96 | #define CMD_SET_DATW_8 ((1 << 1) | (0 << 0)) /* 8bit */ |
| 97 | |
| 98 | /* CE_CMD_CTRL */ |
| 99 | #define CMD_CTRL_BREAK (1 << 0) |
| 100 | |
| 101 | /* CE_BLOCK_SET */ |
| 102 | #define BLOCK_SIZE_MASK 0x0000ffff |
| 103 | |
Yusuke Goda | fdc50a9 | 2010-05-26 14:41:59 -0700 | [diff] [blame] | 104 | /* CE_INT */ |
| 105 | #define INT_CCSDE (1 << 29) |
| 106 | #define INT_CMD12DRE (1 << 26) |
| 107 | #define INT_CMD12RBE (1 << 25) |
| 108 | #define INT_CMD12CRE (1 << 24) |
| 109 | #define INT_DTRANE (1 << 23) |
| 110 | #define INT_BUFRE (1 << 22) |
| 111 | #define INT_BUFWEN (1 << 21) |
| 112 | #define INT_BUFREN (1 << 20) |
| 113 | #define INT_CCSRCV (1 << 19) |
| 114 | #define INT_RBSYE (1 << 17) |
| 115 | #define INT_CRSPE (1 << 16) |
| 116 | #define INT_CMDVIO (1 << 15) |
| 117 | #define INT_BUFVIO (1 << 14) |
| 118 | #define INT_WDATERR (1 << 11) |
| 119 | #define INT_RDATERR (1 << 10) |
| 120 | #define INT_RIDXERR (1 << 9) |
| 121 | #define INT_RSPERR (1 << 8) |
| 122 | #define INT_CCSTO (1 << 5) |
| 123 | #define INT_CRCSTO (1 << 4) |
| 124 | #define INT_WDATTO (1 << 3) |
| 125 | #define INT_RDATTO (1 << 2) |
| 126 | #define INT_RBSYTO (1 << 1) |
| 127 | #define INT_RSPTO (1 << 0) |
| 128 | #define INT_ERR_STS (INT_CMDVIO | INT_BUFVIO | INT_WDATERR | \ |
| 129 | INT_RDATERR | INT_RIDXERR | INT_RSPERR | \ |
| 130 | INT_CCSTO | INT_CRCSTO | INT_WDATTO | \ |
| 131 | INT_RDATTO | INT_RBSYTO | INT_RSPTO) |
| 132 | |
Guennadi Liakhovetski | 8af5075 | 2012-12-12 15:45:14 +0100 | [diff] [blame] | 133 | #define INT_ALL (INT_RBSYE | INT_CRSPE | INT_BUFREN | \ |
| 134 | INT_BUFWEN | INT_CMD12DRE | INT_BUFRE | \ |
| 135 | INT_DTRANE | INT_CMD12RBE | INT_CMD12CRE) |
| 136 | |
Yusuke Goda | fdc50a9 | 2010-05-26 14:41:59 -0700 | [diff] [blame] | 137 | /* CE_INT_MASK */ |
| 138 | #define MASK_ALL 0x00000000 |
| 139 | #define MASK_MCCSDE (1 << 29) |
| 140 | #define MASK_MCMD12DRE (1 << 26) |
| 141 | #define MASK_MCMD12RBE (1 << 25) |
| 142 | #define MASK_MCMD12CRE (1 << 24) |
| 143 | #define MASK_MDTRANE (1 << 23) |
| 144 | #define MASK_MBUFRE (1 << 22) |
| 145 | #define MASK_MBUFWEN (1 << 21) |
| 146 | #define MASK_MBUFREN (1 << 20) |
| 147 | #define MASK_MCCSRCV (1 << 19) |
| 148 | #define MASK_MRBSYE (1 << 17) |
| 149 | #define MASK_MCRSPE (1 << 16) |
| 150 | #define MASK_MCMDVIO (1 << 15) |
| 151 | #define MASK_MBUFVIO (1 << 14) |
| 152 | #define MASK_MWDATERR (1 << 11) |
| 153 | #define MASK_MRDATERR (1 << 10) |
| 154 | #define MASK_MRIDXERR (1 << 9) |
| 155 | #define MASK_MRSPERR (1 << 8) |
| 156 | #define MASK_MCCSTO (1 << 5) |
| 157 | #define MASK_MCRCSTO (1 << 4) |
| 158 | #define MASK_MWDATTO (1 << 3) |
| 159 | #define MASK_MRDATTO (1 << 2) |
| 160 | #define MASK_MRBSYTO (1 << 1) |
| 161 | #define MASK_MRSPTO (1 << 0) |
| 162 | |
Guennadi Liakhovetski | ee4b888 | 2011-12-14 19:31:52 +0100 | [diff] [blame] | 163 | #define MASK_START_CMD (MASK_MCMDVIO | MASK_MBUFVIO | MASK_MWDATERR | \ |
| 164 | MASK_MRDATERR | MASK_MRIDXERR | MASK_MRSPERR | \ |
| 165 | MASK_MCCSTO | MASK_MCRCSTO | MASK_MWDATTO | \ |
| 166 | MASK_MRDATTO | MASK_MRBSYTO | MASK_MRSPTO) |
| 167 | |
Guennadi Liakhovetski | 8af5075 | 2012-12-12 15:45:14 +0100 | [diff] [blame] | 168 | #define MASK_CLEAN (INT_ERR_STS | MASK_MRBSYE | MASK_MCRSPE | \ |
| 169 | MASK_MBUFREN | MASK_MBUFWEN | \ |
| 170 | MASK_MCMD12DRE | MASK_MBUFRE | MASK_MDTRANE | \ |
| 171 | MASK_MCMD12RBE | MASK_MCMD12CRE) |
| 172 | |
Yusuke Goda | fdc50a9 | 2010-05-26 14:41:59 -0700 | [diff] [blame] | 173 | /* CE_HOST_STS1 */ |
| 174 | #define STS1_CMDSEQ (1 << 31) |
| 175 | |
| 176 | /* CE_HOST_STS2 */ |
| 177 | #define STS2_CRCSTE (1 << 31) |
| 178 | #define STS2_CRC16E (1 << 30) |
| 179 | #define STS2_AC12CRCE (1 << 29) |
| 180 | #define STS2_RSPCRC7E (1 << 28) |
| 181 | #define STS2_CRCSTEBE (1 << 27) |
| 182 | #define STS2_RDATEBE (1 << 26) |
| 183 | #define STS2_AC12REBE (1 << 25) |
| 184 | #define STS2_RSPEBE (1 << 24) |
| 185 | #define STS2_AC12IDXE (1 << 23) |
| 186 | #define STS2_RSPIDXE (1 << 22) |
| 187 | #define STS2_CCSTO (1 << 15) |
| 188 | #define STS2_RDATTO (1 << 14) |
| 189 | #define STS2_DATBSYTO (1 << 13) |
| 190 | #define STS2_CRCSTTO (1 << 12) |
| 191 | #define STS2_AC12BSYTO (1 << 11) |
| 192 | #define STS2_RSPBSYTO (1 << 10) |
| 193 | #define STS2_AC12RSPTO (1 << 9) |
| 194 | #define STS2_RSPTO (1 << 8) |
| 195 | #define STS2_CRC_ERR (STS2_CRCSTE | STS2_CRC16E | \ |
| 196 | STS2_AC12CRCE | STS2_RSPCRC7E | STS2_CRCSTEBE) |
| 197 | #define STS2_TIMEOUT_ERR (STS2_CCSTO | STS2_RDATTO | \ |
| 198 | STS2_DATBSYTO | STS2_CRCSTTO | \ |
| 199 | STS2_AC12BSYTO | STS2_RSPBSYTO | \ |
| 200 | STS2_AC12RSPTO | STS2_RSPTO) |
| 201 | |
Yusuke Goda | fdc50a9 | 2010-05-26 14:41:59 -0700 | [diff] [blame] | 202 | #define CLKDEV_EMMC_DATA 52000000 /* 52MHz */ |
| 203 | #define CLKDEV_MMC_DATA 20000000 /* 20MHz */ |
| 204 | #define CLKDEV_INIT 400000 /* 400 KHz */ |
| 205 | |
Guennadi Liakhovetski | 3b0beaf | 2011-04-15 18:30:47 +0000 | [diff] [blame] | 206 | enum mmcif_state { |
| 207 | STATE_IDLE, |
| 208 | STATE_REQUEST, |
| 209 | STATE_IOS, |
Guennadi Liakhovetski | 8047310 | 2012-12-12 15:38:14 +0100 | [diff] [blame] | 210 | STATE_TIMEOUT, |
Guennadi Liakhovetski | 3b0beaf | 2011-04-15 18:30:47 +0000 | [diff] [blame] | 211 | }; |
| 212 | |
Guennadi Liakhovetski | f985da1 | 2011-12-25 21:07:52 +0100 | [diff] [blame] | 213 | enum mmcif_wait_for { |
| 214 | MMCIF_WAIT_FOR_REQUEST, |
| 215 | MMCIF_WAIT_FOR_CMD, |
| 216 | MMCIF_WAIT_FOR_MREAD, |
| 217 | MMCIF_WAIT_FOR_MWRITE, |
| 218 | MMCIF_WAIT_FOR_READ, |
| 219 | MMCIF_WAIT_FOR_WRITE, |
| 220 | MMCIF_WAIT_FOR_READ_END, |
| 221 | MMCIF_WAIT_FOR_WRITE_END, |
| 222 | MMCIF_WAIT_FOR_STOP, |
| 223 | }; |
| 224 | |
Yusuke Goda | fdc50a9 | 2010-05-26 14:41:59 -0700 | [diff] [blame] | 225 | struct sh_mmcif_host { |
| 226 | struct mmc_host *mmc; |
Guennadi Liakhovetski | f985da1 | 2011-12-25 21:07:52 +0100 | [diff] [blame] | 227 | struct mmc_request *mrq; |
Yusuke Goda | fdc50a9 | 2010-05-26 14:41:59 -0700 | [diff] [blame] | 228 | struct platform_device *pd; |
| 229 | struct clk *hclk; |
| 230 | unsigned int clk; |
| 231 | int bus_width; |
Teppei Kamijou | 555061f | 2012-12-12 15:38:08 +0100 | [diff] [blame] | 232 | unsigned char timing; |
Guennadi Liakhovetski | aa0787a | 2010-11-24 10:05:12 +0000 | [diff] [blame] | 233 | bool sd_error; |
Guennadi Liakhovetski | f985da1 | 2011-12-25 21:07:52 +0100 | [diff] [blame] | 234 | bool dying; |
Yusuke Goda | fdc50a9 | 2010-05-26 14:41:59 -0700 | [diff] [blame] | 235 | long timeout; |
| 236 | void __iomem *addr; |
Guennadi Liakhovetski | f985da1 | 2011-12-25 21:07:52 +0100 | [diff] [blame] | 237 | u32 *pio_ptr; |
Guennadi Liakhovetski | ee4b888 | 2011-12-14 19:31:52 +0100 | [diff] [blame] | 238 | spinlock_t lock; /* protect sh_mmcif_host::state */ |
Guennadi Liakhovetski | 3b0beaf | 2011-04-15 18:30:47 +0000 | [diff] [blame] | 239 | enum mmcif_state state; |
Guennadi Liakhovetski | f985da1 | 2011-12-25 21:07:52 +0100 | [diff] [blame] | 240 | enum mmcif_wait_for wait_for; |
| 241 | struct delayed_work timeout_work; |
| 242 | size_t blocksize; |
| 243 | int sg_idx; |
| 244 | int sg_blkidx; |
Guennadi Liakhovetski | faca664 | 2011-05-05 16:20:48 +0000 | [diff] [blame] | 245 | bool power; |
Guennadi Liakhovetski | c9b0cef | 2011-05-26 15:33:30 +0200 | [diff] [blame] | 246 | bool card_present; |
Guennadi Liakhovetski | 8047310 | 2012-12-12 15:38:14 +0100 | [diff] [blame] | 247 | struct mutex thread_lock; |
Yusuke Goda | fdc50a9 | 2010-05-26 14:41:59 -0700 | [diff] [blame] | 248 | |
Guennadi Liakhovetski | a782d68 | 2010-11-24 10:05:22 +0000 | [diff] [blame] | 249 | /* DMA support */ |
| 250 | struct dma_chan *chan_rx; |
| 251 | struct dma_chan *chan_tx; |
| 252 | struct completion dma_complete; |
Linus Walleij | f38f94c | 2011-02-10 16:09:50 +0100 | [diff] [blame] | 253 | bool dma_active; |
Guennadi Liakhovetski | a782d68 | 2010-11-24 10:05:22 +0000 | [diff] [blame] | 254 | }; |
Yusuke Goda | fdc50a9 | 2010-05-26 14:41:59 -0700 | [diff] [blame] | 255 | |
| 256 | static inline void sh_mmcif_bitset(struct sh_mmcif_host *host, |
| 257 | unsigned int reg, u32 val) |
| 258 | { |
Magnus Damm | 487d9fc | 2010-05-18 14:42:51 +0000 | [diff] [blame] | 259 | writel(val | readl(host->addr + reg), host->addr + reg); |
Yusuke Goda | fdc50a9 | 2010-05-26 14:41:59 -0700 | [diff] [blame] | 260 | } |
| 261 | |
| 262 | static inline void sh_mmcif_bitclr(struct sh_mmcif_host *host, |
| 263 | unsigned int reg, u32 val) |
| 264 | { |
Magnus Damm | 487d9fc | 2010-05-18 14:42:51 +0000 | [diff] [blame] | 265 | writel(~val & readl(host->addr + reg), host->addr + reg); |
Yusuke Goda | fdc50a9 | 2010-05-26 14:41:59 -0700 | [diff] [blame] | 266 | } |
| 267 | |
Guennadi Liakhovetski | a782d68 | 2010-11-24 10:05:22 +0000 | [diff] [blame] | 268 | static void mmcif_dma_complete(void *arg) |
| 269 | { |
| 270 | struct sh_mmcif_host *host = arg; |
Guennadi Liakhovetski | 8047310 | 2012-12-12 15:38:14 +0100 | [diff] [blame] | 271 | struct mmc_request *mrq = host->mrq; |
Guennadi Liakhovetski | 6998340 | 2011-12-26 12:52:13 -0500 | [diff] [blame] | 272 | |
Guennadi Liakhovetski | a782d68 | 2010-11-24 10:05:22 +0000 | [diff] [blame] | 273 | dev_dbg(&host->pd->dev, "Command completed\n"); |
| 274 | |
Guennadi Liakhovetski | 8047310 | 2012-12-12 15:38:14 +0100 | [diff] [blame] | 275 | if (WARN(!mrq || !mrq->data, "%s: NULL data in DMA completion!\n", |
Guennadi Liakhovetski | a782d68 | 2010-11-24 10:05:22 +0000 | [diff] [blame] | 276 | dev_name(&host->pd->dev))) |
| 277 | return; |
| 278 | |
Guennadi Liakhovetski | a782d68 | 2010-11-24 10:05:22 +0000 | [diff] [blame] | 279 | complete(&host->dma_complete); |
| 280 | } |
| 281 | |
| 282 | static void sh_mmcif_start_dma_rx(struct sh_mmcif_host *host) |
| 283 | { |
Guennadi Liakhovetski | 6998340 | 2011-12-26 12:52:13 -0500 | [diff] [blame] | 284 | struct mmc_data *data = host->mrq->data; |
| 285 | struct scatterlist *sg = data->sg; |
Guennadi Liakhovetski | a782d68 | 2010-11-24 10:05:22 +0000 | [diff] [blame] | 286 | struct dma_async_tx_descriptor *desc = NULL; |
| 287 | struct dma_chan *chan = host->chan_rx; |
| 288 | dma_cookie_t cookie = -EINVAL; |
| 289 | int ret; |
| 290 | |
Guennadi Liakhovetski | 6998340 | 2011-12-26 12:52:13 -0500 | [diff] [blame] | 291 | ret = dma_map_sg(chan->device->dev, sg, data->sg_len, |
Linus Walleij | 1ed828d | 2011-02-10 16:09:29 +0100 | [diff] [blame] | 292 | DMA_FROM_DEVICE); |
Guennadi Liakhovetski | a782d68 | 2010-11-24 10:05:22 +0000 | [diff] [blame] | 293 | if (ret > 0) { |
Linus Walleij | f38f94c | 2011-02-10 16:09:50 +0100 | [diff] [blame] | 294 | host->dma_active = true; |
Alexandre Bounine | 1605282 | 2012-03-08 16:11:18 -0500 | [diff] [blame] | 295 | desc = dmaengine_prep_slave_sg(chan, sg, ret, |
Vinod Koul | 05f5799 | 2011-10-14 10:45:11 +0530 | [diff] [blame] | 296 | DMA_DEV_TO_MEM, DMA_PREP_INTERRUPT | DMA_CTRL_ACK); |
Guennadi Liakhovetski | a782d68 | 2010-11-24 10:05:22 +0000 | [diff] [blame] | 297 | } |
| 298 | |
| 299 | if (desc) { |
| 300 | desc->callback = mmcif_dma_complete; |
| 301 | desc->callback_param = host; |
Linus Walleij | a5ece7d | 2011-02-10 16:10:00 +0100 | [diff] [blame] | 302 | cookie = dmaengine_submit(desc); |
| 303 | sh_mmcif_bitset(host, MMCIF_CE_BUF_ACC, BUF_ACC_DMAREN); |
| 304 | dma_async_issue_pending(chan); |
Guennadi Liakhovetski | a782d68 | 2010-11-24 10:05:22 +0000 | [diff] [blame] | 305 | } |
| 306 | dev_dbg(&host->pd->dev, "%s(): mapped %d -> %d, cookie %d\n", |
Guennadi Liakhovetski | 6998340 | 2011-12-26 12:52:13 -0500 | [diff] [blame] | 307 | __func__, data->sg_len, ret, cookie); |
Guennadi Liakhovetski | a782d68 | 2010-11-24 10:05:22 +0000 | [diff] [blame] | 308 | |
| 309 | if (!desc) { |
| 310 | /* DMA failed, fall back to PIO */ |
| 311 | if (ret >= 0) |
| 312 | ret = -EIO; |
| 313 | host->chan_rx = NULL; |
Linus Walleij | f38f94c | 2011-02-10 16:09:50 +0100 | [diff] [blame] | 314 | host->dma_active = false; |
Guennadi Liakhovetski | a782d68 | 2010-11-24 10:05:22 +0000 | [diff] [blame] | 315 | dma_release_channel(chan); |
| 316 | /* Free the Tx channel too */ |
| 317 | chan = host->chan_tx; |
| 318 | if (chan) { |
| 319 | host->chan_tx = NULL; |
| 320 | dma_release_channel(chan); |
| 321 | } |
| 322 | dev_warn(&host->pd->dev, |
| 323 | "DMA failed: %d, falling back to PIO\n", ret); |
| 324 | sh_mmcif_bitclr(host, MMCIF_CE_BUF_ACC, BUF_ACC_DMAREN | BUF_ACC_DMAWEN); |
| 325 | } |
| 326 | |
| 327 | dev_dbg(&host->pd->dev, "%s(): desc %p, cookie %d, sg[%d]\n", __func__, |
Guennadi Liakhovetski | 6998340 | 2011-12-26 12:52:13 -0500 | [diff] [blame] | 328 | desc, cookie, data->sg_len); |
Guennadi Liakhovetski | a782d68 | 2010-11-24 10:05:22 +0000 | [diff] [blame] | 329 | } |
| 330 | |
| 331 | static void sh_mmcif_start_dma_tx(struct sh_mmcif_host *host) |
| 332 | { |
Guennadi Liakhovetski | 6998340 | 2011-12-26 12:52:13 -0500 | [diff] [blame] | 333 | struct mmc_data *data = host->mrq->data; |
| 334 | struct scatterlist *sg = data->sg; |
Guennadi Liakhovetski | a782d68 | 2010-11-24 10:05:22 +0000 | [diff] [blame] | 335 | struct dma_async_tx_descriptor *desc = NULL; |
| 336 | struct dma_chan *chan = host->chan_tx; |
| 337 | dma_cookie_t cookie = -EINVAL; |
| 338 | int ret; |
| 339 | |
Guennadi Liakhovetski | 6998340 | 2011-12-26 12:52:13 -0500 | [diff] [blame] | 340 | ret = dma_map_sg(chan->device->dev, sg, data->sg_len, |
Linus Walleij | 1ed828d | 2011-02-10 16:09:29 +0100 | [diff] [blame] | 341 | DMA_TO_DEVICE); |
Guennadi Liakhovetski | a782d68 | 2010-11-24 10:05:22 +0000 | [diff] [blame] | 342 | if (ret > 0) { |
Linus Walleij | f38f94c | 2011-02-10 16:09:50 +0100 | [diff] [blame] | 343 | host->dma_active = true; |
Alexandre Bounine | 1605282 | 2012-03-08 16:11:18 -0500 | [diff] [blame] | 344 | desc = dmaengine_prep_slave_sg(chan, sg, ret, |
Vinod Koul | 05f5799 | 2011-10-14 10:45:11 +0530 | [diff] [blame] | 345 | DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT | DMA_CTRL_ACK); |
Guennadi Liakhovetski | a782d68 | 2010-11-24 10:05:22 +0000 | [diff] [blame] | 346 | } |
| 347 | |
| 348 | if (desc) { |
| 349 | desc->callback = mmcif_dma_complete; |
| 350 | desc->callback_param = host; |
Linus Walleij | a5ece7d | 2011-02-10 16:10:00 +0100 | [diff] [blame] | 351 | cookie = dmaengine_submit(desc); |
| 352 | sh_mmcif_bitset(host, MMCIF_CE_BUF_ACC, BUF_ACC_DMAWEN); |
| 353 | dma_async_issue_pending(chan); |
Guennadi Liakhovetski | a782d68 | 2010-11-24 10:05:22 +0000 | [diff] [blame] | 354 | } |
| 355 | dev_dbg(&host->pd->dev, "%s(): mapped %d -> %d, cookie %d\n", |
Guennadi Liakhovetski | 6998340 | 2011-12-26 12:52:13 -0500 | [diff] [blame] | 356 | __func__, data->sg_len, ret, cookie); |
Guennadi Liakhovetski | a782d68 | 2010-11-24 10:05:22 +0000 | [diff] [blame] | 357 | |
| 358 | if (!desc) { |
| 359 | /* DMA failed, fall back to PIO */ |
| 360 | if (ret >= 0) |
| 361 | ret = -EIO; |
| 362 | host->chan_tx = NULL; |
Linus Walleij | f38f94c | 2011-02-10 16:09:50 +0100 | [diff] [blame] | 363 | host->dma_active = false; |
Guennadi Liakhovetski | a782d68 | 2010-11-24 10:05:22 +0000 | [diff] [blame] | 364 | dma_release_channel(chan); |
| 365 | /* Free the Rx channel too */ |
| 366 | chan = host->chan_rx; |
| 367 | if (chan) { |
| 368 | host->chan_rx = NULL; |
| 369 | dma_release_channel(chan); |
| 370 | } |
| 371 | dev_warn(&host->pd->dev, |
| 372 | "DMA failed: %d, falling back to PIO\n", ret); |
| 373 | sh_mmcif_bitclr(host, MMCIF_CE_BUF_ACC, BUF_ACC_DMAREN | BUF_ACC_DMAWEN); |
| 374 | } |
| 375 | |
| 376 | dev_dbg(&host->pd->dev, "%s(): desc %p, cookie %d\n", __func__, |
| 377 | desc, cookie); |
| 378 | } |
| 379 | |
Guennadi Liakhovetski | a782d68 | 2010-11-24 10:05:22 +0000 | [diff] [blame] | 380 | static void sh_mmcif_request_dma(struct sh_mmcif_host *host, |
| 381 | struct sh_mmcif_plat_data *pdata) |
| 382 | { |
Guennadi Liakhovetski | 0e79f9a | 2012-07-05 12:29:43 +0200 | [diff] [blame] | 383 | struct resource *res = platform_get_resource(host->pd, IORESOURCE_MEM, 0); |
| 384 | struct dma_slave_config cfg; |
| 385 | dma_cap_mask_t mask; |
| 386 | int ret; |
| 387 | |
Linus Walleij | f38f94c | 2011-02-10 16:09:50 +0100 | [diff] [blame] | 388 | host->dma_active = false; |
Guennadi Liakhovetski | a782d68 | 2010-11-24 10:05:22 +0000 | [diff] [blame] | 389 | |
Guennadi Liakhovetski | acd6d77 | 2013-06-24 14:36:34 +0200 | [diff] [blame^] | 390 | if (pdata) { |
| 391 | if (pdata->slave_id_tx <= 0 || pdata->slave_id_rx <= 0) |
| 392 | return; |
| 393 | } else if (!host->pd->dev.of_node) { |
Guennadi Liakhovetski | bf68a81 | 2012-05-01 18:18:16 +0200 | [diff] [blame] | 394 | return; |
Guennadi Liakhovetski | acd6d77 | 2013-06-24 14:36:34 +0200 | [diff] [blame^] | 395 | } |
Guennadi Liakhovetski | 0e79f9a | 2012-07-05 12:29:43 +0200 | [diff] [blame] | 396 | |
Guennadi Liakhovetski | a782d68 | 2010-11-24 10:05:22 +0000 | [diff] [blame] | 397 | /* We can only either use DMA for both Tx and Rx or not use it at all */ |
Guennadi Liakhovetski | 0e79f9a | 2012-07-05 12:29:43 +0200 | [diff] [blame] | 398 | dma_cap_zero(mask); |
| 399 | dma_cap_set(DMA_SLAVE, mask); |
Guennadi Liakhovetski | a782d68 | 2010-11-24 10:05:22 +0000 | [diff] [blame] | 400 | |
Guennadi Liakhovetski | acd6d77 | 2013-06-24 14:36:34 +0200 | [diff] [blame^] | 401 | host->chan_tx = dma_request_slave_channel_compat(mask, shdma_chan_filter, |
| 402 | pdata ? (void *)pdata->slave_id_tx : NULL, |
| 403 | &host->pd->dev, "tx"); |
Guennadi Liakhovetski | 0e79f9a | 2012-07-05 12:29:43 +0200 | [diff] [blame] | 404 | dev_dbg(&host->pd->dev, "%s: TX: got channel %p\n", __func__, |
| 405 | host->chan_tx); |
Guennadi Liakhovetski | a782d68 | 2010-11-24 10:05:22 +0000 | [diff] [blame] | 406 | |
Guennadi Liakhovetski | 0e79f9a | 2012-07-05 12:29:43 +0200 | [diff] [blame] | 407 | if (!host->chan_tx) |
| 408 | return; |
Guennadi Liakhovetski | a782d68 | 2010-11-24 10:05:22 +0000 | [diff] [blame] | 409 | |
Guennadi Liakhovetski | acd6d77 | 2013-06-24 14:36:34 +0200 | [diff] [blame^] | 410 | /* In the OF case the driver will get the slave ID from the DT */ |
| 411 | if (pdata) |
| 412 | cfg.slave_id = pdata->slave_id_tx; |
Guennadi Liakhovetski | 0e79f9a | 2012-07-05 12:29:43 +0200 | [diff] [blame] | 413 | cfg.direction = DMA_MEM_TO_DEV; |
| 414 | cfg.dst_addr = res->start + MMCIF_CE_DATA; |
| 415 | cfg.src_addr = 0; |
| 416 | ret = dmaengine_slave_config(host->chan_tx, &cfg); |
| 417 | if (ret < 0) |
| 418 | goto ecfgtx; |
Guennadi Liakhovetski | a782d68 | 2010-11-24 10:05:22 +0000 | [diff] [blame] | 419 | |
Guennadi Liakhovetski | acd6d77 | 2013-06-24 14:36:34 +0200 | [diff] [blame^] | 420 | host->chan_rx = dma_request_slave_channel_compat(mask, shdma_chan_filter, |
| 421 | pdata ? (void *)pdata->slave_id_rx : NULL, |
| 422 | &host->pd->dev, "rx"); |
Guennadi Liakhovetski | 0e79f9a | 2012-07-05 12:29:43 +0200 | [diff] [blame] | 423 | dev_dbg(&host->pd->dev, "%s: RX: got channel %p\n", __func__, |
| 424 | host->chan_rx); |
Guennadi Liakhovetski | a782d68 | 2010-11-24 10:05:22 +0000 | [diff] [blame] | 425 | |
Guennadi Liakhovetski | 0e79f9a | 2012-07-05 12:29:43 +0200 | [diff] [blame] | 426 | if (!host->chan_rx) |
| 427 | goto erqrx; |
Guennadi Liakhovetski | a782d68 | 2010-11-24 10:05:22 +0000 | [diff] [blame] | 428 | |
Guennadi Liakhovetski | acd6d77 | 2013-06-24 14:36:34 +0200 | [diff] [blame^] | 429 | if (pdata) |
| 430 | cfg.slave_id = pdata->slave_id_rx; |
Guennadi Liakhovetski | 0e79f9a | 2012-07-05 12:29:43 +0200 | [diff] [blame] | 431 | cfg.direction = DMA_DEV_TO_MEM; |
| 432 | cfg.dst_addr = 0; |
| 433 | cfg.src_addr = res->start + MMCIF_CE_DATA; |
| 434 | ret = dmaengine_slave_config(host->chan_rx, &cfg); |
| 435 | if (ret < 0) |
| 436 | goto ecfgrx; |
Guennadi Liakhovetski | a782d68 | 2010-11-24 10:05:22 +0000 | [diff] [blame] | 437 | |
Guennadi Liakhovetski | 0e79f9a | 2012-07-05 12:29:43 +0200 | [diff] [blame] | 438 | return; |
| 439 | |
| 440 | ecfgrx: |
| 441 | dma_release_channel(host->chan_rx); |
| 442 | host->chan_rx = NULL; |
| 443 | erqrx: |
| 444 | ecfgtx: |
| 445 | dma_release_channel(host->chan_tx); |
| 446 | host->chan_tx = NULL; |
Guennadi Liakhovetski | a782d68 | 2010-11-24 10:05:22 +0000 | [diff] [blame] | 447 | } |
| 448 | |
| 449 | static void sh_mmcif_release_dma(struct sh_mmcif_host *host) |
| 450 | { |
| 451 | sh_mmcif_bitclr(host, MMCIF_CE_BUF_ACC, BUF_ACC_DMAREN | BUF_ACC_DMAWEN); |
| 452 | /* Descriptors are freed automatically */ |
| 453 | if (host->chan_tx) { |
| 454 | struct dma_chan *chan = host->chan_tx; |
| 455 | host->chan_tx = NULL; |
| 456 | dma_release_channel(chan); |
| 457 | } |
| 458 | if (host->chan_rx) { |
| 459 | struct dma_chan *chan = host->chan_rx; |
| 460 | host->chan_rx = NULL; |
| 461 | dma_release_channel(chan); |
| 462 | } |
| 463 | |
Linus Walleij | f38f94c | 2011-02-10 16:09:50 +0100 | [diff] [blame] | 464 | host->dma_active = false; |
Guennadi Liakhovetski | a782d68 | 2010-11-24 10:05:22 +0000 | [diff] [blame] | 465 | } |
Yusuke Goda | fdc50a9 | 2010-05-26 14:41:59 -0700 | [diff] [blame] | 466 | |
| 467 | static void sh_mmcif_clock_control(struct sh_mmcif_host *host, unsigned int clk) |
| 468 | { |
| 469 | struct sh_mmcif_plat_data *p = host->pd->dev.platform_data; |
Guennadi Liakhovetski | bf68a81 | 2012-05-01 18:18:16 +0200 | [diff] [blame] | 470 | bool sup_pclk = p ? p->sup_pclk : false; |
Yusuke Goda | fdc50a9 | 2010-05-26 14:41:59 -0700 | [diff] [blame] | 471 | |
| 472 | sh_mmcif_bitclr(host, MMCIF_CE_CLK_CTRL, CLK_ENABLE); |
| 473 | sh_mmcif_bitclr(host, MMCIF_CE_CLK_CTRL, CLK_CLEAR); |
| 474 | |
| 475 | if (!clk) |
| 476 | return; |
Guennadi Liakhovetski | bf68a81 | 2012-05-01 18:18:16 +0200 | [diff] [blame] | 477 | if (sup_pclk && clk == host->clk) |
Yusuke Goda | fdc50a9 | 2010-05-26 14:41:59 -0700 | [diff] [blame] | 478 | sh_mmcif_bitset(host, MMCIF_CE_CLK_CTRL, CLK_SUP_PCLK); |
| 479 | else |
| 480 | sh_mmcif_bitset(host, MMCIF_CE_CLK_CTRL, CLK_CLEAR & |
Simon Horman | f938825 | 2012-03-28 18:01:09 +0900 | [diff] [blame] | 481 | ((fls(DIV_ROUND_UP(host->clk, |
| 482 | clk) - 1) - 1) << 16)); |
Yusuke Goda | fdc50a9 | 2010-05-26 14:41:59 -0700 | [diff] [blame] | 483 | |
| 484 | sh_mmcif_bitset(host, MMCIF_CE_CLK_CTRL, CLK_ENABLE); |
| 485 | } |
| 486 | |
| 487 | static void sh_mmcif_sync_reset(struct sh_mmcif_host *host) |
| 488 | { |
| 489 | u32 tmp; |
| 490 | |
Magnus Damm | 487d9fc | 2010-05-18 14:42:51 +0000 | [diff] [blame] | 491 | tmp = 0x010f0000 & sh_mmcif_readl(host->addr, MMCIF_CE_CLK_CTRL); |
Yusuke Goda | fdc50a9 | 2010-05-26 14:41:59 -0700 | [diff] [blame] | 492 | |
Magnus Damm | 487d9fc | 2010-05-18 14:42:51 +0000 | [diff] [blame] | 493 | sh_mmcif_writel(host->addr, MMCIF_CE_VERSION, SOFT_RST_ON); |
| 494 | sh_mmcif_writel(host->addr, MMCIF_CE_VERSION, SOFT_RST_OFF); |
Yusuke Goda | fdc50a9 | 2010-05-26 14:41:59 -0700 | [diff] [blame] | 495 | sh_mmcif_bitset(host, MMCIF_CE_CLK_CTRL, tmp | |
| 496 | SRSPTO_256 | SRBSYTO_29 | SRWDTO_29 | SCCSTO_29); |
| 497 | /* byte swap on */ |
| 498 | sh_mmcif_bitset(host, MMCIF_CE_BUF_ACC, BUF_ACC_ATYP); |
| 499 | } |
| 500 | |
| 501 | static int sh_mmcif_error_manage(struct sh_mmcif_host *host) |
| 502 | { |
| 503 | u32 state1, state2; |
Guennadi Liakhovetski | ee4b888 | 2011-12-14 19:31:52 +0100 | [diff] [blame] | 504 | int ret, timeout; |
Yusuke Goda | fdc50a9 | 2010-05-26 14:41:59 -0700 | [diff] [blame] | 505 | |
Guennadi Liakhovetski | aa0787a | 2010-11-24 10:05:12 +0000 | [diff] [blame] | 506 | host->sd_error = false; |
Yusuke Goda | fdc50a9 | 2010-05-26 14:41:59 -0700 | [diff] [blame] | 507 | |
Magnus Damm | 487d9fc | 2010-05-18 14:42:51 +0000 | [diff] [blame] | 508 | state1 = sh_mmcif_readl(host->addr, MMCIF_CE_HOST_STS1); |
| 509 | state2 = sh_mmcif_readl(host->addr, MMCIF_CE_HOST_STS2); |
Guennadi Liakhovetski | e47bf32 | 2010-11-24 10:05:18 +0000 | [diff] [blame] | 510 | dev_dbg(&host->pd->dev, "ERR HOST_STS1 = %08x\n", state1); |
| 511 | dev_dbg(&host->pd->dev, "ERR HOST_STS2 = %08x\n", state2); |
Yusuke Goda | fdc50a9 | 2010-05-26 14:41:59 -0700 | [diff] [blame] | 512 | |
| 513 | if (state1 & STS1_CMDSEQ) { |
| 514 | sh_mmcif_bitset(host, MMCIF_CE_CMD_CTRL, CMD_CTRL_BREAK); |
| 515 | sh_mmcif_bitset(host, MMCIF_CE_CMD_CTRL, ~CMD_CTRL_BREAK); |
Guennadi Liakhovetski | ee4b888 | 2011-12-14 19:31:52 +0100 | [diff] [blame] | 516 | for (timeout = 10000000; timeout; timeout--) { |
Magnus Damm | 487d9fc | 2010-05-18 14:42:51 +0000 | [diff] [blame] | 517 | if (!(sh_mmcif_readl(host->addr, MMCIF_CE_HOST_STS1) |
Guennadi Liakhovetski | ee4b888 | 2011-12-14 19:31:52 +0100 | [diff] [blame] | 518 | & STS1_CMDSEQ)) |
Yusuke Goda | fdc50a9 | 2010-05-26 14:41:59 -0700 | [diff] [blame] | 519 | break; |
| 520 | mdelay(1); |
| 521 | } |
Guennadi Liakhovetski | ee4b888 | 2011-12-14 19:31:52 +0100 | [diff] [blame] | 522 | if (!timeout) { |
| 523 | dev_err(&host->pd->dev, |
| 524 | "Forced end of command sequence timeout err\n"); |
| 525 | return -EIO; |
| 526 | } |
Yusuke Goda | fdc50a9 | 2010-05-26 14:41:59 -0700 | [diff] [blame] | 527 | sh_mmcif_sync_reset(host); |
Guennadi Liakhovetski | e47bf32 | 2010-11-24 10:05:18 +0000 | [diff] [blame] | 528 | dev_dbg(&host->pd->dev, "Forced end of command sequence\n"); |
Yusuke Goda | fdc50a9 | 2010-05-26 14:41:59 -0700 | [diff] [blame] | 529 | return -EIO; |
| 530 | } |
| 531 | |
| 532 | if (state2 & STS2_CRC_ERR) { |
Teppei Kamijou | e475b27 | 2012-12-12 15:38:18 +0100 | [diff] [blame] | 533 | dev_err(&host->pd->dev, " CRC error: state %u, wait %u\n", |
| 534 | host->state, host->wait_for); |
Yusuke Goda | fdc50a9 | 2010-05-26 14:41:59 -0700 | [diff] [blame] | 535 | ret = -EIO; |
| 536 | } else if (state2 & STS2_TIMEOUT_ERR) { |
Teppei Kamijou | e475b27 | 2012-12-12 15:38:18 +0100 | [diff] [blame] | 537 | dev_err(&host->pd->dev, " Timeout: state %u, wait %u\n", |
| 538 | host->state, host->wait_for); |
Yusuke Goda | fdc50a9 | 2010-05-26 14:41:59 -0700 | [diff] [blame] | 539 | ret = -ETIMEDOUT; |
| 540 | } else { |
Teppei Kamijou | e475b27 | 2012-12-12 15:38:18 +0100 | [diff] [blame] | 541 | dev_dbg(&host->pd->dev, " End/Index error: state %u, wait %u\n", |
| 542 | host->state, host->wait_for); |
Yusuke Goda | fdc50a9 | 2010-05-26 14:41:59 -0700 | [diff] [blame] | 543 | ret = -EIO; |
| 544 | } |
| 545 | return ret; |
| 546 | } |
| 547 | |
Guennadi Liakhovetski | f985da1 | 2011-12-25 21:07:52 +0100 | [diff] [blame] | 548 | static bool sh_mmcif_next_block(struct sh_mmcif_host *host, u32 *p) |
Yusuke Goda | fdc50a9 | 2010-05-26 14:41:59 -0700 | [diff] [blame] | 549 | { |
Guennadi Liakhovetski | f985da1 | 2011-12-25 21:07:52 +0100 | [diff] [blame] | 550 | struct mmc_data *data = host->mrq->data; |
| 551 | |
| 552 | host->sg_blkidx += host->blocksize; |
| 553 | |
| 554 | /* data->sg->length must be a multiple of host->blocksize? */ |
| 555 | BUG_ON(host->sg_blkidx > data->sg->length); |
| 556 | |
| 557 | if (host->sg_blkidx == data->sg->length) { |
| 558 | host->sg_blkidx = 0; |
| 559 | if (++host->sg_idx < data->sg_len) |
| 560 | host->pio_ptr = sg_virt(++data->sg); |
| 561 | } else { |
| 562 | host->pio_ptr = p; |
| 563 | } |
| 564 | |
Guennadi Liakhovetski | 99eb9d8 | 2012-12-12 15:38:13 +0100 | [diff] [blame] | 565 | return host->sg_idx != data->sg_len; |
Guennadi Liakhovetski | f985da1 | 2011-12-25 21:07:52 +0100 | [diff] [blame] | 566 | } |
| 567 | |
| 568 | static void sh_mmcif_single_read(struct sh_mmcif_host *host, |
| 569 | struct mmc_request *mrq) |
| 570 | { |
| 571 | host->blocksize = (sh_mmcif_readl(host->addr, MMCIF_CE_BLOCK_SET) & |
| 572 | BLOCK_SIZE_MASK) + 3; |
| 573 | |
| 574 | host->wait_for = MMCIF_WAIT_FOR_READ; |
Yusuke Goda | fdc50a9 | 2010-05-26 14:41:59 -0700 | [diff] [blame] | 575 | |
Yusuke Goda | fdc50a9 | 2010-05-26 14:41:59 -0700 | [diff] [blame] | 576 | /* buf read enable */ |
| 577 | sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFREN); |
Guennadi Liakhovetski | f985da1 | 2011-12-25 21:07:52 +0100 | [diff] [blame] | 578 | } |
Yusuke Goda | fdc50a9 | 2010-05-26 14:41:59 -0700 | [diff] [blame] | 579 | |
Guennadi Liakhovetski | f985da1 | 2011-12-25 21:07:52 +0100 | [diff] [blame] | 580 | static bool sh_mmcif_read_block(struct sh_mmcif_host *host) |
| 581 | { |
| 582 | struct mmc_data *data = host->mrq->data; |
| 583 | u32 *p = sg_virt(data->sg); |
| 584 | int i; |
| 585 | |
| 586 | if (host->sd_error) { |
| 587 | data->error = sh_mmcif_error_manage(host); |
Teppei Kamijou | e475b27 | 2012-12-12 15:38:18 +0100 | [diff] [blame] | 588 | dev_dbg(&host->pd->dev, "%s(): %d\n", __func__, data->error); |
Guennadi Liakhovetski | f985da1 | 2011-12-25 21:07:52 +0100 | [diff] [blame] | 589 | return false; |
| 590 | } |
| 591 | |
| 592 | for (i = 0; i < host->blocksize / 4; i++) |
Magnus Damm | 487d9fc | 2010-05-18 14:42:51 +0000 | [diff] [blame] | 593 | *p++ = sh_mmcif_readl(host->addr, MMCIF_CE_DATA); |
Yusuke Goda | fdc50a9 | 2010-05-26 14:41:59 -0700 | [diff] [blame] | 594 | |
| 595 | /* buffer read end */ |
| 596 | sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFRE); |
Guennadi Liakhovetski | f985da1 | 2011-12-25 21:07:52 +0100 | [diff] [blame] | 597 | host->wait_for = MMCIF_WAIT_FOR_READ_END; |
Yusuke Goda | fdc50a9 | 2010-05-26 14:41:59 -0700 | [diff] [blame] | 598 | |
Guennadi Liakhovetski | f985da1 | 2011-12-25 21:07:52 +0100 | [diff] [blame] | 599 | return true; |
Yusuke Goda | fdc50a9 | 2010-05-26 14:41:59 -0700 | [diff] [blame] | 600 | } |
| 601 | |
Guennadi Liakhovetski | f985da1 | 2011-12-25 21:07:52 +0100 | [diff] [blame] | 602 | static void sh_mmcif_multi_read(struct sh_mmcif_host *host, |
| 603 | struct mmc_request *mrq) |
Yusuke Goda | fdc50a9 | 2010-05-26 14:41:59 -0700 | [diff] [blame] | 604 | { |
| 605 | struct mmc_data *data = mrq->data; |
Yusuke Goda | fdc50a9 | 2010-05-26 14:41:59 -0700 | [diff] [blame] | 606 | |
Guennadi Liakhovetski | f985da1 | 2011-12-25 21:07:52 +0100 | [diff] [blame] | 607 | if (!data->sg_len || !data->sg->length) |
| 608 | return; |
Yusuke Goda | fdc50a9 | 2010-05-26 14:41:59 -0700 | [diff] [blame] | 609 | |
Guennadi Liakhovetski | f985da1 | 2011-12-25 21:07:52 +0100 | [diff] [blame] | 610 | host->blocksize = sh_mmcif_readl(host->addr, MMCIF_CE_BLOCK_SET) & |
| 611 | BLOCK_SIZE_MASK; |
Yusuke Goda | fdc50a9 | 2010-05-26 14:41:59 -0700 | [diff] [blame] | 612 | |
Guennadi Liakhovetski | f985da1 | 2011-12-25 21:07:52 +0100 | [diff] [blame] | 613 | host->wait_for = MMCIF_WAIT_FOR_MREAD; |
| 614 | host->sg_idx = 0; |
| 615 | host->sg_blkidx = 0; |
| 616 | host->pio_ptr = sg_virt(data->sg); |
Guennadi Liakhovetski | 5df460b | 2012-12-12 15:38:11 +0100 | [diff] [blame] | 617 | |
Guennadi Liakhovetski | f985da1 | 2011-12-25 21:07:52 +0100 | [diff] [blame] | 618 | sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFREN); |
| 619 | } |
| 620 | |
| 621 | static bool sh_mmcif_mread_block(struct sh_mmcif_host *host) |
| 622 | { |
| 623 | struct mmc_data *data = host->mrq->data; |
| 624 | u32 *p = host->pio_ptr; |
| 625 | int i; |
| 626 | |
| 627 | if (host->sd_error) { |
| 628 | data->error = sh_mmcif_error_manage(host); |
Teppei Kamijou | e475b27 | 2012-12-12 15:38:18 +0100 | [diff] [blame] | 629 | dev_dbg(&host->pd->dev, "%s(): %d\n", __func__, data->error); |
Guennadi Liakhovetski | f985da1 | 2011-12-25 21:07:52 +0100 | [diff] [blame] | 630 | return false; |
Yusuke Goda | fdc50a9 | 2010-05-26 14:41:59 -0700 | [diff] [blame] | 631 | } |
Guennadi Liakhovetski | f985da1 | 2011-12-25 21:07:52 +0100 | [diff] [blame] | 632 | |
| 633 | BUG_ON(!data->sg->length); |
| 634 | |
| 635 | for (i = 0; i < host->blocksize / 4; i++) |
| 636 | *p++ = sh_mmcif_readl(host->addr, MMCIF_CE_DATA); |
| 637 | |
| 638 | if (!sh_mmcif_next_block(host, p)) |
| 639 | return false; |
| 640 | |
Guennadi Liakhovetski | f985da1 | 2011-12-25 21:07:52 +0100 | [diff] [blame] | 641 | sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFREN); |
| 642 | |
| 643 | return true; |
Yusuke Goda | fdc50a9 | 2010-05-26 14:41:59 -0700 | [diff] [blame] | 644 | } |
| 645 | |
Guennadi Liakhovetski | f985da1 | 2011-12-25 21:07:52 +0100 | [diff] [blame] | 646 | static void sh_mmcif_single_write(struct sh_mmcif_host *host, |
Yusuke Goda | fdc50a9 | 2010-05-26 14:41:59 -0700 | [diff] [blame] | 647 | struct mmc_request *mrq) |
| 648 | { |
Guennadi Liakhovetski | f985da1 | 2011-12-25 21:07:52 +0100 | [diff] [blame] | 649 | host->blocksize = (sh_mmcif_readl(host->addr, MMCIF_CE_BLOCK_SET) & |
| 650 | BLOCK_SIZE_MASK) + 3; |
Yusuke Goda | fdc50a9 | 2010-05-26 14:41:59 -0700 | [diff] [blame] | 651 | |
Guennadi Liakhovetski | f985da1 | 2011-12-25 21:07:52 +0100 | [diff] [blame] | 652 | host->wait_for = MMCIF_WAIT_FOR_WRITE; |
Yusuke Goda | fdc50a9 | 2010-05-26 14:41:59 -0700 | [diff] [blame] | 653 | |
| 654 | /* buf write enable */ |
Guennadi Liakhovetski | f985da1 | 2011-12-25 21:07:52 +0100 | [diff] [blame] | 655 | sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFWEN); |
| 656 | } |
Yusuke Goda | fdc50a9 | 2010-05-26 14:41:59 -0700 | [diff] [blame] | 657 | |
Guennadi Liakhovetski | f985da1 | 2011-12-25 21:07:52 +0100 | [diff] [blame] | 658 | static bool sh_mmcif_write_block(struct sh_mmcif_host *host) |
| 659 | { |
| 660 | struct mmc_data *data = host->mrq->data; |
| 661 | u32 *p = sg_virt(data->sg); |
| 662 | int i; |
| 663 | |
| 664 | if (host->sd_error) { |
| 665 | data->error = sh_mmcif_error_manage(host); |
Teppei Kamijou | e475b27 | 2012-12-12 15:38:18 +0100 | [diff] [blame] | 666 | dev_dbg(&host->pd->dev, "%s(): %d\n", __func__, data->error); |
Guennadi Liakhovetski | f985da1 | 2011-12-25 21:07:52 +0100 | [diff] [blame] | 667 | return false; |
| 668 | } |
| 669 | |
| 670 | for (i = 0; i < host->blocksize / 4; i++) |
Magnus Damm | 487d9fc | 2010-05-18 14:42:51 +0000 | [diff] [blame] | 671 | sh_mmcif_writel(host->addr, MMCIF_CE_DATA, *p++); |
Yusuke Goda | fdc50a9 | 2010-05-26 14:41:59 -0700 | [diff] [blame] | 672 | |
| 673 | /* buffer write end */ |
| 674 | sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MDTRANE); |
Guennadi Liakhovetski | f985da1 | 2011-12-25 21:07:52 +0100 | [diff] [blame] | 675 | host->wait_for = MMCIF_WAIT_FOR_WRITE_END; |
Yusuke Goda | fdc50a9 | 2010-05-26 14:41:59 -0700 | [diff] [blame] | 676 | |
Guennadi Liakhovetski | f985da1 | 2011-12-25 21:07:52 +0100 | [diff] [blame] | 677 | return true; |
Yusuke Goda | fdc50a9 | 2010-05-26 14:41:59 -0700 | [diff] [blame] | 678 | } |
| 679 | |
Guennadi Liakhovetski | f985da1 | 2011-12-25 21:07:52 +0100 | [diff] [blame] | 680 | static void sh_mmcif_multi_write(struct sh_mmcif_host *host, |
| 681 | struct mmc_request *mrq) |
Yusuke Goda | fdc50a9 | 2010-05-26 14:41:59 -0700 | [diff] [blame] | 682 | { |
| 683 | struct mmc_data *data = mrq->data; |
Yusuke Goda | fdc50a9 | 2010-05-26 14:41:59 -0700 | [diff] [blame] | 684 | |
Guennadi Liakhovetski | f985da1 | 2011-12-25 21:07:52 +0100 | [diff] [blame] | 685 | if (!data->sg_len || !data->sg->length) |
| 686 | return; |
Yusuke Goda | fdc50a9 | 2010-05-26 14:41:59 -0700 | [diff] [blame] | 687 | |
Guennadi Liakhovetski | f985da1 | 2011-12-25 21:07:52 +0100 | [diff] [blame] | 688 | host->blocksize = sh_mmcif_readl(host->addr, MMCIF_CE_BLOCK_SET) & |
| 689 | BLOCK_SIZE_MASK; |
Yusuke Goda | fdc50a9 | 2010-05-26 14:41:59 -0700 | [diff] [blame] | 690 | |
Guennadi Liakhovetski | f985da1 | 2011-12-25 21:07:52 +0100 | [diff] [blame] | 691 | host->wait_for = MMCIF_WAIT_FOR_MWRITE; |
| 692 | host->sg_idx = 0; |
| 693 | host->sg_blkidx = 0; |
| 694 | host->pio_ptr = sg_virt(data->sg); |
Guennadi Liakhovetski | 5df460b | 2012-12-12 15:38:11 +0100 | [diff] [blame] | 695 | |
Guennadi Liakhovetski | f985da1 | 2011-12-25 21:07:52 +0100 | [diff] [blame] | 696 | sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFWEN); |
| 697 | } |
Yusuke Goda | fdc50a9 | 2010-05-26 14:41:59 -0700 | [diff] [blame] | 698 | |
Guennadi Liakhovetski | f985da1 | 2011-12-25 21:07:52 +0100 | [diff] [blame] | 699 | static bool sh_mmcif_mwrite_block(struct sh_mmcif_host *host) |
| 700 | { |
| 701 | struct mmc_data *data = host->mrq->data; |
| 702 | u32 *p = host->pio_ptr; |
| 703 | int i; |
| 704 | |
| 705 | if (host->sd_error) { |
| 706 | data->error = sh_mmcif_error_manage(host); |
Teppei Kamijou | e475b27 | 2012-12-12 15:38:18 +0100 | [diff] [blame] | 707 | dev_dbg(&host->pd->dev, "%s(): %d\n", __func__, data->error); |
Guennadi Liakhovetski | f985da1 | 2011-12-25 21:07:52 +0100 | [diff] [blame] | 708 | return false; |
Yusuke Goda | fdc50a9 | 2010-05-26 14:41:59 -0700 | [diff] [blame] | 709 | } |
Guennadi Liakhovetski | f985da1 | 2011-12-25 21:07:52 +0100 | [diff] [blame] | 710 | |
| 711 | BUG_ON(!data->sg->length); |
| 712 | |
| 713 | for (i = 0; i < host->blocksize / 4; i++) |
| 714 | sh_mmcif_writel(host->addr, MMCIF_CE_DATA, *p++); |
| 715 | |
| 716 | if (!sh_mmcif_next_block(host, p)) |
| 717 | return false; |
| 718 | |
Guennadi Liakhovetski | f985da1 | 2011-12-25 21:07:52 +0100 | [diff] [blame] | 719 | sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFWEN); |
| 720 | |
| 721 | return true; |
Yusuke Goda | fdc50a9 | 2010-05-26 14:41:59 -0700 | [diff] [blame] | 722 | } |
| 723 | |
| 724 | static void sh_mmcif_get_response(struct sh_mmcif_host *host, |
| 725 | struct mmc_command *cmd) |
| 726 | { |
| 727 | if (cmd->flags & MMC_RSP_136) { |
Magnus Damm | 487d9fc | 2010-05-18 14:42:51 +0000 | [diff] [blame] | 728 | cmd->resp[0] = sh_mmcif_readl(host->addr, MMCIF_CE_RESP3); |
| 729 | cmd->resp[1] = sh_mmcif_readl(host->addr, MMCIF_CE_RESP2); |
| 730 | cmd->resp[2] = sh_mmcif_readl(host->addr, MMCIF_CE_RESP1); |
| 731 | cmd->resp[3] = sh_mmcif_readl(host->addr, MMCIF_CE_RESP0); |
Yusuke Goda | fdc50a9 | 2010-05-26 14:41:59 -0700 | [diff] [blame] | 732 | } else |
Magnus Damm | 487d9fc | 2010-05-18 14:42:51 +0000 | [diff] [blame] | 733 | cmd->resp[0] = sh_mmcif_readl(host->addr, MMCIF_CE_RESP0); |
Yusuke Goda | fdc50a9 | 2010-05-26 14:41:59 -0700 | [diff] [blame] | 734 | } |
| 735 | |
| 736 | static void sh_mmcif_get_cmd12response(struct sh_mmcif_host *host, |
| 737 | struct mmc_command *cmd) |
| 738 | { |
Magnus Damm | 487d9fc | 2010-05-18 14:42:51 +0000 | [diff] [blame] | 739 | cmd->resp[0] = sh_mmcif_readl(host->addr, MMCIF_CE_RESP_CMD12); |
Yusuke Goda | fdc50a9 | 2010-05-26 14:41:59 -0700 | [diff] [blame] | 740 | } |
| 741 | |
| 742 | static u32 sh_mmcif_set_cmd(struct sh_mmcif_host *host, |
Guennadi Liakhovetski | 6998340 | 2011-12-26 12:52:13 -0500 | [diff] [blame] | 743 | struct mmc_request *mrq) |
Yusuke Goda | fdc50a9 | 2010-05-26 14:41:59 -0700 | [diff] [blame] | 744 | { |
Guennadi Liakhovetski | 6998340 | 2011-12-26 12:52:13 -0500 | [diff] [blame] | 745 | struct mmc_data *data = mrq->data; |
| 746 | struct mmc_command *cmd = mrq->cmd; |
| 747 | u32 opc = cmd->opcode; |
Yusuke Goda | fdc50a9 | 2010-05-26 14:41:59 -0700 | [diff] [blame] | 748 | u32 tmp = 0; |
| 749 | |
| 750 | /* Response Type check */ |
| 751 | switch (mmc_resp_type(cmd)) { |
| 752 | case MMC_RSP_NONE: |
| 753 | tmp |= CMD_SET_RTYP_NO; |
| 754 | break; |
| 755 | case MMC_RSP_R1: |
| 756 | case MMC_RSP_R1B: |
| 757 | case MMC_RSP_R3: |
| 758 | tmp |= CMD_SET_RTYP_6B; |
| 759 | break; |
| 760 | case MMC_RSP_R2: |
| 761 | tmp |= CMD_SET_RTYP_17B; |
| 762 | break; |
| 763 | default: |
Guennadi Liakhovetski | e47bf32 | 2010-11-24 10:05:18 +0000 | [diff] [blame] | 764 | dev_err(&host->pd->dev, "Unsupported response type.\n"); |
Yusuke Goda | fdc50a9 | 2010-05-26 14:41:59 -0700 | [diff] [blame] | 765 | break; |
| 766 | } |
| 767 | switch (opc) { |
| 768 | /* RBSY */ |
Teppei Kamijou | a812ba0 | 2012-12-12 15:38:10 +0100 | [diff] [blame] | 769 | case MMC_SLEEP_AWAKE: |
Yusuke Goda | fdc50a9 | 2010-05-26 14:41:59 -0700 | [diff] [blame] | 770 | case MMC_SWITCH: |
| 771 | case MMC_STOP_TRANSMISSION: |
| 772 | case MMC_SET_WRITE_PROT: |
| 773 | case MMC_CLR_WRITE_PROT: |
| 774 | case MMC_ERASE: |
Yusuke Goda | fdc50a9 | 2010-05-26 14:41:59 -0700 | [diff] [blame] | 775 | tmp |= CMD_SET_RBSY; |
| 776 | break; |
| 777 | } |
| 778 | /* WDAT / DATW */ |
Guennadi Liakhovetski | 6998340 | 2011-12-26 12:52:13 -0500 | [diff] [blame] | 779 | if (data) { |
Yusuke Goda | fdc50a9 | 2010-05-26 14:41:59 -0700 | [diff] [blame] | 780 | tmp |= CMD_SET_WDAT; |
| 781 | switch (host->bus_width) { |
| 782 | case MMC_BUS_WIDTH_1: |
| 783 | tmp |= CMD_SET_DATW_1; |
| 784 | break; |
| 785 | case MMC_BUS_WIDTH_4: |
| 786 | tmp |= CMD_SET_DATW_4; |
| 787 | break; |
| 788 | case MMC_BUS_WIDTH_8: |
| 789 | tmp |= CMD_SET_DATW_8; |
| 790 | break; |
| 791 | default: |
Guennadi Liakhovetski | e47bf32 | 2010-11-24 10:05:18 +0000 | [diff] [blame] | 792 | dev_err(&host->pd->dev, "Unsupported bus width.\n"); |
Yusuke Goda | fdc50a9 | 2010-05-26 14:41:59 -0700 | [diff] [blame] | 793 | break; |
| 794 | } |
Teppei Kamijou | 555061f | 2012-12-12 15:38:08 +0100 | [diff] [blame] | 795 | switch (host->timing) { |
| 796 | case MMC_TIMING_UHS_DDR50: |
| 797 | /* |
| 798 | * MMC core will only set this timing, if the host |
| 799 | * advertises the MMC_CAP_UHS_DDR50 capability. MMCIF |
| 800 | * implementations with this capability, e.g. sh73a0, |
| 801 | * will have to set it in their platform data. |
| 802 | */ |
| 803 | tmp |= CMD_SET_DARS; |
| 804 | break; |
| 805 | } |
Yusuke Goda | fdc50a9 | 2010-05-26 14:41:59 -0700 | [diff] [blame] | 806 | } |
| 807 | /* DWEN */ |
| 808 | if (opc == MMC_WRITE_BLOCK || opc == MMC_WRITE_MULTIPLE_BLOCK) |
| 809 | tmp |= CMD_SET_DWEN; |
| 810 | /* CMLTE/CMD12EN */ |
| 811 | if (opc == MMC_READ_MULTIPLE_BLOCK || opc == MMC_WRITE_MULTIPLE_BLOCK) { |
| 812 | tmp |= CMD_SET_CMLTE | CMD_SET_CMD12EN; |
| 813 | sh_mmcif_bitset(host, MMCIF_CE_BLOCK_SET, |
Guennadi Liakhovetski | 6998340 | 2011-12-26 12:52:13 -0500 | [diff] [blame] | 814 | data->blocks << 16); |
Yusuke Goda | fdc50a9 | 2010-05-26 14:41:59 -0700 | [diff] [blame] | 815 | } |
| 816 | /* RIDXC[1:0] check bits */ |
| 817 | if (opc == MMC_SEND_OP_COND || opc == MMC_ALL_SEND_CID || |
| 818 | opc == MMC_SEND_CSD || opc == MMC_SEND_CID) |
| 819 | tmp |= CMD_SET_RIDXC_BITS; |
| 820 | /* RCRC7C[1:0] check bits */ |
| 821 | if (opc == MMC_SEND_OP_COND) |
| 822 | tmp |= CMD_SET_CRC7C_BITS; |
| 823 | /* RCRC7C[1:0] internal CRC7 */ |
| 824 | if (opc == MMC_ALL_SEND_CID || |
| 825 | opc == MMC_SEND_CSD || opc == MMC_SEND_CID) |
| 826 | tmp |= CMD_SET_CRC7C_INTERNAL; |
| 827 | |
Guennadi Liakhovetski | 6998340 | 2011-12-26 12:52:13 -0500 | [diff] [blame] | 828 | return (opc << 24) | tmp; |
Yusuke Goda | fdc50a9 | 2010-05-26 14:41:59 -0700 | [diff] [blame] | 829 | } |
| 830 | |
Guennadi Liakhovetski | e47bf32 | 2010-11-24 10:05:18 +0000 | [diff] [blame] | 831 | static int sh_mmcif_data_trans(struct sh_mmcif_host *host, |
Guennadi Liakhovetski | f985da1 | 2011-12-25 21:07:52 +0100 | [diff] [blame] | 832 | struct mmc_request *mrq, u32 opc) |
Yusuke Goda | fdc50a9 | 2010-05-26 14:41:59 -0700 | [diff] [blame] | 833 | { |
Yusuke Goda | fdc50a9 | 2010-05-26 14:41:59 -0700 | [diff] [blame] | 834 | switch (opc) { |
| 835 | case MMC_READ_MULTIPLE_BLOCK: |
Guennadi Liakhovetski | f985da1 | 2011-12-25 21:07:52 +0100 | [diff] [blame] | 836 | sh_mmcif_multi_read(host, mrq); |
| 837 | return 0; |
Yusuke Goda | fdc50a9 | 2010-05-26 14:41:59 -0700 | [diff] [blame] | 838 | case MMC_WRITE_MULTIPLE_BLOCK: |
Guennadi Liakhovetski | f985da1 | 2011-12-25 21:07:52 +0100 | [diff] [blame] | 839 | sh_mmcif_multi_write(host, mrq); |
| 840 | return 0; |
Yusuke Goda | fdc50a9 | 2010-05-26 14:41:59 -0700 | [diff] [blame] | 841 | case MMC_WRITE_BLOCK: |
Guennadi Liakhovetski | f985da1 | 2011-12-25 21:07:52 +0100 | [diff] [blame] | 842 | sh_mmcif_single_write(host, mrq); |
| 843 | return 0; |
Yusuke Goda | fdc50a9 | 2010-05-26 14:41:59 -0700 | [diff] [blame] | 844 | case MMC_READ_SINGLE_BLOCK: |
| 845 | case MMC_SEND_EXT_CSD: |
Guennadi Liakhovetski | f985da1 | 2011-12-25 21:07:52 +0100 | [diff] [blame] | 846 | sh_mmcif_single_read(host, mrq); |
| 847 | return 0; |
Yusuke Goda | fdc50a9 | 2010-05-26 14:41:59 -0700 | [diff] [blame] | 848 | default: |
Teppei Kamijou | e475b27 | 2012-12-12 15:38:18 +0100 | [diff] [blame] | 849 | dev_err(&host->pd->dev, "Unsupported CMD%d\n", opc); |
Guennadi Liakhovetski | ee4b888 | 2011-12-14 19:31:52 +0100 | [diff] [blame] | 850 | return -EINVAL; |
Yusuke Goda | fdc50a9 | 2010-05-26 14:41:59 -0700 | [diff] [blame] | 851 | } |
Yusuke Goda | fdc50a9 | 2010-05-26 14:41:59 -0700 | [diff] [blame] | 852 | } |
| 853 | |
| 854 | static void sh_mmcif_start_cmd(struct sh_mmcif_host *host, |
Guennadi Liakhovetski | ee4b888 | 2011-12-14 19:31:52 +0100 | [diff] [blame] | 855 | struct mmc_request *mrq) |
Yusuke Goda | fdc50a9 | 2010-05-26 14:41:59 -0700 | [diff] [blame] | 856 | { |
Guennadi Liakhovetski | ee4b888 | 2011-12-14 19:31:52 +0100 | [diff] [blame] | 857 | struct mmc_command *cmd = mrq->cmd; |
Guennadi Liakhovetski | f985da1 | 2011-12-25 21:07:52 +0100 | [diff] [blame] | 858 | u32 opc = cmd->opcode; |
| 859 | u32 mask; |
Yusuke Goda | fdc50a9 | 2010-05-26 14:41:59 -0700 | [diff] [blame] | 860 | |
Yusuke Goda | fdc50a9 | 2010-05-26 14:41:59 -0700 | [diff] [blame] | 861 | switch (opc) { |
Guennadi Liakhovetski | ee4b888 | 2011-12-14 19:31:52 +0100 | [diff] [blame] | 862 | /* response busy check */ |
Teppei Kamijou | a812ba0 | 2012-12-12 15:38:10 +0100 | [diff] [blame] | 863 | case MMC_SLEEP_AWAKE: |
Yusuke Goda | fdc50a9 | 2010-05-26 14:41:59 -0700 | [diff] [blame] | 864 | case MMC_SWITCH: |
| 865 | case MMC_STOP_TRANSMISSION: |
| 866 | case MMC_SET_WRITE_PROT: |
| 867 | case MMC_CLR_WRITE_PROT: |
| 868 | case MMC_ERASE: |
Guennadi Liakhovetski | ee4b888 | 2011-12-14 19:31:52 +0100 | [diff] [blame] | 869 | mask = MASK_START_CMD | MASK_MRBSYE; |
Yusuke Goda | fdc50a9 | 2010-05-26 14:41:59 -0700 | [diff] [blame] | 870 | break; |
| 871 | default: |
Guennadi Liakhovetski | ee4b888 | 2011-12-14 19:31:52 +0100 | [diff] [blame] | 872 | mask = MASK_START_CMD | MASK_MCRSPE; |
Yusuke Goda | fdc50a9 | 2010-05-26 14:41:59 -0700 | [diff] [blame] | 873 | break; |
| 874 | } |
Yusuke Goda | fdc50a9 | 2010-05-26 14:41:59 -0700 | [diff] [blame] | 875 | |
Guennadi Liakhovetski | 6998340 | 2011-12-26 12:52:13 -0500 | [diff] [blame] | 876 | if (mrq->data) { |
Magnus Damm | 487d9fc | 2010-05-18 14:42:51 +0000 | [diff] [blame] | 877 | sh_mmcif_writel(host->addr, MMCIF_CE_BLOCK_SET, 0); |
| 878 | sh_mmcif_writel(host->addr, MMCIF_CE_BLOCK_SET, |
| 879 | mrq->data->blksz); |
Yusuke Goda | fdc50a9 | 2010-05-26 14:41:59 -0700 | [diff] [blame] | 880 | } |
Guennadi Liakhovetski | 6998340 | 2011-12-26 12:52:13 -0500 | [diff] [blame] | 881 | opc = sh_mmcif_set_cmd(host, mrq); |
Yusuke Goda | fdc50a9 | 2010-05-26 14:41:59 -0700 | [diff] [blame] | 882 | |
Magnus Damm | 487d9fc | 2010-05-18 14:42:51 +0000 | [diff] [blame] | 883 | sh_mmcif_writel(host->addr, MMCIF_CE_INT, 0xD80430C0); |
| 884 | sh_mmcif_writel(host->addr, MMCIF_CE_INT_MASK, mask); |
Yusuke Goda | fdc50a9 | 2010-05-26 14:41:59 -0700 | [diff] [blame] | 885 | /* set arg */ |
Magnus Damm | 487d9fc | 2010-05-18 14:42:51 +0000 | [diff] [blame] | 886 | sh_mmcif_writel(host->addr, MMCIF_CE_ARG, cmd->arg); |
Yusuke Goda | fdc50a9 | 2010-05-26 14:41:59 -0700 | [diff] [blame] | 887 | /* set cmd */ |
Magnus Damm | 487d9fc | 2010-05-18 14:42:51 +0000 | [diff] [blame] | 888 | sh_mmcif_writel(host->addr, MMCIF_CE_CMD_SET, opc); |
Yusuke Goda | fdc50a9 | 2010-05-26 14:41:59 -0700 | [diff] [blame] | 889 | |
Guennadi Liakhovetski | f985da1 | 2011-12-25 21:07:52 +0100 | [diff] [blame] | 890 | host->wait_for = MMCIF_WAIT_FOR_CMD; |
| 891 | schedule_delayed_work(&host->timeout_work, host->timeout); |
Yusuke Goda | fdc50a9 | 2010-05-26 14:41:59 -0700 | [diff] [blame] | 892 | } |
| 893 | |
| 894 | static void sh_mmcif_stop_cmd(struct sh_mmcif_host *host, |
Guennadi Liakhovetski | ee4b888 | 2011-12-14 19:31:52 +0100 | [diff] [blame] | 895 | struct mmc_request *mrq) |
Yusuke Goda | fdc50a9 | 2010-05-26 14:41:59 -0700 | [diff] [blame] | 896 | { |
Guennadi Liakhovetski | 6998340 | 2011-12-26 12:52:13 -0500 | [diff] [blame] | 897 | switch (mrq->cmd->opcode) { |
| 898 | case MMC_READ_MULTIPLE_BLOCK: |
Yusuke Goda | fdc50a9 | 2010-05-26 14:41:59 -0700 | [diff] [blame] | 899 | sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MCMD12DRE); |
Guennadi Liakhovetski | 6998340 | 2011-12-26 12:52:13 -0500 | [diff] [blame] | 900 | break; |
| 901 | case MMC_WRITE_MULTIPLE_BLOCK: |
Yusuke Goda | fdc50a9 | 2010-05-26 14:41:59 -0700 | [diff] [blame] | 902 | sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MCMD12RBE); |
Guennadi Liakhovetski | 6998340 | 2011-12-26 12:52:13 -0500 | [diff] [blame] | 903 | break; |
| 904 | default: |
Guennadi Liakhovetski | e47bf32 | 2010-11-24 10:05:18 +0000 | [diff] [blame] | 905 | dev_err(&host->pd->dev, "unsupported stop cmd\n"); |
Guennadi Liakhovetski | 6998340 | 2011-12-26 12:52:13 -0500 | [diff] [blame] | 906 | mrq->stop->error = sh_mmcif_error_manage(host); |
Yusuke Goda | fdc50a9 | 2010-05-26 14:41:59 -0700 | [diff] [blame] | 907 | return; |
| 908 | } |
| 909 | |
Guennadi Liakhovetski | f985da1 | 2011-12-25 21:07:52 +0100 | [diff] [blame] | 910 | host->wait_for = MMCIF_WAIT_FOR_STOP; |
Yusuke Goda | fdc50a9 | 2010-05-26 14:41:59 -0700 | [diff] [blame] | 911 | } |
| 912 | |
| 913 | static void sh_mmcif_request(struct mmc_host *mmc, struct mmc_request *mrq) |
| 914 | { |
| 915 | struct sh_mmcif_host *host = mmc_priv(mmc); |
Guennadi Liakhovetski | 3b0beaf | 2011-04-15 18:30:47 +0000 | [diff] [blame] | 916 | unsigned long flags; |
| 917 | |
| 918 | spin_lock_irqsave(&host->lock, flags); |
| 919 | if (host->state != STATE_IDLE) { |
Teppei Kamijou | e475b27 | 2012-12-12 15:38:18 +0100 | [diff] [blame] | 920 | dev_dbg(&host->pd->dev, "%s() rejected, state %u\n", __func__, host->state); |
Guennadi Liakhovetski | 3b0beaf | 2011-04-15 18:30:47 +0000 | [diff] [blame] | 921 | spin_unlock_irqrestore(&host->lock, flags); |
| 922 | mrq->cmd->error = -EAGAIN; |
| 923 | mmc_request_done(mmc, mrq); |
| 924 | return; |
| 925 | } |
| 926 | |
| 927 | host->state = STATE_REQUEST; |
| 928 | spin_unlock_irqrestore(&host->lock, flags); |
Yusuke Goda | fdc50a9 | 2010-05-26 14:41:59 -0700 | [diff] [blame] | 929 | |
| 930 | switch (mrq->cmd->opcode) { |
| 931 | /* MMCIF does not support SD/SDIO command */ |
Laurent Pinchart | 7541ca9 | 2012-06-12 22:56:09 +0200 | [diff] [blame] | 932 | case MMC_SLEEP_AWAKE: /* = SD_IO_SEND_OP_COND (5) */ |
| 933 | case MMC_SEND_EXT_CSD: /* = SD_SEND_IF_COND (8) */ |
| 934 | if ((mrq->cmd->flags & MMC_CMD_MASK) != MMC_CMD_BCR) |
| 935 | break; |
Yusuke Goda | fdc50a9 | 2010-05-26 14:41:59 -0700 | [diff] [blame] | 936 | case MMC_APP_CMD: |
Teppei Kamijou | 92ff0c5 | 2012-12-12 15:38:05 +0100 | [diff] [blame] | 937 | case SD_IO_RW_DIRECT: |
Guennadi Liakhovetski | 3b0beaf | 2011-04-15 18:30:47 +0000 | [diff] [blame] | 938 | host->state = STATE_IDLE; |
Yusuke Goda | fdc50a9 | 2010-05-26 14:41:59 -0700 | [diff] [blame] | 939 | mrq->cmd->error = -ETIMEDOUT; |
| 940 | mmc_request_done(mmc, mrq); |
| 941 | return; |
Yusuke Goda | fdc50a9 | 2010-05-26 14:41:59 -0700 | [diff] [blame] | 942 | default: |
| 943 | break; |
| 944 | } |
Yusuke Goda | fdc50a9 | 2010-05-26 14:41:59 -0700 | [diff] [blame] | 945 | |
Guennadi Liakhovetski | f985da1 | 2011-12-25 21:07:52 +0100 | [diff] [blame] | 946 | host->mrq = mrq; |
Guennadi Liakhovetski | f985da1 | 2011-12-25 21:07:52 +0100 | [diff] [blame] | 947 | |
| 948 | sh_mmcif_start_cmd(host, mrq); |
Yusuke Goda | fdc50a9 | 2010-05-26 14:41:59 -0700 | [diff] [blame] | 949 | } |
| 950 | |
Guennadi Liakhovetski | a660926 | 2012-04-19 18:02:50 +0200 | [diff] [blame] | 951 | static int sh_mmcif_clk_update(struct sh_mmcif_host *host) |
| 952 | { |
| 953 | int ret = clk_enable(host->hclk); |
| 954 | |
| 955 | if (!ret) { |
| 956 | host->clk = clk_get_rate(host->hclk); |
| 957 | host->mmc->f_max = host->clk / 2; |
| 958 | host->mmc->f_min = host->clk / 512; |
| 959 | } |
| 960 | |
| 961 | return ret; |
| 962 | } |
| 963 | |
Guennadi Liakhovetski | 7d17baa | 2012-04-20 18:27:13 +0200 | [diff] [blame] | 964 | static void sh_mmcif_set_power(struct sh_mmcif_host *host, struct mmc_ios *ios) |
| 965 | { |
Guennadi Liakhovetski | 7d17baa | 2012-04-20 18:27:13 +0200 | [diff] [blame] | 966 | struct mmc_host *mmc = host->mmc; |
| 967 | |
Guennadi Liakhovetski | 7d17baa | 2012-04-20 18:27:13 +0200 | [diff] [blame] | 968 | if (!IS_ERR(mmc->supply.vmmc)) |
| 969 | /* Errors ignored... */ |
| 970 | mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, |
| 971 | ios->power_mode ? ios->vdd : 0); |
| 972 | } |
| 973 | |
Yusuke Goda | fdc50a9 | 2010-05-26 14:41:59 -0700 | [diff] [blame] | 974 | static void sh_mmcif_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) |
| 975 | { |
| 976 | struct sh_mmcif_host *host = mmc_priv(mmc); |
Guennadi Liakhovetski | 3b0beaf | 2011-04-15 18:30:47 +0000 | [diff] [blame] | 977 | unsigned long flags; |
| 978 | |
| 979 | spin_lock_irqsave(&host->lock, flags); |
| 980 | if (host->state != STATE_IDLE) { |
Teppei Kamijou | e475b27 | 2012-12-12 15:38:18 +0100 | [diff] [blame] | 981 | dev_dbg(&host->pd->dev, "%s() rejected, state %u\n", __func__, host->state); |
Guennadi Liakhovetski | 3b0beaf | 2011-04-15 18:30:47 +0000 | [diff] [blame] | 982 | spin_unlock_irqrestore(&host->lock, flags); |
| 983 | return; |
| 984 | } |
| 985 | |
| 986 | host->state = STATE_IOS; |
| 987 | spin_unlock_irqrestore(&host->lock, flags); |
Yusuke Goda | fdc50a9 | 2010-05-26 14:41:59 -0700 | [diff] [blame] | 988 | |
Guennadi Liakhovetski | f5e0cec | 2011-02-25 16:58:38 +0100 | [diff] [blame] | 989 | if (ios->power_mode == MMC_POWER_UP) { |
Guennadi Liakhovetski | c9b0cef | 2011-05-26 15:33:30 +0200 | [diff] [blame] | 990 | if (!host->card_present) { |
Guennadi Liakhovetski | faca664 | 2011-05-05 16:20:48 +0000 | [diff] [blame] | 991 | /* See if we also get DMA */ |
| 992 | sh_mmcif_request_dma(host, host->pd->dev.platform_data); |
Guennadi Liakhovetski | c9b0cef | 2011-05-26 15:33:30 +0200 | [diff] [blame] | 993 | host->card_present = true; |
Guennadi Liakhovetski | faca664 | 2011-05-05 16:20:48 +0000 | [diff] [blame] | 994 | } |
Guennadi Liakhovetski | 7d17baa | 2012-04-20 18:27:13 +0200 | [diff] [blame] | 995 | sh_mmcif_set_power(host, ios); |
Guennadi Liakhovetski | f5e0cec | 2011-02-25 16:58:38 +0100 | [diff] [blame] | 996 | } else if (ios->power_mode == MMC_POWER_OFF || !ios->clock) { |
| 997 | /* clock stop */ |
| 998 | sh_mmcif_clock_control(host, 0); |
Guennadi Liakhovetski | faca664 | 2011-05-05 16:20:48 +0000 | [diff] [blame] | 999 | if (ios->power_mode == MMC_POWER_OFF) { |
Guennadi Liakhovetski | c9b0cef | 2011-05-26 15:33:30 +0200 | [diff] [blame] | 1000 | if (host->card_present) { |
Guennadi Liakhovetski | faca664 | 2011-05-05 16:20:48 +0000 | [diff] [blame] | 1001 | sh_mmcif_release_dma(host); |
Guennadi Liakhovetski | c9b0cef | 2011-05-26 15:33:30 +0200 | [diff] [blame] | 1002 | host->card_present = false; |
Guennadi Liakhovetski | faca664 | 2011-05-05 16:20:48 +0000 | [diff] [blame] | 1003 | } |
Guennadi Liakhovetski | c9b0cef | 2011-05-26 15:33:30 +0200 | [diff] [blame] | 1004 | } |
| 1005 | if (host->power) { |
Teppei Kamijou | f8a8ced | 2012-12-12 15:38:06 +0100 | [diff] [blame] | 1006 | pm_runtime_put_sync(&host->pd->dev); |
Guennadi Liakhovetski | b289174 | 2012-04-19 18:02:05 +0200 | [diff] [blame] | 1007 | clk_disable(host->hclk); |
Guennadi Liakhovetski | c9b0cef | 2011-05-26 15:33:30 +0200 | [diff] [blame] | 1008 | host->power = false; |
Guennadi Liakhovetski | 7d17baa | 2012-04-20 18:27:13 +0200 | [diff] [blame] | 1009 | if (ios->power_mode == MMC_POWER_OFF) |
| 1010 | sh_mmcif_set_power(host, ios); |
Guennadi Liakhovetski | faca664 | 2011-05-05 16:20:48 +0000 | [diff] [blame] | 1011 | } |
Guennadi Liakhovetski | 3b0beaf | 2011-04-15 18:30:47 +0000 | [diff] [blame] | 1012 | host->state = STATE_IDLE; |
Guennadi Liakhovetski | f5e0cec | 2011-02-25 16:58:38 +0100 | [diff] [blame] | 1013 | return; |
Yusuke Goda | fdc50a9 | 2010-05-26 14:41:59 -0700 | [diff] [blame] | 1014 | } |
| 1015 | |
Guennadi Liakhovetski | c9b0cef | 2011-05-26 15:33:30 +0200 | [diff] [blame] | 1016 | if (ios->clock) { |
| 1017 | if (!host->power) { |
Guennadi Liakhovetski | a660926 | 2012-04-19 18:02:50 +0200 | [diff] [blame] | 1018 | sh_mmcif_clk_update(host); |
Guennadi Liakhovetski | c9b0cef | 2011-05-26 15:33:30 +0200 | [diff] [blame] | 1019 | pm_runtime_get_sync(&host->pd->dev); |
| 1020 | host->power = true; |
| 1021 | sh_mmcif_sync_reset(host); |
| 1022 | } |
Yusuke Goda | fdc50a9 | 2010-05-26 14:41:59 -0700 | [diff] [blame] | 1023 | sh_mmcif_clock_control(host, ios->clock); |
Guennadi Liakhovetski | c9b0cef | 2011-05-26 15:33:30 +0200 | [diff] [blame] | 1024 | } |
Yusuke Goda | fdc50a9 | 2010-05-26 14:41:59 -0700 | [diff] [blame] | 1025 | |
Teppei Kamijou | 555061f | 2012-12-12 15:38:08 +0100 | [diff] [blame] | 1026 | host->timing = ios->timing; |
Yusuke Goda | fdc50a9 | 2010-05-26 14:41:59 -0700 | [diff] [blame] | 1027 | host->bus_width = ios->bus_width; |
Guennadi Liakhovetski | 3b0beaf | 2011-04-15 18:30:47 +0000 | [diff] [blame] | 1028 | host->state = STATE_IDLE; |
Yusuke Goda | fdc50a9 | 2010-05-26 14:41:59 -0700 | [diff] [blame] | 1029 | } |
| 1030 | |
Arnd Hannemann | 777271d | 2010-08-24 17:27:01 +0200 | [diff] [blame] | 1031 | static int sh_mmcif_get_cd(struct mmc_host *mmc) |
| 1032 | { |
| 1033 | struct sh_mmcif_host *host = mmc_priv(mmc); |
| 1034 | struct sh_mmcif_plat_data *p = host->pd->dev.platform_data; |
Guennadi Liakhovetski | e480606 | 2012-06-14 14:24:35 +0200 | [diff] [blame] | 1035 | int ret = mmc_gpio_get_cd(mmc); |
| 1036 | |
| 1037 | if (ret >= 0) |
| 1038 | return ret; |
Arnd Hannemann | 777271d | 2010-08-24 17:27:01 +0200 | [diff] [blame] | 1039 | |
Guennadi Liakhovetski | bf68a81 | 2012-05-01 18:18:16 +0200 | [diff] [blame] | 1040 | if (!p || !p->get_cd) |
Arnd Hannemann | 777271d | 2010-08-24 17:27:01 +0200 | [diff] [blame] | 1041 | return -ENOSYS; |
| 1042 | else |
| 1043 | return p->get_cd(host->pd); |
| 1044 | } |
| 1045 | |
Yusuke Goda | fdc50a9 | 2010-05-26 14:41:59 -0700 | [diff] [blame] | 1046 | static struct mmc_host_ops sh_mmcif_ops = { |
| 1047 | .request = sh_mmcif_request, |
| 1048 | .set_ios = sh_mmcif_set_ios, |
Arnd Hannemann | 777271d | 2010-08-24 17:27:01 +0200 | [diff] [blame] | 1049 | .get_cd = sh_mmcif_get_cd, |
Yusuke Goda | fdc50a9 | 2010-05-26 14:41:59 -0700 | [diff] [blame] | 1050 | }; |
| 1051 | |
Guennadi Liakhovetski | f985da1 | 2011-12-25 21:07:52 +0100 | [diff] [blame] | 1052 | static bool sh_mmcif_end_cmd(struct sh_mmcif_host *host) |
| 1053 | { |
| 1054 | struct mmc_command *cmd = host->mrq->cmd; |
Guennadi Liakhovetski | 6998340 | 2011-12-26 12:52:13 -0500 | [diff] [blame] | 1055 | struct mmc_data *data = host->mrq->data; |
Guennadi Liakhovetski | f985da1 | 2011-12-25 21:07:52 +0100 | [diff] [blame] | 1056 | long time; |
| 1057 | |
| 1058 | if (host->sd_error) { |
| 1059 | switch (cmd->opcode) { |
| 1060 | case MMC_ALL_SEND_CID: |
| 1061 | case MMC_SELECT_CARD: |
| 1062 | case MMC_APP_CMD: |
| 1063 | cmd->error = -ETIMEDOUT; |
Guennadi Liakhovetski | f985da1 | 2011-12-25 21:07:52 +0100 | [diff] [blame] | 1064 | break; |
| 1065 | default: |
| 1066 | cmd->error = sh_mmcif_error_manage(host); |
Guennadi Liakhovetski | f985da1 | 2011-12-25 21:07:52 +0100 | [diff] [blame] | 1067 | break; |
| 1068 | } |
Teppei Kamijou | e475b27 | 2012-12-12 15:38:18 +0100 | [diff] [blame] | 1069 | dev_dbg(&host->pd->dev, "CMD%d error %d\n", |
| 1070 | cmd->opcode, cmd->error); |
Guennadi Liakhovetski | aba9d64 | 2012-12-12 15:38:15 +0100 | [diff] [blame] | 1071 | host->sd_error = false; |
Guennadi Liakhovetski | f985da1 | 2011-12-25 21:07:52 +0100 | [diff] [blame] | 1072 | return false; |
| 1073 | } |
| 1074 | if (!(cmd->flags & MMC_RSP_PRESENT)) { |
| 1075 | cmd->error = 0; |
| 1076 | return false; |
| 1077 | } |
| 1078 | |
| 1079 | sh_mmcif_get_response(host, cmd); |
| 1080 | |
Guennadi Liakhovetski | 6998340 | 2011-12-26 12:52:13 -0500 | [diff] [blame] | 1081 | if (!data) |
Guennadi Liakhovetski | f985da1 | 2011-12-25 21:07:52 +0100 | [diff] [blame] | 1082 | return false; |
| 1083 | |
Guennadi Liakhovetski | 90f1cb4 | 2012-12-12 15:38:16 +0100 | [diff] [blame] | 1084 | /* |
| 1085 | * Completion can be signalled from DMA callback and error, so, have to |
| 1086 | * reset here, before setting .dma_active |
| 1087 | */ |
| 1088 | init_completion(&host->dma_complete); |
| 1089 | |
Guennadi Liakhovetski | 6998340 | 2011-12-26 12:52:13 -0500 | [diff] [blame] | 1090 | if (data->flags & MMC_DATA_READ) { |
Guennadi Liakhovetski | f985da1 | 2011-12-25 21:07:52 +0100 | [diff] [blame] | 1091 | if (host->chan_rx) |
| 1092 | sh_mmcif_start_dma_rx(host); |
| 1093 | } else { |
| 1094 | if (host->chan_tx) |
| 1095 | sh_mmcif_start_dma_tx(host); |
| 1096 | } |
| 1097 | |
| 1098 | if (!host->dma_active) { |
Guennadi Liakhovetski | 6998340 | 2011-12-26 12:52:13 -0500 | [diff] [blame] | 1099 | data->error = sh_mmcif_data_trans(host, host->mrq, cmd->opcode); |
Guennadi Liakhovetski | 99eb9d8 | 2012-12-12 15:38:13 +0100 | [diff] [blame] | 1100 | return !data->error; |
Guennadi Liakhovetski | f985da1 | 2011-12-25 21:07:52 +0100 | [diff] [blame] | 1101 | } |
| 1102 | |
| 1103 | /* Running in the IRQ thread, can sleep */ |
| 1104 | time = wait_for_completion_interruptible_timeout(&host->dma_complete, |
| 1105 | host->timeout); |
Teppei Kamijou | eae3098 | 2012-12-12 15:38:12 +0100 | [diff] [blame] | 1106 | |
| 1107 | if (data->flags & MMC_DATA_READ) |
| 1108 | dma_unmap_sg(host->chan_rx->device->dev, |
| 1109 | data->sg, data->sg_len, |
| 1110 | DMA_FROM_DEVICE); |
| 1111 | else |
| 1112 | dma_unmap_sg(host->chan_tx->device->dev, |
| 1113 | data->sg, data->sg_len, |
| 1114 | DMA_TO_DEVICE); |
| 1115 | |
Guennadi Liakhovetski | f985da1 | 2011-12-25 21:07:52 +0100 | [diff] [blame] | 1116 | if (host->sd_error) { |
| 1117 | dev_err(host->mmc->parent, |
| 1118 | "Error IRQ while waiting for DMA completion!\n"); |
| 1119 | /* Woken up by an error IRQ: abort DMA */ |
Guennadi Liakhovetski | 6998340 | 2011-12-26 12:52:13 -0500 | [diff] [blame] | 1120 | data->error = sh_mmcif_error_manage(host); |
Guennadi Liakhovetski | f985da1 | 2011-12-25 21:07:52 +0100 | [diff] [blame] | 1121 | } else if (!time) { |
Teppei Kamijou | e475b27 | 2012-12-12 15:38:18 +0100 | [diff] [blame] | 1122 | dev_err(host->mmc->parent, "DMA timeout!\n"); |
Guennadi Liakhovetski | 6998340 | 2011-12-26 12:52:13 -0500 | [diff] [blame] | 1123 | data->error = -ETIMEDOUT; |
Guennadi Liakhovetski | f985da1 | 2011-12-25 21:07:52 +0100 | [diff] [blame] | 1124 | } else if (time < 0) { |
Teppei Kamijou | e475b27 | 2012-12-12 15:38:18 +0100 | [diff] [blame] | 1125 | dev_err(host->mmc->parent, |
| 1126 | "wait_for_completion_...() error %ld!\n", time); |
Guennadi Liakhovetski | 6998340 | 2011-12-26 12:52:13 -0500 | [diff] [blame] | 1127 | data->error = time; |
Guennadi Liakhovetski | f985da1 | 2011-12-25 21:07:52 +0100 | [diff] [blame] | 1128 | } |
| 1129 | sh_mmcif_bitclr(host, MMCIF_CE_BUF_ACC, |
| 1130 | BUF_ACC_DMAREN | BUF_ACC_DMAWEN); |
| 1131 | host->dma_active = false; |
| 1132 | |
Teppei Kamijou | eae3098 | 2012-12-12 15:38:12 +0100 | [diff] [blame] | 1133 | if (data->error) { |
Guennadi Liakhovetski | 6998340 | 2011-12-26 12:52:13 -0500 | [diff] [blame] | 1134 | data->bytes_xfered = 0; |
Teppei Kamijou | eae3098 | 2012-12-12 15:38:12 +0100 | [diff] [blame] | 1135 | /* Abort DMA */ |
| 1136 | if (data->flags & MMC_DATA_READ) |
| 1137 | dmaengine_terminate_all(host->chan_rx); |
| 1138 | else |
| 1139 | dmaengine_terminate_all(host->chan_tx); |
| 1140 | } |
Guennadi Liakhovetski | f985da1 | 2011-12-25 21:07:52 +0100 | [diff] [blame] | 1141 | |
| 1142 | return false; |
| 1143 | } |
| 1144 | |
| 1145 | static irqreturn_t sh_mmcif_irqt(int irq, void *dev_id) |
| 1146 | { |
| 1147 | struct sh_mmcif_host *host = dev_id; |
Guennadi Liakhovetski | 8047310 | 2012-12-12 15:38:14 +0100 | [diff] [blame] | 1148 | struct mmc_request *mrq; |
Guennadi Liakhovetski | 5df460b | 2012-12-12 15:38:11 +0100 | [diff] [blame] | 1149 | bool wait = false; |
Guennadi Liakhovetski | f985da1 | 2011-12-25 21:07:52 +0100 | [diff] [blame] | 1150 | |
| 1151 | cancel_delayed_work_sync(&host->timeout_work); |
| 1152 | |
Guennadi Liakhovetski | 8047310 | 2012-12-12 15:38:14 +0100 | [diff] [blame] | 1153 | mutex_lock(&host->thread_lock); |
| 1154 | |
| 1155 | mrq = host->mrq; |
| 1156 | if (!mrq) { |
| 1157 | dev_dbg(&host->pd->dev, "IRQ thread state %u, wait %u: NULL mrq!\n", |
| 1158 | host->state, host->wait_for); |
| 1159 | mutex_unlock(&host->thread_lock); |
| 1160 | return IRQ_HANDLED; |
| 1161 | } |
| 1162 | |
Guennadi Liakhovetski | f985da1 | 2011-12-25 21:07:52 +0100 | [diff] [blame] | 1163 | /* |
| 1164 | * All handlers return true, if processing continues, and false, if the |
| 1165 | * request has to be completed - successfully or not |
| 1166 | */ |
| 1167 | switch (host->wait_for) { |
| 1168 | case MMCIF_WAIT_FOR_REQUEST: |
| 1169 | /* We're too late, the timeout has already kicked in */ |
Guennadi Liakhovetski | 8047310 | 2012-12-12 15:38:14 +0100 | [diff] [blame] | 1170 | mutex_unlock(&host->thread_lock); |
Guennadi Liakhovetski | f985da1 | 2011-12-25 21:07:52 +0100 | [diff] [blame] | 1171 | return IRQ_HANDLED; |
| 1172 | case MMCIF_WAIT_FOR_CMD: |
Guennadi Liakhovetski | 5df460b | 2012-12-12 15:38:11 +0100 | [diff] [blame] | 1173 | /* Wait for data? */ |
| 1174 | wait = sh_mmcif_end_cmd(host); |
Guennadi Liakhovetski | f985da1 | 2011-12-25 21:07:52 +0100 | [diff] [blame] | 1175 | break; |
| 1176 | case MMCIF_WAIT_FOR_MREAD: |
Guennadi Liakhovetski | 5df460b | 2012-12-12 15:38:11 +0100 | [diff] [blame] | 1177 | /* Wait for more data? */ |
| 1178 | wait = sh_mmcif_mread_block(host); |
Guennadi Liakhovetski | f985da1 | 2011-12-25 21:07:52 +0100 | [diff] [blame] | 1179 | break; |
| 1180 | case MMCIF_WAIT_FOR_READ: |
Guennadi Liakhovetski | 5df460b | 2012-12-12 15:38:11 +0100 | [diff] [blame] | 1181 | /* Wait for data end? */ |
| 1182 | wait = sh_mmcif_read_block(host); |
Guennadi Liakhovetski | f985da1 | 2011-12-25 21:07:52 +0100 | [diff] [blame] | 1183 | break; |
| 1184 | case MMCIF_WAIT_FOR_MWRITE: |
Guennadi Liakhovetski | 5df460b | 2012-12-12 15:38:11 +0100 | [diff] [blame] | 1185 | /* Wait data to write? */ |
| 1186 | wait = sh_mmcif_mwrite_block(host); |
Guennadi Liakhovetski | f985da1 | 2011-12-25 21:07:52 +0100 | [diff] [blame] | 1187 | break; |
| 1188 | case MMCIF_WAIT_FOR_WRITE: |
Guennadi Liakhovetski | 5df460b | 2012-12-12 15:38:11 +0100 | [diff] [blame] | 1189 | /* Wait for data end? */ |
| 1190 | wait = sh_mmcif_write_block(host); |
Guennadi Liakhovetski | f985da1 | 2011-12-25 21:07:52 +0100 | [diff] [blame] | 1191 | break; |
| 1192 | case MMCIF_WAIT_FOR_STOP: |
| 1193 | if (host->sd_error) { |
| 1194 | mrq->stop->error = sh_mmcif_error_manage(host); |
Teppei Kamijou | e475b27 | 2012-12-12 15:38:18 +0100 | [diff] [blame] | 1195 | dev_dbg(&host->pd->dev, "%s(): %d\n", __func__, mrq->stop->error); |
Guennadi Liakhovetski | f985da1 | 2011-12-25 21:07:52 +0100 | [diff] [blame] | 1196 | break; |
| 1197 | } |
| 1198 | sh_mmcif_get_cmd12response(host, mrq->stop); |
| 1199 | mrq->stop->error = 0; |
| 1200 | break; |
| 1201 | case MMCIF_WAIT_FOR_READ_END: |
| 1202 | case MMCIF_WAIT_FOR_WRITE_END: |
Teppei Kamijou | e475b27 | 2012-12-12 15:38:18 +0100 | [diff] [blame] | 1203 | if (host->sd_error) { |
Guennadi Liakhovetski | 91ab252 | 2012-08-22 06:49:47 +0000 | [diff] [blame] | 1204 | mrq->data->error = sh_mmcif_error_manage(host); |
Teppei Kamijou | e475b27 | 2012-12-12 15:38:18 +0100 | [diff] [blame] | 1205 | dev_dbg(&host->pd->dev, "%s(): %d\n", __func__, mrq->data->error); |
| 1206 | } |
Guennadi Liakhovetski | f985da1 | 2011-12-25 21:07:52 +0100 | [diff] [blame] | 1207 | break; |
| 1208 | default: |
| 1209 | BUG(); |
| 1210 | } |
| 1211 | |
Guennadi Liakhovetski | 5df460b | 2012-12-12 15:38:11 +0100 | [diff] [blame] | 1212 | if (wait) { |
| 1213 | schedule_delayed_work(&host->timeout_work, host->timeout); |
| 1214 | /* Wait for more data */ |
Guennadi Liakhovetski | 8047310 | 2012-12-12 15:38:14 +0100 | [diff] [blame] | 1215 | mutex_unlock(&host->thread_lock); |
Guennadi Liakhovetski | 5df460b | 2012-12-12 15:38:11 +0100 | [diff] [blame] | 1216 | return IRQ_HANDLED; |
| 1217 | } |
| 1218 | |
Guennadi Liakhovetski | f985da1 | 2011-12-25 21:07:52 +0100 | [diff] [blame] | 1219 | if (host->wait_for != MMCIF_WAIT_FOR_STOP) { |
Guennadi Liakhovetski | 91ab252 | 2012-08-22 06:49:47 +0000 | [diff] [blame] | 1220 | struct mmc_data *data = mrq->data; |
Guennadi Liakhovetski | 6998340 | 2011-12-26 12:52:13 -0500 | [diff] [blame] | 1221 | if (!mrq->cmd->error && data && !data->error) |
| 1222 | data->bytes_xfered = |
| 1223 | data->blocks * data->blksz; |
Guennadi Liakhovetski | f985da1 | 2011-12-25 21:07:52 +0100 | [diff] [blame] | 1224 | |
Guennadi Liakhovetski | 6998340 | 2011-12-26 12:52:13 -0500 | [diff] [blame] | 1225 | if (mrq->stop && !mrq->cmd->error && (!data || !data->error)) { |
Guennadi Liakhovetski | f985da1 | 2011-12-25 21:07:52 +0100 | [diff] [blame] | 1226 | sh_mmcif_stop_cmd(host, mrq); |
Guennadi Liakhovetski | 5df460b | 2012-12-12 15:38:11 +0100 | [diff] [blame] | 1227 | if (!mrq->stop->error) { |
| 1228 | schedule_delayed_work(&host->timeout_work, host->timeout); |
Guennadi Liakhovetski | 8047310 | 2012-12-12 15:38:14 +0100 | [diff] [blame] | 1229 | mutex_unlock(&host->thread_lock); |
Guennadi Liakhovetski | f985da1 | 2011-12-25 21:07:52 +0100 | [diff] [blame] | 1230 | return IRQ_HANDLED; |
Guennadi Liakhovetski | 5df460b | 2012-12-12 15:38:11 +0100 | [diff] [blame] | 1231 | } |
Guennadi Liakhovetski | f985da1 | 2011-12-25 21:07:52 +0100 | [diff] [blame] | 1232 | } |
| 1233 | } |
| 1234 | |
| 1235 | host->wait_for = MMCIF_WAIT_FOR_REQUEST; |
| 1236 | host->state = STATE_IDLE; |
Guennadi Liakhovetski | 6998340 | 2011-12-26 12:52:13 -0500 | [diff] [blame] | 1237 | host->mrq = NULL; |
Guennadi Liakhovetski | f985da1 | 2011-12-25 21:07:52 +0100 | [diff] [blame] | 1238 | mmc_request_done(host->mmc, mrq); |
| 1239 | |
Guennadi Liakhovetski | 8047310 | 2012-12-12 15:38:14 +0100 | [diff] [blame] | 1240 | mutex_unlock(&host->thread_lock); |
| 1241 | |
Guennadi Liakhovetski | f985da1 | 2011-12-25 21:07:52 +0100 | [diff] [blame] | 1242 | return IRQ_HANDLED; |
| 1243 | } |
| 1244 | |
Yusuke Goda | fdc50a9 | 2010-05-26 14:41:59 -0700 | [diff] [blame] | 1245 | static irqreturn_t sh_mmcif_intr(int irq, void *dev_id) |
| 1246 | { |
| 1247 | struct sh_mmcif_host *host = dev_id; |
Guennadi Liakhovetski | aa0787a | 2010-11-24 10:05:12 +0000 | [diff] [blame] | 1248 | u32 state; |
Yusuke Goda | fdc50a9 | 2010-05-26 14:41:59 -0700 | [diff] [blame] | 1249 | |
Magnus Damm | 487d9fc | 2010-05-18 14:42:51 +0000 | [diff] [blame] | 1250 | state = sh_mmcif_readl(host->addr, MMCIF_CE_INT); |
Guennadi Liakhovetski | 19f1ba5 | 2013-05-15 07:50:51 +0200 | [diff] [blame] | 1251 | sh_mmcif_writel(host->addr, MMCIF_CE_INT, |
| 1252 | ~(state & sh_mmcif_readl(host->addr, MMCIF_CE_INT_MASK))); |
Guennadi Liakhovetski | 8af5075 | 2012-12-12 15:45:14 +0100 | [diff] [blame] | 1253 | sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, state & MASK_CLEAN); |
Yusuke Goda | fdc50a9 | 2010-05-26 14:41:59 -0700 | [diff] [blame] | 1254 | |
Guennadi Liakhovetski | 8af5075 | 2012-12-12 15:45:14 +0100 | [diff] [blame] | 1255 | if (state & ~MASK_CLEAN) |
| 1256 | dev_dbg(&host->pd->dev, "IRQ state = 0x%08x incompletely cleared\n", |
| 1257 | state); |
| 1258 | |
| 1259 | if (state & INT_ERR_STS || state & ~INT_ALL) { |
Guennadi Liakhovetski | aa0787a | 2010-11-24 10:05:12 +0000 | [diff] [blame] | 1260 | host->sd_error = true; |
Guennadi Liakhovetski | 8af5075 | 2012-12-12 15:45:14 +0100 | [diff] [blame] | 1261 | dev_dbg(&host->pd->dev, "int err state = 0x%08x\n", state); |
Yusuke Goda | fdc50a9 | 2010-05-26 14:41:59 -0700 | [diff] [blame] | 1262 | } |
Guennadi Liakhovetski | f985da1 | 2011-12-25 21:07:52 +0100 | [diff] [blame] | 1263 | if (state & ~(INT_CMD12RBE | INT_CMD12CRE)) { |
Guennadi Liakhovetski | 8af5075 | 2012-12-12 15:45:14 +0100 | [diff] [blame] | 1264 | if (!host->mrq) |
| 1265 | dev_dbg(&host->pd->dev, "NULL IRQ state = 0x%08x\n", state); |
Guennadi Liakhovetski | f985da1 | 2011-12-25 21:07:52 +0100 | [diff] [blame] | 1266 | if (!host->dma_active) |
| 1267 | return IRQ_WAKE_THREAD; |
| 1268 | else if (host->sd_error) |
| 1269 | mmcif_dma_complete(host); |
| 1270 | } else { |
Guennadi Liakhovetski | aa0787a | 2010-11-24 10:05:12 +0000 | [diff] [blame] | 1271 | dev_dbg(&host->pd->dev, "Unexpected IRQ 0x%x\n", state); |
Guennadi Liakhovetski | f985da1 | 2011-12-25 21:07:52 +0100 | [diff] [blame] | 1272 | } |
Yusuke Goda | fdc50a9 | 2010-05-26 14:41:59 -0700 | [diff] [blame] | 1273 | |
| 1274 | return IRQ_HANDLED; |
| 1275 | } |
| 1276 | |
Guennadi Liakhovetski | f985da1 | 2011-12-25 21:07:52 +0100 | [diff] [blame] | 1277 | static void mmcif_timeout_work(struct work_struct *work) |
| 1278 | { |
| 1279 | struct delayed_work *d = container_of(work, struct delayed_work, work); |
| 1280 | struct sh_mmcif_host *host = container_of(d, struct sh_mmcif_host, timeout_work); |
| 1281 | struct mmc_request *mrq = host->mrq; |
Guennadi Liakhovetski | 8047310 | 2012-12-12 15:38:14 +0100 | [diff] [blame] | 1282 | unsigned long flags; |
Guennadi Liakhovetski | f985da1 | 2011-12-25 21:07:52 +0100 | [diff] [blame] | 1283 | |
| 1284 | if (host->dying) |
| 1285 | /* Don't run after mmc_remove_host() */ |
| 1286 | return; |
| 1287 | |
Teppei Kamijou | e475b27 | 2012-12-12 15:38:18 +0100 | [diff] [blame] | 1288 | dev_err(&host->pd->dev, "Timeout waiting for %u on CMD%u\n", |
Guennadi Liakhovetski | 8047310 | 2012-12-12 15:38:14 +0100 | [diff] [blame] | 1289 | host->wait_for, mrq->cmd->opcode); |
| 1290 | |
| 1291 | spin_lock_irqsave(&host->lock, flags); |
| 1292 | if (host->state == STATE_IDLE) { |
| 1293 | spin_unlock_irqrestore(&host->lock, flags); |
| 1294 | return; |
| 1295 | } |
| 1296 | |
| 1297 | host->state = STATE_TIMEOUT; |
| 1298 | spin_unlock_irqrestore(&host->lock, flags); |
| 1299 | |
Guennadi Liakhovetski | f985da1 | 2011-12-25 21:07:52 +0100 | [diff] [blame] | 1300 | /* |
| 1301 | * Handle races with cancel_delayed_work(), unless |
| 1302 | * cancel_delayed_work_sync() is used |
| 1303 | */ |
| 1304 | switch (host->wait_for) { |
| 1305 | case MMCIF_WAIT_FOR_CMD: |
| 1306 | mrq->cmd->error = sh_mmcif_error_manage(host); |
| 1307 | break; |
| 1308 | case MMCIF_WAIT_FOR_STOP: |
| 1309 | mrq->stop->error = sh_mmcif_error_manage(host); |
| 1310 | break; |
| 1311 | case MMCIF_WAIT_FOR_MREAD: |
| 1312 | case MMCIF_WAIT_FOR_MWRITE: |
| 1313 | case MMCIF_WAIT_FOR_READ: |
| 1314 | case MMCIF_WAIT_FOR_WRITE: |
| 1315 | case MMCIF_WAIT_FOR_READ_END: |
| 1316 | case MMCIF_WAIT_FOR_WRITE_END: |
Guennadi Liakhovetski | 6998340 | 2011-12-26 12:52:13 -0500 | [diff] [blame] | 1317 | mrq->data->error = sh_mmcif_error_manage(host); |
Guennadi Liakhovetski | f985da1 | 2011-12-25 21:07:52 +0100 | [diff] [blame] | 1318 | break; |
| 1319 | default: |
| 1320 | BUG(); |
| 1321 | } |
| 1322 | |
| 1323 | host->state = STATE_IDLE; |
| 1324 | host->wait_for = MMCIF_WAIT_FOR_REQUEST; |
Guennadi Liakhovetski | f985da1 | 2011-12-25 21:07:52 +0100 | [diff] [blame] | 1325 | host->mrq = NULL; |
| 1326 | mmc_request_done(host->mmc, mrq); |
| 1327 | } |
| 1328 | |
Guennadi Liakhovetski | 7d17baa | 2012-04-20 18:27:13 +0200 | [diff] [blame] | 1329 | static void sh_mmcif_init_ocr(struct sh_mmcif_host *host) |
| 1330 | { |
| 1331 | struct sh_mmcif_plat_data *pd = host->pd->dev.platform_data; |
| 1332 | struct mmc_host *mmc = host->mmc; |
| 1333 | |
| 1334 | mmc_regulator_get_supply(mmc); |
| 1335 | |
Guennadi Liakhovetski | bf68a81 | 2012-05-01 18:18:16 +0200 | [diff] [blame] | 1336 | if (!pd) |
| 1337 | return; |
| 1338 | |
Guennadi Liakhovetski | 7d17baa | 2012-04-20 18:27:13 +0200 | [diff] [blame] | 1339 | if (!mmc->ocr_avail) |
| 1340 | mmc->ocr_avail = pd->ocr; |
| 1341 | else if (pd->ocr) |
| 1342 | dev_warn(mmc_dev(mmc), "Platform OCR mask is ignored\n"); |
| 1343 | } |
| 1344 | |
Bill Pemberton | c3be1ef | 2012-11-19 13:23:06 -0500 | [diff] [blame] | 1345 | static int sh_mmcif_probe(struct platform_device *pdev) |
Yusuke Goda | fdc50a9 | 2010-05-26 14:41:59 -0700 | [diff] [blame] | 1346 | { |
| 1347 | int ret = 0, irq[2]; |
| 1348 | struct mmc_host *mmc; |
Guennadi Liakhovetski | e47bf32 | 2010-11-24 10:05:18 +0000 | [diff] [blame] | 1349 | struct sh_mmcif_host *host; |
Guennadi Liakhovetski | e1aae2e | 2012-04-19 16:15:52 +0200 | [diff] [blame] | 1350 | struct sh_mmcif_plat_data *pd = pdev->dev.platform_data; |
Yusuke Goda | fdc50a9 | 2010-05-26 14:41:59 -0700 | [diff] [blame] | 1351 | struct resource *res; |
| 1352 | void __iomem *reg; |
Shinya Kuribayashi | 2cd5b3e | 2013-01-14 14:12:36 -0500 | [diff] [blame] | 1353 | const char *name; |
Yusuke Goda | fdc50a9 | 2010-05-26 14:41:59 -0700 | [diff] [blame] | 1354 | |
| 1355 | irq[0] = platform_get_irq(pdev, 0); |
| 1356 | irq[1] = platform_get_irq(pdev, 1); |
Shinya Kuribayashi | 2cd5b3e | 2013-01-14 14:12:36 -0500 | [diff] [blame] | 1357 | if (irq[0] < 0) { |
Guennadi Liakhovetski | e47bf32 | 2010-11-24 10:05:18 +0000 | [diff] [blame] | 1358 | dev_err(&pdev->dev, "Get irq error\n"); |
Yusuke Goda | fdc50a9 | 2010-05-26 14:41:59 -0700 | [diff] [blame] | 1359 | return -ENXIO; |
| 1360 | } |
| 1361 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
| 1362 | if (!res) { |
| 1363 | dev_err(&pdev->dev, "platform_get_resource error.\n"); |
| 1364 | return -ENXIO; |
| 1365 | } |
| 1366 | reg = ioremap(res->start, resource_size(res)); |
| 1367 | if (!reg) { |
| 1368 | dev_err(&pdev->dev, "ioremap error.\n"); |
| 1369 | return -ENOMEM; |
| 1370 | } |
Guennadi Liakhovetski | e1aae2e | 2012-04-19 16:15:52 +0200 | [diff] [blame] | 1371 | |
Yusuke Goda | fdc50a9 | 2010-05-26 14:41:59 -0700 | [diff] [blame] | 1372 | mmc = mmc_alloc_host(sizeof(struct sh_mmcif_host), &pdev->dev); |
| 1373 | if (!mmc) { |
| 1374 | ret = -ENOMEM; |
Guennadi Liakhovetski | e1aae2e | 2012-04-19 16:15:52 +0200 | [diff] [blame] | 1375 | goto ealloch; |
Yusuke Goda | fdc50a9 | 2010-05-26 14:41:59 -0700 | [diff] [blame] | 1376 | } |
Simon Baatz | 2c9054d | 2013-06-09 22:14:12 +0200 | [diff] [blame] | 1377 | |
| 1378 | ret = mmc_of_parse(mmc); |
| 1379 | if (ret < 0) |
| 1380 | goto eofparse; |
| 1381 | |
Yusuke Goda | fdc50a9 | 2010-05-26 14:41:59 -0700 | [diff] [blame] | 1382 | host = mmc_priv(mmc); |
| 1383 | host->mmc = mmc; |
| 1384 | host->addr = reg; |
Teppei Kamijou | f9fd54f | 2012-12-12 15:38:09 +0100 | [diff] [blame] | 1385 | host->timeout = msecs_to_jiffies(1000); |
Yusuke Goda | fdc50a9 | 2010-05-26 14:41:59 -0700 | [diff] [blame] | 1386 | |
Yusuke Goda | fdc50a9 | 2010-05-26 14:41:59 -0700 | [diff] [blame] | 1387 | host->pd = pdev; |
| 1388 | |
Guennadi Liakhovetski | 3b0beaf | 2011-04-15 18:30:47 +0000 | [diff] [blame] | 1389 | spin_lock_init(&host->lock); |
Yusuke Goda | fdc50a9 | 2010-05-26 14:41:59 -0700 | [diff] [blame] | 1390 | |
| 1391 | mmc->ops = &sh_mmcif_ops; |
Guennadi Liakhovetski | 7d17baa | 2012-04-20 18:27:13 +0200 | [diff] [blame] | 1392 | sh_mmcif_init_ocr(host); |
| 1393 | |
Guennadi Liakhovetski | eca889f | 2013-02-15 16:13:54 +0100 | [diff] [blame] | 1394 | mmc->caps |= MMC_CAP_MMC_HIGHSPEED | MMC_CAP_WAIT_WHILE_BUSY; |
Guennadi Liakhovetski | bf68a81 | 2012-05-01 18:18:16 +0200 | [diff] [blame] | 1395 | if (pd && pd->caps) |
Yusuke Goda | fdc50a9 | 2010-05-26 14:41:59 -0700 | [diff] [blame] | 1396 | mmc->caps |= pd->caps; |
Guennadi Liakhovetski | a782d68 | 2010-11-24 10:05:22 +0000 | [diff] [blame] | 1397 | mmc->max_segs = 32; |
Yusuke Goda | fdc50a9 | 2010-05-26 14:41:59 -0700 | [diff] [blame] | 1398 | mmc->max_blk_size = 512; |
Guennadi Liakhovetski | a782d68 | 2010-11-24 10:05:22 +0000 | [diff] [blame] | 1399 | mmc->max_req_size = PAGE_CACHE_SIZE * mmc->max_segs; |
| 1400 | mmc->max_blk_count = mmc->max_req_size / mmc->max_blk_size; |
Yusuke Goda | fdc50a9 | 2010-05-26 14:41:59 -0700 | [diff] [blame] | 1401 | mmc->max_seg_size = mmc->max_req_size; |
| 1402 | |
Yusuke Goda | fdc50a9 | 2010-05-26 14:41:59 -0700 | [diff] [blame] | 1403 | platform_set_drvdata(pdev, host); |
Guennadi Liakhovetski | a782d68 | 2010-11-24 10:05:22 +0000 | [diff] [blame] | 1404 | |
Guennadi Liakhovetski | faca664 | 2011-05-05 16:20:48 +0000 | [diff] [blame] | 1405 | pm_runtime_enable(&pdev->dev); |
| 1406 | host->power = false; |
| 1407 | |
Guennadi Liakhovetski | 047a9ce | 2012-11-28 10:24:27 +0100 | [diff] [blame] | 1408 | host->hclk = clk_get(&pdev->dev, NULL); |
Guennadi Liakhovetski | b289174 | 2012-04-19 18:02:05 +0200 | [diff] [blame] | 1409 | if (IS_ERR(host->hclk)) { |
| 1410 | ret = PTR_ERR(host->hclk); |
Guennadi Liakhovetski | 047a9ce | 2012-11-28 10:24:27 +0100 | [diff] [blame] | 1411 | dev_err(&pdev->dev, "cannot get clock: %d\n", ret); |
Guennadi Liakhovetski | b289174 | 2012-04-19 18:02:05 +0200 | [diff] [blame] | 1412 | goto eclkget; |
| 1413 | } |
Guennadi Liakhovetski | a660926 | 2012-04-19 18:02:50 +0200 | [diff] [blame] | 1414 | ret = sh_mmcif_clk_update(host); |
| 1415 | if (ret < 0) |
| 1416 | goto eclkupdate; |
Guennadi Liakhovetski | b289174 | 2012-04-19 18:02:05 +0200 | [diff] [blame] | 1417 | |
Guennadi Liakhovetski | faca664 | 2011-05-05 16:20:48 +0000 | [diff] [blame] | 1418 | ret = pm_runtime_resume(&pdev->dev); |
| 1419 | if (ret < 0) |
Guennadi Liakhovetski | e1aae2e | 2012-04-19 16:15:52 +0200 | [diff] [blame] | 1420 | goto eresume; |
Guennadi Liakhovetski | a782d68 | 2010-11-24 10:05:22 +0000 | [diff] [blame] | 1421 | |
Guennadi Liakhovetski | 5ba85d9 | 2012-01-21 00:41:28 +0100 | [diff] [blame] | 1422 | INIT_DELAYED_WORK(&host->timeout_work, mmcif_timeout_work); |
Yusuke Goda | fdc50a9 | 2010-05-26 14:41:59 -0700 | [diff] [blame] | 1423 | |
Guennadi Liakhovetski | b289174 | 2012-04-19 18:02:05 +0200 | [diff] [blame] | 1424 | sh_mmcif_sync_reset(host); |
Guennadi Liakhovetski | 3b0beaf | 2011-04-15 18:30:47 +0000 | [diff] [blame] | 1425 | sh_mmcif_writel(host->addr, MMCIF_CE_INT_MASK, MASK_ALL); |
| 1426 | |
Shinya Kuribayashi | 2cd5b3e | 2013-01-14 14:12:36 -0500 | [diff] [blame] | 1427 | name = irq[1] < 0 ? dev_name(&pdev->dev) : "sh_mmc:error"; |
| 1428 | ret = request_threaded_irq(irq[0], sh_mmcif_intr, sh_mmcif_irqt, 0, name, host); |
Yusuke Goda | fdc50a9 | 2010-05-26 14:41:59 -0700 | [diff] [blame] | 1429 | if (ret) { |
Shinya Kuribayashi | 2cd5b3e | 2013-01-14 14:12:36 -0500 | [diff] [blame] | 1430 | dev_err(&pdev->dev, "request_irq error (%s)\n", name); |
Guennadi Liakhovetski | e1aae2e | 2012-04-19 16:15:52 +0200 | [diff] [blame] | 1431 | goto ereqirq0; |
Yusuke Goda | fdc50a9 | 2010-05-26 14:41:59 -0700 | [diff] [blame] | 1432 | } |
Shinya Kuribayashi | 2cd5b3e | 2013-01-14 14:12:36 -0500 | [diff] [blame] | 1433 | if (irq[1] >= 0) { |
| 1434 | ret = request_threaded_irq(irq[1], sh_mmcif_intr, sh_mmcif_irqt, |
| 1435 | 0, "sh_mmc:int", host); |
| 1436 | if (ret) { |
| 1437 | dev_err(&pdev->dev, "request_irq error (sh_mmc:int)\n"); |
| 1438 | goto ereqirq1; |
| 1439 | } |
Yusuke Goda | fdc50a9 | 2010-05-26 14:41:59 -0700 | [diff] [blame] | 1440 | } |
| 1441 | |
Guennadi Liakhovetski | e480606 | 2012-06-14 14:24:35 +0200 | [diff] [blame] | 1442 | if (pd && pd->use_cd_gpio) { |
Laurent Pinchart | 214fc30 | 2013-08-08 12:38:31 +0200 | [diff] [blame] | 1443 | ret = mmc_gpio_request_cd(mmc, pd->cd_gpio, 0); |
Guennadi Liakhovetski | e480606 | 2012-06-14 14:24:35 +0200 | [diff] [blame] | 1444 | if (ret < 0) |
| 1445 | goto erqcd; |
| 1446 | } |
| 1447 | |
Guennadi Liakhovetski | 8047310 | 2012-12-12 15:38:14 +0100 | [diff] [blame] | 1448 | mutex_init(&host->thread_lock); |
| 1449 | |
Guennadi Liakhovetski | b289174 | 2012-04-19 18:02:05 +0200 | [diff] [blame] | 1450 | clk_disable(host->hclk); |
Guennadi Liakhovetski | 5ba85d9 | 2012-01-21 00:41:28 +0100 | [diff] [blame] | 1451 | ret = mmc_add_host(mmc); |
| 1452 | if (ret < 0) |
Guennadi Liakhovetski | e1aae2e | 2012-04-19 16:15:52 +0200 | [diff] [blame] | 1453 | goto emmcaddh; |
Yusuke Goda | fdc50a9 | 2010-05-26 14:41:59 -0700 | [diff] [blame] | 1454 | |
Rafael J. Wysocki | efe6a8a | 2012-03-13 01:02:15 +0100 | [diff] [blame] | 1455 | dev_pm_qos_expose_latency_limit(&pdev->dev, 100); |
| 1456 | |
Guennadi Liakhovetski | e47bf32 | 2010-11-24 10:05:18 +0000 | [diff] [blame] | 1457 | dev_info(&pdev->dev, "driver version %s\n", DRIVER_VERSION); |
| 1458 | dev_dbg(&pdev->dev, "chip ver H'%04x\n", |
Magnus Damm | 487d9fc | 2010-05-18 14:42:51 +0000 | [diff] [blame] | 1459 | sh_mmcif_readl(host->addr, MMCIF_CE_VERSION) & 0x0000ffff); |
Yusuke Goda | fdc50a9 | 2010-05-26 14:41:59 -0700 | [diff] [blame] | 1460 | return ret; |
| 1461 | |
Guennadi Liakhovetski | e1aae2e | 2012-04-19 16:15:52 +0200 | [diff] [blame] | 1462 | emmcaddh: |
Guennadi Liakhovetski | e480606 | 2012-06-14 14:24:35 +0200 | [diff] [blame] | 1463 | erqcd: |
Shinya Kuribayashi | 2cd5b3e | 2013-01-14 14:12:36 -0500 | [diff] [blame] | 1464 | if (irq[1] >= 0) |
| 1465 | free_irq(irq[1], host); |
Guennadi Liakhovetski | e1aae2e | 2012-04-19 16:15:52 +0200 | [diff] [blame] | 1466 | ereqirq1: |
Guennadi Liakhovetski | 5ba85d9 | 2012-01-21 00:41:28 +0100 | [diff] [blame] | 1467 | free_irq(irq[0], host); |
Guennadi Liakhovetski | e1aae2e | 2012-04-19 16:15:52 +0200 | [diff] [blame] | 1468 | ereqirq0: |
Guennadi Liakhovetski | faca664 | 2011-05-05 16:20:48 +0000 | [diff] [blame] | 1469 | pm_runtime_suspend(&pdev->dev); |
Guennadi Liakhovetski | e1aae2e | 2012-04-19 16:15:52 +0200 | [diff] [blame] | 1470 | eresume: |
Yusuke Goda | fdc50a9 | 2010-05-26 14:41:59 -0700 | [diff] [blame] | 1471 | clk_disable(host->hclk); |
Guennadi Liakhovetski | a660926 | 2012-04-19 18:02:50 +0200 | [diff] [blame] | 1472 | eclkupdate: |
Guennadi Liakhovetski | b289174 | 2012-04-19 18:02:05 +0200 | [diff] [blame] | 1473 | clk_put(host->hclk); |
Guennadi Liakhovetski | e1aae2e | 2012-04-19 16:15:52 +0200 | [diff] [blame] | 1474 | eclkget: |
Guennadi Liakhovetski | b289174 | 2012-04-19 18:02:05 +0200 | [diff] [blame] | 1475 | pm_runtime_disable(&pdev->dev); |
Simon Baatz | 2c9054d | 2013-06-09 22:14:12 +0200 | [diff] [blame] | 1476 | eofparse: |
Yusuke Goda | fdc50a9 | 2010-05-26 14:41:59 -0700 | [diff] [blame] | 1477 | mmc_free_host(mmc); |
Guennadi Liakhovetski | e1aae2e | 2012-04-19 16:15:52 +0200 | [diff] [blame] | 1478 | ealloch: |
| 1479 | iounmap(reg); |
Yusuke Goda | fdc50a9 | 2010-05-26 14:41:59 -0700 | [diff] [blame] | 1480 | return ret; |
| 1481 | } |
| 1482 | |
Bill Pemberton | 6e0ee71 | 2012-11-19 13:26:03 -0500 | [diff] [blame] | 1483 | static int sh_mmcif_remove(struct platform_device *pdev) |
Yusuke Goda | fdc50a9 | 2010-05-26 14:41:59 -0700 | [diff] [blame] | 1484 | { |
| 1485 | struct sh_mmcif_host *host = platform_get_drvdata(pdev); |
| 1486 | int irq[2]; |
| 1487 | |
Guennadi Liakhovetski | f985da1 | 2011-12-25 21:07:52 +0100 | [diff] [blame] | 1488 | host->dying = true; |
Guennadi Liakhovetski | b289174 | 2012-04-19 18:02:05 +0200 | [diff] [blame] | 1489 | clk_enable(host->hclk); |
Guennadi Liakhovetski | faca664 | 2011-05-05 16:20:48 +0000 | [diff] [blame] | 1490 | pm_runtime_get_sync(&pdev->dev); |
Guennadi Liakhovetski | aa0787a | 2010-11-24 10:05:12 +0000 | [diff] [blame] | 1491 | |
Rafael J. Wysocki | efe6a8a | 2012-03-13 01:02:15 +0100 | [diff] [blame] | 1492 | dev_pm_qos_hide_latency_limit(&pdev->dev); |
| 1493 | |
Guennadi Liakhovetski | faca664 | 2011-05-05 16:20:48 +0000 | [diff] [blame] | 1494 | mmc_remove_host(host->mmc); |
Guennadi Liakhovetski | 3b0beaf | 2011-04-15 18:30:47 +0000 | [diff] [blame] | 1495 | sh_mmcif_writel(host->addr, MMCIF_CE_INT_MASK, MASK_ALL); |
| 1496 | |
Guennadi Liakhovetski | f985da1 | 2011-12-25 21:07:52 +0100 | [diff] [blame] | 1497 | /* |
| 1498 | * FIXME: cancel_delayed_work(_sync)() and free_irq() race with the |
| 1499 | * mmc_remove_host() call above. But swapping order doesn't help either |
| 1500 | * (a query on the linux-mmc mailing list didn't bring any replies). |
| 1501 | */ |
| 1502 | cancel_delayed_work_sync(&host->timeout_work); |
| 1503 | |
Guennadi Liakhovetski | aa0787a | 2010-11-24 10:05:12 +0000 | [diff] [blame] | 1504 | if (host->addr) |
| 1505 | iounmap(host->addr); |
| 1506 | |
Yusuke Goda | fdc50a9 | 2010-05-26 14:41:59 -0700 | [diff] [blame] | 1507 | irq[0] = platform_get_irq(pdev, 0); |
| 1508 | irq[1] = platform_get_irq(pdev, 1); |
| 1509 | |
Yusuke Goda | fdc50a9 | 2010-05-26 14:41:59 -0700 | [diff] [blame] | 1510 | free_irq(irq[0], host); |
Shinya Kuribayashi | 2cd5b3e | 2013-01-14 14:12:36 -0500 | [diff] [blame] | 1511 | if (irq[1] >= 0) |
| 1512 | free_irq(irq[1], host); |
Yusuke Goda | fdc50a9 | 2010-05-26 14:41:59 -0700 | [diff] [blame] | 1513 | |
Guennadi Liakhovetski | a0d28ba | 2012-10-23 14:08:52 +0200 | [diff] [blame] | 1514 | clk_disable(host->hclk); |
Yusuke Goda | fdc50a9 | 2010-05-26 14:41:59 -0700 | [diff] [blame] | 1515 | mmc_free_host(host->mmc); |
Guennadi Liakhovetski | faca664 | 2011-05-05 16:20:48 +0000 | [diff] [blame] | 1516 | pm_runtime_put_sync(&pdev->dev); |
| 1517 | pm_runtime_disable(&pdev->dev); |
Yusuke Goda | fdc50a9 | 2010-05-26 14:41:59 -0700 | [diff] [blame] | 1518 | |
| 1519 | return 0; |
| 1520 | } |
| 1521 | |
Guennadi Liakhovetski | faca664 | 2011-05-05 16:20:48 +0000 | [diff] [blame] | 1522 | #ifdef CONFIG_PM |
| 1523 | static int sh_mmcif_suspend(struct device *dev) |
| 1524 | { |
Guennadi Liakhovetski | b289174 | 2012-04-19 18:02:05 +0200 | [diff] [blame] | 1525 | struct sh_mmcif_host *host = dev_get_drvdata(dev); |
Guennadi Liakhovetski | faca664 | 2011-05-05 16:20:48 +0000 | [diff] [blame] | 1526 | int ret = mmc_suspend_host(host->mmc); |
| 1527 | |
Guennadi Liakhovetski | b289174 | 2012-04-19 18:02:05 +0200 | [diff] [blame] | 1528 | if (!ret) |
Guennadi Liakhovetski | faca664 | 2011-05-05 16:20:48 +0000 | [diff] [blame] | 1529 | sh_mmcif_writel(host->addr, MMCIF_CE_INT_MASK, MASK_ALL); |
Guennadi Liakhovetski | faca664 | 2011-05-05 16:20:48 +0000 | [diff] [blame] | 1530 | |
| 1531 | return ret; |
| 1532 | } |
| 1533 | |
| 1534 | static int sh_mmcif_resume(struct device *dev) |
| 1535 | { |
Guennadi Liakhovetski | b289174 | 2012-04-19 18:02:05 +0200 | [diff] [blame] | 1536 | struct sh_mmcif_host *host = dev_get_drvdata(dev); |
Guennadi Liakhovetski | faca664 | 2011-05-05 16:20:48 +0000 | [diff] [blame] | 1537 | |
| 1538 | return mmc_resume_host(host->mmc); |
| 1539 | } |
| 1540 | #else |
| 1541 | #define sh_mmcif_suspend NULL |
| 1542 | #define sh_mmcif_resume NULL |
| 1543 | #endif /* CONFIG_PM */ |
| 1544 | |
Guennadi Liakhovetski | bf68a81 | 2012-05-01 18:18:16 +0200 | [diff] [blame] | 1545 | static const struct of_device_id mmcif_of_match[] = { |
| 1546 | { .compatible = "renesas,sh-mmcif" }, |
| 1547 | { } |
| 1548 | }; |
| 1549 | MODULE_DEVICE_TABLE(of, mmcif_of_match); |
| 1550 | |
Guennadi Liakhovetski | faca664 | 2011-05-05 16:20:48 +0000 | [diff] [blame] | 1551 | static const struct dev_pm_ops sh_mmcif_dev_pm_ops = { |
| 1552 | .suspend = sh_mmcif_suspend, |
| 1553 | .resume = sh_mmcif_resume, |
| 1554 | }; |
| 1555 | |
Yusuke Goda | fdc50a9 | 2010-05-26 14:41:59 -0700 | [diff] [blame] | 1556 | static struct platform_driver sh_mmcif_driver = { |
| 1557 | .probe = sh_mmcif_probe, |
| 1558 | .remove = sh_mmcif_remove, |
| 1559 | .driver = { |
| 1560 | .name = DRIVER_NAME, |
Guennadi Liakhovetski | faca664 | 2011-05-05 16:20:48 +0000 | [diff] [blame] | 1561 | .pm = &sh_mmcif_dev_pm_ops, |
Guennadi Liakhovetski | bf68a81 | 2012-05-01 18:18:16 +0200 | [diff] [blame] | 1562 | .owner = THIS_MODULE, |
| 1563 | .of_match_table = mmcif_of_match, |
Yusuke Goda | fdc50a9 | 2010-05-26 14:41:59 -0700 | [diff] [blame] | 1564 | }, |
| 1565 | }; |
| 1566 | |
Axel Lin | d1f81a6 | 2011-11-26 12:55:43 +0800 | [diff] [blame] | 1567 | module_platform_driver(sh_mmcif_driver); |
Yusuke Goda | fdc50a9 | 2010-05-26 14:41:59 -0700 | [diff] [blame] | 1568 | |
| 1569 | MODULE_DESCRIPTION("SuperH on-chip MMC/eMMC interface driver"); |
| 1570 | MODULE_LICENSE("GPL"); |
Guennadi Liakhovetski | aa0787a | 2010-11-24 10:05:12 +0000 | [diff] [blame] | 1571 | MODULE_ALIAS("platform:" DRIVER_NAME); |
Yusuke Goda | fdc50a9 | 2010-05-26 14:41:59 -0700 | [diff] [blame] | 1572 | MODULE_AUTHOR("Yusuke Goda <yusuke.goda.sx@renesas.com>"); |