Baruch Siach | 1ab52cf | 2009-06-22 16:36:29 +0300 | [diff] [blame] | 1 | /* |
Shinya Kuribayashi | a0e06ea | 2009-11-06 21:52:22 +0900 | [diff] [blame] | 2 | * Synopsys DesignWare I2C adapter driver (master only). |
Baruch Siach | 1ab52cf | 2009-06-22 16:36:29 +0300 | [diff] [blame] | 3 | * |
| 4 | * Based on the TI DAVINCI I2C adapter driver. |
| 5 | * |
| 6 | * Copyright (C) 2006 Texas Instruments. |
| 7 | * Copyright (C) 2007 MontaVista Software Inc. |
| 8 | * Copyright (C) 2009 Provigent Ltd. |
| 9 | * |
| 10 | * ---------------------------------------------------------------------------- |
| 11 | * |
| 12 | * This program is free software; you can redistribute it and/or modify |
| 13 | * it under the terms of the GNU General Public License as published by |
| 14 | * the Free Software Foundation; either version 2 of the License, or |
| 15 | * (at your option) any later version. |
| 16 | * |
| 17 | * This program is distributed in the hope that it will be useful, |
| 18 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 19 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 20 | * GNU General Public License for more details. |
| 21 | * |
| 22 | * You should have received a copy of the GNU General Public License |
| 23 | * along with this program; if not, write to the Free Software |
| 24 | * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. |
| 25 | * ---------------------------------------------------------------------------- |
| 26 | * |
| 27 | */ |
Baruch Siach | 1ab52cf | 2009-06-22 16:36:29 +0300 | [diff] [blame] | 28 | #include <linux/clk.h> |
| 29 | #include <linux/errno.h> |
Baruch Siach | 1ab52cf | 2009-06-22 16:36:29 +0300 | [diff] [blame] | 30 | #include <linux/err.h> |
Dirk Brandewie | 2373f6b | 2011-10-29 10:57:23 +0100 | [diff] [blame] | 31 | #include <linux/i2c.h> |
Baruch Siach | 1ab52cf | 2009-06-22 16:36:29 +0300 | [diff] [blame] | 32 | #include <linux/interrupt.h> |
Baruch Siach | 1ab52cf | 2009-06-22 16:36:29 +0300 | [diff] [blame] | 33 | #include <linux/io.h> |
Dirk Brandewie | 2373f6b | 2011-10-29 10:57:23 +0100 | [diff] [blame] | 34 | #include <linux/delay.h> |
| 35 | #include "i2c-designware-core.h" |
Shinya Kuribayashi | ce6eb57 | 2009-11-06 21:51:57 +0900 | [diff] [blame] | 36 | |
Baruch Siach | 1ab52cf | 2009-06-22 16:36:29 +0300 | [diff] [blame] | 37 | static char *abort_sources[] = { |
Shinya Kuribayashi | a0e06ea | 2009-11-06 21:52:22 +0900 | [diff] [blame] | 38 | [ABRT_7B_ADDR_NOACK] = |
Baruch Siach | 1ab52cf | 2009-06-22 16:36:29 +0300 | [diff] [blame] | 39 | "slave address not acknowledged (7bit mode)", |
Shinya Kuribayashi | a0e06ea | 2009-11-06 21:52:22 +0900 | [diff] [blame] | 40 | [ABRT_10ADDR1_NOACK] = |
Baruch Siach | 1ab52cf | 2009-06-22 16:36:29 +0300 | [diff] [blame] | 41 | "first address byte not acknowledged (10bit mode)", |
Shinya Kuribayashi | a0e06ea | 2009-11-06 21:52:22 +0900 | [diff] [blame] | 42 | [ABRT_10ADDR2_NOACK] = |
Baruch Siach | 1ab52cf | 2009-06-22 16:36:29 +0300 | [diff] [blame] | 43 | "second address byte not acknowledged (10bit mode)", |
Shinya Kuribayashi | a0e06ea | 2009-11-06 21:52:22 +0900 | [diff] [blame] | 44 | [ABRT_TXDATA_NOACK] = |
Baruch Siach | 1ab52cf | 2009-06-22 16:36:29 +0300 | [diff] [blame] | 45 | "data not acknowledged", |
Shinya Kuribayashi | a0e06ea | 2009-11-06 21:52:22 +0900 | [diff] [blame] | 46 | [ABRT_GCALL_NOACK] = |
Baruch Siach | 1ab52cf | 2009-06-22 16:36:29 +0300 | [diff] [blame] | 47 | "no acknowledgement for a general call", |
Shinya Kuribayashi | a0e06ea | 2009-11-06 21:52:22 +0900 | [diff] [blame] | 48 | [ABRT_GCALL_READ] = |
Baruch Siach | 1ab52cf | 2009-06-22 16:36:29 +0300 | [diff] [blame] | 49 | "read after general call", |
Shinya Kuribayashi | a0e06ea | 2009-11-06 21:52:22 +0900 | [diff] [blame] | 50 | [ABRT_SBYTE_ACKDET] = |
Baruch Siach | 1ab52cf | 2009-06-22 16:36:29 +0300 | [diff] [blame] | 51 | "start byte acknowledged", |
Shinya Kuribayashi | a0e06ea | 2009-11-06 21:52:22 +0900 | [diff] [blame] | 52 | [ABRT_SBYTE_NORSTRT] = |
Baruch Siach | 1ab52cf | 2009-06-22 16:36:29 +0300 | [diff] [blame] | 53 | "trying to send start byte when restart is disabled", |
Shinya Kuribayashi | a0e06ea | 2009-11-06 21:52:22 +0900 | [diff] [blame] | 54 | [ABRT_10B_RD_NORSTRT] = |
Baruch Siach | 1ab52cf | 2009-06-22 16:36:29 +0300 | [diff] [blame] | 55 | "trying to read when restart is disabled (10bit mode)", |
Shinya Kuribayashi | a0e06ea | 2009-11-06 21:52:22 +0900 | [diff] [blame] | 56 | [ABRT_MASTER_DIS] = |
Baruch Siach | 1ab52cf | 2009-06-22 16:36:29 +0300 | [diff] [blame] | 57 | "trying to use disabled adapter", |
Shinya Kuribayashi | a0e06ea | 2009-11-06 21:52:22 +0900 | [diff] [blame] | 58 | [ARB_LOST] = |
Baruch Siach | 1ab52cf | 2009-06-22 16:36:29 +0300 | [diff] [blame] | 59 | "lost arbitration", |
| 60 | }; |
| 61 | |
Dirk Brandewie | 2373f6b | 2011-10-29 10:57:23 +0100 | [diff] [blame] | 62 | u32 dw_readl(struct dw_i2c_dev *dev, int offset) |
Jean-Hugues Deschenes | 7f27960 | 2011-10-06 11:26:25 -0700 | [diff] [blame] | 63 | { |
Jean-Hugues Deschenes | 18c4089 | 2011-10-06 11:26:27 -0700 | [diff] [blame] | 64 | u32 value = readl(dev->base + offset); |
| 65 | |
| 66 | if (dev->swab) |
| 67 | return swab32(value); |
| 68 | else |
| 69 | return value; |
Jean-Hugues Deschenes | 7f27960 | 2011-10-06 11:26:25 -0700 | [diff] [blame] | 70 | } |
| 71 | |
Dirk Brandewie | 2373f6b | 2011-10-29 10:57:23 +0100 | [diff] [blame] | 72 | void dw_writel(struct dw_i2c_dev *dev, u32 b, int offset) |
Jean-Hugues Deschenes | 7f27960 | 2011-10-06 11:26:25 -0700 | [diff] [blame] | 73 | { |
Jean-Hugues Deschenes | 18c4089 | 2011-10-06 11:26:27 -0700 | [diff] [blame] | 74 | if (dev->swab) |
| 75 | b = swab32(b); |
| 76 | |
Jean-Hugues Deschenes | 7f27960 | 2011-10-06 11:26:25 -0700 | [diff] [blame] | 77 | writel(b, dev->base + offset); |
| 78 | } |
| 79 | |
Shinya Kuribayashi | d60c7e8 | 2009-11-06 21:47:01 +0900 | [diff] [blame] | 80 | static u32 |
| 81 | i2c_dw_scl_hcnt(u32 ic_clk, u32 tSYMBOL, u32 tf, int cond, int offset) |
| 82 | { |
| 83 | /* |
| 84 | * DesignWare I2C core doesn't seem to have solid strategy to meet |
| 85 | * the tHD;STA timing spec. Configuring _HCNT based on tHIGH spec |
| 86 | * will result in violation of the tHD;STA spec. |
| 87 | */ |
| 88 | if (cond) |
| 89 | /* |
| 90 | * Conditional expression: |
| 91 | * |
| 92 | * IC_[FS]S_SCL_HCNT + (1+4+3) >= IC_CLK * tHIGH |
| 93 | * |
| 94 | * This is based on the DW manuals, and represents an ideal |
| 95 | * configuration. The resulting I2C bus speed will be |
| 96 | * faster than any of the others. |
| 97 | * |
| 98 | * If your hardware is free from tHD;STA issue, try this one. |
| 99 | */ |
| 100 | return (ic_clk * tSYMBOL + 5000) / 10000 - 8 + offset; |
| 101 | else |
| 102 | /* |
| 103 | * Conditional expression: |
| 104 | * |
| 105 | * IC_[FS]S_SCL_HCNT + 3 >= IC_CLK * (tHD;STA + tf) |
| 106 | * |
| 107 | * This is just experimental rule; the tHD;STA period turned |
| 108 | * out to be proportinal to (_HCNT + 3). With this setting, |
| 109 | * we could meet both tHIGH and tHD;STA timing specs. |
| 110 | * |
| 111 | * If unsure, you'd better to take this alternative. |
| 112 | * |
| 113 | * The reason why we need to take into account "tf" here, |
| 114 | * is the same as described in i2c_dw_scl_lcnt(). |
| 115 | */ |
| 116 | return (ic_clk * (tSYMBOL + tf) + 5000) / 10000 - 3 + offset; |
| 117 | } |
| 118 | |
| 119 | static u32 i2c_dw_scl_lcnt(u32 ic_clk, u32 tLOW, u32 tf, int offset) |
| 120 | { |
| 121 | /* |
| 122 | * Conditional expression: |
| 123 | * |
| 124 | * IC_[FS]S_SCL_LCNT + 1 >= IC_CLK * (tLOW + tf) |
| 125 | * |
| 126 | * DW I2C core starts counting the SCL CNTs for the LOW period |
| 127 | * of the SCL clock (tLOW) as soon as it pulls the SCL line. |
| 128 | * In order to meet the tLOW timing spec, we need to take into |
| 129 | * account the fall time of SCL signal (tf). Default tf value |
| 130 | * should be 0.3 us, for safety. |
| 131 | */ |
| 132 | return ((ic_clk * (tLOW + tf) + 5000) / 10000) - 1 + offset; |
| 133 | } |
| 134 | |
Baruch Siach | 1ab52cf | 2009-06-22 16:36:29 +0300 | [diff] [blame] | 135 | /** |
| 136 | * i2c_dw_init() - initialize the designware i2c master hardware |
| 137 | * @dev: device private data |
| 138 | * |
| 139 | * This functions configures and enables the I2C master. |
| 140 | * This function is called during I2C init function, and in case of timeout at |
| 141 | * run time. |
| 142 | */ |
Dirk Brandewie | 2373f6b | 2011-10-29 10:57:23 +0100 | [diff] [blame] | 143 | int i2c_dw_init(struct dw_i2c_dev *dev) |
Baruch Siach | 1ab52cf | 2009-06-22 16:36:29 +0300 | [diff] [blame] | 144 | { |
Dirk Brandewie | 1d31b58 | 2011-10-06 11:26:30 -0700 | [diff] [blame] | 145 | u32 input_clock_khz; |
Dirk Brandewie | e18563f | 2011-10-06 11:26:32 -0700 | [diff] [blame] | 146 | u32 hcnt, lcnt; |
Dirk Brandewie | 4a423a8 | 2011-10-06 11:26:28 -0700 | [diff] [blame] | 147 | u32 reg; |
| 148 | |
Dirk Brandewie | 1d31b58 | 2011-10-06 11:26:30 -0700 | [diff] [blame] | 149 | input_clock_khz = dev->get_clk_rate_khz(dev); |
| 150 | |
Dirk Brandewie | 4a423a8 | 2011-10-06 11:26:28 -0700 | [diff] [blame] | 151 | /* Configure register endianess access */ |
| 152 | reg = dw_readl(dev, DW_IC_COMP_TYPE); |
| 153 | if (reg == ___constant_swab32(DW_IC_COMP_TYPE_VALUE)) { |
| 154 | dev->swab = 1; |
| 155 | reg = DW_IC_COMP_TYPE_VALUE; |
| 156 | } |
| 157 | |
| 158 | if (reg != DW_IC_COMP_TYPE_VALUE) { |
| 159 | dev_err(dev->dev, "Unknown Synopsys component type: " |
| 160 | "0x%08x\n", reg); |
| 161 | return -ENODEV; |
| 162 | } |
Baruch Siach | 1ab52cf | 2009-06-22 16:36:29 +0300 | [diff] [blame] | 163 | |
| 164 | /* Disable the adapter */ |
Jean-Hugues Deschenes | 7f27960 | 2011-10-06 11:26:25 -0700 | [diff] [blame] | 165 | dw_writel(dev, 0, DW_IC_ENABLE); |
Baruch Siach | 1ab52cf | 2009-06-22 16:36:29 +0300 | [diff] [blame] | 166 | |
| 167 | /* set standard and fast speed deviders for high/low periods */ |
Shinya Kuribayashi | d60c7e8 | 2009-11-06 21:47:01 +0900 | [diff] [blame] | 168 | |
| 169 | /* Standard-mode */ |
| 170 | hcnt = i2c_dw_scl_hcnt(input_clock_khz, |
| 171 | 40, /* tHD;STA = tHIGH = 4.0 us */ |
| 172 | 3, /* tf = 0.3 us */ |
| 173 | 0, /* 0: DW default, 1: Ideal */ |
| 174 | 0); /* No offset */ |
| 175 | lcnt = i2c_dw_scl_lcnt(input_clock_khz, |
| 176 | 47, /* tLOW = 4.7 us */ |
| 177 | 3, /* tf = 0.3 us */ |
| 178 | 0); /* No offset */ |
Jean-Hugues Deschenes | 7f27960 | 2011-10-06 11:26:25 -0700 | [diff] [blame] | 179 | dw_writel(dev, hcnt, DW_IC_SS_SCL_HCNT); |
| 180 | dw_writel(dev, lcnt, DW_IC_SS_SCL_LCNT); |
Shinya Kuribayashi | d60c7e8 | 2009-11-06 21:47:01 +0900 | [diff] [blame] | 181 | dev_dbg(dev->dev, "Standard-mode HCNT:LCNT = %d:%d\n", hcnt, lcnt); |
| 182 | |
| 183 | /* Fast-mode */ |
| 184 | hcnt = i2c_dw_scl_hcnt(input_clock_khz, |
| 185 | 6, /* tHD;STA = tHIGH = 0.6 us */ |
| 186 | 3, /* tf = 0.3 us */ |
| 187 | 0, /* 0: DW default, 1: Ideal */ |
| 188 | 0); /* No offset */ |
| 189 | lcnt = i2c_dw_scl_lcnt(input_clock_khz, |
| 190 | 13, /* tLOW = 1.3 us */ |
| 191 | 3, /* tf = 0.3 us */ |
| 192 | 0); /* No offset */ |
Jean-Hugues Deschenes | 7f27960 | 2011-10-06 11:26:25 -0700 | [diff] [blame] | 193 | dw_writel(dev, hcnt, DW_IC_FS_SCL_HCNT); |
| 194 | dw_writel(dev, lcnt, DW_IC_FS_SCL_LCNT); |
Shinya Kuribayashi | d60c7e8 | 2009-11-06 21:47:01 +0900 | [diff] [blame] | 195 | dev_dbg(dev->dev, "Fast-mode HCNT:LCNT = %d:%d\n", hcnt, lcnt); |
Baruch Siach | 1ab52cf | 2009-06-22 16:36:29 +0300 | [diff] [blame] | 196 | |
Shinya Kuribayashi | 4cb6d1d | 2009-11-06 21:48:12 +0900 | [diff] [blame] | 197 | /* Configure Tx/Rx FIFO threshold levels */ |
Jean-Hugues Deschenes | 7f27960 | 2011-10-06 11:26:25 -0700 | [diff] [blame] | 198 | dw_writel(dev, dev->tx_fifo_depth - 1, DW_IC_TX_TL); |
| 199 | dw_writel(dev, 0, DW_IC_RX_TL); |
Shinya Kuribayashi | 4cb6d1d | 2009-11-06 21:48:12 +0900 | [diff] [blame] | 200 | |
Baruch Siach | 1ab52cf | 2009-06-22 16:36:29 +0300 | [diff] [blame] | 201 | /* configure the i2c master */ |
Dirk Brandewie | e18563f | 2011-10-06 11:26:32 -0700 | [diff] [blame] | 202 | dw_writel(dev, dev->master_cfg , DW_IC_CON); |
Dirk Brandewie | 4a423a8 | 2011-10-06 11:26:28 -0700 | [diff] [blame] | 203 | return 0; |
Baruch Siach | 1ab52cf | 2009-06-22 16:36:29 +0300 | [diff] [blame] | 204 | } |
| 205 | |
| 206 | /* |
| 207 | * Waiting for bus not busy |
| 208 | */ |
| 209 | static int i2c_dw_wait_bus_not_busy(struct dw_i2c_dev *dev) |
| 210 | { |
| 211 | int timeout = TIMEOUT; |
| 212 | |
Jean-Hugues Deschenes | 7f27960 | 2011-10-06 11:26:25 -0700 | [diff] [blame] | 213 | while (dw_readl(dev, DW_IC_STATUS) & DW_IC_STATUS_ACTIVITY) { |
Baruch Siach | 1ab52cf | 2009-06-22 16:36:29 +0300 | [diff] [blame] | 214 | if (timeout <= 0) { |
| 215 | dev_warn(dev->dev, "timeout waiting for bus ready\n"); |
| 216 | return -ETIMEDOUT; |
| 217 | } |
| 218 | timeout--; |
| 219 | mdelay(1); |
| 220 | } |
| 221 | |
| 222 | return 0; |
| 223 | } |
| 224 | |
Shinya Kuribayashi | 81e798b | 2009-11-06 21:48:55 +0900 | [diff] [blame] | 225 | static void i2c_dw_xfer_init(struct dw_i2c_dev *dev) |
| 226 | { |
| 227 | struct i2c_msg *msgs = dev->msgs; |
| 228 | u32 ic_con; |
| 229 | |
| 230 | /* Disable the adapter */ |
Jean-Hugues Deschenes | 7f27960 | 2011-10-06 11:26:25 -0700 | [diff] [blame] | 231 | dw_writel(dev, 0, DW_IC_ENABLE); |
Shinya Kuribayashi | 81e798b | 2009-11-06 21:48:55 +0900 | [diff] [blame] | 232 | |
| 233 | /* set the slave (target) address */ |
Jean-Hugues Deschenes | 7f27960 | 2011-10-06 11:26:25 -0700 | [diff] [blame] | 234 | dw_writel(dev, msgs[dev->msg_write_idx].addr, DW_IC_TAR); |
Shinya Kuribayashi | 81e798b | 2009-11-06 21:48:55 +0900 | [diff] [blame] | 235 | |
| 236 | /* if the slave address is ten bit address, enable 10BITADDR */ |
Jean-Hugues Deschenes | 7f27960 | 2011-10-06 11:26:25 -0700 | [diff] [blame] | 237 | ic_con = dw_readl(dev, DW_IC_CON); |
Shinya Kuribayashi | 81e798b | 2009-11-06 21:48:55 +0900 | [diff] [blame] | 238 | if (msgs[dev->msg_write_idx].flags & I2C_M_TEN) |
| 239 | ic_con |= DW_IC_CON_10BITADDR_MASTER; |
| 240 | else |
| 241 | ic_con &= ~DW_IC_CON_10BITADDR_MASTER; |
Jean-Hugues Deschenes | 7f27960 | 2011-10-06 11:26:25 -0700 | [diff] [blame] | 242 | dw_writel(dev, ic_con, DW_IC_CON); |
Shinya Kuribayashi | 81e798b | 2009-11-06 21:48:55 +0900 | [diff] [blame] | 243 | |
| 244 | /* Enable the adapter */ |
Jean-Hugues Deschenes | 7f27960 | 2011-10-06 11:26:25 -0700 | [diff] [blame] | 245 | dw_writel(dev, 1, DW_IC_ENABLE); |
Shinya Kuribayashi | 201d6a7 | 2009-11-06 21:50:40 +0900 | [diff] [blame] | 246 | |
| 247 | /* Enable interrupts */ |
Jean-Hugues Deschenes | 7f27960 | 2011-10-06 11:26:25 -0700 | [diff] [blame] | 248 | dw_writel(dev, DW_IC_INTR_DEFAULT_MASK, DW_IC_INTR_MASK); |
Shinya Kuribayashi | 81e798b | 2009-11-06 21:48:55 +0900 | [diff] [blame] | 249 | } |
| 250 | |
Baruch Siach | 1ab52cf | 2009-06-22 16:36:29 +0300 | [diff] [blame] | 251 | /* |
Shinya Kuribayashi | 201d6a7 | 2009-11-06 21:50:40 +0900 | [diff] [blame] | 252 | * Initiate (and continue) low level master read/write transaction. |
| 253 | * This function is only called from i2c_dw_isr, and pumping i2c_msg |
| 254 | * messages into the tx buffer. Even if the size of i2c_msg data is |
| 255 | * longer than the size of the tx buffer, it handles everything. |
Baruch Siach | 1ab52cf | 2009-06-22 16:36:29 +0300 | [diff] [blame] | 256 | */ |
Dirk Brandewie | 2373f6b | 2011-10-29 10:57:23 +0100 | [diff] [blame] | 257 | void |
Shinya Kuribayashi | e77cf23 | 2009-11-06 21:46:04 +0900 | [diff] [blame] | 258 | i2c_dw_xfer_msg(struct dw_i2c_dev *dev) |
Baruch Siach | 1ab52cf | 2009-06-22 16:36:29 +0300 | [diff] [blame] | 259 | { |
Baruch Siach | 1ab52cf | 2009-06-22 16:36:29 +0300 | [diff] [blame] | 260 | struct i2c_msg *msgs = dev->msgs; |
Shinya Kuribayashi | 81e798b | 2009-11-06 21:48:55 +0900 | [diff] [blame] | 261 | u32 intr_mask; |
Shinya Kuribayashi | ae72222 | 2009-11-06 21:49:39 +0900 | [diff] [blame] | 262 | int tx_limit, rx_limit; |
Shinya Kuribayashi | ed5e1dd | 2009-11-06 21:43:52 +0900 | [diff] [blame] | 263 | u32 addr = msgs[dev->msg_write_idx].addr; |
| 264 | u32 buf_len = dev->tx_buf_len; |
Justin P. Mattock | 6993248 | 2011-07-26 23:06:29 -0700 | [diff] [blame] | 265 | u8 *buf = dev->tx_buf; |
Baruch Siach | 1ab52cf | 2009-06-22 16:36:29 +0300 | [diff] [blame] | 266 | |
Shinya Kuribayashi | 201d6a7 | 2009-11-06 21:50:40 +0900 | [diff] [blame] | 267 | intr_mask = DW_IC_INTR_DEFAULT_MASK; |
Shinya Kuribayashi | c70c5cd | 2009-11-06 21:47:30 +0900 | [diff] [blame] | 268 | |
Shinya Kuribayashi | 6d2ea48 | 2009-11-06 21:46:29 +0900 | [diff] [blame] | 269 | for (; dev->msg_write_idx < dev->msgs_num; dev->msg_write_idx++) { |
Shinya Kuribayashi | a0e06ea | 2009-11-06 21:52:22 +0900 | [diff] [blame] | 270 | /* |
| 271 | * if target address has changed, we need to |
Baruch Siach | 1ab52cf | 2009-06-22 16:36:29 +0300 | [diff] [blame] | 272 | * reprogram the target address in the i2c |
| 273 | * adapter when we are done with this transfer |
| 274 | */ |
Shinya Kuribayashi | 8f588e4 | 2009-11-06 21:51:18 +0900 | [diff] [blame] | 275 | if (msgs[dev->msg_write_idx].addr != addr) { |
| 276 | dev_err(dev->dev, |
| 277 | "%s: invalid target address\n", __func__); |
| 278 | dev->msg_err = -EINVAL; |
| 279 | break; |
| 280 | } |
Baruch Siach | 1ab52cf | 2009-06-22 16:36:29 +0300 | [diff] [blame] | 281 | |
| 282 | if (msgs[dev->msg_write_idx].len == 0) { |
| 283 | dev_err(dev->dev, |
| 284 | "%s: invalid message length\n", __func__); |
| 285 | dev->msg_err = -EINVAL; |
Shinya Kuribayashi | 8f588e4 | 2009-11-06 21:51:18 +0900 | [diff] [blame] | 286 | break; |
Baruch Siach | 1ab52cf | 2009-06-22 16:36:29 +0300 | [diff] [blame] | 287 | } |
| 288 | |
| 289 | if (!(dev->status & STATUS_WRITE_IN_PROGRESS)) { |
| 290 | /* new i2c_msg */ |
Shinya Kuribayashi | 26ea15b | 2009-11-06 21:49:14 +0900 | [diff] [blame] | 291 | buf = msgs[dev->msg_write_idx].buf; |
Baruch Siach | 1ab52cf | 2009-06-22 16:36:29 +0300 | [diff] [blame] | 292 | buf_len = msgs[dev->msg_write_idx].len; |
| 293 | } |
| 294 | |
Jean-Hugues Deschenes | 7f27960 | 2011-10-06 11:26:25 -0700 | [diff] [blame] | 295 | tx_limit = dev->tx_fifo_depth - dw_readl(dev, DW_IC_TXFLR); |
| 296 | rx_limit = dev->rx_fifo_depth - dw_readl(dev, DW_IC_RXFLR); |
Shinya Kuribayashi | ae72222 | 2009-11-06 21:49:39 +0900 | [diff] [blame] | 297 | |
Baruch Siach | 1ab52cf | 2009-06-22 16:36:29 +0300 | [diff] [blame] | 298 | while (buf_len > 0 && tx_limit > 0 && rx_limit > 0) { |
| 299 | if (msgs[dev->msg_write_idx].flags & I2C_M_RD) { |
Jean-Hugues Deschenes | 7f27960 | 2011-10-06 11:26:25 -0700 | [diff] [blame] | 300 | dw_writel(dev, 0x100, DW_IC_DATA_CMD); |
Baruch Siach | 1ab52cf | 2009-06-22 16:36:29 +0300 | [diff] [blame] | 301 | rx_limit--; |
| 302 | } else |
Jean-Hugues Deschenes | 7f27960 | 2011-10-06 11:26:25 -0700 | [diff] [blame] | 303 | dw_writel(dev, *buf++, DW_IC_DATA_CMD); |
Baruch Siach | 1ab52cf | 2009-06-22 16:36:29 +0300 | [diff] [blame] | 304 | tx_limit--; buf_len--; |
| 305 | } |
Shinya Kuribayashi | c70c5cd | 2009-11-06 21:47:30 +0900 | [diff] [blame] | 306 | |
Shinya Kuribayashi | 26ea15b | 2009-11-06 21:49:14 +0900 | [diff] [blame] | 307 | dev->tx_buf = buf; |
Shinya Kuribayashi | c70c5cd | 2009-11-06 21:47:30 +0900 | [diff] [blame] | 308 | dev->tx_buf_len = buf_len; |
| 309 | |
| 310 | if (buf_len > 0) { |
| 311 | /* more bytes to be written */ |
Shinya Kuribayashi | c70c5cd | 2009-11-06 21:47:30 +0900 | [diff] [blame] | 312 | dev->status |= STATUS_WRITE_IN_PROGRESS; |
| 313 | break; |
Shinya Kuribayashi | 69151e5 | 2009-11-06 21:51:00 +0900 | [diff] [blame] | 314 | } else |
Shinya Kuribayashi | c70c5cd | 2009-11-06 21:47:30 +0900 | [diff] [blame] | 315 | dev->status &= ~STATUS_WRITE_IN_PROGRESS; |
Baruch Siach | 1ab52cf | 2009-06-22 16:36:29 +0300 | [diff] [blame] | 316 | } |
| 317 | |
Shinya Kuribayashi | 69151e5 | 2009-11-06 21:51:00 +0900 | [diff] [blame] | 318 | /* |
| 319 | * If i2c_msg index search is completed, we don't need TX_EMPTY |
| 320 | * interrupt any more. |
| 321 | */ |
| 322 | if (dev->msg_write_idx == dev->msgs_num) |
| 323 | intr_mask &= ~DW_IC_INTR_TX_EMPTY; |
| 324 | |
Shinya Kuribayashi | 8f588e4 | 2009-11-06 21:51:18 +0900 | [diff] [blame] | 325 | if (dev->msg_err) |
| 326 | intr_mask = 0; |
| 327 | |
Dirk Brandewie | 2373f6b | 2011-10-29 10:57:23 +0100 | [diff] [blame] | 328 | dw_writel(dev, intr_mask, DW_IC_INTR_MASK); |
Baruch Siach | 1ab52cf | 2009-06-22 16:36:29 +0300 | [diff] [blame] | 329 | } |
| 330 | |
| 331 | static void |
Shinya Kuribayashi | 78839bd | 2009-11-06 21:45:39 +0900 | [diff] [blame] | 332 | i2c_dw_read(struct dw_i2c_dev *dev) |
Baruch Siach | 1ab52cf | 2009-06-22 16:36:29 +0300 | [diff] [blame] | 333 | { |
Baruch Siach | 1ab52cf | 2009-06-22 16:36:29 +0300 | [diff] [blame] | 334 | struct i2c_msg *msgs = dev->msgs; |
Shinya Kuribayashi | ae72222 | 2009-11-06 21:49:39 +0900 | [diff] [blame] | 335 | int rx_valid; |
Baruch Siach | 1ab52cf | 2009-06-22 16:36:29 +0300 | [diff] [blame] | 336 | |
Shinya Kuribayashi | 6d2ea48 | 2009-11-06 21:46:29 +0900 | [diff] [blame] | 337 | for (; dev->msg_read_idx < dev->msgs_num; dev->msg_read_idx++) { |
Shinya Kuribayashi | ed5e1dd | 2009-11-06 21:43:52 +0900 | [diff] [blame] | 338 | u32 len; |
Baruch Siach | 1ab52cf | 2009-06-22 16:36:29 +0300 | [diff] [blame] | 339 | u8 *buf; |
| 340 | |
| 341 | if (!(msgs[dev->msg_read_idx].flags & I2C_M_RD)) |
| 342 | continue; |
| 343 | |
Baruch Siach | 1ab52cf | 2009-06-22 16:36:29 +0300 | [diff] [blame] | 344 | if (!(dev->status & STATUS_READ_IN_PROGRESS)) { |
| 345 | len = msgs[dev->msg_read_idx].len; |
| 346 | buf = msgs[dev->msg_read_idx].buf; |
| 347 | } else { |
| 348 | len = dev->rx_buf_len; |
| 349 | buf = dev->rx_buf; |
| 350 | } |
| 351 | |
Jean-Hugues Deschenes | 7f27960 | 2011-10-06 11:26:25 -0700 | [diff] [blame] | 352 | rx_valid = dw_readl(dev, DW_IC_RXFLR); |
Shinya Kuribayashi | ae72222 | 2009-11-06 21:49:39 +0900 | [diff] [blame] | 353 | |
Baruch Siach | 1ab52cf | 2009-06-22 16:36:29 +0300 | [diff] [blame] | 354 | for (; len > 0 && rx_valid > 0; len--, rx_valid--) |
Jean-Hugues Deschenes | 7f27960 | 2011-10-06 11:26:25 -0700 | [diff] [blame] | 355 | *buf++ = dw_readl(dev, DW_IC_DATA_CMD); |
Baruch Siach | 1ab52cf | 2009-06-22 16:36:29 +0300 | [diff] [blame] | 356 | |
| 357 | if (len > 0) { |
| 358 | dev->status |= STATUS_READ_IN_PROGRESS; |
| 359 | dev->rx_buf_len = len; |
| 360 | dev->rx_buf = buf; |
| 361 | return; |
| 362 | } else |
| 363 | dev->status &= ~STATUS_READ_IN_PROGRESS; |
| 364 | } |
| 365 | } |
| 366 | |
Shinya Kuribayashi | ce6eb57 | 2009-11-06 21:51:57 +0900 | [diff] [blame] | 367 | static int i2c_dw_handle_tx_abort(struct dw_i2c_dev *dev) |
| 368 | { |
| 369 | unsigned long abort_source = dev->abort_source; |
| 370 | int i; |
| 371 | |
Shinya Kuribayashi | 6d1ea0f | 2009-11-16 20:40:14 +0900 | [diff] [blame] | 372 | if (abort_source & DW_IC_TX_ABRT_NOACK) { |
Akinobu Mita | 984b3f5 | 2010-03-05 13:41:37 -0800 | [diff] [blame] | 373 | for_each_set_bit(i, &abort_source, ARRAY_SIZE(abort_sources)) |
Shinya Kuribayashi | 6d1ea0f | 2009-11-16 20:40:14 +0900 | [diff] [blame] | 374 | dev_dbg(dev->dev, |
| 375 | "%s: %s\n", __func__, abort_sources[i]); |
| 376 | return -EREMOTEIO; |
| 377 | } |
| 378 | |
Akinobu Mita | 984b3f5 | 2010-03-05 13:41:37 -0800 | [diff] [blame] | 379 | for_each_set_bit(i, &abort_source, ARRAY_SIZE(abort_sources)) |
Shinya Kuribayashi | ce6eb57 | 2009-11-06 21:51:57 +0900 | [diff] [blame] | 380 | dev_err(dev->dev, "%s: %s\n", __func__, abort_sources[i]); |
| 381 | |
| 382 | if (abort_source & DW_IC_TX_ARB_LOST) |
| 383 | return -EAGAIN; |
Shinya Kuribayashi | ce6eb57 | 2009-11-06 21:51:57 +0900 | [diff] [blame] | 384 | else if (abort_source & DW_IC_TX_ABRT_GCALL_READ) |
| 385 | return -EINVAL; /* wrong msgs[] data */ |
| 386 | else |
| 387 | return -EIO; |
| 388 | } |
| 389 | |
Baruch Siach | 1ab52cf | 2009-06-22 16:36:29 +0300 | [diff] [blame] | 390 | /* |
| 391 | * Prepare controller for a transaction and call i2c_dw_xfer_msg |
| 392 | */ |
Dirk Brandewie | 2373f6b | 2011-10-29 10:57:23 +0100 | [diff] [blame] | 393 | int |
Baruch Siach | 1ab52cf | 2009-06-22 16:36:29 +0300 | [diff] [blame] | 394 | i2c_dw_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num) |
| 395 | { |
| 396 | struct dw_i2c_dev *dev = i2c_get_adapdata(adap); |
| 397 | int ret; |
| 398 | |
| 399 | dev_dbg(dev->dev, "%s: msgs: %d\n", __func__, num); |
| 400 | |
| 401 | mutex_lock(&dev->lock); |
| 402 | |
| 403 | INIT_COMPLETION(dev->cmd_complete); |
| 404 | dev->msgs = msgs; |
| 405 | dev->msgs_num = num; |
| 406 | dev->cmd_err = 0; |
| 407 | dev->msg_write_idx = 0; |
| 408 | dev->msg_read_idx = 0; |
| 409 | dev->msg_err = 0; |
| 410 | dev->status = STATUS_IDLE; |
Shinya Kuribayashi | ce6eb57 | 2009-11-06 21:51:57 +0900 | [diff] [blame] | 411 | dev->abort_source = 0; |
Baruch Siach | 1ab52cf | 2009-06-22 16:36:29 +0300 | [diff] [blame] | 412 | |
| 413 | ret = i2c_dw_wait_bus_not_busy(dev); |
| 414 | if (ret < 0) |
| 415 | goto done; |
| 416 | |
| 417 | /* start the transfers */ |
Shinya Kuribayashi | 81e798b | 2009-11-06 21:48:55 +0900 | [diff] [blame] | 418 | i2c_dw_xfer_init(dev); |
Baruch Siach | 1ab52cf | 2009-06-22 16:36:29 +0300 | [diff] [blame] | 419 | |
| 420 | /* wait for tx to complete */ |
| 421 | ret = wait_for_completion_interruptible_timeout(&dev->cmd_complete, HZ); |
| 422 | if (ret == 0) { |
| 423 | dev_err(dev->dev, "controller timed out\n"); |
| 424 | i2c_dw_init(dev); |
| 425 | ret = -ETIMEDOUT; |
| 426 | goto done; |
| 427 | } else if (ret < 0) |
| 428 | goto done; |
| 429 | |
| 430 | if (dev->msg_err) { |
| 431 | ret = dev->msg_err; |
| 432 | goto done; |
| 433 | } |
| 434 | |
| 435 | /* no error */ |
| 436 | if (likely(!dev->cmd_err)) { |
Shinya Kuribayashi | 0774539 | 2009-11-06 21:47:51 +0900 | [diff] [blame] | 437 | /* Disable the adapter */ |
Jean-Hugues Deschenes | 7f27960 | 2011-10-06 11:26:25 -0700 | [diff] [blame] | 438 | dw_writel(dev, 0, DW_IC_ENABLE); |
Baruch Siach | 1ab52cf | 2009-06-22 16:36:29 +0300 | [diff] [blame] | 439 | ret = num; |
| 440 | goto done; |
| 441 | } |
| 442 | |
| 443 | /* We have an error */ |
| 444 | if (dev->cmd_err == DW_IC_ERR_TX_ABRT) { |
Shinya Kuribayashi | ce6eb57 | 2009-11-06 21:51:57 +0900 | [diff] [blame] | 445 | ret = i2c_dw_handle_tx_abort(dev); |
| 446 | goto done; |
Baruch Siach | 1ab52cf | 2009-06-22 16:36:29 +0300 | [diff] [blame] | 447 | } |
| 448 | ret = -EIO; |
| 449 | |
| 450 | done: |
| 451 | mutex_unlock(&dev->lock); |
| 452 | |
| 453 | return ret; |
| 454 | } |
| 455 | |
Dirk Brandewie | 2373f6b | 2011-10-29 10:57:23 +0100 | [diff] [blame] | 456 | u32 i2c_dw_func(struct i2c_adapter *adap) |
Baruch Siach | 1ab52cf | 2009-06-22 16:36:29 +0300 | [diff] [blame] | 457 | { |
Dirk Brandewie | 2fa8326 | 2011-10-06 11:26:31 -0700 | [diff] [blame] | 458 | struct dw_i2c_dev *dev = i2c_get_adapdata(adap); |
| 459 | return dev->functionality; |
Baruch Siach | 1ab52cf | 2009-06-22 16:36:29 +0300 | [diff] [blame] | 460 | } |
| 461 | |
Shinya Kuribayashi | e28000a | 2009-11-06 21:44:37 +0900 | [diff] [blame] | 462 | static u32 i2c_dw_read_clear_intrbits(struct dw_i2c_dev *dev) |
| 463 | { |
| 464 | u32 stat; |
| 465 | |
| 466 | /* |
| 467 | * The IC_INTR_STAT register just indicates "enabled" interrupts. |
| 468 | * Ths unmasked raw version of interrupt status bits are available |
| 469 | * in the IC_RAW_INTR_STAT register. |
| 470 | * |
| 471 | * That is, |
Dirk Brandewie | 2373f6b | 2011-10-29 10:57:23 +0100 | [diff] [blame] | 472 | * stat = dw_readl(IC_INTR_STAT); |
Shinya Kuribayashi | e28000a | 2009-11-06 21:44:37 +0900 | [diff] [blame] | 473 | * equals to, |
Dirk Brandewie | 2373f6b | 2011-10-29 10:57:23 +0100 | [diff] [blame] | 474 | * stat = dw_readl(IC_RAW_INTR_STAT) & dw_readl(IC_INTR_MASK); |
Shinya Kuribayashi | e28000a | 2009-11-06 21:44:37 +0900 | [diff] [blame] | 475 | * |
| 476 | * The raw version might be useful for debugging purposes. |
| 477 | */ |
Jean-Hugues Deschenes | 7f27960 | 2011-10-06 11:26:25 -0700 | [diff] [blame] | 478 | stat = dw_readl(dev, DW_IC_INTR_STAT); |
Shinya Kuribayashi | e28000a | 2009-11-06 21:44:37 +0900 | [diff] [blame] | 479 | |
| 480 | /* |
| 481 | * Do not use the IC_CLR_INTR register to clear interrupts, or |
| 482 | * you'll miss some interrupts, triggered during the period from |
Dirk Brandewie | 2373f6b | 2011-10-29 10:57:23 +0100 | [diff] [blame] | 483 | * dw_readl(IC_INTR_STAT) to dw_readl(IC_CLR_INTR). |
Shinya Kuribayashi | e28000a | 2009-11-06 21:44:37 +0900 | [diff] [blame] | 484 | * |
| 485 | * Instead, use the separately-prepared IC_CLR_* registers. |
| 486 | */ |
| 487 | if (stat & DW_IC_INTR_RX_UNDER) |
Jean-Hugues Deschenes | 7f27960 | 2011-10-06 11:26:25 -0700 | [diff] [blame] | 488 | dw_readl(dev, DW_IC_CLR_RX_UNDER); |
Shinya Kuribayashi | e28000a | 2009-11-06 21:44:37 +0900 | [diff] [blame] | 489 | if (stat & DW_IC_INTR_RX_OVER) |
Jean-Hugues Deschenes | 7f27960 | 2011-10-06 11:26:25 -0700 | [diff] [blame] | 490 | dw_readl(dev, DW_IC_CLR_RX_OVER); |
Shinya Kuribayashi | e28000a | 2009-11-06 21:44:37 +0900 | [diff] [blame] | 491 | if (stat & DW_IC_INTR_TX_OVER) |
Jean-Hugues Deschenes | 7f27960 | 2011-10-06 11:26:25 -0700 | [diff] [blame] | 492 | dw_readl(dev, DW_IC_CLR_TX_OVER); |
Shinya Kuribayashi | e28000a | 2009-11-06 21:44:37 +0900 | [diff] [blame] | 493 | if (stat & DW_IC_INTR_RD_REQ) |
Jean-Hugues Deschenes | 7f27960 | 2011-10-06 11:26:25 -0700 | [diff] [blame] | 494 | dw_readl(dev, DW_IC_CLR_RD_REQ); |
Shinya Kuribayashi | e28000a | 2009-11-06 21:44:37 +0900 | [diff] [blame] | 495 | if (stat & DW_IC_INTR_TX_ABRT) { |
| 496 | /* |
| 497 | * The IC_TX_ABRT_SOURCE register is cleared whenever |
| 498 | * the IC_CLR_TX_ABRT is read. Preserve it beforehand. |
| 499 | */ |
Jean-Hugues Deschenes | 7f27960 | 2011-10-06 11:26:25 -0700 | [diff] [blame] | 500 | dev->abort_source = dw_readl(dev, DW_IC_TX_ABRT_SOURCE); |
| 501 | dw_readl(dev, DW_IC_CLR_TX_ABRT); |
Shinya Kuribayashi | e28000a | 2009-11-06 21:44:37 +0900 | [diff] [blame] | 502 | } |
| 503 | if (stat & DW_IC_INTR_RX_DONE) |
Jean-Hugues Deschenes | 7f27960 | 2011-10-06 11:26:25 -0700 | [diff] [blame] | 504 | dw_readl(dev, DW_IC_CLR_RX_DONE); |
Shinya Kuribayashi | e28000a | 2009-11-06 21:44:37 +0900 | [diff] [blame] | 505 | if (stat & DW_IC_INTR_ACTIVITY) |
Jean-Hugues Deschenes | 7f27960 | 2011-10-06 11:26:25 -0700 | [diff] [blame] | 506 | dw_readl(dev, DW_IC_CLR_ACTIVITY); |
Shinya Kuribayashi | e28000a | 2009-11-06 21:44:37 +0900 | [diff] [blame] | 507 | if (stat & DW_IC_INTR_STOP_DET) |
Jean-Hugues Deschenes | 7f27960 | 2011-10-06 11:26:25 -0700 | [diff] [blame] | 508 | dw_readl(dev, DW_IC_CLR_STOP_DET); |
Shinya Kuribayashi | e28000a | 2009-11-06 21:44:37 +0900 | [diff] [blame] | 509 | if (stat & DW_IC_INTR_START_DET) |
Jean-Hugues Deschenes | 7f27960 | 2011-10-06 11:26:25 -0700 | [diff] [blame] | 510 | dw_readl(dev, DW_IC_CLR_START_DET); |
Shinya Kuribayashi | e28000a | 2009-11-06 21:44:37 +0900 | [diff] [blame] | 511 | if (stat & DW_IC_INTR_GEN_CALL) |
Jean-Hugues Deschenes | 7f27960 | 2011-10-06 11:26:25 -0700 | [diff] [blame] | 512 | dw_readl(dev, DW_IC_CLR_GEN_CALL); |
Shinya Kuribayashi | e28000a | 2009-11-06 21:44:37 +0900 | [diff] [blame] | 513 | |
| 514 | return stat; |
| 515 | } |
| 516 | |
Baruch Siach | 1ab52cf | 2009-06-22 16:36:29 +0300 | [diff] [blame] | 517 | /* |
| 518 | * Interrupt service routine. This gets called whenever an I2C interrupt |
| 519 | * occurs. |
| 520 | */ |
Dirk Brandewie | 2373f6b | 2011-10-29 10:57:23 +0100 | [diff] [blame] | 521 | irqreturn_t i2c_dw_isr(int this_irq, void *dev_id) |
Baruch Siach | 1ab52cf | 2009-06-22 16:36:29 +0300 | [diff] [blame] | 522 | { |
| 523 | struct dw_i2c_dev *dev = dev_id; |
Dirk Brandewie | af06cf6 | 2011-10-06 11:26:33 -0700 | [diff] [blame^] | 524 | u32 stat, enabled; |
| 525 | |
| 526 | enabled = dw_readl(dev, DW_IC_ENABLE); |
| 527 | stat = dw_readl(dev, DW_IC_RAW_INTR_STAT); |
| 528 | dev_dbg(dev->dev, "%s: %s enabled= 0x%x stat=0x%x\n", __func__, |
| 529 | dev->adapter.name, enabled, stat); |
| 530 | if (!enabled || !(stat & ~DW_IC_INTR_ACTIVITY)) |
| 531 | return IRQ_NONE; |
Baruch Siach | 1ab52cf | 2009-06-22 16:36:29 +0300 | [diff] [blame] | 532 | |
Shinya Kuribayashi | e28000a | 2009-11-06 21:44:37 +0900 | [diff] [blame] | 533 | stat = i2c_dw_read_clear_intrbits(dev); |
Shinya Kuribayashi | e28000a | 2009-11-06 21:44:37 +0900 | [diff] [blame] | 534 | |
Baruch Siach | 1ab52cf | 2009-06-22 16:36:29 +0300 | [diff] [blame] | 535 | if (stat & DW_IC_INTR_TX_ABRT) { |
Baruch Siach | 1ab52cf | 2009-06-22 16:36:29 +0300 | [diff] [blame] | 536 | dev->cmd_err |= DW_IC_ERR_TX_ABRT; |
| 537 | dev->status = STATUS_IDLE; |
Shinya Kuribayashi | 597fe31 | 2009-11-06 21:51:36 +0900 | [diff] [blame] | 538 | |
| 539 | /* |
| 540 | * Anytime TX_ABRT is set, the contents of the tx/rx |
| 541 | * buffers are flushed. Make sure to skip them. |
| 542 | */ |
Jean-Hugues Deschenes | 7f27960 | 2011-10-06 11:26:25 -0700 | [diff] [blame] | 543 | dw_writel(dev, 0, DW_IC_INTR_MASK); |
Shinya Kuribayashi | 597fe31 | 2009-11-06 21:51:36 +0900 | [diff] [blame] | 544 | goto tx_aborted; |
Shinya Kuribayashi | 0774539 | 2009-11-06 21:47:51 +0900 | [diff] [blame] | 545 | } |
Baruch Siach | 1ab52cf | 2009-06-22 16:36:29 +0300 | [diff] [blame] | 546 | |
Shinya Kuribayashi | 21a89d4 | 2009-11-06 21:48:33 +0900 | [diff] [blame] | 547 | if (stat & DW_IC_INTR_RX_FULL) |
Shinya Kuribayashi | 0774539 | 2009-11-06 21:47:51 +0900 | [diff] [blame] | 548 | i2c_dw_read(dev); |
Shinya Kuribayashi | 21a89d4 | 2009-11-06 21:48:33 +0900 | [diff] [blame] | 549 | |
| 550 | if (stat & DW_IC_INTR_TX_EMPTY) |
Shinya Kuribayashi | 0774539 | 2009-11-06 21:47:51 +0900 | [diff] [blame] | 551 | i2c_dw_xfer_msg(dev); |
Shinya Kuribayashi | 0774539 | 2009-11-06 21:47:51 +0900 | [diff] [blame] | 552 | |
| 553 | /* |
| 554 | * No need to modify or disable the interrupt mask here. |
| 555 | * i2c_dw_xfer_msg() will take care of it according to |
| 556 | * the current transmit status. |
| 557 | */ |
| 558 | |
Shinya Kuribayashi | 597fe31 | 2009-11-06 21:51:36 +0900 | [diff] [blame] | 559 | tx_aborted: |
Shinya Kuribayashi | 8f588e4 | 2009-11-06 21:51:18 +0900 | [diff] [blame] | 560 | if ((stat & (DW_IC_INTR_TX_ABRT | DW_IC_INTR_STOP_DET)) || dev->msg_err) |
Baruch Siach | 1ab52cf | 2009-06-22 16:36:29 +0300 | [diff] [blame] | 561 | complete(&dev->cmd_complete); |
| 562 | |
| 563 | return IRQ_HANDLED; |
| 564 | } |