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Linus Torvalds1da177e2005-04-16 15:20:36 -07001/*------------------------------------------------------------------------
2 . smc91x.h - macros for SMSC's 91C9x/91C1xx single-chip Ethernet device.
3 .
4 . Copyright (C) 1996 by Erik Stahlman
5 . Copyright (C) 2001 Standard Microsystems Corporation
6 . Developed by Simple Network Magic Corporation
7 . Copyright (C) 2003 Monta Vista Software, Inc.
8 . Unified SMC91x driver by Nicolas Pitre
9 .
10 . This program is free software; you can redistribute it and/or modify
11 . it under the terms of the GNU General Public License as published by
12 . the Free Software Foundation; either version 2 of the License, or
13 . (at your option) any later version.
14 .
15 . This program is distributed in the hope that it will be useful,
16 . but WITHOUT ANY WARRANTY; without even the implied warranty of
17 . MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 . GNU General Public License for more details.
19 .
20 . You should have received a copy of the GNU General Public License
21 . along with this program; if not, write to the Free Software
22 . Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
23 .
24 . Information contained in this file was obtained from the LAN91C111
25 . manual from SMC. To get a copy, if you really want one, you can find
26 . information under www.smsc.com.
27 .
28 . Authors
29 . Erik Stahlman <erik@vt.edu>
30 . Daris A Nevil <dnevil@snmc.com>
31 . Nicolas Pitre <nico@cam.org>
32 .
33 ---------------------------------------------------------------------------*/
34#ifndef _SMC91X_H_
35#define _SMC91X_H_
36
Magnus Damm3e947942008-02-22 19:55:15 +090037#include <linux/smc91x.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070038
39/*
40 * Define your architecture specific bus configuration parameters here.
41 */
42
43#if defined(CONFIG_ARCH_LUBBOCK)
44
45/* We can only do 16-bit reads and writes in the static memory space. */
46#define SMC_CAN_USE_8BIT 0
47#define SMC_CAN_USE_16BIT 1
48#define SMC_CAN_USE_32BIT 0
49#define SMC_NOWAIT 1
50
51/* The first two address lines aren't connected... */
52#define SMC_IO_SHIFT 2
53
54#define SMC_inw(a, r) readw((a) + (r))
55#define SMC_outw(v, a, r) writew(v, (a) + (r))
56#define SMC_insw(a, r, p, l) readsw((a) + (r), p, l)
57#define SMC_outsw(a, r, p, l) writesw((a) + (r), p, l)
Russell Kinge7b3dc72008-01-14 22:30:10 +000058#define SMC_IRQ_FLAGS (-1) /* from resource */
Linus Torvalds1da177e2005-04-16 15:20:36 -070059
Mike Frysinger95af9fe2007-11-23 17:55:50 +080060#elif defined(CONFIG_BLACKFIN)
Wu, Bryan0851a282007-05-06 14:50:32 -070061
62#define SMC_IRQ_FLAGS IRQF_TRIGGER_HIGH
Jean-Christian de Rivazc5760abd2007-06-11 17:44:14 +080063#define RPC_LSA_DEFAULT RPC_LED_100_10
64#define RPC_LSB_DEFAULT RPC_LED_TX_RX
Wu, Bryan0851a282007-05-06 14:50:32 -070065
66# if defined (CONFIG_BFIN561_EZKIT)
67#define SMC_CAN_USE_8BIT 0
68#define SMC_CAN_USE_16BIT 1
69#define SMC_CAN_USE_32BIT 1
70#define SMC_IO_SHIFT 0
71#define SMC_NOWAIT 1
72#define SMC_USE_BFIN_DMA 0
73
74
75#define SMC_inw(a, r) readw((a) + (r))
76#define SMC_outw(v, a, r) writew(v, (a) + (r))
77#define SMC_inl(a, r) readl((a) + (r))
78#define SMC_outl(v, a, r) writel(v, (a) + (r))
79#define SMC_outsl(a, r, p, l) outsl((unsigned long *)((a) + (r)), p, l)
80#define SMC_insl(a, r, p, l) insl ((unsigned long *)((a) + (r)), p, l)
81# else
82#define SMC_CAN_USE_8BIT 0
83#define SMC_CAN_USE_16BIT 1
84#define SMC_CAN_USE_32BIT 0
85#define SMC_IO_SHIFT 0
86#define SMC_NOWAIT 1
87#define SMC_USE_BFIN_DMA 0
88
89
90#define SMC_inw(a, r) readw((a) + (r))
91#define SMC_outw(v, a, r) writew(v, (a) + (r))
92#define SMC_outsw(a, r, p, l) outsw((unsigned long *)((a) + (r)), p, l)
93#define SMC_insw(a, r, p, l) insw ((unsigned long *)((a) + (r)), p, l)
94# endif
95/* check if the mac in reg is valid */
Bryan Wu7427d8b2008-06-11 12:08:39 +080096#define SMC_GET_MAC_ADDR(lp, addr) \
Wu, Bryan0851a282007-05-06 14:50:32 -070097 do { \
98 unsigned int __v; \
Bryan Wu7427d8b2008-06-11 12:08:39 +080099 __v = SMC_inw(ioaddr, ADDR0_REG(lp)); \
Wu, Bryan0851a282007-05-06 14:50:32 -0700100 addr[0] = __v; addr[1] = __v >> 8; \
Bryan Wu7427d8b2008-06-11 12:08:39 +0800101 __v = SMC_inw(ioaddr, ADDR1_REG(lp)); \
Wu, Bryan0851a282007-05-06 14:50:32 -0700102 addr[2] = __v; addr[3] = __v >> 8; \
Bryan Wu7427d8b2008-06-11 12:08:39 +0800103 __v = SMC_inw(ioaddr, ADDR2_REG(lp)); \
Wu, Bryan0851a282007-05-06 14:50:32 -0700104 addr[4] = __v; addr[5] = __v >> 8; \
105 if (*(u32 *)(&addr[0]) == 0xFFFFFFFF) { \
106 random_ether_addr(addr); \
107 } \
108 } while (0)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700109#elif defined(CONFIG_REDWOOD_5) || defined(CONFIG_REDWOOD_6)
110
111/* We can only do 16-bit reads and writes in the static memory space. */
112#define SMC_CAN_USE_8BIT 0
113#define SMC_CAN_USE_16BIT 1
114#define SMC_CAN_USE_32BIT 0
115#define SMC_NOWAIT 1
116
117#define SMC_IO_SHIFT 0
118
119#define SMC_inw(a, r) in_be16((volatile u16 *)((a) + (r)))
120#define SMC_outw(v, a, r) out_be16((volatile u16 *)((a) + (r)), v)
121#define SMC_insw(a, r, p, l) \
122 do { \
123 unsigned long __port = (a) + (r); \
124 u16 *__p = (u16 *)(p); \
125 int __l = (l); \
126 insw(__port, __p, __l); \
127 while (__l > 0) { \
128 *__p = swab16(*__p); \
129 __p++; \
130 __l--; \
131 } \
132 } while (0)
133#define SMC_outsw(a, r, p, l) \
134 do { \
135 unsigned long __port = (a) + (r); \
136 u16 *__p = (u16 *)(p); \
137 int __l = (l); \
138 while (__l > 0) { \
139 /* Believe it or not, the swab isn't needed. */ \
140 outw( /* swab16 */ (*__p++), __port); \
141 __l--; \
142 } \
143 } while (0)
Russell King9ded96f2006-01-08 01:02:07 -0800144#define SMC_IRQ_FLAGS (0)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700145
146#elif defined(CONFIG_SA1100_PLEB)
147/* We can only do 16-bit reads and writes in the static memory space. */
148#define SMC_CAN_USE_8BIT 1
149#define SMC_CAN_USE_16BIT 1
150#define SMC_CAN_USE_32BIT 0
151#define SMC_IO_SHIFT 0
152#define SMC_NOWAIT 1
153
Russell King1cf99be2005-11-12 21:49:36 +0000154#define SMC_inb(a, r) readb((a) + (r))
155#define SMC_insb(a, r, p, l) readsb((a) + (r), p, (l))
156#define SMC_inw(a, r) readw((a) + (r))
157#define SMC_insw(a, r, p, l) readsw((a) + (r), p, l)
158#define SMC_outb(v, a, r) writeb(v, (a) + (r))
159#define SMC_outsb(a, r, p, l) writesb((a) + (r), p, (l))
160#define SMC_outw(v, a, r) writew(v, (a) + (r))
161#define SMC_outsw(a, r, p, l) writesw((a) + (r), p, l)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700162
Russell Kinge7b3dc72008-01-14 22:30:10 +0000163#define SMC_IRQ_FLAGS (-1)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700164
165#elif defined(CONFIG_SA1100_ASSABET)
166
167#include <asm/arch/neponset.h>
168
169/* We can only do 8-bit reads and writes in the static memory space. */
170#define SMC_CAN_USE_8BIT 1
171#define SMC_CAN_USE_16BIT 0
172#define SMC_CAN_USE_32BIT 0
173#define SMC_NOWAIT 1
174
175/* The first two address lines aren't connected... */
176#define SMC_IO_SHIFT 2
177
178#define SMC_inb(a, r) readb((a) + (r))
179#define SMC_outb(v, a, r) writeb(v, (a) + (r))
180#define SMC_insb(a, r, p, l) readsb((a) + (r), p, (l))
181#define SMC_outsb(a, r, p, l) writesb((a) + (r), p, (l))
Russell Kinge7b3dc72008-01-14 22:30:10 +0000182#define SMC_IRQ_FLAGS (-1) /* from resource */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700183
Lennert Buytenhekb0348b92006-03-28 17:19:50 +0200184#elif defined(CONFIG_MACH_LOGICPD_PXA270)
185
186#define SMC_CAN_USE_8BIT 0
187#define SMC_CAN_USE_16BIT 1
188#define SMC_CAN_USE_32BIT 0
189#define SMC_IO_SHIFT 0
190#define SMC_NOWAIT 1
Lennert Buytenhekb0348b92006-03-28 17:19:50 +0200191
Lennert Buytenhekb0348b92006-03-28 17:19:50 +0200192#define SMC_inw(a, r) readw((a) + (r))
Lennert Buytenhekb0348b92006-03-28 17:19:50 +0200193#define SMC_outw(v, a, r) writew(v, (a) + (r))
Lennert Buytenhekb0348b92006-03-28 17:19:50 +0200194#define SMC_insw(a, r, p, l) readsw((a) + (r), p, l)
195#define SMC_outsw(a, r, p, l) writesw((a) + (r), p, l)
196
Linus Torvalds1da177e2005-04-16 15:20:36 -0700197#elif defined(CONFIG_ARCH_INNOKOM) || \
198 defined(CONFIG_MACH_MAINSTONE) || \
199 defined(CONFIG_ARCH_PXA_IDP) || \
Robert Schwebel4f15a982008-01-08 08:50:02 +0100200 defined(CONFIG_ARCH_RAMSES) || \
201 defined(CONFIG_ARCH_PCM027)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700202
203#define SMC_CAN_USE_8BIT 1
204#define SMC_CAN_USE_16BIT 1
205#define SMC_CAN_USE_32BIT 1
206#define SMC_IO_SHIFT 0
207#define SMC_NOWAIT 1
208#define SMC_USE_PXA_DMA 1
209
210#define SMC_inb(a, r) readb((a) + (r))
211#define SMC_inw(a, r) readw((a) + (r))
212#define SMC_inl(a, r) readl((a) + (r))
213#define SMC_outb(v, a, r) writeb(v, (a) + (r))
214#define SMC_outl(v, a, r) writel(v, (a) + (r))
215#define SMC_insl(a, r, p, l) readsl((a) + (r), p, l)
216#define SMC_outsl(a, r, p, l) writesl((a) + (r), p, l)
Russell Kinge7b3dc72008-01-14 22:30:10 +0000217#define SMC_IRQ_FLAGS (-1) /* from resource */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700218
219/* We actually can't write halfwords properly if not word aligned */
220static inline void
Nicolas Pitreeb1d6982005-05-12 20:19:09 -0400221SMC_outw(u16 val, void __iomem *ioaddr, int reg)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700222{
223 if (reg & 2) {
224 unsigned int v = val << 16;
225 v |= readl(ioaddr + (reg & ~2)) & 0xffff;
226 writel(v, ioaddr + (reg & ~2));
227 } else {
228 writew(val, ioaddr + reg);
229 }
230}
231
eric miao7c826a02007-10-30 09:48:41 +0800232#elif defined(CONFIG_MACH_ZYLONITE)
233
234#define SMC_CAN_USE_8BIT 1
235#define SMC_CAN_USE_16BIT 1
236#define SMC_CAN_USE_32BIT 0
237#define SMC_IO_SHIFT 0
238#define SMC_NOWAIT 1
239#define SMC_USE_PXA_DMA 1
240#define SMC_inb(a, r) readb((a) + (r))
241#define SMC_inw(a, r) readw((a) + (r))
242#define SMC_insw(a, r, p, l) insw((a) + (r), p, l)
243#define SMC_outsw(a, r, p, l) outsw((a) + (r), p, l)
244#define SMC_outb(v, a, r) writeb(v, (a) + (r))
245#define SMC_outw(v, a, r) writew(v, (a) + (r))
Russell Kinge7b3dc72008-01-14 22:30:10 +0000246#define SMC_IRQ_FLAGS (-1) /* from resource */
eric miao7c826a02007-10-30 09:48:41 +0800247
Linus Torvalds1da177e2005-04-16 15:20:36 -0700248#elif defined(CONFIG_ARCH_OMAP)
249
250/* We can only do 16-bit reads and writes in the static memory space. */
251#define SMC_CAN_USE_8BIT 0
252#define SMC_CAN_USE_16BIT 1
253#define SMC_CAN_USE_32BIT 0
254#define SMC_IO_SHIFT 0
255#define SMC_NOWAIT 1
256
Linus Torvalds1da177e2005-04-16 15:20:36 -0700257#define SMC_inw(a, r) readw((a) + (r))
258#define SMC_outw(v, a, r) writew(v, (a) + (r))
259#define SMC_insw(a, r, p, l) readsw((a) + (r), p, l)
260#define SMC_outsw(a, r, p, l) writesw((a) + (r), p, l)
Russell Kinge7b3dc72008-01-14 22:30:10 +0000261#define SMC_IRQ_FLAGS (-1) /* from resource */
David Brownell5f13e7e2005-05-16 08:53:52 -0700262
Linus Torvalds1da177e2005-04-16 15:20:36 -0700263#elif defined(CONFIG_SH_SH4202_MICRODEV)
264
265#define SMC_CAN_USE_8BIT 0
266#define SMC_CAN_USE_16BIT 1
267#define SMC_CAN_USE_32BIT 0
268
269#define SMC_inb(a, r) inb((a) + (r) - 0xa0000000)
270#define SMC_inw(a, r) inw((a) + (r) - 0xa0000000)
271#define SMC_inl(a, r) inl((a) + (r) - 0xa0000000)
272#define SMC_outb(v, a, r) outb(v, (a) + (r) - 0xa0000000)
273#define SMC_outw(v, a, r) outw(v, (a) + (r) - 0xa0000000)
274#define SMC_outl(v, a, r) outl(v, (a) + (r) - 0xa0000000)
275#define SMC_insl(a, r, p, l) insl((a) + (r) - 0xa0000000, p, l)
276#define SMC_outsl(a, r, p, l) outsl((a) + (r) - 0xa0000000, p, l)
277#define SMC_insw(a, r, p, l) insw((a) + (r) - 0xa0000000, p, l)
278#define SMC_outsw(a, r, p, l) outsw((a) + (r) - 0xa0000000, p, l)
279
Russell King9ded96f2006-01-08 01:02:07 -0800280#define SMC_IRQ_FLAGS (0)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700281
282#elif defined(CONFIG_ISA)
283
284#define SMC_CAN_USE_8BIT 1
285#define SMC_CAN_USE_16BIT 1
286#define SMC_CAN_USE_32BIT 0
287
288#define SMC_inb(a, r) inb((a) + (r))
289#define SMC_inw(a, r) inw((a) + (r))
290#define SMC_outb(v, a, r) outb(v, (a) + (r))
291#define SMC_outw(v, a, r) outw(v, (a) + (r))
292#define SMC_insw(a, r, p, l) insw((a) + (r), p, l)
293#define SMC_outsw(a, r, p, l) outsw((a) + (r), p, l)
294
295#elif defined(CONFIG_M32R)
296
297#define SMC_CAN_USE_8BIT 0
298#define SMC_CAN_USE_16BIT 1
299#define SMC_CAN_USE_32BIT 0
300
Mariusz Kozlowski59dc76a2006-12-04 15:04:56 -0800301#define SMC_inb(a, r) inb(((u32)a) + (r))
Hirokazu Takataf3ac9fb2005-10-30 15:00:06 -0800302#define SMC_inw(a, r) inw(((u32)a) + (r))
303#define SMC_outb(v, a, r) outb(v, ((u32)a) + (r))
304#define SMC_outw(v, a, r) outw(v, ((u32)a) + (r))
305#define SMC_insw(a, r, p, l) insw(((u32)a) + (r), p, l)
306#define SMC_outsw(a, r, p, l) outsw(((u32)a) + (r), p, l)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700307
Russell King9ded96f2006-01-08 01:02:07 -0800308#define SMC_IRQ_FLAGS (0)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700309
310#define RPC_LSA_DEFAULT RPC_LED_TX_RX
311#define RPC_LSB_DEFAULT RPC_LED_100_10
312
Marc Singerd4adcff2006-05-16 11:41:40 +0100313#elif defined(CONFIG_MACH_LPD79520) \
314 || defined(CONFIG_MACH_LPD7A400) \
315 || defined(CONFIG_MACH_LPD7A404)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700316
Marc Singerd4adcff2006-05-16 11:41:40 +0100317/* The LPD7X_IOBARRIER is necessary to overcome a mismatch between the
318 * way that the CPU handles chip selects and the way that the SMC chip
319 * expects the chip select to operate. Refer to
Linus Torvalds1da177e2005-04-16 15:20:36 -0700320 * Documentation/arm/Sharp-LH/IOBarrier for details. The read from
Marc Singerd4adcff2006-05-16 11:41:40 +0100321 * IOBARRIER is a byte, in order that we read the least-common
322 * denominator. It would be wasteful to read 32 bits from an 8-bit
323 * accessible region.
Linus Torvalds1da177e2005-04-16 15:20:36 -0700324 *
325 * There is no explicit protection against interrupts intervening
326 * between the writew and the IOBARRIER. In SMC ISR there is a
327 * preamble that performs an IOBARRIER in the extremely unlikely event
328 * that the driver interrupts itself between a writew to the chip an
329 * the IOBARRIER that follows *and* the cache is large enough that the
330 * first off-chip access while handing the interrupt is to the SMC
331 * chip. Other devices in the same address space as the SMC chip must
332 * be aware of the potential for trouble and perform a similar
333 * IOBARRIER on entry to their ISR.
334 */
335
336#include <asm/arch/constants.h> /* IOBARRIER_VIRT */
337
338#define SMC_CAN_USE_8BIT 0
339#define SMC_CAN_USE_16BIT 1
340#define SMC_CAN_USE_32BIT 0
341#define SMC_NOWAIT 0
Marc Singerd4adcff2006-05-16 11:41:40 +0100342#define LPD7X_IOBARRIER readb (IOBARRIER_VIRT)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700343
Marc Singerd4adcff2006-05-16 11:41:40 +0100344#define SMC_inw(a,r)\
345 ({ unsigned short v = readw ((void*) ((a) + (r))); LPD7X_IOBARRIER; v; })
346#define SMC_outw(v,a,r) ({ writew ((v), (a) + (r)); LPD7X_IOBARRIER; })
Linus Torvalds1da177e2005-04-16 15:20:36 -0700347
Marc Singerd4adcff2006-05-16 11:41:40 +0100348#define SMC_insw LPD7_SMC_insw
349static inline void LPD7_SMC_insw (unsigned char* a, int r,
350 unsigned char* p, int l)
351{
352 unsigned short* ps = (unsigned short*) p;
353 while (l-- > 0) {
354 *ps++ = readw (a + r);
355 LPD7X_IOBARRIER;
356 }
357}
Nicolas Pitre09779c62006-03-20 11:54:27 -0500358
Marc Singerd4adcff2006-05-16 11:41:40 +0100359#define SMC_outsw LPD7_SMC_outsw
360static inline void LPD7_SMC_outsw (unsigned char* a, int r,
361 unsigned char* p, int l)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700362{
363 unsigned short* ps = (unsigned short*) p;
364 while (l-- > 0) {
365 writew (*ps++, a + r);
Marc Singerd4adcff2006-05-16 11:41:40 +0100366 LPD7X_IOBARRIER;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700367 }
368}
369
Marc Singerd4adcff2006-05-16 11:41:40 +0100370#define SMC_INTERRUPT_PREAMBLE LPD7X_IOBARRIER
Linus Torvalds1da177e2005-04-16 15:20:36 -0700371
372#define RPC_LSA_DEFAULT RPC_LED_TX_RX
373#define RPC_LSB_DEFAULT RPC_LED_100_10
374
Pete Popov55793452005-11-09 22:46:05 -0500375#elif defined(CONFIG_SOC_AU1X00)
376
377#include <au1xxx.h>
378
379/* We can only do 16-bit reads and writes in the static memory space. */
380#define SMC_CAN_USE_8BIT 0
381#define SMC_CAN_USE_16BIT 1
382#define SMC_CAN_USE_32BIT 0
383#define SMC_IO_SHIFT 0
384#define SMC_NOWAIT 1
385
386#define SMC_inw(a, r) au_readw((unsigned long)((a) + (r)))
387#define SMC_insw(a, r, p, l) \
388 do { \
389 unsigned long _a = (unsigned long)((a) + (r)); \
390 int _l = (l); \
391 u16 *_p = (u16 *)(p); \
392 while (_l-- > 0) \
393 *_p++ = au_readw(_a); \
394 } while(0)
395#define SMC_outw(v, a, r) au_writew(v, (unsigned long)((a) + (r)))
396#define SMC_outsw(a, r, p, l) \
397 do { \
398 unsigned long _a = (unsigned long)((a) + (r)); \
399 int _l = (l); \
400 const u16 *_p = (const u16 *)(p); \
401 while (_l-- > 0) \
402 au_writew(*_p++ , _a); \
403 } while(0)
404
Russell King9ded96f2006-01-08 01:02:07 -0800405#define SMC_IRQ_FLAGS (0)
Pete Popov55793452005-11-09 22:46:05 -0500406
Deepak Saxena8431adf2006-07-11 23:02:48 -0700407#elif defined(CONFIG_ARCH_VERSATILE)
408
409#define SMC_CAN_USE_8BIT 1
410#define SMC_CAN_USE_16BIT 1
411#define SMC_CAN_USE_32BIT 1
412#define SMC_NOWAIT 1
413
414#define SMC_inb(a, r) readb((a) + (r))
415#define SMC_inw(a, r) readw((a) + (r))
416#define SMC_inl(a, r) readl((a) + (r))
417#define SMC_outb(v, a, r) writeb(v, (a) + (r))
418#define SMC_outw(v, a, r) writew(v, (a) + (r))
419#define SMC_outl(v, a, r) writel(v, (a) + (r))
420#define SMC_insl(a, r, p, l) readsl((a) + (r), p, l)
421#define SMC_outsl(a, r, p, l) writesl((a) + (r), p, l)
Russell Kinge7b3dc72008-01-14 22:30:10 +0000422#define SMC_IRQ_FLAGS (-1) /* from resource */
Deepak Saxena8431adf2006-07-11 23:02:48 -0700423
David Howellsb920de12008-02-08 04:19:31 -0800424#elif defined(CONFIG_MN10300)
425
426/*
427 * MN10300/AM33 configuration
428 */
429
430#include <asm/unit/smc91111.h>
431
Linus Torvalds1da177e2005-04-16 15:20:36 -0700432#else
433
David Howellsb920de12008-02-08 04:19:31 -0800434/*
435 * Default configuration
436 */
437
Linus Torvalds1da177e2005-04-16 15:20:36 -0700438#define SMC_CAN_USE_8BIT 1
439#define SMC_CAN_USE_16BIT 1
440#define SMC_CAN_USE_32BIT 1
441#define SMC_NOWAIT 1
442
443#define SMC_inb(a, r) readb((a) + (r))
444#define SMC_inw(a, r) readw((a) + (r))
445#define SMC_inl(a, r) readl((a) + (r))
446#define SMC_outb(v, a, r) writeb(v, (a) + (r))
447#define SMC_outw(v, a, r) writew(v, (a) + (r))
448#define SMC_outl(v, a, r) writel(v, (a) + (r))
Magnus Damm8a214c12008-02-22 19:55:24 +0900449#define SMC_insw(a, r, p, l) readsw((a) + (r), p, l)
450#define SMC_outsw(a, r, p, l) writesw((a) + (r), p, l)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700451#define SMC_insl(a, r, p, l) readsl((a) + (r), p, l)
452#define SMC_outsl(a, r, p, l) writesl((a) + (r), p, l)
453
454#define RPC_LSA_DEFAULT RPC_LED_100_10
455#define RPC_LSB_DEFAULT RPC_LED_TX_RX
456
Magnus Damm3e947942008-02-22 19:55:15 +0900457#define SMC_DYNAMIC_BUS_CONFIG
Linus Torvalds1da177e2005-04-16 15:20:36 -0700458#endif
459
Russell King073ac8f2007-09-01 21:27:18 +0100460
461/* store this information for the driver.. */
462struct smc_local {
463 /*
464 * If I have to wait until memory is available to send a
465 * packet, I will store the skbuff here, until I get the
466 * desired memory. Then, I'll send it out and free it.
467 */
468 struct sk_buff *pending_tx_skb;
469 struct tasklet_struct tx_task;
470
471 /* version/revision of the SMC91x chip */
472 int version;
473
474 /* Contains the current active transmission mode */
475 int tcr_cur_mode;
476
477 /* Contains the current active receive mode */
478 int rcr_cur_mode;
479
480 /* Contains the current active receive/phy mode */
481 int rpc_cur_mode;
482 int ctl_rfduplx;
483 int ctl_rspeed;
484
485 u32 msg_enable;
486 u32 phy_type;
487 struct mii_if_info mii;
488
489 /* work queue */
490 struct work_struct phy_configure;
491 struct net_device *dev;
492 int work_pending;
493
494 spinlock_t lock;
495
496#ifdef SMC_USE_PXA_DMA
497 /* DMA needs the physical address of the chip */
498 u_long physaddr;
499 struct device *device;
500#endif
501 void __iomem *base;
502 void __iomem *datacs;
Magnus Damm3e947942008-02-22 19:55:15 +0900503
504 struct smc91x_platdata cfg;
Russell King073ac8f2007-09-01 21:27:18 +0100505};
506
Magnus Damm3e947942008-02-22 19:55:15 +0900507#ifdef SMC_DYNAMIC_BUS_CONFIG
508#define SMC_8BIT(p) (((p)->cfg.flags & SMC91X_USE_8BIT) && SMC_CAN_USE_8BIT)
509#define SMC_16BIT(p) (((p)->cfg.flags & SMC91X_USE_16BIT) && SMC_CAN_USE_16BIT)
510#define SMC_32BIT(p) (((p)->cfg.flags & SMC91X_USE_32BIT) && SMC_CAN_USE_32BIT)
511#else
512#define SMC_8BIT(p) SMC_CAN_USE_8BIT
513#define SMC_16BIT(p) SMC_CAN_USE_16BIT
514#define SMC_32BIT(p) SMC_CAN_USE_32BIT
515#endif
Russell King073ac8f2007-09-01 21:27:18 +0100516
Linus Torvalds1da177e2005-04-16 15:20:36 -0700517#ifdef SMC_USE_PXA_DMA
518/*
519 * Let's use the DMA engine on the XScale PXA2xx for RX packets. This is
520 * always happening in irq context so no need to worry about races. TX is
521 * different and probably not worth it for that reason, and not as critical
522 * as RX which can overrun memory and lose packets.
523 */
524#include <linux/dma-mapping.h>
525#include <asm/dma.h>
526#include <asm/arch/pxa-regs.h>
527
528#ifdef SMC_insl
529#undef SMC_insl
530#define SMC_insl(a, r, p, l) \
Russell King073ac8f2007-09-01 21:27:18 +0100531 smc_pxa_dma_insl(a, lp, r, dev->dma, p, l)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700532static inline void
Russell King073ac8f2007-09-01 21:27:18 +0100533smc_pxa_dma_insl(void __iomem *ioaddr, struct smc_local *lp, int reg, int dma,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700534 u_char *buf, int len)
535{
Russell King073ac8f2007-09-01 21:27:18 +0100536 u_long physaddr = lp->physaddr;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700537 dma_addr_t dmabuf;
538
539 /* fallback if no DMA available */
540 if (dma == (unsigned char)-1) {
541 readsl(ioaddr + reg, buf, len);
542 return;
543 }
544
545 /* 64 bit alignment is required for memory to memory DMA */
546 if ((long)buf & 4) {
547 *((u32 *)buf) = SMC_inl(ioaddr, reg);
548 buf += 4;
549 len--;
550 }
551
552 len *= 4;
Russell King073ac8f2007-09-01 21:27:18 +0100553 dmabuf = dma_map_single(lp->device, buf, len, DMA_FROM_DEVICE);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700554 DCSR(dma) = DCSR_NODESC;
555 DTADR(dma) = dmabuf;
556 DSADR(dma) = physaddr + reg;
557 DCMD(dma) = (DCMD_INCTRGADDR | DCMD_BURST32 |
558 DCMD_WIDTH4 | (DCMD_LENGTH & len));
559 DCSR(dma) = DCSR_NODESC | DCSR_RUN;
560 while (!(DCSR(dma) & DCSR_STOPSTATE))
561 cpu_relax();
562 DCSR(dma) = 0;
Russell King073ac8f2007-09-01 21:27:18 +0100563 dma_unmap_single(lp->device, dmabuf, len, DMA_FROM_DEVICE);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700564}
565#endif
566
567#ifdef SMC_insw
568#undef SMC_insw
569#define SMC_insw(a, r, p, l) \
Russell King073ac8f2007-09-01 21:27:18 +0100570 smc_pxa_dma_insw(a, lp, r, dev->dma, p, l)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700571static inline void
Russell King073ac8f2007-09-01 21:27:18 +0100572smc_pxa_dma_insw(void __iomem *ioaddr, struct smc_local *lp, int reg, int dma,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700573 u_char *buf, int len)
574{
Russell King073ac8f2007-09-01 21:27:18 +0100575 u_long physaddr = lp->physaddr;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700576 dma_addr_t dmabuf;
577
578 /* fallback if no DMA available */
579 if (dma == (unsigned char)-1) {
580 readsw(ioaddr + reg, buf, len);
581 return;
582 }
583
584 /* 64 bit alignment is required for memory to memory DMA */
585 while ((long)buf & 6) {
586 *((u16 *)buf) = SMC_inw(ioaddr, reg);
587 buf += 2;
588 len--;
589 }
590
591 len *= 2;
Russell King073ac8f2007-09-01 21:27:18 +0100592 dmabuf = dma_map_single(lp->device, buf, len, DMA_FROM_DEVICE);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700593 DCSR(dma) = DCSR_NODESC;
594 DTADR(dma) = dmabuf;
595 DSADR(dma) = physaddr + reg;
596 DCMD(dma) = (DCMD_INCTRGADDR | DCMD_BURST32 |
597 DCMD_WIDTH2 | (DCMD_LENGTH & len));
598 DCSR(dma) = DCSR_NODESC | DCSR_RUN;
599 while (!(DCSR(dma) & DCSR_STOPSTATE))
600 cpu_relax();
601 DCSR(dma) = 0;
Russell King073ac8f2007-09-01 21:27:18 +0100602 dma_unmap_single(lp->device, dmabuf, len, DMA_FROM_DEVICE);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700603}
604#endif
605
606static void
David Howells7d12e782006-10-05 14:55:46 +0100607smc_pxa_dma_irq(int dma, void *dummy)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700608{
609 DCSR(dma) = 0;
610}
611#endif /* SMC_USE_PXA_DMA */
612
613
Nicolas Pitre09779c62006-03-20 11:54:27 -0500614/*
615 * Everything a particular hardware setup needs should have been defined
616 * at this point. Add stubs for the undefined cases, mainly to avoid
617 * compilation warnings since they'll be optimized away, or to prevent buggy
618 * use of them.
619 */
620
621#if ! SMC_CAN_USE_32BIT
622#define SMC_inl(ioaddr, reg) ({ BUG(); 0; })
623#define SMC_outl(x, ioaddr, reg) BUG()
624#define SMC_insl(a, r, p, l) BUG()
625#define SMC_outsl(a, r, p, l) BUG()
626#endif
627
628#if !defined(SMC_insl) || !defined(SMC_outsl)
629#define SMC_insl(a, r, p, l) BUG()
630#define SMC_outsl(a, r, p, l) BUG()
631#endif
632
633#if ! SMC_CAN_USE_16BIT
634
635/*
636 * Any 16-bit access is performed with two 8-bit accesses if the hardware
637 * can't do it directly. Most registers are 16-bit so those are mandatory.
638 */
639#define SMC_outw(x, ioaddr, reg) \
640 do { \
641 unsigned int __val16 = (x); \
642 SMC_outb( __val16, ioaddr, reg ); \
643 SMC_outb( __val16 >> 8, ioaddr, reg + (1 << SMC_IO_SHIFT));\
644 } while (0)
645#define SMC_inw(ioaddr, reg) \
646 ({ \
647 unsigned int __val16; \
648 __val16 = SMC_inb( ioaddr, reg ); \
649 __val16 |= SMC_inb( ioaddr, reg + (1 << SMC_IO_SHIFT)) << 8; \
650 __val16; \
651 })
652
653#define SMC_insw(a, r, p, l) BUG()
654#define SMC_outsw(a, r, p, l) BUG()
655
656#endif
657
658#if !defined(SMC_insw) || !defined(SMC_outsw)
659#define SMC_insw(a, r, p, l) BUG()
660#define SMC_outsw(a, r, p, l) BUG()
661#endif
662
663#if ! SMC_CAN_USE_8BIT
664#define SMC_inb(ioaddr, reg) ({ BUG(); 0; })
665#define SMC_outb(x, ioaddr, reg) BUG()
666#define SMC_insb(a, r, p, l) BUG()
667#define SMC_outsb(a, r, p, l) BUG()
668#endif
669
670#if !defined(SMC_insb) || !defined(SMC_outsb)
671#define SMC_insb(a, r, p, l) BUG()
672#define SMC_outsb(a, r, p, l) BUG()
673#endif
674
675#ifndef SMC_CAN_USE_DATACS
676#define SMC_CAN_USE_DATACS 0
677#endif
678
Linus Torvalds1da177e2005-04-16 15:20:36 -0700679#ifndef SMC_IO_SHIFT
680#define SMC_IO_SHIFT 0
681#endif
Nicolas Pitre09779c62006-03-20 11:54:27 -0500682
683#ifndef SMC_IRQ_FLAGS
Thomas Gleixner1fb9df52006-07-01 19:29:39 -0700684#define SMC_IRQ_FLAGS IRQF_TRIGGER_RISING
Nicolas Pitre09779c62006-03-20 11:54:27 -0500685#endif
686
687#ifndef SMC_INTERRUPT_PREAMBLE
688#define SMC_INTERRUPT_PREAMBLE
689#endif
690
691
692/* Because of bank switching, the LAN91x uses only 16 I/O ports */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700693#define SMC_IO_EXTENT (16 << SMC_IO_SHIFT)
694#define SMC_DATA_EXTENT (4)
695
696/*
697 . Bank Select Register:
698 .
699 . yyyy yyyy 0000 00xx
700 . xx = bank number
701 . yyyy yyyy = 0x33, for identification purposes.
702*/
703#define BANK_SELECT (14 << SMC_IO_SHIFT)
704
705
706// Transmit Control Register
707/* BANK 0 */
Magnus Dammcfdfa862008-02-22 19:55:05 +0900708#define TCR_REG(lp) SMC_REG(lp, 0x0000, 0)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700709#define TCR_ENABLE 0x0001 // When 1 we can transmit
710#define TCR_LOOP 0x0002 // Controls output pin LBK
711#define TCR_FORCOL 0x0004 // When 1 will force a collision
712#define TCR_PAD_EN 0x0080 // When 1 will pad tx frames < 64 bytes w/0
713#define TCR_NOCRC 0x0100 // When 1 will not append CRC to tx frames
714#define TCR_MON_CSN 0x0400 // When 1 tx monitors carrier
715#define TCR_FDUPLX 0x0800 // When 1 enables full duplex operation
716#define TCR_STP_SQET 0x1000 // When 1 stops tx if Signal Quality Error
717#define TCR_EPH_LOOP 0x2000 // When 1 enables EPH block loopback
718#define TCR_SWFDUP 0x8000 // When 1 enables Switched Full Duplex mode
719
720#define TCR_CLEAR 0 /* do NOTHING */
721/* the default settings for the TCR register : */
722#define TCR_DEFAULT (TCR_ENABLE | TCR_PAD_EN)
723
724
725// EPH Status Register
726/* BANK 0 */
Magnus Dammcfdfa862008-02-22 19:55:05 +0900727#define EPH_STATUS_REG(lp) SMC_REG(lp, 0x0002, 0)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700728#define ES_TX_SUC 0x0001 // Last TX was successful
729#define ES_SNGL_COL 0x0002 // Single collision detected for last tx
730#define ES_MUL_COL 0x0004 // Multiple collisions detected for last tx
731#define ES_LTX_MULT 0x0008 // Last tx was a multicast
732#define ES_16COL 0x0010 // 16 Collisions Reached
733#define ES_SQET 0x0020 // Signal Quality Error Test
734#define ES_LTXBRD 0x0040 // Last tx was a broadcast
735#define ES_TXDEFR 0x0080 // Transmit Deferred
736#define ES_LATCOL 0x0200 // Late collision detected on last tx
737#define ES_LOSTCARR 0x0400 // Lost Carrier Sense
738#define ES_EXC_DEF 0x0800 // Excessive Deferral
739#define ES_CTR_ROL 0x1000 // Counter Roll Over indication
740#define ES_LINK_OK 0x4000 // Driven by inverted value of nLNK pin
741#define ES_TXUNRN 0x8000 // Tx Underrun
742
743
744// Receive Control Register
745/* BANK 0 */
Magnus Dammcfdfa862008-02-22 19:55:05 +0900746#define RCR_REG(lp) SMC_REG(lp, 0x0004, 0)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700747#define RCR_RX_ABORT 0x0001 // Set if a rx frame was aborted
748#define RCR_PRMS 0x0002 // Enable promiscuous mode
749#define RCR_ALMUL 0x0004 // When set accepts all multicast frames
750#define RCR_RXEN 0x0100 // IFF this is set, we can receive packets
751#define RCR_STRIP_CRC 0x0200 // When set strips CRC from rx packets
752#define RCR_ABORT_ENB 0x0200 // When set will abort rx on collision
753#define RCR_FILT_CAR 0x0400 // When set filters leading 12 bit s of carrier
754#define RCR_SOFTRST 0x8000 // resets the chip
755
756/* the normal settings for the RCR register : */
757#define RCR_DEFAULT (RCR_STRIP_CRC | RCR_RXEN)
758#define RCR_CLEAR 0x0 // set it to a base state
759
760
761// Counter Register
762/* BANK 0 */
Magnus Dammcfdfa862008-02-22 19:55:05 +0900763#define COUNTER_REG(lp) SMC_REG(lp, 0x0006, 0)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700764
765
766// Memory Information Register
767/* BANK 0 */
Magnus Dammcfdfa862008-02-22 19:55:05 +0900768#define MIR_REG(lp) SMC_REG(lp, 0x0008, 0)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700769
770
771// Receive/Phy Control Register
772/* BANK 0 */
Magnus Dammcfdfa862008-02-22 19:55:05 +0900773#define RPC_REG(lp) SMC_REG(lp, 0x000A, 0)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700774#define RPC_SPEED 0x2000 // When 1 PHY is in 100Mbps mode.
775#define RPC_DPLX 0x1000 // When 1 PHY is in Full-Duplex Mode
776#define RPC_ANEG 0x0800 // When 1 PHY is in Auto-Negotiate Mode
777#define RPC_LSXA_SHFT 5 // Bits to shift LS2A,LS1A,LS0A to lsb
778#define RPC_LSXB_SHFT 2 // Bits to get LS2B,LS1B,LS0B to lsb
779#define RPC_LED_100_10 (0x00) // LED = 100Mbps OR's with 10Mbps link detect
780#define RPC_LED_RES (0x01) // LED = Reserved
781#define RPC_LED_10 (0x02) // LED = 10Mbps link detect
782#define RPC_LED_FD (0x03) // LED = Full Duplex Mode
783#define RPC_LED_TX_RX (0x04) // LED = TX or RX packet occurred
784#define RPC_LED_100 (0x05) // LED = 100Mbps link dectect
785#define RPC_LED_TX (0x06) // LED = TX packet occurred
786#define RPC_LED_RX (0x07) // LED = RX packet occurred
787
788#ifndef RPC_LSA_DEFAULT
789#define RPC_LSA_DEFAULT RPC_LED_100
790#endif
791#ifndef RPC_LSB_DEFAULT
792#define RPC_LSB_DEFAULT RPC_LED_FD
793#endif
794
795#define RPC_DEFAULT (RPC_ANEG | (RPC_LSA_DEFAULT << RPC_LSXA_SHFT) | (RPC_LSB_DEFAULT << RPC_LSXB_SHFT) | RPC_SPEED | RPC_DPLX)
796
797
798/* Bank 0 0x0C is reserved */
799
800// Bank Select Register
801/* All Banks */
802#define BSR_REG 0x000E
803
804
805// Configuration Reg
806/* BANK 1 */
Magnus Dammcfdfa862008-02-22 19:55:05 +0900807#define CONFIG_REG(lp) SMC_REG(lp, 0x0000, 1)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700808#define CONFIG_EXT_PHY 0x0200 // 1=external MII, 0=internal Phy
809#define CONFIG_GPCNTRL 0x0400 // Inverse value drives pin nCNTRL
810#define CONFIG_NO_WAIT 0x1000 // When 1 no extra wait states on ISA bus
811#define CONFIG_EPH_POWER_EN 0x8000 // When 0 EPH is placed into low power mode.
812
813// Default is powered-up, Internal Phy, Wait States, and pin nCNTRL=low
814#define CONFIG_DEFAULT (CONFIG_EPH_POWER_EN)
815
816
817// Base Address Register
818/* BANK 1 */
Magnus Dammcfdfa862008-02-22 19:55:05 +0900819#define BASE_REG(lp) SMC_REG(lp, 0x0002, 1)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700820
821
822// Individual Address Registers
823/* BANK 1 */
Magnus Dammcfdfa862008-02-22 19:55:05 +0900824#define ADDR0_REG(lp) SMC_REG(lp, 0x0004, 1)
825#define ADDR1_REG(lp) SMC_REG(lp, 0x0006, 1)
826#define ADDR2_REG(lp) SMC_REG(lp, 0x0008, 1)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700827
828
829// General Purpose Register
830/* BANK 1 */
Magnus Dammcfdfa862008-02-22 19:55:05 +0900831#define GP_REG(lp) SMC_REG(lp, 0x000A, 1)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700832
833
834// Control Register
835/* BANK 1 */
Magnus Dammcfdfa862008-02-22 19:55:05 +0900836#define CTL_REG(lp) SMC_REG(lp, 0x000C, 1)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700837#define CTL_RCV_BAD 0x4000 // When 1 bad CRC packets are received
838#define CTL_AUTO_RELEASE 0x0800 // When 1 tx pages are released automatically
839#define CTL_LE_ENABLE 0x0080 // When 1 enables Link Error interrupt
840#define CTL_CR_ENABLE 0x0040 // When 1 enables Counter Rollover interrupt
841#define CTL_TE_ENABLE 0x0020 // When 1 enables Transmit Error interrupt
842#define CTL_EEPROM_SELECT 0x0004 // Controls EEPROM reload & store
843#define CTL_RELOAD 0x0002 // When set reads EEPROM into registers
844#define CTL_STORE 0x0001 // When set stores registers into EEPROM
845
846
847// MMU Command Register
848/* BANK 2 */
Magnus Dammcfdfa862008-02-22 19:55:05 +0900849#define MMU_CMD_REG(lp) SMC_REG(lp, 0x0000, 2)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700850#define MC_BUSY 1 // When 1 the last release has not completed
851#define MC_NOP (0<<5) // No Op
852#define MC_ALLOC (1<<5) // OR with number of 256 byte packets
853#define MC_RESET (2<<5) // Reset MMU to initial state
854#define MC_REMOVE (3<<5) // Remove the current rx packet
855#define MC_RELEASE (4<<5) // Remove and release the current rx packet
856#define MC_FREEPKT (5<<5) // Release packet in PNR register
857#define MC_ENQUEUE (6<<5) // Enqueue the packet for transmit
858#define MC_RSTTXFIFO (7<<5) // Reset the TX FIFOs
859
860
861// Packet Number Register
862/* BANK 2 */
Magnus Dammcfdfa862008-02-22 19:55:05 +0900863#define PN_REG(lp) SMC_REG(lp, 0x0002, 2)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700864
865
866// Allocation Result Register
867/* BANK 2 */
Magnus Dammcfdfa862008-02-22 19:55:05 +0900868#define AR_REG(lp) SMC_REG(lp, 0x0003, 2)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700869#define AR_FAILED 0x80 // Alocation Failed
870
871
872// TX FIFO Ports Register
873/* BANK 2 */
Magnus Dammcfdfa862008-02-22 19:55:05 +0900874#define TXFIFO_REG(lp) SMC_REG(lp, 0x0004, 2)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700875#define TXFIFO_TEMPTY 0x80 // TX FIFO Empty
876
877// RX FIFO Ports Register
878/* BANK 2 */
Magnus Dammcfdfa862008-02-22 19:55:05 +0900879#define RXFIFO_REG(lp) SMC_REG(lp, 0x0005, 2)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700880#define RXFIFO_REMPTY 0x80 // RX FIFO Empty
881
Magnus Dammcfdfa862008-02-22 19:55:05 +0900882#define FIFO_REG(lp) SMC_REG(lp, 0x0004, 2)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700883
884// Pointer Register
885/* BANK 2 */
Magnus Dammcfdfa862008-02-22 19:55:05 +0900886#define PTR_REG(lp) SMC_REG(lp, 0x0006, 2)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700887#define PTR_RCV 0x8000 // 1=Receive area, 0=Transmit area
888#define PTR_AUTOINC 0x4000 // Auto increment the pointer on each access
889#define PTR_READ 0x2000 // When 1 the operation is a read
890
891
892// Data Register
893/* BANK 2 */
Magnus Dammcfdfa862008-02-22 19:55:05 +0900894#define DATA_REG(lp) SMC_REG(lp, 0x0008, 2)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700895
896
897// Interrupt Status/Acknowledge Register
898/* BANK 2 */
Magnus Dammcfdfa862008-02-22 19:55:05 +0900899#define INT_REG(lp) SMC_REG(lp, 0x000C, 2)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700900
901
902// Interrupt Mask Register
903/* BANK 2 */
Magnus Dammcfdfa862008-02-22 19:55:05 +0900904#define IM_REG(lp) SMC_REG(lp, 0x000D, 2)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700905#define IM_MDINT 0x80 // PHY MI Register 18 Interrupt
906#define IM_ERCV_INT 0x40 // Early Receive Interrupt
907#define IM_EPH_INT 0x20 // Set by Ethernet Protocol Handler section
908#define IM_RX_OVRN_INT 0x10 // Set by Receiver Overruns
909#define IM_ALLOC_INT 0x08 // Set when allocation request is completed
910#define IM_TX_EMPTY_INT 0x04 // Set if the TX FIFO goes empty
911#define IM_TX_INT 0x02 // Transmit Interrupt
912#define IM_RCV_INT 0x01 // Receive Interrupt
913
914
915// Multicast Table Registers
916/* BANK 3 */
Magnus Dammcfdfa862008-02-22 19:55:05 +0900917#define MCAST_REG1(lp) SMC_REG(lp, 0x0000, 3)
918#define MCAST_REG2(lp) SMC_REG(lp, 0x0002, 3)
919#define MCAST_REG3(lp) SMC_REG(lp, 0x0004, 3)
920#define MCAST_REG4(lp) SMC_REG(lp, 0x0006, 3)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700921
922
923// Management Interface Register (MII)
924/* BANK 3 */
Magnus Dammcfdfa862008-02-22 19:55:05 +0900925#define MII_REG(lp) SMC_REG(lp, 0x0008, 3)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700926#define MII_MSK_CRS100 0x4000 // Disables CRS100 detection during tx half dup
927#define MII_MDOE 0x0008 // MII Output Enable
928#define MII_MCLK 0x0004 // MII Clock, pin MDCLK
929#define MII_MDI 0x0002 // MII Input, pin MDI
930#define MII_MDO 0x0001 // MII Output, pin MDO
931
932
933// Revision Register
934/* BANK 3 */
935/* ( hi: chip id low: rev # ) */
Magnus Dammcfdfa862008-02-22 19:55:05 +0900936#define REV_REG(lp) SMC_REG(lp, 0x000A, 3)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700937
938
939// Early RCV Register
940/* BANK 3 */
941/* this is NOT on SMC9192 */
Magnus Dammcfdfa862008-02-22 19:55:05 +0900942#define ERCV_REG(lp) SMC_REG(lp, 0x000C, 3)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700943#define ERCV_RCV_DISCRD 0x0080 // When 1 discards a packet being received
944#define ERCV_THRESHOLD 0x001F // ERCV Threshold Mask
945
946
947// External Register
948/* BANK 7 */
Magnus Dammcfdfa862008-02-22 19:55:05 +0900949#define EXT_REG(lp) SMC_REG(lp, 0x0000, 7)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700950
951
952#define CHIP_9192 3
953#define CHIP_9194 4
954#define CHIP_9195 5
955#define CHIP_9196 6
956#define CHIP_91100 7
957#define CHIP_91100FD 8
958#define CHIP_91111FD 9
959
960static const char * chip_ids[ 16 ] = {
961 NULL, NULL, NULL,
962 /* 3 */ "SMC91C90/91C92",
963 /* 4 */ "SMC91C94",
964 /* 5 */ "SMC91C95",
965 /* 6 */ "SMC91C96",
966 /* 7 */ "SMC91C100",
967 /* 8 */ "SMC91C100FD",
968 /* 9 */ "SMC91C11xFD",
969 NULL, NULL, NULL,
970 NULL, NULL, NULL};
971
972
973/*
Linus Torvalds1da177e2005-04-16 15:20:36 -0700974 . Receive status bits
975*/
976#define RS_ALGNERR 0x8000
977#define RS_BRODCAST 0x4000
978#define RS_BADCRC 0x2000
979#define RS_ODDFRAME 0x1000
980#define RS_TOOLONG 0x0800
981#define RS_TOOSHORT 0x0400
982#define RS_MULTICAST 0x0001
983#define RS_ERRORS (RS_ALGNERR | RS_BADCRC | RS_TOOLONG | RS_TOOSHORT)
984
985
986/*
987 * PHY IDs
988 * LAN83C183 == LAN91C111 Internal PHY
989 */
990#define PHY_LAN83C183 0x0016f840
991#define PHY_LAN83C180 0x02821c50
992
993/*
994 * PHY Register Addresses (LAN91C111 Internal PHY)
995 *
996 * Generic PHY registers can be found in <linux/mii.h>
997 *
998 * These phy registers are specific to our on-board phy.
999 */
1000
1001// PHY Configuration Register 1
1002#define PHY_CFG1_REG 0x10
1003#define PHY_CFG1_LNKDIS 0x8000 // 1=Rx Link Detect Function disabled
1004#define PHY_CFG1_XMTDIS 0x4000 // 1=TP Transmitter Disabled
1005#define PHY_CFG1_XMTPDN 0x2000 // 1=TP Transmitter Powered Down
1006#define PHY_CFG1_BYPSCR 0x0400 // 1=Bypass scrambler/descrambler
1007#define PHY_CFG1_UNSCDS 0x0200 // 1=Unscramble Idle Reception Disable
1008#define PHY_CFG1_EQLZR 0x0100 // 1=Rx Equalizer Disabled
1009#define PHY_CFG1_CABLE 0x0080 // 1=STP(150ohm), 0=UTP(100ohm)
1010#define PHY_CFG1_RLVL0 0x0040 // 1=Rx Squelch level reduced by 4.5db
1011#define PHY_CFG1_TLVL_SHIFT 2 // Transmit Output Level Adjust
1012#define PHY_CFG1_TLVL_MASK 0x003C
1013#define PHY_CFG1_TRF_MASK 0x0003 // Transmitter Rise/Fall time
1014
1015
1016// PHY Configuration Register 2
1017#define PHY_CFG2_REG 0x11
1018#define PHY_CFG2_APOLDIS 0x0020 // 1=Auto Polarity Correction disabled
1019#define PHY_CFG2_JABDIS 0x0010 // 1=Jabber disabled
1020#define PHY_CFG2_MREG 0x0008 // 1=Multiple register access (MII mgt)
1021#define PHY_CFG2_INTMDIO 0x0004 // 1=Interrupt signaled with MDIO pulseo
1022
1023// PHY Status Output (and Interrupt status) Register
1024#define PHY_INT_REG 0x12 // Status Output (Interrupt Status)
1025#define PHY_INT_INT 0x8000 // 1=bits have changed since last read
1026#define PHY_INT_LNKFAIL 0x4000 // 1=Link Not detected
1027#define PHY_INT_LOSSSYNC 0x2000 // 1=Descrambler has lost sync
1028#define PHY_INT_CWRD 0x1000 // 1=Invalid 4B5B code detected on rx
1029#define PHY_INT_SSD 0x0800 // 1=No Start Of Stream detected on rx
1030#define PHY_INT_ESD 0x0400 // 1=No End Of Stream detected on rx
1031#define PHY_INT_RPOL 0x0200 // 1=Reverse Polarity detected
1032#define PHY_INT_JAB 0x0100 // 1=Jabber detected
1033#define PHY_INT_SPDDET 0x0080 // 1=100Base-TX mode, 0=10Base-T mode
1034#define PHY_INT_DPLXDET 0x0040 // 1=Device in Full Duplex
1035
1036// PHY Interrupt/Status Mask Register
1037#define PHY_MASK_REG 0x13 // Interrupt Mask
1038// Uses the same bit definitions as PHY_INT_REG
1039
1040
1041/*
1042 * SMC91C96 ethernet config and status registers.
1043 * These are in the "attribute" space.
1044 */
1045#define ECOR 0x8000
1046#define ECOR_RESET 0x80
1047#define ECOR_LEVEL_IRQ 0x40
1048#define ECOR_WR_ATTRIB 0x04
1049#define ECOR_ENABLE 0x01
1050
1051#define ECSR 0x8002
1052#define ECSR_IOIS8 0x20
1053#define ECSR_PWRDWN 0x04
1054#define ECSR_INT 0x02
1055
1056#define ATTRIB_SIZE ((64*1024) << SMC_IO_SHIFT)
1057
1058
1059/*
1060 * Macros to abstract register access according to the data bus
1061 * capabilities. Please use those and not the in/out primitives.
1062 * Note: the following macros do *not* select the bank -- this must
1063 * be done separately as needed in the main code. The SMC_REG() macro
1064 * only uses the bank argument for debugging purposes (when enabled).
Nicolas Pitre09779c62006-03-20 11:54:27 -05001065 *
1066 * Note: despite inline functions being safer, everything leading to this
1067 * should preferably be macros to let BUG() display the line number in
1068 * the core source code since we're interested in the top call site
1069 * not in any inline function location.
Linus Torvalds1da177e2005-04-16 15:20:36 -07001070 */
1071
1072#if SMC_DEBUG > 0
Magnus Dammcfdfa862008-02-22 19:55:05 +09001073#define SMC_REG(lp, reg, bank) \
Linus Torvalds1da177e2005-04-16 15:20:36 -07001074 ({ \
Magnus Dammcfdfa862008-02-22 19:55:05 +09001075 int __b = SMC_CURRENT_BANK(lp); \
Linus Torvalds1da177e2005-04-16 15:20:36 -07001076 if (unlikely((__b & ~0xf0) != (0x3300 | bank))) { \
1077 printk( "%s: bank reg screwed (0x%04x)\n", \
1078 CARDNAME, __b ); \
1079 BUG(); \
1080 } \
1081 reg<<SMC_IO_SHIFT; \
1082 })
1083#else
Magnus Dammcfdfa862008-02-22 19:55:05 +09001084#define SMC_REG(lp, reg, bank) (reg<<SMC_IO_SHIFT)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001085#endif
1086
Nicolas Pitre09779c62006-03-20 11:54:27 -05001087/*
1088 * Hack Alert: Some setups just can't write 8 or 16 bits reliably when not
1089 * aligned to a 32 bit boundary. I tell you that does exist!
1090 * Fortunately the affected register accesses can be easily worked around
1091 * since we can write zeroes to the preceeding 16 bits without adverse
1092 * effects and use a 32-bit access.
1093 *
1094 * Enforce it on any 32-bit capable setup for now.
1095 */
Magnus Damm3e947942008-02-22 19:55:15 +09001096#define SMC_MUST_ALIGN_WRITE(lp) SMC_32BIT(lp)
Nicolas Pitre09779c62006-03-20 11:54:27 -05001097
Magnus Dammcfdfa862008-02-22 19:55:05 +09001098#define SMC_GET_PN(lp) \
Magnus Damm3e947942008-02-22 19:55:15 +09001099 (SMC_8BIT(lp) ? (SMC_inb(ioaddr, PN_REG(lp))) \
Magnus Dammcfdfa862008-02-22 19:55:05 +09001100 : (SMC_inw(ioaddr, PN_REG(lp)) & 0xFF))
Nicolas Pitre09779c62006-03-20 11:54:27 -05001101
Magnus Dammcfdfa862008-02-22 19:55:05 +09001102#define SMC_SET_PN(lp, x) \
Nicolas Pitre09779c62006-03-20 11:54:27 -05001103 do { \
Magnus Damm3e947942008-02-22 19:55:15 +09001104 if (SMC_MUST_ALIGN_WRITE(lp)) \
Magnus Dammcfdfa862008-02-22 19:55:05 +09001105 SMC_outl((x)<<16, ioaddr, SMC_REG(lp, 0, 2)); \
Magnus Damm3e947942008-02-22 19:55:15 +09001106 else if (SMC_8BIT(lp)) \
Magnus Dammcfdfa862008-02-22 19:55:05 +09001107 SMC_outb(x, ioaddr, PN_REG(lp)); \
Nicolas Pitre09779c62006-03-20 11:54:27 -05001108 else \
Magnus Dammcfdfa862008-02-22 19:55:05 +09001109 SMC_outw(x, ioaddr, PN_REG(lp)); \
Nicolas Pitre09779c62006-03-20 11:54:27 -05001110 } while (0)
1111
Magnus Dammcfdfa862008-02-22 19:55:05 +09001112#define SMC_GET_AR(lp) \
Magnus Damm3e947942008-02-22 19:55:15 +09001113 (SMC_8BIT(lp) ? (SMC_inb(ioaddr, AR_REG(lp))) \
Magnus Dammcfdfa862008-02-22 19:55:05 +09001114 : (SMC_inw(ioaddr, PN_REG(lp)) >> 8))
Nicolas Pitre09779c62006-03-20 11:54:27 -05001115
Magnus Dammcfdfa862008-02-22 19:55:05 +09001116#define SMC_GET_TXFIFO(lp) \
Magnus Damm3e947942008-02-22 19:55:15 +09001117 (SMC_8BIT(lp) ? (SMC_inb(ioaddr, TXFIFO_REG(lp))) \
Magnus Dammcfdfa862008-02-22 19:55:05 +09001118 : (SMC_inw(ioaddr, TXFIFO_REG(lp)) & 0xFF))
Nicolas Pitre09779c62006-03-20 11:54:27 -05001119
Magnus Dammcfdfa862008-02-22 19:55:05 +09001120#define SMC_GET_RXFIFO(lp) \
Magnus Damm3e947942008-02-22 19:55:15 +09001121 (SMC_8BIT(lp) ? (SMC_inb(ioaddr, RXFIFO_REG(lp))) \
Magnus Dammcfdfa862008-02-22 19:55:05 +09001122 : (SMC_inw(ioaddr, TXFIFO_REG(lp)) >> 8))
Nicolas Pitre09779c62006-03-20 11:54:27 -05001123
Magnus Dammcfdfa862008-02-22 19:55:05 +09001124#define SMC_GET_INT(lp) \
Magnus Damm3e947942008-02-22 19:55:15 +09001125 (SMC_8BIT(lp) ? (SMC_inb(ioaddr, INT_REG(lp))) \
Magnus Dammcfdfa862008-02-22 19:55:05 +09001126 : (SMC_inw(ioaddr, INT_REG(lp)) & 0xFF))
Nicolas Pitre09779c62006-03-20 11:54:27 -05001127
Magnus Dammcfdfa862008-02-22 19:55:05 +09001128#define SMC_ACK_INT(lp, x) \
Linus Torvalds1da177e2005-04-16 15:20:36 -07001129 do { \
Magnus Damm3e947942008-02-22 19:55:15 +09001130 if (SMC_8BIT(lp)) \
Magnus Dammcfdfa862008-02-22 19:55:05 +09001131 SMC_outb(x, ioaddr, INT_REG(lp)); \
Nicolas Pitre09779c62006-03-20 11:54:27 -05001132 else { \
1133 unsigned long __flags; \
1134 int __mask; \
1135 local_irq_save(__flags); \
Magnus Dammcfdfa862008-02-22 19:55:05 +09001136 __mask = SMC_inw(ioaddr, INT_REG(lp)) & ~0xff; \
1137 SMC_outw(__mask | (x), ioaddr, INT_REG(lp)); \
Nicolas Pitre09779c62006-03-20 11:54:27 -05001138 local_irq_restore(__flags); \
1139 } \
Linus Torvalds1da177e2005-04-16 15:20:36 -07001140 } while (0)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001141
Magnus Dammcfdfa862008-02-22 19:55:05 +09001142#define SMC_GET_INT_MASK(lp) \
Magnus Damm3e947942008-02-22 19:55:15 +09001143 (SMC_8BIT(lp) ? (SMC_inb(ioaddr, IM_REG(lp))) \
Magnus Dammcfdfa862008-02-22 19:55:05 +09001144 : (SMC_inw(ioaddr, INT_REG(lp)) >> 8))
Nicolas Pitre09779c62006-03-20 11:54:27 -05001145
Magnus Dammcfdfa862008-02-22 19:55:05 +09001146#define SMC_SET_INT_MASK(lp, x) \
Nicolas Pitre09779c62006-03-20 11:54:27 -05001147 do { \
Magnus Damm3e947942008-02-22 19:55:15 +09001148 if (SMC_8BIT(lp)) \
Magnus Dammcfdfa862008-02-22 19:55:05 +09001149 SMC_outb(x, ioaddr, IM_REG(lp)); \
Nicolas Pitre09779c62006-03-20 11:54:27 -05001150 else \
Magnus Dammcfdfa862008-02-22 19:55:05 +09001151 SMC_outw((x) << 8, ioaddr, INT_REG(lp)); \
Nicolas Pitre09779c62006-03-20 11:54:27 -05001152 } while (0)
1153
Magnus Dammcfdfa862008-02-22 19:55:05 +09001154#define SMC_CURRENT_BANK(lp) SMC_inw(ioaddr, BANK_SELECT)
Nicolas Pitre09779c62006-03-20 11:54:27 -05001155
Magnus Dammcfdfa862008-02-22 19:55:05 +09001156#define SMC_SELECT_BANK(lp, x) \
Nicolas Pitre09779c62006-03-20 11:54:27 -05001157 do { \
Magnus Damm3e947942008-02-22 19:55:15 +09001158 if (SMC_MUST_ALIGN_WRITE(lp)) \
Nicolas Pitre09779c62006-03-20 11:54:27 -05001159 SMC_outl((x)<<16, ioaddr, 12<<SMC_IO_SHIFT); \
1160 else \
1161 SMC_outw(x, ioaddr, BANK_SELECT); \
1162 } while (0)
1163
Magnus Dammcfdfa862008-02-22 19:55:05 +09001164#define SMC_GET_BASE(lp) SMC_inw(ioaddr, BASE_REG(lp))
Nicolas Pitre09779c62006-03-20 11:54:27 -05001165
Magnus Dammcfdfa862008-02-22 19:55:05 +09001166#define SMC_SET_BASE(lp, x) SMC_outw(x, ioaddr, BASE_REG(lp))
Nicolas Pitre09779c62006-03-20 11:54:27 -05001167
Magnus Dammcfdfa862008-02-22 19:55:05 +09001168#define SMC_GET_CONFIG(lp) SMC_inw(ioaddr, CONFIG_REG(lp))
Nicolas Pitre09779c62006-03-20 11:54:27 -05001169
Magnus Dammcfdfa862008-02-22 19:55:05 +09001170#define SMC_SET_CONFIG(lp, x) SMC_outw(x, ioaddr, CONFIG_REG(lp))
Nicolas Pitre09779c62006-03-20 11:54:27 -05001171
Magnus Dammcfdfa862008-02-22 19:55:05 +09001172#define SMC_GET_COUNTER(lp) SMC_inw(ioaddr, COUNTER_REG(lp))
Nicolas Pitre09779c62006-03-20 11:54:27 -05001173
Magnus Dammcfdfa862008-02-22 19:55:05 +09001174#define SMC_GET_CTL(lp) SMC_inw(ioaddr, CTL_REG(lp))
Nicolas Pitre09779c62006-03-20 11:54:27 -05001175
Magnus Dammcfdfa862008-02-22 19:55:05 +09001176#define SMC_SET_CTL(lp, x) SMC_outw(x, ioaddr, CTL_REG(lp))
Nicolas Pitre09779c62006-03-20 11:54:27 -05001177
Magnus Dammcfdfa862008-02-22 19:55:05 +09001178#define SMC_GET_MII(lp) SMC_inw(ioaddr, MII_REG(lp))
Nicolas Pitre09779c62006-03-20 11:54:27 -05001179
Magnus Dammcfdfa862008-02-22 19:55:05 +09001180#define SMC_SET_MII(lp, x) SMC_outw(x, ioaddr, MII_REG(lp))
Nicolas Pitre09779c62006-03-20 11:54:27 -05001181
Magnus Dammcfdfa862008-02-22 19:55:05 +09001182#define SMC_GET_MIR(lp) SMC_inw(ioaddr, MIR_REG(lp))
Nicolas Pitre09779c62006-03-20 11:54:27 -05001183
Magnus Dammcfdfa862008-02-22 19:55:05 +09001184#define SMC_SET_MIR(lp, x) SMC_outw(x, ioaddr, MIR_REG(lp))
Nicolas Pitre09779c62006-03-20 11:54:27 -05001185
Magnus Dammcfdfa862008-02-22 19:55:05 +09001186#define SMC_GET_MMU_CMD(lp) SMC_inw(ioaddr, MMU_CMD_REG(lp))
Nicolas Pitre09779c62006-03-20 11:54:27 -05001187
Magnus Dammcfdfa862008-02-22 19:55:05 +09001188#define SMC_SET_MMU_CMD(lp, x) SMC_outw(x, ioaddr, MMU_CMD_REG(lp))
Nicolas Pitre09779c62006-03-20 11:54:27 -05001189
Magnus Dammcfdfa862008-02-22 19:55:05 +09001190#define SMC_GET_FIFO(lp) SMC_inw(ioaddr, FIFO_REG(lp))
Nicolas Pitre09779c62006-03-20 11:54:27 -05001191
Magnus Dammcfdfa862008-02-22 19:55:05 +09001192#define SMC_GET_PTR(lp) SMC_inw(ioaddr, PTR_REG(lp))
Nicolas Pitre09779c62006-03-20 11:54:27 -05001193
Magnus Dammcfdfa862008-02-22 19:55:05 +09001194#define SMC_SET_PTR(lp, x) \
Nicolas Pitre09779c62006-03-20 11:54:27 -05001195 do { \
Magnus Damm3e947942008-02-22 19:55:15 +09001196 if (SMC_MUST_ALIGN_WRITE(lp)) \
Magnus Dammcfdfa862008-02-22 19:55:05 +09001197 SMC_outl((x)<<16, ioaddr, SMC_REG(lp, 4, 2)); \
Nicolas Pitre09779c62006-03-20 11:54:27 -05001198 else \
Magnus Dammcfdfa862008-02-22 19:55:05 +09001199 SMC_outw(x, ioaddr, PTR_REG(lp)); \
Nicolas Pitre09779c62006-03-20 11:54:27 -05001200 } while (0)
1201
Magnus Dammcfdfa862008-02-22 19:55:05 +09001202#define SMC_GET_EPH_STATUS(lp) SMC_inw(ioaddr, EPH_STATUS_REG(lp))
Nicolas Pitre09779c62006-03-20 11:54:27 -05001203
Magnus Dammcfdfa862008-02-22 19:55:05 +09001204#define SMC_GET_RCR(lp) SMC_inw(ioaddr, RCR_REG(lp))
Nicolas Pitre09779c62006-03-20 11:54:27 -05001205
Magnus Dammcfdfa862008-02-22 19:55:05 +09001206#define SMC_SET_RCR(lp, x) SMC_outw(x, ioaddr, RCR_REG(lp))
Nicolas Pitre09779c62006-03-20 11:54:27 -05001207
Magnus Dammcfdfa862008-02-22 19:55:05 +09001208#define SMC_GET_REV(lp) SMC_inw(ioaddr, REV_REG(lp))
Nicolas Pitre09779c62006-03-20 11:54:27 -05001209
Magnus Dammcfdfa862008-02-22 19:55:05 +09001210#define SMC_GET_RPC(lp) SMC_inw(ioaddr, RPC_REG(lp))
Nicolas Pitre09779c62006-03-20 11:54:27 -05001211
Magnus Dammcfdfa862008-02-22 19:55:05 +09001212#define SMC_SET_RPC(lp, x) \
Nicolas Pitre09779c62006-03-20 11:54:27 -05001213 do { \
Magnus Damm3e947942008-02-22 19:55:15 +09001214 if (SMC_MUST_ALIGN_WRITE(lp)) \
Magnus Dammcfdfa862008-02-22 19:55:05 +09001215 SMC_outl((x)<<16, ioaddr, SMC_REG(lp, 8, 0)); \
Nicolas Pitre09779c62006-03-20 11:54:27 -05001216 else \
Magnus Dammcfdfa862008-02-22 19:55:05 +09001217 SMC_outw(x, ioaddr, RPC_REG(lp)); \
Nicolas Pitre09779c62006-03-20 11:54:27 -05001218 } while (0)
1219
Magnus Dammcfdfa862008-02-22 19:55:05 +09001220#define SMC_GET_TCR(lp) SMC_inw(ioaddr, TCR_REG(lp))
Nicolas Pitre09779c62006-03-20 11:54:27 -05001221
Magnus Dammcfdfa862008-02-22 19:55:05 +09001222#define SMC_SET_TCR(lp, x) SMC_outw(x, ioaddr, TCR_REG(lp))
Linus Torvalds1da177e2005-04-16 15:20:36 -07001223
1224#ifndef SMC_GET_MAC_ADDR
Magnus Dammcfdfa862008-02-22 19:55:05 +09001225#define SMC_GET_MAC_ADDR(lp, addr) \
Linus Torvalds1da177e2005-04-16 15:20:36 -07001226 do { \
1227 unsigned int __v; \
Magnus Dammcfdfa862008-02-22 19:55:05 +09001228 __v = SMC_inw(ioaddr, ADDR0_REG(lp)); \
Linus Torvalds1da177e2005-04-16 15:20:36 -07001229 addr[0] = __v; addr[1] = __v >> 8; \
Magnus Dammcfdfa862008-02-22 19:55:05 +09001230 __v = SMC_inw(ioaddr, ADDR1_REG(lp)); \
Linus Torvalds1da177e2005-04-16 15:20:36 -07001231 addr[2] = __v; addr[3] = __v >> 8; \
Magnus Dammcfdfa862008-02-22 19:55:05 +09001232 __v = SMC_inw(ioaddr, ADDR2_REG(lp)); \
Linus Torvalds1da177e2005-04-16 15:20:36 -07001233 addr[4] = __v; addr[5] = __v >> 8; \
1234 } while (0)
1235#endif
1236
Magnus Dammcfdfa862008-02-22 19:55:05 +09001237#define SMC_SET_MAC_ADDR(lp, addr) \
Linus Torvalds1da177e2005-04-16 15:20:36 -07001238 do { \
Magnus Dammcfdfa862008-02-22 19:55:05 +09001239 SMC_outw(addr[0]|(addr[1] << 8), ioaddr, ADDR0_REG(lp)); \
1240 SMC_outw(addr[2]|(addr[3] << 8), ioaddr, ADDR1_REG(lp)); \
1241 SMC_outw(addr[4]|(addr[5] << 8), ioaddr, ADDR2_REG(lp)); \
Linus Torvalds1da177e2005-04-16 15:20:36 -07001242 } while (0)
1243
Magnus Dammcfdfa862008-02-22 19:55:05 +09001244#define SMC_SET_MCAST(lp, x) \
Linus Torvalds1da177e2005-04-16 15:20:36 -07001245 do { \
1246 const unsigned char *mt = (x); \
Magnus Dammcfdfa862008-02-22 19:55:05 +09001247 SMC_outw(mt[0] | (mt[1] << 8), ioaddr, MCAST_REG1(lp)); \
1248 SMC_outw(mt[2] | (mt[3] << 8), ioaddr, MCAST_REG2(lp)); \
1249 SMC_outw(mt[4] | (mt[5] << 8), ioaddr, MCAST_REG3(lp)); \
1250 SMC_outw(mt[6] | (mt[7] << 8), ioaddr, MCAST_REG4(lp)); \
Linus Torvalds1da177e2005-04-16 15:20:36 -07001251 } while (0)
1252
Magnus Dammcfdfa862008-02-22 19:55:05 +09001253#define SMC_PUT_PKT_HDR(lp, status, length) \
Linus Torvalds1da177e2005-04-16 15:20:36 -07001254 do { \
Magnus Damm3e947942008-02-22 19:55:15 +09001255 if (SMC_32BIT(lp)) \
Magnus Dammcfdfa862008-02-22 19:55:05 +09001256 SMC_outl((status) | (length)<<16, ioaddr, \
1257 DATA_REG(lp)); \
Nicolas Pitre09779c62006-03-20 11:54:27 -05001258 else { \
Magnus Dammcfdfa862008-02-22 19:55:05 +09001259 SMC_outw(status, ioaddr, DATA_REG(lp)); \
1260 SMC_outw(length, ioaddr, DATA_REG(lp)); \
Nicolas Pitre09779c62006-03-20 11:54:27 -05001261 } \
Linus Torvalds1da177e2005-04-16 15:20:36 -07001262 } while (0)
Nicolas Pitre09779c62006-03-20 11:54:27 -05001263
Magnus Dammcfdfa862008-02-22 19:55:05 +09001264#define SMC_GET_PKT_HDR(lp, status, length) \
Linus Torvalds1da177e2005-04-16 15:20:36 -07001265 do { \
Magnus Damm3e947942008-02-22 19:55:15 +09001266 if (SMC_32BIT(lp)) { \
Magnus Dammcfdfa862008-02-22 19:55:05 +09001267 unsigned int __val = SMC_inl(ioaddr, DATA_REG(lp)); \
Nicolas Pitre09779c62006-03-20 11:54:27 -05001268 (status) = __val & 0xffff; \
1269 (length) = __val >> 16; \
1270 } else { \
Magnus Dammcfdfa862008-02-22 19:55:05 +09001271 (status) = SMC_inw(ioaddr, DATA_REG(lp)); \
1272 (length) = SMC_inw(ioaddr, DATA_REG(lp)); \
Linus Torvalds1da177e2005-04-16 15:20:36 -07001273 } \
1274 } while (0)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001275
Magnus Dammcfdfa862008-02-22 19:55:05 +09001276#define SMC_PUSH_DATA(lp, p, l) \
Nicolas Pitre09779c62006-03-20 11:54:27 -05001277 do { \
Magnus Damm3e947942008-02-22 19:55:15 +09001278 if (SMC_32BIT(lp)) { \
Nicolas Pitre09779c62006-03-20 11:54:27 -05001279 void *__ptr = (p); \
1280 int __len = (l); \
Al Virofbd81972006-05-30 23:58:25 -04001281 void __iomem *__ioaddr = ioaddr; \
Nicolas Pitre09779c62006-03-20 11:54:27 -05001282 if (__len >= 2 && (unsigned long)__ptr & 2) { \
1283 __len -= 2; \
Magnus Dammcfdfa862008-02-22 19:55:05 +09001284 SMC_outw(*(u16 *)__ptr, ioaddr, \
1285 DATA_REG(lp)); \
Nicolas Pitre09779c62006-03-20 11:54:27 -05001286 __ptr += 2; \
1287 } \
1288 if (SMC_CAN_USE_DATACS && lp->datacs) \
1289 __ioaddr = lp->datacs; \
Magnus Dammcfdfa862008-02-22 19:55:05 +09001290 SMC_outsl(__ioaddr, DATA_REG(lp), __ptr, __len>>2); \
Nicolas Pitre09779c62006-03-20 11:54:27 -05001291 if (__len & 2) { \
1292 __ptr += (__len & ~3); \
Magnus Dammcfdfa862008-02-22 19:55:05 +09001293 SMC_outw(*((u16 *)__ptr), ioaddr, \
1294 DATA_REG(lp)); \
Nicolas Pitre09779c62006-03-20 11:54:27 -05001295 } \
Magnus Damm3e947942008-02-22 19:55:15 +09001296 } else if (SMC_16BIT(lp)) \
Magnus Dammcfdfa862008-02-22 19:55:05 +09001297 SMC_outsw(ioaddr, DATA_REG(lp), p, (l) >> 1); \
Magnus Damm3e947942008-02-22 19:55:15 +09001298 else if (SMC_8BIT(lp)) \
Magnus Dammcfdfa862008-02-22 19:55:05 +09001299 SMC_outsb(ioaddr, DATA_REG(lp), p, l); \
Nicolas Pitre09779c62006-03-20 11:54:27 -05001300 } while (0)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001301
Magnus Dammcfdfa862008-02-22 19:55:05 +09001302#define SMC_PULL_DATA(lp, p, l) \
Nicolas Pitre09779c62006-03-20 11:54:27 -05001303 do { \
Magnus Damm3e947942008-02-22 19:55:15 +09001304 if (SMC_32BIT(lp)) { \
Nicolas Pitre09779c62006-03-20 11:54:27 -05001305 void *__ptr = (p); \
1306 int __len = (l); \
Al Virofbd81972006-05-30 23:58:25 -04001307 void __iomem *__ioaddr = ioaddr; \
Nicolas Pitre09779c62006-03-20 11:54:27 -05001308 if ((unsigned long)__ptr & 2) { \
1309 /* \
1310 * We want 32bit alignment here. \
1311 * Since some buses perform a full \
1312 * 32bit fetch even for 16bit data \
1313 * we can't use SMC_inw() here. \
1314 * Back both source (on-chip) and \
1315 * destination pointers of 2 bytes. \
1316 * This is possible since the call to \
1317 * SMC_GET_PKT_HDR() already advanced \
1318 * the source pointer of 4 bytes, and \
1319 * the skb_reserve(skb, 2) advanced \
1320 * the destination pointer of 2 bytes. \
1321 */ \
1322 __ptr -= 2; \
1323 __len += 2; \
Magnus Dammcfdfa862008-02-22 19:55:05 +09001324 SMC_SET_PTR(lp, \
1325 2|PTR_READ|PTR_RCV|PTR_AUTOINC); \
Nicolas Pitre09779c62006-03-20 11:54:27 -05001326 } \
1327 if (SMC_CAN_USE_DATACS && lp->datacs) \
1328 __ioaddr = lp->datacs; \
Linus Torvalds1da177e2005-04-16 15:20:36 -07001329 __len += 2; \
Magnus Dammcfdfa862008-02-22 19:55:05 +09001330 SMC_insl(__ioaddr, DATA_REG(lp), __ptr, __len>>2); \
Magnus Damm3e947942008-02-22 19:55:15 +09001331 } else if (SMC_16BIT(lp)) \
Magnus Dammcfdfa862008-02-22 19:55:05 +09001332 SMC_insw(ioaddr, DATA_REG(lp), p, (l) >> 1); \
Magnus Damm3e947942008-02-22 19:55:15 +09001333 else if (SMC_8BIT(lp)) \
Magnus Dammcfdfa862008-02-22 19:55:05 +09001334 SMC_insb(ioaddr, DATA_REG(lp), p, l); \
Nicolas Pitre09779c62006-03-20 11:54:27 -05001335 } while (0)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001336
1337#endif /* _SMC91X_H_ */