Jingoo Han | 340cba6 | 2013-06-21 16:24:54 +0900 | [diff] [blame] | 1 | /* |
Jingoo Han | 4b1ced8 | 2013-07-31 17:14:10 +0900 | [diff] [blame] | 2 | * Synopsys Designware PCIe host controller driver |
Jingoo Han | 340cba6 | 2013-06-21 16:24:54 +0900 | [diff] [blame] | 3 | * |
| 4 | * Copyright (C) 2013 Samsung Electronics Co., Ltd. |
| 5 | * http://www.samsung.com |
| 6 | * |
| 7 | * Author: Jingoo Han <jg1.han@samsung.com> |
| 8 | * |
| 9 | * This program is free software; you can redistribute it and/or modify |
| 10 | * it under the terms of the GNU General Public License version 2 as |
| 11 | * published by the Free Software Foundation. |
| 12 | */ |
| 13 | |
Jingoo Han | f342d94 | 2013-09-06 15:54:59 +0900 | [diff] [blame] | 14 | #include <linux/irq.h> |
| 15 | #include <linux/irqdomain.h> |
Jingoo Han | 340cba6 | 2013-06-21 16:24:54 +0900 | [diff] [blame] | 16 | #include <linux/kernel.h> |
Jingoo Han | 340cba6 | 2013-06-21 16:24:54 +0900 | [diff] [blame] | 17 | #include <linux/module.h> |
Jingoo Han | f342d94 | 2013-09-06 15:54:59 +0900 | [diff] [blame] | 18 | #include <linux/msi.h> |
Jingoo Han | 340cba6 | 2013-06-21 16:24:54 +0900 | [diff] [blame] | 19 | #include <linux/of_address.h> |
Lucas Stach | 804f57b | 2014-03-05 14:25:51 +0100 | [diff] [blame] | 20 | #include <linux/of_pci.h> |
Jingoo Han | 340cba6 | 2013-06-21 16:24:54 +0900 | [diff] [blame] | 21 | #include <linux/pci.h> |
| 22 | #include <linux/pci_regs.h> |
Kishon Vijay Abraham I | 4dd964d | 2014-07-17 14:30:40 +0530 | [diff] [blame] | 23 | #include <linux/platform_device.h> |
Jingoo Han | 340cba6 | 2013-06-21 16:24:54 +0900 | [diff] [blame] | 24 | #include <linux/types.h> |
| 25 | |
Jingoo Han | 4b1ced8 | 2013-07-31 17:14:10 +0900 | [diff] [blame] | 26 | #include "pcie-designware.h" |
Jingoo Han | 340cba6 | 2013-06-21 16:24:54 +0900 | [diff] [blame] | 27 | |
| 28 | /* Synopsis specific PCIE configuration registers */ |
| 29 | #define PCIE_PORT_LINK_CONTROL 0x710 |
| 30 | #define PORT_LINK_MODE_MASK (0x3f << 16) |
Jingoo Han | 4b1ced8 | 2013-07-31 17:14:10 +0900 | [diff] [blame] | 31 | #define PORT_LINK_MODE_1_LANES (0x1 << 16) |
| 32 | #define PORT_LINK_MODE_2_LANES (0x3 << 16) |
Jingoo Han | 340cba6 | 2013-06-21 16:24:54 +0900 | [diff] [blame] | 33 | #define PORT_LINK_MODE_4_LANES (0x7 << 16) |
Zhou Wang | 5b0f073 | 2015-05-13 14:44:34 +0800 | [diff] [blame] | 34 | #define PORT_LINK_MODE_8_LANES (0xf << 16) |
Jingoo Han | 340cba6 | 2013-06-21 16:24:54 +0900 | [diff] [blame] | 35 | |
| 36 | #define PCIE_LINK_WIDTH_SPEED_CONTROL 0x80C |
| 37 | #define PORT_LOGIC_SPEED_CHANGE (0x1 << 17) |
Zhou Wang | ed8b472 | 2015-08-26 11:17:34 +0800 | [diff] [blame] | 38 | #define PORT_LOGIC_LINK_WIDTH_MASK (0x1f << 8) |
Jingoo Han | 4b1ced8 | 2013-07-31 17:14:10 +0900 | [diff] [blame] | 39 | #define PORT_LOGIC_LINK_WIDTH_1_LANES (0x1 << 8) |
| 40 | #define PORT_LOGIC_LINK_WIDTH_2_LANES (0x2 << 8) |
| 41 | #define PORT_LOGIC_LINK_WIDTH_4_LANES (0x4 << 8) |
Zhou Wang | 5b0f073 | 2015-05-13 14:44:34 +0800 | [diff] [blame] | 42 | #define PORT_LOGIC_LINK_WIDTH_8_LANES (0x8 << 8) |
Jingoo Han | 340cba6 | 2013-06-21 16:24:54 +0900 | [diff] [blame] | 43 | |
| 44 | #define PCIE_MSI_ADDR_LO 0x820 |
| 45 | #define PCIE_MSI_ADDR_HI 0x824 |
| 46 | #define PCIE_MSI_INTR0_ENABLE 0x828 |
| 47 | #define PCIE_MSI_INTR0_MASK 0x82C |
| 48 | #define PCIE_MSI_INTR0_STATUS 0x830 |
| 49 | |
| 50 | #define PCIE_ATU_VIEWPORT 0x900 |
| 51 | #define PCIE_ATU_REGION_INBOUND (0x1 << 31) |
| 52 | #define PCIE_ATU_REGION_OUTBOUND (0x0 << 31) |
| 53 | #define PCIE_ATU_REGION_INDEX1 (0x1 << 0) |
| 54 | #define PCIE_ATU_REGION_INDEX0 (0x0 << 0) |
| 55 | #define PCIE_ATU_CR1 0x904 |
| 56 | #define PCIE_ATU_TYPE_MEM (0x0 << 0) |
| 57 | #define PCIE_ATU_TYPE_IO (0x2 << 0) |
| 58 | #define PCIE_ATU_TYPE_CFG0 (0x4 << 0) |
| 59 | #define PCIE_ATU_TYPE_CFG1 (0x5 << 0) |
| 60 | #define PCIE_ATU_CR2 0x908 |
| 61 | #define PCIE_ATU_ENABLE (0x1 << 31) |
| 62 | #define PCIE_ATU_BAR_MODE_ENABLE (0x1 << 30) |
| 63 | #define PCIE_ATU_LOWER_BASE 0x90C |
| 64 | #define PCIE_ATU_UPPER_BASE 0x910 |
| 65 | #define PCIE_ATU_LIMIT 0x914 |
| 66 | #define PCIE_ATU_LOWER_TARGET 0x918 |
| 67 | #define PCIE_ATU_BUS(x) (((x) & 0xff) << 24) |
| 68 | #define PCIE_ATU_DEV(x) (((x) & 0x1f) << 19) |
| 69 | #define PCIE_ATU_FUNC(x) (((x) & 0x7) << 16) |
| 70 | #define PCIE_ATU_UPPER_TARGET 0x91C |
| 71 | |
Jingoo Han | 4b1ced8 | 2013-07-31 17:14:10 +0900 | [diff] [blame] | 72 | static struct hw_pci dw_pci; |
Jingoo Han | 340cba6 | 2013-06-21 16:24:54 +0900 | [diff] [blame] | 73 | |
Bjorn Helgaas | 73e4085 | 2013-10-09 09:12:37 -0600 | [diff] [blame] | 74 | static unsigned long global_io_offset; |
Jingoo Han | 340cba6 | 2013-06-21 16:24:54 +0900 | [diff] [blame] | 75 | |
| 76 | static inline struct pcie_port *sys_to_pcie(struct pci_sys_data *sys) |
| 77 | { |
Lucas Stach | 84a263f | 2014-09-05 09:37:55 -0600 | [diff] [blame] | 78 | BUG_ON(!sys->private_data); |
| 79 | |
Jingoo Han | 340cba6 | 2013-06-21 16:24:54 +0900 | [diff] [blame] | 80 | return sys->private_data; |
| 81 | } |
| 82 | |
Gabriele Paoloni | 4c45852 | 2015-10-08 14:27:48 -0500 | [diff] [blame] | 83 | int dw_pcie_cfg_read(void __iomem *addr, int size, u32 *val) |
Jingoo Han | 340cba6 | 2013-06-21 16:24:54 +0900 | [diff] [blame] | 84 | { |
Gabriele Paoloni | b6b18f5 | 2015-10-08 14:27:53 -0500 | [diff] [blame^] | 85 | if ((uintptr_t)addr & (size - 1)) { |
| 86 | *val = 0; |
| 87 | return PCIBIOS_BAD_REGISTER_NUMBER; |
| 88 | } |
| 89 | |
Gabriele Paoloni | c003ca9 | 2015-10-08 14:27:43 -0500 | [diff] [blame] | 90 | if (size == 4) |
| 91 | *val = readl(addr); |
Jingoo Han | 340cba6 | 2013-06-21 16:24:54 +0900 | [diff] [blame] | 92 | else if (size == 2) |
Gabriele Paoloni | 4c45852 | 2015-10-08 14:27:48 -0500 | [diff] [blame] | 93 | *val = readw(addr); |
Gabriele Paoloni | c003ca9 | 2015-10-08 14:27:43 -0500 | [diff] [blame] | 94 | else if (size == 1) |
Gabriele Paoloni | 4c45852 | 2015-10-08 14:27:48 -0500 | [diff] [blame] | 95 | *val = readb(addr); |
Gabriele Paoloni | c003ca9 | 2015-10-08 14:27:43 -0500 | [diff] [blame] | 96 | else { |
| 97 | *val = 0; |
Jingoo Han | 340cba6 | 2013-06-21 16:24:54 +0900 | [diff] [blame] | 98 | return PCIBIOS_BAD_REGISTER_NUMBER; |
Gabriele Paoloni | c003ca9 | 2015-10-08 14:27:43 -0500 | [diff] [blame] | 99 | } |
Jingoo Han | 340cba6 | 2013-06-21 16:24:54 +0900 | [diff] [blame] | 100 | |
| 101 | return PCIBIOS_SUCCESSFUL; |
| 102 | } |
| 103 | |
Gabriele Paoloni | 4c45852 | 2015-10-08 14:27:48 -0500 | [diff] [blame] | 104 | int dw_pcie_cfg_write(void __iomem *addr, int size, u32 val) |
Jingoo Han | 340cba6 | 2013-06-21 16:24:54 +0900 | [diff] [blame] | 105 | { |
Gabriele Paoloni | b6b18f5 | 2015-10-08 14:27:53 -0500 | [diff] [blame^] | 106 | if ((uintptr_t)addr & (size - 1)) |
| 107 | return PCIBIOS_BAD_REGISTER_NUMBER; |
| 108 | |
Jingoo Han | 340cba6 | 2013-06-21 16:24:54 +0900 | [diff] [blame] | 109 | if (size == 4) |
| 110 | writel(val, addr); |
| 111 | else if (size == 2) |
Gabriele Paoloni | 4c45852 | 2015-10-08 14:27:48 -0500 | [diff] [blame] | 112 | writew(val, addr); |
Jingoo Han | 340cba6 | 2013-06-21 16:24:54 +0900 | [diff] [blame] | 113 | else if (size == 1) |
Gabriele Paoloni | 4c45852 | 2015-10-08 14:27:48 -0500 | [diff] [blame] | 114 | writeb(val, addr); |
Jingoo Han | 340cba6 | 2013-06-21 16:24:54 +0900 | [diff] [blame] | 115 | else |
| 116 | return PCIBIOS_BAD_REGISTER_NUMBER; |
| 117 | |
| 118 | return PCIBIOS_SUCCESSFUL; |
| 119 | } |
| 120 | |
Seungwon Jeon | f7b7868 | 2013-08-28 20:53:30 +0900 | [diff] [blame] | 121 | static inline void dw_pcie_readl_rc(struct pcie_port *pp, u32 reg, u32 *val) |
Jingoo Han | 340cba6 | 2013-06-21 16:24:54 +0900 | [diff] [blame] | 122 | { |
Jingoo Han | 4b1ced8 | 2013-07-31 17:14:10 +0900 | [diff] [blame] | 123 | if (pp->ops->readl_rc) |
Seungwon Jeon | f7b7868 | 2013-08-28 20:53:30 +0900 | [diff] [blame] | 124 | pp->ops->readl_rc(pp, pp->dbi_base + reg, val); |
Jingoo Han | 4b1ced8 | 2013-07-31 17:14:10 +0900 | [diff] [blame] | 125 | else |
Seungwon Jeon | f7b7868 | 2013-08-28 20:53:30 +0900 | [diff] [blame] | 126 | *val = readl(pp->dbi_base + reg); |
Jingoo Han | 340cba6 | 2013-06-21 16:24:54 +0900 | [diff] [blame] | 127 | } |
| 128 | |
Seungwon Jeon | f7b7868 | 2013-08-28 20:53:30 +0900 | [diff] [blame] | 129 | static inline void dw_pcie_writel_rc(struct pcie_port *pp, u32 val, u32 reg) |
Jingoo Han | 340cba6 | 2013-06-21 16:24:54 +0900 | [diff] [blame] | 130 | { |
Jingoo Han | 4b1ced8 | 2013-07-31 17:14:10 +0900 | [diff] [blame] | 131 | if (pp->ops->writel_rc) |
Seungwon Jeon | f7b7868 | 2013-08-28 20:53:30 +0900 | [diff] [blame] | 132 | pp->ops->writel_rc(pp, val, pp->dbi_base + reg); |
Jingoo Han | 4b1ced8 | 2013-07-31 17:14:10 +0900 | [diff] [blame] | 133 | else |
Seungwon Jeon | f7b7868 | 2013-08-28 20:53:30 +0900 | [diff] [blame] | 134 | writel(val, pp->dbi_base + reg); |
Jingoo Han | 340cba6 | 2013-06-21 16:24:54 +0900 | [diff] [blame] | 135 | } |
| 136 | |
Bjorn Helgaas | 73e4085 | 2013-10-09 09:12:37 -0600 | [diff] [blame] | 137 | static int dw_pcie_rd_own_conf(struct pcie_port *pp, int where, int size, |
| 138 | u32 *val) |
Jingoo Han | 340cba6 | 2013-06-21 16:24:54 +0900 | [diff] [blame] | 139 | { |
| 140 | int ret; |
| 141 | |
Jingoo Han | 4b1ced8 | 2013-07-31 17:14:10 +0900 | [diff] [blame] | 142 | if (pp->ops->rd_own_conf) |
| 143 | ret = pp->ops->rd_own_conf(pp, where, size, val); |
| 144 | else |
Gabriele Paoloni | 4c45852 | 2015-10-08 14:27:48 -0500 | [diff] [blame] | 145 | ret = dw_pcie_cfg_read(pp->dbi_base + where, size, val); |
Jingoo Han | 4b1ced8 | 2013-07-31 17:14:10 +0900 | [diff] [blame] | 146 | |
Jingoo Han | 340cba6 | 2013-06-21 16:24:54 +0900 | [diff] [blame] | 147 | return ret; |
| 148 | } |
| 149 | |
Bjorn Helgaas | 73e4085 | 2013-10-09 09:12:37 -0600 | [diff] [blame] | 150 | static int dw_pcie_wr_own_conf(struct pcie_port *pp, int where, int size, |
| 151 | u32 val) |
Jingoo Han | 340cba6 | 2013-06-21 16:24:54 +0900 | [diff] [blame] | 152 | { |
| 153 | int ret; |
| 154 | |
Jingoo Han | 4b1ced8 | 2013-07-31 17:14:10 +0900 | [diff] [blame] | 155 | if (pp->ops->wr_own_conf) |
| 156 | ret = pp->ops->wr_own_conf(pp, where, size, val); |
Jingoo Han | 340cba6 | 2013-06-21 16:24:54 +0900 | [diff] [blame] | 157 | else |
Gabriele Paoloni | 4c45852 | 2015-10-08 14:27:48 -0500 | [diff] [blame] | 158 | ret = dw_pcie_cfg_write(pp->dbi_base + where, size, val); |
Jingoo Han | 340cba6 | 2013-06-21 16:24:54 +0900 | [diff] [blame] | 159 | |
| 160 | return ret; |
| 161 | } |
| 162 | |
Jisheng Zhang | 63503c8 | 2015-04-30 16:22:28 +0800 | [diff] [blame] | 163 | static void dw_pcie_prog_outbound_atu(struct pcie_port *pp, int index, |
| 164 | int type, u64 cpu_addr, u64 pci_addr, u32 size) |
| 165 | { |
| 166 | dw_pcie_writel_rc(pp, PCIE_ATU_REGION_OUTBOUND | index, |
| 167 | PCIE_ATU_VIEWPORT); |
| 168 | dw_pcie_writel_rc(pp, lower_32_bits(cpu_addr), PCIE_ATU_LOWER_BASE); |
| 169 | dw_pcie_writel_rc(pp, upper_32_bits(cpu_addr), PCIE_ATU_UPPER_BASE); |
| 170 | dw_pcie_writel_rc(pp, lower_32_bits(cpu_addr + size - 1), |
| 171 | PCIE_ATU_LIMIT); |
| 172 | dw_pcie_writel_rc(pp, lower_32_bits(pci_addr), PCIE_ATU_LOWER_TARGET); |
| 173 | dw_pcie_writel_rc(pp, upper_32_bits(pci_addr), PCIE_ATU_UPPER_TARGET); |
| 174 | dw_pcie_writel_rc(pp, type, PCIE_ATU_CR1); |
| 175 | dw_pcie_writel_rc(pp, PCIE_ATU_ENABLE, PCIE_ATU_CR2); |
| 176 | } |
| 177 | |
Jingoo Han | f342d94 | 2013-09-06 15:54:59 +0900 | [diff] [blame] | 178 | static struct irq_chip dw_msi_irq_chip = { |
| 179 | .name = "PCI-MSI", |
Thomas Gleixner | 280510f | 2014-11-23 12:23:20 +0100 | [diff] [blame] | 180 | .irq_enable = pci_msi_unmask_irq, |
| 181 | .irq_disable = pci_msi_mask_irq, |
| 182 | .irq_mask = pci_msi_mask_irq, |
| 183 | .irq_unmask = pci_msi_unmask_irq, |
Jingoo Han | f342d94 | 2013-09-06 15:54:59 +0900 | [diff] [blame] | 184 | }; |
| 185 | |
| 186 | /* MSI int handler */ |
Lucas Stach | 7f4f16e | 2014-03-28 17:52:58 +0100 | [diff] [blame] | 187 | irqreturn_t dw_handle_msi_irq(struct pcie_port *pp) |
Jingoo Han | f342d94 | 2013-09-06 15:54:59 +0900 | [diff] [blame] | 188 | { |
| 189 | unsigned long val; |
Pratyush Anand | 904d0e7 | 2013-10-09 21:32:12 +0900 | [diff] [blame] | 190 | int i, pos, irq; |
Lucas Stach | 7f4f16e | 2014-03-28 17:52:58 +0100 | [diff] [blame] | 191 | irqreturn_t ret = IRQ_NONE; |
Jingoo Han | f342d94 | 2013-09-06 15:54:59 +0900 | [diff] [blame] | 192 | |
| 193 | for (i = 0; i < MAX_MSI_CTRLS; i++) { |
| 194 | dw_pcie_rd_own_conf(pp, PCIE_MSI_INTR0_STATUS + i * 12, 4, |
| 195 | (u32 *)&val); |
| 196 | if (val) { |
Lucas Stach | 7f4f16e | 2014-03-28 17:52:58 +0100 | [diff] [blame] | 197 | ret = IRQ_HANDLED; |
Jingoo Han | f342d94 | 2013-09-06 15:54:59 +0900 | [diff] [blame] | 198 | pos = 0; |
| 199 | while ((pos = find_next_bit(&val, 32, pos)) != 32) { |
Pratyush Anand | 904d0e7 | 2013-10-09 21:32:12 +0900 | [diff] [blame] | 200 | irq = irq_find_mapping(pp->irq_domain, |
| 201 | i * 32 + pos); |
Harro Haan | ca16589 | 2013-12-12 19:29:03 +0100 | [diff] [blame] | 202 | dw_pcie_wr_own_conf(pp, |
| 203 | PCIE_MSI_INTR0_STATUS + i * 12, |
| 204 | 4, 1 << pos); |
Pratyush Anand | 904d0e7 | 2013-10-09 21:32:12 +0900 | [diff] [blame] | 205 | generic_handle_irq(irq); |
Jingoo Han | f342d94 | 2013-09-06 15:54:59 +0900 | [diff] [blame] | 206 | pos++; |
| 207 | } |
| 208 | } |
Jingoo Han | f342d94 | 2013-09-06 15:54:59 +0900 | [diff] [blame] | 209 | } |
Lucas Stach | 7f4f16e | 2014-03-28 17:52:58 +0100 | [diff] [blame] | 210 | |
| 211 | return ret; |
Jingoo Han | f342d94 | 2013-09-06 15:54:59 +0900 | [diff] [blame] | 212 | } |
| 213 | |
| 214 | void dw_pcie_msi_init(struct pcie_port *pp) |
| 215 | { |
Lucas Stach | c8947fb | 2015-09-18 13:58:35 -0500 | [diff] [blame] | 216 | u64 msi_target; |
| 217 | |
Jingoo Han | f342d94 | 2013-09-06 15:54:59 +0900 | [diff] [blame] | 218 | pp->msi_data = __get_free_pages(GFP_KERNEL, 0); |
Lucas Stach | c8947fb | 2015-09-18 13:58:35 -0500 | [diff] [blame] | 219 | msi_target = virt_to_phys((void *)pp->msi_data); |
Jingoo Han | f342d94 | 2013-09-06 15:54:59 +0900 | [diff] [blame] | 220 | |
| 221 | /* program the msi_data */ |
| 222 | dw_pcie_wr_own_conf(pp, PCIE_MSI_ADDR_LO, 4, |
Lucas Stach | c8947fb | 2015-09-18 13:58:35 -0500 | [diff] [blame] | 223 | (u32)(msi_target & 0xffffffff)); |
| 224 | dw_pcie_wr_own_conf(pp, PCIE_MSI_ADDR_HI, 4, |
| 225 | (u32)(msi_target >> 32 & 0xffffffff)); |
Jingoo Han | f342d94 | 2013-09-06 15:54:59 +0900 | [diff] [blame] | 226 | } |
| 227 | |
Murali Karicheri | 2f37c5a | 2014-07-21 12:58:42 -0400 | [diff] [blame] | 228 | static void dw_pcie_msi_clear_irq(struct pcie_port *pp, int irq) |
| 229 | { |
| 230 | unsigned int res, bit, val; |
| 231 | |
| 232 | res = (irq / 32) * 12; |
| 233 | bit = irq % 32; |
| 234 | dw_pcie_rd_own_conf(pp, PCIE_MSI_INTR0_ENABLE + res, 4, &val); |
| 235 | val &= ~(1 << bit); |
| 236 | dw_pcie_wr_own_conf(pp, PCIE_MSI_INTR0_ENABLE + res, 4, val); |
| 237 | } |
| 238 | |
Bjørn Erik Nilsen | be3f48c | 2013-11-29 14:35:24 +0100 | [diff] [blame] | 239 | static void clear_irq_range(struct pcie_port *pp, unsigned int irq_base, |
Jingoo Han | 58275f2f | 2013-12-27 09:30:25 +0900 | [diff] [blame] | 240 | unsigned int nvec, unsigned int pos) |
Bjørn Erik Nilsen | be3f48c | 2013-11-29 14:35:24 +0100 | [diff] [blame] | 241 | { |
Murali Karicheri | 2f37c5a | 2014-07-21 12:58:42 -0400 | [diff] [blame] | 242 | unsigned int i; |
Bjørn Erik Nilsen | be3f48c | 2013-11-29 14:35:24 +0100 | [diff] [blame] | 243 | |
Bjorn Helgaas | 0b8cfb6 | 2013-12-09 15:11:25 -0700 | [diff] [blame] | 244 | for (i = 0; i < nvec; i++) { |
Bjørn Erik Nilsen | be3f48c | 2013-11-29 14:35:24 +0100 | [diff] [blame] | 245 | irq_set_msi_desc_off(irq_base, i, NULL); |
Jingoo Han | 58275f2f | 2013-12-27 09:30:25 +0900 | [diff] [blame] | 246 | /* Disable corresponding interrupt on MSI controller */ |
Murali Karicheri | 2f37c5a | 2014-07-21 12:58:42 -0400 | [diff] [blame] | 247 | if (pp->ops->msi_clear_irq) |
| 248 | pp->ops->msi_clear_irq(pp, pos + i); |
| 249 | else |
| 250 | dw_pcie_msi_clear_irq(pp, pos + i); |
Bjørn Erik Nilsen | be3f48c | 2013-11-29 14:35:24 +0100 | [diff] [blame] | 251 | } |
Lucas Stach | c8df6ac | 2014-09-30 18:36:27 +0200 | [diff] [blame] | 252 | |
| 253 | bitmap_release_region(pp->msi_irq_in_use, pos, order_base_2(nvec)); |
Bjørn Erik Nilsen | be3f48c | 2013-11-29 14:35:24 +0100 | [diff] [blame] | 254 | } |
| 255 | |
Murali Karicheri | 2f37c5a | 2014-07-21 12:58:42 -0400 | [diff] [blame] | 256 | static void dw_pcie_msi_set_irq(struct pcie_port *pp, int irq) |
| 257 | { |
| 258 | unsigned int res, bit, val; |
| 259 | |
| 260 | res = (irq / 32) * 12; |
| 261 | bit = irq % 32; |
| 262 | dw_pcie_rd_own_conf(pp, PCIE_MSI_INTR0_ENABLE + res, 4, &val); |
| 263 | val |= 1 << bit; |
| 264 | dw_pcie_wr_own_conf(pp, PCIE_MSI_INTR0_ENABLE + res, 4, val); |
| 265 | } |
| 266 | |
Jingoo Han | f342d94 | 2013-09-06 15:54:59 +0900 | [diff] [blame] | 267 | static int assign_irq(int no_irqs, struct msi_desc *desc, int *pos) |
| 268 | { |
Lucas Stach | c8df6ac | 2014-09-30 18:36:27 +0200 | [diff] [blame] | 269 | int irq, pos0, i; |
Jiang Liu | e39758e | 2015-07-09 16:00:43 +0800 | [diff] [blame] | 270 | struct pcie_port *pp = sys_to_pcie(msi_desc_to_pci_sysdata(desc)); |
Jingoo Han | f342d94 | 2013-09-06 15:54:59 +0900 | [diff] [blame] | 271 | |
Lucas Stach | c8df6ac | 2014-09-30 18:36:27 +0200 | [diff] [blame] | 272 | pos0 = bitmap_find_free_region(pp->msi_irq_in_use, MAX_MSI_IRQS, |
| 273 | order_base_2(no_irqs)); |
| 274 | if (pos0 < 0) |
| 275 | goto no_valid_irq; |
Jingoo Han | f342d94 | 2013-09-06 15:54:59 +0900 | [diff] [blame] | 276 | |
Pratyush Anand | 904d0e7 | 2013-10-09 21:32:12 +0900 | [diff] [blame] | 277 | irq = irq_find_mapping(pp->irq_domain, pos0); |
| 278 | if (!irq) |
Jingoo Han | f342d94 | 2013-09-06 15:54:59 +0900 | [diff] [blame] | 279 | goto no_valid_irq; |
| 280 | |
Bjørn Erik Nilsen | be3f48c | 2013-11-29 14:35:24 +0100 | [diff] [blame] | 281 | /* |
| 282 | * irq_create_mapping (called from dw_pcie_host_init) pre-allocates |
| 283 | * descs so there is no need to allocate descs here. We can therefore |
| 284 | * assume that if irq_find_mapping above returns non-zero, then the |
| 285 | * descs are also successfully allocated. |
| 286 | */ |
| 287 | |
Bjorn Helgaas | 0b8cfb6 | 2013-12-09 15:11:25 -0700 | [diff] [blame] | 288 | for (i = 0; i < no_irqs; i++) { |
Bjørn Erik Nilsen | be3f48c | 2013-11-29 14:35:24 +0100 | [diff] [blame] | 289 | if (irq_set_msi_desc_off(irq, i, desc) != 0) { |
| 290 | clear_irq_range(pp, irq, i, pos0); |
| 291 | goto no_valid_irq; |
| 292 | } |
Jingoo Han | f342d94 | 2013-09-06 15:54:59 +0900 | [diff] [blame] | 293 | /*Enable corresponding interrupt in MSI interrupt controller */ |
Murali Karicheri | 2f37c5a | 2014-07-21 12:58:42 -0400 | [diff] [blame] | 294 | if (pp->ops->msi_set_irq) |
| 295 | pp->ops->msi_set_irq(pp, pos0 + i); |
| 296 | else |
| 297 | dw_pcie_msi_set_irq(pp, pos0 + i); |
Jingoo Han | f342d94 | 2013-09-06 15:54:59 +0900 | [diff] [blame] | 298 | } |
| 299 | |
| 300 | *pos = pos0; |
Lucas Stach | 7970737 | 2015-09-18 13:58:35 -0500 | [diff] [blame] | 301 | desc->nvec_used = no_irqs; |
| 302 | desc->msi_attrib.multiple = order_base_2(no_irqs); |
| 303 | |
Jingoo Han | f342d94 | 2013-09-06 15:54:59 +0900 | [diff] [blame] | 304 | return irq; |
| 305 | |
| 306 | no_valid_irq: |
| 307 | *pos = pos0; |
| 308 | return -ENOSPC; |
| 309 | } |
| 310 | |
Lucas Stach | ea643e1 | 2015-09-18 13:58:35 -0500 | [diff] [blame] | 311 | static void dw_msi_setup_msg(struct pcie_port *pp, unsigned int irq, u32 pos) |
Jingoo Han | f342d94 | 2013-09-06 15:54:59 +0900 | [diff] [blame] | 312 | { |
Jingoo Han | f342d94 | 2013-09-06 15:54:59 +0900 | [diff] [blame] | 313 | struct msi_msg msg; |
Lucas Stach | c8947fb | 2015-09-18 13:58:35 -0500 | [diff] [blame] | 314 | u64 msi_target; |
Jingoo Han | f342d94 | 2013-09-06 15:54:59 +0900 | [diff] [blame] | 315 | |
Minghuan Lian | 450e344 | 2014-09-23 22:28:58 +0800 | [diff] [blame] | 316 | if (pp->ops->get_msi_addr) |
Lucas Stach | c8947fb | 2015-09-18 13:58:35 -0500 | [diff] [blame] | 317 | msi_target = pp->ops->get_msi_addr(pp); |
Murali Karicheri | 2f37c5a | 2014-07-21 12:58:42 -0400 | [diff] [blame] | 318 | else |
Lucas Stach | c8947fb | 2015-09-18 13:58:35 -0500 | [diff] [blame] | 319 | msi_target = virt_to_phys((void *)pp->msi_data); |
| 320 | |
| 321 | msg.address_lo = (u32)(msi_target & 0xffffffff); |
| 322 | msg.address_hi = (u32)(msi_target >> 32 & 0xffffffff); |
Minghuan Lian | 24832b4 | 2014-09-23 22:28:59 +0800 | [diff] [blame] | 323 | |
| 324 | if (pp->ops->get_msi_data) |
| 325 | msg.data = pp->ops->get_msi_data(pp, pos); |
| 326 | else |
| 327 | msg.data = pos; |
| 328 | |
Jiang Liu | 83a1891 | 2014-11-09 23:10:34 +0800 | [diff] [blame] | 329 | pci_write_msi_msg(irq, &msg); |
Lucas Stach | ea643e1 | 2015-09-18 13:58:35 -0500 | [diff] [blame] | 330 | } |
| 331 | |
| 332 | static int dw_msi_setup_irq(struct msi_controller *chip, struct pci_dev *pdev, |
| 333 | struct msi_desc *desc) |
| 334 | { |
| 335 | int irq, pos; |
| 336 | struct pcie_port *pp = sys_to_pcie(pdev->bus->sysdata); |
| 337 | |
| 338 | if (desc->msi_attrib.is_msix) |
| 339 | return -EINVAL; |
| 340 | |
| 341 | irq = assign_irq(1, desc, &pos); |
| 342 | if (irq < 0) |
| 343 | return irq; |
| 344 | |
| 345 | dw_msi_setup_msg(pp, irq, pos); |
Jingoo Han | f342d94 | 2013-09-06 15:54:59 +0900 | [diff] [blame] | 346 | |
| 347 | return 0; |
| 348 | } |
| 349 | |
Lucas Stach | 7970737 | 2015-09-18 13:58:35 -0500 | [diff] [blame] | 350 | static int dw_msi_setup_irqs(struct msi_controller *chip, struct pci_dev *pdev, |
| 351 | int nvec, int type) |
| 352 | { |
| 353 | #ifdef CONFIG_PCI_MSI |
| 354 | int irq, pos; |
| 355 | struct msi_desc *desc; |
| 356 | struct pcie_port *pp = sys_to_pcie(pdev->bus->sysdata); |
| 357 | |
| 358 | /* MSI-X interrupts are not supported */ |
| 359 | if (type == PCI_CAP_ID_MSIX) |
| 360 | return -EINVAL; |
| 361 | |
| 362 | WARN_ON(!list_is_singular(&pdev->dev.msi_list)); |
| 363 | desc = list_entry(pdev->dev.msi_list.next, struct msi_desc, list); |
| 364 | |
| 365 | irq = assign_irq(nvec, desc, &pos); |
| 366 | if (irq < 0) |
| 367 | return irq; |
| 368 | |
| 369 | dw_msi_setup_msg(pp, irq, pos); |
| 370 | |
| 371 | return 0; |
| 372 | #else |
| 373 | return -EINVAL; |
| 374 | #endif |
| 375 | } |
| 376 | |
Yijing Wang | c2791b8 | 2014-11-11 17:45:45 -0700 | [diff] [blame] | 377 | static void dw_msi_teardown_irq(struct msi_controller *chip, unsigned int irq) |
Jingoo Han | f342d94 | 2013-09-06 15:54:59 +0900 | [diff] [blame] | 378 | { |
Lucas Stach | 91f8ae8 | 2014-09-30 18:36:26 +0200 | [diff] [blame] | 379 | struct irq_data *data = irq_get_irq_data(irq); |
Jiang Liu | c391f26 | 2015-06-01 16:05:41 +0800 | [diff] [blame] | 380 | struct msi_desc *msi = irq_data_get_msi_desc(data); |
Jiang Liu | e39758e | 2015-07-09 16:00:43 +0800 | [diff] [blame] | 381 | struct pcie_port *pp = sys_to_pcie(msi_desc_to_pci_sysdata(msi)); |
Lucas Stach | 91f8ae8 | 2014-09-30 18:36:26 +0200 | [diff] [blame] | 382 | |
| 383 | clear_irq_range(pp, irq, 1, data->hwirq); |
Jingoo Han | f342d94 | 2013-09-06 15:54:59 +0900 | [diff] [blame] | 384 | } |
| 385 | |
Yijing Wang | c2791b8 | 2014-11-11 17:45:45 -0700 | [diff] [blame] | 386 | static struct msi_controller dw_pcie_msi_chip = { |
Jingoo Han | f342d94 | 2013-09-06 15:54:59 +0900 | [diff] [blame] | 387 | .setup_irq = dw_msi_setup_irq, |
Lucas Stach | 7970737 | 2015-09-18 13:58:35 -0500 | [diff] [blame] | 388 | .setup_irqs = dw_msi_setup_irqs, |
Jingoo Han | f342d94 | 2013-09-06 15:54:59 +0900 | [diff] [blame] | 389 | .teardown_irq = dw_msi_teardown_irq, |
| 390 | }; |
| 391 | |
Jingoo Han | 4b1ced8 | 2013-07-31 17:14:10 +0900 | [diff] [blame] | 392 | int dw_pcie_link_up(struct pcie_port *pp) |
Jingoo Han | 340cba6 | 2013-06-21 16:24:54 +0900 | [diff] [blame] | 393 | { |
Jingoo Han | 4b1ced8 | 2013-07-31 17:14:10 +0900 | [diff] [blame] | 394 | if (pp->ops->link_up) |
| 395 | return pp->ops->link_up(pp); |
Jingoo Han | 340cba6 | 2013-06-21 16:24:54 +0900 | [diff] [blame] | 396 | else |
Jingoo Han | 340cba6 | 2013-06-21 16:24:54 +0900 | [diff] [blame] | 397 | return 0; |
Jingoo Han | 340cba6 | 2013-06-21 16:24:54 +0900 | [diff] [blame] | 398 | } |
| 399 | |
Jingoo Han | f342d94 | 2013-09-06 15:54:59 +0900 | [diff] [blame] | 400 | static int dw_pcie_msi_map(struct irq_domain *domain, unsigned int irq, |
| 401 | irq_hw_number_t hwirq) |
| 402 | { |
| 403 | irq_set_chip_and_handler(irq, &dw_msi_irq_chip, handle_simple_irq); |
| 404 | irq_set_chip_data(irq, domain->host_data); |
Jingoo Han | f342d94 | 2013-09-06 15:54:59 +0900 | [diff] [blame] | 405 | |
| 406 | return 0; |
| 407 | } |
| 408 | |
| 409 | static const struct irq_domain_ops msi_domain_ops = { |
| 410 | .map = dw_pcie_msi_map, |
| 411 | }; |
| 412 | |
Matwey V. Kornilov | a43f32d | 2015-02-19 20:41:48 +0300 | [diff] [blame] | 413 | int dw_pcie_host_init(struct pcie_port *pp) |
Jingoo Han | 340cba6 | 2013-06-21 16:24:54 +0900 | [diff] [blame] | 414 | { |
Jingoo Han | 4b1ced8 | 2013-07-31 17:14:10 +0900 | [diff] [blame] | 415 | struct device_node *np = pp->dev->of_node; |
Kishon Vijay Abraham I | 4dd964d | 2014-07-17 14:30:40 +0530 | [diff] [blame] | 416 | struct platform_device *pdev = to_platform_device(pp->dev); |
Jingoo Han | 340cba6 | 2013-06-21 16:24:54 +0900 | [diff] [blame] | 417 | struct of_pci_range range; |
| 418 | struct of_pci_range_parser parser; |
Kishon Vijay Abraham I | 4dd964d | 2014-07-17 14:30:40 +0530 | [diff] [blame] | 419 | struct resource *cfg_res; |
Kishon Vijay Abraham I | f4c55c5 | 2014-07-17 14:30:41 +0530 | [diff] [blame] | 420 | u32 val, na, ns; |
| 421 | const __be32 *addrp; |
Murali Karicheri | b14a3d1 | 2014-07-23 14:54:51 -0400 | [diff] [blame] | 422 | int i, index, ret; |
Kishon Vijay Abraham I | f4c55c5 | 2014-07-17 14:30:41 +0530 | [diff] [blame] | 423 | |
| 424 | /* Find the address cell size and the number of cells in order to get |
| 425 | * the untranslated address. |
| 426 | */ |
| 427 | of_property_read_u32(np, "#address-cells", &na); |
| 428 | ns = of_n_size_cells(np); |
Jingoo Han | f342d94 | 2013-09-06 15:54:59 +0900 | [diff] [blame] | 429 | |
Kishon Vijay Abraham I | 4dd964d | 2014-07-17 14:30:40 +0530 | [diff] [blame] | 430 | cfg_res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "config"); |
| 431 | if (cfg_res) { |
Pratyush Anand | adf70fc | 2014-09-05 17:48:54 -0600 | [diff] [blame] | 432 | pp->cfg0_size = resource_size(cfg_res)/2; |
| 433 | pp->cfg1_size = resource_size(cfg_res)/2; |
Kishon Vijay Abraham I | 4dd964d | 2014-07-17 14:30:40 +0530 | [diff] [blame] | 434 | pp->cfg0_base = cfg_res->start; |
Pratyush Anand | adf70fc | 2014-09-05 17:48:54 -0600 | [diff] [blame] | 435 | pp->cfg1_base = cfg_res->start + pp->cfg0_size; |
Kishon Vijay Abraham I | f4c55c5 | 2014-07-17 14:30:41 +0530 | [diff] [blame] | 436 | |
| 437 | /* Find the untranslated configuration space address */ |
| 438 | index = of_property_match_string(np, "reg-names", "config"); |
Fabio Estevam | 9f0dbe0 | 2014-09-22 14:52:07 -0600 | [diff] [blame] | 439 | addrp = of_get_address(np, index, NULL, NULL); |
Kishon Vijay Abraham I | f4c55c5 | 2014-07-17 14:30:41 +0530 | [diff] [blame] | 440 | pp->cfg0_mod_base = of_read_number(addrp, ns); |
Pratyush Anand | adf70fc | 2014-09-05 17:48:54 -0600 | [diff] [blame] | 441 | pp->cfg1_mod_base = pp->cfg0_mod_base + pp->cfg0_size; |
Murali Karicheri | 0f41421 | 2015-07-21 17:54:11 -0400 | [diff] [blame] | 442 | } else if (!pp->va_cfg0_base) { |
Kishon Vijay Abraham I | 4dd964d | 2014-07-17 14:30:40 +0530 | [diff] [blame] | 443 | dev_err(pp->dev, "missing *config* reg space\n"); |
| 444 | } |
| 445 | |
Jingoo Han | 340cba6 | 2013-06-21 16:24:54 +0900 | [diff] [blame] | 446 | if (of_pci_range_parser_init(&parser, np)) { |
Jingoo Han | 4b1ced8 | 2013-07-31 17:14:10 +0900 | [diff] [blame] | 447 | dev_err(pp->dev, "missing ranges property\n"); |
Jingoo Han | 340cba6 | 2013-06-21 16:24:54 +0900 | [diff] [blame] | 448 | return -EINVAL; |
| 449 | } |
| 450 | |
| 451 | /* Get the I/O and memory ranges from DT */ |
| 452 | for_each_of_pci_range(&parser, &range) { |
| 453 | unsigned long restype = range.flags & IORESOURCE_TYPE_BITS; |
Jingoo Han | 2c992f3 | 2014-11-12 12:27:04 +0900 | [diff] [blame] | 454 | |
Jingoo Han | 340cba6 | 2013-06-21 16:24:54 +0900 | [diff] [blame] | 455 | if (restype == IORESOURCE_IO) { |
| 456 | of_pci_range_to_resource(&range, np, &pp->io); |
| 457 | pp->io.name = "I/O"; |
| 458 | pp->io.start = max_t(resource_size_t, |
| 459 | PCIBIOS_MIN_IO, |
| 460 | range.pci_addr + global_io_offset); |
| 461 | pp->io.end = min_t(resource_size_t, |
| 462 | IO_SPACE_LIMIT, |
| 463 | range.pci_addr + range.size |
Minghuan Lian | 0c61ea7 | 2014-09-23 22:28:57 +0800 | [diff] [blame] | 464 | + global_io_offset - 1); |
Pratyush Anand | adf70fc | 2014-09-05 17:48:54 -0600 | [diff] [blame] | 465 | pp->io_size = resource_size(&pp->io); |
| 466 | pp->io_bus_addr = range.pci_addr; |
Pratyush Anand | fce8591 | 2013-12-11 15:08:33 +0530 | [diff] [blame] | 467 | pp->io_base = range.cpu_addr; |
Kishon Vijay Abraham I | f4c55c5 | 2014-07-17 14:30:41 +0530 | [diff] [blame] | 468 | |
| 469 | /* Find the untranslated IO space address */ |
| 470 | pp->io_mod_base = of_read_number(parser.range - |
| 471 | parser.np + na, ns); |
Jingoo Han | 340cba6 | 2013-06-21 16:24:54 +0900 | [diff] [blame] | 472 | } |
| 473 | if (restype == IORESOURCE_MEM) { |
| 474 | of_pci_range_to_resource(&range, np, &pp->mem); |
| 475 | pp->mem.name = "MEM"; |
Pratyush Anand | adf70fc | 2014-09-05 17:48:54 -0600 | [diff] [blame] | 476 | pp->mem_size = resource_size(&pp->mem); |
| 477 | pp->mem_bus_addr = range.pci_addr; |
Kishon Vijay Abraham I | f4c55c5 | 2014-07-17 14:30:41 +0530 | [diff] [blame] | 478 | |
| 479 | /* Find the untranslated MEM space address */ |
| 480 | pp->mem_mod_base = of_read_number(parser.range - |
| 481 | parser.np + na, ns); |
Jingoo Han | 340cba6 | 2013-06-21 16:24:54 +0900 | [diff] [blame] | 482 | } |
| 483 | if (restype == 0) { |
| 484 | of_pci_range_to_resource(&range, np, &pp->cfg); |
Pratyush Anand | adf70fc | 2014-09-05 17:48:54 -0600 | [diff] [blame] | 485 | pp->cfg0_size = resource_size(&pp->cfg)/2; |
| 486 | pp->cfg1_size = resource_size(&pp->cfg)/2; |
Kishon Vijay Abraham I | 4dd964d | 2014-07-17 14:30:40 +0530 | [diff] [blame] | 487 | pp->cfg0_base = pp->cfg.start; |
Pratyush Anand | adf70fc | 2014-09-05 17:48:54 -0600 | [diff] [blame] | 488 | pp->cfg1_base = pp->cfg.start + pp->cfg0_size; |
Kishon Vijay Abraham I | f4c55c5 | 2014-07-17 14:30:41 +0530 | [diff] [blame] | 489 | |
| 490 | /* Find the untranslated configuration space address */ |
| 491 | pp->cfg0_mod_base = of_read_number(parser.range - |
| 492 | parser.np + na, ns); |
| 493 | pp->cfg1_mod_base = pp->cfg0_mod_base + |
Pratyush Anand | adf70fc | 2014-09-05 17:48:54 -0600 | [diff] [blame] | 494 | pp->cfg0_size; |
Jingoo Han | 340cba6 | 2013-06-21 16:24:54 +0900 | [diff] [blame] | 495 | } |
| 496 | } |
| 497 | |
Lucas Stach | 4f2ebe0 | 2014-07-23 19:52:38 +0200 | [diff] [blame] | 498 | ret = of_pci_parse_bus_range(np, &pp->busn); |
| 499 | if (ret < 0) { |
| 500 | pp->busn.name = np->name; |
| 501 | pp->busn.start = 0; |
| 502 | pp->busn.end = 0xff; |
| 503 | pp->busn.flags = IORESOURCE_BUS; |
| 504 | dev_dbg(pp->dev, "failed to parse bus-range property: %d, using default %pR\n", |
| 505 | ret, &pp->busn); |
| 506 | } |
| 507 | |
Jingoo Han | 4b1ced8 | 2013-07-31 17:14:10 +0900 | [diff] [blame] | 508 | if (!pp->dbi_base) { |
| 509 | pp->dbi_base = devm_ioremap(pp->dev, pp->cfg.start, |
| 510 | resource_size(&pp->cfg)); |
| 511 | if (!pp->dbi_base) { |
| 512 | dev_err(pp->dev, "error with ioremap\n"); |
| 513 | return -ENOMEM; |
| 514 | } |
Jingoo Han | 340cba6 | 2013-06-21 16:24:54 +0900 | [diff] [blame] | 515 | } |
Jingoo Han | 340cba6 | 2013-06-21 16:24:54 +0900 | [diff] [blame] | 516 | |
Jingoo Han | 4b1ced8 | 2013-07-31 17:14:10 +0900 | [diff] [blame] | 517 | pp->mem_base = pp->mem.start; |
| 518 | |
Jingoo Han | 4b1ced8 | 2013-07-31 17:14:10 +0900 | [diff] [blame] | 519 | if (!pp->va_cfg0_base) { |
Murali Karicheri | b14a3d1 | 2014-07-23 14:54:51 -0400 | [diff] [blame] | 520 | pp->va_cfg0_base = devm_ioremap(pp->dev, pp->cfg0_base, |
Pratyush Anand | adf70fc | 2014-09-05 17:48:54 -0600 | [diff] [blame] | 521 | pp->cfg0_size); |
Murali Karicheri | b14a3d1 | 2014-07-23 14:54:51 -0400 | [diff] [blame] | 522 | if (!pp->va_cfg0_base) { |
| 523 | dev_err(pp->dev, "error with ioremap in function\n"); |
| 524 | return -ENOMEM; |
| 525 | } |
Jingoo Han | 340cba6 | 2013-06-21 16:24:54 +0900 | [diff] [blame] | 526 | } |
Murali Karicheri | b14a3d1 | 2014-07-23 14:54:51 -0400 | [diff] [blame] | 527 | |
Jingoo Han | 4b1ced8 | 2013-07-31 17:14:10 +0900 | [diff] [blame] | 528 | if (!pp->va_cfg1_base) { |
Murali Karicheri | b14a3d1 | 2014-07-23 14:54:51 -0400 | [diff] [blame] | 529 | pp->va_cfg1_base = devm_ioremap(pp->dev, pp->cfg1_base, |
Pratyush Anand | adf70fc | 2014-09-05 17:48:54 -0600 | [diff] [blame] | 530 | pp->cfg1_size); |
Murali Karicheri | b14a3d1 | 2014-07-23 14:54:51 -0400 | [diff] [blame] | 531 | if (!pp->va_cfg1_base) { |
| 532 | dev_err(pp->dev, "error with ioremap\n"); |
| 533 | return -ENOMEM; |
| 534 | } |
Jingoo Han | 4b1ced8 | 2013-07-31 17:14:10 +0900 | [diff] [blame] | 535 | } |
Jingoo Han | 340cba6 | 2013-06-21 16:24:54 +0900 | [diff] [blame] | 536 | |
Jingoo Han | 4b1ced8 | 2013-07-31 17:14:10 +0900 | [diff] [blame] | 537 | if (of_property_read_u32(np, "num-lanes", &pp->lanes)) { |
| 538 | dev_err(pp->dev, "Failed to parse the number of lanes\n"); |
| 539 | return -EINVAL; |
| 540 | } |
Jingoo Han | 340cba6 | 2013-06-21 16:24:54 +0900 | [diff] [blame] | 541 | |
Jingoo Han | f342d94 | 2013-09-06 15:54:59 +0900 | [diff] [blame] | 542 | if (IS_ENABLED(CONFIG_PCI_MSI)) { |
Murali Karicheri | b14a3d1 | 2014-07-23 14:54:51 -0400 | [diff] [blame] | 543 | if (!pp->ops->msi_host_init) { |
| 544 | pp->irq_domain = irq_domain_add_linear(pp->dev->of_node, |
| 545 | MAX_MSI_IRQS, &msi_domain_ops, |
| 546 | &dw_pcie_msi_chip); |
| 547 | if (!pp->irq_domain) { |
| 548 | dev_err(pp->dev, "irq domain init failed\n"); |
| 549 | return -ENXIO; |
| 550 | } |
Jingoo Han | f342d94 | 2013-09-06 15:54:59 +0900 | [diff] [blame] | 551 | |
Murali Karicheri | b14a3d1 | 2014-07-23 14:54:51 -0400 | [diff] [blame] | 552 | for (i = 0; i < MAX_MSI_IRQS; i++) |
| 553 | irq_create_mapping(pp->irq_domain, i); |
| 554 | } else { |
| 555 | ret = pp->ops->msi_host_init(pp, &dw_pcie_msi_chip); |
| 556 | if (ret < 0) |
| 557 | return ret; |
| 558 | } |
Jingoo Han | f342d94 | 2013-09-06 15:54:59 +0900 | [diff] [blame] | 559 | } |
| 560 | |
Jingoo Han | 4b1ced8 | 2013-07-31 17:14:10 +0900 | [diff] [blame] | 561 | if (pp->ops->host_init) |
| 562 | pp->ops->host_init(pp); |
Jingoo Han | 340cba6 | 2013-06-21 16:24:54 +0900 | [diff] [blame] | 563 | |
Jisheng Zhang | 2d91b49 | 2015-04-30 16:22:29 +0800 | [diff] [blame] | 564 | if (!pp->ops->rd_other_conf) |
| 565 | dw_pcie_prog_outbound_atu(pp, PCIE_ATU_REGION_INDEX1, |
| 566 | PCIE_ATU_TYPE_MEM, pp->mem_mod_base, |
| 567 | pp->mem_bus_addr, pp->mem_size); |
| 568 | |
Jingoo Han | 4b1ced8 | 2013-07-31 17:14:10 +0900 | [diff] [blame] | 569 | dw_pcie_wr_own_conf(pp, PCI_BASE_ADDRESS_0, 4, 0); |
| 570 | |
| 571 | /* program correct class for RC */ |
| 572 | dw_pcie_wr_own_conf(pp, PCI_CLASS_DEVICE, 2, PCI_CLASS_BRIDGE_PCI); |
| 573 | |
| 574 | dw_pcie_rd_own_conf(pp, PCIE_LINK_WIDTH_SPEED_CONTROL, 4, &val); |
| 575 | val |= PORT_LOGIC_SPEED_CHANGE; |
| 576 | dw_pcie_wr_own_conf(pp, PCIE_LINK_WIDTH_SPEED_CONTROL, 4, val); |
| 577 | |
Yijing Wang | 0815f95 | 2014-11-11 15:38:07 -0700 | [diff] [blame] | 578 | #ifdef CONFIG_PCI_MSI |
| 579 | dw_pcie_msi_chip.dev = pp->dev; |
Yijing Wang | 0815f95 | 2014-11-11 15:38:07 -0700 | [diff] [blame] | 580 | #endif |
| 581 | |
Jingoo Han | 4b1ced8 | 2013-07-31 17:14:10 +0900 | [diff] [blame] | 582 | dw_pci.nr_controllers = 1; |
| 583 | dw_pci.private_data = (void **)&pp; |
| 584 | |
Lucas Stach | 804f57b | 2014-03-05 14:25:51 +0100 | [diff] [blame] | 585 | pci_common_init_dev(pp->dev, &dw_pci); |
Jingoo Han | 340cba6 | 2013-06-21 16:24:54 +0900 | [diff] [blame] | 586 | |
Jingoo Han | 340cba6 | 2013-06-21 16:24:54 +0900 | [diff] [blame] | 587 | return 0; |
Jingoo Han | 4b1ced8 | 2013-07-31 17:14:10 +0900 | [diff] [blame] | 588 | } |
Jingoo Han | 340cba6 | 2013-06-21 16:24:54 +0900 | [diff] [blame] | 589 | |
Jingoo Han | 4b1ced8 | 2013-07-31 17:14:10 +0900 | [diff] [blame] | 590 | static int dw_pcie_rd_other_conf(struct pcie_port *pp, struct pci_bus *bus, |
| 591 | u32 devfn, int where, int size, u32 *val) |
| 592 | { |
Jisheng Zhang | 2d91b49 | 2015-04-30 16:22:29 +0800 | [diff] [blame] | 593 | int ret, type; |
Gabriele Paoloni | 4c45852 | 2015-10-08 14:27:48 -0500 | [diff] [blame] | 594 | u32 busdev, cfg_size; |
Jisheng Zhang | 2d91b49 | 2015-04-30 16:22:29 +0800 | [diff] [blame] | 595 | u64 cpu_addr; |
| 596 | void __iomem *va_cfg_base; |
Jingoo Han | 4b1ced8 | 2013-07-31 17:14:10 +0900 | [diff] [blame] | 597 | |
| 598 | busdev = PCIE_ATU_BUS(bus->number) | PCIE_ATU_DEV(PCI_SLOT(devfn)) | |
| 599 | PCIE_ATU_FUNC(PCI_FUNC(devfn)); |
Jingoo Han | 4b1ced8 | 2013-07-31 17:14:10 +0900 | [diff] [blame] | 600 | |
| 601 | if (bus->parent->number == pp->root_bus_nr) { |
Jisheng Zhang | 2d91b49 | 2015-04-30 16:22:29 +0800 | [diff] [blame] | 602 | type = PCIE_ATU_TYPE_CFG0; |
| 603 | cpu_addr = pp->cfg0_mod_base; |
| 604 | cfg_size = pp->cfg0_size; |
| 605 | va_cfg_base = pp->va_cfg0_base; |
Jingoo Han | 4b1ced8 | 2013-07-31 17:14:10 +0900 | [diff] [blame] | 606 | } else { |
Jisheng Zhang | 2d91b49 | 2015-04-30 16:22:29 +0800 | [diff] [blame] | 607 | type = PCIE_ATU_TYPE_CFG1; |
| 608 | cpu_addr = pp->cfg1_mod_base; |
| 609 | cfg_size = pp->cfg1_size; |
| 610 | va_cfg_base = pp->va_cfg1_base; |
Jingoo Han | 4b1ced8 | 2013-07-31 17:14:10 +0900 | [diff] [blame] | 611 | } |
| 612 | |
Jisheng Zhang | 2d91b49 | 2015-04-30 16:22:29 +0800 | [diff] [blame] | 613 | dw_pcie_prog_outbound_atu(pp, PCIE_ATU_REGION_INDEX0, |
| 614 | type, cpu_addr, |
| 615 | busdev, cfg_size); |
Gabriele Paoloni | 4c45852 | 2015-10-08 14:27:48 -0500 | [diff] [blame] | 616 | ret = dw_pcie_cfg_read(va_cfg_base + where, size, val); |
Jisheng Zhang | 2d91b49 | 2015-04-30 16:22:29 +0800 | [diff] [blame] | 617 | dw_pcie_prog_outbound_atu(pp, PCIE_ATU_REGION_INDEX0, |
| 618 | PCIE_ATU_TYPE_IO, pp->io_mod_base, |
| 619 | pp->io_bus_addr, pp->io_size); |
| 620 | |
Jingoo Han | 340cba6 | 2013-06-21 16:24:54 +0900 | [diff] [blame] | 621 | return ret; |
| 622 | } |
| 623 | |
Jingoo Han | 4b1ced8 | 2013-07-31 17:14:10 +0900 | [diff] [blame] | 624 | static int dw_pcie_wr_other_conf(struct pcie_port *pp, struct pci_bus *bus, |
| 625 | u32 devfn, int where, int size, u32 val) |
Jingoo Han | 340cba6 | 2013-06-21 16:24:54 +0900 | [diff] [blame] | 626 | { |
Jisheng Zhang | 2d91b49 | 2015-04-30 16:22:29 +0800 | [diff] [blame] | 627 | int ret, type; |
Gabriele Paoloni | 4c45852 | 2015-10-08 14:27:48 -0500 | [diff] [blame] | 628 | u32 busdev, cfg_size; |
Jisheng Zhang | 2d91b49 | 2015-04-30 16:22:29 +0800 | [diff] [blame] | 629 | u64 cpu_addr; |
| 630 | void __iomem *va_cfg_base; |
Jingoo Han | 340cba6 | 2013-06-21 16:24:54 +0900 | [diff] [blame] | 631 | |
Jingoo Han | 4b1ced8 | 2013-07-31 17:14:10 +0900 | [diff] [blame] | 632 | busdev = PCIE_ATU_BUS(bus->number) | PCIE_ATU_DEV(PCI_SLOT(devfn)) | |
| 633 | PCIE_ATU_FUNC(PCI_FUNC(devfn)); |
Jingoo Han | 340cba6 | 2013-06-21 16:24:54 +0900 | [diff] [blame] | 634 | |
Jingoo Han | 4b1ced8 | 2013-07-31 17:14:10 +0900 | [diff] [blame] | 635 | if (bus->parent->number == pp->root_bus_nr) { |
Jisheng Zhang | 2d91b49 | 2015-04-30 16:22:29 +0800 | [diff] [blame] | 636 | type = PCIE_ATU_TYPE_CFG0; |
| 637 | cpu_addr = pp->cfg0_mod_base; |
| 638 | cfg_size = pp->cfg0_size; |
| 639 | va_cfg_base = pp->va_cfg0_base; |
Jingoo Han | 4b1ced8 | 2013-07-31 17:14:10 +0900 | [diff] [blame] | 640 | } else { |
Jisheng Zhang | 2d91b49 | 2015-04-30 16:22:29 +0800 | [diff] [blame] | 641 | type = PCIE_ATU_TYPE_CFG1; |
| 642 | cpu_addr = pp->cfg1_mod_base; |
| 643 | cfg_size = pp->cfg1_size; |
| 644 | va_cfg_base = pp->va_cfg1_base; |
Jingoo Han | 4b1ced8 | 2013-07-31 17:14:10 +0900 | [diff] [blame] | 645 | } |
| 646 | |
Jisheng Zhang | 2d91b49 | 2015-04-30 16:22:29 +0800 | [diff] [blame] | 647 | dw_pcie_prog_outbound_atu(pp, PCIE_ATU_REGION_INDEX0, |
| 648 | type, cpu_addr, |
| 649 | busdev, cfg_size); |
Gabriele Paoloni | 4c45852 | 2015-10-08 14:27:48 -0500 | [diff] [blame] | 650 | ret = dw_pcie_cfg_write(va_cfg_base + where, size, val); |
Jisheng Zhang | 2d91b49 | 2015-04-30 16:22:29 +0800 | [diff] [blame] | 651 | dw_pcie_prog_outbound_atu(pp, PCIE_ATU_REGION_INDEX0, |
| 652 | PCIE_ATU_TYPE_IO, pp->io_mod_base, |
| 653 | pp->io_bus_addr, pp->io_size); |
| 654 | |
Jingoo Han | 4b1ced8 | 2013-07-31 17:14:10 +0900 | [diff] [blame] | 655 | return ret; |
Jingoo Han | 340cba6 | 2013-06-21 16:24:54 +0900 | [diff] [blame] | 656 | } |
| 657 | |
Jingoo Han | 4b1ced8 | 2013-07-31 17:14:10 +0900 | [diff] [blame] | 658 | static int dw_pcie_valid_config(struct pcie_port *pp, |
| 659 | struct pci_bus *bus, int dev) |
Jingoo Han | 340cba6 | 2013-06-21 16:24:54 +0900 | [diff] [blame] | 660 | { |
Jingoo Han | 4b1ced8 | 2013-07-31 17:14:10 +0900 | [diff] [blame] | 661 | /* If there is no link, then there is no device */ |
| 662 | if (bus->number != pp->root_bus_nr) { |
| 663 | if (!dw_pcie_link_up(pp)) |
| 664 | return 0; |
| 665 | } |
Jingoo Han | 340cba6 | 2013-06-21 16:24:54 +0900 | [diff] [blame] | 666 | |
Jingoo Han | 4b1ced8 | 2013-07-31 17:14:10 +0900 | [diff] [blame] | 667 | /* access only one slot on each root port */ |
| 668 | if (bus->number == pp->root_bus_nr && dev > 0) |
| 669 | return 0; |
Jingoo Han | 340cba6 | 2013-06-21 16:24:54 +0900 | [diff] [blame] | 670 | |
| 671 | /* |
Jingoo Han | 4b1ced8 | 2013-07-31 17:14:10 +0900 | [diff] [blame] | 672 | * do not read more than one device on the bus directly attached |
| 673 | * to RC's (Virtual Bridge's) DS side. |
Jingoo Han | 340cba6 | 2013-06-21 16:24:54 +0900 | [diff] [blame] | 674 | */ |
Jingoo Han | 4b1ced8 | 2013-07-31 17:14:10 +0900 | [diff] [blame] | 675 | if (bus->primary == pp->root_bus_nr && dev > 0) |
Jingoo Han | 340cba6 | 2013-06-21 16:24:54 +0900 | [diff] [blame] | 676 | return 0; |
Jingoo Han | 340cba6 | 2013-06-21 16:24:54 +0900 | [diff] [blame] | 677 | |
| 678 | return 1; |
| 679 | } |
| 680 | |
Jingoo Han | 4b1ced8 | 2013-07-31 17:14:10 +0900 | [diff] [blame] | 681 | static int dw_pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where, |
| 682 | int size, u32 *val) |
Jingoo Han | 340cba6 | 2013-06-21 16:24:54 +0900 | [diff] [blame] | 683 | { |
Jingoo Han | 4b1ced8 | 2013-07-31 17:14:10 +0900 | [diff] [blame] | 684 | struct pcie_port *pp = sys_to_pcie(bus->sysdata); |
Jingoo Han | 4b1ced8 | 2013-07-31 17:14:10 +0900 | [diff] [blame] | 685 | int ret; |
Jingoo Han | 340cba6 | 2013-06-21 16:24:54 +0900 | [diff] [blame] | 686 | |
Jingoo Han | 4b1ced8 | 2013-07-31 17:14:10 +0900 | [diff] [blame] | 687 | if (dw_pcie_valid_config(pp, bus, PCI_SLOT(devfn)) == 0) { |
| 688 | *val = 0xffffffff; |
| 689 | return PCIBIOS_DEVICE_NOT_FOUND; |
| 690 | } |
| 691 | |
Jingoo Han | 4b1ced8 | 2013-07-31 17:14:10 +0900 | [diff] [blame] | 692 | if (bus->number != pp->root_bus_nr) |
Murali Karicheri | a1c0ae9 | 2014-07-21 12:58:41 -0400 | [diff] [blame] | 693 | if (pp->ops->rd_other_conf) |
| 694 | ret = pp->ops->rd_other_conf(pp, bus, devfn, |
| 695 | where, size, val); |
| 696 | else |
| 697 | ret = dw_pcie_rd_other_conf(pp, bus, devfn, |
Jingoo Han | 4b1ced8 | 2013-07-31 17:14:10 +0900 | [diff] [blame] | 698 | where, size, val); |
| 699 | else |
| 700 | ret = dw_pcie_rd_own_conf(pp, where, size, val); |
Jingoo Han | 4b1ced8 | 2013-07-31 17:14:10 +0900 | [diff] [blame] | 701 | |
| 702 | return ret; |
Jingoo Han | 340cba6 | 2013-06-21 16:24:54 +0900 | [diff] [blame] | 703 | } |
Jingoo Han | 4b1ced8 | 2013-07-31 17:14:10 +0900 | [diff] [blame] | 704 | |
| 705 | static int dw_pcie_wr_conf(struct pci_bus *bus, u32 devfn, |
| 706 | int where, int size, u32 val) |
| 707 | { |
| 708 | struct pcie_port *pp = sys_to_pcie(bus->sysdata); |
Jingoo Han | 4b1ced8 | 2013-07-31 17:14:10 +0900 | [diff] [blame] | 709 | int ret; |
| 710 | |
Jingoo Han | 4b1ced8 | 2013-07-31 17:14:10 +0900 | [diff] [blame] | 711 | if (dw_pcie_valid_config(pp, bus, PCI_SLOT(devfn)) == 0) |
| 712 | return PCIBIOS_DEVICE_NOT_FOUND; |
| 713 | |
Jingoo Han | 4b1ced8 | 2013-07-31 17:14:10 +0900 | [diff] [blame] | 714 | if (bus->number != pp->root_bus_nr) |
Murali Karicheri | a1c0ae9 | 2014-07-21 12:58:41 -0400 | [diff] [blame] | 715 | if (pp->ops->wr_other_conf) |
| 716 | ret = pp->ops->wr_other_conf(pp, bus, devfn, |
| 717 | where, size, val); |
| 718 | else |
| 719 | ret = dw_pcie_wr_other_conf(pp, bus, devfn, |
Jingoo Han | 4b1ced8 | 2013-07-31 17:14:10 +0900 | [diff] [blame] | 720 | where, size, val); |
| 721 | else |
| 722 | ret = dw_pcie_wr_own_conf(pp, where, size, val); |
Jingoo Han | 4b1ced8 | 2013-07-31 17:14:10 +0900 | [diff] [blame] | 723 | |
| 724 | return ret; |
| 725 | } |
| 726 | |
| 727 | static struct pci_ops dw_pcie_ops = { |
| 728 | .read = dw_pcie_rd_conf, |
| 729 | .write = dw_pcie_wr_conf, |
| 730 | }; |
| 731 | |
Bjorn Helgaas | 73e4085 | 2013-10-09 09:12:37 -0600 | [diff] [blame] | 732 | static int dw_pcie_setup(int nr, struct pci_sys_data *sys) |
Jingoo Han | 4b1ced8 | 2013-07-31 17:14:10 +0900 | [diff] [blame] | 733 | { |
| 734 | struct pcie_port *pp; |
| 735 | |
| 736 | pp = sys_to_pcie(sys); |
| 737 | |
Pratyush Anand | adf70fc | 2014-09-05 17:48:54 -0600 | [diff] [blame] | 738 | if (global_io_offset < SZ_1M && pp->io_size > 0) { |
| 739 | sys->io_offset = global_io_offset - pp->io_bus_addr; |
Pratyush Anand | fce8591 | 2013-12-11 15:08:33 +0530 | [diff] [blame] | 740 | pci_ioremap_io(global_io_offset, pp->io_base); |
Jingoo Han | 4b1ced8 | 2013-07-31 17:14:10 +0900 | [diff] [blame] | 741 | global_io_offset += SZ_64K; |
| 742 | pci_add_resource_offset(&sys->resources, &pp->io, |
| 743 | sys->io_offset); |
| 744 | } |
| 745 | |
Pratyush Anand | adf70fc | 2014-09-05 17:48:54 -0600 | [diff] [blame] | 746 | sys->mem_offset = pp->mem.start - pp->mem_bus_addr; |
Jingoo Han | 4b1ced8 | 2013-07-31 17:14:10 +0900 | [diff] [blame] | 747 | pci_add_resource_offset(&sys->resources, &pp->mem, sys->mem_offset); |
Lucas Stach | 4f2ebe0 | 2014-07-23 19:52:38 +0200 | [diff] [blame] | 748 | pci_add_resource(&sys->resources, &pp->busn); |
Jingoo Han | 4b1ced8 | 2013-07-31 17:14:10 +0900 | [diff] [blame] | 749 | |
| 750 | return 1; |
| 751 | } |
| 752 | |
Bjorn Helgaas | 73e4085 | 2013-10-09 09:12:37 -0600 | [diff] [blame] | 753 | static struct pci_bus *dw_pcie_scan_bus(int nr, struct pci_sys_data *sys) |
Jingoo Han | 4b1ced8 | 2013-07-31 17:14:10 +0900 | [diff] [blame] | 754 | { |
| 755 | struct pci_bus *bus; |
| 756 | struct pcie_port *pp = sys_to_pcie(sys); |
| 757 | |
Lucas Stach | 92483df | 2014-07-23 19:52:39 +0200 | [diff] [blame] | 758 | pp->root_bus_nr = sys->busnr; |
Lorenzo Pieralisi | 8953aab | 2015-07-29 12:33:18 +0100 | [diff] [blame] | 759 | |
| 760 | if (IS_ENABLED(CONFIG_PCI_MSI)) |
| 761 | bus = pci_scan_root_bus_msi(pp->dev, sys->busnr, &dw_pcie_ops, |
| 762 | sys, &sys->resources, |
| 763 | &dw_pcie_msi_chip); |
| 764 | else |
| 765 | bus = pci_scan_root_bus(pp->dev, sys->busnr, &dw_pcie_ops, |
| 766 | sys, &sys->resources); |
| 767 | |
Lucas Stach | 92483df | 2014-07-23 19:52:39 +0200 | [diff] [blame] | 768 | if (!bus) |
| 769 | return NULL; |
| 770 | |
Murali Karicheri | b14a3d1 | 2014-07-23 14:54:51 -0400 | [diff] [blame] | 771 | if (bus && pp->ops->scan_bus) |
| 772 | pp->ops->scan_bus(pp); |
| 773 | |
Jingoo Han | 4b1ced8 | 2013-07-31 17:14:10 +0900 | [diff] [blame] | 774 | return bus; |
| 775 | } |
| 776 | |
Bjorn Helgaas | 73e4085 | 2013-10-09 09:12:37 -0600 | [diff] [blame] | 777 | static int dw_pcie_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) |
Jingoo Han | 4b1ced8 | 2013-07-31 17:14:10 +0900 | [diff] [blame] | 778 | { |
| 779 | struct pcie_port *pp = sys_to_pcie(dev->bus->sysdata); |
Lucas Stach | 804f57b | 2014-03-05 14:25:51 +0100 | [diff] [blame] | 780 | int irq; |
Jingoo Han | 4b1ced8 | 2013-07-31 17:14:10 +0900 | [diff] [blame] | 781 | |
Lucas Stach | 804f57b | 2014-03-05 14:25:51 +0100 | [diff] [blame] | 782 | irq = of_irq_parse_and_map_pci(dev, slot, pin); |
| 783 | if (!irq) |
| 784 | irq = pp->irq; |
| 785 | |
| 786 | return irq; |
Jingoo Han | 4b1ced8 | 2013-07-31 17:14:10 +0900 | [diff] [blame] | 787 | } |
| 788 | |
| 789 | static struct hw_pci dw_pci = { |
| 790 | .setup = dw_pcie_setup, |
| 791 | .scan = dw_pcie_scan_bus, |
| 792 | .map_irq = dw_pcie_map_irq, |
| 793 | }; |
| 794 | |
| 795 | void dw_pcie_setup_rc(struct pcie_port *pp) |
| 796 | { |
Jingoo Han | 4b1ced8 | 2013-07-31 17:14:10 +0900 | [diff] [blame] | 797 | u32 val; |
| 798 | u32 membase; |
| 799 | u32 memlimit; |
| 800 | |
Mohit Kumar | 66c5c34 | 2014-04-14 14:22:54 -0600 | [diff] [blame] | 801 | /* set the number of lanes */ |
Seungwon Jeon | f7b7868 | 2013-08-28 20:53:30 +0900 | [diff] [blame] | 802 | dw_pcie_readl_rc(pp, PCIE_PORT_LINK_CONTROL, &val); |
Jingoo Han | 4b1ced8 | 2013-07-31 17:14:10 +0900 | [diff] [blame] | 803 | val &= ~PORT_LINK_MODE_MASK; |
| 804 | switch (pp->lanes) { |
| 805 | case 1: |
| 806 | val |= PORT_LINK_MODE_1_LANES; |
| 807 | break; |
| 808 | case 2: |
| 809 | val |= PORT_LINK_MODE_2_LANES; |
| 810 | break; |
| 811 | case 4: |
| 812 | val |= PORT_LINK_MODE_4_LANES; |
| 813 | break; |
Zhou Wang | 5b0f073 | 2015-05-13 14:44:34 +0800 | [diff] [blame] | 814 | case 8: |
| 815 | val |= PORT_LINK_MODE_8_LANES; |
| 816 | break; |
Jingoo Han | 4b1ced8 | 2013-07-31 17:14:10 +0900 | [diff] [blame] | 817 | } |
Seungwon Jeon | f7b7868 | 2013-08-28 20:53:30 +0900 | [diff] [blame] | 818 | dw_pcie_writel_rc(pp, val, PCIE_PORT_LINK_CONTROL); |
Jingoo Han | 4b1ced8 | 2013-07-31 17:14:10 +0900 | [diff] [blame] | 819 | |
| 820 | /* set link width speed control register */ |
Seungwon Jeon | f7b7868 | 2013-08-28 20:53:30 +0900 | [diff] [blame] | 821 | dw_pcie_readl_rc(pp, PCIE_LINK_WIDTH_SPEED_CONTROL, &val); |
Jingoo Han | 4b1ced8 | 2013-07-31 17:14:10 +0900 | [diff] [blame] | 822 | val &= ~PORT_LOGIC_LINK_WIDTH_MASK; |
| 823 | switch (pp->lanes) { |
| 824 | case 1: |
| 825 | val |= PORT_LOGIC_LINK_WIDTH_1_LANES; |
| 826 | break; |
| 827 | case 2: |
| 828 | val |= PORT_LOGIC_LINK_WIDTH_2_LANES; |
| 829 | break; |
| 830 | case 4: |
| 831 | val |= PORT_LOGIC_LINK_WIDTH_4_LANES; |
| 832 | break; |
Zhou Wang | 5b0f073 | 2015-05-13 14:44:34 +0800 | [diff] [blame] | 833 | case 8: |
| 834 | val |= PORT_LOGIC_LINK_WIDTH_8_LANES; |
| 835 | break; |
Jingoo Han | 4b1ced8 | 2013-07-31 17:14:10 +0900 | [diff] [blame] | 836 | } |
Seungwon Jeon | f7b7868 | 2013-08-28 20:53:30 +0900 | [diff] [blame] | 837 | dw_pcie_writel_rc(pp, val, PCIE_LINK_WIDTH_SPEED_CONTROL); |
Jingoo Han | 4b1ced8 | 2013-07-31 17:14:10 +0900 | [diff] [blame] | 838 | |
| 839 | /* setup RC BARs */ |
Seungwon Jeon | f7b7868 | 2013-08-28 20:53:30 +0900 | [diff] [blame] | 840 | dw_pcie_writel_rc(pp, 0x00000004, PCI_BASE_ADDRESS_0); |
Mohit Kumar | dbffdd6 | 2014-02-19 17:34:35 +0530 | [diff] [blame] | 841 | dw_pcie_writel_rc(pp, 0x00000000, PCI_BASE_ADDRESS_1); |
Jingoo Han | 4b1ced8 | 2013-07-31 17:14:10 +0900 | [diff] [blame] | 842 | |
| 843 | /* setup interrupt pins */ |
Seungwon Jeon | f7b7868 | 2013-08-28 20:53:30 +0900 | [diff] [blame] | 844 | dw_pcie_readl_rc(pp, PCI_INTERRUPT_LINE, &val); |
Jingoo Han | 4b1ced8 | 2013-07-31 17:14:10 +0900 | [diff] [blame] | 845 | val &= 0xffff00ff; |
| 846 | val |= 0x00000100; |
Seungwon Jeon | f7b7868 | 2013-08-28 20:53:30 +0900 | [diff] [blame] | 847 | dw_pcie_writel_rc(pp, val, PCI_INTERRUPT_LINE); |
Jingoo Han | 4b1ced8 | 2013-07-31 17:14:10 +0900 | [diff] [blame] | 848 | |
| 849 | /* setup bus numbers */ |
Seungwon Jeon | f7b7868 | 2013-08-28 20:53:30 +0900 | [diff] [blame] | 850 | dw_pcie_readl_rc(pp, PCI_PRIMARY_BUS, &val); |
Jingoo Han | 4b1ced8 | 2013-07-31 17:14:10 +0900 | [diff] [blame] | 851 | val &= 0xff000000; |
| 852 | val |= 0x00010100; |
Seungwon Jeon | f7b7868 | 2013-08-28 20:53:30 +0900 | [diff] [blame] | 853 | dw_pcie_writel_rc(pp, val, PCI_PRIMARY_BUS); |
Jingoo Han | 4b1ced8 | 2013-07-31 17:14:10 +0900 | [diff] [blame] | 854 | |
| 855 | /* setup memory base, memory limit */ |
| 856 | membase = ((u32)pp->mem_base & 0xfff00000) >> 16; |
Pratyush Anand | adf70fc | 2014-09-05 17:48:54 -0600 | [diff] [blame] | 857 | memlimit = (pp->mem_size + (u32)pp->mem_base) & 0xfff00000; |
Jingoo Han | 4b1ced8 | 2013-07-31 17:14:10 +0900 | [diff] [blame] | 858 | val = memlimit | membase; |
Seungwon Jeon | f7b7868 | 2013-08-28 20:53:30 +0900 | [diff] [blame] | 859 | dw_pcie_writel_rc(pp, val, PCI_MEMORY_BASE); |
Jingoo Han | 4b1ced8 | 2013-07-31 17:14:10 +0900 | [diff] [blame] | 860 | |
| 861 | /* setup command register */ |
Seungwon Jeon | f7b7868 | 2013-08-28 20:53:30 +0900 | [diff] [blame] | 862 | dw_pcie_readl_rc(pp, PCI_COMMAND, &val); |
Jingoo Han | 4b1ced8 | 2013-07-31 17:14:10 +0900 | [diff] [blame] | 863 | val &= 0xffff0000; |
| 864 | val |= PCI_COMMAND_IO | PCI_COMMAND_MEMORY | |
| 865 | PCI_COMMAND_MASTER | PCI_COMMAND_SERR; |
Seungwon Jeon | f7b7868 | 2013-08-28 20:53:30 +0900 | [diff] [blame] | 866 | dw_pcie_writel_rc(pp, val, PCI_COMMAND); |
Jingoo Han | 4b1ced8 | 2013-07-31 17:14:10 +0900 | [diff] [blame] | 867 | } |
Jingoo Han | 340cba6 | 2013-06-21 16:24:54 +0900 | [diff] [blame] | 868 | |
| 869 | MODULE_AUTHOR("Jingoo Han <jg1.han@samsung.com>"); |
Jingoo Han | 4b1ced8 | 2013-07-31 17:14:10 +0900 | [diff] [blame] | 870 | MODULE_DESCRIPTION("Designware PCIe host controller driver"); |
Jingoo Han | 340cba6 | 2013-06-21 16:24:54 +0900 | [diff] [blame] | 871 | MODULE_LICENSE("GPL v2"); |