blob: 30f921421b0c944217832ba86856a6904f8fef11 [file] [log] [blame]
Jani Nikula7c10a2b2014-10-27 16:26:43 +02001/*
2 * Copyright © 2014 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 */
23
24#include <linux/kernel.h>
Imre Deak58fddc22015-01-08 17:54:14 +020025#include <linux/component.h>
26#include <drm/i915_component.h>
27#include "intel_drv.h"
Jani Nikula7c10a2b2014-10-27 16:26:43 +020028
29#include <drm/drmP.h>
30#include <drm/drm_edid.h>
Jani Nikula7c10a2b2014-10-27 16:26:43 +020031#include "i915_drv.h"
32
Jani Nikula28855d22014-10-27 16:27:00 +020033/**
34 * DOC: High Definition Audio over HDMI and Display Port
35 *
36 * The graphics and audio drivers together support High Definition Audio over
37 * HDMI and Display Port. The audio programming sequences are divided into audio
38 * codec and controller enable and disable sequences. The graphics driver
39 * handles the audio codec sequences, while the audio driver handles the audio
40 * controller sequences.
41 *
42 * The disable sequences must be performed before disabling the transcoder or
43 * port. The enable sequences may only be performed after enabling the
Jani Nikula3e6da4a2015-07-02 16:05:27 +030044 * transcoder and port, and after completed link training. Therefore the audio
45 * enable/disable sequences are part of the modeset sequence.
Jani Nikula28855d22014-10-27 16:27:00 +020046 *
47 * The codec and controller sequences could be done either parallel or serial,
48 * but generally the ELDV/PD change in the codec sequence indicates to the audio
49 * driver that the controller sequence should start. Indeed, most of the
50 * co-operation between the graphics and audio drivers is handled via audio
51 * related registers. (The notable exception is the power management, not
52 * covered here.)
Libin Yangcb422612015-10-01 17:01:09 +080053 *
54 * The struct i915_audio_component is used to interact between the graphics
55 * and audio drivers. The struct i915_audio_component_ops *ops in it is
56 * defined in graphics driver and called in audio driver. The
57 * struct i915_audio_component_audio_ops *audio_ops is called from i915 driver.
Jani Nikula28855d22014-10-27 16:27:00 +020058 */
59
Jani Nikula87fcb2a2014-10-27 16:26:44 +020060static const struct {
Jani Nikula7c10a2b2014-10-27 16:26:43 +020061 int clock;
62 u32 config;
63} hdmi_audio_clock[] = {
Ville Syrjälä606bb5e2015-10-08 11:43:34 +030064 { 25175, AUD_CONFIG_PIXEL_CLOCK_HDMI_25175 },
Jani Nikula7c10a2b2014-10-27 16:26:43 +020065 { 25200, AUD_CONFIG_PIXEL_CLOCK_HDMI_25200 }, /* default per bspec */
66 { 27000, AUD_CONFIG_PIXEL_CLOCK_HDMI_27000 },
Ville Syrjälä606bb5e2015-10-08 11:43:34 +030067 { 27027, AUD_CONFIG_PIXEL_CLOCK_HDMI_27027 },
Jani Nikula7c10a2b2014-10-27 16:26:43 +020068 { 54000, AUD_CONFIG_PIXEL_CLOCK_HDMI_54000 },
Ville Syrjälä606bb5e2015-10-08 11:43:34 +030069 { 54054, AUD_CONFIG_PIXEL_CLOCK_HDMI_54054 },
70 { 74176, AUD_CONFIG_PIXEL_CLOCK_HDMI_74176 },
Jani Nikula7c10a2b2014-10-27 16:26:43 +020071 { 74250, AUD_CONFIG_PIXEL_CLOCK_HDMI_74250 },
Ville Syrjälä606bb5e2015-10-08 11:43:34 +030072 { 148352, AUD_CONFIG_PIXEL_CLOCK_HDMI_148352 },
Jani Nikula7c10a2b2014-10-27 16:26:43 +020073 { 148500, AUD_CONFIG_PIXEL_CLOCK_HDMI_148500 },
74};
75
Libin Yang4a21ef72015-09-02 14:11:39 +080076/* HDMI N/CTS table */
77#define TMDS_297M 297000
Ville Syrjälä606bb5e2015-10-08 11:43:34 +030078#define TMDS_296M 296703
Libin Yang4a21ef72015-09-02 14:11:39 +080079static const struct {
80 int sample_rate;
81 int clock;
82 int n;
83 int cts;
84} aud_ncts[] = {
85 { 44100, TMDS_296M, 4459, 234375 },
86 { 44100, TMDS_297M, 4704, 247500 },
87 { 48000, TMDS_296M, 5824, 281250 },
88 { 48000, TMDS_297M, 5120, 247500 },
89 { 32000, TMDS_296M, 5824, 421875 },
90 { 32000, TMDS_297M, 3072, 222750 },
91 { 88200, TMDS_296M, 8918, 234375 },
92 { 88200, TMDS_297M, 9408, 247500 },
93 { 96000, TMDS_296M, 11648, 281250 },
94 { 96000, TMDS_297M, 10240, 247500 },
95 { 176400, TMDS_296M, 17836, 234375 },
96 { 176400, TMDS_297M, 18816, 247500 },
97 { 192000, TMDS_296M, 23296, 281250 },
98 { 192000, TMDS_297M, 20480, 247500 },
99};
100
Jani Nikula7c10a2b2014-10-27 16:26:43 +0200101/* get AUD_CONFIG_PIXEL_CLOCK_HDMI_* value for mode */
Ville Syrjälä5e7234c2015-09-25 16:37:43 +0300102static u32 audio_config_hdmi_pixel_clock(const struct drm_display_mode *adjusted_mode)
Jani Nikula7c10a2b2014-10-27 16:26:43 +0200103{
104 int i;
105
106 for (i = 0; i < ARRAY_SIZE(hdmi_audio_clock); i++) {
Ville Syrjäläaad941d2015-09-25 16:38:56 +0300107 if (adjusted_mode->crtc_clock == hdmi_audio_clock[i].clock)
Jani Nikula7c10a2b2014-10-27 16:26:43 +0200108 break;
109 }
110
111 if (i == ARRAY_SIZE(hdmi_audio_clock)) {
Ville Syrjälä5e7234c2015-09-25 16:37:43 +0300112 DRM_DEBUG_KMS("HDMI audio pixel clock setting for %d not found, falling back to defaults\n",
Ville Syrjäläaad941d2015-09-25 16:38:56 +0300113 adjusted_mode->crtc_clock);
Jani Nikula7c10a2b2014-10-27 16:26:43 +0200114 i = 1;
115 }
116
117 DRM_DEBUG_KMS("Configuring HDMI audio for pixel clock %d (0x%08x)\n",
118 hdmi_audio_clock[i].clock,
119 hdmi_audio_clock[i].config);
120
121 return hdmi_audio_clock[i].config;
122}
123
Libin Yang4a21ef72015-09-02 14:11:39 +0800124static int audio_config_get_n(const struct drm_display_mode *mode, int rate)
125{
126 int i;
127
128 for (i = 0; i < ARRAY_SIZE(aud_ncts); i++) {
129 if ((rate == aud_ncts[i].sample_rate) &&
130 (mode->clock == aud_ncts[i].clock)) {
131 return aud_ncts[i].n;
132 }
133 }
134 return 0;
135}
136
Libin Yang7e8275c2015-09-25 09:36:12 +0800137static uint32_t audio_config_setup_n_reg(int n, uint32_t val)
138{
139 int n_low, n_up;
140 uint32_t tmp = val;
141
142 n_low = n & 0xfff;
143 n_up = (n >> 12) & 0xff;
144 tmp &= ~(AUD_CONFIG_UPPER_N_MASK | AUD_CONFIG_LOWER_N_MASK);
145 tmp |= ((n_up << AUD_CONFIG_UPPER_N_SHIFT) |
146 (n_low << AUD_CONFIG_LOWER_N_SHIFT) |
147 AUD_CONFIG_N_PROG_ENABLE);
148 return tmp;
149}
150
Libin Yang4a21ef72015-09-02 14:11:39 +0800151/* check whether N/CTS/M need be set manually */
152static bool audio_rate_need_prog(struct intel_crtc *crtc,
Takashi Iwai87f77ef2015-09-30 09:39:01 +0200153 const struct drm_display_mode *mode)
Libin Yang4a21ef72015-09-02 14:11:39 +0800154{
155 if (((mode->clock == TMDS_297M) ||
156 (mode->clock == TMDS_296M)) &&
157 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
158 return true;
159 else
160 return false;
161}
162
Jani Nikula7c10a2b2014-10-27 16:26:43 +0200163static bool intel_eld_uptodate(struct drm_connector *connector,
Ville Syrjäläf0f59a02015-11-18 15:33:26 +0200164 i915_reg_t reg_eldv, uint32_t bits_eldv,
165 i915_reg_t reg_elda, uint32_t bits_elda,
166 i915_reg_t reg_edid)
Jani Nikula7c10a2b2014-10-27 16:26:43 +0200167{
168 struct drm_i915_private *dev_priv = connector->dev->dev_private;
169 uint8_t *eld = connector->eld;
Jani Nikulaf9f682a2014-10-27 16:26:45 +0200170 uint32_t tmp;
171 int i;
Jani Nikula7c10a2b2014-10-27 16:26:43 +0200172
Jani Nikulaf9f682a2014-10-27 16:26:45 +0200173 tmp = I915_READ(reg_eldv);
174 tmp &= bits_eldv;
Jani Nikula7c10a2b2014-10-27 16:26:43 +0200175
Jani Nikulaf9f682a2014-10-27 16:26:45 +0200176 if (!tmp)
Jani Nikula7c10a2b2014-10-27 16:26:43 +0200177 return false;
178
Jani Nikulaf9f682a2014-10-27 16:26:45 +0200179 tmp = I915_READ(reg_elda);
180 tmp &= ~bits_elda;
181 I915_WRITE(reg_elda, tmp);
Jani Nikula7c10a2b2014-10-27 16:26:43 +0200182
Jani Nikula938fd8a2014-10-28 16:20:48 +0200183 for (i = 0; i < drm_eld_size(eld) / 4; i++)
Jani Nikula7c10a2b2014-10-27 16:26:43 +0200184 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
185 return false;
186
187 return true;
188}
189
Jani Nikula76d8d3e2014-10-27 16:26:57 +0200190static void g4x_audio_codec_disable(struct intel_encoder *encoder)
191{
192 struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
193 uint32_t eldv, tmp;
194
195 DRM_DEBUG_KMS("Disable audio codec\n");
196
197 tmp = I915_READ(G4X_AUD_VID_DID);
198 if (tmp == INTEL_AUDIO_DEVBLC || tmp == INTEL_AUDIO_DEVCL)
199 eldv = G4X_ELDV_DEVCL_DEVBLC;
200 else
201 eldv = G4X_ELDV_DEVCTG;
202
203 /* Invalidate ELD */
204 tmp = I915_READ(G4X_AUD_CNTL_ST);
205 tmp &= ~eldv;
206 I915_WRITE(G4X_AUD_CNTL_ST, tmp);
207}
208
Jani Nikula69bfe1a2014-10-27 16:26:50 +0200209static void g4x_audio_codec_enable(struct drm_connector *connector,
210 struct intel_encoder *encoder,
Ville Syrjälä5e7234c2015-09-25 16:37:43 +0300211 const struct drm_display_mode *adjusted_mode)
Jani Nikula7c10a2b2014-10-27 16:26:43 +0200212{
213 struct drm_i915_private *dev_priv = connector->dev->dev_private;
214 uint8_t *eld = connector->eld;
215 uint32_t eldv;
Jani Nikulaf9f682a2014-10-27 16:26:45 +0200216 uint32_t tmp;
217 int len, i;
Jani Nikula7c10a2b2014-10-27 16:26:43 +0200218
Jani Nikulad5ee08d2014-10-27 16:26:58 +0200219 DRM_DEBUG_KMS("Enable audio codec, %u bytes ELD\n", eld[2]);
220
Jani Nikulaf9f682a2014-10-27 16:26:45 +0200221 tmp = I915_READ(G4X_AUD_VID_DID);
222 if (tmp == INTEL_AUDIO_DEVBLC || tmp == INTEL_AUDIO_DEVCL)
Jani Nikula7c10a2b2014-10-27 16:26:43 +0200223 eldv = G4X_ELDV_DEVCL_DEVBLC;
224 else
225 eldv = G4X_ELDV_DEVCTG;
226
227 if (intel_eld_uptodate(connector,
228 G4X_AUD_CNTL_ST, eldv,
Jani Nikulac46f1112014-10-27 16:26:52 +0200229 G4X_AUD_CNTL_ST, G4X_ELD_ADDR_MASK,
Jani Nikula7c10a2b2014-10-27 16:26:43 +0200230 G4X_HDMIW_HDMIEDID))
231 return;
232
Jani Nikulaf9f682a2014-10-27 16:26:45 +0200233 tmp = I915_READ(G4X_AUD_CNTL_ST);
Jani Nikulac46f1112014-10-27 16:26:52 +0200234 tmp &= ~(eldv | G4X_ELD_ADDR_MASK);
Jani Nikulaf9f682a2014-10-27 16:26:45 +0200235 len = (tmp >> 9) & 0x1f; /* ELD buffer size */
236 I915_WRITE(G4X_AUD_CNTL_ST, tmp);
Jani Nikula7c10a2b2014-10-27 16:26:43 +0200237
Jani Nikula938fd8a2014-10-28 16:20:48 +0200238 len = min(drm_eld_size(eld) / 4, len);
Jani Nikula7c10a2b2014-10-27 16:26:43 +0200239 DRM_DEBUG_DRIVER("ELD size %d\n", len);
240 for (i = 0; i < len; i++)
241 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
242
Jani Nikulaf9f682a2014-10-27 16:26:45 +0200243 tmp = I915_READ(G4X_AUD_CNTL_ST);
244 tmp |= eldv;
245 I915_WRITE(G4X_AUD_CNTL_ST, tmp);
Jani Nikula7c10a2b2014-10-27 16:26:43 +0200246}
247
Jani Nikula69bfe1a2014-10-27 16:26:50 +0200248static void hsw_audio_codec_disable(struct intel_encoder *encoder)
249{
Jani Nikula5fad84a2014-11-04 10:30:23 +0200250 struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
251 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
252 enum pipe pipe = intel_crtc->pipe;
Jani Nikula69bfe1a2014-10-27 16:26:50 +0200253 uint32_t tmp;
254
Jani Nikula5fad84a2014-11-04 10:30:23 +0200255 DRM_DEBUG_KMS("Disable audio codec on pipe %c\n", pipe_name(pipe));
256
Libin Yang4a21ef72015-09-02 14:11:39 +0800257 mutex_lock(&dev_priv->av_mutex);
258
Jani Nikula5fad84a2014-11-04 10:30:23 +0200259 /* Disable timestamps */
260 tmp = I915_READ(HSW_AUD_CFG(pipe));
261 tmp &= ~AUD_CONFIG_N_VALUE_INDEX;
262 tmp |= AUD_CONFIG_N_PROG_ENABLE;
263 tmp &= ~AUD_CONFIG_UPPER_N_MASK;
264 tmp &= ~AUD_CONFIG_LOWER_N_MASK;
Libin Yang3d52ccf2015-12-02 14:09:44 +0800265 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DISPLAYPORT) ||
266 intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DP_MST))
Jani Nikula5fad84a2014-11-04 10:30:23 +0200267 tmp |= AUD_CONFIG_N_VALUE_INDEX;
268 I915_WRITE(HSW_AUD_CFG(pipe), tmp);
269
270 /* Invalidate ELD */
Jani Nikula69bfe1a2014-10-27 16:26:50 +0200271 tmp = I915_READ(HSW_AUD_PIN_ELD_CP_VLD);
Jani Nikula82910ac2014-10-27 16:26:59 +0200272 tmp &= ~AUDIO_ELD_VALID(pipe);
Jani Nikulaeb45fa02014-11-18 12:11:29 +0200273 tmp &= ~AUDIO_OUTPUT_ENABLE(pipe);
Jani Nikula69bfe1a2014-10-27 16:26:50 +0200274 I915_WRITE(HSW_AUD_PIN_ELD_CP_VLD, tmp);
Libin Yang4a21ef72015-09-02 14:11:39 +0800275
276 mutex_unlock(&dev_priv->av_mutex);
Jani Nikula69bfe1a2014-10-27 16:26:50 +0200277}
278
279static void hsw_audio_codec_enable(struct drm_connector *connector,
280 struct intel_encoder *encoder,
Ville Syrjälä5e7234c2015-09-25 16:37:43 +0300281 const struct drm_display_mode *adjusted_mode)
Jani Nikula7c10a2b2014-10-27 16:26:43 +0200282{
283 struct drm_i915_private *dev_priv = connector->dev->dev_private;
Jani Nikula820d2d72014-10-27 16:26:47 +0200284 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
Jani Nikula5fad84a2014-11-04 10:30:23 +0200285 enum pipe pipe = intel_crtc->pipe;
Libin Yang7e8275c2015-09-25 09:36:12 +0800286 struct i915_audio_component *acomp = dev_priv->audio_component;
Jani Nikula5fad84a2014-11-04 10:30:23 +0200287 const uint8_t *eld = connector->eld;
Libin Yang7e8275c2015-09-25 09:36:12 +0800288 struct intel_digital_port *intel_dig_port =
289 enc_to_dig_port(&encoder->base);
290 enum port port = intel_dig_port->port;
Jani Nikulaf9f682a2014-10-27 16:26:45 +0200291 uint32_t tmp;
292 int len, i;
Libin Yang7e8275c2015-09-25 09:36:12 +0800293 int n, rate;
Jani Nikula7c10a2b2014-10-27 16:26:43 +0200294
Jani Nikula5fad84a2014-11-04 10:30:23 +0200295 DRM_DEBUG_KMS("Enable audio codec on pipe %c, %u bytes ELD\n",
Jani Nikula938fd8a2014-10-28 16:20:48 +0200296 pipe_name(pipe), drm_eld_size(eld));
Jani Nikula7c10a2b2014-10-27 16:26:43 +0200297
Libin Yang4a21ef72015-09-02 14:11:39 +0800298 mutex_lock(&dev_priv->av_mutex);
299
Jani Nikula5fad84a2014-11-04 10:30:23 +0200300 /* Enable audio presence detect, invalidate ELD */
Jani Nikula69bfe1a2014-10-27 16:26:50 +0200301 tmp = I915_READ(HSW_AUD_PIN_ELD_CP_VLD);
Jani Nikula82910ac2014-10-27 16:26:59 +0200302 tmp |= AUDIO_OUTPUT_ENABLE(pipe);
303 tmp &= ~AUDIO_ELD_VALID(pipe);
Jani Nikula69bfe1a2014-10-27 16:26:50 +0200304 I915_WRITE(HSW_AUD_PIN_ELD_CP_VLD, tmp);
Jani Nikula5fad84a2014-11-04 10:30:23 +0200305
306 /*
307 * FIXME: We're supposed to wait for vblank here, but we have vblanks
308 * disabled during the mode set. The proper fix would be to push the
309 * rest of the setup into a vblank work item, queued here, but the
310 * infrastructure is not there yet.
311 */
312
313 /* Reset ELD write address */
314 tmp = I915_READ(HSW_AUD_DIP_ELD_CTRL(pipe));
315 tmp &= ~IBX_ELD_ADDRESS_MASK;
316 I915_WRITE(HSW_AUD_DIP_ELD_CTRL(pipe), tmp);
317
318 /* Up to 84 bytes of hw ELD buffer */
Jani Nikula938fd8a2014-10-28 16:20:48 +0200319 len = min(drm_eld_size(eld), 84);
320 for (i = 0; i < len / 4; i++)
Jani Nikula5fad84a2014-11-04 10:30:23 +0200321 I915_WRITE(HSW_AUD_EDID_DATA(pipe), *((uint32_t *)eld + i));
322
323 /* ELD valid */
324 tmp = I915_READ(HSW_AUD_PIN_ELD_CP_VLD);
Jani Nikula82910ac2014-10-27 16:26:59 +0200325 tmp |= AUDIO_ELD_VALID(pipe);
Jani Nikula5fad84a2014-11-04 10:30:23 +0200326 I915_WRITE(HSW_AUD_PIN_ELD_CP_VLD, tmp);
327
328 /* Enable timestamps */
329 tmp = I915_READ(HSW_AUD_CFG(pipe));
330 tmp &= ~AUD_CONFIG_N_VALUE_INDEX;
Jani Nikula5fad84a2014-11-04 10:30:23 +0200331 tmp &= ~AUD_CONFIG_PIXEL_CLOCK_HDMI_MASK;
332 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DISPLAYPORT))
333 tmp |= AUD_CONFIG_N_VALUE_INDEX;
334 else
Ville Syrjälä5e7234c2015-09-25 16:37:43 +0300335 tmp |= audio_config_hdmi_pixel_clock(adjusted_mode);
Libin Yang7e8275c2015-09-25 09:36:12 +0800336
337 tmp &= ~AUD_CONFIG_N_PROG_ENABLE;
Daniel Vetter28446592015-10-07 15:34:15 +0200338 if (audio_rate_need_prog(intel_crtc, adjusted_mode)) {
Libin Yang7e8275c2015-09-25 09:36:12 +0800339 if (!acomp)
340 rate = 0;
341 else if (port >= PORT_A && port <= PORT_E)
342 rate = acomp->aud_sample_rate[port];
343 else {
344 DRM_ERROR("invalid port: %d\n", port);
345 rate = 0;
346 }
Daniel Vetter28446592015-10-07 15:34:15 +0200347 n = audio_config_get_n(adjusted_mode, rate);
Libin Yang7e8275c2015-09-25 09:36:12 +0800348 if (n != 0)
349 tmp = audio_config_setup_n_reg(n, tmp);
350 else
351 DRM_DEBUG_KMS("no suitable N value is found\n");
352 }
353
Jani Nikula5fad84a2014-11-04 10:30:23 +0200354 I915_WRITE(HSW_AUD_CFG(pipe), tmp);
Libin Yang4a21ef72015-09-02 14:11:39 +0800355
356 mutex_unlock(&dev_priv->av_mutex);
Jani Nikula7c10a2b2014-10-27 16:26:43 +0200357}
358
Jani Nikula495a5bb2014-10-27 16:26:55 +0200359static void ilk_audio_codec_disable(struct intel_encoder *encoder)
360{
361 struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
362 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
363 struct intel_digital_port *intel_dig_port =
364 enc_to_dig_port(&encoder->base);
365 enum port port = intel_dig_port->port;
366 enum pipe pipe = intel_crtc->pipe;
367 uint32_t tmp, eldv;
Ville Syrjäläf0f59a02015-11-18 15:33:26 +0200368 i915_reg_t aud_config, aud_cntrl_st2;
Jani Nikula495a5bb2014-10-27 16:26:55 +0200369
370 DRM_DEBUG_KMS("Disable audio codec on port %c, pipe %c\n",
371 port_name(port), pipe_name(pipe));
372
Jani Nikulad3902c32015-05-04 17:20:49 +0300373 if (WARN_ON(port == PORT_A))
374 return;
375
Jani Nikula495a5bb2014-10-27 16:26:55 +0200376 if (HAS_PCH_IBX(dev_priv->dev)) {
377 aud_config = IBX_AUD_CFG(pipe);
378 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
Wayne Boyer666a4532015-12-09 12:29:35 -0800379 } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
Jani Nikula495a5bb2014-10-27 16:26:55 +0200380 aud_config = VLV_AUD_CFG(pipe);
381 aud_cntrl_st2 = VLV_AUD_CNTL_ST2;
382 } else {
383 aud_config = CPT_AUD_CFG(pipe);
384 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
385 }
386
387 /* Disable timestamps */
388 tmp = I915_READ(aud_config);
389 tmp &= ~AUD_CONFIG_N_VALUE_INDEX;
390 tmp |= AUD_CONFIG_N_PROG_ENABLE;
391 tmp &= ~AUD_CONFIG_UPPER_N_MASK;
392 tmp &= ~AUD_CONFIG_LOWER_N_MASK;
393 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DISPLAYPORT))
394 tmp |= AUD_CONFIG_N_VALUE_INDEX;
395 I915_WRITE(aud_config, tmp);
396
Jani Nikulad3902c32015-05-04 17:20:49 +0300397 eldv = IBX_ELD_VALID(port);
Jani Nikula495a5bb2014-10-27 16:26:55 +0200398
399 /* Invalidate ELD */
400 tmp = I915_READ(aud_cntrl_st2);
401 tmp &= ~eldv;
402 I915_WRITE(aud_cntrl_st2, tmp);
403}
404
Jani Nikula69bfe1a2014-10-27 16:26:50 +0200405static void ilk_audio_codec_enable(struct drm_connector *connector,
406 struct intel_encoder *encoder,
Ville Syrjälä5e7234c2015-09-25 16:37:43 +0300407 const struct drm_display_mode *adjusted_mode)
Jani Nikula7c10a2b2014-10-27 16:26:43 +0200408{
409 struct drm_i915_private *dev_priv = connector->dev->dev_private;
Jani Nikula820d2d72014-10-27 16:26:47 +0200410 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
Jani Nikulac6bde932014-11-04 10:31:28 +0200411 struct intel_digital_port *intel_dig_port =
412 enc_to_dig_port(&encoder->base);
413 enum port port = intel_dig_port->port;
414 enum pipe pipe = intel_crtc->pipe;
Jani Nikula7c10a2b2014-10-27 16:26:43 +0200415 uint8_t *eld = connector->eld;
416 uint32_t eldv;
Jani Nikulaf9f682a2014-10-27 16:26:45 +0200417 uint32_t tmp;
418 int len, i;
Ville Syrjäläf0f59a02015-11-18 15:33:26 +0200419 i915_reg_t hdmiw_hdmiedid, aud_config, aud_cntl_st, aud_cntrl_st2;
Jani Nikulac6bde932014-11-04 10:31:28 +0200420
421 DRM_DEBUG_KMS("Enable audio codec on port %c, pipe %c, %u bytes ELD\n",
Jani Nikula938fd8a2014-10-28 16:20:48 +0200422 port_name(port), pipe_name(pipe), drm_eld_size(eld));
Jani Nikulac6bde932014-11-04 10:31:28 +0200423
Jani Nikulad3902c32015-05-04 17:20:49 +0300424 if (WARN_ON(port == PORT_A))
425 return;
426
Jani Nikulac6bde932014-11-04 10:31:28 +0200427 /*
428 * FIXME: We're supposed to wait for vblank here, but we have vblanks
429 * disabled during the mode set. The proper fix would be to push the
430 * rest of the setup into a vblank work item, queued here, but the
431 * infrastructure is not there yet.
432 */
Jani Nikula7c10a2b2014-10-27 16:26:43 +0200433
434 if (HAS_PCH_IBX(connector->dev)) {
435 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
436 aud_config = IBX_AUD_CFG(pipe);
437 aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
438 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
Wayne Boyer666a4532015-12-09 12:29:35 -0800439 } else if (IS_VALLEYVIEW(connector->dev) ||
440 IS_CHERRYVIEW(connector->dev)) {
Jani Nikula7c10a2b2014-10-27 16:26:43 +0200441 hdmiw_hdmiedid = VLV_HDMIW_HDMIEDID(pipe);
442 aud_config = VLV_AUD_CFG(pipe);
443 aud_cntl_st = VLV_AUD_CNTL_ST(pipe);
444 aud_cntrl_st2 = VLV_AUD_CNTL_ST2;
445 } else {
446 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);
447 aud_config = CPT_AUD_CFG(pipe);
448 aud_cntl_st = CPT_AUD_CNTL_ST(pipe);
449 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
450 }
451
Jani Nikulad3902c32015-05-04 17:20:49 +0300452 eldv = IBX_ELD_VALID(port);
Jani Nikula7c10a2b2014-10-27 16:26:43 +0200453
Jani Nikulac6bde932014-11-04 10:31:28 +0200454 /* Invalidate ELD */
Jani Nikulaf9f682a2014-10-27 16:26:45 +0200455 tmp = I915_READ(aud_cntrl_st2);
456 tmp &= ~eldv;
457 I915_WRITE(aud_cntrl_st2, tmp);
Jani Nikula7c10a2b2014-10-27 16:26:43 +0200458
Jani Nikulac6bde932014-11-04 10:31:28 +0200459 /* Reset ELD write address */
Jani Nikulaf9f682a2014-10-27 16:26:45 +0200460 tmp = I915_READ(aud_cntl_st);
Jani Nikulac46f1112014-10-27 16:26:52 +0200461 tmp &= ~IBX_ELD_ADDRESS_MASK;
Jani Nikulaf9f682a2014-10-27 16:26:45 +0200462 I915_WRITE(aud_cntl_st, tmp);
Jani Nikula7c10a2b2014-10-27 16:26:43 +0200463
Jani Nikulac6bde932014-11-04 10:31:28 +0200464 /* Up to 84 bytes of hw ELD buffer */
Jani Nikula938fd8a2014-10-28 16:20:48 +0200465 len = min(drm_eld_size(eld), 84);
466 for (i = 0; i < len / 4; i++)
Jani Nikula7c10a2b2014-10-27 16:26:43 +0200467 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
468
Jani Nikulac6bde932014-11-04 10:31:28 +0200469 /* ELD valid */
Jani Nikulaf9f682a2014-10-27 16:26:45 +0200470 tmp = I915_READ(aud_cntrl_st2);
471 tmp |= eldv;
472 I915_WRITE(aud_cntrl_st2, tmp);
Jani Nikulac6bde932014-11-04 10:31:28 +0200473
474 /* Enable timestamps */
475 tmp = I915_READ(aud_config);
476 tmp &= ~AUD_CONFIG_N_VALUE_INDEX;
477 tmp &= ~AUD_CONFIG_N_PROG_ENABLE;
478 tmp &= ~AUD_CONFIG_PIXEL_CLOCK_HDMI_MASK;
Libin Yang3d52ccf2015-12-02 14:09:44 +0800479 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DISPLAYPORT) ||
480 intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DP_MST))
Jani Nikulac6bde932014-11-04 10:31:28 +0200481 tmp |= AUD_CONFIG_N_VALUE_INDEX;
482 else
Ville Syrjälä5e7234c2015-09-25 16:37:43 +0300483 tmp |= audio_config_hdmi_pixel_clock(adjusted_mode);
Jani Nikulac6bde932014-11-04 10:31:28 +0200484 I915_WRITE(aud_config, tmp);
Jani Nikula7c10a2b2014-10-27 16:26:43 +0200485}
486
Jani Nikula69bfe1a2014-10-27 16:26:50 +0200487/**
488 * intel_audio_codec_enable - Enable the audio codec for HD audio
489 * @intel_encoder: encoder on which to enable audio
490 *
491 * The enable sequences may only be performed after enabling the transcoder and
492 * port, and after completed link training.
493 */
494void intel_audio_codec_enable(struct intel_encoder *intel_encoder)
Jani Nikula7c10a2b2014-10-27 16:26:43 +0200495{
Jani Nikula33d1e7c62014-10-27 16:26:46 +0200496 struct drm_encoder *encoder = &intel_encoder->base;
497 struct intel_crtc *crtc = to_intel_crtc(encoder->crtc);
Ville Syrjälä7c5f93b2015-09-08 13:40:49 +0300498 const struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode;
Jani Nikula7c10a2b2014-10-27 16:26:43 +0200499 struct drm_connector *connector;
500 struct drm_device *dev = encoder->dev;
501 struct drm_i915_private *dev_priv = dev->dev_private;
David Henningsson51e1d832015-08-19 10:48:56 +0200502 struct i915_audio_component *acomp = dev_priv->audio_component;
503 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
504 enum port port = intel_dig_port->port;
Jani Nikula7c10a2b2014-10-27 16:26:43 +0200505
Ville Syrjälä9e5a3b52015-09-07 18:22:57 +0300506 connector = drm_select_eld(encoder);
Jani Nikula7c10a2b2014-10-27 16:26:43 +0200507 if (!connector)
508 return;
509
510 DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
511 connector->base.id,
512 connector->name,
513 connector->encoder->base.id,
514 connector->encoder->name);
515
Jani Nikula6189b032014-10-28 13:53:01 +0200516 /* ELD Conn_Type */
517 connector->eld[5] &= ~(3 << 2);
Libin Yang3d52ccf2015-12-02 14:09:44 +0800518 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
519 intel_pipe_has_type(crtc, INTEL_OUTPUT_DP_MST))
Jani Nikula6189b032014-10-28 13:53:01 +0200520 connector->eld[5] |= (1 << 2);
521
Ville Syrjälä124abe02015-09-08 13:40:45 +0300522 connector->eld[6] = drm_av_sync_delay(connector, adjusted_mode) / 2;
Jani Nikula7c10a2b2014-10-27 16:26:43 +0200523
Jani Nikula69bfe1a2014-10-27 16:26:50 +0200524 if (dev_priv->display.audio_codec_enable)
Ville Syrjälä124abe02015-09-08 13:40:45 +0300525 dev_priv->display.audio_codec_enable(connector, intel_encoder,
526 adjusted_mode);
David Henningsson51e1d832015-08-19 10:48:56 +0200527
Takashi Iwaicae666c2015-11-12 15:23:41 +0100528 mutex_lock(&dev_priv->av_mutex);
529 intel_dig_port->audio_connector = connector;
Takashi Iwai2f791902016-02-24 15:35:22 +0100530 /* referred in audio callbacks */
531 dev_priv->dig_port_map[port] = intel_encoder;
Takashi Iwaicae666c2015-11-12 15:23:41 +0100532 mutex_unlock(&dev_priv->av_mutex);
533
David Henningsson51e1d832015-08-19 10:48:56 +0200534 if (acomp && acomp->audio_ops && acomp->audio_ops->pin_eld_notify)
David Henningssonf0675d42015-09-03 11:51:34 +0200535 acomp->audio_ops->pin_eld_notify(acomp->audio_ops->audio_ptr, (int) port);
Jani Nikula69bfe1a2014-10-27 16:26:50 +0200536}
537
538/**
539 * intel_audio_codec_disable - Disable the audio codec for HD audio
Geliang Tang95d0be62015-09-15 06:04:36 -0700540 * @intel_encoder: encoder on which to disable audio
Jani Nikula69bfe1a2014-10-27 16:26:50 +0200541 *
542 * The disable sequences must be performed before disabling the transcoder or
543 * port.
544 */
David Henningsson51e1d832015-08-19 10:48:56 +0200545void intel_audio_codec_disable(struct intel_encoder *intel_encoder)
Jani Nikula69bfe1a2014-10-27 16:26:50 +0200546{
David Henningsson51e1d832015-08-19 10:48:56 +0200547 struct drm_encoder *encoder = &intel_encoder->base;
548 struct drm_device *dev = encoder->dev;
Jani Nikula69bfe1a2014-10-27 16:26:50 +0200549 struct drm_i915_private *dev_priv = dev->dev_private;
David Henningsson51e1d832015-08-19 10:48:56 +0200550 struct i915_audio_component *acomp = dev_priv->audio_component;
551 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
552 enum port port = intel_dig_port->port;
Jani Nikula69bfe1a2014-10-27 16:26:50 +0200553
554 if (dev_priv->display.audio_codec_disable)
David Henningsson51e1d832015-08-19 10:48:56 +0200555 dev_priv->display.audio_codec_disable(intel_encoder);
556
Takashi Iwaicae666c2015-11-12 15:23:41 +0100557 mutex_lock(&dev_priv->av_mutex);
558 intel_dig_port->audio_connector = NULL;
Takashi Iwai2f791902016-02-24 15:35:22 +0100559 dev_priv->dig_port_map[port] = NULL;
Takashi Iwaicae666c2015-11-12 15:23:41 +0100560 mutex_unlock(&dev_priv->av_mutex);
561
David Henningsson51e1d832015-08-19 10:48:56 +0200562 if (acomp && acomp->audio_ops && acomp->audio_ops->pin_eld_notify)
David Henningssonf0675d42015-09-03 11:51:34 +0200563 acomp->audio_ops->pin_eld_notify(acomp->audio_ops->audio_ptr, (int) port);
Jani Nikula7c10a2b2014-10-27 16:26:43 +0200564}
565
566/**
567 * intel_init_audio - Set up chip specific audio functions
568 * @dev: drm device
569 */
570void intel_init_audio(struct drm_device *dev)
571{
572 struct drm_i915_private *dev_priv = dev->dev_private;
573
Jani Nikula69bfe1a2014-10-27 16:26:50 +0200574 if (IS_G4X(dev)) {
575 dev_priv->display.audio_codec_enable = g4x_audio_codec_enable;
Jani Nikula76d8d3e2014-10-27 16:26:57 +0200576 dev_priv->display.audio_codec_disable = g4x_audio_codec_disable;
Wayne Boyer666a4532015-12-09 12:29:35 -0800577 } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
Jani Nikula69bfe1a2014-10-27 16:26:50 +0200578 dev_priv->display.audio_codec_enable = ilk_audio_codec_enable;
Jani Nikula495a5bb2014-10-27 16:26:55 +0200579 dev_priv->display.audio_codec_disable = ilk_audio_codec_disable;
Jani Nikula69bfe1a2014-10-27 16:26:50 +0200580 } else if (IS_HASWELL(dev) || INTEL_INFO(dev)->gen >= 8) {
581 dev_priv->display.audio_codec_enable = hsw_audio_codec_enable;
582 dev_priv->display.audio_codec_disable = hsw_audio_codec_disable;
583 } else if (HAS_PCH_SPLIT(dev)) {
584 dev_priv->display.audio_codec_enable = ilk_audio_codec_enable;
Jani Nikula495a5bb2014-10-27 16:26:55 +0200585 dev_priv->display.audio_codec_disable = ilk_audio_codec_disable;
Jani Nikula69bfe1a2014-10-27 16:26:50 +0200586 }
Jani Nikula7c10a2b2014-10-27 16:26:43 +0200587}
Imre Deak58fddc22015-01-08 17:54:14 +0200588
589static void i915_audio_component_get_power(struct device *dev)
590{
591 intel_display_power_get(dev_to_i915(dev), POWER_DOMAIN_AUDIO);
592}
593
594static void i915_audio_component_put_power(struct device *dev)
595{
596 intel_display_power_put(dev_to_i915(dev), POWER_DOMAIN_AUDIO);
597}
598
Lu, Han632f3ab2015-05-05 09:05:47 +0800599static void i915_audio_component_codec_wake_override(struct device *dev,
600 bool enable)
601{
602 struct drm_i915_private *dev_priv = dev_to_i915(dev);
603 u32 tmp;
604
Rodrigo Vivief11bdb2015-10-28 04:16:45 -0700605 if (!IS_SKYLAKE(dev_priv) && !IS_KABYLAKE(dev_priv))
Lu, Han632f3ab2015-05-05 09:05:47 +0800606 return;
607
608 /*
609 * Enable/disable generating the codec wake signal, overriding the
610 * internal logic to generate the codec wake to controller.
611 */
612 tmp = I915_READ(HSW_AUD_CHICKENBIT);
613 tmp &= ~SKL_AUD_CODEC_WAKE_SIGNAL;
614 I915_WRITE(HSW_AUD_CHICKENBIT, tmp);
615 usleep_range(1000, 1500);
616
617 if (enable) {
618 tmp = I915_READ(HSW_AUD_CHICKENBIT);
619 tmp |= SKL_AUD_CODEC_WAKE_SIGNAL;
620 I915_WRITE(HSW_AUD_CHICKENBIT, tmp);
621 usleep_range(1000, 1500);
622 }
623}
624
Imre Deak58fddc22015-01-08 17:54:14 +0200625/* Get CDCLK in kHz */
626static int i915_audio_component_get_cdclk_freq(struct device *dev)
627{
628 struct drm_i915_private *dev_priv = dev_to_i915(dev);
629 int ret;
630
631 if (WARN_ON_ONCE(!HAS_DDI(dev_priv)))
632 return -ENODEV;
633
634 intel_display_power_get(dev_priv, POWER_DOMAIN_AUDIO);
Ville Syrjälä1652d192015-03-31 14:12:01 +0300635 ret = dev_priv->display.get_display_clock_speed(dev_priv->dev);
636
Imre Deak58fddc22015-01-08 17:54:14 +0200637 intel_display_power_put(dev_priv, POWER_DOMAIN_AUDIO);
638
639 return ret;
640}
641
Libin Yang4a21ef72015-09-02 14:11:39 +0800642static int i915_audio_component_sync_audio_rate(struct device *dev,
643 int port, int rate)
644{
645 struct drm_i915_private *dev_priv = dev_to_i915(dev);
Libin Yang4a21ef72015-09-02 14:11:39 +0800646 struct intel_encoder *intel_encoder;
Libin Yang4a21ef72015-09-02 14:11:39 +0800647 struct intel_crtc *crtc;
648 struct drm_display_mode *mode;
Libin Yang7e8275c2015-09-25 09:36:12 +0800649 struct i915_audio_component *acomp = dev_priv->audio_component;
Takashi Iwai0bdf5a02015-11-30 18:19:39 +0100650 enum pipe pipe = INVALID_PIPE;
Libin Yang4a21ef72015-09-02 14:11:39 +0800651 u32 tmp;
Libin Yang7e8275c2015-09-25 09:36:12 +0800652 int n;
Takashi Iwai0bdf5a02015-11-30 18:19:39 +0100653 int err = 0;
Libin Yang4a21ef72015-09-02 14:11:39 +0800654
Rodrigo Vivief11bdb2015-10-28 04:16:45 -0700655 /* HSW, BDW, SKL, KBL need this fix */
Libin Yang4a21ef72015-09-02 14:11:39 +0800656 if (!IS_SKYLAKE(dev_priv) &&
Rodrigo Vivief11bdb2015-10-28 04:16:45 -0700657 !IS_KABYLAKE(dev_priv) &&
658 !IS_BROADWELL(dev_priv) &&
659 !IS_HASWELL(dev_priv))
Libin Yang4a21ef72015-09-02 14:11:39 +0800660 return 0;
661
662 mutex_lock(&dev_priv->av_mutex);
663 /* 1. get the pipe */
Takashi Iwai0bdf5a02015-11-30 18:19:39 +0100664 intel_encoder = dev_priv->dig_port_map[port];
665 /* intel_encoder might be NULL for DP MST */
666 if (!intel_encoder || !intel_encoder->base.crtc ||
667 intel_encoder->type != INTEL_OUTPUT_HDMI) {
668 DRM_DEBUG_KMS("no valid port %c\n", port_name(port));
669 err = -ENODEV;
670 goto unlock;
Libin Yang4a21ef72015-09-02 14:11:39 +0800671 }
Takashi Iwai0bdf5a02015-11-30 18:19:39 +0100672 crtc = to_intel_crtc(intel_encoder->base.crtc);
673 pipe = crtc->pipe;
Libin Yang4a21ef72015-09-02 14:11:39 +0800674 if (pipe == INVALID_PIPE) {
675 DRM_DEBUG_KMS("no pipe for the port %c\n", port_name(port));
Takashi Iwai0bdf5a02015-11-30 18:19:39 +0100676 err = -ENODEV;
677 goto unlock;
Libin Yang4a21ef72015-09-02 14:11:39 +0800678 }
Takashi Iwai0bdf5a02015-11-30 18:19:39 +0100679
Libin Yang4a21ef72015-09-02 14:11:39 +0800680 DRM_DEBUG_KMS("pipe %c connects port %c\n",
681 pipe_name(pipe), port_name(port));
682 mode = &crtc->config->base.adjusted_mode;
683
Libin Yang7e8275c2015-09-25 09:36:12 +0800684 /* port must be valid now, otherwise the pipe will be invalid */
685 acomp->aud_sample_rate[port] = rate;
686
Libin Yang4a21ef72015-09-02 14:11:39 +0800687 /* 2. check whether to set the N/CTS/M manually or not */
688 if (!audio_rate_need_prog(crtc, mode)) {
689 tmp = I915_READ(HSW_AUD_CFG(pipe));
690 tmp &= ~AUD_CONFIG_N_PROG_ENABLE;
691 I915_WRITE(HSW_AUD_CFG(pipe), tmp);
Takashi Iwai0bdf5a02015-11-30 18:19:39 +0100692 goto unlock;
Libin Yang4a21ef72015-09-02 14:11:39 +0800693 }
694
695 n = audio_config_get_n(mode, rate);
696 if (n == 0) {
697 DRM_DEBUG_KMS("Using automatic mode for N value on port %c\n",
698 port_name(port));
699 tmp = I915_READ(HSW_AUD_CFG(pipe));
700 tmp &= ~AUD_CONFIG_N_PROG_ENABLE;
701 I915_WRITE(HSW_AUD_CFG(pipe), tmp);
Takashi Iwai0bdf5a02015-11-30 18:19:39 +0100702 goto unlock;
Libin Yang4a21ef72015-09-02 14:11:39 +0800703 }
Libin Yang4a21ef72015-09-02 14:11:39 +0800704
Libin Yang7e8275c2015-09-25 09:36:12 +0800705 /* 3. set the N/CTS/M */
Libin Yang4a21ef72015-09-02 14:11:39 +0800706 tmp = I915_READ(HSW_AUD_CFG(pipe));
Libin Yang7e8275c2015-09-25 09:36:12 +0800707 tmp = audio_config_setup_n_reg(n, tmp);
Libin Yang4a21ef72015-09-02 14:11:39 +0800708 I915_WRITE(HSW_AUD_CFG(pipe), tmp);
709
Takashi Iwai0bdf5a02015-11-30 18:19:39 +0100710 unlock:
Libin Yang4a21ef72015-09-02 14:11:39 +0800711 mutex_unlock(&dev_priv->av_mutex);
Takashi Iwai0bdf5a02015-11-30 18:19:39 +0100712 return err;
Libin Yang4a21ef72015-09-02 14:11:39 +0800713}
714
Takashi Iwaicae666c2015-11-12 15:23:41 +0100715static int i915_audio_component_get_eld(struct device *dev, int port,
716 bool *enabled,
717 unsigned char *buf, int max_bytes)
718{
719 struct drm_i915_private *dev_priv = dev_to_i915(dev);
Takashi Iwaicae666c2015-11-12 15:23:41 +0100720 struct intel_encoder *intel_encoder;
721 struct intel_digital_port *intel_dig_port;
722 const u8 *eld;
723 int ret = -EINVAL;
724
725 mutex_lock(&dev_priv->av_mutex);
Takashi Iwai0bdf5a02015-11-30 18:19:39 +0100726 intel_encoder = dev_priv->dig_port_map[port];
727 /* intel_encoder might be NULL for DP MST */
728 if (intel_encoder) {
729 ret = 0;
Takashi Iwaicae666c2015-11-12 15:23:41 +0100730 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
Takashi Iwai0bdf5a02015-11-30 18:19:39 +0100731 *enabled = intel_dig_port->audio_connector != NULL;
732 if (*enabled) {
Takashi Iwaicae666c2015-11-12 15:23:41 +0100733 eld = intel_dig_port->audio_connector->eld;
734 ret = drm_eld_size(eld);
735 memcpy(buf, eld, min(max_bytes, ret));
Takashi Iwaicae666c2015-11-12 15:23:41 +0100736 }
737 }
738
739 mutex_unlock(&dev_priv->av_mutex);
740 return ret;
Imre Deak58fddc22015-01-08 17:54:14 +0200741}
742
743static const struct i915_audio_component_ops i915_audio_component_ops = {
744 .owner = THIS_MODULE,
745 .get_power = i915_audio_component_get_power,
746 .put_power = i915_audio_component_put_power,
Lu, Han632f3ab2015-05-05 09:05:47 +0800747 .codec_wake_override = i915_audio_component_codec_wake_override,
Imre Deak58fddc22015-01-08 17:54:14 +0200748 .get_cdclk_freq = i915_audio_component_get_cdclk_freq,
Libin Yang4a21ef72015-09-02 14:11:39 +0800749 .sync_audio_rate = i915_audio_component_sync_audio_rate,
Takashi Iwaicae666c2015-11-12 15:23:41 +0100750 .get_eld = i915_audio_component_get_eld,
Imre Deak58fddc22015-01-08 17:54:14 +0200751};
752
753static int i915_audio_component_bind(struct device *i915_dev,
754 struct device *hda_dev, void *data)
755{
756 struct i915_audio_component *acomp = data;
David Henningsson51e1d832015-08-19 10:48:56 +0200757 struct drm_i915_private *dev_priv = dev_to_i915(i915_dev);
Libin Yang7e8275c2015-09-25 09:36:12 +0800758 int i;
Imre Deak58fddc22015-01-08 17:54:14 +0200759
760 if (WARN_ON(acomp->ops || acomp->dev))
761 return -EEXIST;
762
David Henningssond5f362a2015-09-03 11:51:35 +0200763 drm_modeset_lock_all(dev_priv->dev);
Imre Deak58fddc22015-01-08 17:54:14 +0200764 acomp->ops = &i915_audio_component_ops;
765 acomp->dev = i915_dev;
Libin Yang7e8275c2015-09-25 09:36:12 +0800766 BUILD_BUG_ON(MAX_PORTS != I915_MAX_PORTS);
767 for (i = 0; i < ARRAY_SIZE(acomp->aud_sample_rate); i++)
768 acomp->aud_sample_rate[i] = 0;
David Henningsson51e1d832015-08-19 10:48:56 +0200769 dev_priv->audio_component = acomp;
David Henningssond5f362a2015-09-03 11:51:35 +0200770 drm_modeset_unlock_all(dev_priv->dev);
Imre Deak58fddc22015-01-08 17:54:14 +0200771
772 return 0;
773}
774
775static void i915_audio_component_unbind(struct device *i915_dev,
776 struct device *hda_dev, void *data)
777{
778 struct i915_audio_component *acomp = data;
David Henningsson51e1d832015-08-19 10:48:56 +0200779 struct drm_i915_private *dev_priv = dev_to_i915(i915_dev);
Imre Deak58fddc22015-01-08 17:54:14 +0200780
David Henningssond5f362a2015-09-03 11:51:35 +0200781 drm_modeset_lock_all(dev_priv->dev);
Imre Deak58fddc22015-01-08 17:54:14 +0200782 acomp->ops = NULL;
783 acomp->dev = NULL;
David Henningsson51e1d832015-08-19 10:48:56 +0200784 dev_priv->audio_component = NULL;
David Henningssond5f362a2015-09-03 11:51:35 +0200785 drm_modeset_unlock_all(dev_priv->dev);
Imre Deak58fddc22015-01-08 17:54:14 +0200786}
787
788static const struct component_ops i915_audio_component_bind_ops = {
789 .bind = i915_audio_component_bind,
790 .unbind = i915_audio_component_unbind,
791};
792
793/**
794 * i915_audio_component_init - initialize and register the audio component
795 * @dev_priv: i915 device instance
796 *
797 * This will register with the component framework a child component which
798 * will bind dynamically to the snd_hda_intel driver's corresponding master
799 * component when the latter is registered. During binding the child
800 * initializes an instance of struct i915_audio_component which it receives
801 * from the master. The master can then start to use the interface defined by
802 * this struct. Each side can break the binding at any point by deregistering
803 * its own component after which each side's component unbind callback is
804 * called.
805 *
806 * We ignore any error during registration and continue with reduced
807 * functionality (i.e. without HDMI audio).
808 */
809void i915_audio_component_init(struct drm_i915_private *dev_priv)
810{
811 int ret;
812
813 ret = component_add(dev_priv->dev->dev, &i915_audio_component_bind_ops);
814 if (ret < 0) {
815 DRM_ERROR("failed to add audio component (%d)\n", ret);
816 /* continue with reduced functionality */
817 return;
818 }
819
820 dev_priv->audio_component_registered = true;
821}
822
823/**
824 * i915_audio_component_cleanup - deregister the audio component
825 * @dev_priv: i915 device instance
826 *
827 * Deregisters the audio component, breaking any existing binding to the
828 * corresponding snd_hda_intel driver's master component.
829 */
830void i915_audio_component_cleanup(struct drm_i915_private *dev_priv)
831{
832 if (!dev_priv->audio_component_registered)
833 return;
834
835 component_del(dev_priv->dev->dev, &i915_audio_component_bind_ops);
836 dev_priv->audio_component_registered = false;
837}