blob: 453ce106b5fc8e09ed41639383f938040e3db1f4 [file] [log] [blame]
Boojin Kimb7d861d2011-12-26 18:49:52 +09001/*
2 * Copyright (c) 2012 Samsung Electronics Co., Ltd.
3 * http://www.samsung.com
Jassi Brarb3040e42010-05-23 20:28:19 -07004 *
5 * Copyright (C) 2010 Samsung Electronics Co. Ltd.
6 * Jaswinder Singh <jassi.brar@samsung.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 */
13
Boojin Kimb7d861d2011-12-26 18:49:52 +090014#include <linux/kernel.h>
Jassi Brarb3040e42010-05-23 20:28:19 -070015#include <linux/io.h>
16#include <linux/init.h>
17#include <linux/slab.h>
18#include <linux/module.h>
Boojin Kimb7d861d2011-12-26 18:49:52 +090019#include <linux/string.h>
20#include <linux/delay.h>
21#include <linux/interrupt.h>
22#include <linux/dma-mapping.h>
Jassi Brarb3040e42010-05-23 20:28:19 -070023#include <linux/dmaengine.h>
Jassi Brarb3040e42010-05-23 20:28:19 -070024#include <linux/amba/bus.h>
25#include <linux/amba/pl330.h>
Boojin Kim1b9bb712011-09-02 09:44:30 +090026#include <linux/scatterlist.h>
Thomas Abraham93ed5542011-10-24 11:43:31 +020027#include <linux/of.h>
Padmavathi Vennaa80258f2013-02-14 09:10:06 +053028#include <linux/of_dma.h>
Sachin Kamatbcc7fa92013-03-04 14:36:27 +053029#include <linux/err.h>
Jassi Brarb3040e42010-05-23 20:28:19 -070030
Russell King - ARM Linuxd2ebfb32012-03-06 22:34:26 +000031#include "dmaengine.h"
Boojin Kimb7d861d2011-12-26 18:49:52 +090032#define PL330_MAX_CHAN 8
33#define PL330_MAX_IRQS 32
34#define PL330_MAX_PERI 32
35
Lars-Peter Clausenf0564c72014-07-06 20:32:19 +020036enum pl330_cachectrl {
37 CCTRL0, /* Noncacheable and nonbufferable */
38 CCTRL1, /* Bufferable only */
39 CCTRL2, /* Cacheable, but do not allocate */
40 CCTRL3, /* Cacheable and bufferable, but do not allocate */
41 INVALID1, /* AWCACHE = 0x1000 */
42 INVALID2,
43 CCTRL6, /* Cacheable write-through, allocate on writes only */
44 CCTRL7, /* Cacheable write-back, allocate on writes only */
Boojin Kimb7d861d2011-12-26 18:49:52 +090045};
46
47enum pl330_byteswap {
48 SWAP_NO,
49 SWAP_2,
50 SWAP_4,
51 SWAP_8,
52 SWAP_16,
53};
54
Boojin Kimb7d861d2011-12-26 18:49:52 +090055/* Register and Bit field Definitions */
56#define DS 0x0
57#define DS_ST_STOP 0x0
58#define DS_ST_EXEC 0x1
59#define DS_ST_CMISS 0x2
60#define DS_ST_UPDTPC 0x3
61#define DS_ST_WFE 0x4
62#define DS_ST_ATBRR 0x5
63#define DS_ST_QBUSY 0x6
64#define DS_ST_WFP 0x7
65#define DS_ST_KILL 0x8
66#define DS_ST_CMPLT 0x9
67#define DS_ST_FLTCMP 0xe
68#define DS_ST_FAULT 0xf
69
70#define DPC 0x4
71#define INTEN 0x20
72#define ES 0x24
73#define INTSTATUS 0x28
74#define INTCLR 0x2c
75#define FSM 0x30
76#define FSC 0x34
77#define FTM 0x38
78
79#define _FTC 0x40
80#define FTC(n) (_FTC + (n)*0x4)
81
82#define _CS 0x100
83#define CS(n) (_CS + (n)*0x8)
84#define CS_CNS (1 << 21)
85
86#define _CPC 0x104
87#define CPC(n) (_CPC + (n)*0x8)
88
89#define _SA 0x400
90#define SA(n) (_SA + (n)*0x20)
91
92#define _DA 0x404
93#define DA(n) (_DA + (n)*0x20)
94
95#define _CC 0x408
96#define CC(n) (_CC + (n)*0x20)
97
98#define CC_SRCINC (1 << 0)
99#define CC_DSTINC (1 << 14)
100#define CC_SRCPRI (1 << 8)
101#define CC_DSTPRI (1 << 22)
102#define CC_SRCNS (1 << 9)
103#define CC_DSTNS (1 << 23)
104#define CC_SRCIA (1 << 10)
105#define CC_DSTIA (1 << 24)
106#define CC_SRCBRSTLEN_SHFT 4
107#define CC_DSTBRSTLEN_SHFT 18
108#define CC_SRCBRSTSIZE_SHFT 1
109#define CC_DSTBRSTSIZE_SHFT 15
110#define CC_SRCCCTRL_SHFT 11
111#define CC_SRCCCTRL_MASK 0x7
112#define CC_DSTCCTRL_SHFT 25
113#define CC_DRCCCTRL_MASK 0x7
114#define CC_SWAP_SHFT 28
115
116#define _LC0 0x40c
117#define LC0(n) (_LC0 + (n)*0x20)
118
119#define _LC1 0x410
120#define LC1(n) (_LC1 + (n)*0x20)
121
122#define DBGSTATUS 0xd00
123#define DBG_BUSY (1 << 0)
124
125#define DBGCMD 0xd04
126#define DBGINST0 0xd08
127#define DBGINST1 0xd0c
128
129#define CR0 0xe00
130#define CR1 0xe04
131#define CR2 0xe08
132#define CR3 0xe0c
133#define CR4 0xe10
134#define CRD 0xe14
135
136#define PERIPH_ID 0xfe0
Boojin Kim3ecf51a2011-12-26 18:55:47 +0900137#define PERIPH_REV_SHIFT 20
138#define PERIPH_REV_MASK 0xf
139#define PERIPH_REV_R0P0 0
140#define PERIPH_REV_R1P0 1
141#define PERIPH_REV_R1P1 2
Boojin Kimb7d861d2011-12-26 18:49:52 +0900142
143#define CR0_PERIPH_REQ_SET (1 << 0)
144#define CR0_BOOT_EN_SET (1 << 1)
145#define CR0_BOOT_MAN_NS (1 << 2)
146#define CR0_NUM_CHANS_SHIFT 4
147#define CR0_NUM_CHANS_MASK 0x7
148#define CR0_NUM_PERIPH_SHIFT 12
149#define CR0_NUM_PERIPH_MASK 0x1f
150#define CR0_NUM_EVENTS_SHIFT 17
151#define CR0_NUM_EVENTS_MASK 0x1f
152
153#define CR1_ICACHE_LEN_SHIFT 0
154#define CR1_ICACHE_LEN_MASK 0x7
155#define CR1_NUM_ICACHELINES_SHIFT 4
156#define CR1_NUM_ICACHELINES_MASK 0xf
157
158#define CRD_DATA_WIDTH_SHIFT 0
159#define CRD_DATA_WIDTH_MASK 0x7
160#define CRD_WR_CAP_SHIFT 4
161#define CRD_WR_CAP_MASK 0x7
162#define CRD_WR_Q_DEP_SHIFT 8
163#define CRD_WR_Q_DEP_MASK 0xf
164#define CRD_RD_CAP_SHIFT 12
165#define CRD_RD_CAP_MASK 0x7
166#define CRD_RD_Q_DEP_SHIFT 16
167#define CRD_RD_Q_DEP_MASK 0xf
168#define CRD_DATA_BUFF_SHIFT 20
169#define CRD_DATA_BUFF_MASK 0x3ff
170
171#define PART 0x330
172#define DESIGNER 0x41
173#define REVISION 0x0
174#define INTEG_CFG 0x0
175#define PERIPH_ID_VAL ((PART << 0) | (DESIGNER << 12))
176
Boojin Kimb7d861d2011-12-26 18:49:52 +0900177#define PL330_STATE_STOPPED (1 << 0)
178#define PL330_STATE_EXECUTING (1 << 1)
179#define PL330_STATE_WFE (1 << 2)
180#define PL330_STATE_FAULTING (1 << 3)
181#define PL330_STATE_COMPLETING (1 << 4)
182#define PL330_STATE_WFP (1 << 5)
183#define PL330_STATE_KILLING (1 << 6)
184#define PL330_STATE_FAULT_COMPLETING (1 << 7)
185#define PL330_STATE_CACHEMISS (1 << 8)
186#define PL330_STATE_UPDTPC (1 << 9)
187#define PL330_STATE_ATBARRIER (1 << 10)
188#define PL330_STATE_QUEUEBUSY (1 << 11)
189#define PL330_STATE_INVALID (1 << 15)
190
191#define PL330_STABLE_STATES (PL330_STATE_STOPPED | PL330_STATE_EXECUTING \
192 | PL330_STATE_WFE | PL330_STATE_FAULTING)
193
194#define CMD_DMAADDH 0x54
195#define CMD_DMAEND 0x00
196#define CMD_DMAFLUSHP 0x35
197#define CMD_DMAGO 0xa0
198#define CMD_DMALD 0x04
199#define CMD_DMALDP 0x25
200#define CMD_DMALP 0x20
201#define CMD_DMALPEND 0x28
202#define CMD_DMAKILL 0x01
203#define CMD_DMAMOV 0xbc
204#define CMD_DMANOP 0x18
205#define CMD_DMARMB 0x12
206#define CMD_DMASEV 0x34
207#define CMD_DMAST 0x08
208#define CMD_DMASTP 0x29
209#define CMD_DMASTZ 0x0c
210#define CMD_DMAWFE 0x36
211#define CMD_DMAWFP 0x30
212#define CMD_DMAWMB 0x13
213
214#define SZ_DMAADDH 3
215#define SZ_DMAEND 1
216#define SZ_DMAFLUSHP 2
217#define SZ_DMALD 1
218#define SZ_DMALDP 2
219#define SZ_DMALP 2
220#define SZ_DMALPEND 2
221#define SZ_DMAKILL 1
222#define SZ_DMAMOV 6
223#define SZ_DMANOP 1
224#define SZ_DMARMB 1
225#define SZ_DMASEV 2
226#define SZ_DMAST 1
227#define SZ_DMASTP 2
228#define SZ_DMASTZ 1
229#define SZ_DMAWFE 2
230#define SZ_DMAWFP 2
231#define SZ_DMAWMB 1
232#define SZ_DMAGO 6
233
234#define BRST_LEN(ccr) ((((ccr) >> CC_SRCBRSTLEN_SHFT) & 0xf) + 1)
235#define BRST_SIZE(ccr) (1 << (((ccr) >> CC_SRCBRSTSIZE_SHFT) & 0x7))
236
237#define BYTE_TO_BURST(b, ccr) ((b) / BRST_SIZE(ccr) / BRST_LEN(ccr))
238#define BURST_TO_BYTE(c, ccr) ((c) * BRST_SIZE(ccr) * BRST_LEN(ccr))
239
240/*
241 * With 256 bytes, we can do more than 2.5MB and 5MB xfers per req
242 * at 1byte/burst for P<->M and M<->M respectively.
243 * For typical scenario, at 1word/burst, 10MB and 20MB xfers per req
244 * should be enough for P<->M and M<->M respectively.
245 */
246#define MCODE_BUFF_PER_REQ 256
247
248/* If the _pl330_req is available to the client */
249#define IS_FREE(req) (*((u8 *)((req)->mc_cpu)) == CMD_DMAEND)
250
251/* Use this _only_ to wait on transient states */
252#define UNTIL(t, s) while (!(_state(t) & (s))) cpu_relax();
253
254#ifdef PL330_DEBUG_MCGEN
255static unsigned cmd_line;
256#define PL330_DBGCMD_DUMP(off, x...) do { \
257 printk("%x:", cmd_line); \
258 printk(x); \
259 cmd_line += off; \
260 } while (0)
261#define PL330_DBGMC_START(addr) (cmd_line = addr)
262#else
263#define PL330_DBGCMD_DUMP(off, x...) do {} while (0)
264#define PL330_DBGMC_START(addr) do {} while (0)
265#endif
266
267/* The number of default descriptors */
Russell King - ARM Linuxd2ebfb32012-03-06 22:34:26 +0000268
Jassi Brarb3040e42010-05-23 20:28:19 -0700269#define NR_DEFAULT_DESC 16
270
Boojin Kimb7d861d2011-12-26 18:49:52 +0900271/* Populated by the PL330 core driver for DMA API driver's info */
272struct pl330_config {
273 u32 periph_id;
Boojin Kimb7d861d2011-12-26 18:49:52 +0900274#define DMAC_MODE_NS (1 << 0)
275 unsigned int mode;
276 unsigned int data_bus_width:10; /* In number of bits */
277 unsigned int data_buf_dep:10;
278 unsigned int num_chan:4;
279 unsigned int num_peri:6;
280 u32 peri_ns;
281 unsigned int num_events:6;
282 u32 irq_ns;
283};
284
285/* Handle to the DMAC provided to the PL330 core */
286struct pl330_info {
287 /* Owning device */
288 struct device *dev;
289 /* Size of MicroCode buffers for each channel. */
290 unsigned mcbufsz;
291 /* ioremap'ed address of PL330 registers. */
292 void __iomem *base;
Boojin Kimb7d861d2011-12-26 18:49:52 +0900293 /* PL330 core data, Client must not touch it. */
294 void *pl330_data;
295 /* Populated by the PL330 core driver during pl330_add */
296 struct pl330_config pcfg;
Boojin Kimb7d861d2011-12-26 18:49:52 +0900297};
298
299/**
300 * Request Configuration.
301 * The PL330 core does not modify this and uses the last
302 * working configuration if the request doesn't provide any.
303 *
304 * The Client may want to provide this info only for the
305 * first request and a request with new settings.
306 */
307struct pl330_reqcfg {
308 /* Address Incrementing */
309 unsigned dst_inc:1;
310 unsigned src_inc:1;
311
312 /*
313 * For now, the SRC & DST protection levels
314 * and burst size/length are assumed same.
315 */
316 bool nonsecure;
317 bool privileged;
318 bool insnaccess;
319 unsigned brst_len:5;
320 unsigned brst_size:3; /* in power of 2 */
321
Lars-Peter Clausenf0564c72014-07-06 20:32:19 +0200322 enum pl330_cachectrl dcctl;
323 enum pl330_cachectrl scctl;
Boojin Kimb7d861d2011-12-26 18:49:52 +0900324 enum pl330_byteswap swap;
Boojin Kim3ecf51a2011-12-26 18:55:47 +0900325 struct pl330_config *pcfg;
Boojin Kimb7d861d2011-12-26 18:49:52 +0900326};
327
328/*
329 * One cycle of DMAC operation.
330 * There may be more than one xfer in a request.
331 */
332struct pl330_xfer {
333 u32 src_addr;
334 u32 dst_addr;
335 /* Size to xfer */
336 u32 bytes;
Boojin Kimb7d861d2011-12-26 18:49:52 +0900337};
338
339/* The xfer callbacks are made with one of these arguments. */
340enum pl330_op_err {
341 /* The all xfers in the request were success. */
342 PL330_ERR_NONE,
343 /* If req aborted due to global error. */
344 PL330_ERR_ABORT,
345 /* If req failed due to problem with Channel. */
346 PL330_ERR_FAIL,
347};
348
349/* A request defining Scatter-Gather List ending with NULL xfer. */
350struct pl330_req {
Lars-Peter Clausen585a9d02014-07-06 20:32:18 +0200351 enum dma_transfer_direction rqtype;
Boojin Kimb7d861d2011-12-26 18:49:52 +0900352 /* Index of peripheral for the xfer. */
353 unsigned peri:5;
354 /* Unique token for this xfer, set by the client. */
355 void *token;
356 /* Callback to be called after xfer. */
357 void (*xfer_cb)(void *token, enum pl330_op_err err);
358 /* If NULL, req will be done at last set parameters. */
359 struct pl330_reqcfg *cfg;
360 /* Pointer to first xfer in the request. */
361 struct pl330_xfer *x;
Javi Merinofdec53d2012-06-13 15:07:00 +0100362 /* Hook to attach to DMAC's list of reqs with due callback */
363 struct list_head rqd;
Boojin Kimb7d861d2011-12-26 18:49:52 +0900364};
365
Boojin Kimb7d861d2011-12-26 18:49:52 +0900366enum pl330_chan_op {
367 /* Start the channel */
368 PL330_OP_START,
369 /* Abort the active xfer */
370 PL330_OP_ABORT,
371 /* Stop xfer and flush queue */
372 PL330_OP_FLUSH,
373};
374
375struct _xfer_spec {
376 u32 ccr;
377 struct pl330_req *r;
378 struct pl330_xfer *x;
379};
380
381enum dmamov_dst {
382 SAR = 0,
383 CCR,
384 DAR,
385};
386
387enum pl330_dst {
388 SRC = 0,
389 DST,
390};
391
392enum pl330_cond {
393 SINGLE,
394 BURST,
395 ALWAYS,
396};
397
398struct _pl330_req {
399 u32 mc_bus;
400 void *mc_cpu;
Boojin Kimb7d861d2011-12-26 18:49:52 +0900401 struct pl330_req *r;
Boojin Kimb7d861d2011-12-26 18:49:52 +0900402};
403
404/* ToBeDone for tasklet */
405struct _pl330_tbd {
406 bool reset_dmac;
407 bool reset_mngr;
408 u8 reset_chan;
409};
410
411/* A DMAC Thread */
412struct pl330_thread {
413 u8 id;
414 int ev;
415 /* If the channel is not yet acquired by any client */
416 bool free;
417 /* Parent DMAC */
418 struct pl330_dmac *dmac;
419 /* Only two at a time */
420 struct _pl330_req req[2];
421 /* Index of the last enqueued request */
422 unsigned lstenq;
423 /* Index of the last submitted request or -1 if the DMA is stopped */
424 int req_running;
425};
426
427enum pl330_dmac_state {
428 UNINIT,
429 INIT,
430 DYING,
431};
432
433/* A DMAC */
434struct pl330_dmac {
435 spinlock_t lock;
436 /* Holds list of reqs with due callbacks */
437 struct list_head req_done;
438 /* Pointer to platform specific stuff */
439 struct pl330_info *pinfo;
440 /* Maximum possible events/irqs */
441 int events[32];
442 /* BUS address of MicroCode buffer */
Will Deaconfed8c452013-06-10 19:34:38 +0100443 dma_addr_t mcode_bus;
Boojin Kimb7d861d2011-12-26 18:49:52 +0900444 /* CPU address of MicroCode buffer */
445 void *mcode_cpu;
446 /* List of all Channel threads */
447 struct pl330_thread *channels;
448 /* Pointer to the MANAGER thread */
449 struct pl330_thread *manager;
450 /* To handle bad news in interrupt */
451 struct tasklet_struct tasks;
452 struct _pl330_tbd dmac_tbd;
453 /* State of DMAC operation */
454 enum pl330_dmac_state state;
455};
456
Jassi Brarb3040e42010-05-23 20:28:19 -0700457enum desc_status {
458 /* In the DMAC pool */
459 FREE,
460 /*
Masanari Iidad73111c2012-08-04 23:37:53 +0900461 * Allocated to some channel during prep_xxx
Jassi Brarb3040e42010-05-23 20:28:19 -0700462 * Also may be sitting on the work_list.
463 */
464 PREP,
465 /*
466 * Sitting on the work_list and already submitted
467 * to the PL330 core. Not more than two descriptors
468 * of a channel can be BUSY at any time.
469 */
470 BUSY,
471 /*
472 * Sitting on the channel work_list but xfer done
473 * by PL330 core
474 */
475 DONE,
476};
477
478struct dma_pl330_chan {
479 /* Schedule desc completion */
480 struct tasklet_struct task;
481
482 /* DMA-Engine Channel */
483 struct dma_chan chan;
484
Lars-Peter Clausen04abf5d2014-01-11 20:08:38 +0100485 /* List of submitted descriptors */
486 struct list_head submitted_list;
487 /* List of issued descriptors */
Jassi Brarb3040e42010-05-23 20:28:19 -0700488 struct list_head work_list;
Lars-Peter Clausen39ff8612013-08-27 20:34:05 +0200489 /* List of completed descriptors */
490 struct list_head completed_list;
Jassi Brarb3040e42010-05-23 20:28:19 -0700491
492 /* Pointer to the DMAC that manages this channel,
493 * NULL if the channel is available to be acquired.
494 * As the parent, this DMAC also provides descriptors
495 * to the channel.
496 */
497 struct dma_pl330_dmac *dmac;
498
499 /* To protect channel manipulation */
500 spinlock_t lock;
501
502 /* Token of a hardware channel thread of PL330 DMAC
503 * NULL if the channel is available to be acquired.
504 */
505 void *pl330_chid;
Boojin Kim1b9bb712011-09-02 09:44:30 +0900506
507 /* For D-to-M and M-to-D channels */
508 int burst_sz; /* the peripheral fifo width */
Boojin Kim1d0c1d62011-09-02 09:44:31 +0900509 int burst_len; /* the number of burst */
Boojin Kim1b9bb712011-09-02 09:44:30 +0900510 dma_addr_t fifo_addr;
Boojin Kim42bc9cf2011-09-02 09:44:33 +0900511
512 /* for cyclic capability */
513 bool cyclic;
Jassi Brarb3040e42010-05-23 20:28:19 -0700514};
515
516struct dma_pl330_dmac {
517 struct pl330_info pif;
518
519 /* DMA-Engine Device */
520 struct dma_device ddma;
521
Lars-Peter Clausenb714b842013-11-25 16:07:46 +0100522 /* Holds info about sg limitations */
523 struct device_dma_parameters dma_parms;
524
Jassi Brarb3040e42010-05-23 20:28:19 -0700525 /* Pool of descriptors available for the DMAC's channels */
526 struct list_head desc_pool;
527 /* To protect desc_pool manipulation */
528 spinlock_t pool_lock;
529
530 /* Peripheral channels connected to this DMAC */
Lars-Peter Clausen70cbb162014-01-11 20:08:39 +0100531 unsigned int num_peripherals;
Rob Herring4e0e6102011-07-25 16:05:04 -0500532 struct dma_pl330_chan *peripherals; /* keep at end */
Jassi Brarb3040e42010-05-23 20:28:19 -0700533};
534
535struct dma_pl330_desc {
536 /* To attach to a queue as child */
537 struct list_head node;
538
539 /* Descriptor for the DMA Engine API */
540 struct dma_async_tx_descriptor txd;
541
542 /* Xfer for PL330 core */
543 struct pl330_xfer px;
544
545 struct pl330_reqcfg rqcfg;
546 struct pl330_req req;
547
548 enum desc_status status;
549
550 /* The channel which currently holds this desc */
551 struct dma_pl330_chan *pchan;
552};
553
Boojin Kimb7d861d2011-12-26 18:49:52 +0900554static inline void _callback(struct pl330_req *r, enum pl330_op_err err)
555{
556 if (r && r->xfer_cb)
557 r->xfer_cb(r->token, err);
558}
559
560static inline bool _queue_empty(struct pl330_thread *thrd)
561{
562 return (IS_FREE(&thrd->req[0]) && IS_FREE(&thrd->req[1]))
563 ? true : false;
564}
565
566static inline bool _queue_full(struct pl330_thread *thrd)
567{
568 return (IS_FREE(&thrd->req[0]) || IS_FREE(&thrd->req[1]))
569 ? false : true;
570}
571
572static inline bool is_manager(struct pl330_thread *thrd)
573{
574 struct pl330_dmac *pl330 = thrd->dmac;
575
576 /* MANAGER is indexed at the end */
577 if (thrd->id == pl330->pinfo->pcfg.num_chan)
578 return true;
579 else
580 return false;
581}
582
583/* If manager of the thread is in Non-Secure mode */
584static inline bool _manager_ns(struct pl330_thread *thrd)
585{
586 struct pl330_dmac *pl330 = thrd->dmac;
587
588 return (pl330->pinfo->pcfg.mode & DMAC_MODE_NS) ? true : false;
589}
590
Boojin Kim3ecf51a2011-12-26 18:55:47 +0900591static inline u32 get_revision(u32 periph_id)
592{
593 return (periph_id >> PERIPH_REV_SHIFT) & PERIPH_REV_MASK;
594}
595
Boojin Kimb7d861d2011-12-26 18:49:52 +0900596static inline u32 _emit_ADDH(unsigned dry_run, u8 buf[],
597 enum pl330_dst da, u16 val)
598{
599 if (dry_run)
600 return SZ_DMAADDH;
601
602 buf[0] = CMD_DMAADDH;
603 buf[0] |= (da << 1);
604 *((u16 *)&buf[1]) = val;
605
606 PL330_DBGCMD_DUMP(SZ_DMAADDH, "\tDMAADDH %s %u\n",
607 da == 1 ? "DA" : "SA", val);
608
609 return SZ_DMAADDH;
610}
611
612static inline u32 _emit_END(unsigned dry_run, u8 buf[])
613{
614 if (dry_run)
615 return SZ_DMAEND;
616
617 buf[0] = CMD_DMAEND;
618
619 PL330_DBGCMD_DUMP(SZ_DMAEND, "\tDMAEND\n");
620
621 return SZ_DMAEND;
622}
623
624static inline u32 _emit_FLUSHP(unsigned dry_run, u8 buf[], u8 peri)
625{
626 if (dry_run)
627 return SZ_DMAFLUSHP;
628
629 buf[0] = CMD_DMAFLUSHP;
630
631 peri &= 0x1f;
632 peri <<= 3;
633 buf[1] = peri;
634
635 PL330_DBGCMD_DUMP(SZ_DMAFLUSHP, "\tDMAFLUSHP %u\n", peri >> 3);
636
637 return SZ_DMAFLUSHP;
638}
639
640static inline u32 _emit_LD(unsigned dry_run, u8 buf[], enum pl330_cond cond)
641{
642 if (dry_run)
643 return SZ_DMALD;
644
645 buf[0] = CMD_DMALD;
646
647 if (cond == SINGLE)
648 buf[0] |= (0 << 1) | (1 << 0);
649 else if (cond == BURST)
650 buf[0] |= (1 << 1) | (1 << 0);
651
652 PL330_DBGCMD_DUMP(SZ_DMALD, "\tDMALD%c\n",
653 cond == SINGLE ? 'S' : (cond == BURST ? 'B' : 'A'));
654
655 return SZ_DMALD;
656}
657
658static inline u32 _emit_LDP(unsigned dry_run, u8 buf[],
659 enum pl330_cond cond, u8 peri)
660{
661 if (dry_run)
662 return SZ_DMALDP;
663
664 buf[0] = CMD_DMALDP;
665
666 if (cond == BURST)
667 buf[0] |= (1 << 1);
668
669 peri &= 0x1f;
670 peri <<= 3;
671 buf[1] = peri;
672
673 PL330_DBGCMD_DUMP(SZ_DMALDP, "\tDMALDP%c %u\n",
674 cond == SINGLE ? 'S' : 'B', peri >> 3);
675
676 return SZ_DMALDP;
677}
678
679static inline u32 _emit_LP(unsigned dry_run, u8 buf[],
680 unsigned loop, u8 cnt)
681{
682 if (dry_run)
683 return SZ_DMALP;
684
685 buf[0] = CMD_DMALP;
686
687 if (loop)
688 buf[0] |= (1 << 1);
689
690 cnt--; /* DMAC increments by 1 internally */
691 buf[1] = cnt;
692
693 PL330_DBGCMD_DUMP(SZ_DMALP, "\tDMALP_%c %u\n", loop ? '1' : '0', cnt);
694
695 return SZ_DMALP;
696}
697
698struct _arg_LPEND {
699 enum pl330_cond cond;
700 bool forever;
701 unsigned loop;
702 u8 bjump;
703};
704
705static inline u32 _emit_LPEND(unsigned dry_run, u8 buf[],
706 const struct _arg_LPEND *arg)
707{
708 enum pl330_cond cond = arg->cond;
709 bool forever = arg->forever;
710 unsigned loop = arg->loop;
711 u8 bjump = arg->bjump;
712
713 if (dry_run)
714 return SZ_DMALPEND;
715
716 buf[0] = CMD_DMALPEND;
717
718 if (loop)
719 buf[0] |= (1 << 2);
720
721 if (!forever)
722 buf[0] |= (1 << 4);
723
724 if (cond == SINGLE)
725 buf[0] |= (0 << 1) | (1 << 0);
726 else if (cond == BURST)
727 buf[0] |= (1 << 1) | (1 << 0);
728
729 buf[1] = bjump;
730
731 PL330_DBGCMD_DUMP(SZ_DMALPEND, "\tDMALP%s%c_%c bjmpto_%x\n",
732 forever ? "FE" : "END",
733 cond == SINGLE ? 'S' : (cond == BURST ? 'B' : 'A'),
734 loop ? '1' : '0',
735 bjump);
736
737 return SZ_DMALPEND;
738}
739
740static inline u32 _emit_KILL(unsigned dry_run, u8 buf[])
741{
742 if (dry_run)
743 return SZ_DMAKILL;
744
745 buf[0] = CMD_DMAKILL;
746
747 return SZ_DMAKILL;
748}
749
750static inline u32 _emit_MOV(unsigned dry_run, u8 buf[],
751 enum dmamov_dst dst, u32 val)
752{
753 if (dry_run)
754 return SZ_DMAMOV;
755
756 buf[0] = CMD_DMAMOV;
757 buf[1] = dst;
758 *((u32 *)&buf[2]) = val;
759
760 PL330_DBGCMD_DUMP(SZ_DMAMOV, "\tDMAMOV %s 0x%x\n",
761 dst == SAR ? "SAR" : (dst == DAR ? "DAR" : "CCR"), val);
762
763 return SZ_DMAMOV;
764}
765
766static inline u32 _emit_NOP(unsigned dry_run, u8 buf[])
767{
768 if (dry_run)
769 return SZ_DMANOP;
770
771 buf[0] = CMD_DMANOP;
772
773 PL330_DBGCMD_DUMP(SZ_DMANOP, "\tDMANOP\n");
774
775 return SZ_DMANOP;
776}
777
778static inline u32 _emit_RMB(unsigned dry_run, u8 buf[])
779{
780 if (dry_run)
781 return SZ_DMARMB;
782
783 buf[0] = CMD_DMARMB;
784
785 PL330_DBGCMD_DUMP(SZ_DMARMB, "\tDMARMB\n");
786
787 return SZ_DMARMB;
788}
789
790static inline u32 _emit_SEV(unsigned dry_run, u8 buf[], u8 ev)
791{
792 if (dry_run)
793 return SZ_DMASEV;
794
795 buf[0] = CMD_DMASEV;
796
797 ev &= 0x1f;
798 ev <<= 3;
799 buf[1] = ev;
800
801 PL330_DBGCMD_DUMP(SZ_DMASEV, "\tDMASEV %u\n", ev >> 3);
802
803 return SZ_DMASEV;
804}
805
806static inline u32 _emit_ST(unsigned dry_run, u8 buf[], enum pl330_cond cond)
807{
808 if (dry_run)
809 return SZ_DMAST;
810
811 buf[0] = CMD_DMAST;
812
813 if (cond == SINGLE)
814 buf[0] |= (0 << 1) | (1 << 0);
815 else if (cond == BURST)
816 buf[0] |= (1 << 1) | (1 << 0);
817
818 PL330_DBGCMD_DUMP(SZ_DMAST, "\tDMAST%c\n",
819 cond == SINGLE ? 'S' : (cond == BURST ? 'B' : 'A'));
820
821 return SZ_DMAST;
822}
823
824static inline u32 _emit_STP(unsigned dry_run, u8 buf[],
825 enum pl330_cond cond, u8 peri)
826{
827 if (dry_run)
828 return SZ_DMASTP;
829
830 buf[0] = CMD_DMASTP;
831
832 if (cond == BURST)
833 buf[0] |= (1 << 1);
834
835 peri &= 0x1f;
836 peri <<= 3;
837 buf[1] = peri;
838
839 PL330_DBGCMD_DUMP(SZ_DMASTP, "\tDMASTP%c %u\n",
840 cond == SINGLE ? 'S' : 'B', peri >> 3);
841
842 return SZ_DMASTP;
843}
844
845static inline u32 _emit_STZ(unsigned dry_run, u8 buf[])
846{
847 if (dry_run)
848 return SZ_DMASTZ;
849
850 buf[0] = CMD_DMASTZ;
851
852 PL330_DBGCMD_DUMP(SZ_DMASTZ, "\tDMASTZ\n");
853
854 return SZ_DMASTZ;
855}
856
857static inline u32 _emit_WFE(unsigned dry_run, u8 buf[], u8 ev,
858 unsigned invalidate)
859{
860 if (dry_run)
861 return SZ_DMAWFE;
862
863 buf[0] = CMD_DMAWFE;
864
865 ev &= 0x1f;
866 ev <<= 3;
867 buf[1] = ev;
868
869 if (invalidate)
870 buf[1] |= (1 << 1);
871
872 PL330_DBGCMD_DUMP(SZ_DMAWFE, "\tDMAWFE %u%s\n",
873 ev >> 3, invalidate ? ", I" : "");
874
875 return SZ_DMAWFE;
876}
877
878static inline u32 _emit_WFP(unsigned dry_run, u8 buf[],
879 enum pl330_cond cond, u8 peri)
880{
881 if (dry_run)
882 return SZ_DMAWFP;
883
884 buf[0] = CMD_DMAWFP;
885
886 if (cond == SINGLE)
887 buf[0] |= (0 << 1) | (0 << 0);
888 else if (cond == BURST)
889 buf[0] |= (1 << 1) | (0 << 0);
890 else
891 buf[0] |= (0 << 1) | (1 << 0);
892
893 peri &= 0x1f;
894 peri <<= 3;
895 buf[1] = peri;
896
897 PL330_DBGCMD_DUMP(SZ_DMAWFP, "\tDMAWFP%c %u\n",
898 cond == SINGLE ? 'S' : (cond == BURST ? 'B' : 'P'), peri >> 3);
899
900 return SZ_DMAWFP;
901}
902
903static inline u32 _emit_WMB(unsigned dry_run, u8 buf[])
904{
905 if (dry_run)
906 return SZ_DMAWMB;
907
908 buf[0] = CMD_DMAWMB;
909
910 PL330_DBGCMD_DUMP(SZ_DMAWMB, "\tDMAWMB\n");
911
912 return SZ_DMAWMB;
913}
914
915struct _arg_GO {
916 u8 chan;
917 u32 addr;
918 unsigned ns;
919};
920
921static inline u32 _emit_GO(unsigned dry_run, u8 buf[],
922 const struct _arg_GO *arg)
923{
924 u8 chan = arg->chan;
925 u32 addr = arg->addr;
926 unsigned ns = arg->ns;
927
928 if (dry_run)
929 return SZ_DMAGO;
930
931 buf[0] = CMD_DMAGO;
932 buf[0] |= (ns << 1);
933
934 buf[1] = chan & 0x7;
935
936 *((u32 *)&buf[2]) = addr;
937
938 return SZ_DMAGO;
939}
940
941#define msecs_to_loops(t) (loops_per_jiffy / 1000 * HZ * t)
942
943/* Returns Time-Out */
944static bool _until_dmac_idle(struct pl330_thread *thrd)
945{
946 void __iomem *regs = thrd->dmac->pinfo->base;
947 unsigned long loops = msecs_to_loops(5);
948
949 do {
950 /* Until Manager is Idle */
951 if (!(readl(regs + DBGSTATUS) & DBG_BUSY))
952 break;
953
954 cpu_relax();
955 } while (--loops);
956
957 if (!loops)
958 return true;
959
960 return false;
961}
962
963static inline void _execute_DBGINSN(struct pl330_thread *thrd,
964 u8 insn[], bool as_manager)
965{
966 void __iomem *regs = thrd->dmac->pinfo->base;
967 u32 val;
968
969 val = (insn[0] << 16) | (insn[1] << 24);
970 if (!as_manager) {
971 val |= (1 << 0);
972 val |= (thrd->id << 8); /* Channel Number */
973 }
974 writel(val, regs + DBGINST0);
975
976 val = *((u32 *)&insn[2]);
977 writel(val, regs + DBGINST1);
978
979 /* If timed out due to halted state-machine */
980 if (_until_dmac_idle(thrd)) {
981 dev_err(thrd->dmac->pinfo->dev, "DMAC halted!\n");
982 return;
983 }
984
985 /* Get going */
986 writel(0, regs + DBGCMD);
987}
988
989/*
990 * Mark a _pl330_req as free.
991 * We do it by writing DMAEND as the first instruction
992 * because no valid request is going to have DMAEND as
993 * its first instruction to execute.
994 */
995static void mark_free(struct pl330_thread *thrd, int idx)
996{
997 struct _pl330_req *req = &thrd->req[idx];
998
999 _emit_END(0, req->mc_cpu);
Boojin Kimb7d861d2011-12-26 18:49:52 +09001000
1001 thrd->req_running = -1;
1002}
1003
1004static inline u32 _state(struct pl330_thread *thrd)
1005{
1006 void __iomem *regs = thrd->dmac->pinfo->base;
1007 u32 val;
1008
1009 if (is_manager(thrd))
1010 val = readl(regs + DS) & 0xf;
1011 else
1012 val = readl(regs + CS(thrd->id)) & 0xf;
1013
1014 switch (val) {
1015 case DS_ST_STOP:
1016 return PL330_STATE_STOPPED;
1017 case DS_ST_EXEC:
1018 return PL330_STATE_EXECUTING;
1019 case DS_ST_CMISS:
1020 return PL330_STATE_CACHEMISS;
1021 case DS_ST_UPDTPC:
1022 return PL330_STATE_UPDTPC;
1023 case DS_ST_WFE:
1024 return PL330_STATE_WFE;
1025 case DS_ST_FAULT:
1026 return PL330_STATE_FAULTING;
1027 case DS_ST_ATBRR:
1028 if (is_manager(thrd))
1029 return PL330_STATE_INVALID;
1030 else
1031 return PL330_STATE_ATBARRIER;
1032 case DS_ST_QBUSY:
1033 if (is_manager(thrd))
1034 return PL330_STATE_INVALID;
1035 else
1036 return PL330_STATE_QUEUEBUSY;
1037 case DS_ST_WFP:
1038 if (is_manager(thrd))
1039 return PL330_STATE_INVALID;
1040 else
1041 return PL330_STATE_WFP;
1042 case DS_ST_KILL:
1043 if (is_manager(thrd))
1044 return PL330_STATE_INVALID;
1045 else
1046 return PL330_STATE_KILLING;
1047 case DS_ST_CMPLT:
1048 if (is_manager(thrd))
1049 return PL330_STATE_INVALID;
1050 else
1051 return PL330_STATE_COMPLETING;
1052 case DS_ST_FLTCMP:
1053 if (is_manager(thrd))
1054 return PL330_STATE_INVALID;
1055 else
1056 return PL330_STATE_FAULT_COMPLETING;
1057 default:
1058 return PL330_STATE_INVALID;
1059 }
1060}
1061
1062static void _stop(struct pl330_thread *thrd)
1063{
1064 void __iomem *regs = thrd->dmac->pinfo->base;
1065 u8 insn[6] = {0, 0, 0, 0, 0, 0};
1066
1067 if (_state(thrd) == PL330_STATE_FAULT_COMPLETING)
1068 UNTIL(thrd, PL330_STATE_FAULTING | PL330_STATE_KILLING);
1069
1070 /* Return if nothing needs to be done */
1071 if (_state(thrd) == PL330_STATE_COMPLETING
1072 || _state(thrd) == PL330_STATE_KILLING
1073 || _state(thrd) == PL330_STATE_STOPPED)
1074 return;
1075
1076 _emit_KILL(0, insn);
1077
1078 /* Stop generating interrupts for SEV */
1079 writel(readl(regs + INTEN) & ~(1 << thrd->ev), regs + INTEN);
1080
1081 _execute_DBGINSN(thrd, insn, is_manager(thrd));
1082}
1083
1084/* Start doing req 'idx' of thread 'thrd' */
1085static bool _trigger(struct pl330_thread *thrd)
1086{
1087 void __iomem *regs = thrd->dmac->pinfo->base;
1088 struct _pl330_req *req;
1089 struct pl330_req *r;
1090 struct _arg_GO go;
1091 unsigned ns;
1092 u8 insn[6] = {0, 0, 0, 0, 0, 0};
1093 int idx;
1094
1095 /* Return if already ACTIVE */
1096 if (_state(thrd) != PL330_STATE_STOPPED)
1097 return true;
1098
1099 idx = 1 - thrd->lstenq;
1100 if (!IS_FREE(&thrd->req[idx]))
1101 req = &thrd->req[idx];
1102 else {
1103 idx = thrd->lstenq;
1104 if (!IS_FREE(&thrd->req[idx]))
1105 req = &thrd->req[idx];
1106 else
1107 req = NULL;
1108 }
1109
1110 /* Return if no request */
1111 if (!req || !req->r)
1112 return true;
1113
1114 r = req->r;
1115
1116 if (r->cfg)
1117 ns = r->cfg->nonsecure ? 1 : 0;
1118 else if (readl(regs + CS(thrd->id)) & CS_CNS)
1119 ns = 1;
1120 else
1121 ns = 0;
1122
1123 /* See 'Abort Sources' point-4 at Page 2-25 */
1124 if (_manager_ns(thrd) && !ns)
1125 dev_info(thrd->dmac->pinfo->dev, "%s:%d Recipe for ABORT!\n",
1126 __func__, __LINE__);
1127
1128 go.chan = thrd->id;
1129 go.addr = req->mc_bus;
1130 go.ns = ns;
1131 _emit_GO(0, insn, &go);
1132
1133 /* Set to generate interrupts for SEV */
1134 writel(readl(regs + INTEN) | (1 << thrd->ev), regs + INTEN);
1135
1136 /* Only manager can execute GO */
1137 _execute_DBGINSN(thrd, insn, true);
1138
1139 thrd->req_running = idx;
1140
1141 return true;
1142}
1143
1144static bool _start(struct pl330_thread *thrd)
1145{
1146 switch (_state(thrd)) {
1147 case PL330_STATE_FAULT_COMPLETING:
1148 UNTIL(thrd, PL330_STATE_FAULTING | PL330_STATE_KILLING);
1149
1150 if (_state(thrd) == PL330_STATE_KILLING)
1151 UNTIL(thrd, PL330_STATE_STOPPED)
1152
1153 case PL330_STATE_FAULTING:
1154 _stop(thrd);
1155
1156 case PL330_STATE_KILLING:
1157 case PL330_STATE_COMPLETING:
1158 UNTIL(thrd, PL330_STATE_STOPPED)
1159
1160 case PL330_STATE_STOPPED:
1161 return _trigger(thrd);
1162
1163 case PL330_STATE_WFP:
1164 case PL330_STATE_QUEUEBUSY:
1165 case PL330_STATE_ATBARRIER:
1166 case PL330_STATE_UPDTPC:
1167 case PL330_STATE_CACHEMISS:
1168 case PL330_STATE_EXECUTING:
1169 return true;
1170
1171 case PL330_STATE_WFE: /* For RESUME, nothing yet */
1172 default:
1173 return false;
1174 }
1175}
1176
1177static inline int _ldst_memtomem(unsigned dry_run, u8 buf[],
1178 const struct _xfer_spec *pxs, int cyc)
1179{
1180 int off = 0;
Boojin Kim3ecf51a2011-12-26 18:55:47 +09001181 struct pl330_config *pcfg = pxs->r->cfg->pcfg;
Boojin Kimb7d861d2011-12-26 18:49:52 +09001182
Boojin Kim3ecf51a2011-12-26 18:55:47 +09001183 /* check lock-up free version */
1184 if (get_revision(pcfg->periph_id) >= PERIPH_REV_R1P0) {
1185 while (cyc--) {
1186 off += _emit_LD(dry_run, &buf[off], ALWAYS);
1187 off += _emit_ST(dry_run, &buf[off], ALWAYS);
1188 }
1189 } else {
1190 while (cyc--) {
1191 off += _emit_LD(dry_run, &buf[off], ALWAYS);
1192 off += _emit_RMB(dry_run, &buf[off]);
1193 off += _emit_ST(dry_run, &buf[off], ALWAYS);
1194 off += _emit_WMB(dry_run, &buf[off]);
1195 }
Boojin Kimb7d861d2011-12-26 18:49:52 +09001196 }
1197
1198 return off;
1199}
1200
1201static inline int _ldst_devtomem(unsigned dry_run, u8 buf[],
1202 const struct _xfer_spec *pxs, int cyc)
1203{
1204 int off = 0;
1205
1206 while (cyc--) {
1207 off += _emit_WFP(dry_run, &buf[off], SINGLE, pxs->r->peri);
1208 off += _emit_LDP(dry_run, &buf[off], SINGLE, pxs->r->peri);
1209 off += _emit_ST(dry_run, &buf[off], ALWAYS);
1210 off += _emit_FLUSHP(dry_run, &buf[off], pxs->r->peri);
1211 }
1212
1213 return off;
1214}
1215
1216static inline int _ldst_memtodev(unsigned dry_run, u8 buf[],
1217 const struct _xfer_spec *pxs, int cyc)
1218{
1219 int off = 0;
1220
1221 while (cyc--) {
1222 off += _emit_WFP(dry_run, &buf[off], SINGLE, pxs->r->peri);
1223 off += _emit_LD(dry_run, &buf[off], ALWAYS);
1224 off += _emit_STP(dry_run, &buf[off], SINGLE, pxs->r->peri);
1225 off += _emit_FLUSHP(dry_run, &buf[off], pxs->r->peri);
1226 }
1227
1228 return off;
1229}
1230
1231static int _bursts(unsigned dry_run, u8 buf[],
1232 const struct _xfer_spec *pxs, int cyc)
1233{
1234 int off = 0;
1235
1236 switch (pxs->r->rqtype) {
Lars-Peter Clausen585a9d02014-07-06 20:32:18 +02001237 case DMA_MEM_TO_DEV:
Boojin Kimb7d861d2011-12-26 18:49:52 +09001238 off += _ldst_memtodev(dry_run, &buf[off], pxs, cyc);
1239 break;
Lars-Peter Clausen585a9d02014-07-06 20:32:18 +02001240 case DMA_DEV_TO_MEM:
Boojin Kimb7d861d2011-12-26 18:49:52 +09001241 off += _ldst_devtomem(dry_run, &buf[off], pxs, cyc);
1242 break;
Lars-Peter Clausen585a9d02014-07-06 20:32:18 +02001243 case DMA_MEM_TO_MEM:
Boojin Kimb7d861d2011-12-26 18:49:52 +09001244 off += _ldst_memtomem(dry_run, &buf[off], pxs, cyc);
1245 break;
1246 default:
1247 off += 0x40000000; /* Scare off the Client */
1248 break;
1249 }
1250
1251 return off;
1252}
1253
1254/* Returns bytes consumed and updates bursts */
1255static inline int _loop(unsigned dry_run, u8 buf[],
1256 unsigned long *bursts, const struct _xfer_spec *pxs)
1257{
1258 int cyc, cycmax, szlp, szlpend, szbrst, off;
1259 unsigned lcnt0, lcnt1, ljmp0, ljmp1;
1260 struct _arg_LPEND lpend;
1261
1262 /* Max iterations possible in DMALP is 256 */
1263 if (*bursts >= 256*256) {
1264 lcnt1 = 256;
1265 lcnt0 = 256;
1266 cyc = *bursts / lcnt1 / lcnt0;
1267 } else if (*bursts > 256) {
1268 lcnt1 = 256;
1269 lcnt0 = *bursts / lcnt1;
1270 cyc = 1;
1271 } else {
1272 lcnt1 = *bursts;
1273 lcnt0 = 0;
1274 cyc = 1;
1275 }
1276
1277 szlp = _emit_LP(1, buf, 0, 0);
1278 szbrst = _bursts(1, buf, pxs, 1);
1279
1280 lpend.cond = ALWAYS;
1281 lpend.forever = false;
1282 lpend.loop = 0;
1283 lpend.bjump = 0;
1284 szlpend = _emit_LPEND(1, buf, &lpend);
1285
1286 if (lcnt0) {
1287 szlp *= 2;
1288 szlpend *= 2;
1289 }
1290
1291 /*
1292 * Max bursts that we can unroll due to limit on the
1293 * size of backward jump that can be encoded in DMALPEND
1294 * which is 8-bits and hence 255
1295 */
1296 cycmax = (255 - (szlp + szlpend)) / szbrst;
1297
1298 cyc = (cycmax < cyc) ? cycmax : cyc;
1299
1300 off = 0;
1301
1302 if (lcnt0) {
1303 off += _emit_LP(dry_run, &buf[off], 0, lcnt0);
1304 ljmp0 = off;
1305 }
1306
1307 off += _emit_LP(dry_run, &buf[off], 1, lcnt1);
1308 ljmp1 = off;
1309
1310 off += _bursts(dry_run, &buf[off], pxs, cyc);
1311
1312 lpend.cond = ALWAYS;
1313 lpend.forever = false;
1314 lpend.loop = 1;
1315 lpend.bjump = off - ljmp1;
1316 off += _emit_LPEND(dry_run, &buf[off], &lpend);
1317
1318 if (lcnt0) {
1319 lpend.cond = ALWAYS;
1320 lpend.forever = false;
1321 lpend.loop = 0;
1322 lpend.bjump = off - ljmp0;
1323 off += _emit_LPEND(dry_run, &buf[off], &lpend);
1324 }
1325
1326 *bursts = lcnt1 * cyc;
1327 if (lcnt0)
1328 *bursts *= lcnt0;
1329
1330 return off;
1331}
1332
1333static inline int _setup_loops(unsigned dry_run, u8 buf[],
1334 const struct _xfer_spec *pxs)
1335{
1336 struct pl330_xfer *x = pxs->x;
1337 u32 ccr = pxs->ccr;
1338 unsigned long c, bursts = BYTE_TO_BURST(x->bytes, ccr);
1339 int off = 0;
1340
1341 while (bursts) {
1342 c = bursts;
1343 off += _loop(dry_run, &buf[off], &c, pxs);
1344 bursts -= c;
1345 }
1346
1347 return off;
1348}
1349
1350static inline int _setup_xfer(unsigned dry_run, u8 buf[],
1351 const struct _xfer_spec *pxs)
1352{
1353 struct pl330_xfer *x = pxs->x;
1354 int off = 0;
1355
1356 /* DMAMOV SAR, x->src_addr */
1357 off += _emit_MOV(dry_run, &buf[off], SAR, x->src_addr);
1358 /* DMAMOV DAR, x->dst_addr */
1359 off += _emit_MOV(dry_run, &buf[off], DAR, x->dst_addr);
1360
1361 /* Setup Loop(s) */
1362 off += _setup_loops(dry_run, &buf[off], pxs);
1363
1364 return off;
1365}
1366
1367/*
1368 * A req is a sequence of one or more xfer units.
1369 * Returns the number of bytes taken to setup the MC for the req.
1370 */
1371static int _setup_req(unsigned dry_run, struct pl330_thread *thrd,
1372 unsigned index, struct _xfer_spec *pxs)
1373{
1374 struct _pl330_req *req = &thrd->req[index];
1375 struct pl330_xfer *x;
1376 u8 *buf = req->mc_cpu;
1377 int off = 0;
1378
1379 PL330_DBGMC_START(req->mc_bus);
1380
1381 /* DMAMOV CCR, ccr */
1382 off += _emit_MOV(dry_run, &buf[off], CCR, pxs->ccr);
1383
1384 x = pxs->r->x;
Lars-Peter Clausend5cef122014-07-06 20:32:23 +02001385 /* Error if xfer length is not aligned at burst size */
1386 if (x->bytes % (BRST_SIZE(pxs->ccr) * BRST_LEN(pxs->ccr)))
1387 return -EINVAL;
Boojin Kimb7d861d2011-12-26 18:49:52 +09001388
Lars-Peter Clausend5cef122014-07-06 20:32:23 +02001389 pxs->x = x;
1390 off += _setup_xfer(dry_run, &buf[off], pxs);
Boojin Kimb7d861d2011-12-26 18:49:52 +09001391
1392 /* DMASEV peripheral/event */
1393 off += _emit_SEV(dry_run, &buf[off], thrd->ev);
1394 /* DMAEND */
1395 off += _emit_END(dry_run, &buf[off]);
1396
1397 return off;
1398}
1399
1400static inline u32 _prepare_ccr(const struct pl330_reqcfg *rqc)
1401{
1402 u32 ccr = 0;
1403
1404 if (rqc->src_inc)
1405 ccr |= CC_SRCINC;
1406
1407 if (rqc->dst_inc)
1408 ccr |= CC_DSTINC;
1409
1410 /* We set same protection levels for Src and DST for now */
1411 if (rqc->privileged)
1412 ccr |= CC_SRCPRI | CC_DSTPRI;
1413 if (rqc->nonsecure)
1414 ccr |= CC_SRCNS | CC_DSTNS;
1415 if (rqc->insnaccess)
1416 ccr |= CC_SRCIA | CC_DSTIA;
1417
1418 ccr |= (((rqc->brst_len - 1) & 0xf) << CC_SRCBRSTLEN_SHFT);
1419 ccr |= (((rqc->brst_len - 1) & 0xf) << CC_DSTBRSTLEN_SHFT);
1420
1421 ccr |= (rqc->brst_size << CC_SRCBRSTSIZE_SHFT);
1422 ccr |= (rqc->brst_size << CC_DSTBRSTSIZE_SHFT);
1423
1424 ccr |= (rqc->scctl << CC_SRCCCTRL_SHFT);
1425 ccr |= (rqc->dcctl << CC_DSTCCTRL_SHFT);
1426
1427 ccr |= (rqc->swap << CC_SWAP_SHFT);
1428
1429 return ccr;
1430}
1431
1432static inline bool _is_valid(u32 ccr)
1433{
Lars-Peter Clausenf0564c72014-07-06 20:32:19 +02001434 enum pl330_cachectrl dcctl;
1435 enum pl330_cachectrl scctl;
Boojin Kimb7d861d2011-12-26 18:49:52 +09001436
1437 dcctl = (ccr >> CC_DSTCCTRL_SHFT) & CC_DRCCCTRL_MASK;
1438 scctl = (ccr >> CC_SRCCCTRL_SHFT) & CC_SRCCCTRL_MASK;
1439
Lars-Peter Clausenf0564c72014-07-06 20:32:19 +02001440 if (dcctl == INVALID1 || dcctl == INVALID2
1441 || scctl == INVALID1 || scctl == INVALID2)
Boojin Kimb7d861d2011-12-26 18:49:52 +09001442 return false;
1443 else
1444 return true;
1445}
1446
1447/*
1448 * Submit a list of xfers after which the client wants notification.
1449 * Client is not notified after each xfer unit, just once after all
1450 * xfer units are done or some error occurs.
1451 */
1452static int pl330_submit_req(void *ch_id, struct pl330_req *r)
1453{
1454 struct pl330_thread *thrd = ch_id;
1455 struct pl330_dmac *pl330;
1456 struct pl330_info *pi;
1457 struct _xfer_spec xs;
1458 unsigned long flags;
1459 void __iomem *regs;
1460 unsigned idx;
1461 u32 ccr;
1462 int ret = 0;
1463
1464 /* No Req or Unacquired Channel or DMAC */
1465 if (!r || !thrd || thrd->free)
1466 return -EINVAL;
1467
1468 pl330 = thrd->dmac;
1469 pi = pl330->pinfo;
1470 regs = pi->base;
1471
1472 if (pl330->state == DYING
1473 || pl330->dmac_tbd.reset_chan & (1 << thrd->id)) {
1474 dev_info(thrd->dmac->pinfo->dev, "%s:%d\n",
1475 __func__, __LINE__);
1476 return -EAGAIN;
1477 }
1478
1479 /* If request for non-existing peripheral */
Lars-Peter Clausen585a9d02014-07-06 20:32:18 +02001480 if (r->rqtype != DMA_MEM_TO_MEM && r->peri >= pi->pcfg.num_peri) {
Boojin Kimb7d861d2011-12-26 18:49:52 +09001481 dev_info(thrd->dmac->pinfo->dev,
1482 "%s:%d Invalid peripheral(%u)!\n",
1483 __func__, __LINE__, r->peri);
1484 return -EINVAL;
1485 }
1486
1487 spin_lock_irqsave(&pl330->lock, flags);
1488
1489 if (_queue_full(thrd)) {
1490 ret = -EAGAIN;
1491 goto xfer_exit;
1492 }
1493
Boojin Kimb7d861d2011-12-26 18:49:52 +09001494
1495 /* Use last settings, if not provided */
Sachin Kamat2e2c6822012-09-17 15:20:22 +05301496 if (r->cfg) {
1497 /* Prefer Secure Channel */
1498 if (!_manager_ns(thrd))
1499 r->cfg->nonsecure = 0;
1500 else
1501 r->cfg->nonsecure = 1;
1502
Boojin Kimb7d861d2011-12-26 18:49:52 +09001503 ccr = _prepare_ccr(r->cfg);
Sachin Kamat2e2c6822012-09-17 15:20:22 +05301504 } else {
Boojin Kimb7d861d2011-12-26 18:49:52 +09001505 ccr = readl(regs + CC(thrd->id));
Sachin Kamat2e2c6822012-09-17 15:20:22 +05301506 }
Boojin Kimb7d861d2011-12-26 18:49:52 +09001507
1508 /* If this req doesn't have valid xfer settings */
1509 if (!_is_valid(ccr)) {
1510 ret = -EINVAL;
1511 dev_info(thrd->dmac->pinfo->dev, "%s:%d Invalid CCR(%x)!\n",
1512 __func__, __LINE__, ccr);
1513 goto xfer_exit;
1514 }
1515
1516 idx = IS_FREE(&thrd->req[0]) ? 0 : 1;
1517
1518 xs.ccr = ccr;
1519 xs.r = r;
1520
1521 /* First dry run to check if req is acceptable */
1522 ret = _setup_req(1, thrd, idx, &xs);
1523 if (ret < 0)
1524 goto xfer_exit;
1525
1526 if (ret > pi->mcbufsz / 2) {
1527 dev_info(thrd->dmac->pinfo->dev,
1528 "%s:%d Trying increasing mcbufsz\n",
1529 __func__, __LINE__);
1530 ret = -ENOMEM;
1531 goto xfer_exit;
1532 }
1533
1534 /* Hook the request */
1535 thrd->lstenq = idx;
Boojin Kimb7d861d2011-12-26 18:49:52 +09001536 thrd->req[idx].r = r;
Lars-Peter Clausenbe025322014-07-06 20:32:24 +02001537 _setup_req(0, thrd, idx, &xs);
Boojin Kimb7d861d2011-12-26 18:49:52 +09001538
1539 ret = 0;
1540
1541xfer_exit:
1542 spin_unlock_irqrestore(&pl330->lock, flags);
1543
1544 return ret;
1545}
1546
1547static void pl330_dotask(unsigned long data)
1548{
1549 struct pl330_dmac *pl330 = (struct pl330_dmac *) data;
1550 struct pl330_info *pi = pl330->pinfo;
1551 unsigned long flags;
1552 int i;
1553
1554 spin_lock_irqsave(&pl330->lock, flags);
1555
1556 /* The DMAC itself gone nuts */
1557 if (pl330->dmac_tbd.reset_dmac) {
1558 pl330->state = DYING;
1559 /* Reset the manager too */
1560 pl330->dmac_tbd.reset_mngr = true;
1561 /* Clear the reset flag */
1562 pl330->dmac_tbd.reset_dmac = false;
1563 }
1564
1565 if (pl330->dmac_tbd.reset_mngr) {
1566 _stop(pl330->manager);
1567 /* Reset all channels */
1568 pl330->dmac_tbd.reset_chan = (1 << pi->pcfg.num_chan) - 1;
1569 /* Clear the reset flag */
1570 pl330->dmac_tbd.reset_mngr = false;
1571 }
1572
1573 for (i = 0; i < pi->pcfg.num_chan; i++) {
1574
1575 if (pl330->dmac_tbd.reset_chan & (1 << i)) {
1576 struct pl330_thread *thrd = &pl330->channels[i];
1577 void __iomem *regs = pi->base;
1578 enum pl330_op_err err;
1579
1580 _stop(thrd);
1581
1582 if (readl(regs + FSC) & (1 << thrd->id))
1583 err = PL330_ERR_FAIL;
1584 else
1585 err = PL330_ERR_ABORT;
1586
1587 spin_unlock_irqrestore(&pl330->lock, flags);
1588
1589 _callback(thrd->req[1 - thrd->lstenq].r, err);
1590 _callback(thrd->req[thrd->lstenq].r, err);
1591
1592 spin_lock_irqsave(&pl330->lock, flags);
1593
1594 thrd->req[0].r = NULL;
1595 thrd->req[1].r = NULL;
1596 mark_free(thrd, 0);
1597 mark_free(thrd, 1);
1598
1599 /* Clear the reset flag */
1600 pl330->dmac_tbd.reset_chan &= ~(1 << i);
1601 }
1602 }
1603
1604 spin_unlock_irqrestore(&pl330->lock, flags);
1605
1606 return;
1607}
1608
1609/* Returns 1 if state was updated, 0 otherwise */
1610static int pl330_update(const struct pl330_info *pi)
1611{
Javi Merinofdec53d2012-06-13 15:07:00 +01001612 struct pl330_req *rqdone, *tmp;
Boojin Kimb7d861d2011-12-26 18:49:52 +09001613 struct pl330_dmac *pl330;
1614 unsigned long flags;
1615 void __iomem *regs;
1616 u32 val;
1617 int id, ev, ret = 0;
1618
1619 if (!pi || !pi->pl330_data)
1620 return 0;
1621
1622 regs = pi->base;
1623 pl330 = pi->pl330_data;
1624
1625 spin_lock_irqsave(&pl330->lock, flags);
1626
1627 val = readl(regs + FSM) & 0x1;
1628 if (val)
1629 pl330->dmac_tbd.reset_mngr = true;
1630 else
1631 pl330->dmac_tbd.reset_mngr = false;
1632
1633 val = readl(regs + FSC) & ((1 << pi->pcfg.num_chan) - 1);
1634 pl330->dmac_tbd.reset_chan |= val;
1635 if (val) {
1636 int i = 0;
1637 while (i < pi->pcfg.num_chan) {
1638 if (val & (1 << i)) {
1639 dev_info(pi->dev,
1640 "Reset Channel-%d\t CS-%x FTC-%x\n",
1641 i, readl(regs + CS(i)),
1642 readl(regs + FTC(i)));
1643 _stop(&pl330->channels[i]);
1644 }
1645 i++;
1646 }
1647 }
1648
1649 /* Check which event happened i.e, thread notified */
1650 val = readl(regs + ES);
1651 if (pi->pcfg.num_events < 32
1652 && val & ~((1 << pi->pcfg.num_events) - 1)) {
1653 pl330->dmac_tbd.reset_dmac = true;
1654 dev_err(pi->dev, "%s:%d Unexpected!\n", __func__, __LINE__);
1655 ret = 1;
1656 goto updt_exit;
1657 }
1658
1659 for (ev = 0; ev < pi->pcfg.num_events; ev++) {
1660 if (val & (1 << ev)) { /* Event occurred */
1661 struct pl330_thread *thrd;
1662 u32 inten = readl(regs + INTEN);
1663 int active;
1664
1665 /* Clear the event */
1666 if (inten & (1 << ev))
1667 writel(1 << ev, regs + INTCLR);
1668
1669 ret = 1;
1670
1671 id = pl330->events[ev];
1672
1673 thrd = &pl330->channels[id];
1674
1675 active = thrd->req_running;
1676 if (active == -1) /* Aborted */
1677 continue;
1678
Javi Merinofdec53d2012-06-13 15:07:00 +01001679 /* Detach the req */
1680 rqdone = thrd->req[active].r;
1681 thrd->req[active].r = NULL;
1682
Boojin Kimb7d861d2011-12-26 18:49:52 +09001683 mark_free(thrd, active);
1684
1685 /* Get going again ASAP */
1686 _start(thrd);
1687
1688 /* For now, just make a list of callbacks to be done */
1689 list_add_tail(&rqdone->rqd, &pl330->req_done);
1690 }
1691 }
1692
1693 /* Now that we are in no hurry, do the callbacks */
Javi Merinofdec53d2012-06-13 15:07:00 +01001694 list_for_each_entry_safe(rqdone, tmp, &pl330->req_done, rqd) {
1695 list_del(&rqdone->rqd);
Boojin Kimb7d861d2011-12-26 18:49:52 +09001696
1697 spin_unlock_irqrestore(&pl330->lock, flags);
Javi Merinofdec53d2012-06-13 15:07:00 +01001698 _callback(rqdone, PL330_ERR_NONE);
Boojin Kimb7d861d2011-12-26 18:49:52 +09001699 spin_lock_irqsave(&pl330->lock, flags);
1700 }
1701
1702updt_exit:
1703 spin_unlock_irqrestore(&pl330->lock, flags);
1704
1705 if (pl330->dmac_tbd.reset_dmac
1706 || pl330->dmac_tbd.reset_mngr
1707 || pl330->dmac_tbd.reset_chan) {
1708 ret = 1;
1709 tasklet_schedule(&pl330->tasks);
1710 }
1711
1712 return ret;
1713}
1714
1715static int pl330_chan_ctrl(void *ch_id, enum pl330_chan_op op)
1716{
1717 struct pl330_thread *thrd = ch_id;
1718 struct pl330_dmac *pl330;
1719 unsigned long flags;
Linus Torvaldsef08e782012-03-29 15:34:57 -07001720 int ret = 0, active;
Boojin Kimb7d861d2011-12-26 18:49:52 +09001721
1722 if (!thrd || thrd->free || thrd->dmac->state == DYING)
1723 return -EINVAL;
1724
1725 pl330 = thrd->dmac;
Linus Torvaldsef08e782012-03-29 15:34:57 -07001726 active = thrd->req_running;
Boojin Kimb7d861d2011-12-26 18:49:52 +09001727
1728 spin_lock_irqsave(&pl330->lock, flags);
1729
1730 switch (op) {
1731 case PL330_OP_FLUSH:
1732 /* Make sure the channel is stopped */
1733 _stop(thrd);
1734
1735 thrd->req[0].r = NULL;
1736 thrd->req[1].r = NULL;
1737 mark_free(thrd, 0);
1738 mark_free(thrd, 1);
1739 break;
1740
1741 case PL330_OP_ABORT:
1742 /* Make sure the channel is stopped */
1743 _stop(thrd);
1744
1745 /* ABORT is only for the active req */
1746 if (active == -1)
1747 break;
1748
1749 thrd->req[active].r = NULL;
1750 mark_free(thrd, active);
1751
1752 /* Start the next */
1753 case PL330_OP_START:
1754 if ((active == -1) && !_start(thrd))
1755 ret = -EIO;
1756 break;
1757
1758 default:
1759 ret = -EINVAL;
1760 }
1761
1762 spin_unlock_irqrestore(&pl330->lock, flags);
1763 return ret;
1764}
1765
Boojin Kimb7d861d2011-12-26 18:49:52 +09001766/* Reserve an event */
1767static inline int _alloc_event(struct pl330_thread *thrd)
1768{
1769 struct pl330_dmac *pl330 = thrd->dmac;
1770 struct pl330_info *pi = pl330->pinfo;
1771 int ev;
1772
1773 for (ev = 0; ev < pi->pcfg.num_events; ev++)
1774 if (pl330->events[ev] == -1) {
1775 pl330->events[ev] = thrd->id;
1776 return ev;
1777 }
1778
1779 return -1;
1780}
1781
1782static bool _chan_ns(const struct pl330_info *pi, int i)
1783{
1784 return pi->pcfg.irq_ns & (1 << i);
1785}
1786
1787/* Upon success, returns IdentityToken for the
1788 * allocated channel, NULL otherwise.
1789 */
1790static void *pl330_request_channel(const struct pl330_info *pi)
1791{
1792 struct pl330_thread *thrd = NULL;
1793 struct pl330_dmac *pl330;
1794 unsigned long flags;
1795 int chans, i;
1796
1797 if (!pi || !pi->pl330_data)
1798 return NULL;
1799
1800 pl330 = pi->pl330_data;
1801
1802 if (pl330->state == DYING)
1803 return NULL;
1804
1805 chans = pi->pcfg.num_chan;
1806
1807 spin_lock_irqsave(&pl330->lock, flags);
1808
1809 for (i = 0; i < chans; i++) {
1810 thrd = &pl330->channels[i];
1811 if ((thrd->free) && (!_manager_ns(thrd) ||
1812 _chan_ns(pi, i))) {
1813 thrd->ev = _alloc_event(thrd);
1814 if (thrd->ev >= 0) {
1815 thrd->free = false;
1816 thrd->lstenq = 1;
1817 thrd->req[0].r = NULL;
1818 mark_free(thrd, 0);
1819 thrd->req[1].r = NULL;
1820 mark_free(thrd, 1);
1821 break;
1822 }
1823 }
1824 thrd = NULL;
1825 }
1826
1827 spin_unlock_irqrestore(&pl330->lock, flags);
1828
1829 return thrd;
1830}
1831
1832/* Release an event */
1833static inline void _free_event(struct pl330_thread *thrd, int ev)
1834{
1835 struct pl330_dmac *pl330 = thrd->dmac;
1836 struct pl330_info *pi = pl330->pinfo;
1837
1838 /* If the event is valid and was held by the thread */
1839 if (ev >= 0 && ev < pi->pcfg.num_events
1840 && pl330->events[ev] == thrd->id)
1841 pl330->events[ev] = -1;
1842}
1843
1844static void pl330_release_channel(void *ch_id)
1845{
1846 struct pl330_thread *thrd = ch_id;
1847 struct pl330_dmac *pl330;
1848 unsigned long flags;
1849
1850 if (!thrd || thrd->free)
1851 return;
1852
1853 _stop(thrd);
1854
1855 _callback(thrd->req[1 - thrd->lstenq].r, PL330_ERR_ABORT);
1856 _callback(thrd->req[thrd->lstenq].r, PL330_ERR_ABORT);
1857
1858 pl330 = thrd->dmac;
1859
1860 spin_lock_irqsave(&pl330->lock, flags);
1861 _free_event(thrd, thrd->ev);
1862 thrd->free = true;
1863 spin_unlock_irqrestore(&pl330->lock, flags);
1864}
1865
1866/* Initialize the structure for PL330 configuration, that can be used
1867 * by the client driver the make best use of the DMAC
1868 */
1869static void read_dmac_config(struct pl330_info *pi)
1870{
1871 void __iomem *regs = pi->base;
1872 u32 val;
1873
1874 val = readl(regs + CRD) >> CRD_DATA_WIDTH_SHIFT;
1875 val &= CRD_DATA_WIDTH_MASK;
1876 pi->pcfg.data_bus_width = 8 * (1 << val);
1877
1878 val = readl(regs + CRD) >> CRD_DATA_BUFF_SHIFT;
1879 val &= CRD_DATA_BUFF_MASK;
1880 pi->pcfg.data_buf_dep = val + 1;
1881
1882 val = readl(regs + CR0) >> CR0_NUM_CHANS_SHIFT;
1883 val &= CR0_NUM_CHANS_MASK;
1884 val += 1;
1885 pi->pcfg.num_chan = val;
1886
1887 val = readl(regs + CR0);
1888 if (val & CR0_PERIPH_REQ_SET) {
1889 val = (val >> CR0_NUM_PERIPH_SHIFT) & CR0_NUM_PERIPH_MASK;
1890 val += 1;
1891 pi->pcfg.num_peri = val;
1892 pi->pcfg.peri_ns = readl(regs + CR4);
1893 } else {
1894 pi->pcfg.num_peri = 0;
1895 }
1896
1897 val = readl(regs + CR0);
1898 if (val & CR0_BOOT_MAN_NS)
1899 pi->pcfg.mode |= DMAC_MODE_NS;
1900 else
1901 pi->pcfg.mode &= ~DMAC_MODE_NS;
1902
1903 val = readl(regs + CR0) >> CR0_NUM_EVENTS_SHIFT;
1904 val &= CR0_NUM_EVENTS_MASK;
1905 val += 1;
1906 pi->pcfg.num_events = val;
1907
1908 pi->pcfg.irq_ns = readl(regs + CR3);
Boojin Kimb7d861d2011-12-26 18:49:52 +09001909}
1910
1911static inline void _reset_thread(struct pl330_thread *thrd)
1912{
1913 struct pl330_dmac *pl330 = thrd->dmac;
1914 struct pl330_info *pi = pl330->pinfo;
1915
1916 thrd->req[0].mc_cpu = pl330->mcode_cpu
1917 + (thrd->id * pi->mcbufsz);
1918 thrd->req[0].mc_bus = pl330->mcode_bus
1919 + (thrd->id * pi->mcbufsz);
1920 thrd->req[0].r = NULL;
1921 mark_free(thrd, 0);
1922
1923 thrd->req[1].mc_cpu = thrd->req[0].mc_cpu
1924 + pi->mcbufsz / 2;
1925 thrd->req[1].mc_bus = thrd->req[0].mc_bus
1926 + pi->mcbufsz / 2;
1927 thrd->req[1].r = NULL;
1928 mark_free(thrd, 1);
1929}
1930
1931static int dmac_alloc_threads(struct pl330_dmac *pl330)
1932{
1933 struct pl330_info *pi = pl330->pinfo;
1934 int chans = pi->pcfg.num_chan;
1935 struct pl330_thread *thrd;
1936 int i;
1937
1938 /* Allocate 1 Manager and 'chans' Channel threads */
1939 pl330->channels = kzalloc((1 + chans) * sizeof(*thrd),
1940 GFP_KERNEL);
1941 if (!pl330->channels)
1942 return -ENOMEM;
1943
1944 /* Init Channel threads */
1945 for (i = 0; i < chans; i++) {
1946 thrd = &pl330->channels[i];
1947 thrd->id = i;
1948 thrd->dmac = pl330;
1949 _reset_thread(thrd);
1950 thrd->free = true;
1951 }
1952
1953 /* MANAGER is indexed at the end */
1954 thrd = &pl330->channels[chans];
1955 thrd->id = chans;
1956 thrd->dmac = pl330;
1957 thrd->free = false;
1958 pl330->manager = thrd;
1959
1960 return 0;
1961}
1962
1963static int dmac_alloc_resources(struct pl330_dmac *pl330)
1964{
1965 struct pl330_info *pi = pl330->pinfo;
1966 int chans = pi->pcfg.num_chan;
1967 int ret;
1968
1969 /*
1970 * Alloc MicroCode buffer for 'chans' Channel threads.
1971 * A channel's buffer offset is (Channel_Id * MCODE_BUFF_PERCHAN)
1972 */
1973 pl330->mcode_cpu = dma_alloc_coherent(pi->dev,
1974 chans * pi->mcbufsz,
1975 &pl330->mcode_bus, GFP_KERNEL);
1976 if (!pl330->mcode_cpu) {
1977 dev_err(pi->dev, "%s:%d Can't allocate memory!\n",
1978 __func__, __LINE__);
1979 return -ENOMEM;
1980 }
1981
1982 ret = dmac_alloc_threads(pl330);
1983 if (ret) {
1984 dev_err(pi->dev, "%s:%d Can't to create channels for DMAC!\n",
1985 __func__, __LINE__);
1986 dma_free_coherent(pi->dev,
1987 chans * pi->mcbufsz,
1988 pl330->mcode_cpu, pl330->mcode_bus);
1989 return ret;
1990 }
1991
1992 return 0;
1993}
1994
1995static int pl330_add(struct pl330_info *pi)
1996{
1997 struct pl330_dmac *pl330;
1998 void __iomem *regs;
1999 int i, ret;
2000
2001 if (!pi || !pi->dev)
2002 return -EINVAL;
2003
2004 /* If already added */
2005 if (pi->pl330_data)
2006 return -EINVAL;
2007
Boojin Kimb7d861d2011-12-26 18:49:52 +09002008 regs = pi->base;
2009
2010 /* Check if we can handle this DMAC */
Will Deacon09677172013-06-10 19:34:37 +01002011 if ((pi->pcfg.periph_id & 0xfffff) != PERIPH_ID_VAL) {
2012 dev_err(pi->dev, "PERIPH_ID 0x%x !\n", pi->pcfg.periph_id);
Boojin Kimb7d861d2011-12-26 18:49:52 +09002013 return -EINVAL;
2014 }
2015
2016 /* Read the configuration of the DMAC */
2017 read_dmac_config(pi);
2018
2019 if (pi->pcfg.num_events == 0) {
2020 dev_err(pi->dev, "%s:%d Can't work without events!\n",
2021 __func__, __LINE__);
2022 return -EINVAL;
2023 }
2024
2025 pl330 = kzalloc(sizeof(*pl330), GFP_KERNEL);
2026 if (!pl330) {
2027 dev_err(pi->dev, "%s:%d Can't allocate memory!\n",
2028 __func__, __LINE__);
2029 return -ENOMEM;
2030 }
2031
2032 /* Assign the info structure and private data */
2033 pl330->pinfo = pi;
2034 pi->pl330_data = pl330;
2035
2036 spin_lock_init(&pl330->lock);
2037
2038 INIT_LIST_HEAD(&pl330->req_done);
2039
2040 /* Use default MC buffer size if not provided */
2041 if (!pi->mcbufsz)
2042 pi->mcbufsz = MCODE_BUFF_PER_REQ * 2;
2043
2044 /* Mark all events as free */
2045 for (i = 0; i < pi->pcfg.num_events; i++)
2046 pl330->events[i] = -1;
2047
2048 /* Allocate resources needed by the DMAC */
2049 ret = dmac_alloc_resources(pl330);
2050 if (ret) {
2051 dev_err(pi->dev, "Unable to create channels for DMAC\n");
2052 kfree(pl330);
2053 return ret;
2054 }
2055
2056 tasklet_init(&pl330->tasks, pl330_dotask, (unsigned long) pl330);
2057
2058 pl330->state = INIT;
2059
2060 return 0;
2061}
2062
2063static int dmac_free_threads(struct pl330_dmac *pl330)
2064{
2065 struct pl330_info *pi = pl330->pinfo;
2066 int chans = pi->pcfg.num_chan;
2067 struct pl330_thread *thrd;
2068 int i;
2069
2070 /* Release Channel threads */
2071 for (i = 0; i < chans; i++) {
2072 thrd = &pl330->channels[i];
2073 pl330_release_channel((void *)thrd);
2074 }
2075
2076 /* Free memory */
2077 kfree(pl330->channels);
2078
2079 return 0;
2080}
2081
2082static void dmac_free_resources(struct pl330_dmac *pl330)
2083{
2084 struct pl330_info *pi = pl330->pinfo;
2085 int chans = pi->pcfg.num_chan;
2086
2087 dmac_free_threads(pl330);
2088
2089 dma_free_coherent(pi->dev, chans * pi->mcbufsz,
2090 pl330->mcode_cpu, pl330->mcode_bus);
2091}
2092
2093static void pl330_del(struct pl330_info *pi)
2094{
2095 struct pl330_dmac *pl330;
2096
2097 if (!pi || !pi->pl330_data)
2098 return;
2099
2100 pl330 = pi->pl330_data;
2101
2102 pl330->state = UNINIT;
2103
2104 tasklet_kill(&pl330->tasks);
2105
2106 /* Free DMAC resources */
2107 dmac_free_resources(pl330);
2108
2109 kfree(pl330);
2110 pi->pl330_data = NULL;
2111}
2112
Thomas Abraham3e2ec132011-10-24 11:43:02 +02002113/* forward declaration */
2114static struct amba_driver pl330_driver;
2115
Jassi Brarb3040e42010-05-23 20:28:19 -07002116static inline struct dma_pl330_chan *
2117to_pchan(struct dma_chan *ch)
2118{
2119 if (!ch)
2120 return NULL;
2121
2122 return container_of(ch, struct dma_pl330_chan, chan);
2123}
2124
2125static inline struct dma_pl330_desc *
2126to_desc(struct dma_async_tx_descriptor *tx)
2127{
2128 return container_of(tx, struct dma_pl330_desc, txd);
2129}
2130
Jassi Brarb3040e42010-05-23 20:28:19 -07002131static inline void fill_queue(struct dma_pl330_chan *pch)
2132{
2133 struct dma_pl330_desc *desc;
2134 int ret;
2135
2136 list_for_each_entry(desc, &pch->work_list, node) {
2137
2138 /* If already submitted */
2139 if (desc->status == BUSY)
Jassi Brar30fb9802013-02-13 16:13:14 +05302140 continue;
Jassi Brarb3040e42010-05-23 20:28:19 -07002141
2142 ret = pl330_submit_req(pch->pl330_chid,
2143 &desc->req);
2144 if (!ret) {
2145 desc->status = BUSY;
Jassi Brarb3040e42010-05-23 20:28:19 -07002146 } else if (ret == -EAGAIN) {
2147 /* QFull or DMAC Dying */
2148 break;
2149 } else {
2150 /* Unacceptable request */
2151 desc->status = DONE;
2152 dev_err(pch->dmac->pif.dev, "%s:%d Bad Desc(%d)\n",
2153 __func__, __LINE__, desc->txd.cookie);
2154 tasklet_schedule(&pch->task);
2155 }
2156 }
2157}
2158
2159static void pl330_tasklet(unsigned long data)
2160{
2161 struct dma_pl330_chan *pch = (struct dma_pl330_chan *)data;
2162 struct dma_pl330_desc *desc, *_dt;
2163 unsigned long flags;
Jassi Brarb3040e42010-05-23 20:28:19 -07002164
2165 spin_lock_irqsave(&pch->lock, flags);
2166
2167 /* Pick up ripe tomatoes */
2168 list_for_each_entry_safe(desc, _dt, &pch->work_list, node)
2169 if (desc->status == DONE) {
Tushar Behera30c1dc02012-05-23 16:47:31 +05302170 if (!pch->cyclic)
Vinod Kouleab21582012-05-11 11:24:41 +05302171 dma_cookie_complete(&desc->txd);
Lars-Peter Clausen39ff8612013-08-27 20:34:05 +02002172 list_move_tail(&desc->node, &pch->completed_list);
Jassi Brarb3040e42010-05-23 20:28:19 -07002173 }
2174
2175 /* Try to submit a req imm. next to the last completed cookie */
2176 fill_queue(pch);
2177
2178 /* Make sure the PL330 Channel thread is active */
2179 pl330_chan_ctrl(pch->pl330_chid, PL330_OP_START);
2180
Lars-Peter Clausen39ff8612013-08-27 20:34:05 +02002181 while (!list_empty(&pch->completed_list)) {
2182 dma_async_tx_callback callback;
2183 void *callback_param;
Jassi Brarb3040e42010-05-23 20:28:19 -07002184
Lars-Peter Clausen39ff8612013-08-27 20:34:05 +02002185 desc = list_first_entry(&pch->completed_list,
2186 struct dma_pl330_desc, node);
2187
2188 callback = desc->txd.callback;
2189 callback_param = desc->txd.callback_param;
2190
2191 if (pch->cyclic) {
2192 desc->status = PREP;
2193 list_move_tail(&desc->node, &pch->work_list);
2194 } else {
2195 desc->status = FREE;
2196 list_move_tail(&desc->node, &pch->dmac->desc_pool);
2197 }
2198
Dan Williamsd38a8c62013-10-18 19:35:23 +02002199 dma_descriptor_unmap(&desc->txd);
2200
Lars-Peter Clausen39ff8612013-08-27 20:34:05 +02002201 if (callback) {
2202 spin_unlock_irqrestore(&pch->lock, flags);
2203 callback(callback_param);
2204 spin_lock_irqsave(&pch->lock, flags);
2205 }
2206 }
2207 spin_unlock_irqrestore(&pch->lock, flags);
Jassi Brarb3040e42010-05-23 20:28:19 -07002208}
2209
2210static void dma_pl330_rqcb(void *token, enum pl330_op_err err)
2211{
2212 struct dma_pl330_desc *desc = token;
2213 struct dma_pl330_chan *pch = desc->pchan;
2214 unsigned long flags;
2215
2216 /* If desc aborted */
2217 if (!pch)
2218 return;
2219
2220 spin_lock_irqsave(&pch->lock, flags);
2221
2222 desc->status = DONE;
2223
2224 spin_unlock_irqrestore(&pch->lock, flags);
2225
2226 tasklet_schedule(&pch->task);
2227}
2228
Thomas Abraham3e2ec132011-10-24 11:43:02 +02002229bool pl330_filter(struct dma_chan *chan, void *param)
2230{
Thomas Abrahamcd072512011-10-24 11:43:11 +02002231 u8 *peri_id;
Thomas Abraham3e2ec132011-10-24 11:43:02 +02002232
2233 if (chan->device->dev->driver != &pl330_driver.drv)
2234 return false;
2235
Thomas Abrahamcd072512011-10-24 11:43:11 +02002236 peri_id = chan->private;
Dan Carpenter2f986ec2013-11-08 12:51:16 +03002237 return *peri_id == (unsigned long)param;
Thomas Abraham3e2ec132011-10-24 11:43:02 +02002238}
2239EXPORT_SYMBOL(pl330_filter);
2240
Padmavathi Vennaa80258f2013-02-14 09:10:06 +05302241static struct dma_chan *of_dma_pl330_xlate(struct of_phandle_args *dma_spec,
2242 struct of_dma *ofdma)
2243{
2244 int count = dma_spec->args_count;
2245 struct dma_pl330_dmac *pdmac = ofdma->of_dma_data;
Lars-Peter Clausen70cbb162014-01-11 20:08:39 +01002246 unsigned int chan_id;
Padmavathi Vennaa80258f2013-02-14 09:10:06 +05302247
2248 if (count != 1)
2249 return NULL;
2250
Lars-Peter Clausen70cbb162014-01-11 20:08:39 +01002251 chan_id = dma_spec->args[0];
2252 if (chan_id >= pdmac->num_peripherals)
2253 return NULL;
Padmavathi Vennaa80258f2013-02-14 09:10:06 +05302254
Lars-Peter Clausen70cbb162014-01-11 20:08:39 +01002255 return dma_get_slave_channel(&pdmac->peripherals[chan_id].chan);
Padmavathi Vennaa80258f2013-02-14 09:10:06 +05302256}
2257
Jassi Brarb3040e42010-05-23 20:28:19 -07002258static int pl330_alloc_chan_resources(struct dma_chan *chan)
2259{
2260 struct dma_pl330_chan *pch = to_pchan(chan);
2261 struct dma_pl330_dmac *pdmac = pch->dmac;
2262 unsigned long flags;
2263
2264 spin_lock_irqsave(&pch->lock, flags);
2265
Russell King - ARM Linuxd3ee98cdc2012-03-06 22:35:47 +00002266 dma_cookie_init(chan);
Boojin Kim42bc9cf2011-09-02 09:44:33 +09002267 pch->cyclic = false;
Jassi Brarb3040e42010-05-23 20:28:19 -07002268
2269 pch->pl330_chid = pl330_request_channel(&pdmac->pif);
2270 if (!pch->pl330_chid) {
2271 spin_unlock_irqrestore(&pch->lock, flags);
Inderpal Singh02747882012-09-17 09:57:45 +05302272 return -ENOMEM;
Jassi Brarb3040e42010-05-23 20:28:19 -07002273 }
2274
2275 tasklet_init(&pch->task, pl330_tasklet, (unsigned long) pch);
2276
2277 spin_unlock_irqrestore(&pch->lock, flags);
2278
2279 return 1;
2280}
2281
2282static int pl330_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd, unsigned long arg)
2283{
2284 struct dma_pl330_chan *pch = to_pchan(chan);
Lars-Peter Clausen39ff8612013-08-27 20:34:05 +02002285 struct dma_pl330_desc *desc;
Jassi Brarb3040e42010-05-23 20:28:19 -07002286 unsigned long flags;
Boojin Kim1d0c1d62011-09-02 09:44:31 +09002287 struct dma_pl330_dmac *pdmac = pch->dmac;
2288 struct dma_slave_config *slave_config;
Boojin Kimae43b882011-09-02 09:44:32 +09002289 LIST_HEAD(list);
Jassi Brarb3040e42010-05-23 20:28:19 -07002290
Boojin Kim1d0c1d62011-09-02 09:44:31 +09002291 switch (cmd) {
2292 case DMA_TERMINATE_ALL:
2293 spin_lock_irqsave(&pch->lock, flags);
2294
2295 /* FLUSH the PL330 Channel thread */
2296 pl330_chan_ctrl(pch->pl330_chid, PL330_OP_FLUSH);
2297
2298 /* Mark all desc done */
Lars-Peter Clausen04abf5d2014-01-11 20:08:38 +01002299 list_for_each_entry(desc, &pch->submitted_list, node) {
2300 desc->status = FREE;
2301 dma_cookie_complete(&desc->txd);
2302 }
2303
Lars-Peter Clausen39ff8612013-08-27 20:34:05 +02002304 list_for_each_entry(desc, &pch->work_list , node) {
2305 desc->status = FREE;
2306 dma_cookie_complete(&desc->txd);
Boojin Kimae43b882011-09-02 09:44:32 +09002307 }
Boojin Kim1d0c1d62011-09-02 09:44:31 +09002308
Lars-Peter Clausen39ff8612013-08-27 20:34:05 +02002309 list_for_each_entry(desc, &pch->completed_list , node) {
2310 desc->status = FREE;
2311 dma_cookie_complete(&desc->txd);
2312 }
2313
Lars-Peter Clausen04abf5d2014-01-11 20:08:38 +01002314 list_splice_tail_init(&pch->submitted_list, &pdmac->desc_pool);
Lars-Peter Clausen39ff8612013-08-27 20:34:05 +02002315 list_splice_tail_init(&pch->work_list, &pdmac->desc_pool);
2316 list_splice_tail_init(&pch->completed_list, &pdmac->desc_pool);
Boojin Kim1d0c1d62011-09-02 09:44:31 +09002317 spin_unlock_irqrestore(&pch->lock, flags);
Boojin Kim1d0c1d62011-09-02 09:44:31 +09002318 break;
2319 case DMA_SLAVE_CONFIG:
2320 slave_config = (struct dma_slave_config *)arg;
2321
Vinod Kouldb8196d2011-10-13 22:34:23 +05302322 if (slave_config->direction == DMA_MEM_TO_DEV) {
Boojin Kim1d0c1d62011-09-02 09:44:31 +09002323 if (slave_config->dst_addr)
2324 pch->fifo_addr = slave_config->dst_addr;
2325 if (slave_config->dst_addr_width)
2326 pch->burst_sz = __ffs(slave_config->dst_addr_width);
2327 if (slave_config->dst_maxburst)
2328 pch->burst_len = slave_config->dst_maxburst;
Vinod Kouldb8196d2011-10-13 22:34:23 +05302329 } else if (slave_config->direction == DMA_DEV_TO_MEM) {
Boojin Kim1d0c1d62011-09-02 09:44:31 +09002330 if (slave_config->src_addr)
2331 pch->fifo_addr = slave_config->src_addr;
2332 if (slave_config->src_addr_width)
2333 pch->burst_sz = __ffs(slave_config->src_addr_width);
2334 if (slave_config->src_maxburst)
2335 pch->burst_len = slave_config->src_maxburst;
2336 }
2337 break;
2338 default:
2339 dev_err(pch->dmac->pif.dev, "Not supported command.\n");
Jassi Brarb3040e42010-05-23 20:28:19 -07002340 return -ENXIO;
Boojin Kim1d0c1d62011-09-02 09:44:31 +09002341 }
Jassi Brarb3040e42010-05-23 20:28:19 -07002342
2343 return 0;
2344}
2345
2346static void pl330_free_chan_resources(struct dma_chan *chan)
2347{
2348 struct dma_pl330_chan *pch = to_pchan(chan);
2349 unsigned long flags;
2350
Jassi Brarb3040e42010-05-23 20:28:19 -07002351 tasklet_kill(&pch->task);
2352
Bartlomiej Zolnierkiewiczda331ba2013-07-03 15:00:43 -07002353 spin_lock_irqsave(&pch->lock, flags);
2354
Jassi Brarb3040e42010-05-23 20:28:19 -07002355 pl330_release_channel(pch->pl330_chid);
2356 pch->pl330_chid = NULL;
2357
Boojin Kim42bc9cf2011-09-02 09:44:33 +09002358 if (pch->cyclic)
2359 list_splice_tail_init(&pch->work_list, &pch->dmac->desc_pool);
2360
Jassi Brarb3040e42010-05-23 20:28:19 -07002361 spin_unlock_irqrestore(&pch->lock, flags);
2362}
2363
2364static enum dma_status
2365pl330_tx_status(struct dma_chan *chan, dma_cookie_t cookie,
2366 struct dma_tx_state *txstate)
2367{
Russell King - ARM Linux96a2af42012-03-06 22:35:27 +00002368 return dma_cookie_status(chan, cookie, txstate);
Jassi Brarb3040e42010-05-23 20:28:19 -07002369}
2370
2371static void pl330_issue_pending(struct dma_chan *chan)
2372{
Lars-Peter Clausen04abf5d2014-01-11 20:08:38 +01002373 struct dma_pl330_chan *pch = to_pchan(chan);
2374 unsigned long flags;
2375
2376 spin_lock_irqsave(&pch->lock, flags);
2377 list_splice_tail_init(&pch->submitted_list, &pch->work_list);
2378 spin_unlock_irqrestore(&pch->lock, flags);
2379
2380 pl330_tasklet((unsigned long)pch);
Jassi Brarb3040e42010-05-23 20:28:19 -07002381}
2382
2383/*
2384 * We returned the last one of the circular list of descriptor(s)
2385 * from prep_xxx, so the argument to submit corresponds to the last
2386 * descriptor of the list.
2387 */
2388static dma_cookie_t pl330_tx_submit(struct dma_async_tx_descriptor *tx)
2389{
2390 struct dma_pl330_desc *desc, *last = to_desc(tx);
2391 struct dma_pl330_chan *pch = to_pchan(tx->chan);
2392 dma_cookie_t cookie;
2393 unsigned long flags;
2394
2395 spin_lock_irqsave(&pch->lock, flags);
2396
2397 /* Assign cookies to all nodes */
Jassi Brarb3040e42010-05-23 20:28:19 -07002398 while (!list_empty(&last->node)) {
2399 desc = list_entry(last->node.next, struct dma_pl330_desc, node);
Lars-Peter Clausenfc514462013-07-23 10:24:50 +02002400 if (pch->cyclic) {
2401 desc->txd.callback = last->txd.callback;
2402 desc->txd.callback_param = last->txd.callback_param;
2403 }
Jassi Brarb3040e42010-05-23 20:28:19 -07002404
Russell King - ARM Linux884485e2012-03-06 22:34:46 +00002405 dma_cookie_assign(&desc->txd);
Jassi Brarb3040e42010-05-23 20:28:19 -07002406
Lars-Peter Clausen04abf5d2014-01-11 20:08:38 +01002407 list_move_tail(&desc->node, &pch->submitted_list);
Jassi Brarb3040e42010-05-23 20:28:19 -07002408 }
2409
Russell King - ARM Linux884485e2012-03-06 22:34:46 +00002410 cookie = dma_cookie_assign(&last->txd);
Lars-Peter Clausen04abf5d2014-01-11 20:08:38 +01002411 list_add_tail(&last->node, &pch->submitted_list);
Jassi Brarb3040e42010-05-23 20:28:19 -07002412 spin_unlock_irqrestore(&pch->lock, flags);
2413
2414 return cookie;
2415}
2416
2417static inline void _init_desc(struct dma_pl330_desc *desc)
2418{
Jassi Brarb3040e42010-05-23 20:28:19 -07002419 desc->req.x = &desc->px;
2420 desc->req.token = desc;
2421 desc->rqcfg.swap = SWAP_NO;
Lars-Peter Clausenf0564c72014-07-06 20:32:19 +02002422 desc->rqcfg.scctl = CCTRL0;
2423 desc->rqcfg.dcctl = CCTRL0;
Jassi Brarb3040e42010-05-23 20:28:19 -07002424 desc->req.cfg = &desc->rqcfg;
2425 desc->req.xfer_cb = dma_pl330_rqcb;
2426 desc->txd.tx_submit = pl330_tx_submit;
2427
2428 INIT_LIST_HEAD(&desc->node);
2429}
2430
2431/* Returns the number of descriptors added to the DMAC pool */
Sachin Kamat5a67ac52012-06-04 17:09:45 +05302432static int add_desc(struct dma_pl330_dmac *pdmac, gfp_t flg, int count)
Jassi Brarb3040e42010-05-23 20:28:19 -07002433{
2434 struct dma_pl330_desc *desc;
2435 unsigned long flags;
2436 int i;
2437
2438 if (!pdmac)
2439 return 0;
2440
Will Deacon0baf8f62013-12-02 18:01:30 +00002441 desc = kcalloc(count, sizeof(*desc), flg);
Jassi Brarb3040e42010-05-23 20:28:19 -07002442 if (!desc)
2443 return 0;
2444
2445 spin_lock_irqsave(&pdmac->pool_lock, flags);
2446
2447 for (i = 0; i < count; i++) {
2448 _init_desc(&desc[i]);
2449 list_add_tail(&desc[i].node, &pdmac->desc_pool);
2450 }
2451
2452 spin_unlock_irqrestore(&pdmac->pool_lock, flags);
2453
2454 return count;
2455}
2456
2457static struct dma_pl330_desc *
2458pluck_desc(struct dma_pl330_dmac *pdmac)
2459{
2460 struct dma_pl330_desc *desc = NULL;
2461 unsigned long flags;
2462
2463 if (!pdmac)
2464 return NULL;
2465
2466 spin_lock_irqsave(&pdmac->pool_lock, flags);
2467
2468 if (!list_empty(&pdmac->desc_pool)) {
2469 desc = list_entry(pdmac->desc_pool.next,
2470 struct dma_pl330_desc, node);
2471
2472 list_del_init(&desc->node);
2473
2474 desc->status = PREP;
2475 desc->txd.callback = NULL;
2476 }
2477
2478 spin_unlock_irqrestore(&pdmac->pool_lock, flags);
2479
2480 return desc;
2481}
2482
2483static struct dma_pl330_desc *pl330_get_desc(struct dma_pl330_chan *pch)
2484{
2485 struct dma_pl330_dmac *pdmac = pch->dmac;
Thomas Abrahamcd072512011-10-24 11:43:11 +02002486 u8 *peri_id = pch->chan.private;
Jassi Brarb3040e42010-05-23 20:28:19 -07002487 struct dma_pl330_desc *desc;
2488
2489 /* Pluck one desc from the pool of DMAC */
2490 desc = pluck_desc(pdmac);
2491
2492 /* If the DMAC pool is empty, alloc new */
2493 if (!desc) {
2494 if (!add_desc(pdmac, GFP_ATOMIC, 1))
2495 return NULL;
2496
2497 /* Try again */
2498 desc = pluck_desc(pdmac);
2499 if (!desc) {
2500 dev_err(pch->dmac->pif.dev,
2501 "%s:%d ALERT!\n", __func__, __LINE__);
2502 return NULL;
2503 }
2504 }
2505
2506 /* Initialize the descriptor */
2507 desc->pchan = pch;
2508 desc->txd.cookie = 0;
2509 async_tx_ack(&desc->txd);
2510
Thomas Abrahamcd072512011-10-24 11:43:11 +02002511 desc->req.peri = peri_id ? pch->chan.chan_id : 0;
Boojin Kim3ecf51a2011-12-26 18:55:47 +09002512 desc->rqcfg.pcfg = &pch->dmac->pif.pcfg;
Jassi Brarb3040e42010-05-23 20:28:19 -07002513
2514 dma_async_tx_descriptor_init(&desc->txd, &pch->chan);
2515
2516 return desc;
2517}
2518
2519static inline void fill_px(struct pl330_xfer *px,
2520 dma_addr_t dst, dma_addr_t src, size_t len)
2521{
Jassi Brarb3040e42010-05-23 20:28:19 -07002522 px->bytes = len;
2523 px->dst_addr = dst;
2524 px->src_addr = src;
2525}
2526
2527static struct dma_pl330_desc *
2528__pl330_prep_dma_memcpy(struct dma_pl330_chan *pch, dma_addr_t dst,
2529 dma_addr_t src, size_t len)
2530{
2531 struct dma_pl330_desc *desc = pl330_get_desc(pch);
2532
2533 if (!desc) {
2534 dev_err(pch->dmac->pif.dev, "%s:%d Unable to fetch desc\n",
2535 __func__, __LINE__);
2536 return NULL;
2537 }
2538
2539 /*
2540 * Ideally we should lookout for reqs bigger than
2541 * those that can be programmed with 256 bytes of
2542 * MC buffer, but considering a req size is seldom
2543 * going to be word-unaligned and more than 200MB,
2544 * we take it easy.
2545 * Also, should the limit is reached we'd rather
2546 * have the platform increase MC buffer size than
2547 * complicating this API driver.
2548 */
2549 fill_px(&desc->px, dst, src, len);
2550
2551 return desc;
2552}
2553
2554/* Call after fixing burst size */
2555static inline int get_burst_len(struct dma_pl330_desc *desc, size_t len)
2556{
2557 struct dma_pl330_chan *pch = desc->pchan;
2558 struct pl330_info *pi = &pch->dmac->pif;
2559 int burst_len;
2560
2561 burst_len = pi->pcfg.data_bus_width / 8;
2562 burst_len *= pi->pcfg.data_buf_dep;
2563 burst_len >>= desc->rqcfg.brst_size;
2564
2565 /* src/dst_burst_len can't be more than 16 */
2566 if (burst_len > 16)
2567 burst_len = 16;
2568
2569 while (burst_len > 1) {
2570 if (!(len % (burst_len << desc->rqcfg.brst_size)))
2571 break;
2572 burst_len--;
2573 }
2574
2575 return burst_len;
2576}
2577
Boojin Kim42bc9cf2011-09-02 09:44:33 +09002578static struct dma_async_tx_descriptor *pl330_prep_dma_cyclic(
2579 struct dma_chan *chan, dma_addr_t dma_addr, size_t len,
Alexandre Bounine185ecb52012-03-08 15:35:13 -05002580 size_t period_len, enum dma_transfer_direction direction,
Peter Ujfalusiec8b5e42012-09-14 15:05:47 +03002581 unsigned long flags, void *context)
Boojin Kim42bc9cf2011-09-02 09:44:33 +09002582{
Lars-Peter Clausenfc514462013-07-23 10:24:50 +02002583 struct dma_pl330_desc *desc = NULL, *first = NULL;
Boojin Kim42bc9cf2011-09-02 09:44:33 +09002584 struct dma_pl330_chan *pch = to_pchan(chan);
Lars-Peter Clausenfc514462013-07-23 10:24:50 +02002585 struct dma_pl330_dmac *pdmac = pch->dmac;
2586 unsigned int i;
Boojin Kim42bc9cf2011-09-02 09:44:33 +09002587 dma_addr_t dst;
2588 dma_addr_t src;
2589
Lars-Peter Clausenfc514462013-07-23 10:24:50 +02002590 if (len % period_len != 0)
Boojin Kim42bc9cf2011-09-02 09:44:33 +09002591 return NULL;
Boojin Kim42bc9cf2011-09-02 09:44:33 +09002592
Lars-Peter Clausenfc514462013-07-23 10:24:50 +02002593 if (!is_slave_direction(direction)) {
Boojin Kim42bc9cf2011-09-02 09:44:33 +09002594 dev_err(pch->dmac->pif.dev, "%s:%d Invalid dma direction\n",
2595 __func__, __LINE__);
2596 return NULL;
2597 }
2598
Lars-Peter Clausenfc514462013-07-23 10:24:50 +02002599 for (i = 0; i < len / period_len; i++) {
2600 desc = pl330_get_desc(pch);
2601 if (!desc) {
2602 dev_err(pch->dmac->pif.dev, "%s:%d Unable to fetch desc\n",
2603 __func__, __LINE__);
2604
2605 if (!first)
2606 return NULL;
2607
2608 spin_lock_irqsave(&pdmac->pool_lock, flags);
2609
2610 while (!list_empty(&first->node)) {
2611 desc = list_entry(first->node.next,
2612 struct dma_pl330_desc, node);
2613 list_move_tail(&desc->node, &pdmac->desc_pool);
2614 }
2615
2616 list_move_tail(&first->node, &pdmac->desc_pool);
2617
2618 spin_unlock_irqrestore(&pdmac->pool_lock, flags);
2619
2620 return NULL;
2621 }
2622
2623 switch (direction) {
2624 case DMA_MEM_TO_DEV:
2625 desc->rqcfg.src_inc = 1;
2626 desc->rqcfg.dst_inc = 0;
Lars-Peter Clausenfc514462013-07-23 10:24:50 +02002627 src = dma_addr;
2628 dst = pch->fifo_addr;
2629 break;
2630 case DMA_DEV_TO_MEM:
2631 desc->rqcfg.src_inc = 0;
2632 desc->rqcfg.dst_inc = 1;
Lars-Peter Clausenfc514462013-07-23 10:24:50 +02002633 src = pch->fifo_addr;
2634 dst = dma_addr;
2635 break;
2636 default:
2637 break;
2638 }
2639
Lars-Peter Clausen585a9d02014-07-06 20:32:18 +02002640 desc->req.rqtype = direction;
Lars-Peter Clausenfc514462013-07-23 10:24:50 +02002641 desc->rqcfg.brst_size = pch->burst_sz;
2642 desc->rqcfg.brst_len = 1;
2643 fill_px(&desc->px, dst, src, period_len);
2644
2645 if (!first)
2646 first = desc;
2647 else
2648 list_add_tail(&desc->node, &first->node);
2649
2650 dma_addr += period_len;
2651 }
2652
2653 if (!desc)
2654 return NULL;
Boojin Kim42bc9cf2011-09-02 09:44:33 +09002655
2656 pch->cyclic = true;
Lars-Peter Clausenfc514462013-07-23 10:24:50 +02002657 desc->txd.flags = flags;
Boojin Kim42bc9cf2011-09-02 09:44:33 +09002658
2659 return &desc->txd;
2660}
2661
Jassi Brarb3040e42010-05-23 20:28:19 -07002662static struct dma_async_tx_descriptor *
2663pl330_prep_dma_memcpy(struct dma_chan *chan, dma_addr_t dst,
2664 dma_addr_t src, size_t len, unsigned long flags)
2665{
2666 struct dma_pl330_desc *desc;
2667 struct dma_pl330_chan *pch = to_pchan(chan);
Jassi Brarb3040e42010-05-23 20:28:19 -07002668 struct pl330_info *pi;
2669 int burst;
2670
Rob Herring4e0e6102011-07-25 16:05:04 -05002671 if (unlikely(!pch || !len))
Jassi Brarb3040e42010-05-23 20:28:19 -07002672 return NULL;
2673
Jassi Brarb3040e42010-05-23 20:28:19 -07002674 pi = &pch->dmac->pif;
2675
2676 desc = __pl330_prep_dma_memcpy(pch, dst, src, len);
2677 if (!desc)
2678 return NULL;
2679
2680 desc->rqcfg.src_inc = 1;
2681 desc->rqcfg.dst_inc = 1;
Lars-Peter Clausen585a9d02014-07-06 20:32:18 +02002682 desc->req.rqtype = DMA_MEM_TO_MEM;
Jassi Brarb3040e42010-05-23 20:28:19 -07002683
2684 /* Select max possible burst size */
2685 burst = pi->pcfg.data_bus_width / 8;
2686
2687 while (burst > 1) {
2688 if (!(len % burst))
2689 break;
2690 burst /= 2;
2691 }
2692
2693 desc->rqcfg.brst_size = 0;
2694 while (burst != (1 << desc->rqcfg.brst_size))
2695 desc->rqcfg.brst_size++;
2696
2697 desc->rqcfg.brst_len = get_burst_len(desc, len);
2698
2699 desc->txd.flags = flags;
2700
2701 return &desc->txd;
2702}
2703
Chanho Park52a9d172013-08-09 20:11:33 +09002704static void __pl330_giveback_desc(struct dma_pl330_dmac *pdmac,
2705 struct dma_pl330_desc *first)
2706{
2707 unsigned long flags;
2708 struct dma_pl330_desc *desc;
2709
2710 if (!first)
2711 return;
2712
2713 spin_lock_irqsave(&pdmac->pool_lock, flags);
2714
2715 while (!list_empty(&first->node)) {
2716 desc = list_entry(first->node.next,
2717 struct dma_pl330_desc, node);
2718 list_move_tail(&desc->node, &pdmac->desc_pool);
2719 }
2720
2721 list_move_tail(&first->node, &pdmac->desc_pool);
2722
2723 spin_unlock_irqrestore(&pdmac->pool_lock, flags);
2724}
2725
Jassi Brarb3040e42010-05-23 20:28:19 -07002726static struct dma_async_tx_descriptor *
2727pl330_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl,
Vinod Kouldb8196d2011-10-13 22:34:23 +05302728 unsigned int sg_len, enum dma_transfer_direction direction,
Alexandre Bounine185ecb52012-03-08 15:35:13 -05002729 unsigned long flg, void *context)
Jassi Brarb3040e42010-05-23 20:28:19 -07002730{
2731 struct dma_pl330_desc *first, *desc = NULL;
2732 struct dma_pl330_chan *pch = to_pchan(chan);
Jassi Brarb3040e42010-05-23 20:28:19 -07002733 struct scatterlist *sg;
Boojin Kim1b9bb712011-09-02 09:44:30 +09002734 int i;
Jassi Brarb3040e42010-05-23 20:28:19 -07002735 dma_addr_t addr;
2736
Thomas Abrahamcd072512011-10-24 11:43:11 +02002737 if (unlikely(!pch || !sgl || !sg_len))
Jassi Brarb3040e42010-05-23 20:28:19 -07002738 return NULL;
2739
Boojin Kim1b9bb712011-09-02 09:44:30 +09002740 addr = pch->fifo_addr;
Jassi Brarb3040e42010-05-23 20:28:19 -07002741
2742 first = NULL;
2743
2744 for_each_sg(sgl, sg, sg_len, i) {
2745
2746 desc = pl330_get_desc(pch);
2747 if (!desc) {
2748 struct dma_pl330_dmac *pdmac = pch->dmac;
2749
2750 dev_err(pch->dmac->pif.dev,
2751 "%s:%d Unable to fetch desc\n",
2752 __func__, __LINE__);
Chanho Park52a9d172013-08-09 20:11:33 +09002753 __pl330_giveback_desc(pdmac, first);
Jassi Brarb3040e42010-05-23 20:28:19 -07002754
2755 return NULL;
2756 }
2757
2758 if (!first)
2759 first = desc;
2760 else
2761 list_add_tail(&desc->node, &first->node);
2762
Vinod Kouldb8196d2011-10-13 22:34:23 +05302763 if (direction == DMA_MEM_TO_DEV) {
Jassi Brarb3040e42010-05-23 20:28:19 -07002764 desc->rqcfg.src_inc = 1;
2765 desc->rqcfg.dst_inc = 0;
2766 fill_px(&desc->px,
2767 addr, sg_dma_address(sg), sg_dma_len(sg));
2768 } else {
2769 desc->rqcfg.src_inc = 0;
2770 desc->rqcfg.dst_inc = 1;
2771 fill_px(&desc->px,
2772 sg_dma_address(sg), addr, sg_dma_len(sg));
2773 }
2774
Boojin Kim1b9bb712011-09-02 09:44:30 +09002775 desc->rqcfg.brst_size = pch->burst_sz;
Jassi Brarb3040e42010-05-23 20:28:19 -07002776 desc->rqcfg.brst_len = 1;
Lars-Peter Clausen585a9d02014-07-06 20:32:18 +02002777 desc->req.rqtype = direction;
Jassi Brarb3040e42010-05-23 20:28:19 -07002778 }
2779
2780 /* Return the last desc in the chain */
2781 desc->txd.flags = flg;
2782 return &desc->txd;
2783}
2784
2785static irqreturn_t pl330_irq_handler(int irq, void *data)
2786{
2787 if (pl330_update(data))
2788 return IRQ_HANDLED;
2789 else
2790 return IRQ_NONE;
2791}
2792
Lars-Peter Clausenca38ff12013-07-15 17:53:08 +02002793#define PL330_DMA_BUSWIDTHS \
2794 BIT(DMA_SLAVE_BUSWIDTH_UNDEFINED) | \
2795 BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | \
2796 BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) | \
2797 BIT(DMA_SLAVE_BUSWIDTH_4_BYTES) | \
2798 BIT(DMA_SLAVE_BUSWIDTH_8_BYTES)
2799
2800static int pl330_dma_device_slave_caps(struct dma_chan *dchan,
2801 struct dma_slave_caps *caps)
2802{
2803 caps->src_addr_widths = PL330_DMA_BUSWIDTHS;
2804 caps->dstn_addr_widths = PL330_DMA_BUSWIDTHS;
2805 caps->directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV);
2806 caps->cmd_pause = false;
2807 caps->cmd_terminate = true;
Lars-Peter Clausenbfb9bb42014-01-11 14:02:17 +01002808 caps->residue_granularity = DMA_RESIDUE_GRANULARITY_DESCRIPTOR;
Lars-Peter Clausenca38ff12013-07-15 17:53:08 +02002809
Lars-Peter Clausenca38ff12013-07-15 17:53:08 +02002810 return 0;
2811}
2812
Bill Pemberton463a1f82012-11-19 13:22:55 -05002813static int
Russell Kingaa25afa2011-02-19 15:55:00 +00002814pl330_probe(struct amba_device *adev, const struct amba_id *id)
Jassi Brarb3040e42010-05-23 20:28:19 -07002815{
2816 struct dma_pl330_platdata *pdat;
2817 struct dma_pl330_dmac *pdmac;
Padmavathi Venna0b94c572013-03-05 14:55:31 +05302818 struct dma_pl330_chan *pch, *_p;
Jassi Brarb3040e42010-05-23 20:28:19 -07002819 struct pl330_info *pi;
2820 struct dma_device *pd;
2821 struct resource *res;
2822 int i, ret, irq;
Rob Herring4e0e6102011-07-25 16:05:04 -05002823 int num_chan;
Jassi Brarb3040e42010-05-23 20:28:19 -07002824
Jingoo Hand4adcc02013-07-30 17:09:11 +09002825 pdat = dev_get_platdata(&adev->dev);
Jassi Brarb3040e42010-05-23 20:28:19 -07002826
Russell King64113012013-06-27 10:29:32 +01002827 ret = dma_set_mask_and_coherent(&adev->dev, DMA_BIT_MASK(32));
2828 if (ret)
2829 return ret;
2830
Jassi Brarb3040e42010-05-23 20:28:19 -07002831 /* Allocate a new DMAC and its Channels */
Sachin Kamate4d43c12012-11-15 06:27:50 +00002832 pdmac = devm_kzalloc(&adev->dev, sizeof(*pdmac), GFP_KERNEL);
Jassi Brarb3040e42010-05-23 20:28:19 -07002833 if (!pdmac) {
2834 dev_err(&adev->dev, "unable to allocate mem\n");
2835 return -ENOMEM;
2836 }
2837
2838 pi = &pdmac->pif;
2839 pi->dev = &adev->dev;
2840 pi->pl330_data = NULL;
Rob Herring4e0e6102011-07-25 16:05:04 -05002841 pi->mcbufsz = pdat ? pdat->mcbuf_sz : 0;
Jassi Brarb3040e42010-05-23 20:28:19 -07002842
2843 res = &adev->res;
Sachin Kamatbcc7fa92013-03-04 14:36:27 +05302844 pi->base = devm_ioremap_resource(&adev->dev, res);
2845 if (IS_ERR(pi->base))
2846 return PTR_ERR(pi->base);
Jassi Brarb3040e42010-05-23 20:28:19 -07002847
Boojin Kima2f52032011-09-02 09:44:29 +09002848 amba_set_drvdata(adev, pdmac);
2849
Dan Carpenter02808b42013-11-08 12:50:24 +03002850 for (i = 0; i < AMBA_NR_IRQS; i++) {
Michal Simeke98b3ca2013-09-30 08:50:48 +02002851 irq = adev->irq[i];
2852 if (irq) {
2853 ret = devm_request_irq(&adev->dev, irq,
2854 pl330_irq_handler, 0,
2855 dev_name(&adev->dev), pi);
2856 if (ret)
2857 return ret;
2858 } else {
2859 break;
2860 }
2861 }
Jassi Brarb3040e42010-05-23 20:28:19 -07002862
Will Deacon09677172013-06-10 19:34:37 +01002863 pi->pcfg.periph_id = adev->periphid;
Jassi Brarb3040e42010-05-23 20:28:19 -07002864 ret = pl330_add(pi);
2865 if (ret)
Michal Simek173e8382013-09-04 16:40:17 +02002866 return ret;
Jassi Brarb3040e42010-05-23 20:28:19 -07002867
2868 INIT_LIST_HEAD(&pdmac->desc_pool);
2869 spin_lock_init(&pdmac->pool_lock);
2870
2871 /* Create a descriptor pool of default size */
2872 if (!add_desc(pdmac, GFP_KERNEL, NR_DEFAULT_DESC))
2873 dev_warn(&adev->dev, "unable to allocate desc\n");
2874
2875 pd = &pdmac->ddma;
2876 INIT_LIST_HEAD(&pd->channels);
2877
2878 /* Initialize channel parameters */
Olof Johanssonc8473822012-04-08 16:26:19 -07002879 if (pdat)
2880 num_chan = max_t(int, pdat->nr_valid_peri, pi->pcfg.num_chan);
2881 else
2882 num_chan = max_t(int, pi->pcfg.num_peri, pi->pcfg.num_chan);
2883
Lars-Peter Clausen70cbb162014-01-11 20:08:39 +01002884 pdmac->num_peripherals = num_chan;
2885
Rob Herring4e0e6102011-07-25 16:05:04 -05002886 pdmac->peripherals = kzalloc(num_chan * sizeof(*pch), GFP_KERNEL);
Sachin Kamat61c6e752012-09-17 15:20:23 +05302887 if (!pdmac->peripherals) {
2888 ret = -ENOMEM;
2889 dev_err(&adev->dev, "unable to allocate pdmac->peripherals\n");
Sachin Kamate4d43c12012-11-15 06:27:50 +00002890 goto probe_err2;
Sachin Kamat61c6e752012-09-17 15:20:23 +05302891 }
Jassi Brarb3040e42010-05-23 20:28:19 -07002892
Rob Herring4e0e6102011-07-25 16:05:04 -05002893 for (i = 0; i < num_chan; i++) {
2894 pch = &pdmac->peripherals[i];
Thomas Abraham93ed5542011-10-24 11:43:31 +02002895 if (!adev->dev.of_node)
2896 pch->chan.private = pdat ? &pdat->peri_id[i] : NULL;
2897 else
2898 pch->chan.private = adev->dev.of_node;
Jassi Brarb3040e42010-05-23 20:28:19 -07002899
Lars-Peter Clausen04abf5d2014-01-11 20:08:38 +01002900 INIT_LIST_HEAD(&pch->submitted_list);
Jassi Brarb3040e42010-05-23 20:28:19 -07002901 INIT_LIST_HEAD(&pch->work_list);
Lars-Peter Clausen39ff8612013-08-27 20:34:05 +02002902 INIT_LIST_HEAD(&pch->completed_list);
Jassi Brarb3040e42010-05-23 20:28:19 -07002903 spin_lock_init(&pch->lock);
2904 pch->pl330_chid = NULL;
Jassi Brarb3040e42010-05-23 20:28:19 -07002905 pch->chan.device = pd;
Jassi Brarb3040e42010-05-23 20:28:19 -07002906 pch->dmac = pdmac;
2907
2908 /* Add the channel to the DMAC list */
Jassi Brarb3040e42010-05-23 20:28:19 -07002909 list_add_tail(&pch->chan.device_node, &pd->channels);
2910 }
2911
2912 pd->dev = &adev->dev;
Thomas Abraham93ed5542011-10-24 11:43:31 +02002913 if (pdat) {
Thomas Abrahamcd072512011-10-24 11:43:11 +02002914 pd->cap_mask = pdat->cap_mask;
Thomas Abraham93ed5542011-10-24 11:43:31 +02002915 } else {
Thomas Abrahamcd072512011-10-24 11:43:11 +02002916 dma_cap_set(DMA_MEMCPY, pd->cap_mask);
Thomas Abraham93ed5542011-10-24 11:43:31 +02002917 if (pi->pcfg.num_peri) {
2918 dma_cap_set(DMA_SLAVE, pd->cap_mask);
2919 dma_cap_set(DMA_CYCLIC, pd->cap_mask);
Tushar Behera5557a412012-08-29 10:16:25 +05302920 dma_cap_set(DMA_PRIVATE, pd->cap_mask);
Thomas Abraham93ed5542011-10-24 11:43:31 +02002921 }
2922 }
Jassi Brarb3040e42010-05-23 20:28:19 -07002923
2924 pd->device_alloc_chan_resources = pl330_alloc_chan_resources;
2925 pd->device_free_chan_resources = pl330_free_chan_resources;
2926 pd->device_prep_dma_memcpy = pl330_prep_dma_memcpy;
Boojin Kim42bc9cf2011-09-02 09:44:33 +09002927 pd->device_prep_dma_cyclic = pl330_prep_dma_cyclic;
Jassi Brarb3040e42010-05-23 20:28:19 -07002928 pd->device_tx_status = pl330_tx_status;
2929 pd->device_prep_slave_sg = pl330_prep_slave_sg;
2930 pd->device_control = pl330_control;
2931 pd->device_issue_pending = pl330_issue_pending;
Lars-Peter Clausenca38ff12013-07-15 17:53:08 +02002932 pd->device_slave_caps = pl330_dma_device_slave_caps;
Jassi Brarb3040e42010-05-23 20:28:19 -07002933
2934 ret = dma_async_device_register(pd);
2935 if (ret) {
2936 dev_err(&adev->dev, "unable to register DMAC\n");
Padmavathi Venna0b94c572013-03-05 14:55:31 +05302937 goto probe_err3;
2938 }
2939
2940 if (adev->dev.of_node) {
2941 ret = of_dma_controller_register(adev->dev.of_node,
2942 of_dma_pl330_xlate, pdmac);
2943 if (ret) {
2944 dev_err(&adev->dev,
2945 "unable to register DMA to the generic DT DMA helpers\n");
2946 }
Jassi Brarb3040e42010-05-23 20:28:19 -07002947 }
Lars-Peter Clausenb714b842013-11-25 16:07:46 +01002948
2949 adev->dev.dma_parms = &pdmac->dma_parms;
2950
Vinod Kouldbaf6d82013-09-02 21:54:48 +05302951 /*
2952 * This is the limit for transfers with a buswidth of 1, larger
2953 * buswidths will have larger limits.
2954 */
2955 ret = dma_set_max_seg_size(&adev->dev, 1900800);
2956 if (ret)
2957 dev_err(&adev->dev, "unable to set the seg size\n");
2958
Jassi Brarb3040e42010-05-23 20:28:19 -07002959
Jassi Brarb3040e42010-05-23 20:28:19 -07002960 dev_info(&adev->dev,
2961 "Loaded driver for PL330 DMAC-%d\n", adev->periphid);
2962 dev_info(&adev->dev,
2963 "\tDBUFF-%ux%ubytes Num_Chans-%u Num_Peri-%u Num_Events-%u\n",
2964 pi->pcfg.data_buf_dep,
2965 pi->pcfg.data_bus_width / 8, pi->pcfg.num_chan,
2966 pi->pcfg.num_peri, pi->pcfg.num_events);
2967
2968 return 0;
Padmavathi Venna0b94c572013-03-05 14:55:31 +05302969probe_err3:
Padmavathi Venna0b94c572013-03-05 14:55:31 +05302970 /* Idle the DMAC */
2971 list_for_each_entry_safe(pch, _p, &pdmac->ddma.channels,
2972 chan.device_node) {
2973
2974 /* Remove the channel */
2975 list_del(&pch->chan.device_node);
2976
2977 /* Flush the channel */
2978 pl330_control(&pch->chan, DMA_TERMINATE_ALL, 0);
2979 pl330_free_chan_resources(&pch->chan);
2980 }
Jassi Brarb3040e42010-05-23 20:28:19 -07002981probe_err2:
Sachin Kamate4d43c12012-11-15 06:27:50 +00002982 pl330_del(pi);
Jassi Brarb3040e42010-05-23 20:28:19 -07002983
2984 return ret;
2985}
2986
Greg Kroah-Hartman4bf27b82012-12-21 15:09:59 -08002987static int pl330_remove(struct amba_device *adev)
Jassi Brarb3040e42010-05-23 20:28:19 -07002988{
2989 struct dma_pl330_dmac *pdmac = amba_get_drvdata(adev);
2990 struct dma_pl330_chan *pch, *_p;
2991 struct pl330_info *pi;
Jassi Brarb3040e42010-05-23 20:28:19 -07002992
2993 if (!pdmac)
2994 return 0;
2995
Padmavathi Venna0b94c572013-03-05 14:55:31 +05302996 if (adev->dev.of_node)
2997 of_dma_controller_free(adev->dev.of_node);
Padmavathi Venna421da892013-02-14 09:10:07 +05302998
Padmavathi Venna0b94c572013-03-05 14:55:31 +05302999 dma_async_device_unregister(&pdmac->ddma);
Jassi Brarb3040e42010-05-23 20:28:19 -07003000
3001 /* Idle the DMAC */
3002 list_for_each_entry_safe(pch, _p, &pdmac->ddma.channels,
3003 chan.device_node) {
3004
3005 /* Remove the channel */
3006 list_del(&pch->chan.device_node);
3007
3008 /* Flush the channel */
3009 pl330_control(&pch->chan, DMA_TERMINATE_ALL, 0);
3010 pl330_free_chan_resources(&pch->chan);
3011 }
3012
3013 pi = &pdmac->pif;
3014
3015 pl330_del(pi);
3016
Jassi Brarb3040e42010-05-23 20:28:19 -07003017 return 0;
3018}
3019
3020static struct amba_id pl330_ids[] = {
3021 {
3022 .id = 0x00041330,
3023 .mask = 0x000fffff,
3024 },
3025 { 0, 0 },
3026};
3027
Dave Martine8fa5162011-10-05 15:15:20 +01003028MODULE_DEVICE_TABLE(amba, pl330_ids);
3029
Jassi Brarb3040e42010-05-23 20:28:19 -07003030static struct amba_driver pl330_driver = {
3031 .drv = {
3032 .owner = THIS_MODULE,
3033 .name = "dma-pl330",
Jassi Brarb3040e42010-05-23 20:28:19 -07003034 },
3035 .id_table = pl330_ids,
3036 .probe = pl330_probe,
3037 .remove = pl330_remove,
3038};
3039
viresh kumar9e5ed092012-03-15 10:40:38 +01003040module_amba_driver(pl330_driver);
Jassi Brarb3040e42010-05-23 20:28:19 -07003041
3042MODULE_AUTHOR("Jaswinder Singh <jassi.brar@samsung.com>");
3043MODULE_DESCRIPTION("API Driver for PL330 DMAC");
3044MODULE_LICENSE("GPL");