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Jean-Christophe PLAGNIOL-VILLARD5b6089c2012-04-09 19:26:33 +08001/*
2 * at91sam9260.dtsi - Device Tree Include file for AT91SAM9260 family SoC
3 *
4 * Copyright (C) 2011 Atmel,
5 * 2011 Nicolas Ferre <nicolas.ferre@atmel.com>,
6 * 2011 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
7 *
8 * Licensed under GPLv2 or later.
9 */
10
11/include/ "skeleton.dtsi"
12
13/ {
14 model = "Atmel AT91SAM9260 family SoC";
15 compatible = "atmel,at91sam9260";
16 interrupt-parent = <&aic>;
17
18 aliases {
19 serial0 = &dbgu;
20 serial1 = &usart0;
21 serial2 = &usart1;
22 serial3 = &usart2;
23 serial4 = &usart3;
Jean-Christophe PLAGNIOL-VILLARD9e3129e2012-11-19 06:40:01 +080024 serial5 = &uart0;
25 serial6 = &uart1;
Jean-Christophe PLAGNIOL-VILLARD5b6089c2012-04-09 19:26:33 +080026 gpio0 = &pioA;
27 gpio1 = &pioB;
28 gpio2 = &pioC;
29 tcb0 = &tcb0;
30 tcb1 = &tcb1;
Ludovic Desroches05dcd362012-09-12 08:42:16 +020031 i2c0 = &i2c0;
Bo Shen099343c2012-11-07 11:41:41 +080032 ssc0 = &ssc0;
Jean-Christophe PLAGNIOL-VILLARD5b6089c2012-04-09 19:26:33 +080033 };
34 cpus {
35 cpu@0 {
36 compatible = "arm,arm926ejs";
37 };
38 };
39
40 memory {
41 reg = <0x20000000 0x04000000>;
42 };
43
44 ahb {
45 compatible = "simple-bus";
46 #address-cells = <1>;
47 #size-cells = <1>;
48 ranges;
49
50 apb {
51 compatible = "simple-bus";
52 #address-cells = <1>;
53 #size-cells = <1>;
54 ranges;
55
56 aic: interrupt-controller@fffff000 {
Ludovic Desrochesf8a073e2012-06-20 16:13:30 +020057 #interrupt-cells = <3>;
Jean-Christophe PLAGNIOL-VILLARD5b6089c2012-04-09 19:26:33 +080058 compatible = "atmel,at91rm9200-aic";
59 interrupt-controller;
60 reg = <0xfffff000 0x200>;
Jean-Christophe PLAGNIOL-VILLARDc6573942012-04-09 19:36:36 +080061 atmel,external-irqs = <29 30 31>;
Jean-Christophe PLAGNIOL-VILLARD5b6089c2012-04-09 19:26:33 +080062 };
63
64 ramc0: ramc@ffffea00 {
65 compatible = "atmel,at91sam9260-sdramc";
66 reg = <0xffffea00 0x200>;
67 };
68
69 pmc: pmc@fffffc00 {
70 compatible = "atmel,at91rm9200-pmc";
71 reg = <0xfffffc00 0x100>;
72 };
73
74 rstc@fffffd00 {
75 compatible = "atmel,at91sam9260-rstc";
76 reg = <0xfffffd00 0x10>;
77 };
78
79 shdwc@fffffd10 {
80 compatible = "atmel,at91sam9260-shdwc";
81 reg = <0xfffffd10 0x10>;
82 };
83
84 pit: timer@fffffd30 {
85 compatible = "atmel,at91sam9260-pit";
86 reg = <0xfffffd30 0xf>;
Ludovic Desrochesf8a073e2012-06-20 16:13:30 +020087 interrupts = <1 4 7>;
Jean-Christophe PLAGNIOL-VILLARD5b6089c2012-04-09 19:26:33 +080088 };
89
90 tcb0: timer@fffa0000 {
91 compatible = "atmel,at91rm9200-tcb";
92 reg = <0xfffa0000 0x100>;
Ludovic Desrochesf8a073e2012-06-20 16:13:30 +020093 interrupts = <17 4 0 18 4 0 19 4 0>;
Jean-Christophe PLAGNIOL-VILLARD5b6089c2012-04-09 19:26:33 +080094 };
95
96 tcb1: timer@fffdc000 {
97 compatible = "atmel,at91rm9200-tcb";
98 reg = <0xfffdc000 0x100>;
Ludovic Desrochesf8a073e2012-06-20 16:13:30 +020099 interrupts = <26 4 0 27 4 0 28 4 0>;
Jean-Christophe PLAGNIOL-VILLARD5b6089c2012-04-09 19:26:33 +0800100 };
101
Jean-Christophe PLAGNIOL-VILLARDe4541ff2012-07-04 17:20:46 +0800102 pinctrl@fffff400 {
103 #address-cells = <1>;
104 #size-cells = <1>;
105 compatible = "atmel,at91rm9200-pinctrl", "simple-bus";
106 ranges = <0xfffff400 0xfffff400 0x600>;
Jean-Christophe PLAGNIOL-VILLARD5b6089c2012-04-09 19:26:33 +0800107
Jean-Christophe PLAGNIOL-VILLARD5314ec82012-07-05 16:56:09 +0800108 atmel,mux-mask = <
109 /* A B */
110 0xffffffff 0xffc00c3b /* pioA */
111 0xffffffff 0x7fff3ccf /* pioB */
112 0xffffffff 0x007fffff /* pioC */
113 >;
114
115 /* shared pinctrl settings */
Jean-Christophe PLAGNIOL-VILLARDec6754a2012-07-05 16:56:09 +0800116 dbgu {
117 pinctrl_dbgu: dbgu-0 {
118 atmel,pins =
119 <1 14 0x1 0x0 /* PB14 periph A */
120 1 15 0x1 0x1>; /* PB15 periph with pullup */
121 };
122 };
123
Jean-Christophe PLAGNIOL-VILLARD9e3129e2012-11-19 06:40:01 +0800124 usart0 {
125 pinctrl_usart0: usart0-0 {
Jean-Christophe PLAGNIOL-VILLARDec6754a2012-07-05 16:56:09 +0800126 atmel,pins =
127 <1 4 0x1 0x0 /* PB4 periph A */
128 1 5 0x1 0x0>; /* PB5 periph A */
129 };
130
Jean-Christophe PLAGNIOL-VILLARDc58c0c52012-11-19 07:30:01 +0800131 pinctrl_usart0_rts: usart0_rts-0 {
Jean-Christophe PLAGNIOL-VILLARDec6754a2012-07-05 16:56:09 +0800132 atmel,pins =
Jean-Christophe PLAGNIOL-VILLARDc58c0c52012-11-19 07:30:01 +0800133 <1 26 0x1 0x0>; /* PB26 periph A */
134 };
135
136 pinctrl_usart0_cts: usart0_cts-0 {
137 atmel,pins =
138 <1 27 0x1 0x0>; /* PB27 periph A */
Jean-Christophe PLAGNIOL-VILLARDec6754a2012-07-05 16:56:09 +0800139 };
140
Jean-Christophe PLAGNIOL-VILLARD9e3129e2012-11-19 06:40:01 +0800141 pinctrl_usart0_dtr_dsr: usart0_dtr_dsr-0 {
Jean-Christophe PLAGNIOL-VILLARDec6754a2012-07-05 16:56:09 +0800142 atmel,pins =
143 <1 24 0x1 0x0 /* PB24 periph A */
144 1 22 0x1 0x0>; /* PB22 periph A */
145 };
146
Jean-Christophe PLAGNIOL-VILLARD9e3129e2012-11-19 06:40:01 +0800147 pinctrl_usart0_dcd: usart0_dcd-0 {
Jean-Christophe PLAGNIOL-VILLARDec6754a2012-07-05 16:56:09 +0800148 atmel,pins =
149 <1 23 0x1 0x0>; /* PB23 periph A */
150 };
151
Jean-Christophe PLAGNIOL-VILLARD9e3129e2012-11-19 06:40:01 +0800152 pinctrl_usart0_ri: usart0_ri-0 {
Jean-Christophe PLAGNIOL-VILLARDec6754a2012-07-05 16:56:09 +0800153 atmel,pins =
154 <1 25 0x1 0x0>; /* PB25 periph A */
155 };
156 };
157
Jean-Christophe PLAGNIOL-VILLARD9e3129e2012-11-19 06:40:01 +0800158 usart1 {
159 pinctrl_usart1: usart1-0 {
Jean-Christophe PLAGNIOL-VILLARDec6754a2012-07-05 16:56:09 +0800160 atmel,pins =
161 <2 6 0x1 0x1 /* PB6 periph A with pullup */
162 2 7 0x1 0x0>; /* PB7 periph A */
163 };
164
Jean-Christophe PLAGNIOL-VILLARDc58c0c52012-11-19 07:30:01 +0800165 pinctrl_usart1_rts: usart1_rts-0 {
Jean-Christophe PLAGNIOL-VILLARDec6754a2012-07-05 16:56:09 +0800166 atmel,pins =
Jean-Christophe PLAGNIOL-VILLARDc58c0c52012-11-19 07:30:01 +0800167 <1 28 0x1 0x0>; /* PB28 periph A */
168 };
169
170 pinctrl_usart1_cts: usart1_cts-0 {
171 atmel,pins =
172 <1 29 0x1 0x0>; /* PB29 periph A */
Jean-Christophe PLAGNIOL-VILLARDec6754a2012-07-05 16:56:09 +0800173 };
174 };
175
Jean-Christophe PLAGNIOL-VILLARD9e3129e2012-11-19 06:40:01 +0800176 usart2 {
177 pinctrl_usart2: usart2-0 {
Jean-Christophe PLAGNIOL-VILLARDec6754a2012-07-05 16:56:09 +0800178 atmel,pins =
179 <1 8 0x1 0x1 /* PB8 periph A with pullup */
180 1 9 0x1 0x0>; /* PB9 periph A */
181 };
182
Jean-Christophe PLAGNIOL-VILLARDc58c0c52012-11-19 07:30:01 +0800183 pinctrl_usart2_rts: usart2_rts-0 {
Jean-Christophe PLAGNIOL-VILLARDec6754a2012-07-05 16:56:09 +0800184 atmel,pins =
Jean-Christophe PLAGNIOL-VILLARDc58c0c52012-11-19 07:30:01 +0800185 <0 4 0x1 0x0>; /* PA4 periph A */
186 };
187
188 pinctrl_usart2_cts: usart2_cts-0 {
189 atmel,pins =
190 <0 5 0x1 0x0>; /* PA5 periph A */
Jean-Christophe PLAGNIOL-VILLARDec6754a2012-07-05 16:56:09 +0800191 };
192 };
193
Jean-Christophe PLAGNIOL-VILLARD9e3129e2012-11-19 06:40:01 +0800194 usart3 {
195 pinctrl_usart3: usart3-0 {
Jean-Christophe PLAGNIOL-VILLARDec6754a2012-07-05 16:56:09 +0800196 atmel,pins =
197 <2 10 0x1 0x1 /* PB10 periph A with pullup */
198 2 11 0x1 0x0>; /* PB11 periph A */
199 };
200
Jean-Christophe PLAGNIOL-VILLARDc58c0c52012-11-19 07:30:01 +0800201 pinctrl_usart3_rts: usart3_rts-0 {
Jean-Christophe PLAGNIOL-VILLARDec6754a2012-07-05 16:56:09 +0800202 atmel,pins =
Jean-Christophe PLAGNIOL-VILLARDc58c0c52012-11-19 07:30:01 +0800203 <3 8 0x2 0x0>; /* PB8 periph B */
204 };
205
206 pinctrl_usart3_cts: usart3_cts-0 {
207 atmel,pins =
208 <3 10 0x2 0x0>; /* PB10 periph B */
Jean-Christophe PLAGNIOL-VILLARDec6754a2012-07-05 16:56:09 +0800209 };
210 };
211
Jean-Christophe PLAGNIOL-VILLARD9e3129e2012-11-19 06:40:01 +0800212 uart0 {
213 pinctrl_uart0: uart0-0 {
Jean-Christophe PLAGNIOL-VILLARDec6754a2012-07-05 16:56:09 +0800214 atmel,pins =
215 <0 31 0x2 0x1 /* PA31 periph B with pullup */
216 0 30 0x2 0x0>; /* PA30 periph B */
217 };
218 };
219
Jean-Christophe PLAGNIOL-VILLARD9e3129e2012-11-19 06:40:01 +0800220 uart1 {
221 pinctrl_uart1: uart1-0 {
Jean-Christophe PLAGNIOL-VILLARDec6754a2012-07-05 16:56:09 +0800222 atmel,pins =
223 <2 12 0x1 0x1 /* PB12 periph A with pullup */
224 2 13 0x1 0x0>; /* PB13 periph A */
225 };
226 };
Jean-Christophe PLAGNIOL-VILLARD5314ec82012-07-05 16:56:09 +0800227
Jean-Christophe PLAGNIOL-VILLARD7a38d452012-07-12 23:36:52 +0800228 nand {
229 pinctrl_nand: nand-0 {
230 atmel,pins =
231 <2 13 0x0 0x1 /* PC13 gpio RDY pin pull_up */
232 2 14 0x0 0x1>; /* PC14 gpio enable pin pull_up */
233 };
234 };
235
Jean-Christophe PLAGNIOL-VILLARDd9b4fe82012-10-23 10:19:11 +0800236 macb {
237 pinctrl_macb_rmii: macb_rmii-0 {
238 atmel,pins =
239 <0 12 0x1 0x0 /* PA12 periph A */
240 0 13 0x1 0x0 /* PA13 periph A */
241 0 14 0x1 0x0 /* PA14 periph A */
242 0 15 0x1 0x0 /* PA15 periph A */
243 0 16 0x1 0x0 /* PA16 periph A */
244 0 17 0x1 0x0 /* PA17 periph A */
245 0 18 0x1 0x0 /* PA18 periph A */
246 0 19 0x1 0x0 /* PA19 periph A */
247 0 20 0x1 0x0 /* PA20 periph A */
248 0 21 0x1 0x0>; /* PA21 periph A */
249 };
250
251 pinctrl_macb_rmii_mii: macb_rmii_mii-0 {
252 atmel,pins =
253 <0 22 0x2 0x0 /* PA22 periph B */
254 0 23 0x2 0x0 /* PA23 periph B */
255 0 24 0x2 0x0 /* PA24 periph B */
256 0 25 0x2 0x0 /* PA25 periph B */
257 0 26 0x2 0x0 /* PA26 periph B */
258 0 27 0x2 0x0 /* PA27 periph B */
259 0 28 0x2 0x0 /* PA28 periph B */
260 0 29 0x2 0x0>; /* PA29 periph B */
261 };
262
263 pinctrl_macb_rmii_mii_alt: macb_rmii_mii-1 {
264 atmel,pins =
265 <0 10 0x2 0x0 /* PA10 periph B */
266 0 11 0x2 0x0 /* PA11 periph B */
267 0 24 0x2 0x0 /* PA24 periph B */
268 0 25 0x2 0x0 /* PA25 periph B */
269 0 26 0x2 0x0 /* PA26 periph B */
270 0 27 0x2 0x0 /* PA27 periph B */
271 0 28 0x2 0x0 /* PA28 periph B */
272 0 29 0x2 0x0>; /* PA29 periph B */
273 };
274 };
275
Jean-Christophe PLAGNIOL-VILLARDd4fe9ac2012-11-16 08:24:17 +0800276 mmc0 {
277 pinctrl_mmc0_clk: mmc0_clk-0 {
278 atmel,pins =
279 <0 8 0x1 0x0>; /* PA8 periph A */
280 };
281
282 pinctrl_mmc0_slot0_cmd_dat0: mmc0_slot0_cmd_dat0-0 {
283 atmel,pins =
284 <0 7 0x1 0x1 /* PA7 periph A with pullup */
285 0 6 0x1 0x1>; /* PA6 periph A with pullup */
286 };
287
288 pinctrl_mmc0_slot0_dat1_3: mmc0_slot0_dat1_3-0 {
289 atmel,pins =
290 <0 9 0x1 0x1 /* PA9 periph A with pullup */
291 0 10 0x1 0x1 /* PA10 periph A with pullup */
292 0 11 0x1 0x1>; /* PA11 periph A with pullup */
293 };
294
295 pinctrl_mmc0_slot1_cmd_dat0: mmc0_slot1_cmd_dat0-0 {
296 atmel,pins =
297 <0 1 0x2 0x1 /* PA1 periph B with pullup */
298 0 0 0x2 0x1>; /* PA0 periph B with pullup */
299 };
300
301 pinctrl_mmc0_slot1_dat1_3: mmc0_slot1_dat1_3-0 {
302 atmel,pins =
303 <0 5 0x2 0x1 /* PA5 periph B with pullup */
304 0 4 0x2 0x1 /* PA4 periph B with pullup */
305 0 3 0x2 0x1>; /* PA3 periph B with pullup */
306 };
307 };
308
Bo Shen544ae6b2013-01-11 15:08:30 +0100309 ssc0 {
310 pinctrl_ssc0_tx: ssc0_tx-0 {
311 atmel,pins =
312 <1 16 0x1 0x0 /* PB16 periph A */
313 1 17 0x1 0x0 /* PB17 periph A */
314 1 18 0x1 0x0>; /* PB18 periph A */
315 };
316
317 pinctrl_ssc0_rx: ssc0_rx-0 {
318 atmel,pins =
319 <1 19 0x1 0x0 /* PB19 periph A */
320 1 20 0x1 0x0 /* PB20 periph A */
321 1 21 0x1 0x0>; /* PB21 periph A */
322 };
323 };
324
Jean-Christophe PLAGNIOL-VILLARDe4541ff2012-07-04 17:20:46 +0800325 pioA: gpio@fffff400 {
326 compatible = "atmel,at91rm9200-gpio";
327 reg = <0xfffff400 0x200>;
328 interrupts = <2 4 1>;
329 #gpio-cells = <2>;
330 gpio-controller;
331 interrupt-controller;
332 #interrupt-cells = <2>;
333 };
Jean-Christophe PLAGNIOL-VILLARD5b6089c2012-04-09 19:26:33 +0800334
Jean-Christophe PLAGNIOL-VILLARDe4541ff2012-07-04 17:20:46 +0800335 pioB: gpio@fffff600 {
336 compatible = "atmel,at91rm9200-gpio";
337 reg = <0xfffff600 0x200>;
338 interrupts = <3 4 1>;
339 #gpio-cells = <2>;
340 gpio-controller;
341 interrupt-controller;
342 #interrupt-cells = <2>;
343 };
344
345 pioC: gpio@fffff800 {
346 compatible = "atmel,at91rm9200-gpio";
347 reg = <0xfffff800 0x200>;
348 interrupts = <4 4 1>;
349 #gpio-cells = <2>;
350 gpio-controller;
351 interrupt-controller;
352 #interrupt-cells = <2>;
353 };
Jean-Christophe PLAGNIOL-VILLARD5b6089c2012-04-09 19:26:33 +0800354 };
355
356 dbgu: serial@fffff200 {
357 compatible = "atmel,at91sam9260-usart";
358 reg = <0xfffff200 0x200>;
Ludovic Desrochesf8a073e2012-06-20 16:13:30 +0200359 interrupts = <1 4 7>;
Jean-Christophe PLAGNIOL-VILLARDec6754a2012-07-05 16:56:09 +0800360 pinctrl-names = "default";
361 pinctrl-0 = <&pinctrl_dbgu>;
Jean-Christophe PLAGNIOL-VILLARD5b6089c2012-04-09 19:26:33 +0800362 status = "disabled";
363 };
364
365 usart0: serial@fffb0000 {
366 compatible = "atmel,at91sam9260-usart";
367 reg = <0xfffb0000 0x200>;
Ludovic Desrochesf8a073e2012-06-20 16:13:30 +0200368 interrupts = <6 4 5>;
Jean-Christophe PLAGNIOL-VILLARD5b6089c2012-04-09 19:26:33 +0800369 atmel,use-dma-rx;
370 atmel,use-dma-tx;
Jean-Christophe PLAGNIOL-VILLARDec6754a2012-07-05 16:56:09 +0800371 pinctrl-names = "default";
Jean-Christophe PLAGNIOL-VILLARD9e3129e2012-11-19 06:40:01 +0800372 pinctrl-0 = <&pinctrl_usart0>;
Jean-Christophe PLAGNIOL-VILLARD5b6089c2012-04-09 19:26:33 +0800373 status = "disabled";
374 };
375
376 usart1: serial@fffb4000 {
377 compatible = "atmel,at91sam9260-usart";
378 reg = <0xfffb4000 0x200>;
Ludovic Desrochesf8a073e2012-06-20 16:13:30 +0200379 interrupts = <7 4 5>;
Jean-Christophe PLAGNIOL-VILLARD5b6089c2012-04-09 19:26:33 +0800380 atmel,use-dma-rx;
381 atmel,use-dma-tx;
Jean-Christophe PLAGNIOL-VILLARDec6754a2012-07-05 16:56:09 +0800382 pinctrl-names = "default";
Jean-Christophe PLAGNIOL-VILLARD9e3129e2012-11-19 06:40:01 +0800383 pinctrl-0 = <&pinctrl_usart1>;
Jean-Christophe PLAGNIOL-VILLARD5b6089c2012-04-09 19:26:33 +0800384 status = "disabled";
385 };
386
387 usart2: serial@fffb8000 {
388 compatible = "atmel,at91sam9260-usart";
389 reg = <0xfffb8000 0x200>;
Ludovic Desrochesf8a073e2012-06-20 16:13:30 +0200390 interrupts = <8 4 5>;
Jean-Christophe PLAGNIOL-VILLARD5b6089c2012-04-09 19:26:33 +0800391 atmel,use-dma-rx;
392 atmel,use-dma-tx;
Jean-Christophe PLAGNIOL-VILLARDec6754a2012-07-05 16:56:09 +0800393 pinctrl-names = "default";
Jean-Christophe PLAGNIOL-VILLARD9e3129e2012-11-19 06:40:01 +0800394 pinctrl-0 = <&pinctrl_usart2>;
Jean-Christophe PLAGNIOL-VILLARD5b6089c2012-04-09 19:26:33 +0800395 status = "disabled";
396 };
397
398 usart3: serial@fffd0000 {
399 compatible = "atmel,at91sam9260-usart";
400 reg = <0xfffd0000 0x200>;
Ludovic Desrochesf8a073e2012-06-20 16:13:30 +0200401 interrupts = <23 4 5>;
Jean-Christophe PLAGNIOL-VILLARD5b6089c2012-04-09 19:26:33 +0800402 atmel,use-dma-rx;
403 atmel,use-dma-tx;
Jean-Christophe PLAGNIOL-VILLARDec6754a2012-07-05 16:56:09 +0800404 pinctrl-names = "default";
Jean-Christophe PLAGNIOL-VILLARD9e3129e2012-11-19 06:40:01 +0800405 pinctrl-0 = <&pinctrl_usart3>;
Jean-Christophe PLAGNIOL-VILLARD5b6089c2012-04-09 19:26:33 +0800406 status = "disabled";
407 };
408
Jean-Christophe PLAGNIOL-VILLARD9e3129e2012-11-19 06:40:01 +0800409 uart0: serial@fffd4000 {
Jean-Christophe PLAGNIOL-VILLARD5b6089c2012-04-09 19:26:33 +0800410 compatible = "atmel,at91sam9260-usart";
411 reg = <0xfffd4000 0x200>;
Ludovic Desrochesf8a073e2012-06-20 16:13:30 +0200412 interrupts = <24 4 5>;
Jean-Christophe PLAGNIOL-VILLARD5b6089c2012-04-09 19:26:33 +0800413 atmel,use-dma-rx;
414 atmel,use-dma-tx;
Jean-Christophe PLAGNIOL-VILLARDec6754a2012-07-05 16:56:09 +0800415 pinctrl-names = "default";
Jean-Christophe PLAGNIOL-VILLARD9e3129e2012-11-19 06:40:01 +0800416 pinctrl-0 = <&pinctrl_uart0>;
Jean-Christophe PLAGNIOL-VILLARD5b6089c2012-04-09 19:26:33 +0800417 status = "disabled";
418 };
419
Jean-Christophe PLAGNIOL-VILLARD9e3129e2012-11-19 06:40:01 +0800420 uart1: serial@fffd8000 {
Jean-Christophe PLAGNIOL-VILLARD5b6089c2012-04-09 19:26:33 +0800421 compatible = "atmel,at91sam9260-usart";
422 reg = <0xfffd8000 0x200>;
Ludovic Desrochesf8a073e2012-06-20 16:13:30 +0200423 interrupts = <25 4 5>;
Jean-Christophe PLAGNIOL-VILLARD5b6089c2012-04-09 19:26:33 +0800424 atmel,use-dma-rx;
425 atmel,use-dma-tx;
Jean-Christophe PLAGNIOL-VILLARDec6754a2012-07-05 16:56:09 +0800426 pinctrl-names = "default";
Jean-Christophe PLAGNIOL-VILLARD9e3129e2012-11-19 06:40:01 +0800427 pinctrl-0 = <&pinctrl_uart1>;
Jean-Christophe PLAGNIOL-VILLARD5b6089c2012-04-09 19:26:33 +0800428 status = "disabled";
429 };
430
431 macb0: ethernet@fffc4000 {
432 compatible = "cdns,at32ap7000-macb", "cdns,macb";
433 reg = <0xfffc4000 0x100>;
Ludovic Desrochesf8a073e2012-06-20 16:13:30 +0200434 interrupts = <21 4 3>;
Jean-Christophe PLAGNIOL-VILLARDd9b4fe82012-10-23 10:19:11 +0800435 pinctrl-names = "default";
436 pinctrl-0 = <&pinctrl_macb_rmii>;
Jean-Christophe PLAGNIOL-VILLARD5b6089c2012-04-09 19:26:33 +0800437 status = "disabled";
438 };
439
440 usb1: gadget@fffa4000 {
441 compatible = "atmel,at91rm9200-udc";
442 reg = <0xfffa4000 0x4000>;
Ludovic Desrochesf8a073e2012-06-20 16:13:30 +0200443 interrupts = <10 4 2>;
Jean-Christophe PLAGNIOL-VILLARD5b6089c2012-04-09 19:26:33 +0800444 status = "disabled";
445 };
Nicolas Ferre73d68d92012-05-16 17:37:06 +0200446
Ludovic Desroches05dcd362012-09-12 08:42:16 +0200447 i2c0: i2c@fffac000 {
448 compatible = "atmel,at91sam9260-i2c";
449 reg = <0xfffac000 0x100>;
450 interrupts = <11 4 6>;
451 #address-cells = <1>;
452 #size-cells = <0>;
453 status = "disabled";
454 };
455
Ludovic Desroches98731372012-11-19 12:23:36 +0100456 mmc0: mmc@fffa8000 {
457 compatible = "atmel,hsmci";
458 reg = <0xfffa8000 0x600>;
459 interrupts = <9 4 0>;
460 #address-cells = <1>;
461 #size-cells = <0>;
462 status = "disabled";
463 };
464
Bo Shen099343c2012-11-07 11:41:41 +0800465 ssc0: ssc@fffbc000 {
466 compatible = "atmel,at91rm9200-ssc";
467 reg = <0xfffbc000 0x4000>;
468 interrupts = <14 4 5>;
Bo Shen544ae6b2013-01-11 15:08:30 +0100469 pinctrl-names = "default";
470 pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>;
Linus Torvalds046e7d62012-12-13 11:51:23 -0800471 status = "disabled";
Bo Shen099343c2012-11-07 11:41:41 +0800472 };
473
Nicolas Ferre73d68d92012-05-16 17:37:06 +0200474 adc0: adc@fffe0000 {
475 compatible = "atmel,at91sam9260-adc";
476 reg = <0xfffe0000 0x100>;
Ludovic Desrochesf8a073e2012-06-20 16:13:30 +0200477 interrupts = <5 4 0>;
Nicolas Ferre73d68d92012-05-16 17:37:06 +0200478 atmel,adc-use-external-triggers;
479 atmel,adc-channels-used = <0xf>;
480 atmel,adc-vref = <3300>;
481 atmel,adc-num-channels = <4>;
482 atmel,adc-startup-time = <15>;
483 atmel,adc-channel-base = <0x30>;
484 atmel,adc-drdy-mask = <0x10000>;
485 atmel,adc-status-register = <0x1c>;
486 atmel,adc-trigger-register = <0x04>;
487
488 trigger@0 {
489 trigger-name = "timer-counter-0";
490 trigger-value = <0x1>;
491 };
492 trigger@1 {
493 trigger-name = "timer-counter-1";
494 trigger-value = <0x3>;
495 };
496
497 trigger@2 {
498 trigger-name = "timer-counter-2";
499 trigger-value = <0x5>;
500 };
501
502 trigger@3 {
503 trigger-name = "external";
504 trigger-value = <0x13>;
505 trigger-external;
506 };
507 };
Fabio Porcedda7492e7c2012-11-12 09:37:26 +0100508
509 watchdog@fffffd40 {
510 compatible = "atmel,at91sam9260-wdt";
511 reg = <0xfffffd40 0x10>;
512 status = "disabled";
513 };
Jean-Christophe PLAGNIOL-VILLARD5b6089c2012-04-09 19:26:33 +0800514 };
515
516 nand0: nand@40000000 {
517 compatible = "atmel,at91rm9200-nand";
518 #address-cells = <1>;
519 #size-cells = <1>;
520 reg = <0x40000000 0x10000000
521 0xffffe800 0x200
522 >;
523 atmel,nand-addr-offset = <21>;
524 atmel,nand-cmd-offset = <22>;
Jean-Christophe PLAGNIOL-VILLARD7a38d452012-07-12 23:36:52 +0800525 pinctrl-names = "default";
526 pinctrl-0 = <&pinctrl_nand>;
Jean-Christophe PLAGNIOL-VILLARD5b6089c2012-04-09 19:26:33 +0800527 gpios = <&pioC 13 0
528 &pioC 14 0
529 0
530 >;
531 status = "disabled";
532 };
533
534 usb0: ohci@00500000 {
535 compatible = "atmel,at91rm9200-ohci", "usb-ohci";
536 reg = <0x00500000 0x100000>;
Ludovic Desrochesf8a073e2012-06-20 16:13:30 +0200537 interrupts = <20 4 2>;
Jean-Christophe PLAGNIOL-VILLARD5b6089c2012-04-09 19:26:33 +0800538 status = "disabled";
539 };
540 };
541
542 i2c@0 {
543 compatible = "i2c-gpio";
544 gpios = <&pioA 23 0 /* sda */
545 &pioA 24 0 /* scl */
546 >;
547 i2c-gpio,sda-open-drain;
548 i2c-gpio,scl-open-drain;
549 i2c-gpio,delay-us = <2>; /* ~100 kHz */
550 #address-cells = <1>;
551 #size-cells = <0>;
552 status = "disabled";
553 };
554};