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Philipp Zabel1c44f5f2008-02-04 22:28:22 -08001/*
Eric Miao38f539a2009-01-20 12:09:06 +08002 * linux/arch/arm/plat-pxa/gpio.c
Philipp Zabel1c44f5f2008-02-04 22:28:22 -08003 *
4 * Generic PXA GPIO handling
5 *
6 * Author: Nicolas Pitre
7 * Created: Jun 15, 2001
8 * Copyright: MontaVista Software Inc.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13 */
Russell King2f8163b2011-07-26 10:53:52 +010014#include <linux/gpio.h>
Philipp Zabel1c44f5f2008-02-04 22:28:22 -080015#include <linux/init.h>
eric miaoe3630db2008-03-04 11:42:26 +080016#include <linux/irq.h>
Russell Kingfced80c2008-09-06 12:10:45 +010017#include <linux/io.h>
Rafael J. Wysocki2eaa03b2011-04-22 22:03:11 +020018#include <linux/syscore_ops.h>
Daniel Mack4aa78262009-06-19 22:56:09 +020019#include <linux/slab.h>
Philipp Zabel1c44f5f2008-02-04 22:28:22 -080020
Linus Walleijf55be1b2011-09-28 09:11:30 +010021#include <mach/gpio-pxa.h>
Philipp Zabel1c44f5f2008-02-04 22:28:22 -080022
Eric Miao3b8e2852009-01-07 11:30:49 +080023int pxa_last_gpio;
24
Philipp Zabel1c44f5f2008-02-04 22:28:22 -080025struct pxa_gpio_chip {
26 struct gpio_chip chip;
Eric Miao0807da52009-01-07 18:01:51 +080027 void __iomem *regbase;
28 char label[10];
29
30 unsigned long irq_mask;
31 unsigned long irq_edge_rise;
32 unsigned long irq_edge_fall;
33
34#ifdef CONFIG_PM
35 unsigned long saved_gplr;
36 unsigned long saved_gpdr;
37 unsigned long saved_grer;
38 unsigned long saved_gfer;
39#endif
Philipp Zabel1c44f5f2008-02-04 22:28:22 -080040};
41
Eric Miao0807da52009-01-07 18:01:51 +080042static DEFINE_SPINLOCK(gpio_lock);
43static struct pxa_gpio_chip *pxa_gpio_chips;
44
45#define for_each_gpio_chip(i, c) \
46 for (i = 0, c = &pxa_gpio_chips[0]; i <= pxa_last_gpio; i += 32, c++)
47
48static inline void __iomem *gpio_chip_base(struct gpio_chip *c)
49{
50 return container_of(c, struct pxa_gpio_chip, chip)->regbase;
51}
52
Linus Walleija0656852011-06-13 10:42:19 +020053static inline struct pxa_gpio_chip *gpio_to_pxachip(unsigned gpio)
Eric Miao0807da52009-01-07 18:01:51 +080054{
55 return &pxa_gpio_chips[gpio_to_bank(gpio)];
56}
57
Philipp Zabel1c44f5f2008-02-04 22:28:22 -080058static int pxa_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
59{
Eric Miao0807da52009-01-07 18:01:51 +080060 void __iomem *base = gpio_chip_base(chip);
61 uint32_t value, mask = 1 << offset;
62 unsigned long flags;
Philipp Zabel1c44f5f2008-02-04 22:28:22 -080063
Eric Miao0807da52009-01-07 18:01:51 +080064 spin_lock_irqsave(&gpio_lock, flags);
65
66 value = __raw_readl(base + GPDR_OFFSET);
Eric Miao067455a2008-11-26 18:12:04 +080067 if (__gpio_is_inverted(chip->base + offset))
68 value |= mask;
69 else
70 value &= ~mask;
Eric Miao0807da52009-01-07 18:01:51 +080071 __raw_writel(value, base + GPDR_OFFSET);
Philipp Zabel1c44f5f2008-02-04 22:28:22 -080072
Eric Miao0807da52009-01-07 18:01:51 +080073 spin_unlock_irqrestore(&gpio_lock, flags);
Philipp Zabel1c44f5f2008-02-04 22:28:22 -080074 return 0;
75}
76
77static int pxa_gpio_direction_output(struct gpio_chip *chip,
Eric Miao0807da52009-01-07 18:01:51 +080078 unsigned offset, int value)
Philipp Zabel1c44f5f2008-02-04 22:28:22 -080079{
Eric Miao0807da52009-01-07 18:01:51 +080080 void __iomem *base = gpio_chip_base(chip);
81 uint32_t tmp, mask = 1 << offset;
82 unsigned long flags;
Philipp Zabel1c44f5f2008-02-04 22:28:22 -080083
Eric Miao0807da52009-01-07 18:01:51 +080084 __raw_writel(mask, base + (value ? GPSR_OFFSET : GPCR_OFFSET));
85
86 spin_lock_irqsave(&gpio_lock, flags);
87
88 tmp = __raw_readl(base + GPDR_OFFSET);
Eric Miao067455a2008-11-26 18:12:04 +080089 if (__gpio_is_inverted(chip->base + offset))
90 tmp &= ~mask;
91 else
92 tmp |= mask;
Eric Miao0807da52009-01-07 18:01:51 +080093 __raw_writel(tmp, base + GPDR_OFFSET);
Philipp Zabel1c44f5f2008-02-04 22:28:22 -080094
Eric Miao0807da52009-01-07 18:01:51 +080095 spin_unlock_irqrestore(&gpio_lock, flags);
Philipp Zabel1c44f5f2008-02-04 22:28:22 -080096 return 0;
97}
98
Philipp Zabel1c44f5f2008-02-04 22:28:22 -080099static int pxa_gpio_get(struct gpio_chip *chip, unsigned offset)
100{
Eric Miao0807da52009-01-07 18:01:51 +0800101 return __raw_readl(gpio_chip_base(chip) + GPLR_OFFSET) & (1 << offset);
Philipp Zabel1c44f5f2008-02-04 22:28:22 -0800102}
103
Philipp Zabel1c44f5f2008-02-04 22:28:22 -0800104static void pxa_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
105{
Eric Miao0807da52009-01-07 18:01:51 +0800106 __raw_writel(1 << offset, gpio_chip_base(chip) +
107 (value ? GPSR_OFFSET : GPCR_OFFSET));
Philipp Zabel1c44f5f2008-02-04 22:28:22 -0800108}
109
Eric Miao0807da52009-01-07 18:01:51 +0800110static int __init pxa_init_gpio_chip(int gpio_end)
Eric Miaoa58fbcd2009-01-06 17:37:37 +0800111{
Eric Miao0807da52009-01-07 18:01:51 +0800112 int i, gpio, nbanks = gpio_to_bank(gpio_end) + 1;
113 struct pxa_gpio_chip *chips;
Eric Miaoa58fbcd2009-01-06 17:37:37 +0800114
Daniel Mack4aa78262009-06-19 22:56:09 +0200115 chips = kzalloc(nbanks * sizeof(struct pxa_gpio_chip), GFP_KERNEL);
Eric Miao0807da52009-01-07 18:01:51 +0800116 if (chips == NULL) {
117 pr_err("%s: failed to allocate GPIO chips\n", __func__);
118 return -ENOMEM;
Eric Miaoa58fbcd2009-01-06 17:37:37 +0800119 }
Eric Miao0807da52009-01-07 18:01:51 +0800120
121 for (i = 0, gpio = 0; i < nbanks; i++, gpio += 32) {
122 struct gpio_chip *c = &chips[i].chip;
123
124 sprintf(chips[i].label, "gpio-%d", i);
Arnd Bergmann97b09da2011-10-01 22:03:45 +0200125 chips[i].regbase = GPIO_BANK(i);
Eric Miao0807da52009-01-07 18:01:51 +0800126
127 c->base = gpio;
128 c->label = chips[i].label;
129
130 c->direction_input = pxa_gpio_direction_input;
131 c->direction_output = pxa_gpio_direction_output;
132 c->get = pxa_gpio_get;
133 c->set = pxa_gpio_set;
134
135 /* number of GPIOs on last bank may be less than 32 */
136 c->ngpio = (gpio + 31 > gpio_end) ? (gpio_end - gpio + 1) : 32;
137 gpiochip_add(c);
138 }
139 pxa_gpio_chips = chips;
140 return 0;
Eric Miaoa58fbcd2009-01-06 17:37:37 +0800141}
142
Eric Miaoa8f6fae2009-04-21 14:39:07 +0800143/* Update only those GRERx and GFERx edge detection register bits if those
144 * bits are set in c->irq_mask
145 */
146static inline void update_edge_detect(struct pxa_gpio_chip *c)
147{
148 uint32_t grer, gfer;
149
150 grer = __raw_readl(c->regbase + GRER_OFFSET) & ~c->irq_mask;
151 gfer = __raw_readl(c->regbase + GFER_OFFSET) & ~c->irq_mask;
152 grer |= c->irq_edge_rise & c->irq_mask;
153 gfer |= c->irq_edge_fall & c->irq_mask;
154 __raw_writel(grer, c->regbase + GRER_OFFSET);
155 __raw_writel(gfer, c->regbase + GFER_OFFSET);
156}
157
Lennert Buytenheka3f4c922010-11-29 11:18:26 +0100158static int pxa_gpio_irq_type(struct irq_data *d, unsigned int type)
eric miaoe3630db2008-03-04 11:42:26 +0800159{
Eric Miao0807da52009-01-07 18:01:51 +0800160 struct pxa_gpio_chip *c;
Lennert Buytenheka3f4c922010-11-29 11:18:26 +0100161 int gpio = irq_to_gpio(d->irq);
Eric Miao0807da52009-01-07 18:01:51 +0800162 unsigned long gpdr, mask = GPIO_bit(gpio);
eric miaoe3630db2008-03-04 11:42:26 +0800163
Linus Walleija0656852011-06-13 10:42:19 +0200164 c = gpio_to_pxachip(gpio);
eric miaoe3630db2008-03-04 11:42:26 +0800165
166 if (type == IRQ_TYPE_PROBE) {
167 /* Don't mess with enabled GPIOs using preconfigured edges or
168 * GPIOs set to alternate function or to output during probe
169 */
Eric Miao0807da52009-01-07 18:01:51 +0800170 if ((c->irq_edge_rise | c->irq_edge_fall) & GPIO_bit(gpio))
eric miaoe3630db2008-03-04 11:42:26 +0800171 return 0;
eric miao689c04a2008-03-04 17:18:38 +0800172
173 if (__gpio_is_occupied(gpio))
eric miaoe3630db2008-03-04 11:42:26 +0800174 return 0;
eric miao689c04a2008-03-04 17:18:38 +0800175
eric miaoe3630db2008-03-04 11:42:26 +0800176 type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING;
177 }
178
Eric Miao0807da52009-01-07 18:01:51 +0800179 gpdr = __raw_readl(c->regbase + GPDR_OFFSET);
180
Eric Miao067455a2008-11-26 18:12:04 +0800181 if (__gpio_is_inverted(gpio))
Eric Miao0807da52009-01-07 18:01:51 +0800182 __raw_writel(gpdr | mask, c->regbase + GPDR_OFFSET);
Eric Miao067455a2008-11-26 18:12:04 +0800183 else
Eric Miao0807da52009-01-07 18:01:51 +0800184 __raw_writel(gpdr & ~mask, c->regbase + GPDR_OFFSET);
eric miaoe3630db2008-03-04 11:42:26 +0800185
186 if (type & IRQ_TYPE_EDGE_RISING)
Eric Miao0807da52009-01-07 18:01:51 +0800187 c->irq_edge_rise |= mask;
eric miaoe3630db2008-03-04 11:42:26 +0800188 else
Eric Miao0807da52009-01-07 18:01:51 +0800189 c->irq_edge_rise &= ~mask;
eric miaoe3630db2008-03-04 11:42:26 +0800190
191 if (type & IRQ_TYPE_EDGE_FALLING)
Eric Miao0807da52009-01-07 18:01:51 +0800192 c->irq_edge_fall |= mask;
eric miaoe3630db2008-03-04 11:42:26 +0800193 else
Eric Miao0807da52009-01-07 18:01:51 +0800194 c->irq_edge_fall &= ~mask;
eric miaoe3630db2008-03-04 11:42:26 +0800195
Eric Miaoa8f6fae2009-04-21 14:39:07 +0800196 update_edge_detect(c);
eric miaoe3630db2008-03-04 11:42:26 +0800197
Lennert Buytenheka3f4c922010-11-29 11:18:26 +0100198 pr_debug("%s: IRQ%d (GPIO%d) - edge%s%s\n", __func__, d->irq, gpio,
eric miaoe3630db2008-03-04 11:42:26 +0800199 ((type & IRQ_TYPE_EDGE_RISING) ? " rising" : ""),
200 ((type & IRQ_TYPE_EDGE_FALLING) ? " falling" : ""));
201 return 0;
202}
203
eric miaoe3630db2008-03-04 11:42:26 +0800204static void pxa_gpio_demux_handler(unsigned int irq, struct irq_desc *desc)
205{
Eric Miao0807da52009-01-07 18:01:51 +0800206 struct pxa_gpio_chip *c;
207 int loop, gpio, gpio_base, n;
208 unsigned long gedr;
eric miaoe3630db2008-03-04 11:42:26 +0800209
210 do {
eric miaoe3630db2008-03-04 11:42:26 +0800211 loop = 0;
Eric Miao0807da52009-01-07 18:01:51 +0800212 for_each_gpio_chip(gpio, c) {
213 gpio_base = c->chip.base;
eric miaoe3630db2008-03-04 11:42:26 +0800214
Eric Miao0807da52009-01-07 18:01:51 +0800215 gedr = __raw_readl(c->regbase + GEDR_OFFSET);
216 gedr = gedr & c->irq_mask;
217 __raw_writel(gedr, c->regbase + GEDR_OFFSET);
eric miaoe3630db2008-03-04 11:42:26 +0800218
Eric Miao0807da52009-01-07 18:01:51 +0800219 n = find_first_bit(&gedr, BITS_PER_LONG);
220 while (n < BITS_PER_LONG) {
221 loop = 1;
222
223 generic_handle_irq(gpio_to_irq(gpio_base + n));
224 n = find_next_bit(&gedr, BITS_PER_LONG, n + 1);
225 }
eric miaoe3630db2008-03-04 11:42:26 +0800226 }
227 } while (loop);
228}
229
Lennert Buytenheka3f4c922010-11-29 11:18:26 +0100230static void pxa_ack_muxed_gpio(struct irq_data *d)
eric miaoe3630db2008-03-04 11:42:26 +0800231{
Lennert Buytenheka3f4c922010-11-29 11:18:26 +0100232 int gpio = irq_to_gpio(d->irq);
Linus Walleija0656852011-06-13 10:42:19 +0200233 struct pxa_gpio_chip *c = gpio_to_pxachip(gpio);
Eric Miao0807da52009-01-07 18:01:51 +0800234
235 __raw_writel(GPIO_bit(gpio), c->regbase + GEDR_OFFSET);
eric miaoe3630db2008-03-04 11:42:26 +0800236}
237
Lennert Buytenheka3f4c922010-11-29 11:18:26 +0100238static void pxa_mask_muxed_gpio(struct irq_data *d)
eric miaoe3630db2008-03-04 11:42:26 +0800239{
Lennert Buytenheka3f4c922010-11-29 11:18:26 +0100240 int gpio = irq_to_gpio(d->irq);
Linus Walleija0656852011-06-13 10:42:19 +0200241 struct pxa_gpio_chip *c = gpio_to_pxachip(gpio);
Eric Miao0807da52009-01-07 18:01:51 +0800242 uint32_t grer, gfer;
243
244 c->irq_mask &= ~GPIO_bit(gpio);
245
246 grer = __raw_readl(c->regbase + GRER_OFFSET) & ~GPIO_bit(gpio);
247 gfer = __raw_readl(c->regbase + GFER_OFFSET) & ~GPIO_bit(gpio);
248 __raw_writel(grer, c->regbase + GRER_OFFSET);
249 __raw_writel(gfer, c->regbase + GFER_OFFSET);
eric miaoe3630db2008-03-04 11:42:26 +0800250}
251
Lennert Buytenheka3f4c922010-11-29 11:18:26 +0100252static void pxa_unmask_muxed_gpio(struct irq_data *d)
eric miaoe3630db2008-03-04 11:42:26 +0800253{
Lennert Buytenheka3f4c922010-11-29 11:18:26 +0100254 int gpio = irq_to_gpio(d->irq);
Linus Walleija0656852011-06-13 10:42:19 +0200255 struct pxa_gpio_chip *c = gpio_to_pxachip(gpio);
Eric Miao0807da52009-01-07 18:01:51 +0800256
257 c->irq_mask |= GPIO_bit(gpio);
Eric Miaoa8f6fae2009-04-21 14:39:07 +0800258 update_edge_detect(c);
eric miaoe3630db2008-03-04 11:42:26 +0800259}
260
261static struct irq_chip pxa_muxed_gpio_chip = {
262 .name = "GPIO",
Lennert Buytenheka3f4c922010-11-29 11:18:26 +0100263 .irq_ack = pxa_ack_muxed_gpio,
264 .irq_mask = pxa_mask_muxed_gpio,
265 .irq_unmask = pxa_unmask_muxed_gpio,
266 .irq_set_type = pxa_gpio_irq_type,
eric miaoe3630db2008-03-04 11:42:26 +0800267};
268
Eric Miaoa58fbcd2009-01-06 17:37:37 +0800269void __init pxa_init_gpio(int mux_irq, int start, int end, set_wake_t fn)
eric miaoe3630db2008-03-04 11:42:26 +0800270{
Eric Miao0807da52009-01-07 18:01:51 +0800271 struct pxa_gpio_chip *c;
272 int gpio, irq;
eric miaoe3630db2008-03-04 11:42:26 +0800273
Eric Miaoa58fbcd2009-01-06 17:37:37 +0800274 pxa_last_gpio = end;
eric miaoe3630db2008-03-04 11:42:26 +0800275
Eric Miao0807da52009-01-07 18:01:51 +0800276 /* Initialize GPIO chips */
277 pxa_init_gpio_chip(end);
278
eric miaoe3630db2008-03-04 11:42:26 +0800279 /* clear all GPIO edge detects */
Eric Miao0807da52009-01-07 18:01:51 +0800280 for_each_gpio_chip(gpio, c) {
281 __raw_writel(0, c->regbase + GFER_OFFSET);
282 __raw_writel(0, c->regbase + GRER_OFFSET);
283 __raw_writel(~0,c->regbase + GEDR_OFFSET);
eric miaoe3630db2008-03-04 11:42:26 +0800284 }
285
Eric Miaoa58fbcd2009-01-06 17:37:37 +0800286 for (irq = gpio_to_irq(start); irq <= gpio_to_irq(end); irq++) {
Thomas Gleixnerf38c02f2011-03-24 13:35:09 +0100287 irq_set_chip_and_handler(irq, &pxa_muxed_gpio_chip,
288 handle_edge_irq);
eric miaoe3630db2008-03-04 11:42:26 +0800289 set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
290 }
291
292 /* Install handler for GPIO>=2 edge detect interrupts */
Thomas Gleixner6845664a2011-03-24 13:25:22 +0100293 irq_set_chained_handler(mux_irq, pxa_gpio_demux_handler);
Lennert Buytenheka3f4c922010-11-29 11:18:26 +0100294 pxa_muxed_gpio_chip.irq_set_wake = fn;
eric miaoe3630db2008-03-04 11:42:26 +0800295}
eric miao663707c2008-03-04 16:13:58 +0800296
297#ifdef CONFIG_PM
Rafael J. Wysocki2eaa03b2011-04-22 22:03:11 +0200298static int pxa_gpio_suspend(void)
eric miao663707c2008-03-04 16:13:58 +0800299{
Eric Miao0807da52009-01-07 18:01:51 +0800300 struct pxa_gpio_chip *c;
301 int gpio;
eric miao663707c2008-03-04 16:13:58 +0800302
Eric Miao0807da52009-01-07 18:01:51 +0800303 for_each_gpio_chip(gpio, c) {
304 c->saved_gplr = __raw_readl(c->regbase + GPLR_OFFSET);
305 c->saved_gpdr = __raw_readl(c->regbase + GPDR_OFFSET);
306 c->saved_grer = __raw_readl(c->regbase + GRER_OFFSET);
307 c->saved_gfer = __raw_readl(c->regbase + GFER_OFFSET);
eric miao663707c2008-03-04 16:13:58 +0800308
309 /* Clear GPIO transition detect bits */
Eric Miao0807da52009-01-07 18:01:51 +0800310 __raw_writel(0xffffffff, c->regbase + GEDR_OFFSET);
eric miao663707c2008-03-04 16:13:58 +0800311 }
312 return 0;
313}
314
Rafael J. Wysocki2eaa03b2011-04-22 22:03:11 +0200315static void pxa_gpio_resume(void)
eric miao663707c2008-03-04 16:13:58 +0800316{
Eric Miao0807da52009-01-07 18:01:51 +0800317 struct pxa_gpio_chip *c;
318 int gpio;
eric miao663707c2008-03-04 16:13:58 +0800319
Eric Miao0807da52009-01-07 18:01:51 +0800320 for_each_gpio_chip(gpio, c) {
eric miao663707c2008-03-04 16:13:58 +0800321 /* restore level with set/clear */
Eric Miao0807da52009-01-07 18:01:51 +0800322 __raw_writel( c->saved_gplr, c->regbase + GPSR_OFFSET);
323 __raw_writel(~c->saved_gplr, c->regbase + GPCR_OFFSET);
eric miao663707c2008-03-04 16:13:58 +0800324
Eric Miao0807da52009-01-07 18:01:51 +0800325 __raw_writel(c->saved_grer, c->regbase + GRER_OFFSET);
326 __raw_writel(c->saved_gfer, c->regbase + GFER_OFFSET);
327 __raw_writel(c->saved_gpdr, c->regbase + GPDR_OFFSET);
eric miao663707c2008-03-04 16:13:58 +0800328 }
eric miao663707c2008-03-04 16:13:58 +0800329}
330#else
331#define pxa_gpio_suspend NULL
332#define pxa_gpio_resume NULL
333#endif
334
Rafael J. Wysocki2eaa03b2011-04-22 22:03:11 +0200335struct syscore_ops pxa_gpio_syscore_ops = {
eric miao663707c2008-03-04 16:13:58 +0800336 .suspend = pxa_gpio_suspend,
337 .resume = pxa_gpio_resume,
338};