blob: 4f53dd2a99a818e05c47f41c09f9725f5c093095 [file] [log] [blame]
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001/*
2 * drivers/net/ethernet/mellanox/mlxsw/spectrum.c
3 * Copyright (c) 2015 Mellanox Technologies. All rights reserved.
4 * Copyright (c) 2015 Jiri Pirko <jiri@mellanox.com>
5 * Copyright (c) 2015 Ido Schimmel <idosch@mellanox.com>
6 * Copyright (c) 2015 Elad Raz <eladr@mellanox.com>
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions are met:
10 *
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 * 3. Neither the names of the copyright holders nor the names of its
17 * contributors may be used to endorse or promote products derived from
18 * this software without specific prior written permission.
19 *
20 * Alternatively, this software may be distributed under the terms of the
21 * GNU General Public License ("GPL") version 2 as published by the Free
22 * Software Foundation.
23 *
24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
27 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
28 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
29 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
31 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
32 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
33 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
34 * POSSIBILITY OF SUCH DAMAGE.
35 */
36
37#include <linux/kernel.h>
38#include <linux/module.h>
39#include <linux/types.h>
40#include <linux/netdevice.h>
41#include <linux/etherdevice.h>
42#include <linux/ethtool.h>
43#include <linux/slab.h>
44#include <linux/device.h>
45#include <linux/skbuff.h>
46#include <linux/if_vlan.h>
47#include <linux/if_bridge.h>
48#include <linux/workqueue.h>
49#include <linux/jiffies.h>
50#include <linux/bitops.h>
Ido Schimmel7f71eb42015-12-15 16:03:37 +010051#include <linux/list.h>
Ido Schimmel80bedf12016-06-20 23:03:59 +020052#include <linux/notifier.h>
Ido Schimmel90183b92016-04-06 17:10:08 +020053#include <linux/dcbnl.h>
Jiri Pirko56ade8f2015-10-16 14:01:37 +020054#include <net/switchdev.h>
55#include <generated/utsrelease.h>
56
57#include "spectrum.h"
58#include "core.h"
59#include "reg.h"
60#include "port.h"
61#include "trap.h"
62#include "txheader.h"
63
64static const char mlxsw_sp_driver_name[] = "mlxsw_spectrum";
65static const char mlxsw_sp_driver_version[] = "1.0";
66
67/* tx_hdr_version
68 * Tx header version.
69 * Must be set to 1.
70 */
71MLXSW_ITEM32(tx, hdr, version, 0x00, 28, 4);
72
73/* tx_hdr_ctl
74 * Packet control type.
75 * 0 - Ethernet control (e.g. EMADs, LACP)
76 * 1 - Ethernet data
77 */
78MLXSW_ITEM32(tx, hdr, ctl, 0x00, 26, 2);
79
80/* tx_hdr_proto
81 * Packet protocol type. Must be set to 1 (Ethernet).
82 */
83MLXSW_ITEM32(tx, hdr, proto, 0x00, 21, 3);
84
85/* tx_hdr_rx_is_router
86 * Packet is sent from the router. Valid for data packets only.
87 */
88MLXSW_ITEM32(tx, hdr, rx_is_router, 0x00, 19, 1);
89
90/* tx_hdr_fid_valid
91 * Indicates if the 'fid' field is valid and should be used for
92 * forwarding lookup. Valid for data packets only.
93 */
94MLXSW_ITEM32(tx, hdr, fid_valid, 0x00, 16, 1);
95
96/* tx_hdr_swid
97 * Switch partition ID. Must be set to 0.
98 */
99MLXSW_ITEM32(tx, hdr, swid, 0x00, 12, 3);
100
101/* tx_hdr_control_tclass
102 * Indicates if the packet should use the control TClass and not one
103 * of the data TClasses.
104 */
105MLXSW_ITEM32(tx, hdr, control_tclass, 0x00, 6, 1);
106
107/* tx_hdr_etclass
108 * Egress TClass to be used on the egress device on the egress port.
109 */
110MLXSW_ITEM32(tx, hdr, etclass, 0x00, 0, 4);
111
112/* tx_hdr_port_mid
113 * Destination local port for unicast packets.
114 * Destination multicast ID for multicast packets.
115 *
116 * Control packets are directed to a specific egress port, while data
117 * packets are transmitted through the CPU port (0) into the switch partition,
118 * where forwarding rules are applied.
119 */
120MLXSW_ITEM32(tx, hdr, port_mid, 0x04, 16, 16);
121
122/* tx_hdr_fid
123 * Forwarding ID used for L2 forwarding lookup. Valid only if 'fid_valid' is
124 * set, otherwise calculated based on the packet's VID using VID to FID mapping.
125 * Valid for data packets only.
126 */
127MLXSW_ITEM32(tx, hdr, fid, 0x08, 0, 16);
128
129/* tx_hdr_type
130 * 0 - Data packets
131 * 6 - Control packets
132 */
133MLXSW_ITEM32(tx, hdr, type, 0x0C, 0, 4);
134
135static void mlxsw_sp_txhdr_construct(struct sk_buff *skb,
136 const struct mlxsw_tx_info *tx_info)
137{
138 char *txhdr = skb_push(skb, MLXSW_TXHDR_LEN);
139
140 memset(txhdr, 0, MLXSW_TXHDR_LEN);
141
142 mlxsw_tx_hdr_version_set(txhdr, MLXSW_TXHDR_VERSION_1);
143 mlxsw_tx_hdr_ctl_set(txhdr, MLXSW_TXHDR_ETH_CTL);
144 mlxsw_tx_hdr_proto_set(txhdr, MLXSW_TXHDR_PROTO_ETH);
145 mlxsw_tx_hdr_swid_set(txhdr, 0);
146 mlxsw_tx_hdr_control_tclass_set(txhdr, 1);
147 mlxsw_tx_hdr_port_mid_set(txhdr, tx_info->local_port);
148 mlxsw_tx_hdr_type_set(txhdr, MLXSW_TXHDR_TYPE_CONTROL);
149}
150
151static int mlxsw_sp_base_mac_get(struct mlxsw_sp *mlxsw_sp)
152{
153 char spad_pl[MLXSW_REG_SPAD_LEN];
154 int err;
155
156 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(spad), spad_pl);
157 if (err)
158 return err;
159 mlxsw_reg_spad_base_mac_memcpy_from(spad_pl, mlxsw_sp->base_mac);
160 return 0;
161}
162
163static int mlxsw_sp_port_admin_status_set(struct mlxsw_sp_port *mlxsw_sp_port,
164 bool is_up)
165{
166 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
167 char paos_pl[MLXSW_REG_PAOS_LEN];
168
169 mlxsw_reg_paos_pack(paos_pl, mlxsw_sp_port->local_port,
170 is_up ? MLXSW_PORT_ADMIN_STATUS_UP :
171 MLXSW_PORT_ADMIN_STATUS_DOWN);
172 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(paos), paos_pl);
173}
174
175static int mlxsw_sp_port_oper_status_get(struct mlxsw_sp_port *mlxsw_sp_port,
176 bool *p_is_up)
177{
178 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
179 char paos_pl[MLXSW_REG_PAOS_LEN];
180 u8 oper_status;
181 int err;
182
183 mlxsw_reg_paos_pack(paos_pl, mlxsw_sp_port->local_port, 0);
184 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(paos), paos_pl);
185 if (err)
186 return err;
187 oper_status = mlxsw_reg_paos_oper_status_get(paos_pl);
188 *p_is_up = oper_status == MLXSW_PORT_ADMIN_STATUS_UP ? true : false;
189 return 0;
190}
191
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200192static int mlxsw_sp_port_dev_addr_set(struct mlxsw_sp_port *mlxsw_sp_port,
193 unsigned char *addr)
194{
195 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
196 char ppad_pl[MLXSW_REG_PPAD_LEN];
197
198 mlxsw_reg_ppad_pack(ppad_pl, true, mlxsw_sp_port->local_port);
199 mlxsw_reg_ppad_mac_memcpy_to(ppad_pl, addr);
200 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(ppad), ppad_pl);
201}
202
203static int mlxsw_sp_port_dev_addr_init(struct mlxsw_sp_port *mlxsw_sp_port)
204{
205 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
206 unsigned char *addr = mlxsw_sp_port->dev->dev_addr;
207
208 ether_addr_copy(addr, mlxsw_sp->base_mac);
209 addr[ETH_ALEN - 1] += mlxsw_sp_port->local_port;
210 return mlxsw_sp_port_dev_addr_set(mlxsw_sp_port, addr);
211}
212
213static int mlxsw_sp_port_stp_state_set(struct mlxsw_sp_port *mlxsw_sp_port,
214 u16 vid, enum mlxsw_reg_spms_state state)
215{
216 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
217 char *spms_pl;
218 int err;
219
220 spms_pl = kmalloc(MLXSW_REG_SPMS_LEN, GFP_KERNEL);
221 if (!spms_pl)
222 return -ENOMEM;
223 mlxsw_reg_spms_pack(spms_pl, mlxsw_sp_port->local_port);
224 mlxsw_reg_spms_vid_pack(spms_pl, vid, state);
225 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spms), spms_pl);
226 kfree(spms_pl);
227 return err;
228}
229
230static int mlxsw_sp_port_mtu_set(struct mlxsw_sp_port *mlxsw_sp_port, u16 mtu)
231{
232 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
233 char pmtu_pl[MLXSW_REG_PMTU_LEN];
234 int max_mtu;
235 int err;
236
237 mtu += MLXSW_TXHDR_LEN + ETH_HLEN;
238 mlxsw_reg_pmtu_pack(pmtu_pl, mlxsw_sp_port->local_port, 0);
239 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(pmtu), pmtu_pl);
240 if (err)
241 return err;
242 max_mtu = mlxsw_reg_pmtu_max_mtu_get(pmtu_pl);
243
244 if (mtu > max_mtu)
245 return -EINVAL;
246
247 mlxsw_reg_pmtu_pack(pmtu_pl, mlxsw_sp_port->local_port, mtu);
248 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(pmtu), pmtu_pl);
249}
250
Ido Schimmelbe945352016-06-09 09:51:39 +0200251static int __mlxsw_sp_port_swid_set(struct mlxsw_sp *mlxsw_sp, u8 local_port,
252 u8 swid)
253{
254 char pspa_pl[MLXSW_REG_PSPA_LEN];
255
256 mlxsw_reg_pspa_pack(pspa_pl, swid, local_port);
257 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(pspa), pspa_pl);
258}
259
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200260static int mlxsw_sp_port_swid_set(struct mlxsw_sp_port *mlxsw_sp_port, u8 swid)
261{
262 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200263
Ido Schimmelbe945352016-06-09 09:51:39 +0200264 return __mlxsw_sp_port_swid_set(mlxsw_sp, mlxsw_sp_port->local_port,
265 swid);
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200266}
267
268static int mlxsw_sp_port_vp_mode_set(struct mlxsw_sp_port *mlxsw_sp_port,
269 bool enable)
270{
271 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
272 char svpe_pl[MLXSW_REG_SVPE_LEN];
273
274 mlxsw_reg_svpe_pack(svpe_pl, mlxsw_sp_port->local_port, enable);
275 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(svpe), svpe_pl);
276}
277
278int mlxsw_sp_port_vid_to_fid_set(struct mlxsw_sp_port *mlxsw_sp_port,
279 enum mlxsw_reg_svfa_mt mt, bool valid, u16 fid,
280 u16 vid)
281{
282 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
283 char svfa_pl[MLXSW_REG_SVFA_LEN];
284
285 mlxsw_reg_svfa_pack(svfa_pl, mlxsw_sp_port->local_port, mt, valid,
286 fid, vid);
287 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(svfa), svfa_pl);
288}
289
290static int mlxsw_sp_port_vid_learning_set(struct mlxsw_sp_port *mlxsw_sp_port,
291 u16 vid, bool learn_enable)
292{
293 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
294 char *spvmlr_pl;
295 int err;
296
297 spvmlr_pl = kmalloc(MLXSW_REG_SPVMLR_LEN, GFP_KERNEL);
298 if (!spvmlr_pl)
299 return -ENOMEM;
300 mlxsw_reg_spvmlr_pack(spvmlr_pl, mlxsw_sp_port->local_port, vid, vid,
301 learn_enable);
302 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spvmlr), spvmlr_pl);
303 kfree(spvmlr_pl);
304 return err;
305}
306
307static int
308mlxsw_sp_port_system_port_mapping_set(struct mlxsw_sp_port *mlxsw_sp_port)
309{
310 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
311 char sspr_pl[MLXSW_REG_SSPR_LEN];
312
313 mlxsw_reg_sspr_pack(sspr_pl, mlxsw_sp_port->local_port);
314 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sspr), sspr_pl);
315}
316
Ido Schimmeld664b412016-06-09 09:51:40 +0200317static int mlxsw_sp_port_module_info_get(struct mlxsw_sp *mlxsw_sp,
318 u8 local_port, u8 *p_module,
319 u8 *p_width, u8 *p_lane)
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200320{
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200321 char pmlp_pl[MLXSW_REG_PMLP_LEN];
322 int err;
323
Ido Schimmel558c2d52016-02-26 17:32:29 +0100324 mlxsw_reg_pmlp_pack(pmlp_pl, local_port);
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200325 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(pmlp), pmlp_pl);
326 if (err)
327 return err;
Ido Schimmel558c2d52016-02-26 17:32:29 +0100328 *p_module = mlxsw_reg_pmlp_module_get(pmlp_pl, 0);
329 *p_width = mlxsw_reg_pmlp_width_get(pmlp_pl);
Ido Schimmel2bf9a582016-04-05 10:20:04 +0200330 *p_lane = mlxsw_reg_pmlp_tx_lane_get(pmlp_pl, 0);
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200331 return 0;
332}
333
Ido Schimmel18f1e702016-02-26 17:32:31 +0100334static int mlxsw_sp_port_module_map(struct mlxsw_sp *mlxsw_sp, u8 local_port,
335 u8 module, u8 width, u8 lane)
336{
337 char pmlp_pl[MLXSW_REG_PMLP_LEN];
338 int i;
339
340 mlxsw_reg_pmlp_pack(pmlp_pl, local_port);
341 mlxsw_reg_pmlp_width_set(pmlp_pl, width);
342 for (i = 0; i < width; i++) {
343 mlxsw_reg_pmlp_module_set(pmlp_pl, i, module);
344 mlxsw_reg_pmlp_tx_lane_set(pmlp_pl, i, lane + i); /* Rx & Tx */
345 }
346
347 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(pmlp), pmlp_pl);
348}
349
Ido Schimmel3e9b27b2016-02-26 17:32:28 +0100350static int mlxsw_sp_port_module_unmap(struct mlxsw_sp *mlxsw_sp, u8 local_port)
351{
352 char pmlp_pl[MLXSW_REG_PMLP_LEN];
353
354 mlxsw_reg_pmlp_pack(pmlp_pl, local_port);
355 mlxsw_reg_pmlp_width_set(pmlp_pl, 0);
356 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(pmlp), pmlp_pl);
357}
358
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200359static int mlxsw_sp_port_open(struct net_device *dev)
360{
361 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
362 int err;
363
364 err = mlxsw_sp_port_admin_status_set(mlxsw_sp_port, true);
365 if (err)
366 return err;
367 netif_start_queue(dev);
368 return 0;
369}
370
371static int mlxsw_sp_port_stop(struct net_device *dev)
372{
373 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
374
375 netif_stop_queue(dev);
376 return mlxsw_sp_port_admin_status_set(mlxsw_sp_port, false);
377}
378
379static netdev_tx_t mlxsw_sp_port_xmit(struct sk_buff *skb,
380 struct net_device *dev)
381{
382 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
383 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
384 struct mlxsw_sp_port_pcpu_stats *pcpu_stats;
385 const struct mlxsw_tx_info tx_info = {
386 .local_port = mlxsw_sp_port->local_port,
387 .is_emad = false,
388 };
389 u64 len;
390 int err;
391
Jiri Pirko307c2432016-04-08 19:11:22 +0200392 if (mlxsw_core_skb_transmit_busy(mlxsw_sp->core, &tx_info))
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200393 return NETDEV_TX_BUSY;
394
395 if (unlikely(skb_headroom(skb) < MLXSW_TXHDR_LEN)) {
396 struct sk_buff *skb_orig = skb;
397
398 skb = skb_realloc_headroom(skb, MLXSW_TXHDR_LEN);
399 if (!skb) {
400 this_cpu_inc(mlxsw_sp_port->pcpu_stats->tx_dropped);
401 dev_kfree_skb_any(skb_orig);
402 return NETDEV_TX_OK;
403 }
404 }
405
406 if (eth_skb_pad(skb)) {
407 this_cpu_inc(mlxsw_sp_port->pcpu_stats->tx_dropped);
408 return NETDEV_TX_OK;
409 }
410
411 mlxsw_sp_txhdr_construct(skb, &tx_info);
412 len = skb->len;
413 /* Due to a race we might fail here because of a full queue. In that
414 * unlikely case we simply drop the packet.
415 */
Jiri Pirko307c2432016-04-08 19:11:22 +0200416 err = mlxsw_core_skb_transmit(mlxsw_sp->core, skb, &tx_info);
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200417
418 if (!err) {
419 pcpu_stats = this_cpu_ptr(mlxsw_sp_port->pcpu_stats);
420 u64_stats_update_begin(&pcpu_stats->syncp);
421 pcpu_stats->tx_packets++;
422 pcpu_stats->tx_bytes += len;
423 u64_stats_update_end(&pcpu_stats->syncp);
424 } else {
425 this_cpu_inc(mlxsw_sp_port->pcpu_stats->tx_dropped);
426 dev_kfree_skb_any(skb);
427 }
428 return NETDEV_TX_OK;
429}
430
Jiri Pirkoc5b9b512015-12-03 12:12:22 +0100431static void mlxsw_sp_set_rx_mode(struct net_device *dev)
432{
433}
434
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200435static int mlxsw_sp_port_set_mac_address(struct net_device *dev, void *p)
436{
437 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
438 struct sockaddr *addr = p;
439 int err;
440
441 if (!is_valid_ether_addr(addr->sa_data))
442 return -EADDRNOTAVAIL;
443
444 err = mlxsw_sp_port_dev_addr_set(mlxsw_sp_port, addr->sa_data);
445 if (err)
446 return err;
447 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
448 return 0;
449}
450
Ido Schimmel9f7ec052016-04-06 17:10:14 +0200451static void mlxsw_sp_pg_buf_pack(char *pbmc_pl, int pg_index, int mtu,
Ido Schimmeld81a6bd2016-04-06 17:10:16 +0200452 bool pause_en, bool pfc_en, u16 delay)
Ido Schimmel8e8dfe92016-04-06 17:10:10 +0200453{
454 u16 pg_size = 2 * MLXSW_SP_BYTES_TO_CELLS(mtu);
455
Ido Schimmeld81a6bd2016-04-06 17:10:16 +0200456 delay = pfc_en ? mlxsw_sp_pfc_delay_get(mtu, delay) :
457 MLXSW_SP_PAUSE_DELAY;
Ido Schimmel9f7ec052016-04-06 17:10:14 +0200458
Ido Schimmeld81a6bd2016-04-06 17:10:16 +0200459 if (pause_en || pfc_en)
Ido Schimmel9f7ec052016-04-06 17:10:14 +0200460 mlxsw_reg_pbmc_lossless_buffer_pack(pbmc_pl, pg_index,
Ido Schimmeld81a6bd2016-04-06 17:10:16 +0200461 pg_size + delay, pg_size);
462 else
Ido Schimmel9f7ec052016-04-06 17:10:14 +0200463 mlxsw_reg_pbmc_lossy_buffer_pack(pbmc_pl, pg_index, pg_size);
Ido Schimmel8e8dfe92016-04-06 17:10:10 +0200464}
465
466int __mlxsw_sp_port_headroom_set(struct mlxsw_sp_port *mlxsw_sp_port, int mtu,
Ido Schimmeld81a6bd2016-04-06 17:10:16 +0200467 u8 *prio_tc, bool pause_en,
468 struct ieee_pfc *my_pfc)
Ido Schimmelff6551e2016-04-06 17:10:03 +0200469{
470 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
Ido Schimmeld81a6bd2016-04-06 17:10:16 +0200471 u8 pfc_en = !!my_pfc ? my_pfc->pfc_en : 0;
472 u16 delay = !!my_pfc ? my_pfc->delay : 0;
Ido Schimmelff6551e2016-04-06 17:10:03 +0200473 char pbmc_pl[MLXSW_REG_PBMC_LEN];
Ido Schimmel8e8dfe92016-04-06 17:10:10 +0200474 int i, j, err;
Ido Schimmelff6551e2016-04-06 17:10:03 +0200475
476 mlxsw_reg_pbmc_pack(pbmc_pl, mlxsw_sp_port->local_port, 0, 0);
477 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(pbmc), pbmc_pl);
478 if (err)
479 return err;
Ido Schimmel8e8dfe92016-04-06 17:10:10 +0200480
481 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
482 bool configure = false;
Ido Schimmeld81a6bd2016-04-06 17:10:16 +0200483 bool pfc = false;
Ido Schimmel8e8dfe92016-04-06 17:10:10 +0200484
485 for (j = 0; j < IEEE_8021QAZ_MAX_TCS; j++) {
486 if (prio_tc[j] == i) {
Ido Schimmeld81a6bd2016-04-06 17:10:16 +0200487 pfc = pfc_en & BIT(j);
Ido Schimmel8e8dfe92016-04-06 17:10:10 +0200488 configure = true;
489 break;
490 }
491 }
492
493 if (!configure)
494 continue;
Ido Schimmeld81a6bd2016-04-06 17:10:16 +0200495 mlxsw_sp_pg_buf_pack(pbmc_pl, i, mtu, pause_en, pfc, delay);
Ido Schimmel8e8dfe92016-04-06 17:10:10 +0200496 }
497
Ido Schimmelff6551e2016-04-06 17:10:03 +0200498 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(pbmc), pbmc_pl);
499}
500
Ido Schimmel8e8dfe92016-04-06 17:10:10 +0200501static int mlxsw_sp_port_headroom_set(struct mlxsw_sp_port *mlxsw_sp_port,
Ido Schimmel9f7ec052016-04-06 17:10:14 +0200502 int mtu, bool pause_en)
Ido Schimmel8e8dfe92016-04-06 17:10:10 +0200503{
504 u8 def_prio_tc[IEEE_8021QAZ_MAX_TCS] = {0};
505 bool dcb_en = !!mlxsw_sp_port->dcb.ets;
Ido Schimmeld81a6bd2016-04-06 17:10:16 +0200506 struct ieee_pfc *my_pfc;
Ido Schimmel8e8dfe92016-04-06 17:10:10 +0200507 u8 *prio_tc;
508
509 prio_tc = dcb_en ? mlxsw_sp_port->dcb.ets->prio_tc : def_prio_tc;
Ido Schimmeld81a6bd2016-04-06 17:10:16 +0200510 my_pfc = dcb_en ? mlxsw_sp_port->dcb.pfc : NULL;
Ido Schimmel8e8dfe92016-04-06 17:10:10 +0200511
Ido Schimmel9f7ec052016-04-06 17:10:14 +0200512 return __mlxsw_sp_port_headroom_set(mlxsw_sp_port, mtu, prio_tc,
Ido Schimmeld81a6bd2016-04-06 17:10:16 +0200513 pause_en, my_pfc);
Ido Schimmel8e8dfe92016-04-06 17:10:10 +0200514}
515
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200516static int mlxsw_sp_port_change_mtu(struct net_device *dev, int mtu)
517{
518 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
Ido Schimmel9f7ec052016-04-06 17:10:14 +0200519 bool pause_en = mlxsw_sp_port_is_pause_en(mlxsw_sp_port);
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200520 int err;
521
Ido Schimmel9f7ec052016-04-06 17:10:14 +0200522 err = mlxsw_sp_port_headroom_set(mlxsw_sp_port, mtu, pause_en);
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200523 if (err)
524 return err;
Ido Schimmelff6551e2016-04-06 17:10:03 +0200525 err = mlxsw_sp_port_mtu_set(mlxsw_sp_port, mtu);
526 if (err)
527 goto err_port_mtu_set;
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200528 dev->mtu = mtu;
529 return 0;
Ido Schimmelff6551e2016-04-06 17:10:03 +0200530
531err_port_mtu_set:
Ido Schimmel9f7ec052016-04-06 17:10:14 +0200532 mlxsw_sp_port_headroom_set(mlxsw_sp_port, dev->mtu, pause_en);
Ido Schimmelff6551e2016-04-06 17:10:03 +0200533 return err;
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200534}
535
536static struct rtnl_link_stats64 *
537mlxsw_sp_port_get_stats64(struct net_device *dev,
538 struct rtnl_link_stats64 *stats)
539{
540 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
541 struct mlxsw_sp_port_pcpu_stats *p;
542 u64 rx_packets, rx_bytes, tx_packets, tx_bytes;
543 u32 tx_dropped = 0;
544 unsigned int start;
545 int i;
546
547 for_each_possible_cpu(i) {
548 p = per_cpu_ptr(mlxsw_sp_port->pcpu_stats, i);
549 do {
550 start = u64_stats_fetch_begin_irq(&p->syncp);
551 rx_packets = p->rx_packets;
552 rx_bytes = p->rx_bytes;
553 tx_packets = p->tx_packets;
554 tx_bytes = p->tx_bytes;
555 } while (u64_stats_fetch_retry_irq(&p->syncp, start));
556
557 stats->rx_packets += rx_packets;
558 stats->rx_bytes += rx_bytes;
559 stats->tx_packets += tx_packets;
560 stats->tx_bytes += tx_bytes;
561 /* tx_dropped is u32, updated without syncp protection. */
562 tx_dropped += p->tx_dropped;
563 }
564 stats->tx_dropped = tx_dropped;
565 return stats;
566}
567
568int mlxsw_sp_port_vlan_set(struct mlxsw_sp_port *mlxsw_sp_port, u16 vid_begin,
569 u16 vid_end, bool is_member, bool untagged)
570{
571 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
572 char *spvm_pl;
573 int err;
574
575 spvm_pl = kmalloc(MLXSW_REG_SPVM_LEN, GFP_KERNEL);
576 if (!spvm_pl)
577 return -ENOMEM;
578
579 mlxsw_reg_spvm_pack(spvm_pl, mlxsw_sp_port->local_port, vid_begin,
580 vid_end, is_member, untagged);
581 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spvm), spvm_pl);
582 kfree(spvm_pl);
583 return err;
584}
585
586static int mlxsw_sp_port_vp_mode_trans(struct mlxsw_sp_port *mlxsw_sp_port)
587{
588 enum mlxsw_reg_svfa_mt mt = MLXSW_REG_SVFA_MT_PORT_VID_TO_FID;
589 u16 vid, last_visited_vid;
590 int err;
591
592 for_each_set_bit(vid, mlxsw_sp_port->active_vlans, VLAN_N_VID) {
593 err = mlxsw_sp_port_vid_to_fid_set(mlxsw_sp_port, mt, true, vid,
594 vid);
595 if (err) {
596 last_visited_vid = vid;
597 goto err_port_vid_to_fid_set;
598 }
599 }
600
601 err = mlxsw_sp_port_vp_mode_set(mlxsw_sp_port, true);
602 if (err) {
603 last_visited_vid = VLAN_N_VID;
604 goto err_port_vid_to_fid_set;
605 }
606
607 return 0;
608
609err_port_vid_to_fid_set:
610 for_each_set_bit(vid, mlxsw_sp_port->active_vlans, last_visited_vid)
611 mlxsw_sp_port_vid_to_fid_set(mlxsw_sp_port, mt, false, vid,
612 vid);
613 return err;
614}
615
616static int mlxsw_sp_port_vlan_mode_trans(struct mlxsw_sp_port *mlxsw_sp_port)
617{
618 enum mlxsw_reg_svfa_mt mt = MLXSW_REG_SVFA_MT_PORT_VID_TO_FID;
619 u16 vid;
620 int err;
621
622 err = mlxsw_sp_port_vp_mode_set(mlxsw_sp_port, false);
623 if (err)
624 return err;
625
626 for_each_set_bit(vid, mlxsw_sp_port->active_vlans, VLAN_N_VID) {
627 err = mlxsw_sp_port_vid_to_fid_set(mlxsw_sp_port, mt, false,
628 vid, vid);
629 if (err)
630 return err;
631 }
632
633 return 0;
634}
635
Ido Schimmel7f71eb42015-12-15 16:03:37 +0100636static struct mlxsw_sp_vfid *
637mlxsw_sp_vfid_find(const struct mlxsw_sp *mlxsw_sp, u16 vid)
638{
639 struct mlxsw_sp_vfid *vfid;
640
641 list_for_each_entry(vfid, &mlxsw_sp->port_vfids.list, list) {
642 if (vfid->vid == vid)
643 return vfid;
644 }
645
646 return NULL;
647}
648
649static u16 mlxsw_sp_avail_vfid_get(const struct mlxsw_sp *mlxsw_sp)
650{
651 return find_first_zero_bit(mlxsw_sp->port_vfids.mapped,
652 MLXSW_SP_VFID_PORT_MAX);
653}
654
Ido Schimmelc7e920b2016-06-20 23:04:09 +0200655static int mlxsw_sp_vfid_op(struct mlxsw_sp *mlxsw_sp, u16 fid, bool create)
Ido Schimmel7f71eb42015-12-15 16:03:37 +0100656{
Ido Schimmel7f71eb42015-12-15 16:03:37 +0100657 char sfmr_pl[MLXSW_REG_SFMR_LEN];
658
Ido Schimmelc7e920b2016-06-20 23:04:09 +0200659 mlxsw_reg_sfmr_pack(sfmr_pl, !create, fid, 0);
Ido Schimmel7f71eb42015-12-15 16:03:37 +0100660 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sfmr), sfmr_pl);
661}
662
Ido Schimmel7f71eb42015-12-15 16:03:37 +0100663static struct mlxsw_sp_vfid *mlxsw_sp_vfid_create(struct mlxsw_sp *mlxsw_sp,
664 u16 vid)
665{
666 struct device *dev = mlxsw_sp->bus_info->dev;
Ido Schimmelc7e920b2016-06-20 23:04:09 +0200667 struct mlxsw_sp_vfid *f;
668 u16 vfid, fid;
Ido Schimmel7f71eb42015-12-15 16:03:37 +0100669 int err;
670
Ido Schimmelc7e920b2016-06-20 23:04:09 +0200671 vfid = mlxsw_sp_avail_vfid_get(mlxsw_sp);
672 if (vfid == MLXSW_SP_VFID_PORT_MAX) {
Ido Schimmel7f71eb42015-12-15 16:03:37 +0100673 dev_err(dev, "No available vFIDs\n");
674 return ERR_PTR(-ERANGE);
675 }
676
Ido Schimmelc7e920b2016-06-20 23:04:09 +0200677 fid = mlxsw_sp_vfid_to_fid(vfid);
678 err = mlxsw_sp_vfid_op(mlxsw_sp, fid, true);
Ido Schimmel7f71eb42015-12-15 16:03:37 +0100679 if (err) {
Ido Schimmelc7e920b2016-06-20 23:04:09 +0200680 dev_err(dev, "Failed to create FID=%d\n", fid);
Ido Schimmel7f71eb42015-12-15 16:03:37 +0100681 return ERR_PTR(err);
682 }
683
Ido Schimmelc7e920b2016-06-20 23:04:09 +0200684 f = kzalloc(sizeof(*f), GFP_KERNEL);
685 if (!f)
Ido Schimmel7f71eb42015-12-15 16:03:37 +0100686 goto err_allocate_vfid;
687
Ido Schimmelc7e920b2016-06-20 23:04:09 +0200688 f->vfid = vfid;
689 f->vid = vid;
Ido Schimmel7f71eb42015-12-15 16:03:37 +0100690
Ido Schimmelc7e920b2016-06-20 23:04:09 +0200691 list_add(&f->list, &mlxsw_sp->port_vfids.list);
692 set_bit(vfid, mlxsw_sp->port_vfids.mapped);
Ido Schimmel7f71eb42015-12-15 16:03:37 +0100693
Ido Schimmelc7e920b2016-06-20 23:04:09 +0200694 return f;
Ido Schimmel7f71eb42015-12-15 16:03:37 +0100695
696err_allocate_vfid:
Ido Schimmelc7e920b2016-06-20 23:04:09 +0200697 mlxsw_sp_vfid_op(mlxsw_sp, fid, false);
Ido Schimmel7f71eb42015-12-15 16:03:37 +0100698 return ERR_PTR(-ENOMEM);
699}
700
701static void mlxsw_sp_vfid_destroy(struct mlxsw_sp *mlxsw_sp,
702 struct mlxsw_sp_vfid *vfid)
703{
Ido Schimmelc7e920b2016-06-20 23:04:09 +0200704 u16 fid = mlxsw_sp_vfid_to_fid(vfid->vfid);
705
Ido Schimmel7f71eb42015-12-15 16:03:37 +0100706 clear_bit(vfid->vfid, mlxsw_sp->port_vfids.mapped);
707 list_del(&vfid->list);
708
Ido Schimmelc7e920b2016-06-20 23:04:09 +0200709 mlxsw_sp_vfid_op(mlxsw_sp, fid, false);
Ido Schimmel7f71eb42015-12-15 16:03:37 +0100710
711 kfree(vfid);
712}
713
714static struct mlxsw_sp_port *
715mlxsw_sp_port_vport_create(struct mlxsw_sp_port *mlxsw_sp_port,
716 struct mlxsw_sp_vfid *vfid)
717{
718 struct mlxsw_sp_port *mlxsw_sp_vport;
719
720 mlxsw_sp_vport = kzalloc(sizeof(*mlxsw_sp_vport), GFP_KERNEL);
721 if (!mlxsw_sp_vport)
722 return NULL;
723
724 /* dev will be set correctly after the VLAN device is linked
725 * with the real device. In case of bridge SELF invocation, dev
726 * will remain as is.
727 */
728 mlxsw_sp_vport->dev = mlxsw_sp_port->dev;
729 mlxsw_sp_vport->mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
730 mlxsw_sp_vport->local_port = mlxsw_sp_port->local_port;
731 mlxsw_sp_vport->stp_state = BR_STATE_FORWARDING;
Ido Schimmel272c4472015-12-15 16:03:47 +0100732 mlxsw_sp_vport->lagged = mlxsw_sp_port->lagged;
733 mlxsw_sp_vport->lag_id = mlxsw_sp_port->lag_id;
Ido Schimmel7f71eb42015-12-15 16:03:37 +0100734 mlxsw_sp_vport->vport.vfid = vfid;
735 mlxsw_sp_vport->vport.vid = vfid->vid;
736
737 list_add(&mlxsw_sp_vport->vport.list, &mlxsw_sp_port->vports_list);
738
739 return mlxsw_sp_vport;
740}
741
742static void mlxsw_sp_port_vport_destroy(struct mlxsw_sp_port *mlxsw_sp_vport)
743{
744 list_del(&mlxsw_sp_vport->vport.list);
745 kfree(mlxsw_sp_vport);
746}
747
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200748int mlxsw_sp_port_add_vid(struct net_device *dev, __be16 __always_unused proto,
749 u16 vid)
750{
751 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
752 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
Ido Schimmel7f71eb42015-12-15 16:03:37 +0100753 struct mlxsw_sp_port *mlxsw_sp_vport;
754 struct mlxsw_sp_vfid *vfid;
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200755 int err;
756
757 /* VLAN 0 is added to HW filter when device goes up, but it is
758 * reserved in our case, so simply return.
759 */
760 if (!vid)
761 return 0;
762
Ido Schimmel7f71eb42015-12-15 16:03:37 +0100763 if (mlxsw_sp_port_vport_find(mlxsw_sp_port, vid)) {
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200764 netdev_warn(dev, "VID=%d already configured\n", vid);
765 return 0;
766 }
767
Ido Schimmel7f71eb42015-12-15 16:03:37 +0100768 vfid = mlxsw_sp_vfid_find(mlxsw_sp, vid);
769 if (!vfid) {
770 vfid = mlxsw_sp_vfid_create(mlxsw_sp, vid);
771 if (IS_ERR(vfid)) {
772 netdev_err(dev, "Failed to create vFID for VID=%d\n",
773 vid);
774 return PTR_ERR(vfid);
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200775 }
776 }
777
Ido Schimmel7f71eb42015-12-15 16:03:37 +0100778 mlxsw_sp_vport = mlxsw_sp_port_vport_create(mlxsw_sp_port, vfid);
779 if (!mlxsw_sp_vport) {
780 netdev_err(dev, "Failed to create vPort for VID=%d\n", vid);
781 err = -ENOMEM;
782 goto err_port_vport_create;
783 }
784
785 if (!vfid->nr_vports) {
786 err = mlxsw_sp_vport_flood_set(mlxsw_sp_vport, vfid->vfid,
Ido Schimmel47a0a9e2016-06-20 23:04:08 +0200787 true);
Ido Schimmel7f71eb42015-12-15 16:03:37 +0100788 if (err) {
789 netdev_err(dev, "Failed to setup flooding for vFID=%d\n",
790 vfid->vfid);
791 goto err_vport_flood_set;
792 }
793 }
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200794
795 /* When adding the first VLAN interface on a bridged port we need to
796 * transition all the active 802.1Q bridge VLANs to use explicit
797 * {Port, VID} to FID mappings and set the port's mode to Virtual mode.
798 */
Ido Schimmel7f71eb42015-12-15 16:03:37 +0100799 if (list_is_singular(&mlxsw_sp_port->vports_list)) {
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200800 err = mlxsw_sp_port_vp_mode_trans(mlxsw_sp_port);
801 if (err) {
802 netdev_err(dev, "Failed to set to Virtual mode\n");
Ido Schimmel7f71eb42015-12-15 16:03:37 +0100803 goto err_port_vp_mode_trans;
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200804 }
805 }
806
Ido Schimmel7f71eb42015-12-15 16:03:37 +0100807 err = mlxsw_sp_port_vid_to_fid_set(mlxsw_sp_vport,
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200808 MLXSW_REG_SVFA_MT_PORT_VID_TO_FID,
Ido Schimmel7f71eb42015-12-15 16:03:37 +0100809 true,
810 mlxsw_sp_vfid_to_fid(vfid->vfid),
811 vid);
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200812 if (err) {
813 netdev_err(dev, "Failed to map {Port, VID=%d} to vFID=%d\n",
Ido Schimmel7f71eb42015-12-15 16:03:37 +0100814 vid, vfid->vfid);
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200815 goto err_port_vid_to_fid_set;
816 }
817
Ido Schimmel7f71eb42015-12-15 16:03:37 +0100818 err = mlxsw_sp_port_vid_learning_set(mlxsw_sp_vport, vid, false);
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200819 if (err) {
820 netdev_err(dev, "Failed to disable learning for VID=%d\n", vid);
821 goto err_port_vid_learning_set;
822 }
823
Ido Schimmel7f71eb42015-12-15 16:03:37 +0100824 err = mlxsw_sp_port_vlan_set(mlxsw_sp_vport, vid, vid, true, false);
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200825 if (err) {
826 netdev_err(dev, "Failed to set VLAN membership for VID=%d\n",
827 vid);
828 goto err_port_add_vid;
829 }
830
Ido Schimmel7f71eb42015-12-15 16:03:37 +0100831 err = mlxsw_sp_port_stp_state_set(mlxsw_sp_vport, vid,
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200832 MLXSW_REG_SPMS_STATE_FORWARDING);
833 if (err) {
834 netdev_err(dev, "Failed to set STP state for VID=%d\n", vid);
835 goto err_port_stp_state_set;
836 }
837
Ido Schimmel7f71eb42015-12-15 16:03:37 +0100838 vfid->nr_vports++;
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200839
840 return 0;
841
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200842err_port_stp_state_set:
Ido Schimmel7f71eb42015-12-15 16:03:37 +0100843 mlxsw_sp_port_vlan_set(mlxsw_sp_vport, vid, vid, false, false);
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200844err_port_add_vid:
Ido Schimmel7f71eb42015-12-15 16:03:37 +0100845 mlxsw_sp_port_vid_learning_set(mlxsw_sp_vport, vid, true);
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200846err_port_vid_learning_set:
Ido Schimmel7f71eb42015-12-15 16:03:37 +0100847 mlxsw_sp_port_vid_to_fid_set(mlxsw_sp_vport,
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200848 MLXSW_REG_SVFA_MT_PORT_VID_TO_FID, false,
Ido Schimmel7f71eb42015-12-15 16:03:37 +0100849 mlxsw_sp_vfid_to_fid(vfid->vfid), vid);
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200850err_port_vid_to_fid_set:
Ido Schimmel7f71eb42015-12-15 16:03:37 +0100851 if (list_is_singular(&mlxsw_sp_port->vports_list))
852 mlxsw_sp_port_vlan_mode_trans(mlxsw_sp_port);
853err_port_vp_mode_trans:
854 if (!vfid->nr_vports)
Ido Schimmel47a0a9e2016-06-20 23:04:08 +0200855 mlxsw_sp_vport_flood_set(mlxsw_sp_vport, vfid->vfid, false);
Ido Schimmel7f71eb42015-12-15 16:03:37 +0100856err_vport_flood_set:
857 mlxsw_sp_port_vport_destroy(mlxsw_sp_vport);
858err_port_vport_create:
859 if (!vfid->nr_vports)
860 mlxsw_sp_vfid_destroy(mlxsw_sp, vfid);
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200861 return err;
862}
863
864int mlxsw_sp_port_kill_vid(struct net_device *dev,
865 __be16 __always_unused proto, u16 vid)
866{
867 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
Ido Schimmel7f71eb42015-12-15 16:03:37 +0100868 struct mlxsw_sp_port *mlxsw_sp_vport;
869 struct mlxsw_sp_vfid *vfid;
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200870 int err;
871
872 /* VLAN 0 is removed from HW filter when device goes down, but
873 * it is reserved in our case, so simply return.
874 */
875 if (!vid)
876 return 0;
877
Ido Schimmel7f71eb42015-12-15 16:03:37 +0100878 mlxsw_sp_vport = mlxsw_sp_port_vport_find(mlxsw_sp_port, vid);
879 if (!mlxsw_sp_vport) {
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200880 netdev_warn(dev, "VID=%d does not exist\n", vid);
881 return 0;
882 }
883
Ido Schimmel7f71eb42015-12-15 16:03:37 +0100884 vfid = mlxsw_sp_vport->vport.vfid;
885
886 err = mlxsw_sp_port_stp_state_set(mlxsw_sp_vport, vid,
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200887 MLXSW_REG_SPMS_STATE_DISCARDING);
888 if (err) {
889 netdev_err(dev, "Failed to set STP state for VID=%d\n", vid);
890 return err;
891 }
892
Ido Schimmel7f71eb42015-12-15 16:03:37 +0100893 err = mlxsw_sp_port_vlan_set(mlxsw_sp_vport, vid, vid, false, false);
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200894 if (err) {
895 netdev_err(dev, "Failed to set VLAN membership for VID=%d\n",
896 vid);
897 return err;
898 }
899
Ido Schimmel7f71eb42015-12-15 16:03:37 +0100900 err = mlxsw_sp_port_vid_learning_set(mlxsw_sp_vport, vid, true);
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200901 if (err) {
902 netdev_err(dev, "Failed to enable learning for VID=%d\n", vid);
903 return err;
904 }
905
Ido Schimmel7f71eb42015-12-15 16:03:37 +0100906 err = mlxsw_sp_port_vid_to_fid_set(mlxsw_sp_vport,
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200907 MLXSW_REG_SVFA_MT_PORT_VID_TO_FID,
Ido Schimmel7f71eb42015-12-15 16:03:37 +0100908 false,
909 mlxsw_sp_vfid_to_fid(vfid->vfid),
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200910 vid);
911 if (err) {
912 netdev_err(dev, "Failed to invalidate {Port, VID=%d} to vFID=%d mapping\n",
Ido Schimmel7f71eb42015-12-15 16:03:37 +0100913 vid, vfid->vfid);
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200914 return err;
915 }
916
917 /* When removing the last VLAN interface on a bridged port we need to
918 * transition all active 802.1Q bridge VLANs to use VID to FID
919 * mappings and set port's mode to VLAN mode.
920 */
Ido Schimmel7f71eb42015-12-15 16:03:37 +0100921 if (list_is_singular(&mlxsw_sp_port->vports_list)) {
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200922 err = mlxsw_sp_port_vlan_mode_trans(mlxsw_sp_port);
923 if (err) {
924 netdev_err(dev, "Failed to set to VLAN mode\n");
925 return err;
926 }
927 }
928
Ido Schimmel7f71eb42015-12-15 16:03:37 +0100929 vfid->nr_vports--;
930 mlxsw_sp_port_vport_destroy(mlxsw_sp_vport);
931
932 /* Destroy the vFID if no vPorts are assigned to it anymore. */
933 if (!vfid->nr_vports)
934 mlxsw_sp_vfid_destroy(mlxsw_sp_port->mlxsw_sp, vfid);
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200935
936 return 0;
937}
938
Ido Schimmel2bf9a582016-04-05 10:20:04 +0200939static int mlxsw_sp_port_get_phys_port_name(struct net_device *dev, char *name,
940 size_t len)
941{
942 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
Ido Schimmeld664b412016-06-09 09:51:40 +0200943 u8 module = mlxsw_sp_port->mapping.module;
944 u8 width = mlxsw_sp_port->mapping.width;
945 u8 lane = mlxsw_sp_port->mapping.lane;
Ido Schimmel2bf9a582016-04-05 10:20:04 +0200946 int err;
947
Ido Schimmel2bf9a582016-04-05 10:20:04 +0200948 if (!mlxsw_sp_port->split)
949 err = snprintf(name, len, "p%d", module + 1);
950 else
951 err = snprintf(name, len, "p%ds%d", module + 1,
952 lane / width);
953
954 if (err >= len)
955 return -EINVAL;
956
957 return 0;
958}
959
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200960static const struct net_device_ops mlxsw_sp_port_netdev_ops = {
961 .ndo_open = mlxsw_sp_port_open,
962 .ndo_stop = mlxsw_sp_port_stop,
963 .ndo_start_xmit = mlxsw_sp_port_xmit,
Jiri Pirkoc5b9b512015-12-03 12:12:22 +0100964 .ndo_set_rx_mode = mlxsw_sp_set_rx_mode,
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200965 .ndo_set_mac_address = mlxsw_sp_port_set_mac_address,
966 .ndo_change_mtu = mlxsw_sp_port_change_mtu,
967 .ndo_get_stats64 = mlxsw_sp_port_get_stats64,
968 .ndo_vlan_rx_add_vid = mlxsw_sp_port_add_vid,
969 .ndo_vlan_rx_kill_vid = mlxsw_sp_port_kill_vid,
970 .ndo_fdb_add = switchdev_port_fdb_add,
971 .ndo_fdb_del = switchdev_port_fdb_del,
972 .ndo_fdb_dump = switchdev_port_fdb_dump,
973 .ndo_bridge_setlink = switchdev_port_bridge_setlink,
974 .ndo_bridge_getlink = switchdev_port_bridge_getlink,
975 .ndo_bridge_dellink = switchdev_port_bridge_dellink,
Ido Schimmel2bf9a582016-04-05 10:20:04 +0200976 .ndo_get_phys_port_name = mlxsw_sp_port_get_phys_port_name,
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200977};
978
979static void mlxsw_sp_port_get_drvinfo(struct net_device *dev,
980 struct ethtool_drvinfo *drvinfo)
981{
982 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
983 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
984
985 strlcpy(drvinfo->driver, mlxsw_sp_driver_name, sizeof(drvinfo->driver));
986 strlcpy(drvinfo->version, mlxsw_sp_driver_version,
987 sizeof(drvinfo->version));
988 snprintf(drvinfo->fw_version, sizeof(drvinfo->fw_version),
989 "%d.%d.%d",
990 mlxsw_sp->bus_info->fw_rev.major,
991 mlxsw_sp->bus_info->fw_rev.minor,
992 mlxsw_sp->bus_info->fw_rev.subminor);
993 strlcpy(drvinfo->bus_info, mlxsw_sp->bus_info->device_name,
994 sizeof(drvinfo->bus_info));
995}
996
Ido Schimmel9f7ec052016-04-06 17:10:14 +0200997static void mlxsw_sp_port_get_pauseparam(struct net_device *dev,
998 struct ethtool_pauseparam *pause)
999{
1000 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1001
1002 pause->rx_pause = mlxsw_sp_port->link.rx_pause;
1003 pause->tx_pause = mlxsw_sp_port->link.tx_pause;
1004}
1005
1006static int mlxsw_sp_port_pause_set(struct mlxsw_sp_port *mlxsw_sp_port,
1007 struct ethtool_pauseparam *pause)
1008{
1009 char pfcc_pl[MLXSW_REG_PFCC_LEN];
1010
1011 mlxsw_reg_pfcc_pack(pfcc_pl, mlxsw_sp_port->local_port);
1012 mlxsw_reg_pfcc_pprx_set(pfcc_pl, pause->rx_pause);
1013 mlxsw_reg_pfcc_pptx_set(pfcc_pl, pause->tx_pause);
1014
1015 return mlxsw_reg_write(mlxsw_sp_port->mlxsw_sp->core, MLXSW_REG(pfcc),
1016 pfcc_pl);
1017}
1018
1019static int mlxsw_sp_port_set_pauseparam(struct net_device *dev,
1020 struct ethtool_pauseparam *pause)
1021{
1022 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1023 bool pause_en = pause->tx_pause || pause->rx_pause;
1024 int err;
1025
Ido Schimmeld81a6bd2016-04-06 17:10:16 +02001026 if (mlxsw_sp_port->dcb.pfc && mlxsw_sp_port->dcb.pfc->pfc_en) {
1027 netdev_err(dev, "PFC already enabled on port\n");
1028 return -EINVAL;
1029 }
1030
Ido Schimmel9f7ec052016-04-06 17:10:14 +02001031 if (pause->autoneg) {
1032 netdev_err(dev, "PAUSE frames autonegotiation isn't supported\n");
1033 return -EINVAL;
1034 }
1035
1036 err = mlxsw_sp_port_headroom_set(mlxsw_sp_port, dev->mtu, pause_en);
1037 if (err) {
1038 netdev_err(dev, "Failed to configure port's headroom\n");
1039 return err;
1040 }
1041
1042 err = mlxsw_sp_port_pause_set(mlxsw_sp_port, pause);
1043 if (err) {
1044 netdev_err(dev, "Failed to set PAUSE parameters\n");
1045 goto err_port_pause_configure;
1046 }
1047
1048 mlxsw_sp_port->link.rx_pause = pause->rx_pause;
1049 mlxsw_sp_port->link.tx_pause = pause->tx_pause;
1050
1051 return 0;
1052
1053err_port_pause_configure:
1054 pause_en = mlxsw_sp_port_is_pause_en(mlxsw_sp_port);
1055 mlxsw_sp_port_headroom_set(mlxsw_sp_port, dev->mtu, pause_en);
1056 return err;
1057}
1058
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001059struct mlxsw_sp_port_hw_stats {
1060 char str[ETH_GSTRING_LEN];
1061 u64 (*getter)(char *payload);
1062};
1063
1064static const struct mlxsw_sp_port_hw_stats mlxsw_sp_port_hw_stats[] = {
1065 {
1066 .str = "a_frames_transmitted_ok",
1067 .getter = mlxsw_reg_ppcnt_a_frames_transmitted_ok_get,
1068 },
1069 {
1070 .str = "a_frames_received_ok",
1071 .getter = mlxsw_reg_ppcnt_a_frames_received_ok_get,
1072 },
1073 {
1074 .str = "a_frame_check_sequence_errors",
1075 .getter = mlxsw_reg_ppcnt_a_frame_check_sequence_errors_get,
1076 },
1077 {
1078 .str = "a_alignment_errors",
1079 .getter = mlxsw_reg_ppcnt_a_alignment_errors_get,
1080 },
1081 {
1082 .str = "a_octets_transmitted_ok",
1083 .getter = mlxsw_reg_ppcnt_a_octets_transmitted_ok_get,
1084 },
1085 {
1086 .str = "a_octets_received_ok",
1087 .getter = mlxsw_reg_ppcnt_a_octets_received_ok_get,
1088 },
1089 {
1090 .str = "a_multicast_frames_xmitted_ok",
1091 .getter = mlxsw_reg_ppcnt_a_multicast_frames_xmitted_ok_get,
1092 },
1093 {
1094 .str = "a_broadcast_frames_xmitted_ok",
1095 .getter = mlxsw_reg_ppcnt_a_broadcast_frames_xmitted_ok_get,
1096 },
1097 {
1098 .str = "a_multicast_frames_received_ok",
1099 .getter = mlxsw_reg_ppcnt_a_multicast_frames_received_ok_get,
1100 },
1101 {
1102 .str = "a_broadcast_frames_received_ok",
1103 .getter = mlxsw_reg_ppcnt_a_broadcast_frames_received_ok_get,
1104 },
1105 {
1106 .str = "a_in_range_length_errors",
1107 .getter = mlxsw_reg_ppcnt_a_in_range_length_errors_get,
1108 },
1109 {
1110 .str = "a_out_of_range_length_field",
1111 .getter = mlxsw_reg_ppcnt_a_out_of_range_length_field_get,
1112 },
1113 {
1114 .str = "a_frame_too_long_errors",
1115 .getter = mlxsw_reg_ppcnt_a_frame_too_long_errors_get,
1116 },
1117 {
1118 .str = "a_symbol_error_during_carrier",
1119 .getter = mlxsw_reg_ppcnt_a_symbol_error_during_carrier_get,
1120 },
1121 {
1122 .str = "a_mac_control_frames_transmitted",
1123 .getter = mlxsw_reg_ppcnt_a_mac_control_frames_transmitted_get,
1124 },
1125 {
1126 .str = "a_mac_control_frames_received",
1127 .getter = mlxsw_reg_ppcnt_a_mac_control_frames_received_get,
1128 },
1129 {
1130 .str = "a_unsupported_opcodes_received",
1131 .getter = mlxsw_reg_ppcnt_a_unsupported_opcodes_received_get,
1132 },
1133 {
1134 .str = "a_pause_mac_ctrl_frames_received",
1135 .getter = mlxsw_reg_ppcnt_a_pause_mac_ctrl_frames_received_get,
1136 },
1137 {
1138 .str = "a_pause_mac_ctrl_frames_xmitted",
1139 .getter = mlxsw_reg_ppcnt_a_pause_mac_ctrl_frames_transmitted_get,
1140 },
1141};
1142
1143#define MLXSW_SP_PORT_HW_STATS_LEN ARRAY_SIZE(mlxsw_sp_port_hw_stats)
1144
1145static void mlxsw_sp_port_get_strings(struct net_device *dev,
1146 u32 stringset, u8 *data)
1147{
1148 u8 *p = data;
1149 int i;
1150
1151 switch (stringset) {
1152 case ETH_SS_STATS:
1153 for (i = 0; i < MLXSW_SP_PORT_HW_STATS_LEN; i++) {
1154 memcpy(p, mlxsw_sp_port_hw_stats[i].str,
1155 ETH_GSTRING_LEN);
1156 p += ETH_GSTRING_LEN;
1157 }
1158 break;
1159 }
1160}
1161
Ido Schimmel3a66ee32015-11-27 13:45:55 +01001162static int mlxsw_sp_port_set_phys_id(struct net_device *dev,
1163 enum ethtool_phys_id_state state)
1164{
1165 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1166 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
1167 char mlcr_pl[MLXSW_REG_MLCR_LEN];
1168 bool active;
1169
1170 switch (state) {
1171 case ETHTOOL_ID_ACTIVE:
1172 active = true;
1173 break;
1174 case ETHTOOL_ID_INACTIVE:
1175 active = false;
1176 break;
1177 default:
1178 return -EOPNOTSUPP;
1179 }
1180
1181 mlxsw_reg_mlcr_pack(mlcr_pl, mlxsw_sp_port->local_port, active);
1182 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mlcr), mlcr_pl);
1183}
1184
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001185static void mlxsw_sp_port_get_stats(struct net_device *dev,
1186 struct ethtool_stats *stats, u64 *data)
1187{
1188 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1189 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
1190 char ppcnt_pl[MLXSW_REG_PPCNT_LEN];
1191 int i;
1192 int err;
1193
Ido Schimmel34dba0a2016-04-06 17:10:15 +02001194 mlxsw_reg_ppcnt_pack(ppcnt_pl, mlxsw_sp_port->local_port,
1195 MLXSW_REG_PPCNT_IEEE_8023_CNT, 0);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001196 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(ppcnt), ppcnt_pl);
1197 for (i = 0; i < MLXSW_SP_PORT_HW_STATS_LEN; i++)
1198 data[i] = !err ? mlxsw_sp_port_hw_stats[i].getter(ppcnt_pl) : 0;
1199}
1200
1201static int mlxsw_sp_port_get_sset_count(struct net_device *dev, int sset)
1202{
1203 switch (sset) {
1204 case ETH_SS_STATS:
1205 return MLXSW_SP_PORT_HW_STATS_LEN;
1206 default:
1207 return -EOPNOTSUPP;
1208 }
1209}
1210
1211struct mlxsw_sp_port_link_mode {
1212 u32 mask;
1213 u32 supported;
1214 u32 advertised;
1215 u32 speed;
1216};
1217
1218static const struct mlxsw_sp_port_link_mode mlxsw_sp_port_link_mode[] = {
1219 {
1220 .mask = MLXSW_REG_PTYS_ETH_SPEED_100BASE_T,
1221 .supported = SUPPORTED_100baseT_Full,
1222 .advertised = ADVERTISED_100baseT_Full,
1223 .speed = 100,
1224 },
1225 {
1226 .mask = MLXSW_REG_PTYS_ETH_SPEED_100BASE_TX,
1227 .speed = 100,
1228 },
1229 {
1230 .mask = MLXSW_REG_PTYS_ETH_SPEED_SGMII |
1231 MLXSW_REG_PTYS_ETH_SPEED_1000BASE_KX,
1232 .supported = SUPPORTED_1000baseKX_Full,
1233 .advertised = ADVERTISED_1000baseKX_Full,
1234 .speed = 1000,
1235 },
1236 {
1237 .mask = MLXSW_REG_PTYS_ETH_SPEED_10GBASE_T,
1238 .supported = SUPPORTED_10000baseT_Full,
1239 .advertised = ADVERTISED_10000baseT_Full,
1240 .speed = 10000,
1241 },
1242 {
1243 .mask = MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CX4 |
1244 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KX4,
1245 .supported = SUPPORTED_10000baseKX4_Full,
1246 .advertised = ADVERTISED_10000baseKX4_Full,
1247 .speed = 10000,
1248 },
1249 {
1250 .mask = MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KR |
1251 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CR |
1252 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_SR |
1253 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_ER_LR,
1254 .supported = SUPPORTED_10000baseKR_Full,
1255 .advertised = ADVERTISED_10000baseKR_Full,
1256 .speed = 10000,
1257 },
1258 {
1259 .mask = MLXSW_REG_PTYS_ETH_SPEED_20GBASE_KR2,
1260 .supported = SUPPORTED_20000baseKR2_Full,
1261 .advertised = ADVERTISED_20000baseKR2_Full,
1262 .speed = 20000,
1263 },
1264 {
1265 .mask = MLXSW_REG_PTYS_ETH_SPEED_40GBASE_CR4,
1266 .supported = SUPPORTED_40000baseCR4_Full,
1267 .advertised = ADVERTISED_40000baseCR4_Full,
1268 .speed = 40000,
1269 },
1270 {
1271 .mask = MLXSW_REG_PTYS_ETH_SPEED_40GBASE_KR4,
1272 .supported = SUPPORTED_40000baseKR4_Full,
1273 .advertised = ADVERTISED_40000baseKR4_Full,
1274 .speed = 40000,
1275 },
1276 {
1277 .mask = MLXSW_REG_PTYS_ETH_SPEED_40GBASE_SR4,
1278 .supported = SUPPORTED_40000baseSR4_Full,
1279 .advertised = ADVERTISED_40000baseSR4_Full,
1280 .speed = 40000,
1281 },
1282 {
1283 .mask = MLXSW_REG_PTYS_ETH_SPEED_40GBASE_LR4_ER4,
1284 .supported = SUPPORTED_40000baseLR4_Full,
1285 .advertised = ADVERTISED_40000baseLR4_Full,
1286 .speed = 40000,
1287 },
1288 {
1289 .mask = MLXSW_REG_PTYS_ETH_SPEED_25GBASE_CR |
1290 MLXSW_REG_PTYS_ETH_SPEED_25GBASE_KR |
1291 MLXSW_REG_PTYS_ETH_SPEED_25GBASE_SR,
1292 .speed = 25000,
1293 },
1294 {
1295 .mask = MLXSW_REG_PTYS_ETH_SPEED_50GBASE_KR4 |
1296 MLXSW_REG_PTYS_ETH_SPEED_50GBASE_CR2 |
1297 MLXSW_REG_PTYS_ETH_SPEED_50GBASE_KR2,
1298 .speed = 50000,
1299 },
1300 {
1301 .mask = MLXSW_REG_PTYS_ETH_SPEED_56GBASE_R4,
1302 .supported = SUPPORTED_56000baseKR4_Full,
1303 .advertised = ADVERTISED_56000baseKR4_Full,
1304 .speed = 56000,
1305 },
1306 {
1307 .mask = MLXSW_REG_PTYS_ETH_SPEED_100GBASE_CR4 |
1308 MLXSW_REG_PTYS_ETH_SPEED_100GBASE_SR4 |
1309 MLXSW_REG_PTYS_ETH_SPEED_100GBASE_KR4 |
1310 MLXSW_REG_PTYS_ETH_SPEED_100GBASE_LR4_ER4,
1311 .speed = 100000,
1312 },
1313};
1314
1315#define MLXSW_SP_PORT_LINK_MODE_LEN ARRAY_SIZE(mlxsw_sp_port_link_mode)
1316
1317static u32 mlxsw_sp_from_ptys_supported_port(u32 ptys_eth_proto)
1318{
1319 if (ptys_eth_proto & (MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CR |
1320 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_SR |
1321 MLXSW_REG_PTYS_ETH_SPEED_40GBASE_CR4 |
1322 MLXSW_REG_PTYS_ETH_SPEED_40GBASE_SR4 |
1323 MLXSW_REG_PTYS_ETH_SPEED_100GBASE_SR4 |
1324 MLXSW_REG_PTYS_ETH_SPEED_SGMII))
1325 return SUPPORTED_FIBRE;
1326
1327 if (ptys_eth_proto & (MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KR |
1328 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KX4 |
1329 MLXSW_REG_PTYS_ETH_SPEED_40GBASE_KR4 |
1330 MLXSW_REG_PTYS_ETH_SPEED_100GBASE_KR4 |
1331 MLXSW_REG_PTYS_ETH_SPEED_1000BASE_KX))
1332 return SUPPORTED_Backplane;
1333 return 0;
1334}
1335
1336static u32 mlxsw_sp_from_ptys_supported_link(u32 ptys_eth_proto)
1337{
1338 u32 modes = 0;
1339 int i;
1340
1341 for (i = 0; i < MLXSW_SP_PORT_LINK_MODE_LEN; i++) {
1342 if (ptys_eth_proto & mlxsw_sp_port_link_mode[i].mask)
1343 modes |= mlxsw_sp_port_link_mode[i].supported;
1344 }
1345 return modes;
1346}
1347
1348static u32 mlxsw_sp_from_ptys_advert_link(u32 ptys_eth_proto)
1349{
1350 u32 modes = 0;
1351 int i;
1352
1353 for (i = 0; i < MLXSW_SP_PORT_LINK_MODE_LEN; i++) {
1354 if (ptys_eth_proto & mlxsw_sp_port_link_mode[i].mask)
1355 modes |= mlxsw_sp_port_link_mode[i].advertised;
1356 }
1357 return modes;
1358}
1359
1360static void mlxsw_sp_from_ptys_speed_duplex(bool carrier_ok, u32 ptys_eth_proto,
1361 struct ethtool_cmd *cmd)
1362{
1363 u32 speed = SPEED_UNKNOWN;
1364 u8 duplex = DUPLEX_UNKNOWN;
1365 int i;
1366
1367 if (!carrier_ok)
1368 goto out;
1369
1370 for (i = 0; i < MLXSW_SP_PORT_LINK_MODE_LEN; i++) {
1371 if (ptys_eth_proto & mlxsw_sp_port_link_mode[i].mask) {
1372 speed = mlxsw_sp_port_link_mode[i].speed;
1373 duplex = DUPLEX_FULL;
1374 break;
1375 }
1376 }
1377out:
1378 ethtool_cmd_speed_set(cmd, speed);
1379 cmd->duplex = duplex;
1380}
1381
1382static u8 mlxsw_sp_port_connector_port(u32 ptys_eth_proto)
1383{
1384 if (ptys_eth_proto & (MLXSW_REG_PTYS_ETH_SPEED_10GBASE_SR |
1385 MLXSW_REG_PTYS_ETH_SPEED_40GBASE_SR4 |
1386 MLXSW_REG_PTYS_ETH_SPEED_100GBASE_SR4 |
1387 MLXSW_REG_PTYS_ETH_SPEED_SGMII))
1388 return PORT_FIBRE;
1389
1390 if (ptys_eth_proto & (MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CR |
1391 MLXSW_REG_PTYS_ETH_SPEED_40GBASE_CR4 |
1392 MLXSW_REG_PTYS_ETH_SPEED_100GBASE_CR4))
1393 return PORT_DA;
1394
1395 if (ptys_eth_proto & (MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KR |
1396 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KX4 |
1397 MLXSW_REG_PTYS_ETH_SPEED_40GBASE_KR4 |
1398 MLXSW_REG_PTYS_ETH_SPEED_100GBASE_KR4))
1399 return PORT_NONE;
1400
1401 return PORT_OTHER;
1402}
1403
1404static int mlxsw_sp_port_get_settings(struct net_device *dev,
1405 struct ethtool_cmd *cmd)
1406{
1407 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1408 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
1409 char ptys_pl[MLXSW_REG_PTYS_LEN];
1410 u32 eth_proto_cap;
1411 u32 eth_proto_admin;
1412 u32 eth_proto_oper;
1413 int err;
1414
1415 mlxsw_reg_ptys_pack(ptys_pl, mlxsw_sp_port->local_port, 0);
1416 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(ptys), ptys_pl);
1417 if (err) {
1418 netdev_err(dev, "Failed to get proto");
1419 return err;
1420 }
1421 mlxsw_reg_ptys_unpack(ptys_pl, &eth_proto_cap,
1422 &eth_proto_admin, &eth_proto_oper);
1423
1424 cmd->supported = mlxsw_sp_from_ptys_supported_port(eth_proto_cap) |
1425 mlxsw_sp_from_ptys_supported_link(eth_proto_cap) |
1426 SUPPORTED_Pause | SUPPORTED_Asym_Pause;
1427 cmd->advertising = mlxsw_sp_from_ptys_advert_link(eth_proto_admin);
1428 mlxsw_sp_from_ptys_speed_duplex(netif_carrier_ok(dev),
1429 eth_proto_oper, cmd);
1430
1431 eth_proto_oper = eth_proto_oper ? eth_proto_oper : eth_proto_cap;
1432 cmd->port = mlxsw_sp_port_connector_port(eth_proto_oper);
1433 cmd->lp_advertising = mlxsw_sp_from_ptys_advert_link(eth_proto_oper);
1434
1435 cmd->transceiver = XCVR_INTERNAL;
1436 return 0;
1437}
1438
1439static u32 mlxsw_sp_to_ptys_advert_link(u32 advertising)
1440{
1441 u32 ptys_proto = 0;
1442 int i;
1443
1444 for (i = 0; i < MLXSW_SP_PORT_LINK_MODE_LEN; i++) {
1445 if (advertising & mlxsw_sp_port_link_mode[i].advertised)
1446 ptys_proto |= mlxsw_sp_port_link_mode[i].mask;
1447 }
1448 return ptys_proto;
1449}
1450
1451static u32 mlxsw_sp_to_ptys_speed(u32 speed)
1452{
1453 u32 ptys_proto = 0;
1454 int i;
1455
1456 for (i = 0; i < MLXSW_SP_PORT_LINK_MODE_LEN; i++) {
1457 if (speed == mlxsw_sp_port_link_mode[i].speed)
1458 ptys_proto |= mlxsw_sp_port_link_mode[i].mask;
1459 }
1460 return ptys_proto;
1461}
1462
Ido Schimmel18f1e702016-02-26 17:32:31 +01001463static u32 mlxsw_sp_to_ptys_upper_speed(u32 upper_speed)
1464{
1465 u32 ptys_proto = 0;
1466 int i;
1467
1468 for (i = 0; i < MLXSW_SP_PORT_LINK_MODE_LEN; i++) {
1469 if (mlxsw_sp_port_link_mode[i].speed <= upper_speed)
1470 ptys_proto |= mlxsw_sp_port_link_mode[i].mask;
1471 }
1472 return ptys_proto;
1473}
1474
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001475static int mlxsw_sp_port_set_settings(struct net_device *dev,
1476 struct ethtool_cmd *cmd)
1477{
1478 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1479 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
1480 char ptys_pl[MLXSW_REG_PTYS_LEN];
1481 u32 speed;
1482 u32 eth_proto_new;
1483 u32 eth_proto_cap;
1484 u32 eth_proto_admin;
1485 bool is_up;
1486 int err;
1487
1488 speed = ethtool_cmd_speed(cmd);
1489
1490 eth_proto_new = cmd->autoneg == AUTONEG_ENABLE ?
1491 mlxsw_sp_to_ptys_advert_link(cmd->advertising) :
1492 mlxsw_sp_to_ptys_speed(speed);
1493
1494 mlxsw_reg_ptys_pack(ptys_pl, mlxsw_sp_port->local_port, 0);
1495 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(ptys), ptys_pl);
1496 if (err) {
1497 netdev_err(dev, "Failed to get proto");
1498 return err;
1499 }
1500 mlxsw_reg_ptys_unpack(ptys_pl, &eth_proto_cap, &eth_proto_admin, NULL);
1501
1502 eth_proto_new = eth_proto_new & eth_proto_cap;
1503 if (!eth_proto_new) {
1504 netdev_err(dev, "Not supported proto admin requested");
1505 return -EINVAL;
1506 }
1507 if (eth_proto_new == eth_proto_admin)
1508 return 0;
1509
1510 mlxsw_reg_ptys_pack(ptys_pl, mlxsw_sp_port->local_port, eth_proto_new);
1511 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(ptys), ptys_pl);
1512 if (err) {
1513 netdev_err(dev, "Failed to set proto admin");
1514 return err;
1515 }
1516
1517 err = mlxsw_sp_port_oper_status_get(mlxsw_sp_port, &is_up);
1518 if (err) {
1519 netdev_err(dev, "Failed to get oper status");
1520 return err;
1521 }
1522 if (!is_up)
1523 return 0;
1524
1525 err = mlxsw_sp_port_admin_status_set(mlxsw_sp_port, false);
1526 if (err) {
1527 netdev_err(dev, "Failed to set admin status");
1528 return err;
1529 }
1530
1531 err = mlxsw_sp_port_admin_status_set(mlxsw_sp_port, true);
1532 if (err) {
1533 netdev_err(dev, "Failed to set admin status");
1534 return err;
1535 }
1536
1537 return 0;
1538}
1539
1540static const struct ethtool_ops mlxsw_sp_port_ethtool_ops = {
1541 .get_drvinfo = mlxsw_sp_port_get_drvinfo,
1542 .get_link = ethtool_op_get_link,
Ido Schimmel9f7ec052016-04-06 17:10:14 +02001543 .get_pauseparam = mlxsw_sp_port_get_pauseparam,
1544 .set_pauseparam = mlxsw_sp_port_set_pauseparam,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001545 .get_strings = mlxsw_sp_port_get_strings,
Ido Schimmel3a66ee32015-11-27 13:45:55 +01001546 .set_phys_id = mlxsw_sp_port_set_phys_id,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001547 .get_ethtool_stats = mlxsw_sp_port_get_stats,
1548 .get_sset_count = mlxsw_sp_port_get_sset_count,
1549 .get_settings = mlxsw_sp_port_get_settings,
1550 .set_settings = mlxsw_sp_port_set_settings,
1551};
1552
Ido Schimmel18f1e702016-02-26 17:32:31 +01001553static int
1554mlxsw_sp_port_speed_by_width_set(struct mlxsw_sp_port *mlxsw_sp_port, u8 width)
1555{
1556 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
1557 u32 upper_speed = MLXSW_SP_PORT_BASE_SPEED * width;
1558 char ptys_pl[MLXSW_REG_PTYS_LEN];
1559 u32 eth_proto_admin;
1560
1561 eth_proto_admin = mlxsw_sp_to_ptys_upper_speed(upper_speed);
1562 mlxsw_reg_ptys_pack(ptys_pl, mlxsw_sp_port->local_port,
1563 eth_proto_admin);
1564 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(ptys), ptys_pl);
1565}
1566
Ido Schimmel8e8dfe92016-04-06 17:10:10 +02001567int mlxsw_sp_port_ets_set(struct mlxsw_sp_port *mlxsw_sp_port,
1568 enum mlxsw_reg_qeec_hr hr, u8 index, u8 next_index,
1569 bool dwrr, u8 dwrr_weight)
Ido Schimmel90183b92016-04-06 17:10:08 +02001570{
1571 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
1572 char qeec_pl[MLXSW_REG_QEEC_LEN];
1573
1574 mlxsw_reg_qeec_pack(qeec_pl, mlxsw_sp_port->local_port, hr, index,
1575 next_index);
1576 mlxsw_reg_qeec_de_set(qeec_pl, true);
1577 mlxsw_reg_qeec_dwrr_set(qeec_pl, dwrr);
1578 mlxsw_reg_qeec_dwrr_weight_set(qeec_pl, dwrr_weight);
1579 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(qeec), qeec_pl);
1580}
1581
Ido Schimmelcc7cf512016-04-06 17:10:11 +02001582int mlxsw_sp_port_ets_maxrate_set(struct mlxsw_sp_port *mlxsw_sp_port,
1583 enum mlxsw_reg_qeec_hr hr, u8 index,
1584 u8 next_index, u32 maxrate)
Ido Schimmel90183b92016-04-06 17:10:08 +02001585{
1586 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
1587 char qeec_pl[MLXSW_REG_QEEC_LEN];
1588
1589 mlxsw_reg_qeec_pack(qeec_pl, mlxsw_sp_port->local_port, hr, index,
1590 next_index);
1591 mlxsw_reg_qeec_mase_set(qeec_pl, true);
1592 mlxsw_reg_qeec_max_shaper_rate_set(qeec_pl, maxrate);
1593 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(qeec), qeec_pl);
1594}
1595
Ido Schimmel8e8dfe92016-04-06 17:10:10 +02001596int mlxsw_sp_port_prio_tc_set(struct mlxsw_sp_port *mlxsw_sp_port,
1597 u8 switch_prio, u8 tclass)
Ido Schimmel90183b92016-04-06 17:10:08 +02001598{
1599 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
1600 char qtct_pl[MLXSW_REG_QTCT_LEN];
1601
1602 mlxsw_reg_qtct_pack(qtct_pl, mlxsw_sp_port->local_port, switch_prio,
1603 tclass);
1604 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(qtct), qtct_pl);
1605}
1606
1607static int mlxsw_sp_port_ets_init(struct mlxsw_sp_port *mlxsw_sp_port)
1608{
1609 int err, i;
1610
1611 /* Setup the elements hierarcy, so that each TC is linked to
1612 * one subgroup, which are all member in the same group.
1613 */
1614 err = mlxsw_sp_port_ets_set(mlxsw_sp_port,
1615 MLXSW_REG_QEEC_HIERARCY_GROUP, 0, 0, false,
1616 0);
1617 if (err)
1618 return err;
1619 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
1620 err = mlxsw_sp_port_ets_set(mlxsw_sp_port,
1621 MLXSW_REG_QEEC_HIERARCY_SUBGROUP, i,
1622 0, false, 0);
1623 if (err)
1624 return err;
1625 }
1626 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
1627 err = mlxsw_sp_port_ets_set(mlxsw_sp_port,
1628 MLXSW_REG_QEEC_HIERARCY_TC, i, i,
1629 false, 0);
1630 if (err)
1631 return err;
1632 }
1633
1634 /* Make sure the max shaper is disabled in all hierarcies that
1635 * support it.
1636 */
1637 err = mlxsw_sp_port_ets_maxrate_set(mlxsw_sp_port,
1638 MLXSW_REG_QEEC_HIERARCY_PORT, 0, 0,
1639 MLXSW_REG_QEEC_MAS_DIS);
1640 if (err)
1641 return err;
1642 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
1643 err = mlxsw_sp_port_ets_maxrate_set(mlxsw_sp_port,
1644 MLXSW_REG_QEEC_HIERARCY_SUBGROUP,
1645 i, 0,
1646 MLXSW_REG_QEEC_MAS_DIS);
1647 if (err)
1648 return err;
1649 }
1650 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
1651 err = mlxsw_sp_port_ets_maxrate_set(mlxsw_sp_port,
1652 MLXSW_REG_QEEC_HIERARCY_TC,
1653 i, i,
1654 MLXSW_REG_QEEC_MAS_DIS);
1655 if (err)
1656 return err;
1657 }
1658
1659 /* Map all priorities to traffic class 0. */
1660 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
1661 err = mlxsw_sp_port_prio_tc_set(mlxsw_sp_port, i, 0);
1662 if (err)
1663 return err;
1664 }
1665
1666 return 0;
1667}
1668
Ido Schimmelbe945352016-06-09 09:51:39 +02001669static int mlxsw_sp_port_create(struct mlxsw_sp *mlxsw_sp, u8 local_port,
Ido Schimmeld664b412016-06-09 09:51:40 +02001670 bool split, u8 module, u8 width, u8 lane)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001671{
1672 struct mlxsw_sp_port *mlxsw_sp_port;
1673 struct net_device *dev;
Ido Schimmelbd40e9d2015-12-15 16:03:36 +01001674 size_t bytes;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001675 int err;
1676
1677 dev = alloc_etherdev(sizeof(struct mlxsw_sp_port));
1678 if (!dev)
1679 return -ENOMEM;
1680 mlxsw_sp_port = netdev_priv(dev);
1681 mlxsw_sp_port->dev = dev;
1682 mlxsw_sp_port->mlxsw_sp = mlxsw_sp;
1683 mlxsw_sp_port->local_port = local_port;
Ido Schimmel18f1e702016-02-26 17:32:31 +01001684 mlxsw_sp_port->split = split;
Ido Schimmeld664b412016-06-09 09:51:40 +02001685 mlxsw_sp_port->mapping.module = module;
1686 mlxsw_sp_port->mapping.width = width;
1687 mlxsw_sp_port->mapping.lane = lane;
Ido Schimmelbd40e9d2015-12-15 16:03:36 +01001688 bytes = DIV_ROUND_UP(VLAN_N_VID, BITS_PER_BYTE);
1689 mlxsw_sp_port->active_vlans = kzalloc(bytes, GFP_KERNEL);
1690 if (!mlxsw_sp_port->active_vlans) {
1691 err = -ENOMEM;
1692 goto err_port_active_vlans_alloc;
1693 }
Elad Razfc1273a2016-01-06 13:01:11 +01001694 mlxsw_sp_port->untagged_vlans = kzalloc(bytes, GFP_KERNEL);
1695 if (!mlxsw_sp_port->untagged_vlans) {
1696 err = -ENOMEM;
1697 goto err_port_untagged_vlans_alloc;
1698 }
Ido Schimmel7f71eb42015-12-15 16:03:37 +01001699 INIT_LIST_HEAD(&mlxsw_sp_port->vports_list);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001700
1701 mlxsw_sp_port->pcpu_stats =
1702 netdev_alloc_pcpu_stats(struct mlxsw_sp_port_pcpu_stats);
1703 if (!mlxsw_sp_port->pcpu_stats) {
1704 err = -ENOMEM;
1705 goto err_alloc_stats;
1706 }
1707
1708 dev->netdev_ops = &mlxsw_sp_port_netdev_ops;
1709 dev->ethtool_ops = &mlxsw_sp_port_ethtool_ops;
1710
1711 err = mlxsw_sp_port_dev_addr_init(mlxsw_sp_port);
1712 if (err) {
1713 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Unable to init port mac address\n",
1714 mlxsw_sp_port->local_port);
1715 goto err_dev_addr_init;
1716 }
1717
1718 netif_carrier_off(dev);
1719
1720 dev->features |= NETIF_F_NETNS_LOCAL | NETIF_F_LLTX | NETIF_F_SG |
1721 NETIF_F_HW_VLAN_CTAG_FILTER;
1722
1723 /* Each packet needs to have a Tx header (metadata) on top all other
1724 * headers.
1725 */
1726 dev->hard_header_len += MLXSW_TXHDR_LEN;
1727
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001728 err = mlxsw_sp_port_system_port_mapping_set(mlxsw_sp_port);
1729 if (err) {
1730 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to set system port mapping\n",
1731 mlxsw_sp_port->local_port);
1732 goto err_port_system_port_mapping_set;
1733 }
1734
1735 err = mlxsw_sp_port_swid_set(mlxsw_sp_port, 0);
1736 if (err) {
1737 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to set SWID\n",
1738 mlxsw_sp_port->local_port);
1739 goto err_port_swid_set;
1740 }
1741
Ido Schimmel18f1e702016-02-26 17:32:31 +01001742 err = mlxsw_sp_port_speed_by_width_set(mlxsw_sp_port, width);
1743 if (err) {
1744 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to enable speeds\n",
1745 mlxsw_sp_port->local_port);
1746 goto err_port_speed_by_width_set;
1747 }
1748
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001749 err = mlxsw_sp_port_mtu_set(mlxsw_sp_port, ETH_DATA_LEN);
1750 if (err) {
1751 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to set MTU\n",
1752 mlxsw_sp_port->local_port);
1753 goto err_port_mtu_set;
1754 }
1755
1756 err = mlxsw_sp_port_admin_status_set(mlxsw_sp_port, false);
1757 if (err)
1758 goto err_port_admin_status_set;
1759
1760 err = mlxsw_sp_port_buffers_init(mlxsw_sp_port);
1761 if (err) {
1762 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to initialize buffers\n",
1763 mlxsw_sp_port->local_port);
1764 goto err_port_buffers_init;
1765 }
1766
Ido Schimmel90183b92016-04-06 17:10:08 +02001767 err = mlxsw_sp_port_ets_init(mlxsw_sp_port);
1768 if (err) {
1769 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to initialize ETS\n",
1770 mlxsw_sp_port->local_port);
1771 goto err_port_ets_init;
1772 }
1773
Ido Schimmelf00817d2016-04-06 17:10:09 +02001774 /* ETS and buffers must be initialized before DCB. */
1775 err = mlxsw_sp_port_dcb_init(mlxsw_sp_port);
1776 if (err) {
1777 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to initialize DCB\n",
1778 mlxsw_sp_port->local_port);
1779 goto err_port_dcb_init;
1780 }
1781
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001782 mlxsw_sp_port_switchdev_init(mlxsw_sp_port);
1783 err = register_netdev(dev);
1784 if (err) {
1785 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to register netdev\n",
1786 mlxsw_sp_port->local_port);
1787 goto err_register_netdev;
1788 }
1789
Jiri Pirko932762b2016-04-08 19:11:21 +02001790 err = mlxsw_core_port_init(mlxsw_sp->core, &mlxsw_sp_port->core_port,
1791 mlxsw_sp_port->local_port, dev,
1792 mlxsw_sp_port->split, module);
1793 if (err) {
1794 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to init core port\n",
1795 mlxsw_sp_port->local_port);
1796 goto err_core_port_init;
1797 }
Jiri Pirkoc4745502016-02-26 17:32:26 +01001798
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001799 err = mlxsw_sp_port_vlan_init(mlxsw_sp_port);
1800 if (err)
1801 goto err_port_vlan_init;
1802
1803 mlxsw_sp->ports[local_port] = mlxsw_sp_port;
1804 return 0;
1805
1806err_port_vlan_init:
Jiri Pirko932762b2016-04-08 19:11:21 +02001807 mlxsw_core_port_fini(&mlxsw_sp_port->core_port);
1808err_core_port_init:
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001809 unregister_netdev(dev);
1810err_register_netdev:
Ido Schimmelf00817d2016-04-06 17:10:09 +02001811err_port_dcb_init:
Ido Schimmel90183b92016-04-06 17:10:08 +02001812err_port_ets_init:
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001813err_port_buffers_init:
1814err_port_admin_status_set:
1815err_port_mtu_set:
Ido Schimmel18f1e702016-02-26 17:32:31 +01001816err_port_speed_by_width_set:
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001817err_port_swid_set:
1818err_port_system_port_mapping_set:
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001819err_dev_addr_init:
1820 free_percpu(mlxsw_sp_port->pcpu_stats);
1821err_alloc_stats:
Elad Razfc1273a2016-01-06 13:01:11 +01001822 kfree(mlxsw_sp_port->untagged_vlans);
1823err_port_untagged_vlans_alloc:
Ido Schimmelbd40e9d2015-12-15 16:03:36 +01001824 kfree(mlxsw_sp_port->active_vlans);
1825err_port_active_vlans_alloc:
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001826 free_netdev(dev);
1827 return err;
1828}
1829
Ido Schimmel7f71eb42015-12-15 16:03:37 +01001830static void mlxsw_sp_port_vports_fini(struct mlxsw_sp_port *mlxsw_sp_port)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001831{
Ido Schimmel7f71eb42015-12-15 16:03:37 +01001832 struct net_device *dev = mlxsw_sp_port->dev;
1833 struct mlxsw_sp_port *mlxsw_sp_vport, *tmp;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001834
Ido Schimmel7f71eb42015-12-15 16:03:37 +01001835 list_for_each_entry_safe(mlxsw_sp_vport, tmp,
1836 &mlxsw_sp_port->vports_list, vport.list) {
1837 u16 vid = mlxsw_sp_vport_vid_get(mlxsw_sp_vport);
1838
1839 /* vPorts created for VLAN devices should already be gone
1840 * by now, since we unregistered the port netdev.
1841 */
1842 WARN_ON(is_vlan_dev(mlxsw_sp_vport->dev));
1843 mlxsw_sp_port_kill_vid(dev, 0, vid);
1844 }
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001845}
1846
1847static void mlxsw_sp_port_remove(struct mlxsw_sp *mlxsw_sp, u8 local_port)
1848{
1849 struct mlxsw_sp_port *mlxsw_sp_port = mlxsw_sp->ports[local_port];
1850
1851 if (!mlxsw_sp_port)
1852 return;
Ido Schimmela1333182016-02-26 17:32:30 +01001853 mlxsw_sp->ports[local_port] = NULL;
Jiri Pirko932762b2016-04-08 19:11:21 +02001854 mlxsw_core_port_fini(&mlxsw_sp_port->core_port);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001855 unregister_netdev(mlxsw_sp_port->dev); /* This calls ndo_stop */
Ido Schimmelf00817d2016-04-06 17:10:09 +02001856 mlxsw_sp_port_dcb_fini(mlxsw_sp_port);
Ido Schimmel7f71eb42015-12-15 16:03:37 +01001857 mlxsw_sp_port_vports_fini(mlxsw_sp_port);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001858 mlxsw_sp_port_switchdev_fini(mlxsw_sp_port);
Ido Schimmel3e9b27b2016-02-26 17:32:28 +01001859 mlxsw_sp_port_swid_set(mlxsw_sp_port, MLXSW_PORT_SWID_DISABLED_PORT);
1860 mlxsw_sp_port_module_unmap(mlxsw_sp, mlxsw_sp_port->local_port);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001861 free_percpu(mlxsw_sp_port->pcpu_stats);
Elad Razfc1273a2016-01-06 13:01:11 +01001862 kfree(mlxsw_sp_port->untagged_vlans);
Ido Schimmelbd40e9d2015-12-15 16:03:36 +01001863 kfree(mlxsw_sp_port->active_vlans);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001864 free_netdev(mlxsw_sp_port->dev);
1865}
1866
1867static void mlxsw_sp_ports_remove(struct mlxsw_sp *mlxsw_sp)
1868{
1869 int i;
1870
1871 for (i = 1; i < MLXSW_PORT_MAX_PORTS; i++)
1872 mlxsw_sp_port_remove(mlxsw_sp, i);
1873 kfree(mlxsw_sp->ports);
1874}
1875
1876static int mlxsw_sp_ports_create(struct mlxsw_sp *mlxsw_sp)
1877{
Ido Schimmeld664b412016-06-09 09:51:40 +02001878 u8 module, width, lane;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001879 size_t alloc_size;
1880 int i;
1881 int err;
1882
1883 alloc_size = sizeof(struct mlxsw_sp_port *) * MLXSW_PORT_MAX_PORTS;
1884 mlxsw_sp->ports = kzalloc(alloc_size, GFP_KERNEL);
1885 if (!mlxsw_sp->ports)
1886 return -ENOMEM;
1887
1888 for (i = 1; i < MLXSW_PORT_MAX_PORTS; i++) {
Ido Schimmel558c2d52016-02-26 17:32:29 +01001889 err = mlxsw_sp_port_module_info_get(mlxsw_sp, i, &module,
Ido Schimmeld664b412016-06-09 09:51:40 +02001890 &width, &lane);
Ido Schimmel558c2d52016-02-26 17:32:29 +01001891 if (err)
1892 goto err_port_module_info_get;
1893 if (!width)
1894 continue;
1895 mlxsw_sp->port_to_module[i] = module;
Ido Schimmeld664b412016-06-09 09:51:40 +02001896 err = mlxsw_sp_port_create(mlxsw_sp, i, false, module, width,
1897 lane);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001898 if (err)
1899 goto err_port_create;
1900 }
1901 return 0;
1902
1903err_port_create:
Ido Schimmel558c2d52016-02-26 17:32:29 +01001904err_port_module_info_get:
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001905 for (i--; i >= 1; i--)
1906 mlxsw_sp_port_remove(mlxsw_sp, i);
1907 kfree(mlxsw_sp->ports);
1908 return err;
1909}
1910
Ido Schimmel18f1e702016-02-26 17:32:31 +01001911static u8 mlxsw_sp_cluster_base_port_get(u8 local_port)
1912{
1913 u8 offset = (local_port - 1) % MLXSW_SP_PORTS_PER_CLUSTER_MAX;
1914
1915 return local_port - offset;
1916}
1917
Ido Schimmelbe945352016-06-09 09:51:39 +02001918static int mlxsw_sp_port_split_create(struct mlxsw_sp *mlxsw_sp, u8 base_port,
1919 u8 module, unsigned int count)
1920{
1921 u8 width = MLXSW_PORT_MODULE_MAX_WIDTH / count;
1922 int err, i;
1923
1924 for (i = 0; i < count; i++) {
1925 err = mlxsw_sp_port_module_map(mlxsw_sp, base_port + i, module,
1926 width, i * width);
1927 if (err)
1928 goto err_port_module_map;
1929 }
1930
1931 for (i = 0; i < count; i++) {
1932 err = __mlxsw_sp_port_swid_set(mlxsw_sp, base_port + i, 0);
1933 if (err)
1934 goto err_port_swid_set;
1935 }
1936
1937 for (i = 0; i < count; i++) {
1938 err = mlxsw_sp_port_create(mlxsw_sp, base_port + i, true,
Ido Schimmeld664b412016-06-09 09:51:40 +02001939 module, width, i * width);
Ido Schimmelbe945352016-06-09 09:51:39 +02001940 if (err)
1941 goto err_port_create;
1942 }
1943
1944 return 0;
1945
1946err_port_create:
1947 for (i--; i >= 0; i--)
1948 mlxsw_sp_port_remove(mlxsw_sp, base_port + i);
1949 i = count;
1950err_port_swid_set:
1951 for (i--; i >= 0; i--)
1952 __mlxsw_sp_port_swid_set(mlxsw_sp, base_port + i,
1953 MLXSW_PORT_SWID_DISABLED_PORT);
1954 i = count;
1955err_port_module_map:
1956 for (i--; i >= 0; i--)
1957 mlxsw_sp_port_module_unmap(mlxsw_sp, base_port + i);
1958 return err;
1959}
1960
1961static void mlxsw_sp_port_unsplit_create(struct mlxsw_sp *mlxsw_sp,
1962 u8 base_port, unsigned int count)
1963{
1964 u8 local_port, module, width = MLXSW_PORT_MODULE_MAX_WIDTH;
1965 int i;
1966
1967 /* Split by four means we need to re-create two ports, otherwise
1968 * only one.
1969 */
1970 count = count / 2;
1971
1972 for (i = 0; i < count; i++) {
1973 local_port = base_port + i * 2;
1974 module = mlxsw_sp->port_to_module[local_port];
1975
1976 mlxsw_sp_port_module_map(mlxsw_sp, local_port, module, width,
1977 0);
1978 }
1979
1980 for (i = 0; i < count; i++)
1981 __mlxsw_sp_port_swid_set(mlxsw_sp, base_port + i * 2, 0);
1982
1983 for (i = 0; i < count; i++) {
1984 local_port = base_port + i * 2;
1985 module = mlxsw_sp->port_to_module[local_port];
1986
1987 mlxsw_sp_port_create(mlxsw_sp, local_port, false, module,
Ido Schimmeld664b412016-06-09 09:51:40 +02001988 width, 0);
Ido Schimmelbe945352016-06-09 09:51:39 +02001989 }
1990}
1991
Jiri Pirkob2f10572016-04-08 19:11:23 +02001992static int mlxsw_sp_port_split(struct mlxsw_core *mlxsw_core, u8 local_port,
1993 unsigned int count)
Ido Schimmel18f1e702016-02-26 17:32:31 +01001994{
Jiri Pirkob2f10572016-04-08 19:11:23 +02001995 struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core);
Ido Schimmel18f1e702016-02-26 17:32:31 +01001996 struct mlxsw_sp_port *mlxsw_sp_port;
Ido Schimmel18f1e702016-02-26 17:32:31 +01001997 u8 module, cur_width, base_port;
1998 int i;
1999 int err;
2000
2001 mlxsw_sp_port = mlxsw_sp->ports[local_port];
2002 if (!mlxsw_sp_port) {
2003 dev_err(mlxsw_sp->bus_info->dev, "Port number \"%d\" does not exist\n",
2004 local_port);
2005 return -EINVAL;
2006 }
2007
Ido Schimmeld664b412016-06-09 09:51:40 +02002008 module = mlxsw_sp_port->mapping.module;
2009 cur_width = mlxsw_sp_port->mapping.width;
2010
Ido Schimmel18f1e702016-02-26 17:32:31 +01002011 if (count != 2 && count != 4) {
2012 netdev_err(mlxsw_sp_port->dev, "Port can only be split into 2 or 4 ports\n");
2013 return -EINVAL;
2014 }
2015
Ido Schimmel18f1e702016-02-26 17:32:31 +01002016 if (cur_width != MLXSW_PORT_MODULE_MAX_WIDTH) {
2017 netdev_err(mlxsw_sp_port->dev, "Port cannot be split further\n");
2018 return -EINVAL;
2019 }
2020
2021 /* Make sure we have enough slave (even) ports for the split. */
2022 if (count == 2) {
2023 base_port = local_port;
2024 if (mlxsw_sp->ports[base_port + 1]) {
2025 netdev_err(mlxsw_sp_port->dev, "Invalid split configuration\n");
2026 return -EINVAL;
2027 }
2028 } else {
2029 base_port = mlxsw_sp_cluster_base_port_get(local_port);
2030 if (mlxsw_sp->ports[base_port + 1] ||
2031 mlxsw_sp->ports[base_port + 3]) {
2032 netdev_err(mlxsw_sp_port->dev, "Invalid split configuration\n");
2033 return -EINVAL;
2034 }
2035 }
2036
2037 for (i = 0; i < count; i++)
2038 mlxsw_sp_port_remove(mlxsw_sp, base_port + i);
2039
Ido Schimmelbe945352016-06-09 09:51:39 +02002040 err = mlxsw_sp_port_split_create(mlxsw_sp, base_port, module, count);
2041 if (err) {
2042 dev_err(mlxsw_sp->bus_info->dev, "Failed to create split ports\n");
2043 goto err_port_split_create;
Ido Schimmel18f1e702016-02-26 17:32:31 +01002044 }
2045
2046 return 0;
2047
Ido Schimmelbe945352016-06-09 09:51:39 +02002048err_port_split_create:
2049 mlxsw_sp_port_unsplit_create(mlxsw_sp, base_port, count);
Ido Schimmel18f1e702016-02-26 17:32:31 +01002050 return err;
2051}
2052
Jiri Pirkob2f10572016-04-08 19:11:23 +02002053static int mlxsw_sp_port_unsplit(struct mlxsw_core *mlxsw_core, u8 local_port)
Ido Schimmel18f1e702016-02-26 17:32:31 +01002054{
Jiri Pirkob2f10572016-04-08 19:11:23 +02002055 struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core);
Ido Schimmel18f1e702016-02-26 17:32:31 +01002056 struct mlxsw_sp_port *mlxsw_sp_port;
Ido Schimmeld664b412016-06-09 09:51:40 +02002057 u8 cur_width, base_port;
Ido Schimmel18f1e702016-02-26 17:32:31 +01002058 unsigned int count;
2059 int i;
Ido Schimmel18f1e702016-02-26 17:32:31 +01002060
2061 mlxsw_sp_port = mlxsw_sp->ports[local_port];
2062 if (!mlxsw_sp_port) {
2063 dev_err(mlxsw_sp->bus_info->dev, "Port number \"%d\" does not exist\n",
2064 local_port);
2065 return -EINVAL;
2066 }
2067
2068 if (!mlxsw_sp_port->split) {
2069 netdev_err(mlxsw_sp_port->dev, "Port wasn't split\n");
2070 return -EINVAL;
2071 }
2072
Ido Schimmeld664b412016-06-09 09:51:40 +02002073 cur_width = mlxsw_sp_port->mapping.width;
Ido Schimmel18f1e702016-02-26 17:32:31 +01002074 count = cur_width == 1 ? 4 : 2;
2075
2076 base_port = mlxsw_sp_cluster_base_port_get(local_port);
2077
2078 /* Determine which ports to remove. */
2079 if (count == 2 && local_port >= base_port + 2)
2080 base_port = base_port + 2;
2081
2082 for (i = 0; i < count; i++)
2083 mlxsw_sp_port_remove(mlxsw_sp, base_port + i);
2084
Ido Schimmelbe945352016-06-09 09:51:39 +02002085 mlxsw_sp_port_unsplit_create(mlxsw_sp, base_port, count);
Ido Schimmel18f1e702016-02-26 17:32:31 +01002086
2087 return 0;
2088}
2089
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002090static void mlxsw_sp_pude_event_func(const struct mlxsw_reg_info *reg,
2091 char *pude_pl, void *priv)
2092{
2093 struct mlxsw_sp *mlxsw_sp = priv;
2094 struct mlxsw_sp_port *mlxsw_sp_port;
2095 enum mlxsw_reg_pude_oper_status status;
2096 u8 local_port;
2097
2098 local_port = mlxsw_reg_pude_local_port_get(pude_pl);
2099 mlxsw_sp_port = mlxsw_sp->ports[local_port];
2100 if (!mlxsw_sp_port) {
2101 dev_warn(mlxsw_sp->bus_info->dev, "Port %d: Link event received for non-existent port\n",
2102 local_port);
2103 return;
2104 }
2105
2106 status = mlxsw_reg_pude_oper_status_get(pude_pl);
2107 if (status == MLXSW_PORT_OPER_STATUS_UP) {
2108 netdev_info(mlxsw_sp_port->dev, "link up\n");
2109 netif_carrier_on(mlxsw_sp_port->dev);
2110 } else {
2111 netdev_info(mlxsw_sp_port->dev, "link down\n");
2112 netif_carrier_off(mlxsw_sp_port->dev);
2113 }
2114}
2115
2116static struct mlxsw_event_listener mlxsw_sp_pude_event = {
2117 .func = mlxsw_sp_pude_event_func,
2118 .trap_id = MLXSW_TRAP_ID_PUDE,
2119};
2120
2121static int mlxsw_sp_event_register(struct mlxsw_sp *mlxsw_sp,
2122 enum mlxsw_event_trap_id trap_id)
2123{
2124 struct mlxsw_event_listener *el;
2125 char hpkt_pl[MLXSW_REG_HPKT_LEN];
2126 int err;
2127
2128 switch (trap_id) {
2129 case MLXSW_TRAP_ID_PUDE:
2130 el = &mlxsw_sp_pude_event;
2131 break;
2132 }
2133 err = mlxsw_core_event_listener_register(mlxsw_sp->core, el, mlxsw_sp);
2134 if (err)
2135 return err;
2136
2137 mlxsw_reg_hpkt_pack(hpkt_pl, MLXSW_REG_HPKT_ACTION_FORWARD, trap_id);
2138 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(hpkt), hpkt_pl);
2139 if (err)
2140 goto err_event_trap_set;
2141
2142 return 0;
2143
2144err_event_trap_set:
2145 mlxsw_core_event_listener_unregister(mlxsw_sp->core, el, mlxsw_sp);
2146 return err;
2147}
2148
2149static void mlxsw_sp_event_unregister(struct mlxsw_sp *mlxsw_sp,
2150 enum mlxsw_event_trap_id trap_id)
2151{
2152 struct mlxsw_event_listener *el;
2153
2154 switch (trap_id) {
2155 case MLXSW_TRAP_ID_PUDE:
2156 el = &mlxsw_sp_pude_event;
2157 break;
2158 }
2159 mlxsw_core_event_listener_unregister(mlxsw_sp->core, el, mlxsw_sp);
2160}
2161
2162static void mlxsw_sp_rx_listener_func(struct sk_buff *skb, u8 local_port,
2163 void *priv)
2164{
2165 struct mlxsw_sp *mlxsw_sp = priv;
2166 struct mlxsw_sp_port *mlxsw_sp_port = mlxsw_sp->ports[local_port];
2167 struct mlxsw_sp_port_pcpu_stats *pcpu_stats;
2168
2169 if (unlikely(!mlxsw_sp_port)) {
2170 dev_warn_ratelimited(mlxsw_sp->bus_info->dev, "Port %d: skb received for non-existent port\n",
2171 local_port);
2172 return;
2173 }
2174
2175 skb->dev = mlxsw_sp_port->dev;
2176
2177 pcpu_stats = this_cpu_ptr(mlxsw_sp_port->pcpu_stats);
2178 u64_stats_update_begin(&pcpu_stats->syncp);
2179 pcpu_stats->rx_packets++;
2180 pcpu_stats->rx_bytes += skb->len;
2181 u64_stats_update_end(&pcpu_stats->syncp);
2182
2183 skb->protocol = eth_type_trans(skb, skb->dev);
2184 netif_receive_skb(skb);
2185}
2186
2187static const struct mlxsw_rx_listener mlxsw_sp_rx_listener[] = {
2188 {
2189 .func = mlxsw_sp_rx_listener_func,
2190 .local_port = MLXSW_PORT_DONT_CARE,
2191 .trap_id = MLXSW_TRAP_ID_FDB_MC,
2192 },
2193 /* Traps for specific L2 packet types, not trapped as FDB MC */
2194 {
2195 .func = mlxsw_sp_rx_listener_func,
2196 .local_port = MLXSW_PORT_DONT_CARE,
2197 .trap_id = MLXSW_TRAP_ID_STP,
2198 },
2199 {
2200 .func = mlxsw_sp_rx_listener_func,
2201 .local_port = MLXSW_PORT_DONT_CARE,
2202 .trap_id = MLXSW_TRAP_ID_LACP,
2203 },
2204 {
2205 .func = mlxsw_sp_rx_listener_func,
2206 .local_port = MLXSW_PORT_DONT_CARE,
2207 .trap_id = MLXSW_TRAP_ID_EAPOL,
2208 },
2209 {
2210 .func = mlxsw_sp_rx_listener_func,
2211 .local_port = MLXSW_PORT_DONT_CARE,
2212 .trap_id = MLXSW_TRAP_ID_LLDP,
2213 },
2214 {
2215 .func = mlxsw_sp_rx_listener_func,
2216 .local_port = MLXSW_PORT_DONT_CARE,
2217 .trap_id = MLXSW_TRAP_ID_MMRP,
2218 },
2219 {
2220 .func = mlxsw_sp_rx_listener_func,
2221 .local_port = MLXSW_PORT_DONT_CARE,
2222 .trap_id = MLXSW_TRAP_ID_MVRP,
2223 },
2224 {
2225 .func = mlxsw_sp_rx_listener_func,
2226 .local_port = MLXSW_PORT_DONT_CARE,
2227 .trap_id = MLXSW_TRAP_ID_RPVST,
2228 },
2229 {
2230 .func = mlxsw_sp_rx_listener_func,
2231 .local_port = MLXSW_PORT_DONT_CARE,
2232 .trap_id = MLXSW_TRAP_ID_DHCP,
2233 },
2234 {
2235 .func = mlxsw_sp_rx_listener_func,
2236 .local_port = MLXSW_PORT_DONT_CARE,
2237 .trap_id = MLXSW_TRAP_ID_IGMP_QUERY,
2238 },
2239 {
2240 .func = mlxsw_sp_rx_listener_func,
2241 .local_port = MLXSW_PORT_DONT_CARE,
2242 .trap_id = MLXSW_TRAP_ID_IGMP_V1_REPORT,
2243 },
2244 {
2245 .func = mlxsw_sp_rx_listener_func,
2246 .local_port = MLXSW_PORT_DONT_CARE,
2247 .trap_id = MLXSW_TRAP_ID_IGMP_V2_REPORT,
2248 },
2249 {
2250 .func = mlxsw_sp_rx_listener_func,
2251 .local_port = MLXSW_PORT_DONT_CARE,
2252 .trap_id = MLXSW_TRAP_ID_IGMP_V2_LEAVE,
2253 },
2254 {
2255 .func = mlxsw_sp_rx_listener_func,
2256 .local_port = MLXSW_PORT_DONT_CARE,
2257 .trap_id = MLXSW_TRAP_ID_IGMP_V3_REPORT,
2258 },
2259};
2260
2261static int mlxsw_sp_traps_init(struct mlxsw_sp *mlxsw_sp)
2262{
2263 char htgt_pl[MLXSW_REG_HTGT_LEN];
2264 char hpkt_pl[MLXSW_REG_HPKT_LEN];
2265 int i;
2266 int err;
2267
2268 mlxsw_reg_htgt_pack(htgt_pl, MLXSW_REG_HTGT_TRAP_GROUP_RX);
2269 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(htgt), htgt_pl);
2270 if (err)
2271 return err;
2272
2273 mlxsw_reg_htgt_pack(htgt_pl, MLXSW_REG_HTGT_TRAP_GROUP_CTRL);
2274 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(htgt), htgt_pl);
2275 if (err)
2276 return err;
2277
2278 for (i = 0; i < ARRAY_SIZE(mlxsw_sp_rx_listener); i++) {
2279 err = mlxsw_core_rx_listener_register(mlxsw_sp->core,
2280 &mlxsw_sp_rx_listener[i],
2281 mlxsw_sp);
2282 if (err)
2283 goto err_rx_listener_register;
2284
2285 mlxsw_reg_hpkt_pack(hpkt_pl, MLXSW_REG_HPKT_ACTION_TRAP_TO_CPU,
2286 mlxsw_sp_rx_listener[i].trap_id);
2287 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(hpkt), hpkt_pl);
2288 if (err)
2289 goto err_rx_trap_set;
2290 }
2291 return 0;
2292
2293err_rx_trap_set:
2294 mlxsw_core_rx_listener_unregister(mlxsw_sp->core,
2295 &mlxsw_sp_rx_listener[i],
2296 mlxsw_sp);
2297err_rx_listener_register:
2298 for (i--; i >= 0; i--) {
2299 mlxsw_reg_hpkt_pack(hpkt_pl, MLXSW_REG_HPKT_ACTION_FORWARD,
2300 mlxsw_sp_rx_listener[i].trap_id);
2301 mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(hpkt), hpkt_pl);
2302
2303 mlxsw_core_rx_listener_unregister(mlxsw_sp->core,
2304 &mlxsw_sp_rx_listener[i],
2305 mlxsw_sp);
2306 }
2307 return err;
2308}
2309
2310static void mlxsw_sp_traps_fini(struct mlxsw_sp *mlxsw_sp)
2311{
2312 char hpkt_pl[MLXSW_REG_HPKT_LEN];
2313 int i;
2314
2315 for (i = 0; i < ARRAY_SIZE(mlxsw_sp_rx_listener); i++) {
2316 mlxsw_reg_hpkt_pack(hpkt_pl, MLXSW_REG_HPKT_ACTION_FORWARD,
2317 mlxsw_sp_rx_listener[i].trap_id);
2318 mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(hpkt), hpkt_pl);
2319
2320 mlxsw_core_rx_listener_unregister(mlxsw_sp->core,
2321 &mlxsw_sp_rx_listener[i],
2322 mlxsw_sp);
2323 }
2324}
2325
2326static int __mlxsw_sp_flood_init(struct mlxsw_core *mlxsw_core,
2327 enum mlxsw_reg_sfgc_type type,
2328 enum mlxsw_reg_sfgc_bridge_type bridge_type)
2329{
2330 enum mlxsw_flood_table_type table_type;
2331 enum mlxsw_sp_flood_table flood_table;
2332 char sfgc_pl[MLXSW_REG_SFGC_LEN];
2333
Ido Schimmel19ae6122015-12-15 16:03:39 +01002334 if (bridge_type == MLXSW_REG_SFGC_BRIDGE_TYPE_VFID)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002335 table_type = MLXSW_REG_SFGC_TABLE_TYPE_FID;
Ido Schimmel19ae6122015-12-15 16:03:39 +01002336 else
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002337 table_type = MLXSW_REG_SFGC_TABLE_TYPE_FID_OFFEST;
Ido Schimmel19ae6122015-12-15 16:03:39 +01002338
2339 if (type == MLXSW_REG_SFGC_TYPE_UNKNOWN_UNICAST)
2340 flood_table = MLXSW_SP_FLOOD_TABLE_UC;
2341 else
2342 flood_table = MLXSW_SP_FLOOD_TABLE_BM;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002343
2344 mlxsw_reg_sfgc_pack(sfgc_pl, type, bridge_type, table_type,
2345 flood_table);
2346 return mlxsw_reg_write(mlxsw_core, MLXSW_REG(sfgc), sfgc_pl);
2347}
2348
2349static int mlxsw_sp_flood_init(struct mlxsw_sp *mlxsw_sp)
2350{
2351 int type, err;
2352
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002353 for (type = 0; type < MLXSW_REG_SFGC_TYPE_MAX; type++) {
2354 if (type == MLXSW_REG_SFGC_TYPE_RESERVED)
2355 continue;
2356
2357 err = __mlxsw_sp_flood_init(mlxsw_sp->core, type,
2358 MLXSW_REG_SFGC_BRIDGE_TYPE_VFID);
2359 if (err)
2360 return err;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002361
2362 err = __mlxsw_sp_flood_init(mlxsw_sp->core, type,
2363 MLXSW_REG_SFGC_BRIDGE_TYPE_1Q_FID);
2364 if (err)
2365 return err;
2366 }
2367
2368 return 0;
2369}
2370
Jiri Pirko0d65fc12015-12-03 12:12:28 +01002371static int mlxsw_sp_lag_init(struct mlxsw_sp *mlxsw_sp)
2372{
2373 char slcr_pl[MLXSW_REG_SLCR_LEN];
2374
2375 mlxsw_reg_slcr_pack(slcr_pl, MLXSW_REG_SLCR_LAG_HASH_SMAC |
2376 MLXSW_REG_SLCR_LAG_HASH_DMAC |
2377 MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE |
2378 MLXSW_REG_SLCR_LAG_HASH_VLANID |
2379 MLXSW_REG_SLCR_LAG_HASH_SIP |
2380 MLXSW_REG_SLCR_LAG_HASH_DIP |
2381 MLXSW_REG_SLCR_LAG_HASH_SPORT |
2382 MLXSW_REG_SLCR_LAG_HASH_DPORT |
2383 MLXSW_REG_SLCR_LAG_HASH_IPPROTO);
2384 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(slcr), slcr_pl);
2385}
2386
Jiri Pirkob2f10572016-04-08 19:11:23 +02002387static int mlxsw_sp_init(struct mlxsw_core *mlxsw_core,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002388 const struct mlxsw_bus_info *mlxsw_bus_info)
2389{
Jiri Pirkob2f10572016-04-08 19:11:23 +02002390 struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002391 int err;
2392
2393 mlxsw_sp->core = mlxsw_core;
2394 mlxsw_sp->bus_info = mlxsw_bus_info;
Ido Schimmel7f71eb42015-12-15 16:03:37 +01002395 INIT_LIST_HEAD(&mlxsw_sp->port_vfids.list);
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01002396 INIT_LIST_HEAD(&mlxsw_sp->br_vfids.list);
Elad Raz3a49b4f2016-01-10 21:06:28 +01002397 INIT_LIST_HEAD(&mlxsw_sp->br_mids.list);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002398
2399 err = mlxsw_sp_base_mac_get(mlxsw_sp);
2400 if (err) {
2401 dev_err(mlxsw_sp->bus_info->dev, "Failed to get base mac\n");
2402 return err;
2403 }
2404
2405 err = mlxsw_sp_ports_create(mlxsw_sp);
2406 if (err) {
2407 dev_err(mlxsw_sp->bus_info->dev, "Failed to create ports\n");
Ido Schimmel7f71eb42015-12-15 16:03:37 +01002408 return err;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002409 }
2410
2411 err = mlxsw_sp_event_register(mlxsw_sp, MLXSW_TRAP_ID_PUDE);
2412 if (err) {
2413 dev_err(mlxsw_sp->bus_info->dev, "Failed to register for PUDE events\n");
2414 goto err_event_register;
2415 }
2416
2417 err = mlxsw_sp_traps_init(mlxsw_sp);
2418 if (err) {
2419 dev_err(mlxsw_sp->bus_info->dev, "Failed to set traps for RX\n");
2420 goto err_rx_listener_register;
2421 }
2422
2423 err = mlxsw_sp_flood_init(mlxsw_sp);
2424 if (err) {
2425 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize flood tables\n");
2426 goto err_flood_init;
2427 }
2428
2429 err = mlxsw_sp_buffers_init(mlxsw_sp);
2430 if (err) {
2431 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize buffers\n");
2432 goto err_buffers_init;
2433 }
2434
Jiri Pirko0d65fc12015-12-03 12:12:28 +01002435 err = mlxsw_sp_lag_init(mlxsw_sp);
2436 if (err) {
2437 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize LAG\n");
2438 goto err_lag_init;
2439 }
2440
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002441 err = mlxsw_sp_switchdev_init(mlxsw_sp);
2442 if (err) {
2443 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize switchdev\n");
2444 goto err_switchdev_init;
2445 }
2446
2447 return 0;
2448
2449err_switchdev_init:
Jiri Pirko0d65fc12015-12-03 12:12:28 +01002450err_lag_init:
Jiri Pirko0f433fa2016-04-14 18:19:24 +02002451 mlxsw_sp_buffers_fini(mlxsw_sp);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002452err_buffers_init:
2453err_flood_init:
2454 mlxsw_sp_traps_fini(mlxsw_sp);
2455err_rx_listener_register:
2456 mlxsw_sp_event_unregister(mlxsw_sp, MLXSW_TRAP_ID_PUDE);
2457err_event_register:
2458 mlxsw_sp_ports_remove(mlxsw_sp);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002459 return err;
2460}
2461
Jiri Pirkob2f10572016-04-08 19:11:23 +02002462static void mlxsw_sp_fini(struct mlxsw_core *mlxsw_core)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002463{
Jiri Pirkob2f10572016-04-08 19:11:23 +02002464 struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002465
2466 mlxsw_sp_switchdev_fini(mlxsw_sp);
Jiri Pirko5113bfd2016-05-06 22:20:59 +02002467 mlxsw_sp_buffers_fini(mlxsw_sp);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002468 mlxsw_sp_traps_fini(mlxsw_sp);
2469 mlxsw_sp_event_unregister(mlxsw_sp, MLXSW_TRAP_ID_PUDE);
2470 mlxsw_sp_ports_remove(mlxsw_sp);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002471}
2472
2473static struct mlxsw_config_profile mlxsw_sp_config_profile = {
2474 .used_max_vepa_channels = 1,
2475 .max_vepa_channels = 0,
2476 .used_max_lag = 1,
Jiri Pirko0d65fc12015-12-03 12:12:28 +01002477 .max_lag = MLXSW_SP_LAG_MAX,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002478 .used_max_port_per_lag = 1,
Jiri Pirko0d65fc12015-12-03 12:12:28 +01002479 .max_port_per_lag = MLXSW_SP_PORT_PER_LAG_MAX,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002480 .used_max_mid = 1,
Elad Raz53ae6282016-01-10 21:06:26 +01002481 .max_mid = MLXSW_SP_MID_MAX,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002482 .used_max_pgt = 1,
2483 .max_pgt = 0,
2484 .used_max_system_port = 1,
2485 .max_system_port = 64,
2486 .used_max_vlan_groups = 1,
2487 .max_vlan_groups = 127,
2488 .used_max_regions = 1,
2489 .max_regions = 400,
2490 .used_flood_tables = 1,
2491 .used_flood_mode = 1,
2492 .flood_mode = 3,
2493 .max_fid_offset_flood_tables = 2,
2494 .fid_offset_flood_table_size = VLAN_N_VID - 1,
Ido Schimmel19ae6122015-12-15 16:03:39 +01002495 .max_fid_flood_tables = 2,
2496 .fid_flood_table_size = MLXSW_SP_VFID_MAX,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002497 .used_max_ib_mc = 1,
2498 .max_ib_mc = 0,
2499 .used_max_pkey = 1,
2500 .max_pkey = 0,
2501 .swid_config = {
2502 {
2503 .used_type = 1,
2504 .type = MLXSW_PORT_SWID_TYPE_ETH,
2505 }
2506 },
2507};
2508
2509static struct mlxsw_driver mlxsw_sp_driver = {
Jiri Pirko2d0ed392016-04-14 18:19:30 +02002510 .kind = MLXSW_DEVICE_KIND_SPECTRUM,
2511 .owner = THIS_MODULE,
2512 .priv_size = sizeof(struct mlxsw_sp),
2513 .init = mlxsw_sp_init,
2514 .fini = mlxsw_sp_fini,
2515 .port_split = mlxsw_sp_port_split,
2516 .port_unsplit = mlxsw_sp_port_unsplit,
2517 .sb_pool_get = mlxsw_sp_sb_pool_get,
2518 .sb_pool_set = mlxsw_sp_sb_pool_set,
2519 .sb_port_pool_get = mlxsw_sp_sb_port_pool_get,
2520 .sb_port_pool_set = mlxsw_sp_sb_port_pool_set,
2521 .sb_tc_pool_bind_get = mlxsw_sp_sb_tc_pool_bind_get,
2522 .sb_tc_pool_bind_set = mlxsw_sp_sb_tc_pool_bind_set,
2523 .sb_occ_snapshot = mlxsw_sp_sb_occ_snapshot,
2524 .sb_occ_max_clear = mlxsw_sp_sb_occ_max_clear,
2525 .sb_occ_port_pool_get = mlxsw_sp_sb_occ_port_pool_get,
2526 .sb_occ_tc_port_bind_get = mlxsw_sp_sb_occ_tc_port_bind_get,
2527 .txhdr_construct = mlxsw_sp_txhdr_construct,
2528 .txhdr_len = MLXSW_TXHDR_LEN,
2529 .profile = &mlxsw_sp_config_profile,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002530};
2531
Ido Schimmel039c49a2016-01-27 15:20:18 +01002532static int
2533mlxsw_sp_port_fdb_flush_by_port(const struct mlxsw_sp_port *mlxsw_sp_port)
2534{
2535 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2536 char sfdf_pl[MLXSW_REG_SFDF_LEN];
2537
2538 mlxsw_reg_sfdf_pack(sfdf_pl, MLXSW_REG_SFDF_FLUSH_PER_PORT);
2539 mlxsw_reg_sfdf_system_port_set(sfdf_pl, mlxsw_sp_port->local_port);
2540
2541 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sfdf), sfdf_pl);
2542}
2543
2544static int
2545mlxsw_sp_port_fdb_flush_by_port_fid(const struct mlxsw_sp_port *mlxsw_sp_port,
2546 u16 fid)
2547{
2548 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2549 char sfdf_pl[MLXSW_REG_SFDF_LEN];
2550
2551 mlxsw_reg_sfdf_pack(sfdf_pl, MLXSW_REG_SFDF_FLUSH_PER_PORT_AND_FID);
2552 mlxsw_reg_sfdf_fid_set(sfdf_pl, fid);
2553 mlxsw_reg_sfdf_port_fid_system_port_set(sfdf_pl,
2554 mlxsw_sp_port->local_port);
2555
2556 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sfdf), sfdf_pl);
2557}
2558
2559static int
2560mlxsw_sp_port_fdb_flush_by_lag_id(const struct mlxsw_sp_port *mlxsw_sp_port)
2561{
2562 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2563 char sfdf_pl[MLXSW_REG_SFDF_LEN];
2564
2565 mlxsw_reg_sfdf_pack(sfdf_pl, MLXSW_REG_SFDF_FLUSH_PER_LAG);
2566 mlxsw_reg_sfdf_lag_id_set(sfdf_pl, mlxsw_sp_port->lag_id);
2567
2568 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sfdf), sfdf_pl);
2569}
2570
2571static int
2572mlxsw_sp_port_fdb_flush_by_lag_id_fid(const struct mlxsw_sp_port *mlxsw_sp_port,
2573 u16 fid)
2574{
2575 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2576 char sfdf_pl[MLXSW_REG_SFDF_LEN];
2577
2578 mlxsw_reg_sfdf_pack(sfdf_pl, MLXSW_REG_SFDF_FLUSH_PER_LAG_AND_FID);
2579 mlxsw_reg_sfdf_fid_set(sfdf_pl, fid);
2580 mlxsw_reg_sfdf_lag_fid_lag_id_set(sfdf_pl, mlxsw_sp_port->lag_id);
2581
2582 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sfdf), sfdf_pl);
2583}
2584
2585static int
2586__mlxsw_sp_port_fdb_flush(const struct mlxsw_sp_port *mlxsw_sp_port)
2587{
2588 int err, last_err = 0;
2589 u16 vid;
2590
2591 for (vid = 1; vid < VLAN_N_VID - 1; vid++) {
2592 err = mlxsw_sp_port_fdb_flush_by_port_fid(mlxsw_sp_port, vid);
2593 if (err)
2594 last_err = err;
2595 }
2596
2597 return last_err;
2598}
2599
2600static int
2601__mlxsw_sp_port_fdb_flush_lagged(const struct mlxsw_sp_port *mlxsw_sp_port)
2602{
2603 int err, last_err = 0;
2604 u16 vid;
2605
2606 for (vid = 1; vid < VLAN_N_VID - 1; vid++) {
2607 err = mlxsw_sp_port_fdb_flush_by_lag_id_fid(mlxsw_sp_port, vid);
2608 if (err)
2609 last_err = err;
2610 }
2611
2612 return last_err;
2613}
2614
2615static int mlxsw_sp_port_fdb_flush(struct mlxsw_sp_port *mlxsw_sp_port)
2616{
2617 if (!list_empty(&mlxsw_sp_port->vports_list))
2618 if (mlxsw_sp_port->lagged)
2619 return __mlxsw_sp_port_fdb_flush_lagged(mlxsw_sp_port);
2620 else
2621 return __mlxsw_sp_port_fdb_flush(mlxsw_sp_port);
2622 else
2623 if (mlxsw_sp_port->lagged)
2624 return mlxsw_sp_port_fdb_flush_by_lag_id(mlxsw_sp_port);
2625 else
2626 return mlxsw_sp_port_fdb_flush_by_port(mlxsw_sp_port);
2627}
2628
2629static int mlxsw_sp_vport_fdb_flush(struct mlxsw_sp_port *mlxsw_sp_vport)
2630{
2631 u16 vfid = mlxsw_sp_vport_vfid_get(mlxsw_sp_vport);
2632 u16 fid = mlxsw_sp_vfid_to_fid(vfid);
2633
2634 if (mlxsw_sp_vport->lagged)
2635 return mlxsw_sp_port_fdb_flush_by_lag_id_fid(mlxsw_sp_vport,
2636 fid);
2637 else
2638 return mlxsw_sp_port_fdb_flush_by_port_fid(mlxsw_sp_vport, fid);
2639}
2640
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002641static bool mlxsw_sp_port_dev_check(const struct net_device *dev)
2642{
2643 return dev->netdev_ops == &mlxsw_sp_port_netdev_ops;
2644}
2645
Ido Schimmel7117a572016-06-20 23:04:06 +02002646static bool mlxsw_sp_master_bridge_check(struct mlxsw_sp *mlxsw_sp,
2647 struct net_device *br_dev)
2648{
2649 return !mlxsw_sp->master_bridge.dev ||
2650 mlxsw_sp->master_bridge.dev == br_dev;
2651}
2652
2653static void mlxsw_sp_master_bridge_inc(struct mlxsw_sp *mlxsw_sp,
2654 struct net_device *br_dev)
2655{
2656 mlxsw_sp->master_bridge.dev = br_dev;
2657 mlxsw_sp->master_bridge.ref_count++;
2658}
2659
2660static void mlxsw_sp_master_bridge_dec(struct mlxsw_sp *mlxsw_sp)
2661{
2662 if (--mlxsw_sp->master_bridge.ref_count == 0)
2663 mlxsw_sp->master_bridge.dev = NULL;
2664}
2665
2666static int mlxsw_sp_port_bridge_join(struct mlxsw_sp_port *mlxsw_sp_port,
2667 struct net_device *br_dev)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002668{
2669 struct net_device *dev = mlxsw_sp_port->dev;
2670 int err;
2671
2672 /* When port is not bridged untagged packets are tagged with
2673 * PVID=VID=1, thereby creating an implicit VLAN interface in
2674 * the device. Remove it and let bridge code take care of its
2675 * own VLANs.
2676 */
2677 err = mlxsw_sp_port_kill_vid(dev, 0, 1);
Ido Schimmel6c72a3d2016-01-04 10:42:26 +01002678 if (err)
2679 return err;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002680
Ido Schimmel7117a572016-06-20 23:04:06 +02002681 mlxsw_sp_master_bridge_inc(mlxsw_sp_port->mlxsw_sp, br_dev);
2682
Ido Schimmel6c72a3d2016-01-04 10:42:26 +01002683 mlxsw_sp_port->learning = 1;
2684 mlxsw_sp_port->learning_sync = 1;
2685 mlxsw_sp_port->uc_flood = 1;
2686 mlxsw_sp_port->bridged = 1;
2687
2688 return 0;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002689}
2690
Ido Schimmel82e6db02016-06-20 23:04:04 +02002691static void mlxsw_sp_port_bridge_leave(struct mlxsw_sp_port *mlxsw_sp_port,
2692 bool flush_fdb)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002693{
2694 struct net_device *dev = mlxsw_sp_port->dev;
Ido Schimmel5a8f4522016-01-04 10:42:25 +01002695
Ido Schimmel039c49a2016-01-27 15:20:18 +01002696 if (flush_fdb && mlxsw_sp_port_fdb_flush(mlxsw_sp_port))
2697 netdev_err(mlxsw_sp_port->dev, "Failed to flush FDB\n");
2698
Ido Schimmel28a01d22016-02-18 11:30:02 +01002699 mlxsw_sp_port_pvid_set(mlxsw_sp_port, 1);
2700
Ido Schimmel7117a572016-06-20 23:04:06 +02002701 mlxsw_sp_master_bridge_dec(mlxsw_sp_port->mlxsw_sp);
2702
Ido Schimmel6c72a3d2016-01-04 10:42:26 +01002703 mlxsw_sp_port->learning = 0;
2704 mlxsw_sp_port->learning_sync = 0;
2705 mlxsw_sp_port->uc_flood = 0;
Ido Schimmel5a8f4522016-01-04 10:42:25 +01002706 mlxsw_sp_port->bridged = 0;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002707
2708 /* Add implicit VLAN interface in the device, so that untagged
2709 * packets will be classified to the default vFID.
2710 */
Ido Schimmel82e6db02016-06-20 23:04:04 +02002711 mlxsw_sp_port_add_vid(dev, 0, 1);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002712}
2713
Jiri Pirko0d65fc12015-12-03 12:12:28 +01002714static int mlxsw_sp_lag_create(struct mlxsw_sp *mlxsw_sp, u16 lag_id)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002715{
Jiri Pirko0d65fc12015-12-03 12:12:28 +01002716 char sldr_pl[MLXSW_REG_SLDR_LEN];
2717
2718 mlxsw_reg_sldr_lag_create_pack(sldr_pl, lag_id);
2719 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sldr), sldr_pl);
2720}
2721
2722static int mlxsw_sp_lag_destroy(struct mlxsw_sp *mlxsw_sp, u16 lag_id)
2723{
2724 char sldr_pl[MLXSW_REG_SLDR_LEN];
2725
2726 mlxsw_reg_sldr_lag_destroy_pack(sldr_pl, lag_id);
2727 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sldr), sldr_pl);
2728}
2729
2730static int mlxsw_sp_lag_col_port_add(struct mlxsw_sp_port *mlxsw_sp_port,
2731 u16 lag_id, u8 port_index)
2732{
2733 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2734 char slcor_pl[MLXSW_REG_SLCOR_LEN];
2735
2736 mlxsw_reg_slcor_port_add_pack(slcor_pl, mlxsw_sp_port->local_port,
2737 lag_id, port_index);
2738 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(slcor), slcor_pl);
2739}
2740
2741static int mlxsw_sp_lag_col_port_remove(struct mlxsw_sp_port *mlxsw_sp_port,
2742 u16 lag_id)
2743{
2744 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2745 char slcor_pl[MLXSW_REG_SLCOR_LEN];
2746
2747 mlxsw_reg_slcor_port_remove_pack(slcor_pl, mlxsw_sp_port->local_port,
2748 lag_id);
2749 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(slcor), slcor_pl);
2750}
2751
2752static int mlxsw_sp_lag_col_port_enable(struct mlxsw_sp_port *mlxsw_sp_port,
2753 u16 lag_id)
2754{
2755 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2756 char slcor_pl[MLXSW_REG_SLCOR_LEN];
2757
2758 mlxsw_reg_slcor_col_enable_pack(slcor_pl, mlxsw_sp_port->local_port,
2759 lag_id);
2760 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(slcor), slcor_pl);
2761}
2762
2763static int mlxsw_sp_lag_col_port_disable(struct mlxsw_sp_port *mlxsw_sp_port,
2764 u16 lag_id)
2765{
2766 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2767 char slcor_pl[MLXSW_REG_SLCOR_LEN];
2768
2769 mlxsw_reg_slcor_col_disable_pack(slcor_pl, mlxsw_sp_port->local_port,
2770 lag_id);
2771 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(slcor), slcor_pl);
2772}
2773
2774static int mlxsw_sp_lag_index_get(struct mlxsw_sp *mlxsw_sp,
2775 struct net_device *lag_dev,
2776 u16 *p_lag_id)
2777{
2778 struct mlxsw_sp_upper *lag;
2779 int free_lag_id = -1;
2780 int i;
2781
2782 for (i = 0; i < MLXSW_SP_LAG_MAX; i++) {
2783 lag = mlxsw_sp_lag_get(mlxsw_sp, i);
2784 if (lag->ref_count) {
2785 if (lag->dev == lag_dev) {
2786 *p_lag_id = i;
2787 return 0;
2788 }
2789 } else if (free_lag_id < 0) {
2790 free_lag_id = i;
2791 }
2792 }
2793 if (free_lag_id < 0)
2794 return -EBUSY;
2795 *p_lag_id = free_lag_id;
2796 return 0;
2797}
2798
2799static bool
2800mlxsw_sp_master_lag_check(struct mlxsw_sp *mlxsw_sp,
2801 struct net_device *lag_dev,
2802 struct netdev_lag_upper_info *lag_upper_info)
2803{
2804 u16 lag_id;
2805
2806 if (mlxsw_sp_lag_index_get(mlxsw_sp, lag_dev, &lag_id) != 0)
2807 return false;
2808 if (lag_upper_info->tx_type != NETDEV_LAG_TX_TYPE_HASH)
2809 return false;
2810 return true;
2811}
2812
2813static int mlxsw_sp_port_lag_index_get(struct mlxsw_sp *mlxsw_sp,
2814 u16 lag_id, u8 *p_port_index)
2815{
2816 int i;
2817
2818 for (i = 0; i < MLXSW_SP_PORT_PER_LAG_MAX; i++) {
2819 if (!mlxsw_sp_port_lagged_get(mlxsw_sp, lag_id, i)) {
2820 *p_port_index = i;
2821 return 0;
2822 }
2823 }
2824 return -EBUSY;
2825}
2826
2827static int mlxsw_sp_port_lag_join(struct mlxsw_sp_port *mlxsw_sp_port,
2828 struct net_device *lag_dev)
2829{
2830 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2831 struct mlxsw_sp_upper *lag;
2832 u16 lag_id;
2833 u8 port_index;
2834 int err;
2835
2836 err = mlxsw_sp_lag_index_get(mlxsw_sp, lag_dev, &lag_id);
2837 if (err)
2838 return err;
2839 lag = mlxsw_sp_lag_get(mlxsw_sp, lag_id);
2840 if (!lag->ref_count) {
2841 err = mlxsw_sp_lag_create(mlxsw_sp, lag_id);
2842 if (err)
2843 return err;
2844 lag->dev = lag_dev;
2845 }
2846
2847 err = mlxsw_sp_port_lag_index_get(mlxsw_sp, lag_id, &port_index);
2848 if (err)
2849 return err;
2850 err = mlxsw_sp_lag_col_port_add(mlxsw_sp_port, lag_id, port_index);
2851 if (err)
2852 goto err_col_port_add;
2853 err = mlxsw_sp_lag_col_port_enable(mlxsw_sp_port, lag_id);
2854 if (err)
2855 goto err_col_port_enable;
2856
2857 mlxsw_core_lag_mapping_set(mlxsw_sp->core, lag_id, port_index,
2858 mlxsw_sp_port->local_port);
2859 mlxsw_sp_port->lag_id = lag_id;
2860 mlxsw_sp_port->lagged = 1;
2861 lag->ref_count++;
2862 return 0;
2863
Ido Schimmel51554db2016-05-06 22:18:39 +02002864err_col_port_enable:
2865 mlxsw_sp_lag_col_port_remove(mlxsw_sp_port, lag_id);
Jiri Pirko0d65fc12015-12-03 12:12:28 +01002866err_col_port_add:
2867 if (!lag->ref_count)
2868 mlxsw_sp_lag_destroy(mlxsw_sp, lag_id);
Jiri Pirko0d65fc12015-12-03 12:12:28 +01002869 return err;
2870}
2871
Ido Schimmel82e6db02016-06-20 23:04:04 +02002872static void mlxsw_sp_vport_bridge_leave(struct mlxsw_sp_port *mlxsw_sp_vport,
2873 struct net_device *br_dev,
2874 bool flush_fdb);
Ido Schimmel4dc236c2016-01-27 15:20:16 +01002875
Ido Schimmel82e6db02016-06-20 23:04:04 +02002876static void mlxsw_sp_port_lag_leave(struct mlxsw_sp_port *mlxsw_sp_port,
2877 struct net_device *lag_dev)
Jiri Pirko0d65fc12015-12-03 12:12:28 +01002878{
2879 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
Ido Schimmel4dc236c2016-01-27 15:20:16 +01002880 struct mlxsw_sp_port *mlxsw_sp_vport;
Jiri Pirko0d65fc12015-12-03 12:12:28 +01002881 struct mlxsw_sp_upper *lag;
2882 u16 lag_id = mlxsw_sp_port->lag_id;
Jiri Pirko0d65fc12015-12-03 12:12:28 +01002883
2884 if (!mlxsw_sp_port->lagged)
Ido Schimmel82e6db02016-06-20 23:04:04 +02002885 return;
Jiri Pirko0d65fc12015-12-03 12:12:28 +01002886 lag = mlxsw_sp_lag_get(mlxsw_sp, lag_id);
2887 WARN_ON(lag->ref_count == 0);
2888
Ido Schimmel82e6db02016-06-20 23:04:04 +02002889 mlxsw_sp_lag_col_port_disable(mlxsw_sp_port, lag_id);
2890 mlxsw_sp_lag_col_port_remove(mlxsw_sp_port, lag_id);
Jiri Pirko0d65fc12015-12-03 12:12:28 +01002891
Ido Schimmel4dc236c2016-01-27 15:20:16 +01002892 /* In case we leave a LAG device that has bridges built on top,
2893 * then their teardown sequence is never issued and we need to
2894 * invoke the necessary cleanup routines ourselves.
2895 */
2896 list_for_each_entry(mlxsw_sp_vport, &mlxsw_sp_port->vports_list,
2897 vport.list) {
2898 struct net_device *br_dev;
2899
2900 if (!mlxsw_sp_vport->bridged)
2901 continue;
2902
2903 br_dev = mlxsw_sp_vport_br_get(mlxsw_sp_vport);
Ido Schimmel039c49a2016-01-27 15:20:18 +01002904 mlxsw_sp_vport_bridge_leave(mlxsw_sp_vport, br_dev, false);
Ido Schimmel4dc236c2016-01-27 15:20:16 +01002905 }
2906
2907 if (mlxsw_sp_port->bridged) {
2908 mlxsw_sp_port_active_vlans_del(mlxsw_sp_port);
Ido Schimmel039c49a2016-01-27 15:20:18 +01002909 mlxsw_sp_port_bridge_leave(mlxsw_sp_port, false);
Ido Schimmel4dc236c2016-01-27 15:20:16 +01002910 }
2911
Jiri Pirko0d65fc12015-12-03 12:12:28 +01002912 if (lag->ref_count == 1) {
Ido Schimmel039c49a2016-01-27 15:20:18 +01002913 if (mlxsw_sp_port_fdb_flush_by_lag_id(mlxsw_sp_port))
2914 netdev_err(mlxsw_sp_port->dev, "Failed to flush FDB\n");
Ido Schimmel82e6db02016-06-20 23:04:04 +02002915 mlxsw_sp_lag_destroy(mlxsw_sp, lag_id);
Jiri Pirko0d65fc12015-12-03 12:12:28 +01002916 }
2917
2918 mlxsw_core_lag_mapping_clear(mlxsw_sp->core, lag_id,
2919 mlxsw_sp_port->local_port);
2920 mlxsw_sp_port->lagged = 0;
2921 lag->ref_count--;
Jiri Pirko0d65fc12015-12-03 12:12:28 +01002922}
2923
Jiri Pirko74581202015-12-03 12:12:30 +01002924static int mlxsw_sp_lag_dist_port_add(struct mlxsw_sp_port *mlxsw_sp_port,
2925 u16 lag_id)
2926{
2927 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2928 char sldr_pl[MLXSW_REG_SLDR_LEN];
2929
2930 mlxsw_reg_sldr_lag_add_port_pack(sldr_pl, lag_id,
2931 mlxsw_sp_port->local_port);
2932 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sldr), sldr_pl);
2933}
2934
2935static int mlxsw_sp_lag_dist_port_remove(struct mlxsw_sp_port *mlxsw_sp_port,
2936 u16 lag_id)
2937{
2938 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2939 char sldr_pl[MLXSW_REG_SLDR_LEN];
2940
2941 mlxsw_reg_sldr_lag_remove_port_pack(sldr_pl, lag_id,
2942 mlxsw_sp_port->local_port);
2943 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sldr), sldr_pl);
2944}
2945
2946static int mlxsw_sp_port_lag_tx_en_set(struct mlxsw_sp_port *mlxsw_sp_port,
2947 bool lag_tx_enabled)
2948{
2949 if (lag_tx_enabled)
2950 return mlxsw_sp_lag_dist_port_add(mlxsw_sp_port,
2951 mlxsw_sp_port->lag_id);
2952 else
2953 return mlxsw_sp_lag_dist_port_remove(mlxsw_sp_port,
2954 mlxsw_sp_port->lag_id);
2955}
2956
2957static int mlxsw_sp_port_lag_changed(struct mlxsw_sp_port *mlxsw_sp_port,
2958 struct netdev_lag_lower_state_info *info)
2959{
2960 return mlxsw_sp_port_lag_tx_en_set(mlxsw_sp_port, info->tx_enabled);
2961}
2962
Ido Schimmel9589a7b52015-12-15 16:03:43 +01002963static int mlxsw_sp_port_vlan_link(struct mlxsw_sp_port *mlxsw_sp_port,
2964 struct net_device *vlan_dev)
2965{
2966 struct mlxsw_sp_port *mlxsw_sp_vport;
2967 u16 vid = vlan_dev_vlan_id(vlan_dev);
2968
2969 mlxsw_sp_vport = mlxsw_sp_port_vport_find(mlxsw_sp_port, vid);
Ido Schimmel423b9372016-06-20 23:04:03 +02002970 if (WARN_ON(!mlxsw_sp_vport))
Ido Schimmel9589a7b52015-12-15 16:03:43 +01002971 return -EINVAL;
Ido Schimmel9589a7b52015-12-15 16:03:43 +01002972
2973 mlxsw_sp_vport->dev = vlan_dev;
2974
2975 return 0;
2976}
2977
Ido Schimmel82e6db02016-06-20 23:04:04 +02002978static void mlxsw_sp_port_vlan_unlink(struct mlxsw_sp_port *mlxsw_sp_port,
2979 struct net_device *vlan_dev)
Ido Schimmel9589a7b52015-12-15 16:03:43 +01002980{
2981 struct mlxsw_sp_port *mlxsw_sp_vport;
2982 u16 vid = vlan_dev_vlan_id(vlan_dev);
2983
2984 mlxsw_sp_vport = mlxsw_sp_port_vport_find(mlxsw_sp_port, vid);
Ido Schimmel423b9372016-06-20 23:04:03 +02002985 if (WARN_ON(!mlxsw_sp_vport))
Ido Schimmel82e6db02016-06-20 23:04:04 +02002986 return;
Ido Schimmel9589a7b52015-12-15 16:03:43 +01002987
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01002988 /* When removing a VLAN device while still bridged we should first
2989 * remove it from the bridge, as we receive the bridge's notification
2990 * when the vPort is already gone.
2991 */
2992 if (mlxsw_sp_vport->bridged) {
2993 struct net_device *br_dev;
2994
2995 br_dev = mlxsw_sp_vport_br_get(mlxsw_sp_vport);
Ido Schimmel039c49a2016-01-27 15:20:18 +01002996 mlxsw_sp_vport_bridge_leave(mlxsw_sp_vport, br_dev, true);
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01002997 }
2998
Ido Schimmel9589a7b52015-12-15 16:03:43 +01002999 mlxsw_sp_vport->dev = mlxsw_sp_port->dev;
Ido Schimmel9589a7b52015-12-15 16:03:43 +01003000}
3001
Jiri Pirko74581202015-12-03 12:12:30 +01003002static int mlxsw_sp_netdevice_port_upper_event(struct net_device *dev,
3003 unsigned long event, void *ptr)
Jiri Pirko0d65fc12015-12-03 12:12:28 +01003004{
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003005 struct netdev_notifier_changeupper_info *info;
3006 struct mlxsw_sp_port *mlxsw_sp_port;
3007 struct net_device *upper_dev;
3008 struct mlxsw_sp *mlxsw_sp;
Ido Schimmel80bedf12016-06-20 23:03:59 +02003009 int err = 0;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003010
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003011 mlxsw_sp_port = netdev_priv(dev);
3012 mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
3013 info = ptr;
3014
3015 switch (event) {
3016 case NETDEV_PRECHANGEUPPER:
3017 upper_dev = info->upper_dev;
Ido Schimmel59fe9b32016-06-20 23:04:00 +02003018 if (!is_vlan_dev(upper_dev) &&
3019 !netif_is_lag_master(upper_dev) &&
3020 !netif_is_bridge_master(upper_dev))
3021 return -EINVAL;
Ido Schimmel6ec43902016-06-20 23:04:01 +02003022 if (!info->linking)
Jiri Pirko0d65fc12015-12-03 12:12:28 +01003023 break;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003024 /* HW limitation forbids to put ports to multiple bridges. */
Jiri Pirko0d65fc12015-12-03 12:12:28 +01003025 if (netif_is_bridge_master(upper_dev) &&
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003026 !mlxsw_sp_master_bridge_check(mlxsw_sp, upper_dev))
Ido Schimmel80bedf12016-06-20 23:03:59 +02003027 return -EINVAL;
Jiri Pirko0d65fc12015-12-03 12:12:28 +01003028 if (netif_is_lag_master(upper_dev) &&
3029 !mlxsw_sp_master_lag_check(mlxsw_sp, upper_dev,
3030 info->upper_info))
Ido Schimmel80bedf12016-06-20 23:03:59 +02003031 return -EINVAL;
Ido Schimmel6ec43902016-06-20 23:04:01 +02003032 if (netif_is_lag_master(upper_dev) && vlan_uses_dev(dev))
3033 return -EINVAL;
3034 if (netif_is_lag_port(dev) && is_vlan_dev(upper_dev) &&
3035 !netif_is_lag_master(vlan_dev_real_dev(upper_dev)))
3036 return -EINVAL;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003037 break;
3038 case NETDEV_CHANGEUPPER:
3039 upper_dev = info->upper_dev;
Ido Schimmel9589a7b52015-12-15 16:03:43 +01003040 if (is_vlan_dev(upper_dev)) {
Ido Schimmel80bedf12016-06-20 23:03:59 +02003041 if (info->linking)
Ido Schimmel9589a7b52015-12-15 16:03:43 +01003042 err = mlxsw_sp_port_vlan_link(mlxsw_sp_port,
3043 upper_dev);
Ido Schimmel80bedf12016-06-20 23:03:59 +02003044 else
Ido Schimmel82e6db02016-06-20 23:04:04 +02003045 mlxsw_sp_port_vlan_unlink(mlxsw_sp_port,
3046 upper_dev);
Ido Schimmel9589a7b52015-12-15 16:03:43 +01003047 } else if (netif_is_bridge_master(upper_dev)) {
Ido Schimmel7117a572016-06-20 23:04:06 +02003048 if (info->linking)
3049 err = mlxsw_sp_port_bridge_join(mlxsw_sp_port,
3050 upper_dev);
3051 else
Ido Schimmel82e6db02016-06-20 23:04:04 +02003052 mlxsw_sp_port_bridge_leave(mlxsw_sp_port, true);
Jiri Pirko0d65fc12015-12-03 12:12:28 +01003053 } else if (netif_is_lag_master(upper_dev)) {
Ido Schimmel80bedf12016-06-20 23:03:59 +02003054 if (info->linking)
Jiri Pirko0d65fc12015-12-03 12:12:28 +01003055 err = mlxsw_sp_port_lag_join(mlxsw_sp_port,
3056 upper_dev);
Ido Schimmel80bedf12016-06-20 23:03:59 +02003057 else
Ido Schimmel82e6db02016-06-20 23:04:04 +02003058 mlxsw_sp_port_lag_leave(mlxsw_sp_port,
3059 upper_dev);
Ido Schimmel59fe9b32016-06-20 23:04:00 +02003060 } else {
3061 err = -EINVAL;
3062 WARN_ON(1);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003063 }
3064 break;
3065 }
3066
Ido Schimmel80bedf12016-06-20 23:03:59 +02003067 return err;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003068}
3069
Jiri Pirko74581202015-12-03 12:12:30 +01003070static int mlxsw_sp_netdevice_port_lower_event(struct net_device *dev,
3071 unsigned long event, void *ptr)
3072{
3073 struct netdev_notifier_changelowerstate_info *info;
3074 struct mlxsw_sp_port *mlxsw_sp_port;
3075 int err;
3076
3077 mlxsw_sp_port = netdev_priv(dev);
3078 info = ptr;
3079
3080 switch (event) {
3081 case NETDEV_CHANGELOWERSTATE:
3082 if (netif_is_lag_port(dev) && mlxsw_sp_port->lagged) {
3083 err = mlxsw_sp_port_lag_changed(mlxsw_sp_port,
3084 info->lower_state_info);
3085 if (err)
3086 netdev_err(dev, "Failed to reflect link aggregation lower state change\n");
3087 }
3088 break;
3089 }
3090
Ido Schimmel80bedf12016-06-20 23:03:59 +02003091 return 0;
Jiri Pirko74581202015-12-03 12:12:30 +01003092}
3093
3094static int mlxsw_sp_netdevice_port_event(struct net_device *dev,
3095 unsigned long event, void *ptr)
3096{
3097 switch (event) {
3098 case NETDEV_PRECHANGEUPPER:
3099 case NETDEV_CHANGEUPPER:
3100 return mlxsw_sp_netdevice_port_upper_event(dev, event, ptr);
3101 case NETDEV_CHANGELOWERSTATE:
3102 return mlxsw_sp_netdevice_port_lower_event(dev, event, ptr);
3103 }
3104
Ido Schimmel80bedf12016-06-20 23:03:59 +02003105 return 0;
Jiri Pirko74581202015-12-03 12:12:30 +01003106}
3107
Jiri Pirko0d65fc12015-12-03 12:12:28 +01003108static int mlxsw_sp_netdevice_lag_event(struct net_device *lag_dev,
3109 unsigned long event, void *ptr)
3110{
3111 struct net_device *dev;
3112 struct list_head *iter;
3113 int ret;
3114
3115 netdev_for_each_lower_dev(lag_dev, dev, iter) {
3116 if (mlxsw_sp_port_dev_check(dev)) {
3117 ret = mlxsw_sp_netdevice_port_event(dev, event, ptr);
Ido Schimmel80bedf12016-06-20 23:03:59 +02003118 if (ret)
Jiri Pirko0d65fc12015-12-03 12:12:28 +01003119 return ret;
3120 }
3121 }
3122
Ido Schimmel80bedf12016-06-20 23:03:59 +02003123 return 0;
Jiri Pirko0d65fc12015-12-03 12:12:28 +01003124}
3125
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01003126static struct mlxsw_sp_vfid *
3127mlxsw_sp_br_vfid_find(const struct mlxsw_sp *mlxsw_sp,
3128 const struct net_device *br_dev)
3129{
3130 struct mlxsw_sp_vfid *vfid;
3131
3132 list_for_each_entry(vfid, &mlxsw_sp->br_vfids.list, list) {
3133 if (vfid->br_dev == br_dev)
3134 return vfid;
3135 }
3136
3137 return NULL;
3138}
3139
3140static u16 mlxsw_sp_vfid_to_br_vfid(u16 vfid)
3141{
3142 return vfid - MLXSW_SP_VFID_PORT_MAX;
3143}
3144
3145static u16 mlxsw_sp_br_vfid_to_vfid(u16 br_vfid)
3146{
3147 return MLXSW_SP_VFID_PORT_MAX + br_vfid;
3148}
3149
3150static u16 mlxsw_sp_avail_br_vfid_get(const struct mlxsw_sp *mlxsw_sp)
3151{
3152 return find_first_zero_bit(mlxsw_sp->br_vfids.mapped,
3153 MLXSW_SP_VFID_BR_MAX);
3154}
3155
3156static struct mlxsw_sp_vfid *mlxsw_sp_br_vfid_create(struct mlxsw_sp *mlxsw_sp,
3157 struct net_device *br_dev)
3158{
3159 struct device *dev = mlxsw_sp->bus_info->dev;
Ido Schimmelc7e920b2016-06-20 23:04:09 +02003160 struct mlxsw_sp_vfid *f;
3161 u16 vfid, fid;
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01003162 int err;
3163
Ido Schimmelc7e920b2016-06-20 23:04:09 +02003164 vfid = mlxsw_sp_br_vfid_to_vfid(mlxsw_sp_avail_br_vfid_get(mlxsw_sp));
3165 if (vfid == MLXSW_SP_VFID_MAX) {
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01003166 dev_err(dev, "No available vFIDs\n");
3167 return ERR_PTR(-ERANGE);
3168 }
3169
Ido Schimmelc7e920b2016-06-20 23:04:09 +02003170 fid = mlxsw_sp_vfid_to_fid(vfid);
3171 err = mlxsw_sp_vfid_op(mlxsw_sp, fid, true);
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01003172 if (err) {
Ido Schimmelc7e920b2016-06-20 23:04:09 +02003173 dev_err(dev, "Failed to create FID=%d\n", fid);
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01003174 return ERR_PTR(err);
3175 }
3176
Ido Schimmelc7e920b2016-06-20 23:04:09 +02003177 f = kzalloc(sizeof(*f), GFP_KERNEL);
3178 if (!f)
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01003179 goto err_allocate_vfid;
3180
Ido Schimmelc7e920b2016-06-20 23:04:09 +02003181 f->vfid = vfid;
3182 f->br_dev = br_dev;
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01003183
Ido Schimmelc7e920b2016-06-20 23:04:09 +02003184 list_add(&f->list, &mlxsw_sp->br_vfids.list);
3185 set_bit(mlxsw_sp_vfid_to_br_vfid(vfid), mlxsw_sp->br_vfids.mapped);
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01003186
Ido Schimmelc7e920b2016-06-20 23:04:09 +02003187 return f;
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01003188
3189err_allocate_vfid:
Ido Schimmelc7e920b2016-06-20 23:04:09 +02003190 mlxsw_sp_vfid_op(mlxsw_sp, fid, false);
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01003191 return ERR_PTR(-ENOMEM);
3192}
3193
3194static void mlxsw_sp_br_vfid_destroy(struct mlxsw_sp *mlxsw_sp,
3195 struct mlxsw_sp_vfid *vfid)
3196{
3197 u16 br_vfid = mlxsw_sp_vfid_to_br_vfid(vfid->vfid);
Ido Schimmelc7e920b2016-06-20 23:04:09 +02003198 u16 fid = mlxsw_sp_vfid_to_fid(vfid->vfid);
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01003199
3200 clear_bit(br_vfid, mlxsw_sp->br_vfids.mapped);
3201 list_del(&vfid->list);
3202
Ido Schimmelc7e920b2016-06-20 23:04:09 +02003203 mlxsw_sp_vfid_op(mlxsw_sp, fid, false);
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01003204
3205 kfree(vfid);
3206}
3207
Ido Schimmel82e6db02016-06-20 23:04:04 +02003208static void mlxsw_sp_vport_bridge_leave(struct mlxsw_sp_port *mlxsw_sp_vport,
3209 struct net_device *br_dev,
3210 bool flush_fdb)
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01003211{
3212 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_vport->mlxsw_sp;
3213 u16 vid = mlxsw_sp_vport_vid_get(mlxsw_sp_vport);
3214 struct net_device *dev = mlxsw_sp_vport->dev;
3215 struct mlxsw_sp_vfid *vfid, *new_vfid;
3216 int err;
3217
3218 vfid = mlxsw_sp_br_vfid_find(mlxsw_sp, br_dev);
Ido Schimmel423b9372016-06-20 23:04:03 +02003219 if (WARN_ON(!vfid))
Ido Schimmel82e6db02016-06-20 23:04:04 +02003220 return;
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01003221
3222 /* We need a vFID to go back to after leaving the bridge's vFID. */
3223 new_vfid = mlxsw_sp_vfid_find(mlxsw_sp, vid);
3224 if (!new_vfid) {
3225 new_vfid = mlxsw_sp_vfid_create(mlxsw_sp, vid);
3226 if (IS_ERR(new_vfid)) {
3227 netdev_err(dev, "Failed to create vFID for VID=%d\n",
3228 vid);
Ido Schimmel82e6db02016-06-20 23:04:04 +02003229 return;
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01003230 }
3231 }
3232
3233 /* Invalidate existing {Port, VID} to vFID mapping and create a new
3234 * one for the new vFID.
3235 */
3236 err = mlxsw_sp_port_vid_to_fid_set(mlxsw_sp_vport,
3237 MLXSW_REG_SVFA_MT_PORT_VID_TO_FID,
3238 false,
3239 mlxsw_sp_vfid_to_fid(vfid->vfid),
3240 vid);
3241 if (err) {
3242 netdev_err(dev, "Failed to invalidate {Port, VID} to vFID=%d mapping\n",
3243 vfid->vfid);
3244 goto err_port_vid_to_fid_invalidate;
3245 }
3246
3247 err = mlxsw_sp_port_vid_to_fid_set(mlxsw_sp_vport,
3248 MLXSW_REG_SVFA_MT_PORT_VID_TO_FID,
3249 true,
3250 mlxsw_sp_vfid_to_fid(new_vfid->vfid),
3251 vid);
3252 if (err) {
3253 netdev_err(dev, "Failed to map {Port, VID} to vFID=%d\n",
3254 new_vfid->vfid);
3255 goto err_port_vid_to_fid_validate;
3256 }
3257
3258 err = mlxsw_sp_port_vid_learning_set(mlxsw_sp_vport, vid, false);
3259 if (err) {
3260 netdev_err(dev, "Failed to disable learning\n");
3261 goto err_port_vid_learning_set;
3262 }
3263
Ido Schimmel47a0a9e2016-06-20 23:04:08 +02003264 err = mlxsw_sp_vport_flood_set(mlxsw_sp_vport, vfid->vfid, false);
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01003265 if (err) {
3266 netdev_err(dev, "Failed clear to clear flooding\n");
3267 goto err_vport_flood_set;
3268 }
3269
Ido Schimmel6a9863a2016-02-15 13:19:54 +01003270 err = mlxsw_sp_port_stp_state_set(mlxsw_sp_vport, vid,
3271 MLXSW_REG_SPMS_STATE_FORWARDING);
3272 if (err) {
3273 netdev_err(dev, "Failed to set STP state\n");
3274 goto err_port_stp_state_set;
3275 }
3276
Ido Schimmel039c49a2016-01-27 15:20:18 +01003277 if (flush_fdb && mlxsw_sp_vport_fdb_flush(mlxsw_sp_vport))
3278 netdev_err(dev, "Failed to flush FDB\n");
3279
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01003280 /* Switch between the vFIDs and destroy the old one if needed. */
3281 new_vfid->nr_vports++;
3282 mlxsw_sp_vport->vport.vfid = new_vfid;
3283 vfid->nr_vports--;
3284 if (!vfid->nr_vports)
3285 mlxsw_sp_br_vfid_destroy(mlxsw_sp, vfid);
3286
3287 mlxsw_sp_vport->learning = 0;
3288 mlxsw_sp_vport->learning_sync = 0;
3289 mlxsw_sp_vport->uc_flood = 0;
3290 mlxsw_sp_vport->bridged = 0;
3291
Ido Schimmel82e6db02016-06-20 23:04:04 +02003292 return;
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01003293
Ido Schimmel6a9863a2016-02-15 13:19:54 +01003294err_port_stp_state_set:
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01003295err_vport_flood_set:
3296err_port_vid_learning_set:
3297err_port_vid_to_fid_validate:
3298err_port_vid_to_fid_invalidate:
3299 /* Rollback vFID only if new. */
3300 if (!new_vfid->nr_vports)
3301 mlxsw_sp_vfid_destroy(mlxsw_sp, new_vfid);
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01003302}
3303
3304static int mlxsw_sp_vport_bridge_join(struct mlxsw_sp_port *mlxsw_sp_vport,
3305 struct net_device *br_dev)
3306{
3307 struct mlxsw_sp_vfid *old_vfid = mlxsw_sp_vport->vport.vfid;
3308 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_vport->mlxsw_sp;
3309 u16 vid = mlxsw_sp_vport_vid_get(mlxsw_sp_vport);
3310 struct net_device *dev = mlxsw_sp_vport->dev;
3311 struct mlxsw_sp_vfid *vfid;
3312 int err;
3313
3314 vfid = mlxsw_sp_br_vfid_find(mlxsw_sp, br_dev);
3315 if (!vfid) {
3316 vfid = mlxsw_sp_br_vfid_create(mlxsw_sp, br_dev);
3317 if (IS_ERR(vfid)) {
3318 netdev_err(dev, "Failed to create bridge vFID\n");
3319 return PTR_ERR(vfid);
3320 }
3321 }
3322
Ido Schimmel47a0a9e2016-06-20 23:04:08 +02003323 err = mlxsw_sp_vport_flood_set(mlxsw_sp_vport, vfid->vfid, true);
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01003324 if (err) {
3325 netdev_err(dev, "Failed to setup flooding for vFID=%d\n",
3326 vfid->vfid);
3327 goto err_port_flood_set;
3328 }
3329
3330 err = mlxsw_sp_port_vid_learning_set(mlxsw_sp_vport, vid, true);
3331 if (err) {
3332 netdev_err(dev, "Failed to enable learning\n");
3333 goto err_port_vid_learning_set;
3334 }
3335
3336 /* We need to invalidate existing {Port, VID} to vFID mapping and
3337 * create a new one for the bridge's vFID.
3338 */
3339 err = mlxsw_sp_port_vid_to_fid_set(mlxsw_sp_vport,
3340 MLXSW_REG_SVFA_MT_PORT_VID_TO_FID,
3341 false,
3342 mlxsw_sp_vfid_to_fid(old_vfid->vfid),
3343 vid);
3344 if (err) {
3345 netdev_err(dev, "Failed to invalidate {Port, VID} to vFID=%d mapping\n",
3346 old_vfid->vfid);
3347 goto err_port_vid_to_fid_invalidate;
3348 }
3349
3350 err = mlxsw_sp_port_vid_to_fid_set(mlxsw_sp_vport,
3351 MLXSW_REG_SVFA_MT_PORT_VID_TO_FID,
3352 true,
3353 mlxsw_sp_vfid_to_fid(vfid->vfid),
3354 vid);
3355 if (err) {
3356 netdev_err(dev, "Failed to map {Port, VID} to vFID=%d\n",
3357 vfid->vfid);
3358 goto err_port_vid_to_fid_validate;
3359 }
3360
3361 /* Switch between the vFIDs and destroy the old one if needed. */
3362 vfid->nr_vports++;
3363 mlxsw_sp_vport->vport.vfid = vfid;
3364 old_vfid->nr_vports--;
3365 if (!old_vfid->nr_vports)
3366 mlxsw_sp_vfid_destroy(mlxsw_sp, old_vfid);
3367
3368 mlxsw_sp_vport->learning = 1;
3369 mlxsw_sp_vport->learning_sync = 1;
3370 mlxsw_sp_vport->uc_flood = 1;
3371 mlxsw_sp_vport->bridged = 1;
3372
3373 return 0;
3374
3375err_port_vid_to_fid_validate:
3376 mlxsw_sp_port_vid_to_fid_set(mlxsw_sp_vport,
3377 MLXSW_REG_SVFA_MT_PORT_VID_TO_FID, false,
3378 mlxsw_sp_vfid_to_fid(old_vfid->vfid), vid);
3379err_port_vid_to_fid_invalidate:
3380 mlxsw_sp_port_vid_learning_set(mlxsw_sp_vport, vid, false);
3381err_port_vid_learning_set:
Ido Schimmel47a0a9e2016-06-20 23:04:08 +02003382 mlxsw_sp_vport_flood_set(mlxsw_sp_vport, vfid->vfid, false);
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01003383err_port_flood_set:
3384 if (!vfid->nr_vports)
3385 mlxsw_sp_br_vfid_destroy(mlxsw_sp, vfid);
3386 return err;
3387}
3388
3389static bool
3390mlxsw_sp_port_master_bridge_check(const struct mlxsw_sp_port *mlxsw_sp_port,
3391 const struct net_device *br_dev)
3392{
3393 struct mlxsw_sp_port *mlxsw_sp_vport;
3394
3395 list_for_each_entry(mlxsw_sp_vport, &mlxsw_sp_port->vports_list,
3396 vport.list) {
3397 if (mlxsw_sp_vport_br_get(mlxsw_sp_vport) == br_dev)
3398 return false;
3399 }
3400
3401 return true;
3402}
3403
3404static int mlxsw_sp_netdevice_vport_event(struct net_device *dev,
3405 unsigned long event, void *ptr,
3406 u16 vid)
3407{
3408 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
3409 struct netdev_notifier_changeupper_info *info = ptr;
3410 struct mlxsw_sp_port *mlxsw_sp_vport;
3411 struct net_device *upper_dev;
Ido Schimmel80bedf12016-06-20 23:03:59 +02003412 int err = 0;
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01003413
3414 mlxsw_sp_vport = mlxsw_sp_port_vport_find(mlxsw_sp_port, vid);
3415
3416 switch (event) {
3417 case NETDEV_PRECHANGEUPPER:
3418 upper_dev = info->upper_dev;
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01003419 if (!netif_is_bridge_master(upper_dev))
Ido Schimmel80bedf12016-06-20 23:03:59 +02003420 return -EINVAL;
Ido Schimmelddbe9932016-06-20 23:04:02 +02003421 if (!info->linking)
3422 break;
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01003423 /* We can't have multiple VLAN interfaces configured on
3424 * the same port and being members in the same bridge.
3425 */
3426 if (!mlxsw_sp_port_master_bridge_check(mlxsw_sp_port,
3427 upper_dev))
Ido Schimmel80bedf12016-06-20 23:03:59 +02003428 return -EINVAL;
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01003429 break;
3430 case NETDEV_CHANGEUPPER:
3431 upper_dev = info->upper_dev;
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01003432 if (info->linking) {
Ido Schimmel423b9372016-06-20 23:04:03 +02003433 if (WARN_ON(!mlxsw_sp_vport))
Ido Schimmel80bedf12016-06-20 23:03:59 +02003434 return -EINVAL;
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01003435 err = mlxsw_sp_vport_bridge_join(mlxsw_sp_vport,
3436 upper_dev);
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01003437 } else {
3438 /* We ignore bridge's unlinking notifications if vPort
3439 * is gone, since we already left the bridge when the
3440 * VLAN device was unlinked from the real device.
3441 */
3442 if (!mlxsw_sp_vport)
Ido Schimmel80bedf12016-06-20 23:03:59 +02003443 return 0;
Ido Schimmel82e6db02016-06-20 23:04:04 +02003444 mlxsw_sp_vport_bridge_leave(mlxsw_sp_vport, upper_dev,
3445 true);
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01003446 }
3447 }
3448
Ido Schimmel80bedf12016-06-20 23:03:59 +02003449 return err;
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01003450}
3451
Ido Schimmel272c4472015-12-15 16:03:47 +01003452static int mlxsw_sp_netdevice_lag_vport_event(struct net_device *lag_dev,
3453 unsigned long event, void *ptr,
3454 u16 vid)
3455{
3456 struct net_device *dev;
3457 struct list_head *iter;
3458 int ret;
3459
3460 netdev_for_each_lower_dev(lag_dev, dev, iter) {
3461 if (mlxsw_sp_port_dev_check(dev)) {
3462 ret = mlxsw_sp_netdevice_vport_event(dev, event, ptr,
3463 vid);
Ido Schimmel80bedf12016-06-20 23:03:59 +02003464 if (ret)
Ido Schimmel272c4472015-12-15 16:03:47 +01003465 return ret;
3466 }
3467 }
3468
Ido Schimmel80bedf12016-06-20 23:03:59 +02003469 return 0;
Ido Schimmel272c4472015-12-15 16:03:47 +01003470}
3471
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01003472static int mlxsw_sp_netdevice_vlan_event(struct net_device *vlan_dev,
3473 unsigned long event, void *ptr)
3474{
3475 struct net_device *real_dev = vlan_dev_real_dev(vlan_dev);
3476 u16 vid = vlan_dev_vlan_id(vlan_dev);
3477
Ido Schimmel272c4472015-12-15 16:03:47 +01003478 if (mlxsw_sp_port_dev_check(real_dev))
3479 return mlxsw_sp_netdevice_vport_event(real_dev, event, ptr,
3480 vid);
3481 else if (netif_is_lag_master(real_dev))
3482 return mlxsw_sp_netdevice_lag_vport_event(real_dev, event, ptr,
3483 vid);
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01003484
Ido Schimmel80bedf12016-06-20 23:03:59 +02003485 return 0;
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01003486}
3487
Jiri Pirko0d65fc12015-12-03 12:12:28 +01003488static int mlxsw_sp_netdevice_event(struct notifier_block *unused,
3489 unsigned long event, void *ptr)
3490{
3491 struct net_device *dev = netdev_notifier_info_to_dev(ptr);
Ido Schimmel80bedf12016-06-20 23:03:59 +02003492 int err = 0;
Jiri Pirko0d65fc12015-12-03 12:12:28 +01003493
3494 if (mlxsw_sp_port_dev_check(dev))
Ido Schimmel80bedf12016-06-20 23:03:59 +02003495 err = mlxsw_sp_netdevice_port_event(dev, event, ptr);
3496 else if (netif_is_lag_master(dev))
3497 err = mlxsw_sp_netdevice_lag_event(dev, event, ptr);
3498 else if (is_vlan_dev(dev))
3499 err = mlxsw_sp_netdevice_vlan_event(dev, event, ptr);
Jiri Pirko0d65fc12015-12-03 12:12:28 +01003500
Ido Schimmel80bedf12016-06-20 23:03:59 +02003501 return notifier_from_errno(err);
Jiri Pirko0d65fc12015-12-03 12:12:28 +01003502}
3503
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003504static struct notifier_block mlxsw_sp_netdevice_nb __read_mostly = {
3505 .notifier_call = mlxsw_sp_netdevice_event,
3506};
3507
3508static int __init mlxsw_sp_module_init(void)
3509{
3510 int err;
3511
3512 register_netdevice_notifier(&mlxsw_sp_netdevice_nb);
3513 err = mlxsw_core_driver_register(&mlxsw_sp_driver);
3514 if (err)
3515 goto err_core_driver_register;
3516 return 0;
3517
3518err_core_driver_register:
3519 unregister_netdevice_notifier(&mlxsw_sp_netdevice_nb);
3520 return err;
3521}
3522
3523static void __exit mlxsw_sp_module_exit(void)
3524{
3525 mlxsw_core_driver_unregister(&mlxsw_sp_driver);
3526 unregister_netdevice_notifier(&mlxsw_sp_netdevice_nb);
3527}
3528
3529module_init(mlxsw_sp_module_init);
3530module_exit(mlxsw_sp_module_exit);
3531
3532MODULE_LICENSE("Dual BSD/GPL");
3533MODULE_AUTHOR("Jiri Pirko <jiri@mellanox.com>");
3534MODULE_DESCRIPTION("Mellanox Spectrum driver");
3535MODULE_MLXSW_DRIVER_ALIAS(MLXSW_DEVICE_KIND_SPECTRUM);