Catalin Marinas | bbe8888 | 2007-05-08 22:27:46 +0100 | [diff] [blame] | 1 | /* |
| 2 | * linux/arch/arm/mm/proc-v7.S |
| 3 | * |
| 4 | * Copyright (C) 2001 Deep Blue Solutions Ltd. |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License version 2 as |
| 8 | * published by the Free Software Foundation. |
| 9 | * |
| 10 | * This is the "shell" of the ARMv7 processor support. |
| 11 | */ |
Tim Abbott | 991da17 | 2009-04-27 14:02:22 -0400 | [diff] [blame] | 12 | #include <linux/init.h> |
Catalin Marinas | bbe8888 | 2007-05-08 22:27:46 +0100 | [diff] [blame] | 13 | #include <linux/linkage.h> |
| 14 | #include <asm/assembler.h> |
| 15 | #include <asm/asm-offsets.h> |
Russell King | 5ec9407 | 2008-09-07 19:15:31 +0100 | [diff] [blame] | 16 | #include <asm/hwcap.h> |
Catalin Marinas | bbe8888 | 2007-05-08 22:27:46 +0100 | [diff] [blame] | 17 | #include <asm/pgtable-hwdef.h> |
| 18 | #include <asm/pgtable.h> |
| 19 | |
| 20 | #include "proc-macros.S" |
| 21 | |
Catalin Marinas | 1b6ba46 | 2011-11-22 17:30:29 +0000 | [diff] [blame] | 22 | #ifdef CONFIG_ARM_LPAE |
| 23 | #include "proc-v7-3level.S" |
| 24 | #else |
Catalin Marinas | 8d2cd3a | 2011-11-22 17:30:28 +0000 | [diff] [blame] | 25 | #include "proc-v7-2level.S" |
Catalin Marinas | 1b6ba46 | 2011-11-22 17:30:29 +0000 | [diff] [blame] | 26 | #endif |
Jon Callan | 73b63ef | 2008-11-06 13:23:09 +0000 | [diff] [blame] | 27 | |
Catalin Marinas | bbe8888 | 2007-05-08 22:27:46 +0100 | [diff] [blame] | 28 | ENTRY(cpu_v7_proc_init) |
| 29 | mov pc, lr |
Catalin Marinas | 93ed397 | 2008-08-28 11:22:32 +0100 | [diff] [blame] | 30 | ENDPROC(cpu_v7_proc_init) |
Catalin Marinas | bbe8888 | 2007-05-08 22:27:46 +0100 | [diff] [blame] | 31 | |
| 32 | ENTRY(cpu_v7_proc_fin) |
Tony Lindgren | 1f667c6 | 2010-01-19 17:01:33 +0100 | [diff] [blame] | 33 | mrc p15, 0, r0, c1, c0, 0 @ ctrl register |
| 34 | bic r0, r0, #0x1000 @ ...i............ |
| 35 | bic r0, r0, #0x0006 @ .............ca. |
| 36 | mcr p15, 0, r0, c1, c0, 0 @ disable caches |
Russell King | 9ca03a2 | 2010-07-26 12:22:12 +0100 | [diff] [blame] | 37 | mov pc, lr |
Catalin Marinas | 93ed397 | 2008-08-28 11:22:32 +0100 | [diff] [blame] | 38 | ENDPROC(cpu_v7_proc_fin) |
Catalin Marinas | bbe8888 | 2007-05-08 22:27:46 +0100 | [diff] [blame] | 39 | |
| 40 | /* |
| 41 | * cpu_v7_reset(loc) |
| 42 | * |
| 43 | * Perform a soft reset of the system. Put the CPU into the |
| 44 | * same state as it would be if it had been reset, and branch |
| 45 | * to what would be the reset vector. |
| 46 | * |
| 47 | * - loc - location to jump to for soft reset |
Will Deacon | f4daf06 | 2011-06-06 12:27:34 +0100 | [diff] [blame] | 48 | * |
| 49 | * This code must be executed using a flat identity mapping with |
| 50 | * caches disabled. |
Catalin Marinas | bbe8888 | 2007-05-08 22:27:46 +0100 | [diff] [blame] | 51 | */ |
| 52 | .align 5 |
Will Deacon | 1a4baaf | 2011-11-15 13:25:04 +0000 | [diff] [blame] | 53 | .pushsection .idmap.text, "ax" |
Catalin Marinas | bbe8888 | 2007-05-08 22:27:46 +0100 | [diff] [blame] | 54 | ENTRY(cpu_v7_reset) |
Will Deacon | f4daf06 | 2011-06-06 12:27:34 +0100 | [diff] [blame] | 55 | mrc p15, 0, r1, c1, c0, 0 @ ctrl register |
| 56 | bic r1, r1, #0x1 @ ...............m |
Will Deacon | 0f81bb6 | 2011-08-26 16:34:51 +0100 | [diff] [blame] | 57 | THUMB( bic r1, r1, #1 << 30 ) @ SCTLR.TE (Thumb exceptions) |
Will Deacon | f4daf06 | 2011-06-06 12:27:34 +0100 | [diff] [blame] | 58 | mcr p15, 0, r1, c1, c0, 0 @ disable MMU |
| 59 | isb |
Dave Martin | 153cd8e | 2012-10-16 11:54:00 +0100 | [diff] [blame] | 60 | bx r0 |
Catalin Marinas | 93ed397 | 2008-08-28 11:22:32 +0100 | [diff] [blame] | 61 | ENDPROC(cpu_v7_reset) |
Will Deacon | 1a4baaf | 2011-11-15 13:25:04 +0000 | [diff] [blame] | 62 | .popsection |
Catalin Marinas | bbe8888 | 2007-05-08 22:27:46 +0100 | [diff] [blame] | 63 | |
| 64 | /* |
| 65 | * cpu_v7_do_idle() |
| 66 | * |
| 67 | * Idle the processor (eg, wait for interrupt). |
| 68 | * |
| 69 | * IRQs are already disabled. |
| 70 | */ |
| 71 | ENTRY(cpu_v7_do_idle) |
Catalin Marinas | 8553cb6 | 2008-11-10 14:14:11 +0000 | [diff] [blame] | 72 | dsb @ WFI may enter a low-power mode |
Catalin Marinas | 000b502 | 2008-10-03 11:09:10 +0100 | [diff] [blame] | 73 | wfi |
Catalin Marinas | bbe8888 | 2007-05-08 22:27:46 +0100 | [diff] [blame] | 74 | mov pc, lr |
Catalin Marinas | 93ed397 | 2008-08-28 11:22:32 +0100 | [diff] [blame] | 75 | ENDPROC(cpu_v7_do_idle) |
Catalin Marinas | bbe8888 | 2007-05-08 22:27:46 +0100 | [diff] [blame] | 76 | |
| 77 | ENTRY(cpu_v7_dcache_clean_area) |
Will Deacon | bf3f0f3 | 2013-07-15 14:26:19 +0100 | [diff] [blame] | 78 | ALT_SMP(W(nop)) @ MP extensions imply L1 PTW |
| 79 | ALT_UP_B(1f) |
| 80 | mov pc, lr |
| 81 | 1: dcache_line_size r2, r3 |
| 82 | 2: mcr p15, 0, r0, c7, c10, 1 @ clean D entry |
Catalin Marinas | bbe8888 | 2007-05-08 22:27:46 +0100 | [diff] [blame] | 83 | add r0, r0, r2 |
| 84 | subs r1, r1, r2 |
Will Deacon | bf3f0f3 | 2013-07-15 14:26:19 +0100 | [diff] [blame] | 85 | bhi 2b |
Will Deacon | 6abdd49 | 2013-05-13 12:01:12 +0100 | [diff] [blame] | 86 | dsb ishst |
Catalin Marinas | bbe8888 | 2007-05-08 22:27:46 +0100 | [diff] [blame] | 87 | mov pc, lr |
Catalin Marinas | 93ed397 | 2008-08-28 11:22:32 +0100 | [diff] [blame] | 88 | ENDPROC(cpu_v7_dcache_clean_area) |
Catalin Marinas | bbe8888 | 2007-05-08 22:27:46 +0100 | [diff] [blame] | 89 | |
Dave Martin | 78a8f3c | 2011-06-23 17:26:19 +0100 | [diff] [blame] | 90 | string cpu_v7_name, "ARMv7 Processor" |
Catalin Marinas | bbe8888 | 2007-05-08 22:27:46 +0100 | [diff] [blame] | 91 | .align |
| 92 | |
Russell King | f6b0fa0 | 2011-02-06 15:48:39 +0000 | [diff] [blame] | 93 | /* Suspend/resume support: derived from arch/arm/mach-s5pv210/sleep.S */ |
| 94 | .globl cpu_v7_suspend_size |
Mahesh Sivasubramanian | f3db3f4 | 2013-11-08 23:25:20 +0100 | [diff] [blame] | 95 | .equ cpu_v7_suspend_size, 4 * 9 |
Arnd Bergmann | 15e0d9e | 2011-10-01 21:09:39 +0200 | [diff] [blame] | 96 | #ifdef CONFIG_ARM_CPU_SUSPEND |
Russell King | f6b0fa0 | 2011-02-06 15:48:39 +0000 | [diff] [blame] | 97 | ENTRY(cpu_v7_do_suspend) |
Russell King | de8e71c | 2011-08-27 22:39:09 +0100 | [diff] [blame] | 98 | stmfd sp!, {r4 - r10, lr} |
Russell King | f6b0fa0 | 2011-02-06 15:48:39 +0000 | [diff] [blame] | 99 | mrc p15, 0, r4, c13, c0, 0 @ FCSE/PID |
Russell King | 1aede68 | 2011-08-28 10:30:34 +0100 | [diff] [blame] | 100 | mrc p15, 0, r5, c13, c0, 3 @ User r/o thread ID |
| 101 | stmia r0!, {r4 - r5} |
Will Deacon | aa1aadc | 2012-02-23 13:51:38 +0000 | [diff] [blame] | 102 | #ifdef CONFIG_MMU |
Russell King | f6b0fa0 | 2011-02-06 15:48:39 +0000 | [diff] [blame] | 103 | mrc p15, 0, r6, c3, c0, 0 @ Domain ID |
Mahesh Sivasubramanian | f3db3f4 | 2013-11-08 23:25:20 +0100 | [diff] [blame] | 104 | #ifdef CONFIG_ARM_LPAE |
| 105 | mrrc p15, 1, r5, r7, c2 @ TTB 1 |
| 106 | #else |
Russell King | de8e71c | 2011-08-27 22:39:09 +0100 | [diff] [blame] | 107 | mrc p15, 0, r7, c2, c0, 1 @ TTB 1 |
Mahesh Sivasubramanian | f3db3f4 | 2013-11-08 23:25:20 +0100 | [diff] [blame] | 108 | #endif |
Catalin Marinas | 1b6ba46 | 2011-11-22 17:30:29 +0000 | [diff] [blame] | 109 | mrc p15, 0, r11, c2, c0, 2 @ TTB control register |
Will Deacon | aa1aadc | 2012-02-23 13:51:38 +0000 | [diff] [blame] | 110 | #endif |
Russell King | de8e71c | 2011-08-27 22:39:09 +0100 | [diff] [blame] | 111 | mrc p15, 0, r8, c1, c0, 0 @ Control register |
| 112 | mrc p15, 0, r9, c1, c0, 1 @ Auxiliary control register |
| 113 | mrc p15, 0, r10, c1, c0, 2 @ Co-processor access control |
Mahesh Sivasubramanian | f3db3f4 | 2013-11-08 23:25:20 +0100 | [diff] [blame] | 114 | stmia r0, {r5 - r11} |
Russell King | de8e71c | 2011-08-27 22:39:09 +0100 | [diff] [blame] | 115 | ldmfd sp!, {r4 - r10, pc} |
Russell King | f6b0fa0 | 2011-02-06 15:48:39 +0000 | [diff] [blame] | 116 | ENDPROC(cpu_v7_do_suspend) |
| 117 | |
| 118 | ENTRY(cpu_v7_do_resume) |
| 119 | mov ip, #0 |
Russell King | f6b0fa0 | 2011-02-06 15:48:39 +0000 | [diff] [blame] | 120 | mcr p15, 0, ip, c7, c5, 0 @ invalidate I cache |
Russell King | 1aede68 | 2011-08-28 10:30:34 +0100 | [diff] [blame] | 121 | mcr p15, 0, ip, c13, c0, 1 @ set reserved context ID |
| 122 | ldmia r0!, {r4 - r5} |
Russell King | f6b0fa0 | 2011-02-06 15:48:39 +0000 | [diff] [blame] | 123 | mcr p15, 0, r4, c13, c0, 0 @ FCSE/PID |
Russell King | 1aede68 | 2011-08-28 10:30:34 +0100 | [diff] [blame] | 124 | mcr p15, 0, r5, c13, c0, 3 @ User r/o thread ID |
Mahesh Sivasubramanian | f3db3f4 | 2013-11-08 23:25:20 +0100 | [diff] [blame] | 125 | ldmia r0, {r5 - r11} |
Will Deacon | aa1aadc | 2012-02-23 13:51:38 +0000 | [diff] [blame] | 126 | #ifdef CONFIG_MMU |
| 127 | mcr p15, 0, ip, c8, c7, 0 @ invalidate TLBs |
Russell King | f6b0fa0 | 2011-02-06 15:48:39 +0000 | [diff] [blame] | 128 | mcr p15, 0, r6, c3, c0, 0 @ Domain ID |
Mahesh Sivasubramanian | f3db3f4 | 2013-11-08 23:25:20 +0100 | [diff] [blame] | 129 | #ifdef CONFIG_ARM_LPAE |
| 130 | mcrr p15, 0, r1, ip, c2 @ TTB 0 |
| 131 | mcrr p15, 1, r5, r7, c2 @ TTB 1 |
| 132 | #else |
Russell King | de8e71c | 2011-08-27 22:39:09 +0100 | [diff] [blame] | 133 | ALT_SMP(orr r1, r1, #TTB_FLAGS_SMP) |
| 134 | ALT_UP(orr r1, r1, #TTB_FLAGS_UP) |
| 135 | mcr p15, 0, r1, c2, c0, 0 @ TTB 0 |
| 136 | mcr p15, 0, r7, c2, c0, 1 @ TTB 1 |
Mahesh Sivasubramanian | f3db3f4 | 2013-11-08 23:25:20 +0100 | [diff] [blame] | 137 | #endif |
Catalin Marinas | 1b6ba46 | 2011-11-22 17:30:29 +0000 | [diff] [blame] | 138 | mcr p15, 0, r11, c2, c0, 2 @ TTB control register |
Russell King | f6b0fa0 | 2011-02-06 15:48:39 +0000 | [diff] [blame] | 139 | ldr r4, =PRRR @ PRRR |
| 140 | ldr r5, =NMRR @ NMRR |
| 141 | mcr p15, 0, r4, c10, c2, 0 @ write PRRR |
| 142 | mcr p15, 0, r5, c10, c2, 1 @ write NMRR |
Will Deacon | aa1aadc | 2012-02-23 13:51:38 +0000 | [diff] [blame] | 143 | #endif /* CONFIG_MMU */ |
| 144 | mrc p15, 0, r4, c1, c0, 1 @ Read Auxiliary control register |
| 145 | teq r4, r9 @ Is it already set? |
| 146 | mcrne p15, 0, r9, c1, c0, 1 @ No, so write it |
| 147 | mcr p15, 0, r10, c1, c0, 2 @ Co-processor access control |
Russell King | f6b0fa0 | 2011-02-06 15:48:39 +0000 | [diff] [blame] | 148 | isb |
Russell King | f35235a | 2011-08-27 00:37:38 +0100 | [diff] [blame] | 149 | dsb |
Russell King | de8e71c | 2011-08-27 22:39:09 +0100 | [diff] [blame] | 150 | mov r0, r8 @ control register |
Russell King | f6b0fa0 | 2011-02-06 15:48:39 +0000 | [diff] [blame] | 151 | b cpu_resume_mmu |
| 152 | ENDPROC(cpu_v7_do_resume) |
Russell King | f6b0fa0 | 2011-02-06 15:48:39 +0000 | [diff] [blame] | 153 | #endif |
| 154 | |
Gregory CLEMENT | 3e0a07f | 2013-06-23 10:17:11 +0100 | [diff] [blame] | 155 | #ifdef CONFIG_CPU_PJ4B |
| 156 | globl_equ cpu_pj4b_switch_mm, cpu_v7_switch_mm |
| 157 | globl_equ cpu_pj4b_set_pte_ext, cpu_v7_set_pte_ext |
| 158 | globl_equ cpu_pj4b_proc_init, cpu_v7_proc_init |
| 159 | globl_equ cpu_pj4b_proc_fin, cpu_v7_proc_fin |
| 160 | globl_equ cpu_pj4b_reset, cpu_v7_reset |
| 161 | #ifdef CONFIG_PJ4B_ERRATA_4742 |
| 162 | ENTRY(cpu_pj4b_do_idle) |
| 163 | dsb @ WFI may enter a low-power mode |
| 164 | wfi |
| 165 | dsb @barrier |
| 166 | mov pc, lr |
| 167 | ENDPROC(cpu_pj4b_do_idle) |
| 168 | #else |
| 169 | globl_equ cpu_pj4b_do_idle, cpu_v7_do_idle |
| 170 | #endif |
| 171 | globl_equ cpu_pj4b_dcache_clean_area, cpu_v7_dcache_clean_area |
Gregory CLEMENT | 16c79a3 | 2014-03-28 12:21:16 +0100 | [diff] [blame] | 172 | #ifdef CONFIG_ARM_CPU_SUSPEND |
| 173 | ENTRY(cpu_pj4b_do_suspend) |
| 174 | stmfd sp!, {r6 - r10} |
| 175 | mrc p15, 1, r6, c15, c1, 0 @ save CP15 - extra features |
| 176 | mrc p15, 1, r7, c15, c2, 0 @ save CP15 - Aux Func Modes Ctrl 0 |
| 177 | mrc p15, 1, r8, c15, c1, 2 @ save CP15 - Aux Debug Modes Ctrl 2 |
| 178 | mrc p15, 1, r9, c15, c1, 1 @ save CP15 - Aux Debug Modes Ctrl 1 |
| 179 | mrc p15, 0, r10, c9, c14, 0 @ save CP15 - PMC |
| 180 | stmia r0!, {r6 - r10} |
| 181 | ldmfd sp!, {r6 - r10} |
| 182 | b cpu_v7_do_suspend |
| 183 | ENDPROC(cpu_pj4b_do_suspend) |
| 184 | |
| 185 | ENTRY(cpu_pj4b_do_resume) |
| 186 | ldmia r0!, {r6 - r10} |
| 187 | mcr p15, 1, r6, c15, c1, 0 @ save CP15 - extra features |
| 188 | mcr p15, 1, r7, c15, c2, 0 @ save CP15 - Aux Func Modes Ctrl 0 |
| 189 | mcr p15, 1, r8, c15, c1, 2 @ save CP15 - Aux Debug Modes Ctrl 2 |
| 190 | mcr p15, 1, r9, c15, c1, 1 @ save CP15 - Aux Debug Modes Ctrl 1 |
| 191 | mcr p15, 0, r10, c9, c14, 0 @ save CP15 - PMC |
| 192 | b cpu_v7_do_resume |
| 193 | ENDPROC(cpu_pj4b_do_resume) |
| 194 | #endif |
| 195 | .globl cpu_pj4b_suspend_size |
| 196 | .equ cpu_pj4b_suspend_size, 4 * 14 |
Gregory CLEMENT | 3e0a07f | 2013-06-23 10:17:11 +0100 | [diff] [blame] | 197 | |
| 198 | #endif |
| 199 | |
Catalin Marinas | bbe8888 | 2007-05-08 22:27:46 +0100 | [diff] [blame] | 200 | /* |
| 201 | * __v7_setup |
| 202 | * |
| 203 | * Initialise TLB, Caches, and MMU state ready to switch the MMU |
| 204 | * on. Return in r0 the new CP15 C1 control register setting. |
| 205 | * |
Catalin Marinas | bbe8888 | 2007-05-08 22:27:46 +0100 | [diff] [blame] | 206 | * This should be able to cover all ARMv7 cores. |
| 207 | * |
| 208 | * It is assumed that: |
| 209 | * - cache type register is implemented |
| 210 | */ |
Pawel Moll | 15eb169 | 2011-05-20 14:39:29 +0100 | [diff] [blame] | 211 | __v7_ca5mp_setup: |
Daniel Walker | 14eff18 | 2010-09-17 16:42:10 +0100 | [diff] [blame] | 212 | __v7_ca9mp_setup: |
Jonathan Austin | c90ad5c | 2012-03-15 14:27:07 +0000 | [diff] [blame] | 213 | __v7_cr7mp_setup: |
| 214 | mov r10, #(1 << 0) @ Cache/TLB ops broadcasting |
Will Deacon | 7665d9d | 2011-01-12 17:10:45 +0000 | [diff] [blame] | 215 | b 1f |
Pawel Moll | b424473 | 2011-12-09 20:00:39 +0100 | [diff] [blame] | 216 | __v7_ca7mp_setup: |
Jonathan Austin | ddb2ff7 | 2014-01-13 12:10:57 +0100 | [diff] [blame] | 217 | __v7_ca12mp_setup: |
Will Deacon | 7665d9d | 2011-01-12 17:10:45 +0000 | [diff] [blame] | 218 | __v7_ca15mp_setup: |
Will Deacon | cd000cf | 2014-05-02 17:06:02 +0100 | [diff] [blame^] | 219 | __v7_ca17mp_setup: |
Will Deacon | 7665d9d | 2011-01-12 17:10:45 +0000 | [diff] [blame] | 220 | mov r10, #0 |
| 221 | 1: |
Jon Callan | 73b63ef | 2008-11-06 13:23:09 +0000 | [diff] [blame] | 222 | #ifdef CONFIG_SMP |
Russell King | f00ec48 | 2010-09-04 10:47:48 +0100 | [diff] [blame] | 223 | ALT_SMP(mrc p15, 0, r0, c1, c0, 1) |
| 224 | ALT_UP(mov r0, #(1 << 6)) @ fake it for UP |
Tony Thompson | 1b3a02eb | 2009-11-04 12:16:38 +0000 | [diff] [blame] | 225 | tst r0, #(1 << 6) @ SMP/nAMP mode enabled? |
Will Deacon | 7665d9d | 2011-01-12 17:10:45 +0000 | [diff] [blame] | 226 | orreq r0, r0, #(1 << 6) @ Enable SMP/nAMP mode |
| 227 | orreq r0, r0, r10 @ Enable CPU-specific SMP bits |
| 228 | mcreq p15, 0, r0, c1, c0, 1 |
Jon Callan | 73b63ef | 2008-11-06 13:23:09 +0000 | [diff] [blame] | 229 | #endif |
Haojian Zhuang | d106de3 | 2013-01-05 13:57:38 +0100 | [diff] [blame] | 230 | b __v7_setup |
Gregory CLEMENT | de49019 | 2012-10-03 11:58:07 +0200 | [diff] [blame] | 231 | |
| 232 | __v7_pj4b_setup: |
| 233 | #ifdef CONFIG_CPU_PJ4B |
| 234 | |
| 235 | /* Auxiliary Debug Modes Control 1 Register */ |
| 236 | #define PJ4B_STATIC_BP (1 << 2) /* Enable Static BP */ |
| 237 | #define PJ4B_INTER_PARITY (1 << 8) /* Disable Internal Parity Handling */ |
| 238 | #define PJ4B_BCK_OFF_STREX (1 << 5) /* Enable the back off of STREX instr */ |
| 239 | #define PJ4B_CLEAN_LINE (1 << 16) /* Disable data transfer for clean line */ |
| 240 | |
| 241 | /* Auxiliary Debug Modes Control 2 Register */ |
| 242 | #define PJ4B_FAST_LDR (1 << 23) /* Disable fast LDR */ |
| 243 | #define PJ4B_SNOOP_DATA (1 << 25) /* Do not interleave write and snoop data */ |
| 244 | #define PJ4B_CWF (1 << 27) /* Disable Critical Word First feature */ |
| 245 | #define PJ4B_OUTSDNG_NC (1 << 29) /* Disable outstanding non cacheable rqst */ |
| 246 | #define PJ4B_L1_REP_RR (1 << 30) /* L1 replacement - Strict round robin */ |
| 247 | #define PJ4B_AUX_DBG_CTRL2 (PJ4B_SNOOP_DATA | PJ4B_CWF |\ |
| 248 | PJ4B_OUTSDNG_NC | PJ4B_L1_REP_RR) |
| 249 | |
| 250 | /* Auxiliary Functional Modes Control Register 0 */ |
| 251 | #define PJ4B_SMP_CFB (1 << 1) /* Set SMP mode. Join the coherency fabric */ |
| 252 | #define PJ4B_L1_PAR_CHK (1 << 2) /* Support L1 parity checking */ |
| 253 | #define PJ4B_BROADCAST_CACHE (1 << 8) /* Broadcast Cache and TLB maintenance */ |
| 254 | |
| 255 | /* Auxiliary Debug Modes Control 0 Register */ |
| 256 | #define PJ4B_WFI_WFE (1 << 22) /* WFI/WFE - serve the DVM and back to idle */ |
| 257 | |
| 258 | /* Auxiliary Debug Modes Control 1 Register */ |
| 259 | mrc p15, 1, r0, c15, c1, 1 |
| 260 | orr r0, r0, #PJ4B_CLEAN_LINE |
| 261 | orr r0, r0, #PJ4B_BCK_OFF_STREX |
| 262 | orr r0, r0, #PJ4B_INTER_PARITY |
| 263 | bic r0, r0, #PJ4B_STATIC_BP |
| 264 | mcr p15, 1, r0, c15, c1, 1 |
| 265 | |
| 266 | /* Auxiliary Debug Modes Control 2 Register */ |
| 267 | mrc p15, 1, r0, c15, c1, 2 |
| 268 | bic r0, r0, #PJ4B_FAST_LDR |
| 269 | orr r0, r0, #PJ4B_AUX_DBG_CTRL2 |
| 270 | mcr p15, 1, r0, c15, c1, 2 |
| 271 | |
| 272 | /* Auxiliary Functional Modes Control Register 0 */ |
| 273 | mrc p15, 1, r0, c15, c2, 0 |
| 274 | #ifdef CONFIG_SMP |
| 275 | orr r0, r0, #PJ4B_SMP_CFB |
| 276 | #endif |
| 277 | orr r0, r0, #PJ4B_L1_PAR_CHK |
| 278 | orr r0, r0, #PJ4B_BROADCAST_CACHE |
| 279 | mcr p15, 1, r0, c15, c2, 0 |
| 280 | |
| 281 | /* Auxiliary Debug Modes Control 0 Register */ |
| 282 | mrc p15, 1, r0, c15, c1, 0 |
| 283 | orr r0, r0, #PJ4B_WFI_WFE |
| 284 | mcr p15, 1, r0, c15, c1, 0 |
| 285 | |
| 286 | #endif /* CONFIG_CPU_PJ4B */ |
| 287 | |
Daniel Walker | 14eff18 | 2010-09-17 16:42:10 +0100 | [diff] [blame] | 288 | __v7_setup: |
Catalin Marinas | bbe8888 | 2007-05-08 22:27:46 +0100 | [diff] [blame] | 289 | adr r12, __v7_setup_stack @ the local stack |
| 290 | stmia r12, {r0-r5, r7, r9, r11, lr} |
Santosh Shilimkar | 6323fa2 | 2012-09-10 15:07:26 +0530 | [diff] [blame] | 291 | bl v7_flush_dcache_louis |
Catalin Marinas | bbe8888 | 2007-05-08 22:27:46 +0100 | [diff] [blame] | 292 | ldmia r12, {r0-r5, r7, r9, r11, lr} |
Russell King | 1946d6e | 2009-06-01 12:50:33 +0100 | [diff] [blame] | 293 | |
| 294 | mrc p15, 0, r0, c0, c0, 0 @ read main ID register |
| 295 | and r10, r0, #0xff000000 @ ARM? |
| 296 | teq r10, #0x41000000 |
Will Deacon | 9f05027 | 2010-09-14 09:51:43 +0100 | [diff] [blame] | 297 | bne 3f |
Russell King | 1946d6e | 2009-06-01 12:50:33 +0100 | [diff] [blame] | 298 | and r5, r0, #0x00f00000 @ variant |
| 299 | and r6, r0, #0x0000000f @ revision |
Will Deacon | 6491848 | 2010-09-14 09:50:03 +0100 | [diff] [blame] | 300 | orr r6, r6, r5, lsr #20-4 @ combine variant and revision |
| 301 | ubfx r0, r0, #4, #12 @ primary part number |
Russell King | 1946d6e | 2009-06-01 12:50:33 +0100 | [diff] [blame] | 302 | |
Will Deacon | 6491848 | 2010-09-14 09:50:03 +0100 | [diff] [blame] | 303 | /* Cortex-A8 Errata */ |
| 304 | ldr r10, =0x00000c08 @ Cortex-A8 primary part number |
| 305 | teq r0, r10 |
| 306 | bne 2f |
Rob Herring | 62e4d35 | 2012-12-21 22:42:40 +0100 | [diff] [blame] | 307 | #if defined(CONFIG_ARM_ERRATA_430973) && !defined(CONFIG_ARCH_MULTIPLATFORM) |
| 308 | |
Russell King | 1946d6e | 2009-06-01 12:50:33 +0100 | [diff] [blame] | 309 | teq r5, #0x00100000 @ only present in r1p* |
| 310 | mrceq p15, 0, r10, c1, c0, 1 @ read aux control register |
| 311 | orreq r10, r10, #(1 << 6) @ set IBE to 1 |
| 312 | mcreq p15, 0, r10, c1, c0, 1 @ write aux control register |
Catalin Marinas | 7ce236f | 2009-04-30 17:06:09 +0100 | [diff] [blame] | 313 | #endif |
Catalin Marinas | 855c551 | 2009-04-30 17:06:15 +0100 | [diff] [blame] | 314 | #ifdef CONFIG_ARM_ERRATA_458693 |
Will Deacon | 6491848 | 2010-09-14 09:50:03 +0100 | [diff] [blame] | 315 | teq r6, #0x20 @ only present in r2p0 |
Russell King | 1946d6e | 2009-06-01 12:50:33 +0100 | [diff] [blame] | 316 | mrceq p15, 0, r10, c1, c0, 1 @ read aux control register |
| 317 | orreq r10, r10, #(1 << 5) @ set L1NEON to 1 |
| 318 | orreq r10, r10, #(1 << 9) @ set PLDNOP to 1 |
| 319 | mcreq p15, 0, r10, c1, c0, 1 @ write aux control register |
Catalin Marinas | 855c551 | 2009-04-30 17:06:15 +0100 | [diff] [blame] | 320 | #endif |
Catalin Marinas | 0516e46 | 2009-04-30 17:06:20 +0100 | [diff] [blame] | 321 | #ifdef CONFIG_ARM_ERRATA_460075 |
Will Deacon | 6491848 | 2010-09-14 09:50:03 +0100 | [diff] [blame] | 322 | teq r6, #0x20 @ only present in r2p0 |
Russell King | 1946d6e | 2009-06-01 12:50:33 +0100 | [diff] [blame] | 323 | mrceq p15, 1, r10, c9, c0, 2 @ read L2 cache aux ctrl register |
| 324 | tsteq r10, #1 << 22 |
| 325 | orreq r10, r10, #(1 << 22) @ set the Write Allocate disable bit |
| 326 | mcreq p15, 1, r10, c9, c0, 2 @ write the L2 cache aux ctrl register |
Catalin Marinas | 0516e46 | 2009-04-30 17:06:20 +0100 | [diff] [blame] | 327 | #endif |
Will Deacon | 9f05027 | 2010-09-14 09:51:43 +0100 | [diff] [blame] | 328 | b 3f |
Russell King | 1946d6e | 2009-06-01 12:50:33 +0100 | [diff] [blame] | 329 | |
Will Deacon | 9f05027 | 2010-09-14 09:51:43 +0100 | [diff] [blame] | 330 | /* Cortex-A9 Errata */ |
| 331 | 2: ldr r10, =0x00000c09 @ Cortex-A9 primary part number |
| 332 | teq r0, r10 |
| 333 | bne 3f |
| 334 | #ifdef CONFIG_ARM_ERRATA_742230 |
| 335 | cmp r6, #0x22 @ only present up to r2p2 |
| 336 | mrcle p15, 0, r10, c15, c0, 1 @ read diagnostic register |
| 337 | orrle r10, r10, #1 << 4 @ set bit #4 |
| 338 | mcrle p15, 0, r10, c15, c0, 1 @ write diagnostic register |
| 339 | #endif |
Will Deacon | a672e99 | 2010-09-14 09:53:02 +0100 | [diff] [blame] | 340 | #ifdef CONFIG_ARM_ERRATA_742231 |
| 341 | teq r6, #0x20 @ present in r2p0 |
| 342 | teqne r6, #0x21 @ present in r2p1 |
| 343 | teqne r6, #0x22 @ present in r2p2 |
| 344 | mrceq p15, 0, r10, c15, c0, 1 @ read diagnostic register |
| 345 | orreq r10, r10, #1 << 12 @ set bit #12 |
| 346 | orreq r10, r10, #1 << 22 @ set bit #22 |
| 347 | mcreq p15, 0, r10, c15, c0, 1 @ write diagnostic register |
| 348 | #endif |
Will Deacon | 475d92f | 2010-09-28 14:02:02 +0100 | [diff] [blame] | 349 | #ifdef CONFIG_ARM_ERRATA_743622 |
Will Deacon | efbc74a | 2012-02-24 12:12:38 +0100 | [diff] [blame] | 350 | teq r5, #0x00200000 @ only present in r2p* |
Will Deacon | 475d92f | 2010-09-28 14:02:02 +0100 | [diff] [blame] | 351 | mrceq p15, 0, r10, c15, c0, 1 @ read diagnostic register |
| 352 | orreq r10, r10, #1 << 6 @ set bit #6 |
| 353 | mcreq p15, 0, r10, c15, c0, 1 @ write diagnostic register |
| 354 | #endif |
Dave Martin | ba90c51 | 2011-12-08 13:41:06 +0100 | [diff] [blame] | 355 | #if defined(CONFIG_ARM_ERRATA_751472) && defined(CONFIG_SMP) |
| 356 | ALT_SMP(cmp r6, #0x30) @ present prior to r3p0 |
| 357 | ALT_UP_B(1f) |
Will Deacon | 9a27c27 | 2011-02-18 16:36:35 +0100 | [diff] [blame] | 358 | mrclt p15, 0, r10, c15, c0, 1 @ read diagnostic register |
| 359 | orrlt r10, r10, #1 << 11 @ set bit #11 |
| 360 | mcrlt p15, 0, r10, c15, c0, 1 @ write diagnostic register |
Dave Martin | ba90c51 | 2011-12-08 13:41:06 +0100 | [diff] [blame] | 361 | 1: |
Will Deacon | 9a27c27 | 2011-02-18 16:36:35 +0100 | [diff] [blame] | 362 | #endif |
Will Deacon | 9f05027 | 2010-09-14 09:51:43 +0100 | [diff] [blame] | 363 | |
Will Deacon | 84b6504 | 2013-08-20 17:29:55 +0100 | [diff] [blame] | 364 | /* Cortex-A15 Errata */ |
| 365 | 3: ldr r10, =0x00000c0f @ Cortex-A15 primary part number |
| 366 | teq r0, r10 |
| 367 | bne 4f |
| 368 | |
| 369 | #ifdef CONFIG_ARM_ERRATA_773022 |
| 370 | cmp r6, #0x4 @ only present up to r0p4 |
| 371 | mrcle p15, 0, r10, c1, c0, 1 @ read aux control register |
| 372 | orrle r10, r10, #1 << 1 @ disable loop buffer |
| 373 | mcrle p15, 0, r10, c1, c0, 1 @ write aux control register |
| 374 | #endif |
| 375 | |
| 376 | 4: mov r10, #0 |
Catalin Marinas | bbe8888 | 2007-05-08 22:27:46 +0100 | [diff] [blame] | 377 | mcr p15, 0, r10, c7, c5, 0 @ I+BTB cache invalidate |
Catalin Marinas | 2eb8c82 | 2007-07-20 11:43:02 +0100 | [diff] [blame] | 378 | #ifdef CONFIG_MMU |
Catalin Marinas | bbe8888 | 2007-05-08 22:27:46 +0100 | [diff] [blame] | 379 | mcr p15, 0, r10, c8, c7, 0 @ invalidate I + D TLBs |
Catalin Marinas | 8d2cd3a | 2011-11-22 17:30:28 +0000 | [diff] [blame] | 380 | v7_ttb_setup r10, r4, r8, r5 @ TTBCR, TTBRx setup |
Russell King | f6b0fa0 | 2011-02-06 15:48:39 +0000 | [diff] [blame] | 381 | ldr r5, =PRRR @ PRRR |
| 382 | ldr r6, =NMRR @ NMRR |
Russell King | 3f69c0c | 2008-09-15 17:23:10 +0100 | [diff] [blame] | 383 | mcr p15, 0, r5, c10, c2, 0 @ write PRRR |
| 384 | mcr p15, 0, r6, c10, c2, 1 @ write NMRR |
Catalin Marinas | bdaaaec | 2009-07-24 12:35:06 +0100 | [diff] [blame] | 385 | #endif |
Will Deacon | bae0ca2 | 2014-02-07 19:12:20 +0100 | [diff] [blame] | 386 | dsb @ Complete invalidations |
Jonathan Austin | 078c045 | 2012-04-12 17:45:25 +0100 | [diff] [blame] | 387 | #ifndef CONFIG_ARM_THUMBEE |
| 388 | mrc p15, 0, r0, c0, c1, 0 @ read ID_PFR0 for ThumbEE |
| 389 | and r0, r0, #(0xf << 12) @ ThumbEE enabled field |
| 390 | teq r0, #(1 << 12) @ check if ThumbEE is present |
| 391 | bne 1f |
| 392 | mov r5, #0 |
| 393 | mcr p14, 6, r5, c1, c0, 0 @ Initialize TEEHBR to 0 |
| 394 | mrc p14, 6, r0, c0, c0, 0 @ load TEECR |
| 395 | orr r0, r0, #1 @ set the 1st bit in order to |
| 396 | mcr p14, 6, r0, c0, c0, 0 @ stop userspace TEEHBR access |
| 397 | 1: |
| 398 | #endif |
Catalin Marinas | 2eb8c82 | 2007-07-20 11:43:02 +0100 | [diff] [blame] | 399 | adr r5, v7_crval |
| 400 | ldmia r5, {r5, r6} |
Ben Dooks | 457c240 | 2013-02-12 18:59:57 +0000 | [diff] [blame] | 401 | ARM_BE8(orr r6, r6, #1 << 25) @ big-endian page tables |
Leif Lindholm | 64d2dc3 | 2010-09-16 18:00:47 +0100 | [diff] [blame] | 402 | #ifdef CONFIG_SWP_EMULATE |
| 403 | orr r5, r5, #(1 << 10) @ set SW bit in "clear" |
| 404 | bic r6, r6, #(1 << 10) @ clear it in "mmuset" |
| 405 | #endif |
Catalin Marinas | 2eb8c82 | 2007-07-20 11:43:02 +0100 | [diff] [blame] | 406 | mrc p15, 0, r0, c1, c0, 0 @ read control register |
| 407 | bic r0, r0, r5 @ clear bits them |
| 408 | orr r0, r0, r6 @ set them |
Catalin Marinas | 347c8b7 | 2009-07-24 12:32:56 +0100 | [diff] [blame] | 409 | THUMB( orr r0, r0, #1 << 30 ) @ Thumb exceptions |
Catalin Marinas | bbe8888 | 2007-05-08 22:27:46 +0100 | [diff] [blame] | 410 | mov pc, lr @ return to head.S:__ret |
Catalin Marinas | 93ed397 | 2008-08-28 11:22:32 +0100 | [diff] [blame] | 411 | ENDPROC(__v7_setup) |
Catalin Marinas | bbe8888 | 2007-05-08 22:27:46 +0100 | [diff] [blame] | 412 | |
Catalin Marinas | 8d2cd3a | 2011-11-22 17:30:28 +0000 | [diff] [blame] | 413 | .align 2 |
Catalin Marinas | bbe8888 | 2007-05-08 22:27:46 +0100 | [diff] [blame] | 414 | __v7_setup_stack: |
| 415 | .space 4 * 11 @ 11 registers |
| 416 | |
Russell King | 5085f3f | 2010-10-01 15:37:05 +0100 | [diff] [blame] | 417 | __INITDATA |
| 418 | |
Dave Martin | 78a8f3c | 2011-06-23 17:26:19 +0100 | [diff] [blame] | 419 | @ define struct processor (see <asm/proc-fns.h> and proc-macros.S) |
| 420 | define_processor_functions v7, dabort=v7_early_abort, pabort=v7_pabort, suspend=1 |
Gregory CLEMENT | 3e0a07f | 2013-06-23 10:17:11 +0100 | [diff] [blame] | 421 | #ifdef CONFIG_CPU_PJ4B |
| 422 | define_processor_functions pj4b, dabort=v7_early_abort, pabort=v7_pabort, suspend=1 |
| 423 | #endif |
Catalin Marinas | bbe8888 | 2007-05-08 22:27:46 +0100 | [diff] [blame] | 424 | |
Russell King | 5085f3f | 2010-10-01 15:37:05 +0100 | [diff] [blame] | 425 | .section ".rodata" |
| 426 | |
Dave Martin | 78a8f3c | 2011-06-23 17:26:19 +0100 | [diff] [blame] | 427 | string cpu_arch_name, "armv7" |
| 428 | string cpu_elf_name, "v7" |
Catalin Marinas | bbe8888 | 2007-05-08 22:27:46 +0100 | [diff] [blame] | 429 | .align |
| 430 | |
| 431 | .section ".proc.info.init", #alloc, #execinstr |
| 432 | |
Pawel Moll | dc939cd | 2011-05-20 14:39:28 +0100 | [diff] [blame] | 433 | /* |
| 434 | * Standard v7 proc info content |
| 435 | */ |
Gregory CLEMENT | 3e0a07f | 2013-06-23 10:17:11 +0100 | [diff] [blame] | 436 | .macro __v7_proc initfunc, mm_mmuflags = 0, io_mmuflags = 0, hwcaps = 0, proc_fns = v7_processor_functions |
Pawel Moll | dc939cd | 2011-05-20 14:39:28 +0100 | [diff] [blame] | 437 | ALT_SMP(.long PMD_TYPE_SECT | PMD_SECT_AP_WRITE | PMD_SECT_AP_READ | \ |
Catalin Marinas | 1b6ba46 | 2011-11-22 17:30:29 +0000 | [diff] [blame] | 438 | PMD_SECT_AF | PMD_FLAGS_SMP | \mm_mmuflags) |
Pawel Moll | dc939cd | 2011-05-20 14:39:28 +0100 | [diff] [blame] | 439 | ALT_UP(.long PMD_TYPE_SECT | PMD_SECT_AP_WRITE | PMD_SECT_AP_READ | \ |
Catalin Marinas | 1b6ba46 | 2011-11-22 17:30:29 +0000 | [diff] [blame] | 440 | PMD_SECT_AF | PMD_FLAGS_UP | \mm_mmuflags) |
| 441 | .long PMD_TYPE_SECT | PMD_SECT_AP_WRITE | \ |
| 442 | PMD_SECT_AP_READ | PMD_SECT_AF | \io_mmuflags |
Pawel Moll | dc939cd | 2011-05-20 14:39:28 +0100 | [diff] [blame] | 443 | W(b) \initfunc |
Daniel Walker | 14eff18 | 2010-09-17 16:42:10 +0100 | [diff] [blame] | 444 | .long cpu_arch_name |
| 445 | .long cpu_elf_name |
Pawel Moll | dc939cd | 2011-05-20 14:39:28 +0100 | [diff] [blame] | 446 | .long HWCAP_SWP | HWCAP_HALF | HWCAP_THUMB | HWCAP_FAST_MULT | \ |
| 447 | HWCAP_EDSP | HWCAP_TLS | \hwcaps |
Daniel Walker | 14eff18 | 2010-09-17 16:42:10 +0100 | [diff] [blame] | 448 | .long cpu_v7_name |
Gregory CLEMENT | 3e0a07f | 2013-06-23 10:17:11 +0100 | [diff] [blame] | 449 | .long \proc_fns |
Daniel Walker | 14eff18 | 2010-09-17 16:42:10 +0100 | [diff] [blame] | 450 | .long v7wbi_tlb_fns |
| 451 | .long v6_user_fns |
| 452 | .long v7_cache_fns |
Pawel Moll | dc939cd | 2011-05-20 14:39:28 +0100 | [diff] [blame] | 453 | .endm |
| 454 | |
Catalin Marinas | 1b6ba46 | 2011-11-22 17:30:29 +0000 | [diff] [blame] | 455 | #ifndef CONFIG_ARM_LPAE |
Pawel Moll | dc939cd | 2011-05-20 14:39:28 +0100 | [diff] [blame] | 456 | /* |
Pawel Moll | 15eb169 | 2011-05-20 14:39:29 +0100 | [diff] [blame] | 457 | * ARM Ltd. Cortex A5 processor. |
| 458 | */ |
| 459 | .type __v7_ca5mp_proc_info, #object |
| 460 | __v7_ca5mp_proc_info: |
| 461 | .long 0x410fc050 |
| 462 | .long 0xff0ffff0 |
| 463 | __v7_proc __v7_ca5mp_setup |
| 464 | .size __v7_ca5mp_proc_info, . - __v7_ca5mp_proc_info |
| 465 | |
| 466 | /* |
Pawel Moll | dc939cd | 2011-05-20 14:39:28 +0100 | [diff] [blame] | 467 | * ARM Ltd. Cortex A9 processor. |
| 468 | */ |
| 469 | .type __v7_ca9mp_proc_info, #object |
| 470 | __v7_ca9mp_proc_info: |
| 471 | .long 0x410fc090 |
| 472 | .long 0xff0ffff0 |
| 473 | __v7_proc __v7_ca9mp_setup |
Daniel Walker | 14eff18 | 2010-09-17 16:42:10 +0100 | [diff] [blame] | 474 | .size __v7_ca9mp_proc_info, . - __v7_ca9mp_proc_info |
Gregory CLEMENT | de49019 | 2012-10-03 11:58:07 +0200 | [diff] [blame] | 475 | |
Gregory CLEMENT | b361d61 | 2013-04-09 13:37:20 +0100 | [diff] [blame] | 476 | #endif /* CONFIG_ARM_LPAE */ |
| 477 | |
Gregory CLEMENT | de49019 | 2012-10-03 11:58:07 +0200 | [diff] [blame] | 478 | /* |
| 479 | * Marvell PJ4B processor. |
| 480 | */ |
Gregory CLEMENT | 3e0a07f | 2013-06-23 10:17:11 +0100 | [diff] [blame] | 481 | #ifdef CONFIG_CPU_PJ4B |
Gregory CLEMENT | de49019 | 2012-10-03 11:58:07 +0200 | [diff] [blame] | 482 | .type __v7_pj4b_proc_info, #object |
| 483 | __v7_pj4b_proc_info: |
Gregory CLEMENT | 049be07 | 2013-06-10 18:05:51 +0100 | [diff] [blame] | 484 | .long 0x560f5800 |
| 485 | .long 0xff0fff00 |
Gregory CLEMENT | 3e0a07f | 2013-06-23 10:17:11 +0100 | [diff] [blame] | 486 | __v7_proc __v7_pj4b_setup, proc_fns = pj4b_processor_functions |
Gregory CLEMENT | de49019 | 2012-10-03 11:58:07 +0200 | [diff] [blame] | 487 | .size __v7_pj4b_proc_info, . - __v7_pj4b_proc_info |
Gregory CLEMENT | 3e0a07f | 2013-06-23 10:17:11 +0100 | [diff] [blame] | 488 | #endif |
Daniel Walker | 14eff18 | 2010-09-17 16:42:10 +0100 | [diff] [blame] | 489 | |
Catalin Marinas | bbe8888 | 2007-05-08 22:27:46 +0100 | [diff] [blame] | 490 | /* |
Jonathan Austin | c90ad5c | 2012-03-15 14:27:07 +0000 | [diff] [blame] | 491 | * ARM Ltd. Cortex R7 processor. |
| 492 | */ |
| 493 | .type __v7_cr7mp_proc_info, #object |
| 494 | __v7_cr7mp_proc_info: |
| 495 | .long 0x410fc170 |
| 496 | .long 0xff0ffff0 |
| 497 | __v7_proc __v7_cr7mp_setup |
| 498 | .size __v7_cr7mp_proc_info, . - __v7_cr7mp_proc_info |
| 499 | |
| 500 | /* |
Will Deacon | 868dbf9 | 2012-01-20 12:01:14 +0100 | [diff] [blame] | 501 | * ARM Ltd. Cortex A7 processor. |
| 502 | */ |
| 503 | .type __v7_ca7mp_proc_info, #object |
| 504 | __v7_ca7mp_proc_info: |
| 505 | .long 0x410fc070 |
| 506 | .long 0xff0ffff0 |
Stephen Boyd | 8164f7a | 2013-03-18 19:44:15 +0100 | [diff] [blame] | 507 | __v7_proc __v7_ca7mp_setup |
Will Deacon | 868dbf9 | 2012-01-20 12:01:14 +0100 | [diff] [blame] | 508 | .size __v7_ca7mp_proc_info, . - __v7_ca7mp_proc_info |
| 509 | |
| 510 | /* |
Jonathan Austin | ddb2ff7 | 2014-01-13 12:10:57 +0100 | [diff] [blame] | 511 | * ARM Ltd. Cortex A12 processor. |
| 512 | */ |
| 513 | .type __v7_ca12mp_proc_info, #object |
| 514 | __v7_ca12mp_proc_info: |
| 515 | .long 0x410fc0d0 |
| 516 | .long 0xff0ffff0 |
| 517 | __v7_proc __v7_ca12mp_setup |
| 518 | .size __v7_ca12mp_proc_info, . - __v7_ca12mp_proc_info |
| 519 | |
| 520 | /* |
Will Deacon | 7665d9d | 2011-01-12 17:10:45 +0000 | [diff] [blame] | 521 | * ARM Ltd. Cortex A15 processor. |
| 522 | */ |
| 523 | .type __v7_ca15mp_proc_info, #object |
| 524 | __v7_ca15mp_proc_info: |
| 525 | .long 0x410fc0f0 |
| 526 | .long 0xff0ffff0 |
Stephen Boyd | 8164f7a | 2013-03-18 19:44:15 +0100 | [diff] [blame] | 527 | __v7_proc __v7_ca15mp_setup |
Will Deacon | 7665d9d | 2011-01-12 17:10:45 +0000 | [diff] [blame] | 528 | .size __v7_ca15mp_proc_info, . - __v7_ca15mp_proc_info |
| 529 | |
| 530 | /* |
Will Deacon | cd000cf | 2014-05-02 17:06:02 +0100 | [diff] [blame^] | 531 | * ARM Ltd. Cortex A17 processor. |
| 532 | */ |
| 533 | .type __v7_ca17mp_proc_info, #object |
| 534 | __v7_ca17mp_proc_info: |
| 535 | .long 0x410fc0e0 |
| 536 | .long 0xff0ffff0 |
| 537 | __v7_proc __v7_ca17mp_setup |
| 538 | .size __v7_ca17mp_proc_info, . - __v7_ca17mp_proc_info |
| 539 | |
| 540 | /* |
Stepan Moskovchenko | 120ecfa | 2013-03-18 19:44:16 +0100 | [diff] [blame] | 541 | * Qualcomm Inc. Krait processors. |
| 542 | */ |
| 543 | .type __krait_proc_info, #object |
| 544 | __krait_proc_info: |
| 545 | .long 0x510f0400 @ Required ID value |
| 546 | .long 0xff0ffc00 @ Mask for ID |
| 547 | /* |
| 548 | * Some Krait processors don't indicate support for SDIV and UDIV |
| 549 | * instructions in the ARM instruction set, even though they actually |
| 550 | * do support them. |
| 551 | */ |
| 552 | __v7_proc __v7_setup, hwcaps = HWCAP_IDIV |
| 553 | .size __krait_proc_info, . - __krait_proc_info |
| 554 | |
| 555 | /* |
Catalin Marinas | bbe8888 | 2007-05-08 22:27:46 +0100 | [diff] [blame] | 556 | * Match any ARMv7 processor core. |
| 557 | */ |
| 558 | .type __v7_proc_info, #object |
| 559 | __v7_proc_info: |
| 560 | .long 0x000f0000 @ Required ID value |
| 561 | .long 0x000f0000 @ Mask for ID |
Pawel Moll | dc939cd | 2011-05-20 14:39:28 +0100 | [diff] [blame] | 562 | __v7_proc __v7_setup |
Catalin Marinas | bbe8888 | 2007-05-08 22:27:46 +0100 | [diff] [blame] | 563 | .size __v7_proc_info, . - __v7_proc_info |