blob: e68fdf7e42600558ff7114772b58c8ed65c3ece7 [file] [log] [blame]
Linus Torvalds1da177e2005-04-16 15:20:36 -07001/************************************************************************
ravinandan.arakali@neterion.com776bd202005-09-06 21:36:56 -07002 * s2io.h: A Linux PCI-X Ethernet driver for Neterion 10GbE Server NIC
Ramkrishna Vepa0c61ed52007-03-09 18:28:32 -08003 * Copyright(c) 2002-2007 Neterion Inc.
Linus Torvalds1da177e2005-04-16 15:20:36 -07004
5 * This software may be used and distributed according to the terms of
6 * the GNU General Public License (GPL), incorporated herein by reference.
7 * Drivers based on or derived from this code fall under the GPL and must
8 * retain the authorship, copyright and license notice. This file is not
9 * a complete program and may only be used when the entire operating
10 * system is licensed under the GPL.
11 * See the file COPYING in this distribution for more information.
12 ************************************************************************/
13#ifndef _S2IO_H
14#define _S2IO_H
15
16#define TBD 0
Jiri Slabyb7b5a122007-10-18 23:40:29 -070017#define s2BIT(loc) (0x8000000000000000ULL >> (loc))
Linus Torvalds1da177e2005-04-16 15:20:36 -070018#define vBIT(val, loc, sz) (((u64)val) << (64-loc-sz))
19#define INV(d) ((d&0xff)<<24) | (((d>>8)&0xff)<<16) | (((d>>16)&0xff)<<8)| ((d>>24)&0xff)
20
21#ifndef BOOL
22#define BOOL int
23#endif
24
25#ifndef TRUE
26#define TRUE 1
27#define FALSE 0
28#endif
29
30#undef SUCCESS
31#define SUCCESS 0
32#define FAILURE -1
Sivakumar Subramani19a60522007-01-31 13:30:49 -050033#define S2IO_MINUS_ONE 0xFFFFFFFFFFFFFFFFULL
Sreenivasa Honnurfaa4f792008-01-24 01:45:43 -080034#define S2IO_DISABLE_MAC_ENTRY 0xFFFFFFFFFFFFULL
Sivakumar Subramani19a60522007-01-31 13:30:49 -050035#define S2IO_MAX_PCI_CONFIG_SPACE_REINIT 100
Sivakumar Subramani9fc93a42007-02-24 01:57:32 -050036#define S2IO_BIT_RESET 1
37#define S2IO_BIT_SET 2
Ananda Rajubd1034f2006-04-21 19:20:22 -040038#define CHECKBIT(value, nbit) (value & (1 << nbit))
39
raghavendra.koushik@neterion.com20346722005-08-03 12:24:33 -070040/* Maximum time to flicker LED when asked to identify NIC using ethtool */
41#define MAX_FLICKER_TIME 60000 /* 60 Secs */
42
Linus Torvalds1da177e2005-04-16 15:20:36 -070043/* Maximum outstanding splits to be configured into xena. */
Ralf Baechle1ee6dd72007-01-31 14:09:29 -050044enum {
Linus Torvalds1da177e2005-04-16 15:20:36 -070045 XENA_ONE_SPLIT_TRANSACTION = 0,
46 XENA_TWO_SPLIT_TRANSACTION = 1,
47 XENA_THREE_SPLIT_TRANSACTION = 2,
48 XENA_FOUR_SPLIT_TRANSACTION = 3,
49 XENA_EIGHT_SPLIT_TRANSACTION = 4,
50 XENA_TWELVE_SPLIT_TRANSACTION = 5,
51 XENA_SIXTEEN_SPLIT_TRANSACTION = 6,
52 XENA_THIRTYTWO_SPLIT_TRANSACTION = 7
Ralf Baechle1ee6dd72007-01-31 14:09:29 -050053};
Linus Torvalds1da177e2005-04-16 15:20:36 -070054#define XENA_MAX_OUTSTANDING_SPLITS(n) (n << 4)
55
56/* OS concerned variables and constants */
raghavendra.koushik@neterion.com20346722005-08-03 12:24:33 -070057#define WATCH_DOG_TIMEOUT 15*HZ
58#define EFILL 0x1234
59#define ALIGN_SIZE 127
60#define PCIX_COMMAND_REGISTER 0x62
Linus Torvalds1da177e2005-04-16 15:20:36 -070061
62/*
63 * Debug related variables.
64 */
65/* different debug levels. */
66#define ERR_DBG 0
67#define INIT_DBG 1
68#define INFO_DBG 2
69#define TX_DBG 3
70#define INTR_DBG 4
71
72/* Global variable that defines the present debug level of the driver. */
Adrian Bunk26df54b2006-01-14 03:09:40 +010073static int debug_level = ERR_DBG;
Linus Torvalds1da177e2005-04-16 15:20:36 -070074
75/* DEBUG message print. */
76#define DBG_PRINT(dbg_level, args...) if(!(debug_level<dbg_level)) printk(args)
77
Veena Parat491abf22007-07-23 02:37:14 -040078#ifndef DMA_ERROR_CODE
79#define DMA_ERROR_CODE (~(dma_addr_t)0x0)
80#endif
81
Linus Torvalds1da177e2005-04-16 15:20:36 -070082/* Protocol assist features of the NIC */
83#define L3_CKSUM_OK 0xFFFF
84#define L4_CKSUM_OK 0xFFFF
85#define S2IO_JUMBO_SIZE 9600
86
raghavendra.koushik@neterion.com20346722005-08-03 12:24:33 -070087/* Driver statistics maintained by driver */
Ralf Baechle1ee6dd72007-01-31 14:09:29 -050088struct swStat {
raghavendra.koushik@neterion.com20346722005-08-03 12:24:33 -070089 unsigned long long single_ecc_errs;
90 unsigned long long double_ecc_errs;
Ananda Rajubd1034f2006-04-21 19:20:22 -040091 unsigned long long parity_err_cnt;
92 unsigned long long serious_err_cnt;
93 unsigned long long soft_reset_cnt;
94 unsigned long long fifo_full_cnt;
Sivakumar Subramani8116f3c2007-09-17 13:05:35 -070095 unsigned long long ring_full_cnt[8];
Ravinandan Arakali7d3d04392006-01-25 14:53:07 -050096 /* LRO statistics */
97 unsigned long long clubbed_frms_cnt;
98 unsigned long long sending_both;
99 unsigned long long outof_sequence_pkts;
100 unsigned long long flush_max_pkts;
101 unsigned long long sum_avg_pkts_aggregated;
102 unsigned long long num_aggregations;
Sreenivasa Honnurc53d4942007-05-10 04:18:54 -0400103 /* Other statistics */
104 unsigned long long mem_alloc_fail_cnt;
Veena Parat491abf22007-07-23 02:37:14 -0400105 unsigned long long pci_map_fail_cnt;
Sreenivasa Honnurc53d4942007-05-10 04:18:54 -0400106 unsigned long long watchdog_timer_cnt;
Sreenivasa Honnur491976b2007-05-10 04:22:25 -0400107 unsigned long long mem_allocated;
108 unsigned long long mem_freed;
109 unsigned long long link_up_cnt;
110 unsigned long long link_down_cnt;
111 unsigned long long link_up_time;
112 unsigned long long link_down_time;
113
114 /* Transfer Code statistics */
115 unsigned long long tx_buf_abort_cnt;
116 unsigned long long tx_desc_abort_cnt;
117 unsigned long long tx_parity_err_cnt;
118 unsigned long long tx_link_loss_cnt;
119 unsigned long long tx_list_proc_err_cnt;
120
121 unsigned long long rx_parity_err_cnt;
122 unsigned long long rx_abort_cnt;
123 unsigned long long rx_parity_abort_cnt;
124 unsigned long long rx_rda_fail_cnt;
125 unsigned long long rx_unkn_prot_cnt;
126 unsigned long long rx_fcs_err_cnt;
127 unsigned long long rx_buf_size_err_cnt;
128 unsigned long long rx_rxd_corrupt_cnt;
129 unsigned long long rx_unkn_err_cnt;
Sivakumar Subramani8116f3c2007-09-17 13:05:35 -0700130
131 /* Error/alarm statistics*/
132 unsigned long long tda_err_cnt;
133 unsigned long long pfc_err_cnt;
134 unsigned long long pcc_err_cnt;
135 unsigned long long tti_err_cnt;
136 unsigned long long lso_err_cnt;
137 unsigned long long tpa_err_cnt;
138 unsigned long long sm_err_cnt;
139 unsigned long long mac_tmac_err_cnt;
140 unsigned long long mac_rmac_err_cnt;
141 unsigned long long xgxs_txgxs_err_cnt;
142 unsigned long long xgxs_rxgxs_err_cnt;
143 unsigned long long rc_err_cnt;
144 unsigned long long prc_pcix_err_cnt;
145 unsigned long long rpa_err_cnt;
146 unsigned long long rda_err_cnt;
147 unsigned long long rti_err_cnt;
148 unsigned long long mc_err_cnt;
149
Ralf Baechle1ee6dd72007-01-31 14:09:29 -0500150};
raghavendra.koushik@neterion.com20346722005-08-03 12:24:33 -0700151
Ananda Rajubd1034f2006-04-21 19:20:22 -0400152/* Xpak releated alarm and warnings */
Ralf Baechle1ee6dd72007-01-31 14:09:29 -0500153struct xpakStat {
Ananda Rajubd1034f2006-04-21 19:20:22 -0400154 u64 alarm_transceiver_temp_high;
155 u64 alarm_transceiver_temp_low;
156 u64 alarm_laser_bias_current_high;
157 u64 alarm_laser_bias_current_low;
158 u64 alarm_laser_output_power_high;
159 u64 alarm_laser_output_power_low;
160 u64 warn_transceiver_temp_high;
161 u64 warn_transceiver_temp_low;
162 u64 warn_laser_bias_current_high;
163 u64 warn_laser_bias_current_low;
164 u64 warn_laser_output_power_high;
165 u64 warn_laser_output_power_low;
166 u64 xpak_regs_stat;
167 u32 xpak_timer_count;
Ralf Baechle1ee6dd72007-01-31 14:09:29 -0500168};
Ananda Rajubd1034f2006-04-21 19:20:22 -0400169
170
Linus Torvalds1da177e2005-04-16 15:20:36 -0700171/* The statistics block of Xena */
Ralf Baechle1ee6dd72007-01-31 14:09:29 -0500172struct stat_block {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700173/* Tx MAC statistics counters. */
Al Viro107c3a72006-08-13 15:38:04 -0400174 __le32 tmac_data_octets;
175 __le32 tmac_frms;
176 __le64 tmac_drop_frms;
177 __le32 tmac_bcst_frms;
178 __le32 tmac_mcst_frms;
179 __le64 tmac_pause_ctrl_frms;
180 __le32 tmac_ucst_frms;
181 __le32 tmac_ttl_octets;
182 __le32 tmac_any_err_frms;
183 __le32 tmac_nucst_frms;
184 __le64 tmac_ttl_less_fb_octets;
185 __le64 tmac_vld_ip_octets;
186 __le32 tmac_drop_ip;
187 __le32 tmac_vld_ip;
188 __le32 tmac_rst_tcp;
189 __le32 tmac_icmp;
190 __le64 tmac_tcp;
191 __le32 reserved_0;
192 __le32 tmac_udp;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700193
194/* Rx MAC Statistics counters. */
Al Viro107c3a72006-08-13 15:38:04 -0400195 __le32 rmac_data_octets;
196 __le32 rmac_vld_frms;
197 __le64 rmac_fcs_err_frms;
198 __le64 rmac_drop_frms;
199 __le32 rmac_vld_bcst_frms;
200 __le32 rmac_vld_mcst_frms;
201 __le32 rmac_out_rng_len_err_frms;
202 __le32 rmac_in_rng_len_err_frms;
203 __le64 rmac_long_frms;
204 __le64 rmac_pause_ctrl_frms;
205 __le64 rmac_unsup_ctrl_frms;
206 __le32 rmac_accepted_ucst_frms;
207 __le32 rmac_ttl_octets;
208 __le32 rmac_discarded_frms;
209 __le32 rmac_accepted_nucst_frms;
210 __le32 reserved_1;
211 __le32 rmac_drop_events;
212 __le64 rmac_ttl_less_fb_octets;
213 __le64 rmac_ttl_frms;
214 __le64 reserved_2;
215 __le32 rmac_usized_frms;
216 __le32 reserved_3;
217 __le32 rmac_frag_frms;
218 __le32 rmac_osized_frms;
219 __le32 reserved_4;
220 __le32 rmac_jabber_frms;
221 __le64 rmac_ttl_64_frms;
222 __le64 rmac_ttl_65_127_frms;
223 __le64 reserved_5;
224 __le64 rmac_ttl_128_255_frms;
225 __le64 rmac_ttl_256_511_frms;
226 __le64 reserved_6;
227 __le64 rmac_ttl_512_1023_frms;
228 __le64 rmac_ttl_1024_1518_frms;
229 __le32 rmac_ip;
230 __le32 reserved_7;
231 __le64 rmac_ip_octets;
232 __le32 rmac_drop_ip;
233 __le32 rmac_hdr_err_ip;
234 __le32 reserved_8;
235 __le32 rmac_icmp;
236 __le64 rmac_tcp;
237 __le32 rmac_err_drp_udp;
238 __le32 rmac_udp;
239 __le64 rmac_xgmii_err_sym;
240 __le64 rmac_frms_q0;
241 __le64 rmac_frms_q1;
242 __le64 rmac_frms_q2;
243 __le64 rmac_frms_q3;
244 __le64 rmac_frms_q4;
245 __le64 rmac_frms_q5;
246 __le64 rmac_frms_q6;
247 __le64 rmac_frms_q7;
248 __le16 rmac_full_q3;
249 __le16 rmac_full_q2;
250 __le16 rmac_full_q1;
251 __le16 rmac_full_q0;
252 __le16 rmac_full_q7;
253 __le16 rmac_full_q6;
254 __le16 rmac_full_q5;
255 __le16 rmac_full_q4;
256 __le32 reserved_9;
257 __le32 rmac_pause_cnt;
258 __le64 rmac_xgmii_data_err_cnt;
259 __le64 rmac_xgmii_ctrl_err_cnt;
260 __le32 rmac_err_tcp;
261 __le32 rmac_accepted_ip;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700262
263/* PCI/PCI-X Read transaction statistics. */
Al Viro107c3a72006-08-13 15:38:04 -0400264 __le32 new_rd_req_cnt;
265 __le32 rd_req_cnt;
266 __le32 rd_rtry_cnt;
267 __le32 new_rd_req_rtry_cnt;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700268
269/* PCI/PCI-X Write/Read transaction statistics. */
Al Viro107c3a72006-08-13 15:38:04 -0400270 __le32 wr_req_cnt;
271 __le32 wr_rtry_rd_ack_cnt;
272 __le32 new_wr_req_rtry_cnt;
273 __le32 new_wr_req_cnt;
274 __le32 wr_disc_cnt;
275 __le32 wr_rtry_cnt;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700276
277/* PCI/PCI-X Write / DMA Transaction statistics. */
Al Viro107c3a72006-08-13 15:38:04 -0400278 __le32 txp_wr_cnt;
279 __le32 rd_rtry_wr_ack_cnt;
280 __le32 txd_wr_cnt;
281 __le32 txd_rd_cnt;
282 __le32 rxd_wr_cnt;
283 __le32 rxd_rd_cnt;
284 __le32 rxf_wr_cnt;
285 __le32 txf_rd_cnt;
raghavendra.koushik@neterion.com7ba013a2005-08-03 12:29:20 -0700286
raghavendra.koushik@neterion.com541ae682005-08-03 12:36:55 -0700287/* Tx MAC statistics overflow counters. */
Al Viro107c3a72006-08-13 15:38:04 -0400288 __le32 tmac_data_octets_oflow;
289 __le32 tmac_frms_oflow;
290 __le32 tmac_bcst_frms_oflow;
291 __le32 tmac_mcst_frms_oflow;
292 __le32 tmac_ucst_frms_oflow;
293 __le32 tmac_ttl_octets_oflow;
294 __le32 tmac_any_err_frms_oflow;
295 __le32 tmac_nucst_frms_oflow;
296 __le64 tmac_vlan_frms;
297 __le32 tmac_drop_ip_oflow;
298 __le32 tmac_vld_ip_oflow;
299 __le32 tmac_rst_tcp_oflow;
300 __le32 tmac_icmp_oflow;
301 __le32 tpa_unknown_protocol;
302 __le32 tmac_udp_oflow;
303 __le32 reserved_10;
304 __le32 tpa_parse_failure;
raghavendra.koushik@neterion.com541ae682005-08-03 12:36:55 -0700305
306/* Rx MAC Statistics overflow counters. */
Al Viro107c3a72006-08-13 15:38:04 -0400307 __le32 rmac_data_octets_oflow;
308 __le32 rmac_vld_frms_oflow;
309 __le32 rmac_vld_bcst_frms_oflow;
310 __le32 rmac_vld_mcst_frms_oflow;
311 __le32 rmac_accepted_ucst_frms_oflow;
312 __le32 rmac_ttl_octets_oflow;
313 __le32 rmac_discarded_frms_oflow;
314 __le32 rmac_accepted_nucst_frms_oflow;
315 __le32 rmac_usized_frms_oflow;
316 __le32 rmac_drop_events_oflow;
317 __le32 rmac_frag_frms_oflow;
318 __le32 rmac_osized_frms_oflow;
319 __le32 rmac_ip_oflow;
320 __le32 rmac_jabber_frms_oflow;
321 __le32 rmac_icmp_oflow;
322 __le32 rmac_drop_ip_oflow;
323 __le32 rmac_err_drp_udp_oflow;
324 __le32 rmac_udp_oflow;
325 __le32 reserved_11;
326 __le32 rmac_pause_cnt_oflow;
327 __le64 rmac_ttl_1519_4095_frms;
328 __le64 rmac_ttl_4096_8191_frms;
329 __le64 rmac_ttl_8192_max_frms;
330 __le64 rmac_ttl_gt_max_frms;
331 __le64 rmac_osized_alt_frms;
332 __le64 rmac_jabber_alt_frms;
333 __le64 rmac_gt_max_alt_frms;
334 __le64 rmac_vlan_frms;
335 __le32 rmac_len_discard;
336 __le32 rmac_fcs_discard;
337 __le32 rmac_pf_discard;
338 __le32 rmac_da_discard;
339 __le32 rmac_red_discard;
340 __le32 rmac_rts_discard;
341 __le32 reserved_12;
342 __le32 rmac_ingm_full_discard;
343 __le32 reserved_13;
344 __le32 rmac_accepted_ip_oflow;
345 __le32 reserved_14;
346 __le32 link_fault_cnt;
Ananda Rajubd1034f2006-04-21 19:20:22 -0400347 u8 buffer[20];
Ralf Baechle1ee6dd72007-01-31 14:09:29 -0500348 struct swStat sw_stat;
349 struct xpakStat xpak_stat;
350};
Linus Torvalds1da177e2005-04-16 15:20:36 -0700351
Sivakumar Subramani926930b2007-02-24 01:59:39 -0500352/* Default value for 'vlan_strip_tag' configuration parameter */
353#define NO_STRIP_IN_PROMISC 2
354
raghavendra.koushik@neterion.com20346722005-08-03 12:24:33 -0700355/*
356 * Structures representing different init time configuration
Linus Torvalds1da177e2005-04-16 15:20:36 -0700357 * parameters of the NIC.
358 */
359
raghavendra.koushik@neterion.com20346722005-08-03 12:24:33 -0700360#define MAX_TX_FIFOS 8
361#define MAX_RX_RINGS 8
362
Sreenivasa Honnur6cfc4822008-02-20 17:07:51 -0500363#define FIFO_DEFAULT_NUM 5
364#define FIFO_UDP_MAX_NUM 2 /* 0 - even, 1 -odd ports */
365#define FIFO_OTHER_MAX_NUM 1
366
Surjit Reang2fda0962008-01-24 02:08:59 -0800367
Sreenivasa Honnur0cec35e2007-05-10 04:06:28 -0400368#define MAX_RX_DESC_1 (MAX_RX_RINGS * MAX_RX_BLOCKS_PER_RING * 127 )
369#define MAX_RX_DESC_2 (MAX_RX_RINGS * MAX_RX_BLOCKS_PER_RING * 85 )
370#define MAX_RX_DESC_3 (MAX_RX_RINGS * MAX_RX_BLOCKS_PER_RING * 85 )
371#define MAX_TX_DESC (MAX_AVAILABLE_TXDS)
372
raghavendra.koushik@neterion.com20346722005-08-03 12:24:33 -0700373/* FIFO mappings for all possible number of fifos configured */
Adrian Bunk26df54b2006-01-14 03:09:40 +0100374static int fifo_map[][MAX_TX_FIFOS] = {
raghavendra.koushik@neterion.com20346722005-08-03 12:24:33 -0700375 {0, 0, 0, 0, 0, 0, 0, 0},
376 {0, 0, 0, 0, 1, 1, 1, 1},
377 {0, 0, 0, 1, 1, 1, 2, 2},
378 {0, 0, 1, 1, 2, 2, 3, 3},
379 {0, 0, 1, 1, 2, 2, 3, 4},
380 {0, 0, 1, 1, 2, 3, 4, 5},
381 {0, 0, 1, 2, 3, 4, 5, 6},
382 {0, 1, 2, 3, 4, 5, 6, 7},
383};
384
Sreenivasa Honnur6cfc4822008-02-20 17:07:51 -0500385static u16 fifo_selector[MAX_TX_FIFOS] = {0, 1, 3, 3, 7, 7, 7, 7};
386
Linus Torvalds1da177e2005-04-16 15:20:36 -0700387/* Maintains Per FIFO related information. */
Ralf Baechle1ee6dd72007-01-31 14:09:29 -0500388struct tx_fifo_config {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700389#define MAX_AVAILABLE_TXDS 8192
390 u32 fifo_len; /* specifies len of FIFO upto 8192, ie no of TxDLs */
391/* Priority definition */
392#define TX_FIFO_PRI_0 0 /*Highest */
393#define TX_FIFO_PRI_1 1
394#define TX_FIFO_PRI_2 2
395#define TX_FIFO_PRI_3 3
396#define TX_FIFO_PRI_4 4
397#define TX_FIFO_PRI_5 5
398#define TX_FIFO_PRI_6 6
399#define TX_FIFO_PRI_7 7 /*lowest */
400 u8 fifo_priority; /* specifies pointer level for FIFO */
401 /* user should not set twos fifos with same pri */
402 u8 f_no_snoop;
403#define NO_SNOOP_TXD 0x01
404#define NO_SNOOP_TXD_BUFFER 0x02
Ralf Baechle1ee6dd72007-01-31 14:09:29 -0500405};
Linus Torvalds1da177e2005-04-16 15:20:36 -0700406
407
408/* Maintains per Ring related information */
Ralf Baechle1ee6dd72007-01-31 14:09:29 -0500409struct rx_ring_config {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700410 u32 num_rxd; /*No of RxDs per Rx Ring */
411#define RX_RING_PRI_0 0 /* highest */
412#define RX_RING_PRI_1 1
413#define RX_RING_PRI_2 2
414#define RX_RING_PRI_3 3
415#define RX_RING_PRI_4 4
416#define RX_RING_PRI_5 5
417#define RX_RING_PRI_6 6
418#define RX_RING_PRI_7 7 /* lowest */
419
420 u8 ring_priority; /*Specifies service priority of ring */
421 /* OSM should not set any two rings with same priority */
422 u8 ring_org; /*Organization of ring */
423#define RING_ORG_BUFF1 0x01
424#define RX_RING_ORG_BUFF3 0x03
425#define RX_RING_ORG_BUFF5 0x05
426
427 u8 f_no_snoop;
428#define NO_SNOOP_RXD 0x01
429#define NO_SNOOP_RXD_BUFFER 0x02
Ralf Baechle1ee6dd72007-01-31 14:09:29 -0500430};
Linus Torvalds1da177e2005-04-16 15:20:36 -0700431
raghavendra.koushik@neterion.com20346722005-08-03 12:24:33 -0700432/* This structure provides contains values of the tunable parameters
433 * of the H/W
Linus Torvalds1da177e2005-04-16 15:20:36 -0700434 */
435struct config_param {
436/* Tx Side */
437 u32 tx_fifo_num; /*Number of Tx FIFOs */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700438
Sreenivasa Honnur6cfc4822008-02-20 17:07:51 -0500439 /* 0-No steering, 1-Priority steering, 2-Default fifo map */
440#define NO_STEERING 0
441#define TX_PRIORITY_STEERING 0x1
442#define TX_DEFAULT_STEERING 0x2
443 u8 tx_steering_type;
444
raghavendra.koushik@neterion.com20346722005-08-03 12:24:33 -0700445 u8 fifo_mapping[MAX_TX_FIFOS];
Ralf Baechle1ee6dd72007-01-31 14:09:29 -0500446 struct tx_fifo_config tx_cfg[MAX_TX_FIFOS]; /*Per-Tx FIFO config */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700447 u32 max_txds; /*Max no. of Tx buffer descriptor per TxDL */
448 u64 tx_intr_type;
Sivakumar Subramani8abc4d52007-09-15 13:11:34 -0700449#define INTA 0
450#define MSI_X 2
451 u8 intr_type;
Sivakumar Subramanic77dd432007-08-06 05:36:28 -0400452 u8 napi;
Sivakumar Subramani8abc4d52007-09-15 13:11:34 -0700453
Linus Torvalds1da177e2005-04-16 15:20:36 -0700454 /* Specifies if Tx Intr is UTILZ or PER_LIST type. */
455
456/* Rx Side */
457 u32 rx_ring_num; /*Number of receive rings */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700458#define MAX_RX_BLOCKS_PER_RING 150
459
Ralf Baechle1ee6dd72007-01-31 14:09:29 -0500460 struct rx_ring_config rx_cfg[MAX_RX_RINGS]; /*Per-Rx Ring config */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700461
462#define HEADER_ETHERNET_II_802_3_SIZE 14
463#define HEADER_802_2_SIZE 3
464#define HEADER_SNAP_SIZE 5
465#define HEADER_VLAN_SIZE 4
466
467#define MIN_MTU 46
468#define MAX_PYLD 1500
469#define MAX_MTU (MAX_PYLD+18)
470#define MAX_MTU_VLAN (MAX_PYLD+22)
471#define MAX_PYLD_JUMBO 9600
472#define MAX_MTU_JUMBO (MAX_PYLD_JUMBO+18)
473#define MAX_MTU_JUMBO_VLAN (MAX_PYLD_JUMBO+22)
raghavendra.koushik@neterion.com20346722005-08-03 12:24:33 -0700474 u16 bus_speed;
Sreenivasa Honnurfaa4f792008-01-24 01:45:43 -0800475 int max_mc_addr; /* xena=64 herc=256 */
476 int max_mac_addr; /* xena=16 herc=64 */
477 int mc_start_offset; /* xena=16 herc=64 */
Sreenivasa Honnur3a3d5752008-02-20 16:44:07 -0500478 u8 multiq;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700479};
480
481/* Structure representing MAC Addrs */
Ralf Baechle1ee6dd72007-01-31 14:09:29 -0500482struct mac_addr {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700483 u8 mac_addr[ETH_ALEN];
Ralf Baechle1ee6dd72007-01-31 14:09:29 -0500484};
Linus Torvalds1da177e2005-04-16 15:20:36 -0700485
486/* Structure that represent every FIFO element in the BAR1
raghavendra.koushik@neterion.com20346722005-08-03 12:24:33 -0700487 * Address location.
Linus Torvalds1da177e2005-04-16 15:20:36 -0700488 */
Ralf Baechle1ee6dd72007-01-31 14:09:29 -0500489struct TxFIFO_element {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700490 u64 TxDL_Pointer;
491
492 u64 List_Control;
493#define TX_FIFO_LAST_TXD_NUM( val) vBIT(val,0,8)
Jiri Slabyb7b5a122007-10-18 23:40:29 -0700494#define TX_FIFO_FIRST_LIST s2BIT(14)
495#define TX_FIFO_LAST_LIST s2BIT(15)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700496#define TX_FIFO_FIRSTNLAST_LIST vBIT(3,14,2)
Jiri Slabyb7b5a122007-10-18 23:40:29 -0700497#define TX_FIFO_SPECIAL_FUNC s2BIT(23)
498#define TX_FIFO_DS_NO_SNOOP s2BIT(31)
499#define TX_FIFO_BUFF_NO_SNOOP s2BIT(30)
Ralf Baechle1ee6dd72007-01-31 14:09:29 -0500500};
Linus Torvalds1da177e2005-04-16 15:20:36 -0700501
502/* Tx descriptor structure */
Ralf Baechle1ee6dd72007-01-31 14:09:29 -0500503struct TxD {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700504 u64 Control_1;
505/* bit mask */
Jiri Slabyb7b5a122007-10-18 23:40:29 -0700506#define TXD_LIST_OWN_XENA s2BIT(7)
507#define TXD_T_CODE (s2BIT(12)|s2BIT(13)|s2BIT(14)|s2BIT(15))
Linus Torvalds1da177e2005-04-16 15:20:36 -0700508#define TXD_T_CODE_OK(val) (|(val & TXD_T_CODE))
509#define GET_TXD_T_CODE(val) ((val & TXD_T_CODE)<<12)
Jiri Slabyb7b5a122007-10-18 23:40:29 -0700510#define TXD_GATHER_CODE (s2BIT(22) | s2BIT(23))
511#define TXD_GATHER_CODE_FIRST s2BIT(22)
512#define TXD_GATHER_CODE_LAST s2BIT(23)
513#define TXD_TCP_LSO_EN s2BIT(30)
514#define TXD_UDP_COF_EN s2BIT(31)
515#define TXD_UFO_EN s2BIT(31) | s2BIT(30)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700516#define TXD_TCP_LSO_MSS(val) vBIT(val,34,14)
Ananda Rajufed5ecc2005-11-14 15:25:08 -0500517#define TXD_UFO_MSS(val) vBIT(val,34,14)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700518#define TXD_BUFFER0_SIZE(val) vBIT(val,48,16)
519
520 u64 Control_2;
Jiri Slabyb7b5a122007-10-18 23:40:29 -0700521#define TXD_TX_CKO_CONTROL (s2BIT(5)|s2BIT(6)|s2BIT(7))
522#define TXD_TX_CKO_IPV4_EN s2BIT(5)
523#define TXD_TX_CKO_TCP_EN s2BIT(6)
524#define TXD_TX_CKO_UDP_EN s2BIT(7)
525#define TXD_VLAN_ENABLE s2BIT(15)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700526#define TXD_VLAN_TAG(val) vBIT(val,16,16)
527#define TXD_INT_NUMBER(val) vBIT(val,34,6)
Jiri Slabyb7b5a122007-10-18 23:40:29 -0700528#define TXD_INT_TYPE_PER_LIST s2BIT(47)
529#define TXD_INT_TYPE_UTILZ s2BIT(46)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700530#define TXD_SET_MARKER vBIT(0x6,0,4)
531
532 u64 Buffer_Pointer;
533 u64 Host_Control; /* reserved for host */
Ralf Baechle1ee6dd72007-01-31 14:09:29 -0500534};
Linus Torvalds1da177e2005-04-16 15:20:36 -0700535
536/* Structure to hold the phy and virt addr of every TxDL. */
Ralf Baechle1ee6dd72007-01-31 14:09:29 -0500537struct list_info_hold {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700538 dma_addr_t list_phy_addr;
539 void *list_virt_addr;
Ralf Baechle1ee6dd72007-01-31 14:09:29 -0500540};
Linus Torvalds1da177e2005-04-16 15:20:36 -0700541
Ananda Rajuda6971d2005-10-31 16:55:31 -0500542/* Rx descriptor structure for 1 buffer mode */
Ralf Baechle1ee6dd72007-01-31 14:09:29 -0500543struct RxD_t {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700544 u64 Host_Control; /* reserved for host */
545 u64 Control_1;
Jiri Slabyb7b5a122007-10-18 23:40:29 -0700546#define RXD_OWN_XENA s2BIT(7)
547#define RXD_T_CODE (s2BIT(12)|s2BIT(13)|s2BIT(14)|s2BIT(15))
Linus Torvalds1da177e2005-04-16 15:20:36 -0700548#define RXD_FRAME_PROTO vBIT(0xFFFF,24,8)
Sreenivasa Honnurcdb5bf02008-02-20 17:09:15 -0500549#define RXD_FRAME_VLAN_TAG s2BIT(24)
Jiri Slabyb7b5a122007-10-18 23:40:29 -0700550#define RXD_FRAME_PROTO_IPV4 s2BIT(27)
551#define RXD_FRAME_PROTO_IPV6 s2BIT(28)
552#define RXD_FRAME_IP_FRAG s2BIT(29)
553#define RXD_FRAME_PROTO_TCP s2BIT(30)
554#define RXD_FRAME_PROTO_UDP s2BIT(31)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700555#define TCP_OR_UDP_FRAME (RXD_FRAME_PROTO_TCP | RXD_FRAME_PROTO_UDP)
556#define RXD_GET_L3_CKSUM(val) ((u16)(val>> 16) & 0xFFFF)
557#define RXD_GET_L4_CKSUM(val) ((u16)(val) & 0xFFFF)
558
559 u64 Control_2;
raghavendra.koushik@neterion.com5e25b9d2005-08-03 12:27:09 -0700560#define THE_RXD_MARK 0x3
561#define SET_RXD_MARKER vBIT(THE_RXD_MARK, 0, 2)
562#define GET_RXD_MARKER(ctrl) ((ctrl & SET_RXD_MARKER) >> 62)
563
Linus Torvalds1da177e2005-04-16 15:20:36 -0700564#define MASK_VLAN_TAG vBIT(0xFFFF,48,16)
565#define SET_VLAN_TAG(val) vBIT(val,48,16)
566#define SET_NUM_TAG(val) vBIT(val,16,32)
567
Ananda Rajuda6971d2005-10-31 16:55:31 -0500568
Ralf Baechle1ee6dd72007-01-31 14:09:29 -0500569};
Ananda Rajuda6971d2005-10-31 16:55:31 -0500570/* Rx descriptor structure for 1 buffer mode */
Ralf Baechle1ee6dd72007-01-31 14:09:29 -0500571struct RxD1 {
572 struct RxD_t h;
Ananda Rajuda6971d2005-10-31 16:55:31 -0500573
574#define MASK_BUFFER0_SIZE_1 vBIT(0x3FFF,2,14)
575#define SET_BUFFER0_SIZE_1(val) vBIT(val,2,14)
576#define RXD_GET_BUFFER0_SIZE_1(_Control_2) \
577 (u16)((_Control_2 & MASK_BUFFER0_SIZE_1) >> 48)
578 u64 Buffer0_ptr;
Ralf Baechle1ee6dd72007-01-31 14:09:29 -0500579};
Ananda Rajuda6971d2005-10-31 16:55:31 -0500580/* Rx descriptor structure for 3 or 2 buffer mode */
581
Ralf Baechle1ee6dd72007-01-31 14:09:29 -0500582struct RxD3 {
583 struct RxD_t h;
Ananda Rajuda6971d2005-10-31 16:55:31 -0500584
585#define MASK_BUFFER0_SIZE_3 vBIT(0xFF,2,14)
586#define MASK_BUFFER1_SIZE_3 vBIT(0xFFFF,16,16)
587#define MASK_BUFFER2_SIZE_3 vBIT(0xFFFF,32,16)
588#define SET_BUFFER0_SIZE_3(val) vBIT(val,8,8)
589#define SET_BUFFER1_SIZE_3(val) vBIT(val,16,16)
590#define SET_BUFFER2_SIZE_3(val) vBIT(val,32,16)
591#define RXD_GET_BUFFER0_SIZE_3(Control_2) \
592 (u8)((Control_2 & MASK_BUFFER0_SIZE_3) >> 48)
593#define RXD_GET_BUFFER1_SIZE_3(Control_2) \
594 (u16)((Control_2 & MASK_BUFFER1_SIZE_3) >> 32)
595#define RXD_GET_BUFFER2_SIZE_3(Control_2) \
596 (u16)((Control_2 & MASK_BUFFER2_SIZE_3) >> 16)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700597#define BUF0_LEN 40
598#define BUF1_LEN 1
Linus Torvalds1da177e2005-04-16 15:20:36 -0700599
600 u64 Buffer0_ptr;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700601 u64 Buffer1_ptr;
602 u64 Buffer2_ptr;
Ralf Baechle1ee6dd72007-01-31 14:09:29 -0500603};
Ananda Rajuda6971d2005-10-31 16:55:31 -0500604
Linus Torvalds1da177e2005-04-16 15:20:36 -0700605
raghavendra.koushik@neterion.com20346722005-08-03 12:24:33 -0700606/* Structure that represents the Rx descriptor block which contains
Linus Torvalds1da177e2005-04-16 15:20:36 -0700607 * 128 Rx descriptors.
608 */
Ralf Baechle1ee6dd72007-01-31 14:09:29 -0500609struct RxD_block {
Ananda Rajuda6971d2005-10-31 16:55:31 -0500610#define MAX_RXDS_PER_BLOCK_1 127
Ralf Baechle1ee6dd72007-01-31 14:09:29 -0500611 struct RxD1 rxd[MAX_RXDS_PER_BLOCK_1];
Linus Torvalds1da177e2005-04-16 15:20:36 -0700612
613 u64 reserved_0;
614#define END_OF_BLOCK 0xFEFFFFFFFFFFFFFFULL
raghavendra.koushik@neterion.com20346722005-08-03 12:24:33 -0700615 u64 reserved_1; /* 0xFEFFFFFFFFFFFFFF to mark last
Linus Torvalds1da177e2005-04-16 15:20:36 -0700616 * Rxd in this blk */
617 u64 reserved_2_pNext_RxD_block; /* Logical ptr to next */
618 u64 pNext_RxD_Blk_physical; /* Buff0_ptr.In a 32 bit arch
raghavendra.koushik@neterion.com20346722005-08-03 12:24:33 -0700619 * the upper 32 bits should
Linus Torvalds1da177e2005-04-16 15:20:36 -0700620 * be 0 */
Ralf Baechle1ee6dd72007-01-31 14:09:29 -0500621};
Linus Torvalds1da177e2005-04-16 15:20:36 -0700622
Linus Torvalds1da177e2005-04-16 15:20:36 -0700623#define SIZE_OF_BLOCK 4096
624
Sivakumar Subramani19a60522007-01-31 13:30:49 -0500625#define RXD_MODE_1 0 /* One Buffer mode */
Veena Parat6d517a22007-07-23 02:20:51 -0400626#define RXD_MODE_3B 1 /* Two Buffer mode */
Ananda Rajuda6971d2005-10-31 16:55:31 -0500627
raghavendra.koushik@neterion.com20346722005-08-03 12:24:33 -0700628/* Structure to hold virtual addresses of Buf0 and Buf1 in
Linus Torvalds1da177e2005-04-16 15:20:36 -0700629 * 2buf mode. */
Ralf Baechle1ee6dd72007-01-31 14:09:29 -0500630struct buffAdd {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700631 void *ba_0_org;
632 void *ba_1_org;
633 void *ba_0;
634 void *ba_1;
Ralf Baechle1ee6dd72007-01-31 14:09:29 -0500635};
Linus Torvalds1da177e2005-04-16 15:20:36 -0700636
637/* Structure which stores all the MAC control parameters */
638
raghavendra.koushik@neterion.com20346722005-08-03 12:24:33 -0700639/* This structure stores the offset of the RxD in the ring
640 * from which the Rx Interrupt processor can start picking
Linus Torvalds1da177e2005-04-16 15:20:36 -0700641 * up the RxDs for processing.
642 */
Ralf Baechle1ee6dd72007-01-31 14:09:29 -0500643struct rx_curr_get_info {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700644 u32 block_index;
645 u32 offset;
646 u32 ring_len;
Ralf Baechle1ee6dd72007-01-31 14:09:29 -0500647};
Linus Torvalds1da177e2005-04-16 15:20:36 -0700648
Ralf Baechle1ee6dd72007-01-31 14:09:29 -0500649struct rx_curr_put_info {
650 u32 block_index;
651 u32 offset;
652 u32 ring_len;
653};
Linus Torvalds1da177e2005-04-16 15:20:36 -0700654
655/* This structure stores the offset of the TxDl in the FIFO
raghavendra.koushik@neterion.com20346722005-08-03 12:24:33 -0700656 * from which the Tx Interrupt processor can start picking
Linus Torvalds1da177e2005-04-16 15:20:36 -0700657 * up the TxDLs for send complete interrupt processing.
658 */
Ralf Baechle1ee6dd72007-01-31 14:09:29 -0500659struct tx_curr_get_info {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700660 u32 offset;
661 u32 fifo_len;
Ralf Baechle1ee6dd72007-01-31 14:09:29 -0500662};
Linus Torvalds1da177e2005-04-16 15:20:36 -0700663
Ralf Baechle1ee6dd72007-01-31 14:09:29 -0500664struct tx_curr_put_info {
665 u32 offset;
666 u32 fifo_len;
667};
Linus Torvalds1da177e2005-04-16 15:20:36 -0700668
Ralf Baechle1ee6dd72007-01-31 14:09:29 -0500669struct rxd_info {
Ananda Rajuda6971d2005-10-31 16:55:31 -0500670 void *virt_addr;
671 dma_addr_t dma_addr;
Ralf Baechle1ee6dd72007-01-31 14:09:29 -0500672};
Ananda Rajuda6971d2005-10-31 16:55:31 -0500673
raghavendra.koushik@neterion.com20346722005-08-03 12:24:33 -0700674/* Structure that holds the Phy and virt addresses of the Blocks */
Ralf Baechle1ee6dd72007-01-31 14:09:29 -0500675struct rx_block_info {
Ananda Rajuda6971d2005-10-31 16:55:31 -0500676 void *block_virt_addr;
raghavendra.koushik@neterion.com20346722005-08-03 12:24:33 -0700677 dma_addr_t block_dma_addr;
Ralf Baechle1ee6dd72007-01-31 14:09:29 -0500678 struct rxd_info *rxds;
679};
raghavendra.koushik@neterion.com20346722005-08-03 12:24:33 -0700680
681/* Ring specific structure */
Ralf Baechle1ee6dd72007-01-31 14:09:29 -0500682struct ring_info {
raghavendra.koushik@neterion.com20346722005-08-03 12:24:33 -0700683 /* The ring number */
684 int ring_no;
685
686 /*
687 * Place holders for the virtual and physical addresses of
688 * all the Rx Blocks
689 */
Ralf Baechle1ee6dd72007-01-31 14:09:29 -0500690 struct rx_block_info rx_blocks[MAX_RX_BLOCKS_PER_RING];
raghavendra.koushik@neterion.com20346722005-08-03 12:24:33 -0700691 int block_count;
692 int pkt_cnt;
693
694 /*
695 * Put pointer info which indictes which RxD has to be replenished
696 * with a new buffer.
697 */
Ralf Baechle1ee6dd72007-01-31 14:09:29 -0500698 struct rx_curr_put_info rx_curr_put_info;
raghavendra.koushik@neterion.com20346722005-08-03 12:24:33 -0700699
700 /*
701 * Get pointer info which indictes which is the last RxD that was
702 * processed by the driver.
703 */
Ralf Baechle1ee6dd72007-01-31 14:09:29 -0500704 struct rx_curr_get_info rx_curr_get_info;
raghavendra.koushik@neterion.com20346722005-08-03 12:24:33 -0700705
raghavendra.koushik@neterion.com20346722005-08-03 12:24:33 -0700706 /* Index to the absolute position of the put pointer of Rx ring */
707 int put_pos;
raghavendra.koushik@neterion.com20346722005-08-03 12:24:33 -0700708
raghavendra.koushik@neterion.com20346722005-08-03 12:24:33 -0700709 /* Buffer Address store. */
Ralf Baechle1ee6dd72007-01-31 14:09:29 -0500710 struct buffAdd **ba;
711 struct s2io_nic *nic;
712};
raghavendra.koushik@neterion.com20346722005-08-03 12:24:33 -0700713
714/* Fifo specific structure */
Ralf Baechle1ee6dd72007-01-31 14:09:29 -0500715struct fifo_info {
raghavendra.koushik@neterion.com20346722005-08-03 12:24:33 -0700716 /* FIFO number */
717 int fifo_no;
718
719 /* Maximum TxDs per TxDL */
720 int max_txds;
721
722 /* Place holder of all the TX List's Phy and Virt addresses. */
Ralf Baechle1ee6dd72007-01-31 14:09:29 -0500723 struct list_info_hold *list_info;
raghavendra.koushik@neterion.com20346722005-08-03 12:24:33 -0700724
725 /*
726 * Current offset within the tx FIFO where driver would write
727 * new Tx frame
728 */
Ralf Baechle1ee6dd72007-01-31 14:09:29 -0500729 struct tx_curr_put_info tx_curr_put_info;
raghavendra.koushik@neterion.com20346722005-08-03 12:24:33 -0700730
731 /*
732 * Current offset within tx FIFO from where the driver would start freeing
733 * the buffers
734 */
Ralf Baechle1ee6dd72007-01-31 14:09:29 -0500735 struct tx_curr_get_info tx_curr_get_info;
Sreenivasa Honnur3a3d5752008-02-20 16:44:07 -0500736#define FIFO_QUEUE_START 0
737#define FIFO_QUEUE_STOP 1
738 int queue_state;
739
740 /* copy of sp->dev pointer */
741 struct net_device *dev;
742
743 /* copy of multiq status */
744 u8 multiq;
raghavendra.koushik@neterion.com20346722005-08-03 12:24:33 -0700745
Surjit Reang2fda0962008-01-24 02:08:59 -0800746 /* Per fifo lock */
747 spinlock_t tx_lock;
748
749 /* Per fifo UFO in band structure */
750 u64 *ufo_in_band_v;
751
Ralf Baechle1ee6dd72007-01-31 14:09:29 -0500752 struct s2io_nic *nic;
Surjit Reang2fda0962008-01-24 02:08:59 -0800753} ____cacheline_aligned;
raghavendra.koushik@neterion.com20346722005-08-03 12:24:33 -0700754
Adrian Bunk47bdd712006-06-30 18:25:18 +0200755/* Information related to the Tx and Rx FIFOs and Rings of Xena
Linus Torvalds1da177e2005-04-16 15:20:36 -0700756 * is maintained in this structure.
757 */
Ralf Baechle1ee6dd72007-01-31 14:09:29 -0500758struct mac_info {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700759/* tx side stuff */
760 /* logical pointer of start of each Tx FIFO */
Ralf Baechle1ee6dd72007-01-31 14:09:29 -0500761 struct TxFIFO_element __iomem *tx_FIFO_start[MAX_TX_FIFOS];
Linus Torvalds1da177e2005-04-16 15:20:36 -0700762
raghavendra.koushik@neterion.com20346722005-08-03 12:24:33 -0700763 /* Fifo specific structure */
Ralf Baechle1ee6dd72007-01-31 14:09:29 -0500764 struct fifo_info fifos[MAX_TX_FIFOS];
raghavendra.koushik@neterion.com20346722005-08-03 12:24:33 -0700765
ravinandan.arakali@neterion.com776bd202005-09-06 21:36:56 -0700766 /* Save virtual address of TxD page with zero DMA addr(if any) */
767 void *zerodma_virt_addr;
768
raghavendra.koushik@neterion.com20346722005-08-03 12:24:33 -0700769/* rx side stuff */
770 /* Ring specific structure */
Ralf Baechle1ee6dd72007-01-31 14:09:29 -0500771 struct ring_info rings[MAX_RX_RINGS];
raghavendra.koushik@neterion.com20346722005-08-03 12:24:33 -0700772
773 u16 rmac_pause_time;
774 u16 mc_pause_threshold_q0q3;
775 u16 mc_pause_threshold_q4q7;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700776
777 void *stats_mem; /* orignal pointer to allocated mem */
778 dma_addr_t stats_mem_phy; /* Physical address of the stat block */
779 u32 stats_mem_sz;
Ralf Baechle1ee6dd72007-01-31 14:09:29 -0500780 struct stat_block *stats_info; /* Logical address of the stat block */
781};
Linus Torvalds1da177e2005-04-16 15:20:36 -0700782
783/* structure representing the user defined MAC addresses */
Ralf Baechle1ee6dd72007-01-31 14:09:29 -0500784struct usr_addr {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700785 char addr[ETH_ALEN];
786 int usage_cnt;
Ralf Baechle1ee6dd72007-01-31 14:09:29 -0500787};
Linus Torvalds1da177e2005-04-16 15:20:36 -0700788
Linus Torvalds1da177e2005-04-16 15:20:36 -0700789/* Default Tunable parameters of the NIC. */
Ananda Raju9dc737a2006-04-21 19:05:41 -0400790#define DEFAULT_FIFO_0_LEN 4096
791#define DEFAULT_FIFO_1_7_LEN 512
Ananda Rajuc92ca042006-04-21 19:18:03 -0400792#define SMALL_BLK_CNT 30
793#define LARGE_BLK_CNT 100
Linus Torvalds1da177e2005-04-16 15:20:36 -0700794
Ravinandan Arakalicc6e7c42005-10-04 06:41:24 -0400795/*
796 * Structure to keep track of the MSI-X vectors and the corresponding
797 * argument registered against each vector
798 */
799#define MAX_REQUESTED_MSI_X 17
800struct s2io_msix_entry
801{
802 u16 vector;
803 u16 entry;
804 void *arg;
805
806 u8 type;
807#define MSIX_FIFO_TYPE 1
808#define MSIX_RING_TYPE 2
809
810 u8 in_use;
811#define MSIX_REGISTERED_SUCCESS 0xAA
812};
813
814struct msix_info_st {
815 u64 addr;
816 u64 data;
817};
818
Ravinandan Arakali7d3d04392006-01-25 14:53:07 -0500819/* Data structure to represent a LRO session */
Ralf Baechle1ee6dd72007-01-31 14:09:29 -0500820struct lro {
Ravinandan Arakali7d3d04392006-01-25 14:53:07 -0500821 struct sk_buff *parent;
Ananda Raju75c30b12006-07-24 19:55:09 -0400822 struct sk_buff *last_frag;
Ravinandan Arakali7d3d04392006-01-25 14:53:07 -0500823 u8 *l2h;
824 struct iphdr *iph;
825 struct tcphdr *tcph;
826 u32 tcp_next_seq;
Al Virobd4f3ae2007-02-09 16:40:15 +0000827 __be32 tcp_ack;
Ravinandan Arakali7d3d04392006-01-25 14:53:07 -0500828 int total_len;
829 int frags_len;
830 int sg_num;
831 int in_use;
Al Virobd4f3ae2007-02-09 16:40:15 +0000832 __be16 window;
Sreenivasa Honnurcdb5bf02008-02-20 17:09:15 -0500833 u16 vlan_tag;
Ravinandan Arakali7d3d04392006-01-25 14:53:07 -0500834 u32 cur_tsval;
Surjit Reangc8855952008-02-03 04:27:38 -0800835 __be32 cur_tsecr;
Ravinandan Arakali7d3d04392006-01-25 14:53:07 -0500836 u8 saw_ts;
Sreenivasa Honnurcdb5bf02008-02-20 17:09:15 -0500837} ____cacheline_aligned;
Ravinandan Arakali7d3d04392006-01-25 14:53:07 -0500838
Sivakumar Subramani92b84432007-09-06 06:51:14 -0400839/* These flags represent the devices temporary state */
840enum s2io_device_state_t
841{
842 __S2IO_STATE_LINK_TASK=0,
843 __S2IO_STATE_CARD_UP
844};
845
Linus Torvalds1da177e2005-04-16 15:20:36 -0700846/* Structure representing one instance of the NIC */
raghavendra.koushik@neterion.com20346722005-08-03 12:24:33 -0700847struct s2io_nic {
Ananda Rajuda6971d2005-10-31 16:55:31 -0500848 int rxd_mode;
raghavendra.koushik@neterion.com20346722005-08-03 12:24:33 -0700849 /*
850 * Count of packets to be processed in a given iteration, it will be indicated
851 * by the quota field of the device structure when NAPI is enabled.
852 */
853 int pkts_to_process;
raghavendra.koushik@neterion.com20346722005-08-03 12:24:33 -0700854 struct net_device *dev;
Stephen Hemmingerbea33482007-10-03 16:41:36 -0700855 struct napi_struct napi;
Ralf Baechle1ee6dd72007-01-31 14:09:29 -0500856 struct mac_info mac_control;
raghavendra.koushik@neterion.com20346722005-08-03 12:24:33 -0700857 struct config_param config;
858 struct pci_dev *pdev;
859 void __iomem *bar0;
860 void __iomem *bar1;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700861#define MAX_MAC_SUPPORTED 16
862#define MAX_SUPPORTED_MULTICASTS MAX_MAC_SUPPORTED
863
Sreenivasa Honnurfaa4f792008-01-24 01:45:43 -0800864 struct mac_addr def_mac_addr[256];
Linus Torvalds1da177e2005-04-16 15:20:36 -0700865
866 struct net_device_stats stats;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700867 int high_dma_flag;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700868 int device_enabled_once;
869
Ananda Rajuc92ca042006-04-21 19:18:03 -0400870 char name[60];
Linus Torvalds1da177e2005-04-16 15:20:36 -0700871 struct tasklet_struct task;
872 volatile unsigned long tasklet_status;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700873
raghavendra.koushik@neterion.com25fff882005-08-03 12:34:11 -0700874 /* Timer that handles I/O errors/exceptions */
875 struct timer_list alarm_timer;
876
raghavendra.koushik@neterion.com20346722005-08-03 12:24:33 -0700877 /* Space to back up the PCI config space */
878 u32 config_space[256 / sizeof(u32)];
879
Linus Torvalds1da177e2005-04-16 15:20:36 -0700880 atomic_t rx_bufs_left[MAX_RX_RINGS];
881
Linus Torvalds1da177e2005-04-16 15:20:36 -0700882 spinlock_t put_lock;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700883
884#define PROMISC 1
885#define ALL_MULTI 2
886
887#define MAX_ADDRS_SUPPORTED 64
888 u16 usr_addr_count;
889 u16 mc_addr_count;
Sreenivasa Honnurfaa4f792008-01-24 01:45:43 -0800890 struct usr_addr usr_addrs[256];
Linus Torvalds1da177e2005-04-16 15:20:36 -0700891
892 u16 m_cast_flg;
893 u16 all_multi_pos;
894 u16 promisc_flg;
895
Linus Torvalds1da177e2005-04-16 15:20:36 -0700896 /* Id timer, used to blink NIC to physically identify NIC. */
897 struct timer_list id_timer;
898
899 /* Restart timer, used to restart NIC if the device is stuck and
raghavendra.koushik@neterion.com20346722005-08-03 12:24:33 -0700900 * a schedule task that will set the correct Link state once the
Linus Torvalds1da177e2005-04-16 15:20:36 -0700901 * NIC's PHY has stabilized after a state change.
902 */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700903 struct work_struct rst_timer_task;
904 struct work_struct set_link_task;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700905
raghavendra.koushik@neterion.com20346722005-08-03 12:24:33 -0700906 /* Flag that can be used to turn on or turn off the Rx checksum
Linus Torvalds1da177e2005-04-16 15:20:36 -0700907 * offload feature.
908 */
909 int rx_csum;
910
Sreenivasa Honnur6cfc4822008-02-20 17:07:51 -0500911 /* Below variables are used for fifo selection to transmit a packet */
912 u16 fifo_selector[MAX_TX_FIFOS];
913
914 /* Total fifos for tcp packets */
915 u8 total_tcp_fifos;
916
917 /*
918 * Beginning index of udp for udp packets
919 * Value will be equal to
920 * (tx_fifo_num - FIFO_UDP_MAX_NUM - FIFO_OTHER_MAX_NUM)
921 */
922 u8 udp_fifo_idx;
923
924 u8 total_udp_fifos;
925
926 /*
927 * Beginning index of fifo for all other packets
928 * Value will be equal to (tx_fifo_num - FIFO_OTHER_MAX_NUM)
929 */
930 u8 other_fifo_idx;
931
raghavendra.koushik@neterion.com20346722005-08-03 12:24:33 -0700932 /* after blink, the adapter must be restored with original
Linus Torvalds1da177e2005-04-16 15:20:36 -0700933 * values.
934 */
935 u64 adapt_ctrl_org;
936
937 /* Last known link state. */
938 u16 last_link_state;
939#define LINK_DOWN 1
940#define LINK_UP 2
941
Linus Torvalds1da177e2005-04-16 15:20:36 -0700942 int task_flag;
Sreenivasa Honnur491976b2007-05-10 04:22:25 -0400943 unsigned long long start_time;
raghavendra.koushik@neterion.combe3a6b02005-08-03 12:35:55 -0700944 struct vlan_group *vlgrp;
Ravinandan Arakalicc6e7c42005-10-04 06:41:24 -0400945#define MSIX_FLG 0xA5
946 struct msix_entry *entries;
Sivakumar Subramani8abc4d52007-09-15 13:11:34 -0700947 int msi_detected;
948 wait_queue_head_t msi_wait;
Ravinandan Arakalicc6e7c42005-10-04 06:41:24 -0400949 struct s2io_msix_entry *s2io_entries;
Ananda Rajue6a8fee2006-07-06 23:58:23 -0700950 char desc[MAX_REQUESTED_MSI_X][25];
Ravinandan Arakalicc6e7c42005-10-04 06:41:24 -0400951
Ananda Rajuc92ca042006-04-21 19:18:03 -0400952 int avail_msix_vectors; /* No. of MSI-X vectors granted by system */
953
Ravinandan Arakalicc6e7c42005-10-04 06:41:24 -0400954 struct msix_info_st msix_info[0x3f];
955
raghavendra.koushik@neterion.com541ae682005-08-03 12:36:55 -0700956#define XFRAME_I_DEVICE 1
957#define XFRAME_II_DEVICE 2
958 u8 device_type;
raghavendra.koushik@neterion.combe3a6b02005-08-03 12:35:55 -0700959
Ravinandan Arakali7d3d04392006-01-25 14:53:07 -0500960#define MAX_LRO_SESSIONS 32
Ralf Baechle1ee6dd72007-01-31 14:09:29 -0500961 struct lro lro0_n[MAX_LRO_SESSIONS];
Ravinandan Arakali7d3d04392006-01-25 14:53:07 -0500962 unsigned long clubbed_frms_cnt;
963 unsigned long sending_both;
964 u8 lro;
965 u16 lro_max_aggr_per_sess;
Sivakumar Subramani92b84432007-09-06 06:51:14 -0400966 volatile unsigned long state;
raghavendra.koushik@neterion.com7ba013a2005-08-03 12:29:20 -0700967 spinlock_t rx_lock;
Sivakumar Subramani9caab452007-09-06 06:21:54 -0400968 u64 general_int_mask;
Sivakumar Subramani19a60522007-01-31 13:30:49 -0500969#define VPD_STRING_LEN 80
970 u8 product_name[VPD_STRING_LEN];
971 u8 serial_num[VPD_STRING_LEN];
raghavendra.koushik@neterion.com20346722005-08-03 12:24:33 -0700972};
Linus Torvalds1da177e2005-04-16 15:20:36 -0700973
974#define RESET_ERROR 1;
975#define CMD_ERROR 2;
976
977/* OS related system calls */
978#ifndef readq
979static inline u64 readq(void __iomem *addr)
980{
raghavendra.koushik@neterion.com20346722005-08-03 12:24:33 -0700981 u64 ret = 0;
982 ret = readl(addr + 4);
Andrew Morton7ef24b62005-08-25 17:14:46 -0700983 ret <<= 32;
984 ret |= readl(addr);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700985
986 return ret;
987}
988#endif
989
990#ifndef writeq
991static inline void writeq(u64 val, void __iomem *addr)
992{
993 writel((u32) (val), addr);
994 writel((u32) (val >> 32), (addr + 4));
995}
Ananda Rajuc92ca042006-04-21 19:18:03 -0400996#endif
Linus Torvalds1da177e2005-04-16 15:20:36 -0700997
Jeff Garzik6aa20a22006-09-13 13:24:59 -0400998/*
999 * Some registers have to be written in a particular order to
1000 * expect correct hardware operation. The macro SPECIAL_REG_WRITE
1001 * is used to perform such ordered writes. Defines UF (Upper First)
Ananda Rajuc92ca042006-04-21 19:18:03 -04001002 * and LF (Lower First) will be used to specify the required write order.
Linus Torvalds1da177e2005-04-16 15:20:36 -07001003 */
1004#define UF 1
1005#define LF 2
1006static inline void SPECIAL_REG_WRITE(u64 val, void __iomem *addr, int order)
1007{
Ananda Rajuc92ca042006-04-21 19:18:03 -04001008 u32 ret;
1009
Linus Torvalds1da177e2005-04-16 15:20:36 -07001010 if (order == LF) {
1011 writel((u32) (val), addr);
Ananda Rajuc92ca042006-04-21 19:18:03 -04001012 ret = readl(addr);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001013 writel((u32) (val >> 32), (addr + 4));
Ananda Rajuc92ca042006-04-21 19:18:03 -04001014 ret = readl(addr + 4);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001015 } else {
1016 writel((u32) (val >> 32), (addr + 4));
Ananda Rajuc92ca042006-04-21 19:18:03 -04001017 ret = readl(addr + 4);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001018 writel((u32) (val), addr);
Ananda Rajuc92ca042006-04-21 19:18:03 -04001019 ret = readl(addr);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001020 }
1021}
Linus Torvalds1da177e2005-04-16 15:20:36 -07001022
1023/* Interrupt related values of Xena */
1024
1025#define ENABLE_INTRS 1
1026#define DISABLE_INTRS 2
1027
1028/* Highest level interrupt blocks */
1029#define TX_PIC_INTR (0x0001<<0)
1030#define TX_DMA_INTR (0x0001<<1)
1031#define TX_MAC_INTR (0x0001<<2)
1032#define TX_XGXS_INTR (0x0001<<3)
1033#define TX_TRAFFIC_INTR (0x0001<<4)
1034#define RX_PIC_INTR (0x0001<<5)
1035#define RX_DMA_INTR (0x0001<<6)
1036#define RX_MAC_INTR (0x0001<<7)
1037#define RX_XGXS_INTR (0x0001<<8)
1038#define RX_TRAFFIC_INTR (0x0001<<9)
1039#define MC_INTR (0x0001<<10)
1040#define ENA_ALL_INTRS ( TX_PIC_INTR | \
1041 TX_DMA_INTR | \
1042 TX_MAC_INTR | \
1043 TX_XGXS_INTR | \
1044 TX_TRAFFIC_INTR | \
1045 RX_PIC_INTR | \
1046 RX_DMA_INTR | \
1047 RX_MAC_INTR | \
1048 RX_XGXS_INTR | \
1049 RX_TRAFFIC_INTR | \
1050 MC_INTR )
1051
1052/* Interrupt masks for the general interrupt mask register */
1053#define DISABLE_ALL_INTRS 0xFFFFFFFFFFFFFFFFULL
1054
Jiri Slabyb7b5a122007-10-18 23:40:29 -07001055#define TXPIC_INT_M s2BIT(0)
1056#define TXDMA_INT_M s2BIT(1)
1057#define TXMAC_INT_M s2BIT(2)
1058#define TXXGXS_INT_M s2BIT(3)
1059#define TXTRAFFIC_INT_M s2BIT(8)
1060#define PIC_RX_INT_M s2BIT(32)
1061#define RXDMA_INT_M s2BIT(33)
1062#define RXMAC_INT_M s2BIT(34)
1063#define MC_INT_M s2BIT(35)
1064#define RXXGXS_INT_M s2BIT(36)
1065#define RXTRAFFIC_INT_M s2BIT(40)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001066
1067/* PIC level Interrupts TODO*/
1068
1069/* DMA level Inressupts */
Jiri Slabyb7b5a122007-10-18 23:40:29 -07001070#define TXDMA_PFC_INT_M s2BIT(0)
1071#define TXDMA_PCC_INT_M s2BIT(2)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001072
1073/* PFC block interrupts */
Jiri Slabyb7b5a122007-10-18 23:40:29 -07001074#define PFC_MISC_ERR_1 s2BIT(0) /* Interrupt to indicate FIFO full */
Linus Torvalds1da177e2005-04-16 15:20:36 -07001075
1076/* PCC block interrupts. */
1077#define PCC_FB_ECC_ERR vBIT(0xff, 16, 8) /* Interrupt to indicate
1078 PCC_FB_ECC Error. */
1079
raghavendra.koushik@neterion.com20346722005-08-03 12:24:33 -07001080#define RXD_GET_VLAN_TAG(Control_2) (u16)(Control_2 & MASK_VLAN_TAG)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001081/*
1082 * Prototype declaration.
1083 */
1084static int __devinit s2io_init_nic(struct pci_dev *pdev,
1085 const struct pci_device_id *pre);
1086static void __devexit s2io_rem_nic(struct pci_dev *pdev);
1087static int init_shared_mem(struct s2io_nic *sp);
1088static void free_shared_mem(struct s2io_nic *sp);
1089static int init_nic(struct s2io_nic *nic);
Ralf Baechle1ee6dd72007-01-31 14:09:29 -05001090static void rx_intr_handler(struct ring_info *ring_data);
1091static void tx_intr_handler(struct fifo_info *fifo_data);
Sivakumar Subramani8116f3c2007-09-17 13:05:35 -07001092static void s2io_handle_errors(void * dev_id);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001093
1094static int s2io_starter(void);
Sivakumar Subramani19a60522007-01-31 13:30:49 -05001095static void s2io_closer(void);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001096static void s2io_tx_watchdog(struct net_device *dev);
1097static void s2io_tasklet(unsigned long dev_addr);
1098static void s2io_set_multicast(struct net_device *dev);
Ralf Baechle1ee6dd72007-01-31 14:09:29 -05001099static int rx_osm_handler(struct ring_info *ring_data, struct RxD_t * rxdp);
1100static void s2io_link(struct s2io_nic * sp, int link);
1101static void s2io_reset(struct s2io_nic * sp);
Stephen Hemmingerbea33482007-10-03 16:41:36 -07001102static int s2io_poll(struct napi_struct *napi, int budget);
Ralf Baechle1ee6dd72007-01-31 14:09:29 -05001103static void s2io_init_pci(struct s2io_nic * sp);
Sivakumar Subramani2fd37682007-09-14 07:39:19 -04001104static int do_s2io_prog_unicast(struct net_device *dev, u8 *addr);
raghavendra.koushik@neterion.com25fff882005-08-03 12:34:11 -07001105static void s2io_alarm_handle(unsigned long data);
Ravinandan Arakalicc6e7c42005-10-04 06:41:24 -04001106static irqreturn_t
David Howells7d12e782006-10-05 14:55:46 +01001107s2io_msix_ring_handle(int irq, void *dev_id);
Ravinandan Arakalicc6e7c42005-10-04 06:41:24 -04001108static irqreturn_t
David Howells7d12e782006-10-05 14:55:46 +01001109s2io_msix_fifo_handle(int irq, void *dev_id);
1110static irqreturn_t s2io_isr(int irq, void *dev_id);
Ralf Baechle1ee6dd72007-01-31 14:09:29 -05001111static int verify_xena_quiescence(struct s2io_nic *sp);
Jeff Garzik7282d492006-09-13 14:30:00 -04001112static const struct ethtool_ops netdev_ethtool_ops;
David Howellsc4028952006-11-22 14:57:56 +00001113static void s2io_set_link(struct work_struct *work);
Ralf Baechle1ee6dd72007-01-31 14:09:29 -05001114static int s2io_set_swapper(struct s2io_nic * sp);
1115static void s2io_card_down(struct s2io_nic *nic);
1116static int s2io_card_up(struct s2io_nic *nic);
Sivakumar Subramani9fc93a42007-02-24 01:57:32 -05001117static int wait_for_cmd_complete(void __iomem *addr, u64 busy_bit,
1118 int bit_state);
Ralf Baechle1ee6dd72007-01-31 14:09:29 -05001119static int s2io_add_isr(struct s2io_nic * sp);
1120static void s2io_rem_isr(struct s2io_nic * sp);
Sivakumar Subramani19a60522007-01-31 13:30:49 -05001121
Ralf Baechle1ee6dd72007-01-31 14:09:29 -05001122static void restore_xmsi_data(struct s2io_nic *nic);
Sreenivasa Honnurfaa4f792008-01-24 01:45:43 -08001123static void do_s2io_store_unicast_mc(struct s2io_nic *sp);
1124static void do_s2io_restore_unicast_mc(struct s2io_nic *sp);
1125static u64 do_s2io_read_unicast_mc(struct s2io_nic *sp, int offset);
1126static int do_s2io_add_mc(struct s2io_nic *sp, u8 *addr);
1127static int do_s2io_add_mac(struct s2io_nic *sp, u64 addr, int offset);
1128static int do_s2io_delete_unicast_mc(struct s2io_nic *sp, u64 addr);
Ravinandan Arakali7d3d04392006-01-25 14:53:07 -05001129
Ralf Baechle1ee6dd72007-01-31 14:09:29 -05001130static int
1131s2io_club_tcp_session(u8 *buffer, u8 **tcp, u32 *tcp_len, struct lro **lro,
1132 struct RxD_t *rxdp, struct s2io_nic *sp);
1133static void clear_lro_session(struct lro *lro);
Sreenivasa Honnurcdb5bf02008-02-20 17:09:15 -05001134static void queue_rx_frame(struct sk_buff *skb, u16 vlan_tag);
Ralf Baechle1ee6dd72007-01-31 14:09:29 -05001135static void update_L3L4_header(struct s2io_nic *sp, struct lro *lro);
1136static void lro_append_pkt(struct s2io_nic *sp, struct lro *lro,
1137 struct sk_buff *skb, u32 tcp_len);
Sivakumar Subramani9fc93a42007-02-24 01:57:32 -05001138static int rts_ds_steer(struct s2io_nic *nic, u8 ds_codepoint, u8 ring);
Ananda Rajub41477f2006-07-24 19:52:49 -04001139
Linas Vepstasd796fdb2007-05-14 18:37:30 -05001140static pci_ers_result_t s2io_io_error_detected(struct pci_dev *pdev,
1141 pci_channel_state_t state);
1142static pci_ers_result_t s2io_io_slot_reset(struct pci_dev *pdev);
1143static void s2io_io_resume(struct pci_dev *pdev);
1144
Ananda Raju75c30b12006-07-24 19:55:09 -04001145#define s2io_tcp_mss(skb) skb_shinfo(skb)->gso_size
1146#define s2io_udp_mss(skb) skb_shinfo(skb)->gso_size
1147#define s2io_offload_type(skb) skb_shinfo(skb)->gso_type
1148
Ananda Rajub41477f2006-07-24 19:52:49 -04001149#define S2IO_PARM_INT(X, def_val) \
1150 static unsigned int X = def_val;\
1151 module_param(X , uint, 0);
1152
Linus Torvalds1da177e2005-04-16 15:20:36 -07001153#endif /* _S2IO_H */