blob: acfee7c51b9e4a9856e15d5bc1fde12eee91f2ff [file] [log] [blame]
Kalle Valo5e3dd152013-06-12 20:52:10 +03001/*
2 * Copyright (c) 2005-2011 Atheros Communications Inc.
3 * Copyright (c) 2011-2013 Qualcomm Atheros, Inc.
4 *
5 * Permission to use, copy, modify, and/or distribute this software for any
6 * purpose with or without fee is hereby granted, provided that the above
7 * copyright notice and this permission notice appear in all copies.
8 *
9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
16 */
17
18#ifndef _CORE_H_
19#define _CORE_H_
20
21#include <linux/completion.h>
22#include <linux/if_ether.h>
23#include <linux/types.h>
24#include <linux/pci.h>
25
Michal Kazioredb82362013-07-05 16:15:14 +030026#include "htt.h"
Kalle Valo5e3dd152013-06-12 20:52:10 +030027#include "htc.h"
28#include "hw.h"
29#include "targaddrs.h"
30#include "wmi.h"
31#include "../ath.h"
32#include "../regd.h"
33
34#define MS(_v, _f) (((_v) & _f##_MASK) >> _f##_LSB)
35#define SM(_v, _f) (((_v) << _f##_LSB) & _f##_MASK)
36#define WO(_f) ((_f##_OFFSET) >> 2)
37
38#define ATH10K_SCAN_ID 0
39#define WMI_READY_TIMEOUT (5 * HZ)
40#define ATH10K_FLUSH_TIMEOUT_HZ (5*HZ)
Michal Kazior2e1dea42013-07-31 10:32:40 +020041#define ATH10K_NUM_CHANS 38
Kalle Valo5e3dd152013-06-12 20:52:10 +030042
43/* Antenna noise floor */
44#define ATH10K_DEFAULT_NOISE_FLOOR -95
45
46struct ath10k;
47
Kalle Valo5e3dd152013-06-12 20:52:10 +030048struct ath10k_skb_cb {
49 dma_addr_t paddr;
50 bool is_mapped;
51 bool is_aborted;
52
53 struct {
54 u8 vdev_id;
Kalle Valo5e3dd152013-06-12 20:52:10 +030055 u8 tid;
56 bool is_offchan;
Michal Kazior1f8bb152013-09-18 14:43:22 +020057
58 u8 frag_len;
59 u8 pad_len;
Kalle Valo5e3dd152013-06-12 20:52:10 +030060 } __packed htt;
Kalle Valo5e3dd152013-06-12 20:52:10 +030061} __packed;
62
63static inline struct ath10k_skb_cb *ATH10K_SKB_CB(struct sk_buff *skb)
64{
65 BUILD_BUG_ON(sizeof(struct ath10k_skb_cb) >
66 IEEE80211_TX_INFO_DRIVER_DATA_SIZE);
67 return (struct ath10k_skb_cb *)&IEEE80211_SKB_CB(skb)->driver_data;
68}
69
70static inline int ath10k_skb_map(struct device *dev, struct sk_buff *skb)
71{
72 if (ATH10K_SKB_CB(skb)->is_mapped)
73 return -EINVAL;
74
75 ATH10K_SKB_CB(skb)->paddr = dma_map_single(dev, skb->data, skb->len,
76 DMA_TO_DEVICE);
77
78 if (unlikely(dma_mapping_error(dev, ATH10K_SKB_CB(skb)->paddr)))
79 return -EIO;
80
81 ATH10K_SKB_CB(skb)->is_mapped = true;
82 return 0;
83}
84
85static inline int ath10k_skb_unmap(struct device *dev, struct sk_buff *skb)
86{
87 if (!ATH10K_SKB_CB(skb)->is_mapped)
88 return -EINVAL;
89
90 dma_unmap_single(dev, ATH10K_SKB_CB(skb)->paddr, skb->len,
91 DMA_TO_DEVICE);
92 ATH10K_SKB_CB(skb)->is_mapped = false;
93 return 0;
94}
95
96static inline u32 host_interest_item_address(u32 item_offset)
97{
98 return QCA988X_HOST_INTEREST_ADDRESS + item_offset;
99}
100
101struct ath10k_bmi {
102 bool done_sent;
103};
104
105struct ath10k_wmi {
106 enum ath10k_htc_ep_id eid;
107 struct completion service_ready;
108 struct completion unified_ready;
Michal Kaziorbe8b3942013-09-13 14:16:54 +0200109 wait_queue_head_t tx_credits_wq;
Bartosz Markowskice428702013-09-26 17:47:05 +0200110 struct wmi_cmd_map *cmd;
Kalle Valo5e3dd152013-06-12 20:52:10 +0300111};
112
113struct ath10k_peer_stat {
114 u8 peer_macaddr[ETH_ALEN];
115 u32 peer_rssi;
116 u32 peer_tx_rate;
117};
118
119struct ath10k_target_stats {
120 /* PDEV stats */
121 s32 ch_noise_floor;
122 u32 tx_frame_count;
123 u32 rx_frame_count;
124 u32 rx_clear_count;
125 u32 cycle_count;
126 u32 phy_err_count;
127 u32 chan_tx_power;
128
129 /* PDEV TX stats */
130 s32 comp_queued;
131 s32 comp_delivered;
132 s32 msdu_enqued;
133 s32 mpdu_enqued;
134 s32 wmm_drop;
135 s32 local_enqued;
136 s32 local_freed;
137 s32 hw_queued;
138 s32 hw_reaped;
139 s32 underrun;
140 s32 tx_abort;
141 s32 mpdus_requed;
142 u32 tx_ko;
143 u32 data_rc;
144 u32 self_triggers;
145 u32 sw_retry_failure;
146 u32 illgl_rate_phy_err;
147 u32 pdev_cont_xretry;
148 u32 pdev_tx_timeout;
149 u32 pdev_resets;
150 u32 phy_underrun;
151 u32 txop_ovf;
152
153 /* PDEV RX stats */
154 s32 mid_ppdu_route_change;
155 s32 status_rcvd;
156 s32 r0_frags;
157 s32 r1_frags;
158 s32 r2_frags;
159 s32 r3_frags;
160 s32 htt_msdus;
161 s32 htt_mpdus;
162 s32 loc_msdus;
163 s32 loc_mpdus;
164 s32 oversize_amsdu;
165 s32 phy_errs;
166 s32 phy_err_drop;
167 s32 mpdu_errs;
168
169 /* VDEV STATS */
170
171 /* PEER STATS */
172 u8 peers;
173 struct ath10k_peer_stat peer_stat[TARGET_NUM_PEERS];
174
175 /* TODO: Beacon filter stats */
176
177};
178
179#define ATH10K_MAX_NUM_PEER_IDS (1 << 11) /* htt rx_desc limit */
180
181struct ath10k_peer {
182 struct list_head list;
183 int vdev_id;
184 u8 addr[ETH_ALEN];
185 DECLARE_BITMAP(peer_ids, ATH10K_MAX_NUM_PEER_IDS);
186 struct ieee80211_key_conf *keys[WMI_MAX_KEY_INDEX + 1];
187};
188
189#define ATH10K_VDEV_SETUP_TIMEOUT_HZ (5*HZ)
190
191struct ath10k_vif {
192 u32 vdev_id;
193 enum wmi_vdev_type vdev_type;
194 enum wmi_vdev_subtype vdev_subtype;
195 u32 beacon_interval;
196 u32 dtim_period;
Michal Kaziored543882013-09-13 14:16:56 +0200197 struct sk_buff *beacon;
Kalle Valo5e3dd152013-06-12 20:52:10 +0300198
199 struct ath10k *ar;
200 struct ieee80211_vif *vif;
201
202 struct ieee80211_key_conf *wep_keys[WMI_MAX_KEY_INDEX + 1];
203 u8 def_wep_key_index;
204
205 u16 tx_seq_no;
206
207 union {
208 struct {
209 u8 bssid[ETH_ALEN];
210 u32 uapsd;
211 } sta;
212 struct {
213 /* 127 stations; wmi limit */
214 u8 tim_bitmap[16];
215 u8 tim_len;
216 u32 ssid_len;
217 u8 ssid[IEEE80211_MAX_SSID_LEN];
218 bool hidden_ssid;
219 /* P2P_IE with NoA attribute for P2P_GO case */
220 u32 noa_len;
221 u8 *noa_data;
222 } ap;
223 struct {
224 u8 bssid[ETH_ALEN];
225 } ibss;
226 } u;
227};
228
229struct ath10k_vif_iter {
230 u32 vdev_id;
231 struct ath10k_vif *arvif;
232};
233
234struct ath10k_debug {
235 struct dentry *debugfs_phy;
236
237 struct ath10k_target_stats target_stats;
238 u32 wmi_service_bitmap[WMI_SERVICE_BM_SIZE];
239
240 struct completion event_stats_compl;
Kalle Valoa3d135e2013-09-03 11:44:10 +0300241
242 unsigned long htt_stats_mask;
243 struct delayed_work htt_stats_dwork;
Kalle Valo5e3dd152013-06-12 20:52:10 +0300244};
245
Michal Kaziorf7843d72013-07-16 09:38:52 +0200246enum ath10k_state {
247 ATH10K_STATE_OFF = 0,
248 ATH10K_STATE_ON,
Michal Kazioraffd3212013-07-16 09:54:35 +0200249
250 /* When doing firmware recovery the device is first powered down.
251 * mac80211 is supposed to call in to start() hook later on. It is
252 * however possible that driver unloading and firmware crash overlap.
253 * mac80211 can wait on conf_mutex in stop() while the device is
254 * stopped in ath10k_core_restart() work holding conf_mutex. The state
255 * RESTARTED means that the device is up and mac80211 has started hw
256 * reconfiguration. Once mac80211 is done with the reconfiguration we
257 * set the state to STATE_ON in restart_complete(). */
258 ATH10K_STATE_RESTARTING,
259 ATH10K_STATE_RESTARTED,
260
261 /* The device has crashed while restarting hw. This state is like ON
262 * but commands are blocked in HTC and -ECOMM response is given. This
263 * prevents completion timeouts and makes the driver more responsive to
264 * userspace commands. This is also prevents recursive recovery. */
265 ATH10K_STATE_WEDGED,
Michal Kaziorf7843d72013-07-16 09:38:52 +0200266};
267
Michal Kazior0d9b0432013-08-09 10:13:33 +0200268enum ath10k_fw_features {
269 /* wmi_mgmt_rx_hdr contains extra RSSI information */
270 ATH10K_FW_FEATURE_EXT_WMI_MGMT_RX = 0,
271
Bartosz Markowskice428702013-09-26 17:47:05 +0200272 /* firmware from 10X branch */
273 ATH10K_FW_FEATURE_WMI_10X = 1,
274
Michal Kazior0d9b0432013-08-09 10:13:33 +0200275 /* keep last */
276 ATH10K_FW_FEATURE_COUNT,
277};
278
Kalle Valo5e3dd152013-06-12 20:52:10 +0300279struct ath10k {
280 struct ath_common ath_common;
281 struct ieee80211_hw *hw;
282 struct device *dev;
283 u8 mac_addr[ETH_ALEN];
284
Kalle Valoe01ae682013-09-01 11:22:14 +0300285 u32 chip_id;
Kalle Valo5e3dd152013-06-12 20:52:10 +0300286 u32 target_version;
287 u8 fw_version_major;
288 u32 fw_version_minor;
289 u16 fw_version_release;
290 u16 fw_version_build;
291 u32 phy_capability;
292 u32 hw_min_tx_power;
293 u32 hw_max_tx_power;
294 u32 ht_cap_info;
295 u32 vht_cap_info;
Michal Kazior8865bee42013-07-24 12:36:46 +0200296 u32 num_rf_chains;
Kalle Valo5e3dd152013-06-12 20:52:10 +0300297
Michal Kazior0d9b0432013-08-09 10:13:33 +0200298 DECLARE_BITMAP(fw_features, ATH10K_FW_FEATURE_COUNT);
299
Kalle Valo5e3dd152013-06-12 20:52:10 +0300300 struct targetdef *targetdef;
301 struct hostdef *hostdef;
302
303 bool p2p;
304
305 struct {
306 void *priv;
Kalle Valo5e3dd152013-06-12 20:52:10 +0300307 const struct ath10k_hif_ops *ops;
308 } hif;
309
Kalle Valo5e3dd152013-06-12 20:52:10 +0300310 wait_queue_head_t event_queue;
311 bool is_target_paused;
312
313 struct ath10k_bmi bmi;
Michal Kazioredb82362013-07-05 16:15:14 +0300314 struct ath10k_wmi wmi;
Michal Kaziorcd003fa2013-07-05 16:15:13 +0300315 struct ath10k_htc htc;
Michal Kazioredb82362013-07-05 16:15:14 +0300316 struct ath10k_htt htt;
Kalle Valo5e3dd152013-06-12 20:52:10 +0300317
318 struct ath10k_hw_params {
319 u32 id;
320 const char *name;
321 u32 patch_load_addr;
322
323 struct ath10k_hw_params_fw {
324 const char *dir;
325 const char *fw;
326 const char *otp;
327 const char *board;
328 } fw;
329 } hw_params;
330
Michal Kazior29385052013-07-16 09:38:58 +0200331 const struct firmware *board_data;
332 const struct firmware *otp;
333 const struct firmware *firmware;
334
Kalle Valo5e3dd152013-06-12 20:52:10 +0300335 struct {
336 struct completion started;
337 struct completion completed;
338 struct completion on_channel;
339 struct timer_list timeout;
340 bool is_roc;
341 bool in_progress;
342 bool aborting;
343 int vdev_id;
344 int roc_freq;
345 } scan;
346
347 struct {
348 struct ieee80211_supported_band sbands[IEEE80211_NUM_BANDS];
349 } mac;
350
351 /* should never be NULL; needed for regular htt rx */
352 struct ieee80211_channel *rx_channel;
353
354 /* valid during scan; needed for mgmt rx during scan */
355 struct ieee80211_channel *scan_channel;
356
357 int free_vdev_map;
358 int monitor_vdev_id;
359 bool monitor_enabled;
360 bool monitor_present;
361 unsigned int filter_flags;
362
363 struct wmi_pdev_set_wmm_params_arg wmm_params;
364 struct completion install_key_done;
365
366 struct completion vdev_setup_done;
367
368 struct workqueue_struct *workqueue;
369
370 /* prevents concurrent FW reconfiguration */
371 struct mutex conf_mutex;
372
373 /* protects shared structure data */
374 spinlock_t data_lock;
375
376 struct list_head peers;
377 wait_queue_head_t peer_mapping_wq;
378
379 struct work_struct offchan_tx_work;
380 struct sk_buff_head offchan_tx_queue;
381 struct completion offchan_tx_completed;
382 struct sk_buff *offchan_tx_skb;
383
Michal Kaziorf7843d72013-07-16 09:38:52 +0200384 enum ath10k_state state;
385
Michal Kazioraffd3212013-07-16 09:54:35 +0200386 struct work_struct restart_work;
387
Michal Kazior2e1dea42013-07-31 10:32:40 +0200388 /* cycle count is reported twice for each visited channel during scan.
389 * access protected by data_lock */
390 u32 survey_last_rx_clear_count;
391 u32 survey_last_cycle_count;
392 struct survey_info survey[ATH10K_NUM_CHANS];
393
Kalle Valo5e3dd152013-06-12 20:52:10 +0300394#ifdef CONFIG_ATH10K_DEBUGFS
395 struct ath10k_debug debug;
396#endif
397};
398
399struct ath10k *ath10k_core_create(void *hif_priv, struct device *dev,
Kalle Valo5e3dd152013-06-12 20:52:10 +0300400 const struct ath10k_hif_ops *hif_ops);
401void ath10k_core_destroy(struct ath10k *ar);
402
Michal Kaziordd30a362013-07-16 09:38:51 +0200403int ath10k_core_start(struct ath10k *ar);
404void ath10k_core_stop(struct ath10k *ar);
Kalle Valoe01ae682013-09-01 11:22:14 +0300405int ath10k_core_register(struct ath10k *ar, u32 chip_id);
Kalle Valo5e3dd152013-06-12 20:52:10 +0300406void ath10k_core_unregister(struct ath10k *ar);
407
Kalle Valo5e3dd152013-06-12 20:52:10 +0300408#endif /* _CORE_H_ */