David Ertman | e78b80b | 2014-02-04 01:56:06 +0000 | [diff] [blame] | 1 | /* Intel PRO/1000 Linux driver |
Yanir Lubetkin | 529498c | 2015-06-02 17:05:50 +0300 | [diff] [blame] | 2 | * Copyright(c) 1999 - 2015 Intel Corporation. |
David Ertman | e78b80b | 2014-02-04 01:56:06 +0000 | [diff] [blame] | 3 | * |
| 4 | * This program is free software; you can redistribute it and/or modify it |
| 5 | * under the terms and conditions of the GNU General Public License, |
| 6 | * version 2, as published by the Free Software Foundation. |
| 7 | * |
| 8 | * This program is distributed in the hope it will be useful, but WITHOUT |
| 9 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
| 10 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for |
| 11 | * more details. |
| 12 | * |
| 13 | * The full GNU General Public License is included in this distribution in |
| 14 | * the file called "COPYING". |
| 15 | * |
| 16 | * Contact Information: |
| 17 | * Linux NICS <linux.nics@intel.com> |
| 18 | * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> |
| 19 | * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 |
| 20 | */ |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 21 | |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 22 | #include "e1000.h" |
| 23 | |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 24 | static s32 e1000_wait_autoneg(struct e1000_hw *hw); |
Bruce Allan | 97ac8ca | 2008-04-29 09:16:05 -0700 | [diff] [blame] | 25 | static s32 e1000_access_phy_wakeup_reg_bm(struct e1000_hw *hw, u32 offset, |
Bruce Allan | 2b6b168 | 2011-05-13 07:20:09 +0000 | [diff] [blame] | 26 | u16 *data, bool read, bool page_set); |
Bruce Allan | a4f58f5 | 2009-06-02 11:29:18 +0000 | [diff] [blame] | 27 | static u32 e1000_get_phy_addr_for_hv_page(u32 page); |
| 28 | static s32 e1000_access_phy_debug_regs_hv(struct e1000_hw *hw, u32 offset, |
Bruce Allan | 1f96012d | 2013-01-05 03:06:54 +0000 | [diff] [blame] | 29 | u16 *data, bool read); |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 30 | |
| 31 | /* Cable length tables */ |
Bruce Allan | 6480641 | 2010-12-11 05:53:42 +0000 | [diff] [blame] | 32 | static const u16 e1000_m88_cable_length_table[] = { |
Bruce Allan | 04e115c | 2013-02-20 04:06:22 +0000 | [diff] [blame] | 33 | 0, 50, 80, 110, 140, 140, E1000_CABLE_LENGTH_UNDEFINED |
| 34 | }; |
Bruce Allan | fc830b7 | 2013-02-20 04:06:11 +0000 | [diff] [blame] | 35 | |
Bruce Allan | eb656d4 | 2009-12-01 15:47:02 +0000 | [diff] [blame] | 36 | #define M88E1000_CABLE_LENGTH_TABLE_SIZE \ |
| 37 | ARRAY_SIZE(e1000_m88_cable_length_table) |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 38 | |
Bruce Allan | 6480641 | 2010-12-11 05:53:42 +0000 | [diff] [blame] | 39 | static const u16 e1000_igp_2_cable_length_table[] = { |
| 40 | 0, 0, 0, 0, 0, 0, 0, 0, 3, 5, 8, 11, 13, 16, 18, 21, 0, 0, 0, 3, |
| 41 | 6, 10, 13, 16, 19, 23, 26, 29, 32, 35, 38, 41, 6, 10, 14, 18, 22, |
| 42 | 26, 30, 33, 37, 41, 44, 48, 51, 54, 58, 61, 21, 26, 31, 35, 40, |
| 43 | 44, 49, 53, 57, 61, 65, 68, 72, 75, 79, 82, 40, 45, 51, 56, 61, |
| 44 | 66, 70, 75, 79, 83, 87, 91, 94, 98, 101, 104, 60, 66, 72, 77, 82, |
| 45 | 87, 92, 96, 100, 104, 108, 111, 114, 117, 119, 121, 83, 89, 95, |
| 46 | 100, 105, 109, 113, 116, 119, 122, 124, 104, 109, 114, 118, 121, |
Bruce Allan | 04e115c | 2013-02-20 04:06:22 +0000 | [diff] [blame] | 47 | 124 |
| 48 | }; |
Bruce Allan | fc830b7 | 2013-02-20 04:06:11 +0000 | [diff] [blame] | 49 | |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 50 | #define IGP02E1000_CABLE_LENGTH_TABLE_SIZE \ |
Alejandro Martinez Ruiz | c00acf4 | 2007-10-18 10:16:33 +0200 | [diff] [blame] | 51 | ARRAY_SIZE(e1000_igp_2_cable_length_table) |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 52 | |
| 53 | /** |
| 54 | * e1000e_check_reset_block_generic - Check if PHY reset is blocked |
| 55 | * @hw: pointer to the HW structure |
| 56 | * |
| 57 | * Read the PHY management control register and check whether a PHY reset |
| 58 | * is blocked. If a reset is not blocked return 0, otherwise |
| 59 | * return E1000_BLK_PHY_RESET (12). |
| 60 | **/ |
| 61 | s32 e1000e_check_reset_block_generic(struct e1000_hw *hw) |
| 62 | { |
| 63 | u32 manc; |
| 64 | |
| 65 | manc = er32(MANC); |
| 66 | |
Bruce Allan | e5fe254 | 2013-02-20 04:06:27 +0000 | [diff] [blame] | 67 | return (manc & E1000_MANC_BLK_PHY_RST_ON_IDE) ? E1000_BLK_PHY_RESET : 0; |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 68 | } |
| 69 | |
| 70 | /** |
| 71 | * e1000e_get_phy_id - Retrieve the PHY ID and revision |
| 72 | * @hw: pointer to the HW structure |
| 73 | * |
| 74 | * Reads the PHY registers and stores the PHY ID and possibly the PHY |
| 75 | * revision in the hardware structure. |
| 76 | **/ |
| 77 | s32 e1000e_get_phy_id(struct e1000_hw *hw) |
| 78 | { |
| 79 | struct e1000_phy_info *phy = &hw->phy; |
Bruce Allan | a4f58f5 | 2009-06-02 11:29:18 +0000 | [diff] [blame] | 80 | s32 ret_val = 0; |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 81 | u16 phy_id; |
Bruce Allan | a4f58f5 | 2009-06-02 11:29:18 +0000 | [diff] [blame] | 82 | u16 retry_count = 0; |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 83 | |
Bruce Allan | 668018d | 2012-01-31 07:02:56 +0000 | [diff] [blame] | 84 | if (!phy->ops.read_reg) |
Bruce Allan | 5015e53 | 2012-02-08 02:55:56 +0000 | [diff] [blame] | 85 | return 0; |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 86 | |
Bruce Allan | a4f58f5 | 2009-06-02 11:29:18 +0000 | [diff] [blame] | 87 | while (retry_count < 2) { |
Bruce Allan | c2ade1a | 2013-01-16 08:54:35 +0000 | [diff] [blame] | 88 | ret_val = e1e_rphy(hw, MII_PHYSID1, &phy_id); |
Bruce Allan | a4f58f5 | 2009-06-02 11:29:18 +0000 | [diff] [blame] | 89 | if (ret_val) |
Bruce Allan | 5015e53 | 2012-02-08 02:55:56 +0000 | [diff] [blame] | 90 | return ret_val; |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 91 | |
Bruce Allan | a4f58f5 | 2009-06-02 11:29:18 +0000 | [diff] [blame] | 92 | phy->id = (u32)(phy_id << 16); |
Bruce Allan | ce43a21 | 2013-02-20 04:06:32 +0000 | [diff] [blame] | 93 | usleep_range(20, 40); |
Bruce Allan | c2ade1a | 2013-01-16 08:54:35 +0000 | [diff] [blame] | 94 | ret_val = e1e_rphy(hw, MII_PHYSID2, &phy_id); |
Bruce Allan | a4f58f5 | 2009-06-02 11:29:18 +0000 | [diff] [blame] | 95 | if (ret_val) |
Bruce Allan | 5015e53 | 2012-02-08 02:55:56 +0000 | [diff] [blame] | 96 | return ret_val; |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 97 | |
Bruce Allan | a4f58f5 | 2009-06-02 11:29:18 +0000 | [diff] [blame] | 98 | phy->id |= (u32)(phy_id & PHY_REVISION_MASK); |
| 99 | phy->revision = (u32)(phy_id & ~PHY_REVISION_MASK); |
| 100 | |
| 101 | if (phy->id != 0 && phy->id != PHY_REVISION_MASK) |
Bruce Allan | 5015e53 | 2012-02-08 02:55:56 +0000 | [diff] [blame] | 102 | return 0; |
Bruce Allan | a4f58f5 | 2009-06-02 11:29:18 +0000 | [diff] [blame] | 103 | |
Bruce Allan | a4f58f5 | 2009-06-02 11:29:18 +0000 | [diff] [blame] | 104 | retry_count++; |
| 105 | } |
Bruce Allan | 5015e53 | 2012-02-08 02:55:56 +0000 | [diff] [blame] | 106 | |
| 107 | return 0; |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 108 | } |
| 109 | |
| 110 | /** |
| 111 | * e1000e_phy_reset_dsp - Reset PHY DSP |
| 112 | * @hw: pointer to the HW structure |
| 113 | * |
| 114 | * Reset the digital signal processor. |
| 115 | **/ |
| 116 | s32 e1000e_phy_reset_dsp(struct e1000_hw *hw) |
| 117 | { |
| 118 | s32 ret_val; |
| 119 | |
| 120 | ret_val = e1e_wphy(hw, M88E1000_PHY_GEN_CONTROL, 0xC1); |
| 121 | if (ret_val) |
| 122 | return ret_val; |
| 123 | |
| 124 | return e1e_wphy(hw, M88E1000_PHY_GEN_CONTROL, 0); |
| 125 | } |
| 126 | |
| 127 | /** |
David Graham | 2d9498f | 2008-04-23 11:09:14 -0700 | [diff] [blame] | 128 | * e1000e_read_phy_reg_mdic - Read MDI control register |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 129 | * @hw: pointer to the HW structure |
| 130 | * @offset: register offset to be read |
| 131 | * @data: pointer to the read data |
| 132 | * |
Auke Kok | 489815c | 2008-02-21 15:11:07 -0800 | [diff] [blame] | 133 | * Reads the MDI control register in the PHY at offset and stores the |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 134 | * information read to data. |
| 135 | **/ |
David Graham | 2d9498f | 2008-04-23 11:09:14 -0700 | [diff] [blame] | 136 | s32 e1000e_read_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 *data) |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 137 | { |
| 138 | struct e1000_phy_info *phy = &hw->phy; |
| 139 | u32 i, mdic = 0; |
| 140 | |
| 141 | if (offset > MAX_PHY_REG_ADDRESS) { |
Bruce Allan | 3bb99fe | 2009-11-20 23:25:07 +0000 | [diff] [blame] | 142 | e_dbg("PHY Address %d is out of range\n", offset); |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 143 | return -E1000_ERR_PARAM; |
| 144 | } |
| 145 | |
Bruce Allan | e921eb1 | 2012-11-28 09:28:37 +0000 | [diff] [blame] | 146 | /* Set up Op-code, Phy Address, and register offset in the MDI |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 147 | * Control register. The MAC will take care of interfacing with the |
| 148 | * PHY to retrieve the desired data. |
| 149 | */ |
| 150 | mdic = ((offset << E1000_MDIC_REG_SHIFT) | |
| 151 | (phy->addr << E1000_MDIC_PHY_SHIFT) | |
| 152 | (E1000_MDIC_OP_READ)); |
| 153 | |
| 154 | ew32(MDIC, mdic); |
| 155 | |
Bruce Allan | e921eb1 | 2012-11-28 09:28:37 +0000 | [diff] [blame] | 156 | /* Poll the ready bit to see if the MDI read completed |
Bruce Allan | ad68076 | 2008-03-28 09:15:03 -0700 | [diff] [blame] | 157 | * Increasing the time out as testing showed failures with |
| 158 | * the lower time out |
| 159 | */ |
David Graham | 2d9498f | 2008-04-23 11:09:14 -0700 | [diff] [blame] | 160 | for (i = 0; i < (E1000_GEN_POLL_TIMEOUT * 3); i++) { |
Bruce Allan | 274a85e | 2013-03-19 01:47:12 +0000 | [diff] [blame] | 161 | udelay(50); |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 162 | mdic = er32(MDIC); |
| 163 | if (mdic & E1000_MDIC_READY) |
| 164 | break; |
| 165 | } |
| 166 | if (!(mdic & E1000_MDIC_READY)) { |
Bruce Allan | 3bb99fe | 2009-11-20 23:25:07 +0000 | [diff] [blame] | 167 | e_dbg("MDI Read did not complete\n"); |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 168 | return -E1000_ERR_PHY; |
| 169 | } |
| 170 | if (mdic & E1000_MDIC_ERROR) { |
Bruce Allan | 3bb99fe | 2009-11-20 23:25:07 +0000 | [diff] [blame] | 171 | e_dbg("MDI Error\n"); |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 172 | return -E1000_ERR_PHY; |
| 173 | } |
Bruce Allan | bb03451 | 2013-03-06 09:02:31 +0000 | [diff] [blame] | 174 | if (((mdic & E1000_MDIC_REG_MASK) >> E1000_MDIC_REG_SHIFT) != offset) { |
| 175 | e_dbg("MDI Read offset error - requested %d, returned %d\n", |
| 176 | offset, |
| 177 | (mdic & E1000_MDIC_REG_MASK) >> E1000_MDIC_REG_SHIFT); |
| 178 | return -E1000_ERR_PHY; |
| 179 | } |
Bruce Allan | 53aa82d | 2013-02-20 04:06:06 +0000 | [diff] [blame] | 180 | *data = (u16)mdic; |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 181 | |
Bruce Allan | e921eb1 | 2012-11-28 09:28:37 +0000 | [diff] [blame] | 182 | /* Allow some time after each MDIC transaction to avoid |
Bruce Allan | 664dc87 | 2010-11-24 06:01:46 +0000 | [diff] [blame] | 183 | * reading duplicate data in the next MDIC transaction. |
| 184 | */ |
| 185 | if (hw->mac.type == e1000_pch2lan) |
Bruce Allan | 274a85e | 2013-03-19 01:47:12 +0000 | [diff] [blame] | 186 | udelay(100); |
Bruce Allan | 664dc87 | 2010-11-24 06:01:46 +0000 | [diff] [blame] | 187 | |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 188 | return 0; |
| 189 | } |
| 190 | |
| 191 | /** |
David Graham | 2d9498f | 2008-04-23 11:09:14 -0700 | [diff] [blame] | 192 | * e1000e_write_phy_reg_mdic - Write MDI control register |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 193 | * @hw: pointer to the HW structure |
| 194 | * @offset: register offset to write to |
| 195 | * @data: data to write to register at offset |
| 196 | * |
| 197 | * Writes data to MDI control register in the PHY at offset. |
| 198 | **/ |
David Graham | 2d9498f | 2008-04-23 11:09:14 -0700 | [diff] [blame] | 199 | s32 e1000e_write_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 data) |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 200 | { |
| 201 | struct e1000_phy_info *phy = &hw->phy; |
| 202 | u32 i, mdic = 0; |
| 203 | |
| 204 | if (offset > MAX_PHY_REG_ADDRESS) { |
Bruce Allan | 3bb99fe | 2009-11-20 23:25:07 +0000 | [diff] [blame] | 205 | e_dbg("PHY Address %d is out of range\n", offset); |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 206 | return -E1000_ERR_PARAM; |
| 207 | } |
| 208 | |
Bruce Allan | e921eb1 | 2012-11-28 09:28:37 +0000 | [diff] [blame] | 209 | /* Set up Op-code, Phy Address, and register offset in the MDI |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 210 | * Control register. The MAC will take care of interfacing with the |
| 211 | * PHY to retrieve the desired data. |
| 212 | */ |
| 213 | mdic = (((u32)data) | |
| 214 | (offset << E1000_MDIC_REG_SHIFT) | |
| 215 | (phy->addr << E1000_MDIC_PHY_SHIFT) | |
| 216 | (E1000_MDIC_OP_WRITE)); |
| 217 | |
| 218 | ew32(MDIC, mdic); |
| 219 | |
Bruce Allan | e921eb1 | 2012-11-28 09:28:37 +0000 | [diff] [blame] | 220 | /* Poll the ready bit to see if the MDI read completed |
David Graham | 2d9498f | 2008-04-23 11:09:14 -0700 | [diff] [blame] | 221 | * Increasing the time out as testing showed failures with |
| 222 | * the lower time out |
| 223 | */ |
| 224 | for (i = 0; i < (E1000_GEN_POLL_TIMEOUT * 3); i++) { |
Bruce Allan | 274a85e | 2013-03-19 01:47:12 +0000 | [diff] [blame] | 225 | udelay(50); |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 226 | mdic = er32(MDIC); |
| 227 | if (mdic & E1000_MDIC_READY) |
| 228 | break; |
| 229 | } |
| 230 | if (!(mdic & E1000_MDIC_READY)) { |
Bruce Allan | 3bb99fe | 2009-11-20 23:25:07 +0000 | [diff] [blame] | 231 | e_dbg("MDI Write did not complete\n"); |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 232 | return -E1000_ERR_PHY; |
| 233 | } |
David Graham | 2d9498f | 2008-04-23 11:09:14 -0700 | [diff] [blame] | 234 | if (mdic & E1000_MDIC_ERROR) { |
Bruce Allan | 3bb99fe | 2009-11-20 23:25:07 +0000 | [diff] [blame] | 235 | e_dbg("MDI Error\n"); |
David Graham | 2d9498f | 2008-04-23 11:09:14 -0700 | [diff] [blame] | 236 | return -E1000_ERR_PHY; |
| 237 | } |
Bruce Allan | bb03451 | 2013-03-06 09:02:31 +0000 | [diff] [blame] | 238 | if (((mdic & E1000_MDIC_REG_MASK) >> E1000_MDIC_REG_SHIFT) != offset) { |
| 239 | e_dbg("MDI Write offset error - requested %d, returned %d\n", |
| 240 | offset, |
| 241 | (mdic & E1000_MDIC_REG_MASK) >> E1000_MDIC_REG_SHIFT); |
| 242 | return -E1000_ERR_PHY; |
| 243 | } |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 244 | |
Bruce Allan | e921eb1 | 2012-11-28 09:28:37 +0000 | [diff] [blame] | 245 | /* Allow some time after each MDIC transaction to avoid |
Bruce Allan | 664dc87 | 2010-11-24 06:01:46 +0000 | [diff] [blame] | 246 | * reading duplicate data in the next MDIC transaction. |
| 247 | */ |
| 248 | if (hw->mac.type == e1000_pch2lan) |
Bruce Allan | 274a85e | 2013-03-19 01:47:12 +0000 | [diff] [blame] | 249 | udelay(100); |
Bruce Allan | 664dc87 | 2010-11-24 06:01:46 +0000 | [diff] [blame] | 250 | |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 251 | return 0; |
| 252 | } |
| 253 | |
| 254 | /** |
| 255 | * e1000e_read_phy_reg_m88 - Read m88 PHY register |
| 256 | * @hw: pointer to the HW structure |
| 257 | * @offset: register offset to be read |
| 258 | * @data: pointer to the read data |
| 259 | * |
| 260 | * Acquires semaphore, if necessary, then reads the PHY register at offset |
| 261 | * and storing the retrieved information in data. Release any acquired |
| 262 | * semaphores before exiting. |
| 263 | **/ |
| 264 | s32 e1000e_read_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 *data) |
| 265 | { |
| 266 | s32 ret_val; |
| 267 | |
Bruce Allan | 94d8186 | 2009-11-20 23:25:26 +0000 | [diff] [blame] | 268 | ret_val = hw->phy.ops.acquire(hw); |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 269 | if (ret_val) |
| 270 | return ret_val; |
| 271 | |
David Graham | 2d9498f | 2008-04-23 11:09:14 -0700 | [diff] [blame] | 272 | ret_val = e1000e_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset, |
| 273 | data); |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 274 | |
Bruce Allan | 94d8186 | 2009-11-20 23:25:26 +0000 | [diff] [blame] | 275 | hw->phy.ops.release(hw); |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 276 | |
| 277 | return ret_val; |
| 278 | } |
| 279 | |
| 280 | /** |
| 281 | * e1000e_write_phy_reg_m88 - Write m88 PHY register |
| 282 | * @hw: pointer to the HW structure |
| 283 | * @offset: register offset to write to |
| 284 | * @data: data to write at register offset |
| 285 | * |
| 286 | * Acquires semaphore, if necessary, then writes the data to PHY register |
| 287 | * at the offset. Release any acquired semaphores before exiting. |
| 288 | **/ |
| 289 | s32 e1000e_write_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 data) |
| 290 | { |
| 291 | s32 ret_val; |
| 292 | |
Bruce Allan | 94d8186 | 2009-11-20 23:25:26 +0000 | [diff] [blame] | 293 | ret_val = hw->phy.ops.acquire(hw); |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 294 | if (ret_val) |
| 295 | return ret_val; |
| 296 | |
David Graham | 2d9498f | 2008-04-23 11:09:14 -0700 | [diff] [blame] | 297 | ret_val = e1000e_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset, |
| 298 | data); |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 299 | |
Bruce Allan | 94d8186 | 2009-11-20 23:25:26 +0000 | [diff] [blame] | 300 | hw->phy.ops.release(hw); |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 301 | |
| 302 | return ret_val; |
| 303 | } |
| 304 | |
| 305 | /** |
Bruce Allan | 2b6b168 | 2011-05-13 07:20:09 +0000 | [diff] [blame] | 306 | * e1000_set_page_igp - Set page as on IGP-like PHY(s) |
| 307 | * @hw: pointer to the HW structure |
| 308 | * @page: page to set (shifted left when necessary) |
| 309 | * |
| 310 | * Sets PHY page required for PHY register access. Assumes semaphore is |
| 311 | * already acquired. Note, this function sets phy.addr to 1 so the caller |
| 312 | * must set it appropriately (if necessary) after this function returns. |
| 313 | **/ |
| 314 | s32 e1000_set_page_igp(struct e1000_hw *hw, u16 page) |
| 315 | { |
| 316 | e_dbg("Setting page 0x%x\n", page); |
| 317 | |
| 318 | hw->phy.addr = 1; |
| 319 | |
| 320 | return e1000e_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT, page); |
| 321 | } |
| 322 | |
| 323 | /** |
Bruce Allan | 5ccdcec | 2009-10-26 11:24:02 +0000 | [diff] [blame] | 324 | * __e1000e_read_phy_reg_igp - Read igp PHY register |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 325 | * @hw: pointer to the HW structure |
| 326 | * @offset: register offset to be read |
| 327 | * @data: pointer to the read data |
Bruce Allan | 5ccdcec | 2009-10-26 11:24:02 +0000 | [diff] [blame] | 328 | * @locked: semaphore has already been acquired or not |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 329 | * |
| 330 | * Acquires semaphore, if necessary, then reads the PHY register at offset |
Bruce Allan | 5ccdcec | 2009-10-26 11:24:02 +0000 | [diff] [blame] | 331 | * and stores the retrieved information in data. Release any acquired |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 332 | * semaphores before exiting. |
| 333 | **/ |
Bruce Allan | 5ccdcec | 2009-10-26 11:24:02 +0000 | [diff] [blame] | 334 | static s32 __e1000e_read_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 *data, |
Bruce Allan | 66501f5 | 2013-02-20 04:05:55 +0000 | [diff] [blame] | 335 | bool locked) |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 336 | { |
Bruce Allan | 5ccdcec | 2009-10-26 11:24:02 +0000 | [diff] [blame] | 337 | s32 ret_val = 0; |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 338 | |
Bruce Allan | 5ccdcec | 2009-10-26 11:24:02 +0000 | [diff] [blame] | 339 | if (!locked) { |
Bruce Allan | 668018d | 2012-01-31 07:02:56 +0000 | [diff] [blame] | 340 | if (!hw->phy.ops.acquire) |
Bruce Allan | 5015e53 | 2012-02-08 02:55:56 +0000 | [diff] [blame] | 341 | return 0; |
Bruce Allan | 5ccdcec | 2009-10-26 11:24:02 +0000 | [diff] [blame] | 342 | |
Bruce Allan | 94d8186 | 2009-11-20 23:25:26 +0000 | [diff] [blame] | 343 | ret_val = hw->phy.ops.acquire(hw); |
Bruce Allan | 5ccdcec | 2009-10-26 11:24:02 +0000 | [diff] [blame] | 344 | if (ret_val) |
Bruce Allan | 5015e53 | 2012-02-08 02:55:56 +0000 | [diff] [blame] | 345 | return ret_val; |
Bruce Allan | 5ccdcec | 2009-10-26 11:24:02 +0000 | [diff] [blame] | 346 | } |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 347 | |
Bruce Allan | 5015e53 | 2012-02-08 02:55:56 +0000 | [diff] [blame] | 348 | if (offset > MAX_PHY_MULTI_PAGE_REG) |
David Graham | 2d9498f | 2008-04-23 11:09:14 -0700 | [diff] [blame] | 349 | ret_val = e1000e_write_phy_reg_mdic(hw, |
| 350 | IGP01E1000_PHY_PAGE_SELECT, |
| 351 | (u16)offset); |
Bruce Allan | 5015e53 | 2012-02-08 02:55:56 +0000 | [diff] [blame] | 352 | if (!ret_val) |
| 353 | ret_val = e1000e_read_phy_reg_mdic(hw, |
| 354 | MAX_PHY_REG_ADDRESS & offset, |
| 355 | data); |
Bruce Allan | 5ccdcec | 2009-10-26 11:24:02 +0000 | [diff] [blame] | 356 | if (!locked) |
Bruce Allan | 94d8186 | 2009-11-20 23:25:26 +0000 | [diff] [blame] | 357 | hw->phy.ops.release(hw); |
Bruce Allan | 5015e53 | 2012-02-08 02:55:56 +0000 | [diff] [blame] | 358 | |
Bruce Allan | 5ccdcec | 2009-10-26 11:24:02 +0000 | [diff] [blame] | 359 | return ret_val; |
| 360 | } |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 361 | |
Bruce Allan | 5ccdcec | 2009-10-26 11:24:02 +0000 | [diff] [blame] | 362 | /** |
| 363 | * e1000e_read_phy_reg_igp - Read igp PHY register |
| 364 | * @hw: pointer to the HW structure |
| 365 | * @offset: register offset to be read |
| 366 | * @data: pointer to the read data |
| 367 | * |
| 368 | * Acquires semaphore then reads the PHY register at offset and stores the |
| 369 | * retrieved information in data. |
| 370 | * Release the acquired semaphore before exiting. |
| 371 | **/ |
| 372 | s32 e1000e_read_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 *data) |
| 373 | { |
| 374 | return __e1000e_read_phy_reg_igp(hw, offset, data, false); |
| 375 | } |
| 376 | |
| 377 | /** |
| 378 | * e1000e_read_phy_reg_igp_locked - Read igp PHY register |
| 379 | * @hw: pointer to the HW structure |
| 380 | * @offset: register offset to be read |
| 381 | * @data: pointer to the read data |
| 382 | * |
| 383 | * Reads the PHY register at offset and stores the retrieved information |
| 384 | * in data. Assumes semaphore already acquired. |
| 385 | **/ |
| 386 | s32 e1000e_read_phy_reg_igp_locked(struct e1000_hw *hw, u32 offset, u16 *data) |
| 387 | { |
| 388 | return __e1000e_read_phy_reg_igp(hw, offset, data, true); |
| 389 | } |
| 390 | |
| 391 | /** |
| 392 | * e1000e_write_phy_reg_igp - Write igp PHY register |
| 393 | * @hw: pointer to the HW structure |
| 394 | * @offset: register offset to write to |
| 395 | * @data: data to write at register offset |
| 396 | * @locked: semaphore has already been acquired or not |
| 397 | * |
| 398 | * Acquires semaphore, if necessary, then writes the data to PHY register |
| 399 | * at the offset. Release any acquired semaphores before exiting. |
| 400 | **/ |
| 401 | static s32 __e1000e_write_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 data, |
Bruce Allan | 66501f5 | 2013-02-20 04:05:55 +0000 | [diff] [blame] | 402 | bool locked) |
Bruce Allan | 5ccdcec | 2009-10-26 11:24:02 +0000 | [diff] [blame] | 403 | { |
| 404 | s32 ret_val = 0; |
| 405 | |
| 406 | if (!locked) { |
Bruce Allan | 668018d | 2012-01-31 07:02:56 +0000 | [diff] [blame] | 407 | if (!hw->phy.ops.acquire) |
Bruce Allan | 5015e53 | 2012-02-08 02:55:56 +0000 | [diff] [blame] | 408 | return 0; |
Bruce Allan | 5ccdcec | 2009-10-26 11:24:02 +0000 | [diff] [blame] | 409 | |
Bruce Allan | 94d8186 | 2009-11-20 23:25:26 +0000 | [diff] [blame] | 410 | ret_val = hw->phy.ops.acquire(hw); |
Bruce Allan | 5ccdcec | 2009-10-26 11:24:02 +0000 | [diff] [blame] | 411 | if (ret_val) |
Bruce Allan | 5015e53 | 2012-02-08 02:55:56 +0000 | [diff] [blame] | 412 | return ret_val; |
Bruce Allan | 5ccdcec | 2009-10-26 11:24:02 +0000 | [diff] [blame] | 413 | } |
| 414 | |
Bruce Allan | 5015e53 | 2012-02-08 02:55:56 +0000 | [diff] [blame] | 415 | if (offset > MAX_PHY_MULTI_PAGE_REG) |
Bruce Allan | 5ccdcec | 2009-10-26 11:24:02 +0000 | [diff] [blame] | 416 | ret_val = e1000e_write_phy_reg_mdic(hw, |
| 417 | IGP01E1000_PHY_PAGE_SELECT, |
| 418 | (u16)offset); |
Bruce Allan | 5015e53 | 2012-02-08 02:55:56 +0000 | [diff] [blame] | 419 | if (!ret_val) |
| 420 | ret_val = e1000e_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & |
Bruce Allan | 17e813e | 2013-02-20 04:06:01 +0000 | [diff] [blame] | 421 | offset, data); |
Bruce Allan | 5ccdcec | 2009-10-26 11:24:02 +0000 | [diff] [blame] | 422 | if (!locked) |
Bruce Allan | 94d8186 | 2009-11-20 23:25:26 +0000 | [diff] [blame] | 423 | hw->phy.ops.release(hw); |
Bruce Allan | 5ccdcec | 2009-10-26 11:24:02 +0000 | [diff] [blame] | 424 | |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 425 | return ret_val; |
| 426 | } |
| 427 | |
| 428 | /** |
| 429 | * e1000e_write_phy_reg_igp - Write igp PHY register |
| 430 | * @hw: pointer to the HW structure |
| 431 | * @offset: register offset to write to |
| 432 | * @data: data to write at register offset |
| 433 | * |
Bruce Allan | 5ccdcec | 2009-10-26 11:24:02 +0000 | [diff] [blame] | 434 | * Acquires semaphore then writes the data to PHY register |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 435 | * at the offset. Release any acquired semaphores before exiting. |
| 436 | **/ |
| 437 | s32 e1000e_write_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 data) |
| 438 | { |
Bruce Allan | 5ccdcec | 2009-10-26 11:24:02 +0000 | [diff] [blame] | 439 | return __e1000e_write_phy_reg_igp(hw, offset, data, false); |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 440 | } |
| 441 | |
| 442 | /** |
Bruce Allan | 5ccdcec | 2009-10-26 11:24:02 +0000 | [diff] [blame] | 443 | * e1000e_write_phy_reg_igp_locked - Write igp PHY register |
| 444 | * @hw: pointer to the HW structure |
| 445 | * @offset: register offset to write to |
| 446 | * @data: data to write at register offset |
| 447 | * |
| 448 | * Writes the data to PHY register at the offset. |
| 449 | * Assumes semaphore already acquired. |
| 450 | **/ |
| 451 | s32 e1000e_write_phy_reg_igp_locked(struct e1000_hw *hw, u32 offset, u16 data) |
| 452 | { |
| 453 | return __e1000e_write_phy_reg_igp(hw, offset, data, true); |
| 454 | } |
| 455 | |
| 456 | /** |
| 457 | * __e1000_read_kmrn_reg - Read kumeran register |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 458 | * @hw: pointer to the HW structure |
| 459 | * @offset: register offset to be read |
| 460 | * @data: pointer to the read data |
Bruce Allan | 5ccdcec | 2009-10-26 11:24:02 +0000 | [diff] [blame] | 461 | * @locked: semaphore has already been acquired or not |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 462 | * |
| 463 | * Acquires semaphore, if necessary. Then reads the PHY register at offset |
| 464 | * using the kumeran interface. The information retrieved is stored in data. |
| 465 | * Release any acquired semaphores before exiting. |
| 466 | **/ |
Bruce Allan | 5ccdcec | 2009-10-26 11:24:02 +0000 | [diff] [blame] | 467 | static s32 __e1000_read_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 *data, |
Bruce Allan | 66501f5 | 2013-02-20 04:05:55 +0000 | [diff] [blame] | 468 | bool locked) |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 469 | { |
| 470 | u32 kmrnctrlsta; |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 471 | |
Bruce Allan | 5ccdcec | 2009-10-26 11:24:02 +0000 | [diff] [blame] | 472 | if (!locked) { |
Bruce Allan | 5015e53 | 2012-02-08 02:55:56 +0000 | [diff] [blame] | 473 | s32 ret_val = 0; |
| 474 | |
Bruce Allan | 668018d | 2012-01-31 07:02:56 +0000 | [diff] [blame] | 475 | if (!hw->phy.ops.acquire) |
Bruce Allan | 5015e53 | 2012-02-08 02:55:56 +0000 | [diff] [blame] | 476 | return 0; |
Bruce Allan | 5ccdcec | 2009-10-26 11:24:02 +0000 | [diff] [blame] | 477 | |
Bruce Allan | 94d8186 | 2009-11-20 23:25:26 +0000 | [diff] [blame] | 478 | ret_val = hw->phy.ops.acquire(hw); |
Bruce Allan | 5ccdcec | 2009-10-26 11:24:02 +0000 | [diff] [blame] | 479 | if (ret_val) |
Bruce Allan | 5015e53 | 2012-02-08 02:55:56 +0000 | [diff] [blame] | 480 | return ret_val; |
Bruce Allan | 5ccdcec | 2009-10-26 11:24:02 +0000 | [diff] [blame] | 481 | } |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 482 | |
| 483 | kmrnctrlsta = ((offset << E1000_KMRNCTRLSTA_OFFSET_SHIFT) & |
| 484 | E1000_KMRNCTRLSTA_OFFSET) | E1000_KMRNCTRLSTA_REN; |
| 485 | ew32(KMRNCTRLSTA, kmrnctrlsta); |
Jesse Brandeburg | 945a515 | 2011-07-20 00:56:21 +0000 | [diff] [blame] | 486 | e1e_flush(); |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 487 | |
| 488 | udelay(2); |
| 489 | |
| 490 | kmrnctrlsta = er32(KMRNCTRLSTA); |
| 491 | *data = (u16)kmrnctrlsta; |
| 492 | |
Bruce Allan | 5ccdcec | 2009-10-26 11:24:02 +0000 | [diff] [blame] | 493 | if (!locked) |
Bruce Allan | 94d8186 | 2009-11-20 23:25:26 +0000 | [diff] [blame] | 494 | hw->phy.ops.release(hw); |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 495 | |
Bruce Allan | 5015e53 | 2012-02-08 02:55:56 +0000 | [diff] [blame] | 496 | return 0; |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 497 | } |
| 498 | |
| 499 | /** |
Bruce Allan | 5ccdcec | 2009-10-26 11:24:02 +0000 | [diff] [blame] | 500 | * e1000e_read_kmrn_reg - Read kumeran register |
| 501 | * @hw: pointer to the HW structure |
| 502 | * @offset: register offset to be read |
| 503 | * @data: pointer to the read data |
| 504 | * |
| 505 | * Acquires semaphore then reads the PHY register at offset using the |
| 506 | * kumeran interface. The information retrieved is stored in data. |
| 507 | * Release the acquired semaphore before exiting. |
| 508 | **/ |
| 509 | s32 e1000e_read_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 *data) |
| 510 | { |
| 511 | return __e1000_read_kmrn_reg(hw, offset, data, false); |
| 512 | } |
| 513 | |
| 514 | /** |
Bruce Allan | 1d5846b | 2009-10-29 13:46:05 +0000 | [diff] [blame] | 515 | * e1000e_read_kmrn_reg_locked - Read kumeran register |
Bruce Allan | 5ccdcec | 2009-10-26 11:24:02 +0000 | [diff] [blame] | 516 | * @hw: pointer to the HW structure |
| 517 | * @offset: register offset to be read |
| 518 | * @data: pointer to the read data |
| 519 | * |
| 520 | * Reads the PHY register at offset using the kumeran interface. The |
| 521 | * information retrieved is stored in data. |
| 522 | * Assumes semaphore already acquired. |
| 523 | **/ |
Bruce Allan | 1d5846b | 2009-10-29 13:46:05 +0000 | [diff] [blame] | 524 | s32 e1000e_read_kmrn_reg_locked(struct e1000_hw *hw, u32 offset, u16 *data) |
Bruce Allan | 5ccdcec | 2009-10-26 11:24:02 +0000 | [diff] [blame] | 525 | { |
| 526 | return __e1000_read_kmrn_reg(hw, offset, data, true); |
| 527 | } |
| 528 | |
| 529 | /** |
| 530 | * __e1000_write_kmrn_reg - Write kumeran register |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 531 | * @hw: pointer to the HW structure |
| 532 | * @offset: register offset to write to |
| 533 | * @data: data to write at register offset |
Bruce Allan | 5ccdcec | 2009-10-26 11:24:02 +0000 | [diff] [blame] | 534 | * @locked: semaphore has already been acquired or not |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 535 | * |
| 536 | * Acquires semaphore, if necessary. Then write the data to PHY register |
| 537 | * at the offset using the kumeran interface. Release any acquired semaphores |
| 538 | * before exiting. |
| 539 | **/ |
Bruce Allan | 5ccdcec | 2009-10-26 11:24:02 +0000 | [diff] [blame] | 540 | static s32 __e1000_write_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 data, |
Bruce Allan | 66501f5 | 2013-02-20 04:05:55 +0000 | [diff] [blame] | 541 | bool locked) |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 542 | { |
| 543 | u32 kmrnctrlsta; |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 544 | |
Bruce Allan | 5ccdcec | 2009-10-26 11:24:02 +0000 | [diff] [blame] | 545 | if (!locked) { |
Bruce Allan | 5015e53 | 2012-02-08 02:55:56 +0000 | [diff] [blame] | 546 | s32 ret_val = 0; |
| 547 | |
Bruce Allan | 668018d | 2012-01-31 07:02:56 +0000 | [diff] [blame] | 548 | if (!hw->phy.ops.acquire) |
Bruce Allan | 5015e53 | 2012-02-08 02:55:56 +0000 | [diff] [blame] | 549 | return 0; |
Bruce Allan | 5ccdcec | 2009-10-26 11:24:02 +0000 | [diff] [blame] | 550 | |
Bruce Allan | 94d8186 | 2009-11-20 23:25:26 +0000 | [diff] [blame] | 551 | ret_val = hw->phy.ops.acquire(hw); |
Bruce Allan | 5ccdcec | 2009-10-26 11:24:02 +0000 | [diff] [blame] | 552 | if (ret_val) |
Bruce Allan | 5015e53 | 2012-02-08 02:55:56 +0000 | [diff] [blame] | 553 | return ret_val; |
Bruce Allan | 5ccdcec | 2009-10-26 11:24:02 +0000 | [diff] [blame] | 554 | } |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 555 | |
| 556 | kmrnctrlsta = ((offset << E1000_KMRNCTRLSTA_OFFSET_SHIFT) & |
| 557 | E1000_KMRNCTRLSTA_OFFSET) | data; |
| 558 | ew32(KMRNCTRLSTA, kmrnctrlsta); |
Jesse Brandeburg | 945a515 | 2011-07-20 00:56:21 +0000 | [diff] [blame] | 559 | e1e_flush(); |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 560 | |
| 561 | udelay(2); |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 562 | |
Bruce Allan | 5ccdcec | 2009-10-26 11:24:02 +0000 | [diff] [blame] | 563 | if (!locked) |
Bruce Allan | 94d8186 | 2009-11-20 23:25:26 +0000 | [diff] [blame] | 564 | hw->phy.ops.release(hw); |
Bruce Allan | 5ccdcec | 2009-10-26 11:24:02 +0000 | [diff] [blame] | 565 | |
Bruce Allan | 5015e53 | 2012-02-08 02:55:56 +0000 | [diff] [blame] | 566 | return 0; |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 567 | } |
| 568 | |
| 569 | /** |
Bruce Allan | 5ccdcec | 2009-10-26 11:24:02 +0000 | [diff] [blame] | 570 | * e1000e_write_kmrn_reg - Write kumeran register |
| 571 | * @hw: pointer to the HW structure |
| 572 | * @offset: register offset to write to |
| 573 | * @data: data to write at register offset |
| 574 | * |
| 575 | * Acquires semaphore then writes the data to the PHY register at the offset |
| 576 | * using the kumeran interface. Release the acquired semaphore before exiting. |
| 577 | **/ |
| 578 | s32 e1000e_write_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 data) |
| 579 | { |
| 580 | return __e1000_write_kmrn_reg(hw, offset, data, false); |
| 581 | } |
| 582 | |
| 583 | /** |
Bruce Allan | 1d5846b | 2009-10-29 13:46:05 +0000 | [diff] [blame] | 584 | * e1000e_write_kmrn_reg_locked - Write kumeran register |
Bruce Allan | 5ccdcec | 2009-10-26 11:24:02 +0000 | [diff] [blame] | 585 | * @hw: pointer to the HW structure |
| 586 | * @offset: register offset to write to |
| 587 | * @data: data to write at register offset |
| 588 | * |
| 589 | * Write the data to PHY register at the offset using the kumeran interface. |
| 590 | * Assumes semaphore already acquired. |
| 591 | **/ |
Bruce Allan | 1d5846b | 2009-10-29 13:46:05 +0000 | [diff] [blame] | 592 | s32 e1000e_write_kmrn_reg_locked(struct e1000_hw *hw, u32 offset, u16 data) |
Bruce Allan | 5ccdcec | 2009-10-26 11:24:02 +0000 | [diff] [blame] | 593 | { |
| 594 | return __e1000_write_kmrn_reg(hw, offset, data, true); |
| 595 | } |
| 596 | |
| 597 | /** |
Bruce Allan | 7b9f7e3 | 2012-03-20 03:47:41 +0000 | [diff] [blame] | 598 | * e1000_set_master_slave_mode - Setup PHY for Master/slave mode |
| 599 | * @hw: pointer to the HW structure |
| 600 | * |
| 601 | * Sets up Master/slave mode |
| 602 | **/ |
| 603 | static s32 e1000_set_master_slave_mode(struct e1000_hw *hw) |
| 604 | { |
| 605 | s32 ret_val; |
| 606 | u16 phy_data; |
| 607 | |
| 608 | /* Resolve Master/Slave mode */ |
Bruce Allan | c2ade1a | 2013-01-16 08:54:35 +0000 | [diff] [blame] | 609 | ret_val = e1e_rphy(hw, MII_CTRL1000, &phy_data); |
Bruce Allan | 7b9f7e3 | 2012-03-20 03:47:41 +0000 | [diff] [blame] | 610 | if (ret_val) |
| 611 | return ret_val; |
| 612 | |
| 613 | /* load defaults for future use */ |
Bruce Allan | c2ade1a | 2013-01-16 08:54:35 +0000 | [diff] [blame] | 614 | hw->phy.original_ms_type = (phy_data & CTL1000_ENABLE_MASTER) ? |
| 615 | ((phy_data & CTL1000_AS_MASTER) ? |
Bruce Allan | 7b9f7e3 | 2012-03-20 03:47:41 +0000 | [diff] [blame] | 616 | e1000_ms_force_master : e1000_ms_force_slave) : e1000_ms_auto; |
| 617 | |
| 618 | switch (hw->phy.ms_type) { |
| 619 | case e1000_ms_force_master: |
Bruce Allan | c2ade1a | 2013-01-16 08:54:35 +0000 | [diff] [blame] | 620 | phy_data |= (CTL1000_ENABLE_MASTER | CTL1000_AS_MASTER); |
Bruce Allan | 7b9f7e3 | 2012-03-20 03:47:41 +0000 | [diff] [blame] | 621 | break; |
| 622 | case e1000_ms_force_slave: |
Bruce Allan | c2ade1a | 2013-01-16 08:54:35 +0000 | [diff] [blame] | 623 | phy_data |= CTL1000_ENABLE_MASTER; |
| 624 | phy_data &= ~(CTL1000_AS_MASTER); |
Bruce Allan | 7b9f7e3 | 2012-03-20 03:47:41 +0000 | [diff] [blame] | 625 | break; |
| 626 | case e1000_ms_auto: |
Bruce Allan | c2ade1a | 2013-01-16 08:54:35 +0000 | [diff] [blame] | 627 | phy_data &= ~CTL1000_ENABLE_MASTER; |
Bruce Allan | 7b9f7e3 | 2012-03-20 03:47:41 +0000 | [diff] [blame] | 628 | /* fall-through */ |
| 629 | default: |
| 630 | break; |
| 631 | } |
| 632 | |
Bruce Allan | c2ade1a | 2013-01-16 08:54:35 +0000 | [diff] [blame] | 633 | return e1e_wphy(hw, MII_CTRL1000, phy_data); |
Bruce Allan | 7b9f7e3 | 2012-03-20 03:47:41 +0000 | [diff] [blame] | 634 | } |
| 635 | |
| 636 | /** |
Bruce Allan | a4f58f5 | 2009-06-02 11:29:18 +0000 | [diff] [blame] | 637 | * e1000_copper_link_setup_82577 - Setup 82577 PHY for copper link |
| 638 | * @hw: pointer to the HW structure |
| 639 | * |
| 640 | * Sets up Carrier-sense on Transmit and downshift values. |
| 641 | **/ |
| 642 | s32 e1000_copper_link_setup_82577(struct e1000_hw *hw) |
| 643 | { |
Bruce Allan | a4f58f5 | 2009-06-02 11:29:18 +0000 | [diff] [blame] | 644 | s32 ret_val; |
| 645 | u16 phy_data; |
| 646 | |
Bruce Allan | af667a2 | 2010-12-31 06:10:01 +0000 | [diff] [blame] | 647 | /* Enable CRS on Tx. This must be set for half-duplex operation. */ |
Bruce Allan | 482fed8 | 2011-01-06 14:29:49 +0000 | [diff] [blame] | 648 | ret_val = e1e_rphy(hw, I82577_CFG_REG, &phy_data); |
Bruce Allan | a4f58f5 | 2009-06-02 11:29:18 +0000 | [diff] [blame] | 649 | if (ret_val) |
Bruce Allan | 5015e53 | 2012-02-08 02:55:56 +0000 | [diff] [blame] | 650 | return ret_val; |
Bruce Allan | a4f58f5 | 2009-06-02 11:29:18 +0000 | [diff] [blame] | 651 | |
| 652 | phy_data |= I82577_CFG_ASSERT_CRS_ON_TX; |
| 653 | |
| 654 | /* Enable downshift */ |
| 655 | phy_data |= I82577_CFG_ENABLE_DOWNSHIFT; |
| 656 | |
Bruce Allan | 7b9f7e3 | 2012-03-20 03:47:41 +0000 | [diff] [blame] | 657 | ret_val = e1e_wphy(hw, I82577_CFG_REG, phy_data); |
| 658 | if (ret_val) |
| 659 | return ret_val; |
| 660 | |
Bruce W Allan | e86fd89 | 2012-07-26 02:30:59 +0000 | [diff] [blame] | 661 | /* Set MDI/MDIX mode */ |
| 662 | ret_val = e1e_rphy(hw, I82577_PHY_CTRL_2, &phy_data); |
| 663 | if (ret_val) |
| 664 | return ret_val; |
| 665 | phy_data &= ~I82577_PHY_CTRL2_MDIX_CFG_MASK; |
Bruce Allan | e921eb1 | 2012-11-28 09:28:37 +0000 | [diff] [blame] | 666 | /* Options: |
Bruce W Allan | e86fd89 | 2012-07-26 02:30:59 +0000 | [diff] [blame] | 667 | * 0 - Auto (default) |
| 668 | * 1 - MDI mode |
| 669 | * 2 - MDI-X mode |
| 670 | */ |
| 671 | switch (hw->phy.mdix) { |
| 672 | case 1: |
| 673 | break; |
| 674 | case 2: |
| 675 | phy_data |= I82577_PHY_CTRL2_MANUAL_MDIX; |
| 676 | break; |
| 677 | case 0: |
| 678 | default: |
| 679 | phy_data |= I82577_PHY_CTRL2_AUTO_MDI_MDIX; |
| 680 | break; |
| 681 | } |
| 682 | ret_val = e1e_wphy(hw, I82577_PHY_CTRL_2, phy_data); |
| 683 | if (ret_val) |
| 684 | return ret_val; |
| 685 | |
Bruce Allan | 7b9f7e3 | 2012-03-20 03:47:41 +0000 | [diff] [blame] | 686 | return e1000_set_master_slave_mode(hw); |
Bruce Allan | a4f58f5 | 2009-06-02 11:29:18 +0000 | [diff] [blame] | 687 | } |
| 688 | |
| 689 | /** |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 690 | * e1000e_copper_link_setup_m88 - Setup m88 PHY's for copper link |
| 691 | * @hw: pointer to the HW structure |
| 692 | * |
| 693 | * Sets up MDI/MDI-X and polarity for m88 PHY's. If necessary, transmit clock |
| 694 | * and downshift values are set also. |
| 695 | **/ |
| 696 | s32 e1000e_copper_link_setup_m88(struct e1000_hw *hw) |
| 697 | { |
| 698 | struct e1000_phy_info *phy = &hw->phy; |
| 699 | s32 ret_val; |
| 700 | u16 phy_data; |
| 701 | |
Bruce Allan | ad68076 | 2008-03-28 09:15:03 -0700 | [diff] [blame] | 702 | /* Enable CRS on Tx. This must be set for half-duplex operation. */ |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 703 | ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); |
| 704 | if (ret_val) |
| 705 | return ret_val; |
| 706 | |
Bruce Allan | a4f58f5 | 2009-06-02 11:29:18 +0000 | [diff] [blame] | 707 | /* For BM PHY this bit is downshift enable */ |
| 708 | if (phy->type != e1000_phy_bm) |
David Graham | 2d9498f | 2008-04-23 11:09:14 -0700 | [diff] [blame] | 709 | phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX; |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 710 | |
Bruce Allan | e921eb1 | 2012-11-28 09:28:37 +0000 | [diff] [blame] | 711 | /* Options: |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 712 | * MDI/MDI-X = 0 (default) |
| 713 | * 0 - Auto for all speeds |
| 714 | * 1 - MDI mode |
| 715 | * 2 - MDI-X mode |
| 716 | * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes) |
| 717 | */ |
| 718 | phy_data &= ~M88E1000_PSCR_AUTO_X_MODE; |
| 719 | |
| 720 | switch (phy->mdix) { |
| 721 | case 1: |
| 722 | phy_data |= M88E1000_PSCR_MDI_MANUAL_MODE; |
| 723 | break; |
| 724 | case 2: |
| 725 | phy_data |= M88E1000_PSCR_MDIX_MANUAL_MODE; |
| 726 | break; |
| 727 | case 3: |
| 728 | phy_data |= M88E1000_PSCR_AUTO_X_1000T; |
| 729 | break; |
| 730 | case 0: |
| 731 | default: |
| 732 | phy_data |= M88E1000_PSCR_AUTO_X_MODE; |
| 733 | break; |
| 734 | } |
| 735 | |
Bruce Allan | e921eb1 | 2012-11-28 09:28:37 +0000 | [diff] [blame] | 736 | /* Options: |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 737 | * disable_polarity_correction = 0 (default) |
| 738 | * Automatic Correction for Reversed Cable Polarity |
| 739 | * 0 - Disabled |
| 740 | * 1 - Enabled |
| 741 | */ |
| 742 | phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL; |
Bruce Allan | 04499ec | 2012-04-13 00:08:31 +0000 | [diff] [blame] | 743 | if (phy->disable_polarity_correction) |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 744 | phy_data |= M88E1000_PSCR_POLARITY_REVERSAL; |
| 745 | |
Bruce Allan | 97ac8ca | 2008-04-29 09:16:05 -0700 | [diff] [blame] | 746 | /* Enable downshift on BM (disabled by default) */ |
Matthew Vick | 885fe7b | 2012-04-25 07:25:18 +0000 | [diff] [blame] | 747 | if (phy->type == e1000_phy_bm) { |
| 748 | /* For 82574/82583, first disable then enable downshift */ |
| 749 | if (phy->id == BME1000_E_PHY_ID_R2) { |
| 750 | phy_data &= ~BME1000_PSCR_ENABLE_DOWNSHIFT; |
| 751 | ret_val = e1e_wphy(hw, M88E1000_PHY_SPEC_CTRL, |
| 752 | phy_data); |
| 753 | if (ret_val) |
| 754 | return ret_val; |
| 755 | /* Commit the changes. */ |
Bruce Allan | 6b598e1 | 2013-01-23 06:50:05 +0000 | [diff] [blame] | 756 | ret_val = phy->ops.commit(hw); |
Matthew Vick | 885fe7b | 2012-04-25 07:25:18 +0000 | [diff] [blame] | 757 | if (ret_val) { |
| 758 | e_dbg("Error committing the PHY changes\n"); |
| 759 | return ret_val; |
| 760 | } |
| 761 | } |
| 762 | |
Bruce Allan | 97ac8ca | 2008-04-29 09:16:05 -0700 | [diff] [blame] | 763 | phy_data |= BME1000_PSCR_ENABLE_DOWNSHIFT; |
Matthew Vick | 885fe7b | 2012-04-25 07:25:18 +0000 | [diff] [blame] | 764 | } |
Bruce Allan | 97ac8ca | 2008-04-29 09:16:05 -0700 | [diff] [blame] | 765 | |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 766 | ret_val = e1e_wphy(hw, M88E1000_PHY_SPEC_CTRL, phy_data); |
| 767 | if (ret_val) |
| 768 | return ret_val; |
| 769 | |
Bruce Allan | 4662e82 | 2008-08-26 18:37:06 -0700 | [diff] [blame] | 770 | if ((phy->type == e1000_phy_m88) && |
| 771 | (phy->revision < E1000_REVISION_4) && |
| 772 | (phy->id != BME1000_E_PHY_ID_R2)) { |
Bruce Allan | e921eb1 | 2012-11-28 09:28:37 +0000 | [diff] [blame] | 773 | /* Force TX_CLK in the Extended PHY Specific Control Register |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 774 | * to 25MHz clock. |
| 775 | */ |
| 776 | ret_val = e1e_rphy(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data); |
| 777 | if (ret_val) |
| 778 | return ret_val; |
| 779 | |
| 780 | phy_data |= M88E1000_EPSCR_TX_CLK_25; |
| 781 | |
Bruce Allan | e5fe254 | 2013-02-20 04:06:27 +0000 | [diff] [blame] | 782 | if ((phy->revision == 2) && (phy->id == M88E1111_I_PHY_ID)) { |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 783 | /* 82573L PHY - set the downshift counter to 5x. */ |
| 784 | phy_data &= ~M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK; |
| 785 | phy_data |= M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X; |
| 786 | } else { |
| 787 | /* Configure Master and Slave downshift values */ |
| 788 | phy_data &= ~(M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK | |
| 789 | M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK); |
| 790 | phy_data |= (M88E1000_EPSCR_MASTER_DOWNSHIFT_1X | |
| 791 | M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X); |
| 792 | } |
| 793 | ret_val = e1e_wphy(hw, M88E1000_EXT_PHY_SPEC_CTRL, phy_data); |
| 794 | if (ret_val) |
| 795 | return ret_val; |
| 796 | } |
| 797 | |
Bruce Allan | 4662e82 | 2008-08-26 18:37:06 -0700 | [diff] [blame] | 798 | if ((phy->type == e1000_phy_bm) && (phy->id == BME1000_E_PHY_ID_R2)) { |
| 799 | /* Set PHY page 0, register 29 to 0x0003 */ |
| 800 | ret_val = e1e_wphy(hw, 29, 0x0003); |
| 801 | if (ret_val) |
| 802 | return ret_val; |
| 803 | |
| 804 | /* Set PHY page 0, register 30 to 0x0000 */ |
| 805 | ret_val = e1e_wphy(hw, 30, 0x0000); |
| 806 | if (ret_val) |
| 807 | return ret_val; |
| 808 | } |
| 809 | |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 810 | /* Commit the changes. */ |
Bruce Allan | 6b598e1 | 2013-01-23 06:50:05 +0000 | [diff] [blame] | 811 | if (phy->ops.commit) { |
| 812 | ret_val = phy->ops.commit(hw); |
| 813 | if (ret_val) { |
| 814 | e_dbg("Error committing the PHY changes\n"); |
| 815 | return ret_val; |
| 816 | } |
Bruce Allan | a4f58f5 | 2009-06-02 11:29:18 +0000 | [diff] [blame] | 817 | } |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 818 | |
Bruce Allan | a4f58f5 | 2009-06-02 11:29:18 +0000 | [diff] [blame] | 819 | if (phy->type == e1000_phy_82578) { |
Bruce Allan | 482fed8 | 2011-01-06 14:29:49 +0000 | [diff] [blame] | 820 | ret_val = e1e_rphy(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data); |
Bruce Allan | a4f58f5 | 2009-06-02 11:29:18 +0000 | [diff] [blame] | 821 | if (ret_val) |
| 822 | return ret_val; |
| 823 | |
| 824 | /* 82578 PHY - set the downshift count to 1x. */ |
| 825 | phy_data |= I82578_EPSCR_DOWNSHIFT_ENABLE; |
| 826 | phy_data &= ~I82578_EPSCR_DOWNSHIFT_COUNTER_MASK; |
Bruce Allan | 482fed8 | 2011-01-06 14:29:49 +0000 | [diff] [blame] | 827 | ret_val = e1e_wphy(hw, M88E1000_EXT_PHY_SPEC_CTRL, phy_data); |
Bruce Allan | a4f58f5 | 2009-06-02 11:29:18 +0000 | [diff] [blame] | 828 | if (ret_val) |
| 829 | return ret_val; |
| 830 | } |
| 831 | |
| 832 | return 0; |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 833 | } |
| 834 | |
| 835 | /** |
| 836 | * e1000e_copper_link_setup_igp - Setup igp PHY's for copper link |
| 837 | * @hw: pointer to the HW structure |
| 838 | * |
| 839 | * Sets up LPLU, MDI/MDI-X, polarity, Smartspeed and Master/Slave config for |
| 840 | * igp PHY's. |
| 841 | **/ |
| 842 | s32 e1000e_copper_link_setup_igp(struct e1000_hw *hw) |
| 843 | { |
| 844 | struct e1000_phy_info *phy = &hw->phy; |
| 845 | s32 ret_val; |
| 846 | u16 data; |
| 847 | |
| 848 | ret_val = e1000_phy_hw_reset(hw); |
| 849 | if (ret_val) { |
Bruce Allan | 3bb99fe | 2009-11-20 23:25:07 +0000 | [diff] [blame] | 850 | e_dbg("Error resetting the PHY.\n"); |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 851 | return ret_val; |
| 852 | } |
| 853 | |
Bruce Allan | e921eb1 | 2012-11-28 09:28:37 +0000 | [diff] [blame] | 854 | /* Wait 100ms for MAC to configure PHY from NVM settings, to avoid |
David Graham | 2d9498f | 2008-04-23 11:09:14 -0700 | [diff] [blame] | 855 | * timeout issues when LFS is enabled. |
| 856 | */ |
| 857 | msleep(100); |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 858 | |
| 859 | /* disable lplu d0 during driver init */ |
Bruce Allan | 7de89f0 | 2013-01-05 08:06:03 +0000 | [diff] [blame] | 860 | if (hw->phy.ops.set_d0_lplu_state) { |
| 861 | ret_val = hw->phy.ops.set_d0_lplu_state(hw, false); |
| 862 | if (ret_val) { |
| 863 | e_dbg("Error Disabling LPLU D0\n"); |
| 864 | return ret_val; |
| 865 | } |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 866 | } |
| 867 | /* Configure mdi-mdix settings */ |
| 868 | ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CTRL, &data); |
| 869 | if (ret_val) |
| 870 | return ret_val; |
| 871 | |
| 872 | data &= ~IGP01E1000_PSCR_AUTO_MDIX; |
| 873 | |
| 874 | switch (phy->mdix) { |
| 875 | case 1: |
| 876 | data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX; |
| 877 | break; |
| 878 | case 2: |
| 879 | data |= IGP01E1000_PSCR_FORCE_MDI_MDIX; |
| 880 | break; |
| 881 | case 0: |
| 882 | default: |
| 883 | data |= IGP01E1000_PSCR_AUTO_MDIX; |
| 884 | break; |
| 885 | } |
| 886 | ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CTRL, data); |
| 887 | if (ret_val) |
| 888 | return ret_val; |
| 889 | |
| 890 | /* set auto-master slave resolution settings */ |
| 891 | if (hw->mac.autoneg) { |
Bruce Allan | e921eb1 | 2012-11-28 09:28:37 +0000 | [diff] [blame] | 892 | /* when autonegotiation advertisement is only 1000Mbps then we |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 893 | * should disable SmartSpeed and enable Auto MasterSlave |
Bruce Allan | ad68076 | 2008-03-28 09:15:03 -0700 | [diff] [blame] | 894 | * resolution as hardware default. |
| 895 | */ |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 896 | if (phy->autoneg_advertised == ADVERTISE_1000_FULL) { |
| 897 | /* Disable SmartSpeed */ |
| 898 | ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, |
Bruce Allan | ad68076 | 2008-03-28 09:15:03 -0700 | [diff] [blame] | 899 | &data); |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 900 | if (ret_val) |
| 901 | return ret_val; |
| 902 | |
| 903 | data &= ~IGP01E1000_PSCFR_SMART_SPEED; |
| 904 | ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, |
Bruce Allan | ad68076 | 2008-03-28 09:15:03 -0700 | [diff] [blame] | 905 | data); |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 906 | if (ret_val) |
| 907 | return ret_val; |
| 908 | |
| 909 | /* Set auto Master/Slave resolution process */ |
Bruce Allan | c2ade1a | 2013-01-16 08:54:35 +0000 | [diff] [blame] | 910 | ret_val = e1e_rphy(hw, MII_CTRL1000, &data); |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 911 | if (ret_val) |
| 912 | return ret_val; |
| 913 | |
Bruce Allan | c2ade1a | 2013-01-16 08:54:35 +0000 | [diff] [blame] | 914 | data &= ~CTL1000_ENABLE_MASTER; |
| 915 | ret_val = e1e_wphy(hw, MII_CTRL1000, data); |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 916 | if (ret_val) |
| 917 | return ret_val; |
| 918 | } |
| 919 | |
Bruce Allan | 7b9f7e3 | 2012-03-20 03:47:41 +0000 | [diff] [blame] | 920 | ret_val = e1000_set_master_slave_mode(hw); |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 921 | } |
| 922 | |
| 923 | return ret_val; |
| 924 | } |
| 925 | |
| 926 | /** |
| 927 | * e1000_phy_setup_autoneg - Configure PHY for auto-negotiation |
| 928 | * @hw: pointer to the HW structure |
| 929 | * |
| 930 | * Reads the MII auto-neg advertisement register and/or the 1000T control |
| 931 | * register and if the PHY is already setup for auto-negotiation, then |
| 932 | * return successful. Otherwise, setup advertisement and flow control to |
| 933 | * the appropriate values for the wanted auto-negotiation. |
| 934 | **/ |
| 935 | static s32 e1000_phy_setup_autoneg(struct e1000_hw *hw) |
| 936 | { |
| 937 | struct e1000_phy_info *phy = &hw->phy; |
| 938 | s32 ret_val; |
| 939 | u16 mii_autoneg_adv_reg; |
| 940 | u16 mii_1000t_ctrl_reg = 0; |
| 941 | |
| 942 | phy->autoneg_advertised &= phy->autoneg_mask; |
| 943 | |
| 944 | /* Read the MII Auto-Neg Advertisement Register (Address 4). */ |
Bruce Allan | c2ade1a | 2013-01-16 08:54:35 +0000 | [diff] [blame] | 945 | ret_val = e1e_rphy(hw, MII_ADVERTISE, &mii_autoneg_adv_reg); |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 946 | if (ret_val) |
| 947 | return ret_val; |
| 948 | |
| 949 | if (phy->autoneg_mask & ADVERTISE_1000_FULL) { |
| 950 | /* Read the MII 1000Base-T Control Register (Address 9). */ |
Bruce Allan | c2ade1a | 2013-01-16 08:54:35 +0000 | [diff] [blame] | 951 | ret_val = e1e_rphy(hw, MII_CTRL1000, &mii_1000t_ctrl_reg); |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 952 | if (ret_val) |
| 953 | return ret_val; |
| 954 | } |
| 955 | |
Bruce Allan | e921eb1 | 2012-11-28 09:28:37 +0000 | [diff] [blame] | 956 | /* Need to parse both autoneg_advertised and fc and set up |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 957 | * the appropriate PHY registers. First we will parse for |
| 958 | * autoneg_advertised software override. Since we can advertise |
| 959 | * a plethora of combinations, we need to check each bit |
| 960 | * individually. |
| 961 | */ |
| 962 | |
Bruce Allan | e921eb1 | 2012-11-28 09:28:37 +0000 | [diff] [blame] | 963 | /* First we clear all the 10/100 mb speed bits in the Auto-Neg |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 964 | * Advertisement Register (Address 4) and the 1000 mb speed bits in |
| 965 | * the 1000Base-T Control Register (Address 9). |
| 966 | */ |
Bruce Allan | c2ade1a | 2013-01-16 08:54:35 +0000 | [diff] [blame] | 967 | mii_autoneg_adv_reg &= ~(ADVERTISE_100FULL | |
| 968 | ADVERTISE_100HALF | |
| 969 | ADVERTISE_10FULL | ADVERTISE_10HALF); |
| 970 | mii_1000t_ctrl_reg &= ~(ADVERTISE_1000HALF | ADVERTISE_1000FULL); |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 971 | |
Bruce Allan | 3bb99fe | 2009-11-20 23:25:07 +0000 | [diff] [blame] | 972 | e_dbg("autoneg_advertised %x\n", phy->autoneg_advertised); |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 973 | |
| 974 | /* Do we want to advertise 10 Mb Half Duplex? */ |
| 975 | if (phy->autoneg_advertised & ADVERTISE_10_HALF) { |
Bruce Allan | 3bb99fe | 2009-11-20 23:25:07 +0000 | [diff] [blame] | 976 | e_dbg("Advertise 10mb Half duplex\n"); |
Bruce Allan | c2ade1a | 2013-01-16 08:54:35 +0000 | [diff] [blame] | 977 | mii_autoneg_adv_reg |= ADVERTISE_10HALF; |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 978 | } |
| 979 | |
| 980 | /* Do we want to advertise 10 Mb Full Duplex? */ |
| 981 | if (phy->autoneg_advertised & ADVERTISE_10_FULL) { |
Bruce Allan | 3bb99fe | 2009-11-20 23:25:07 +0000 | [diff] [blame] | 982 | e_dbg("Advertise 10mb Full duplex\n"); |
Bruce Allan | c2ade1a | 2013-01-16 08:54:35 +0000 | [diff] [blame] | 983 | mii_autoneg_adv_reg |= ADVERTISE_10FULL; |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 984 | } |
| 985 | |
| 986 | /* Do we want to advertise 100 Mb Half Duplex? */ |
| 987 | if (phy->autoneg_advertised & ADVERTISE_100_HALF) { |
Bruce Allan | 3bb99fe | 2009-11-20 23:25:07 +0000 | [diff] [blame] | 988 | e_dbg("Advertise 100mb Half duplex\n"); |
Bruce Allan | c2ade1a | 2013-01-16 08:54:35 +0000 | [diff] [blame] | 989 | mii_autoneg_adv_reg |= ADVERTISE_100HALF; |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 990 | } |
| 991 | |
| 992 | /* Do we want to advertise 100 Mb Full Duplex? */ |
| 993 | if (phy->autoneg_advertised & ADVERTISE_100_FULL) { |
Bruce Allan | 3bb99fe | 2009-11-20 23:25:07 +0000 | [diff] [blame] | 994 | e_dbg("Advertise 100mb Full duplex\n"); |
Bruce Allan | c2ade1a | 2013-01-16 08:54:35 +0000 | [diff] [blame] | 995 | mii_autoneg_adv_reg |= ADVERTISE_100FULL; |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 996 | } |
| 997 | |
| 998 | /* We do not allow the Phy to advertise 1000 Mb Half Duplex */ |
| 999 | if (phy->autoneg_advertised & ADVERTISE_1000_HALF) |
Bruce Allan | 3bb99fe | 2009-11-20 23:25:07 +0000 | [diff] [blame] | 1000 | e_dbg("Advertise 1000mb Half duplex request denied!\n"); |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 1001 | |
| 1002 | /* Do we want to advertise 1000 Mb Full Duplex? */ |
| 1003 | if (phy->autoneg_advertised & ADVERTISE_1000_FULL) { |
Bruce Allan | 3bb99fe | 2009-11-20 23:25:07 +0000 | [diff] [blame] | 1004 | e_dbg("Advertise 1000mb Full duplex\n"); |
Bruce Allan | c2ade1a | 2013-01-16 08:54:35 +0000 | [diff] [blame] | 1005 | mii_1000t_ctrl_reg |= ADVERTISE_1000FULL; |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 1006 | } |
| 1007 | |
Bruce Allan | e921eb1 | 2012-11-28 09:28:37 +0000 | [diff] [blame] | 1008 | /* Check for a software override of the flow control settings, and |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 1009 | * setup the PHY advertisement registers accordingly. If |
| 1010 | * auto-negotiation is enabled, then software will have to set the |
| 1011 | * "PAUSE" bits to the correct value in the Auto-Negotiation |
Bruce Allan | c2ade1a | 2013-01-16 08:54:35 +0000 | [diff] [blame] | 1012 | * Advertisement Register (MII_ADVERTISE) and re-start auto- |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 1013 | * negotiation. |
| 1014 | * |
| 1015 | * The possible values of the "fc" parameter are: |
| 1016 | * 0: Flow control is completely disabled |
| 1017 | * 1: Rx flow control is enabled (we can receive pause frames |
Bruce Allan | 3d3a167 | 2012-02-23 03:13:18 +0000 | [diff] [blame] | 1018 | * but not send pause frames). |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 1019 | * 2: Tx flow control is enabled (we can send pause frames |
Bruce Allan | 3d3a167 | 2012-02-23 03:13:18 +0000 | [diff] [blame] | 1020 | * but we do not support receiving pause frames). |
Bruce Allan | ad68076 | 2008-03-28 09:15:03 -0700 | [diff] [blame] | 1021 | * 3: Both Rx and Tx flow control (symmetric) are enabled. |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 1022 | * other: No software override. The flow control configuration |
Bruce Allan | 3d3a167 | 2012-02-23 03:13:18 +0000 | [diff] [blame] | 1023 | * in the EEPROM is used. |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 1024 | */ |
Bruce Allan | 5c48ef3e2 | 2008-11-21 16:57:36 -0800 | [diff] [blame] | 1025 | switch (hw->fc.current_mode) { |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 1026 | case e1000_fc_none: |
Bruce Allan | e921eb1 | 2012-11-28 09:28:37 +0000 | [diff] [blame] | 1027 | /* Flow control (Rx & Tx) is completely disabled by a |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 1028 | * software over-ride. |
| 1029 | */ |
Bruce Allan | c2ade1a | 2013-01-16 08:54:35 +0000 | [diff] [blame] | 1030 | mii_autoneg_adv_reg &= |
| 1031 | ~(ADVERTISE_PAUSE_ASYM | ADVERTISE_PAUSE_CAP); |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 1032 | break; |
| 1033 | case e1000_fc_rx_pause: |
Bruce Allan | e921eb1 | 2012-11-28 09:28:37 +0000 | [diff] [blame] | 1034 | /* Rx Flow control is enabled, and Tx Flow control is |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 1035 | * disabled, by a software over-ride. |
Bruce Allan | ad68076 | 2008-03-28 09:15:03 -0700 | [diff] [blame] | 1036 | * |
| 1037 | * Since there really isn't a way to advertise that we are |
| 1038 | * capable of Rx Pause ONLY, we will advertise that we |
| 1039 | * support both symmetric and asymmetric Rx PAUSE. Later |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 1040 | * (in e1000e_config_fc_after_link_up) we will disable the |
| 1041 | * hw's ability to send PAUSE frames. |
| 1042 | */ |
Bruce Allan | c2ade1a | 2013-01-16 08:54:35 +0000 | [diff] [blame] | 1043 | mii_autoneg_adv_reg |= |
| 1044 | (ADVERTISE_PAUSE_ASYM | ADVERTISE_PAUSE_CAP); |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 1045 | break; |
| 1046 | case e1000_fc_tx_pause: |
Bruce Allan | e921eb1 | 2012-11-28 09:28:37 +0000 | [diff] [blame] | 1047 | /* Tx Flow control is enabled, and Rx Flow control is |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 1048 | * disabled, by a software over-ride. |
| 1049 | */ |
Bruce Allan | c2ade1a | 2013-01-16 08:54:35 +0000 | [diff] [blame] | 1050 | mii_autoneg_adv_reg |= ADVERTISE_PAUSE_ASYM; |
| 1051 | mii_autoneg_adv_reg &= ~ADVERTISE_PAUSE_CAP; |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 1052 | break; |
| 1053 | case e1000_fc_full: |
Bruce Allan | e921eb1 | 2012-11-28 09:28:37 +0000 | [diff] [blame] | 1054 | /* Flow control (both Rx and Tx) is enabled by a software |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 1055 | * over-ride. |
| 1056 | */ |
Bruce Allan | c2ade1a | 2013-01-16 08:54:35 +0000 | [diff] [blame] | 1057 | mii_autoneg_adv_reg |= |
| 1058 | (ADVERTISE_PAUSE_ASYM | ADVERTISE_PAUSE_CAP); |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 1059 | break; |
| 1060 | default: |
Bruce Allan | 3bb99fe | 2009-11-20 23:25:07 +0000 | [diff] [blame] | 1061 | e_dbg("Flow control param set incorrectly\n"); |
Bruce Allan | 7eb61d8 | 2012-02-08 02:55:03 +0000 | [diff] [blame] | 1062 | return -E1000_ERR_CONFIG; |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 1063 | } |
| 1064 | |
Bruce Allan | c2ade1a | 2013-01-16 08:54:35 +0000 | [diff] [blame] | 1065 | ret_val = e1e_wphy(hw, MII_ADVERTISE, mii_autoneg_adv_reg); |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 1066 | if (ret_val) |
| 1067 | return ret_val; |
| 1068 | |
Bruce Allan | 3bb99fe | 2009-11-20 23:25:07 +0000 | [diff] [blame] | 1069 | e_dbg("Auto-Neg Advertising %x\n", mii_autoneg_adv_reg); |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 1070 | |
Bruce Allan | b1cdfea | 2010-12-11 05:53:47 +0000 | [diff] [blame] | 1071 | if (phy->autoneg_mask & ADVERTISE_1000_FULL) |
Bruce Allan | c2ade1a | 2013-01-16 08:54:35 +0000 | [diff] [blame] | 1072 | ret_val = e1e_wphy(hw, MII_CTRL1000, mii_1000t_ctrl_reg); |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 1073 | |
| 1074 | return ret_val; |
| 1075 | } |
| 1076 | |
| 1077 | /** |
| 1078 | * e1000_copper_link_autoneg - Setup/Enable autoneg for copper link |
| 1079 | * @hw: pointer to the HW structure |
| 1080 | * |
| 1081 | * Performs initial bounds checking on autoneg advertisement parameter, then |
| 1082 | * configure to advertise the full capability. Setup the PHY to autoneg |
| 1083 | * and restart the negotiation process between the link partner. If |
Bruce Allan | ad68076 | 2008-03-28 09:15:03 -0700 | [diff] [blame] | 1084 | * autoneg_wait_to_complete, then wait for autoneg to complete before exiting. |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 1085 | **/ |
| 1086 | static s32 e1000_copper_link_autoneg(struct e1000_hw *hw) |
| 1087 | { |
| 1088 | struct e1000_phy_info *phy = &hw->phy; |
| 1089 | s32 ret_val; |
| 1090 | u16 phy_ctrl; |
| 1091 | |
Bruce Allan | e921eb1 | 2012-11-28 09:28:37 +0000 | [diff] [blame] | 1092 | /* Perform some bounds checking on the autoneg advertisement |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 1093 | * parameter. |
| 1094 | */ |
| 1095 | phy->autoneg_advertised &= phy->autoneg_mask; |
| 1096 | |
Bruce Allan | e921eb1 | 2012-11-28 09:28:37 +0000 | [diff] [blame] | 1097 | /* If autoneg_advertised is zero, we assume it was not defaulted |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 1098 | * by the calling code so we set to advertise full capability. |
| 1099 | */ |
Bruce Allan | 04499ec | 2012-04-13 00:08:31 +0000 | [diff] [blame] | 1100 | if (!phy->autoneg_advertised) |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 1101 | phy->autoneg_advertised = phy->autoneg_mask; |
| 1102 | |
Bruce Allan | 3bb99fe | 2009-11-20 23:25:07 +0000 | [diff] [blame] | 1103 | e_dbg("Reconfiguring auto-neg advertisement params\n"); |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 1104 | ret_val = e1000_phy_setup_autoneg(hw); |
| 1105 | if (ret_val) { |
Bruce Allan | 3bb99fe | 2009-11-20 23:25:07 +0000 | [diff] [blame] | 1106 | e_dbg("Error Setting up Auto-Negotiation\n"); |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 1107 | return ret_val; |
| 1108 | } |
Bruce Allan | 3bb99fe | 2009-11-20 23:25:07 +0000 | [diff] [blame] | 1109 | e_dbg("Restarting Auto-Neg\n"); |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 1110 | |
Bruce Allan | e921eb1 | 2012-11-28 09:28:37 +0000 | [diff] [blame] | 1111 | /* Restart auto-negotiation by setting the Auto Neg Enable bit and |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 1112 | * the Auto Neg Restart bit in the PHY control register. |
| 1113 | */ |
Bruce Allan | c2ade1a | 2013-01-16 08:54:35 +0000 | [diff] [blame] | 1114 | ret_val = e1e_rphy(hw, MII_BMCR, &phy_ctrl); |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 1115 | if (ret_val) |
| 1116 | return ret_val; |
| 1117 | |
Bruce Allan | c2ade1a | 2013-01-16 08:54:35 +0000 | [diff] [blame] | 1118 | phy_ctrl |= (BMCR_ANENABLE | BMCR_ANRESTART); |
| 1119 | ret_val = e1e_wphy(hw, MII_BMCR, phy_ctrl); |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 1120 | if (ret_val) |
| 1121 | return ret_val; |
| 1122 | |
Bruce Allan | e921eb1 | 2012-11-28 09:28:37 +0000 | [diff] [blame] | 1123 | /* Does the user want to wait for Auto-Neg to complete here, or |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 1124 | * check at a later time (for example, callback routine). |
| 1125 | */ |
Jeff Kirsher | 318a94d | 2008-03-28 09:15:16 -0700 | [diff] [blame] | 1126 | if (phy->autoneg_wait_to_complete) { |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 1127 | ret_val = e1000_wait_autoneg(hw); |
| 1128 | if (ret_val) { |
Bruce Allan | 434f139 | 2011-12-16 00:46:54 +0000 | [diff] [blame] | 1129 | e_dbg("Error while waiting for autoneg to complete\n"); |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 1130 | return ret_val; |
| 1131 | } |
| 1132 | } |
| 1133 | |
Bruce Allan | f92518d | 2012-02-01 11:16:42 +0000 | [diff] [blame] | 1134 | hw->mac.get_link_status = true; |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 1135 | |
| 1136 | return ret_val; |
| 1137 | } |
| 1138 | |
| 1139 | /** |
| 1140 | * e1000e_setup_copper_link - Configure copper link settings |
| 1141 | * @hw: pointer to the HW structure |
| 1142 | * |
| 1143 | * Calls the appropriate function to configure the link for auto-neg or forced |
| 1144 | * speed and duplex. Then we check for link, once link is established calls |
| 1145 | * to configure collision distance and flow control are called. If link is |
| 1146 | * not established, we return -E1000_ERR_PHY (-2). |
| 1147 | **/ |
| 1148 | s32 e1000e_setup_copper_link(struct e1000_hw *hw) |
| 1149 | { |
| 1150 | s32 ret_val; |
| 1151 | bool link; |
| 1152 | |
| 1153 | if (hw->mac.autoneg) { |
Bruce Allan | e921eb1 | 2012-11-28 09:28:37 +0000 | [diff] [blame] | 1154 | /* Setup autoneg and flow control advertisement and perform |
Bruce Allan | ad68076 | 2008-03-28 09:15:03 -0700 | [diff] [blame] | 1155 | * autonegotiation. |
| 1156 | */ |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 1157 | ret_val = e1000_copper_link_autoneg(hw); |
| 1158 | if (ret_val) |
| 1159 | return ret_val; |
| 1160 | } else { |
Bruce Allan | e921eb1 | 2012-11-28 09:28:37 +0000 | [diff] [blame] | 1161 | /* PHY will be set to 10H, 10F, 100H or 100F |
Bruce Allan | ad68076 | 2008-03-28 09:15:03 -0700 | [diff] [blame] | 1162 | * depending on user settings. |
| 1163 | */ |
Bruce Allan | 3bb99fe | 2009-11-20 23:25:07 +0000 | [diff] [blame] | 1164 | e_dbg("Forcing Speed and Duplex\n"); |
Bruce Allan | c2c6629 | 2013-01-05 08:06:08 +0000 | [diff] [blame] | 1165 | ret_val = hw->phy.ops.force_speed_duplex(hw); |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 1166 | if (ret_val) { |
Bruce Allan | 3bb99fe | 2009-11-20 23:25:07 +0000 | [diff] [blame] | 1167 | e_dbg("Error Forcing Speed and Duplex\n"); |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 1168 | return ret_val; |
| 1169 | } |
| 1170 | } |
| 1171 | |
Bruce Allan | e921eb1 | 2012-11-28 09:28:37 +0000 | [diff] [blame] | 1172 | /* Check link status. Wait up to 100 microseconds for link to become |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 1173 | * valid. |
| 1174 | */ |
Bruce Allan | 3d3a167 | 2012-02-23 03:13:18 +0000 | [diff] [blame] | 1175 | ret_val = e1000e_phy_has_link_generic(hw, COPPER_LINK_UP_LIMIT, 10, |
| 1176 | &link); |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 1177 | if (ret_val) |
| 1178 | return ret_val; |
| 1179 | |
| 1180 | if (link) { |
Bruce Allan | 3bb99fe | 2009-11-20 23:25:07 +0000 | [diff] [blame] | 1181 | e_dbg("Valid link established!!!\n"); |
Bruce Allan | 57cde76 | 2012-02-22 09:02:58 +0000 | [diff] [blame] | 1182 | hw->mac.ops.config_collision_dist(hw); |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 1183 | ret_val = e1000e_config_fc_after_link_up(hw); |
| 1184 | } else { |
Bruce Allan | 3bb99fe | 2009-11-20 23:25:07 +0000 | [diff] [blame] | 1185 | e_dbg("Unable to establish link!!!\n"); |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 1186 | } |
| 1187 | |
| 1188 | return ret_val; |
| 1189 | } |
| 1190 | |
| 1191 | /** |
| 1192 | * e1000e_phy_force_speed_duplex_igp - Force speed/duplex for igp PHY |
| 1193 | * @hw: pointer to the HW structure |
| 1194 | * |
| 1195 | * Calls the PHY setup function to force speed and duplex. Clears the |
| 1196 | * auto-crossover to force MDI manually. Waits for link and returns |
| 1197 | * successful if link up is successful, else -E1000_ERR_PHY (-2). |
| 1198 | **/ |
| 1199 | s32 e1000e_phy_force_speed_duplex_igp(struct e1000_hw *hw) |
| 1200 | { |
| 1201 | struct e1000_phy_info *phy = &hw->phy; |
| 1202 | s32 ret_val; |
| 1203 | u16 phy_data; |
| 1204 | bool link; |
| 1205 | |
Bruce Allan | c2ade1a | 2013-01-16 08:54:35 +0000 | [diff] [blame] | 1206 | ret_val = e1e_rphy(hw, MII_BMCR, &phy_data); |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 1207 | if (ret_val) |
| 1208 | return ret_val; |
| 1209 | |
| 1210 | e1000e_phy_force_speed_duplex_setup(hw, &phy_data); |
| 1211 | |
Bruce Allan | c2ade1a | 2013-01-16 08:54:35 +0000 | [diff] [blame] | 1212 | ret_val = e1e_wphy(hw, MII_BMCR, phy_data); |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 1213 | if (ret_val) |
| 1214 | return ret_val; |
| 1215 | |
Bruce Allan | e921eb1 | 2012-11-28 09:28:37 +0000 | [diff] [blame] | 1216 | /* Clear Auto-Crossover to force MDI manually. IGP requires MDI |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 1217 | * forced whenever speed and duplex are forced. |
| 1218 | */ |
| 1219 | ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data); |
| 1220 | if (ret_val) |
| 1221 | return ret_val; |
| 1222 | |
| 1223 | phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX; |
| 1224 | phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX; |
| 1225 | |
| 1226 | ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CTRL, phy_data); |
| 1227 | if (ret_val) |
| 1228 | return ret_val; |
| 1229 | |
Bruce Allan | 3bb99fe | 2009-11-20 23:25:07 +0000 | [diff] [blame] | 1230 | e_dbg("IGP PSCR: %X\n", phy_data); |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 1231 | |
| 1232 | udelay(1); |
| 1233 | |
Jeff Kirsher | 318a94d | 2008-03-28 09:15:16 -0700 | [diff] [blame] | 1234 | if (phy->autoneg_wait_to_complete) { |
Bruce Allan | 3bb99fe | 2009-11-20 23:25:07 +0000 | [diff] [blame] | 1235 | e_dbg("Waiting for forced speed/duplex link on IGP phy.\n"); |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 1236 | |
Bruce Allan | 3d3a167 | 2012-02-23 03:13:18 +0000 | [diff] [blame] | 1237 | ret_val = e1000e_phy_has_link_generic(hw, PHY_FORCE_LIMIT, |
| 1238 | 100000, &link); |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 1239 | if (ret_val) |
| 1240 | return ret_val; |
| 1241 | |
| 1242 | if (!link) |
Bruce Allan | 3bb99fe | 2009-11-20 23:25:07 +0000 | [diff] [blame] | 1243 | e_dbg("Link taking longer than expected.\n"); |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 1244 | |
| 1245 | /* Try once more */ |
Bruce Allan | 3d3a167 | 2012-02-23 03:13:18 +0000 | [diff] [blame] | 1246 | ret_val = e1000e_phy_has_link_generic(hw, PHY_FORCE_LIMIT, |
| 1247 | 100000, &link); |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 1248 | } |
| 1249 | |
| 1250 | return ret_val; |
| 1251 | } |
| 1252 | |
| 1253 | /** |
| 1254 | * e1000e_phy_force_speed_duplex_m88 - Force speed/duplex for m88 PHY |
| 1255 | * @hw: pointer to the HW structure |
| 1256 | * |
| 1257 | * Calls the PHY setup function to force speed and duplex. Clears the |
| 1258 | * auto-crossover to force MDI manually. Resets the PHY to commit the |
| 1259 | * changes. If time expires while waiting for link up, we reset the DSP. |
Bruce Allan | ad68076 | 2008-03-28 09:15:03 -0700 | [diff] [blame] | 1260 | * After reset, TX_CLK and CRS on Tx must be set. Return successful upon |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 1261 | * successful completion, else return corresponding error code. |
| 1262 | **/ |
| 1263 | s32 e1000e_phy_force_speed_duplex_m88(struct e1000_hw *hw) |
| 1264 | { |
| 1265 | struct e1000_phy_info *phy = &hw->phy; |
| 1266 | s32 ret_val; |
| 1267 | u16 phy_data; |
| 1268 | bool link; |
| 1269 | |
Bruce Allan | e921eb1 | 2012-11-28 09:28:37 +0000 | [diff] [blame] | 1270 | /* Clear Auto-Crossover to force MDI manually. M88E1000 requires MDI |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 1271 | * forced whenever speed and duplex are forced. |
| 1272 | */ |
| 1273 | ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); |
| 1274 | if (ret_val) |
| 1275 | return ret_val; |
| 1276 | |
| 1277 | phy_data &= ~M88E1000_PSCR_AUTO_X_MODE; |
| 1278 | ret_val = e1e_wphy(hw, M88E1000_PHY_SPEC_CTRL, phy_data); |
| 1279 | if (ret_val) |
| 1280 | return ret_val; |
| 1281 | |
Bruce Allan | 3bb99fe | 2009-11-20 23:25:07 +0000 | [diff] [blame] | 1282 | e_dbg("M88E1000 PSCR: %X\n", phy_data); |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 1283 | |
Bruce Allan | c2ade1a | 2013-01-16 08:54:35 +0000 | [diff] [blame] | 1284 | ret_val = e1e_rphy(hw, MII_BMCR, &phy_data); |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 1285 | if (ret_val) |
| 1286 | return ret_val; |
| 1287 | |
| 1288 | e1000e_phy_force_speed_duplex_setup(hw, &phy_data); |
| 1289 | |
Bruce Allan | c2ade1a | 2013-01-16 08:54:35 +0000 | [diff] [blame] | 1290 | ret_val = e1e_wphy(hw, MII_BMCR, phy_data); |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 1291 | if (ret_val) |
| 1292 | return ret_val; |
| 1293 | |
Bruce Allan | 5aa49c8 | 2008-11-21 16:49:53 -0800 | [diff] [blame] | 1294 | /* Reset the phy to commit changes. */ |
Bruce Allan | 6b598e1 | 2013-01-23 06:50:05 +0000 | [diff] [blame] | 1295 | if (hw->phy.ops.commit) { |
| 1296 | ret_val = hw->phy.ops.commit(hw); |
| 1297 | if (ret_val) |
| 1298 | return ret_val; |
| 1299 | } |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 1300 | |
Jeff Kirsher | 318a94d | 2008-03-28 09:15:16 -0700 | [diff] [blame] | 1301 | if (phy->autoneg_wait_to_complete) { |
Bruce Allan | 3bb99fe | 2009-11-20 23:25:07 +0000 | [diff] [blame] | 1302 | e_dbg("Waiting for forced speed/duplex link on M88 phy.\n"); |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 1303 | |
| 1304 | ret_val = e1000e_phy_has_link_generic(hw, PHY_FORCE_LIMIT, |
Bruce Allan | 17e813e | 2013-02-20 04:06:01 +0000 | [diff] [blame] | 1305 | 100000, &link); |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 1306 | if (ret_val) |
| 1307 | return ret_val; |
| 1308 | |
| 1309 | if (!link) { |
Bruce Allan | 0be8401 | 2009-12-02 17:03:18 +0000 | [diff] [blame] | 1310 | if (hw->phy.type != e1000_phy_m88) { |
| 1311 | e_dbg("Link taking longer than expected.\n"); |
| 1312 | } else { |
Bruce Allan | e921eb1 | 2012-11-28 09:28:37 +0000 | [diff] [blame] | 1313 | /* We didn't get link. |
Bruce Allan | 0be8401 | 2009-12-02 17:03:18 +0000 | [diff] [blame] | 1314 | * Reset the DSP and cross our fingers. |
| 1315 | */ |
Bruce Allan | 482fed8 | 2011-01-06 14:29:49 +0000 | [diff] [blame] | 1316 | ret_val = e1e_wphy(hw, M88E1000_PHY_PAGE_SELECT, |
| 1317 | 0x001d); |
Bruce Allan | 0be8401 | 2009-12-02 17:03:18 +0000 | [diff] [blame] | 1318 | if (ret_val) |
| 1319 | return ret_val; |
| 1320 | ret_val = e1000e_phy_reset_dsp(hw); |
| 1321 | if (ret_val) |
| 1322 | return ret_val; |
| 1323 | } |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 1324 | } |
| 1325 | |
| 1326 | /* Try once more */ |
| 1327 | ret_val = e1000e_phy_has_link_generic(hw, PHY_FORCE_LIMIT, |
Bruce Allan | 17e813e | 2013-02-20 04:06:01 +0000 | [diff] [blame] | 1328 | 100000, &link); |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 1329 | if (ret_val) |
| 1330 | return ret_val; |
| 1331 | } |
| 1332 | |
Bruce Allan | 0be8401 | 2009-12-02 17:03:18 +0000 | [diff] [blame] | 1333 | if (hw->phy.type != e1000_phy_m88) |
| 1334 | return 0; |
| 1335 | |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 1336 | ret_val = e1e_rphy(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data); |
| 1337 | if (ret_val) |
| 1338 | return ret_val; |
| 1339 | |
Bruce Allan | e921eb1 | 2012-11-28 09:28:37 +0000 | [diff] [blame] | 1340 | /* Resetting the phy means we need to re-force TX_CLK in the |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 1341 | * Extended PHY Specific Control Register to 25MHz clock from |
| 1342 | * the reset value of 2.5MHz. |
| 1343 | */ |
| 1344 | phy_data |= M88E1000_EPSCR_TX_CLK_25; |
| 1345 | ret_val = e1e_wphy(hw, M88E1000_EXT_PHY_SPEC_CTRL, phy_data); |
| 1346 | if (ret_val) |
| 1347 | return ret_val; |
| 1348 | |
Bruce Allan | e921eb1 | 2012-11-28 09:28:37 +0000 | [diff] [blame] | 1349 | /* In addition, we must re-enable CRS on Tx for both half and full |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 1350 | * duplex. |
| 1351 | */ |
| 1352 | ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); |
| 1353 | if (ret_val) |
| 1354 | return ret_val; |
| 1355 | |
| 1356 | phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX; |
| 1357 | ret_val = e1e_wphy(hw, M88E1000_PHY_SPEC_CTRL, phy_data); |
| 1358 | |
| 1359 | return ret_val; |
| 1360 | } |
| 1361 | |
| 1362 | /** |
Bruce Allan | 0be8401 | 2009-12-02 17:03:18 +0000 | [diff] [blame] | 1363 | * e1000_phy_force_speed_duplex_ife - Force PHY speed & duplex |
| 1364 | * @hw: pointer to the HW structure |
| 1365 | * |
| 1366 | * Forces the speed and duplex settings of the PHY. |
| 1367 | * This is a function pointer entry point only called by |
| 1368 | * PHY setup routines. |
| 1369 | **/ |
| 1370 | s32 e1000_phy_force_speed_duplex_ife(struct e1000_hw *hw) |
| 1371 | { |
| 1372 | struct e1000_phy_info *phy = &hw->phy; |
| 1373 | s32 ret_val; |
| 1374 | u16 data; |
| 1375 | bool link; |
| 1376 | |
Bruce Allan | c2ade1a | 2013-01-16 08:54:35 +0000 | [diff] [blame] | 1377 | ret_val = e1e_rphy(hw, MII_BMCR, &data); |
Bruce Allan | 0be8401 | 2009-12-02 17:03:18 +0000 | [diff] [blame] | 1378 | if (ret_val) |
Bruce Allan | 5015e53 | 2012-02-08 02:55:56 +0000 | [diff] [blame] | 1379 | return ret_val; |
Bruce Allan | 0be8401 | 2009-12-02 17:03:18 +0000 | [diff] [blame] | 1380 | |
| 1381 | e1000e_phy_force_speed_duplex_setup(hw, &data); |
| 1382 | |
Bruce Allan | c2ade1a | 2013-01-16 08:54:35 +0000 | [diff] [blame] | 1383 | ret_val = e1e_wphy(hw, MII_BMCR, data); |
Bruce Allan | 0be8401 | 2009-12-02 17:03:18 +0000 | [diff] [blame] | 1384 | if (ret_val) |
Bruce Allan | 5015e53 | 2012-02-08 02:55:56 +0000 | [diff] [blame] | 1385 | return ret_val; |
Bruce Allan | 0be8401 | 2009-12-02 17:03:18 +0000 | [diff] [blame] | 1386 | |
| 1387 | /* Disable MDI-X support for 10/100 */ |
| 1388 | ret_val = e1e_rphy(hw, IFE_PHY_MDIX_CONTROL, &data); |
| 1389 | if (ret_val) |
Bruce Allan | 5015e53 | 2012-02-08 02:55:56 +0000 | [diff] [blame] | 1390 | return ret_val; |
Bruce Allan | 0be8401 | 2009-12-02 17:03:18 +0000 | [diff] [blame] | 1391 | |
| 1392 | data &= ~IFE_PMC_AUTO_MDIX; |
| 1393 | data &= ~IFE_PMC_FORCE_MDIX; |
| 1394 | |
| 1395 | ret_val = e1e_wphy(hw, IFE_PHY_MDIX_CONTROL, data); |
| 1396 | if (ret_val) |
Bruce Allan | 5015e53 | 2012-02-08 02:55:56 +0000 | [diff] [blame] | 1397 | return ret_val; |
Bruce Allan | 0be8401 | 2009-12-02 17:03:18 +0000 | [diff] [blame] | 1398 | |
| 1399 | e_dbg("IFE PMC: %X\n", data); |
| 1400 | |
| 1401 | udelay(1); |
| 1402 | |
| 1403 | if (phy->autoneg_wait_to_complete) { |
| 1404 | e_dbg("Waiting for forced speed/duplex link on IFE phy.\n"); |
| 1405 | |
Bruce Allan | 3d3a167 | 2012-02-23 03:13:18 +0000 | [diff] [blame] | 1406 | ret_val = e1000e_phy_has_link_generic(hw, PHY_FORCE_LIMIT, |
| 1407 | 100000, &link); |
Bruce Allan | 0be8401 | 2009-12-02 17:03:18 +0000 | [diff] [blame] | 1408 | if (ret_val) |
Bruce Allan | 5015e53 | 2012-02-08 02:55:56 +0000 | [diff] [blame] | 1409 | return ret_val; |
Bruce Allan | 0be8401 | 2009-12-02 17:03:18 +0000 | [diff] [blame] | 1410 | |
| 1411 | if (!link) |
| 1412 | e_dbg("Link taking longer than expected.\n"); |
| 1413 | |
| 1414 | /* Try once more */ |
Bruce Allan | 3d3a167 | 2012-02-23 03:13:18 +0000 | [diff] [blame] | 1415 | ret_val = e1000e_phy_has_link_generic(hw, PHY_FORCE_LIMIT, |
| 1416 | 100000, &link); |
Bruce Allan | 0be8401 | 2009-12-02 17:03:18 +0000 | [diff] [blame] | 1417 | if (ret_val) |
Bruce Allan | 5015e53 | 2012-02-08 02:55:56 +0000 | [diff] [blame] | 1418 | return ret_val; |
Bruce Allan | 0be8401 | 2009-12-02 17:03:18 +0000 | [diff] [blame] | 1419 | } |
| 1420 | |
Bruce Allan | 5015e53 | 2012-02-08 02:55:56 +0000 | [diff] [blame] | 1421 | return 0; |
Bruce Allan | 0be8401 | 2009-12-02 17:03:18 +0000 | [diff] [blame] | 1422 | } |
| 1423 | |
| 1424 | /** |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 1425 | * e1000e_phy_force_speed_duplex_setup - Configure forced PHY speed/duplex |
| 1426 | * @hw: pointer to the HW structure |
Bruce Allan | c2ade1a | 2013-01-16 08:54:35 +0000 | [diff] [blame] | 1427 | * @phy_ctrl: pointer to current value of MII_BMCR |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 1428 | * |
| 1429 | * Forces speed and duplex on the PHY by doing the following: disable flow |
| 1430 | * control, force speed/duplex on the MAC, disable auto speed detection, |
| 1431 | * disable auto-negotiation, configure duplex, configure speed, configure |
| 1432 | * the collision distance, write configuration to CTRL register. The |
Bruce Allan | c2ade1a | 2013-01-16 08:54:35 +0000 | [diff] [blame] | 1433 | * caller must write to the MII_BMCR register for these settings to |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 1434 | * take affect. |
| 1435 | **/ |
| 1436 | void e1000e_phy_force_speed_duplex_setup(struct e1000_hw *hw, u16 *phy_ctrl) |
| 1437 | { |
| 1438 | struct e1000_mac_info *mac = &hw->mac; |
| 1439 | u32 ctrl; |
| 1440 | |
| 1441 | /* Turn off flow control when forcing speed/duplex */ |
Bruce Allan | 5c48ef3e2 | 2008-11-21 16:57:36 -0800 | [diff] [blame] | 1442 | hw->fc.current_mode = e1000_fc_none; |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 1443 | |
| 1444 | /* Force speed/duplex on the mac */ |
| 1445 | ctrl = er32(CTRL); |
| 1446 | ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); |
| 1447 | ctrl &= ~E1000_CTRL_SPD_SEL; |
| 1448 | |
| 1449 | /* Disable Auto Speed Detection */ |
| 1450 | ctrl &= ~E1000_CTRL_ASDE; |
| 1451 | |
| 1452 | /* Disable autoneg on the phy */ |
Bruce Allan | c2ade1a | 2013-01-16 08:54:35 +0000 | [diff] [blame] | 1453 | *phy_ctrl &= ~BMCR_ANENABLE; |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 1454 | |
| 1455 | /* Forcing Full or Half Duplex? */ |
| 1456 | if (mac->forced_speed_duplex & E1000_ALL_HALF_DUPLEX) { |
| 1457 | ctrl &= ~E1000_CTRL_FD; |
Bruce Allan | c2ade1a | 2013-01-16 08:54:35 +0000 | [diff] [blame] | 1458 | *phy_ctrl &= ~BMCR_FULLDPLX; |
Bruce Allan | 3bb99fe | 2009-11-20 23:25:07 +0000 | [diff] [blame] | 1459 | e_dbg("Half Duplex\n"); |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 1460 | } else { |
| 1461 | ctrl |= E1000_CTRL_FD; |
Bruce Allan | c2ade1a | 2013-01-16 08:54:35 +0000 | [diff] [blame] | 1462 | *phy_ctrl |= BMCR_FULLDPLX; |
Bruce Allan | 3bb99fe | 2009-11-20 23:25:07 +0000 | [diff] [blame] | 1463 | e_dbg("Full Duplex\n"); |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 1464 | } |
| 1465 | |
| 1466 | /* Forcing 10mb or 100mb? */ |
| 1467 | if (mac->forced_speed_duplex & E1000_ALL_100_SPEED) { |
| 1468 | ctrl |= E1000_CTRL_SPD_100; |
Bruce Allan | c2ade1a | 2013-01-16 08:54:35 +0000 | [diff] [blame] | 1469 | *phy_ctrl |= BMCR_SPEED100; |
| 1470 | *phy_ctrl &= ~BMCR_SPEED1000; |
Bruce Allan | 3bb99fe | 2009-11-20 23:25:07 +0000 | [diff] [blame] | 1471 | e_dbg("Forcing 100mb\n"); |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 1472 | } else { |
| 1473 | ctrl &= ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100); |
Bruce Allan | c2ade1a | 2013-01-16 08:54:35 +0000 | [diff] [blame] | 1474 | *phy_ctrl &= ~(BMCR_SPEED1000 | BMCR_SPEED100); |
Bruce Allan | 3bb99fe | 2009-11-20 23:25:07 +0000 | [diff] [blame] | 1475 | e_dbg("Forcing 10mb\n"); |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 1476 | } |
| 1477 | |
Bruce Allan | 57cde76 | 2012-02-22 09:02:58 +0000 | [diff] [blame] | 1478 | hw->mac.ops.config_collision_dist(hw); |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 1479 | |
| 1480 | ew32(CTRL, ctrl); |
| 1481 | } |
| 1482 | |
| 1483 | /** |
| 1484 | * e1000e_set_d3_lplu_state - Sets low power link up state for D3 |
| 1485 | * @hw: pointer to the HW structure |
| 1486 | * @active: boolean used to enable/disable lplu |
| 1487 | * |
| 1488 | * Success returns 0, Failure returns 1 |
| 1489 | * |
| 1490 | * The low power link up (lplu) state is set to the power management level D3 |
| 1491 | * and SmartSpeed is disabled when active is true, else clear lplu for D3 |
| 1492 | * and enable Smartspeed. LPLU and Smartspeed are mutually exclusive. LPLU |
| 1493 | * is used during Dx states where the power conservation is most important. |
| 1494 | * During driver activity, SmartSpeed should be enabled so performance is |
| 1495 | * maintained. |
| 1496 | **/ |
| 1497 | s32 e1000e_set_d3_lplu_state(struct e1000_hw *hw, bool active) |
| 1498 | { |
| 1499 | struct e1000_phy_info *phy = &hw->phy; |
| 1500 | s32 ret_val; |
| 1501 | u16 data; |
| 1502 | |
| 1503 | ret_val = e1e_rphy(hw, IGP02E1000_PHY_POWER_MGMT, &data); |
| 1504 | if (ret_val) |
| 1505 | return ret_val; |
| 1506 | |
| 1507 | if (!active) { |
| 1508 | data &= ~IGP02E1000_PM_D3_LPLU; |
David Graham | 2d9498f | 2008-04-23 11:09:14 -0700 | [diff] [blame] | 1509 | ret_val = e1e_wphy(hw, IGP02E1000_PHY_POWER_MGMT, data); |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 1510 | if (ret_val) |
| 1511 | return ret_val; |
Bruce Allan | e921eb1 | 2012-11-28 09:28:37 +0000 | [diff] [blame] | 1512 | /* LPLU and SmartSpeed are mutually exclusive. LPLU is used |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 1513 | * during Dx states where the power conservation is most |
| 1514 | * important. During driver activity we should enable |
Bruce Allan | ad68076 | 2008-03-28 09:15:03 -0700 | [diff] [blame] | 1515 | * SmartSpeed, so performance is maintained. |
| 1516 | */ |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 1517 | if (phy->smart_speed == e1000_smart_speed_on) { |
| 1518 | ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, |
Bruce Allan | ad68076 | 2008-03-28 09:15:03 -0700 | [diff] [blame] | 1519 | &data); |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 1520 | if (ret_val) |
| 1521 | return ret_val; |
| 1522 | |
| 1523 | data |= IGP01E1000_PSCFR_SMART_SPEED; |
| 1524 | ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, |
Bruce Allan | ad68076 | 2008-03-28 09:15:03 -0700 | [diff] [blame] | 1525 | data); |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 1526 | if (ret_val) |
| 1527 | return ret_val; |
| 1528 | } else if (phy->smart_speed == e1000_smart_speed_off) { |
| 1529 | ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, |
Bruce Allan | ad68076 | 2008-03-28 09:15:03 -0700 | [diff] [blame] | 1530 | &data); |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 1531 | if (ret_val) |
| 1532 | return ret_val; |
| 1533 | |
| 1534 | data &= ~IGP01E1000_PSCFR_SMART_SPEED; |
| 1535 | ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, |
Bruce Allan | ad68076 | 2008-03-28 09:15:03 -0700 | [diff] [blame] | 1536 | data); |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 1537 | if (ret_val) |
| 1538 | return ret_val; |
| 1539 | } |
| 1540 | } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) || |
| 1541 | (phy->autoneg_advertised == E1000_ALL_NOT_GIG) || |
| 1542 | (phy->autoneg_advertised == E1000_ALL_10_SPEED)) { |
| 1543 | data |= IGP02E1000_PM_D3_LPLU; |
| 1544 | ret_val = e1e_wphy(hw, IGP02E1000_PHY_POWER_MGMT, data); |
| 1545 | if (ret_val) |
| 1546 | return ret_val; |
| 1547 | |
| 1548 | /* When LPLU is enabled, we should disable SmartSpeed */ |
| 1549 | ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, &data); |
| 1550 | if (ret_val) |
| 1551 | return ret_val; |
| 1552 | |
| 1553 | data &= ~IGP01E1000_PSCFR_SMART_SPEED; |
| 1554 | ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, data); |
| 1555 | } |
| 1556 | |
| 1557 | return ret_val; |
| 1558 | } |
| 1559 | |
| 1560 | /** |
Auke Kok | 489815c | 2008-02-21 15:11:07 -0800 | [diff] [blame] | 1561 | * e1000e_check_downshift - Checks whether a downshift in speed occurred |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 1562 | * @hw: pointer to the HW structure |
| 1563 | * |
| 1564 | * Success returns 0, Failure returns 1 |
| 1565 | * |
| 1566 | * A downshift is detected by querying the PHY link health. |
| 1567 | **/ |
| 1568 | s32 e1000e_check_downshift(struct e1000_hw *hw) |
| 1569 | { |
| 1570 | struct e1000_phy_info *phy = &hw->phy; |
| 1571 | s32 ret_val; |
| 1572 | u16 phy_data, offset, mask; |
| 1573 | |
| 1574 | switch (phy->type) { |
| 1575 | case e1000_phy_m88: |
| 1576 | case e1000_phy_gg82563: |
Bruce Allan | 07f025e | 2009-12-01 15:53:48 +0000 | [diff] [blame] | 1577 | case e1000_phy_bm: |
Bruce Allan | a4f58f5 | 2009-06-02 11:29:18 +0000 | [diff] [blame] | 1578 | case e1000_phy_82578: |
Bruce Allan | e80bd1d | 2013-05-01 01:19:46 +0000 | [diff] [blame] | 1579 | offset = M88E1000_PHY_SPEC_STATUS; |
| 1580 | mask = M88E1000_PSSR_DOWNSHIFT; |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 1581 | break; |
| 1582 | case e1000_phy_igp_2: |
| 1583 | case e1000_phy_igp_3: |
Bruce Allan | e80bd1d | 2013-05-01 01:19:46 +0000 | [diff] [blame] | 1584 | offset = IGP01E1000_PHY_LINK_HEALTH; |
| 1585 | mask = IGP01E1000_PLHR_SS_DOWNGRADE; |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 1586 | break; |
| 1587 | default: |
| 1588 | /* speed downshift not supported */ |
Bruce Allan | 564ea9b | 2009-11-20 23:26:44 +0000 | [diff] [blame] | 1589 | phy->speed_downgraded = false; |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 1590 | return 0; |
| 1591 | } |
| 1592 | |
| 1593 | ret_val = e1e_rphy(hw, offset, &phy_data); |
| 1594 | |
| 1595 | if (!ret_val) |
Bruce Allan | 04499ec | 2012-04-13 00:08:31 +0000 | [diff] [blame] | 1596 | phy->speed_downgraded = !!(phy_data & mask); |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 1597 | |
| 1598 | return ret_val; |
| 1599 | } |
| 1600 | |
| 1601 | /** |
| 1602 | * e1000_check_polarity_m88 - Checks the polarity. |
| 1603 | * @hw: pointer to the HW structure |
| 1604 | * |
| 1605 | * Success returns 0, Failure returns -E1000_ERR_PHY (-2) |
| 1606 | * |
| 1607 | * Polarity is determined based on the PHY specific status register. |
| 1608 | **/ |
Bruce Allan | 0be8401 | 2009-12-02 17:03:18 +0000 | [diff] [blame] | 1609 | s32 e1000_check_polarity_m88(struct e1000_hw *hw) |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 1610 | { |
| 1611 | struct e1000_phy_info *phy = &hw->phy; |
| 1612 | s32 ret_val; |
| 1613 | u16 data; |
| 1614 | |
| 1615 | ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_STATUS, &data); |
| 1616 | |
| 1617 | if (!ret_val) |
Bruce Allan | f0ff439 | 2013-02-20 04:05:39 +0000 | [diff] [blame] | 1618 | phy->cable_polarity = ((data & M88E1000_PSSR_REV_POLARITY) |
| 1619 | ? e1000_rev_polarity_reversed |
| 1620 | : e1000_rev_polarity_normal); |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 1621 | |
| 1622 | return ret_val; |
| 1623 | } |
| 1624 | |
| 1625 | /** |
| 1626 | * e1000_check_polarity_igp - Checks the polarity. |
| 1627 | * @hw: pointer to the HW structure |
| 1628 | * |
| 1629 | * Success returns 0, Failure returns -E1000_ERR_PHY (-2) |
| 1630 | * |
| 1631 | * Polarity is determined based on the PHY port status register, and the |
| 1632 | * current speed (since there is no polarity at 100Mbps). |
| 1633 | **/ |
Bruce Allan | 0be8401 | 2009-12-02 17:03:18 +0000 | [diff] [blame] | 1634 | s32 e1000_check_polarity_igp(struct e1000_hw *hw) |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 1635 | { |
| 1636 | struct e1000_phy_info *phy = &hw->phy; |
| 1637 | s32 ret_val; |
| 1638 | u16 data, offset, mask; |
| 1639 | |
Bruce Allan | e921eb1 | 2012-11-28 09:28:37 +0000 | [diff] [blame] | 1640 | /* Polarity is determined based on the speed of |
Bruce Allan | ad68076 | 2008-03-28 09:15:03 -0700 | [diff] [blame] | 1641 | * our connection. |
| 1642 | */ |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 1643 | ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_STATUS, &data); |
| 1644 | if (ret_val) |
| 1645 | return ret_val; |
| 1646 | |
| 1647 | if ((data & IGP01E1000_PSSR_SPEED_MASK) == |
| 1648 | IGP01E1000_PSSR_SPEED_1000MBPS) { |
Bruce Allan | e80bd1d | 2013-05-01 01:19:46 +0000 | [diff] [blame] | 1649 | offset = IGP01E1000_PHY_PCS_INIT_REG; |
| 1650 | mask = IGP01E1000_PHY_POLARITY_MASK; |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 1651 | } else { |
Bruce Allan | e921eb1 | 2012-11-28 09:28:37 +0000 | [diff] [blame] | 1652 | /* This really only applies to 10Mbps since |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 1653 | * there is no polarity for 100Mbps (always 0). |
| 1654 | */ |
Bruce Allan | e80bd1d | 2013-05-01 01:19:46 +0000 | [diff] [blame] | 1655 | offset = IGP01E1000_PHY_PORT_STATUS; |
| 1656 | mask = IGP01E1000_PSSR_POLARITY_REVERSED; |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 1657 | } |
| 1658 | |
| 1659 | ret_val = e1e_rphy(hw, offset, &data); |
| 1660 | |
| 1661 | if (!ret_val) |
Bruce Allan | f0ff439 | 2013-02-20 04:05:39 +0000 | [diff] [blame] | 1662 | phy->cable_polarity = ((data & mask) |
| 1663 | ? e1000_rev_polarity_reversed |
| 1664 | : e1000_rev_polarity_normal); |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 1665 | |
| 1666 | return ret_val; |
| 1667 | } |
| 1668 | |
| 1669 | /** |
Bruce Allan | 0be8401 | 2009-12-02 17:03:18 +0000 | [diff] [blame] | 1670 | * e1000_check_polarity_ife - Check cable polarity for IFE PHY |
| 1671 | * @hw: pointer to the HW structure |
| 1672 | * |
| 1673 | * Polarity is determined on the polarity reversal feature being enabled. |
| 1674 | **/ |
| 1675 | s32 e1000_check_polarity_ife(struct e1000_hw *hw) |
| 1676 | { |
| 1677 | struct e1000_phy_info *phy = &hw->phy; |
| 1678 | s32 ret_val; |
| 1679 | u16 phy_data, offset, mask; |
| 1680 | |
Bruce Allan | e921eb1 | 2012-11-28 09:28:37 +0000 | [diff] [blame] | 1681 | /* Polarity is determined based on the reversal feature being enabled. |
Bruce Allan | 0be8401 | 2009-12-02 17:03:18 +0000 | [diff] [blame] | 1682 | */ |
| 1683 | if (phy->polarity_correction) { |
| 1684 | offset = IFE_PHY_EXTENDED_STATUS_CONTROL; |
| 1685 | mask = IFE_PESC_POLARITY_REVERSED; |
| 1686 | } else { |
| 1687 | offset = IFE_PHY_SPECIAL_CONTROL; |
| 1688 | mask = IFE_PSC_FORCE_POLARITY; |
| 1689 | } |
| 1690 | |
| 1691 | ret_val = e1e_rphy(hw, offset, &phy_data); |
| 1692 | |
| 1693 | if (!ret_val) |
Bruce Allan | f0ff439 | 2013-02-20 04:05:39 +0000 | [diff] [blame] | 1694 | phy->cable_polarity = ((phy_data & mask) |
| 1695 | ? e1000_rev_polarity_reversed |
| 1696 | : e1000_rev_polarity_normal); |
Bruce Allan | 0be8401 | 2009-12-02 17:03:18 +0000 | [diff] [blame] | 1697 | |
| 1698 | return ret_val; |
| 1699 | } |
| 1700 | |
| 1701 | /** |
Bruce Allan | ad68076 | 2008-03-28 09:15:03 -0700 | [diff] [blame] | 1702 | * e1000_wait_autoneg - Wait for auto-neg completion |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 1703 | * @hw: pointer to the HW structure |
| 1704 | * |
| 1705 | * Waits for auto-negotiation to complete or for the auto-negotiation time |
| 1706 | * limit to expire, which ever happens first. |
| 1707 | **/ |
| 1708 | static s32 e1000_wait_autoneg(struct e1000_hw *hw) |
| 1709 | { |
| 1710 | s32 ret_val = 0; |
| 1711 | u16 i, phy_status; |
| 1712 | |
| 1713 | /* Break after autoneg completes or PHY_AUTO_NEG_LIMIT expires. */ |
| 1714 | for (i = PHY_AUTO_NEG_LIMIT; i > 0; i--) { |
Bruce Allan | c2ade1a | 2013-01-16 08:54:35 +0000 | [diff] [blame] | 1715 | ret_val = e1e_rphy(hw, MII_BMSR, &phy_status); |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 1716 | if (ret_val) |
| 1717 | break; |
Bruce Allan | c2ade1a | 2013-01-16 08:54:35 +0000 | [diff] [blame] | 1718 | ret_val = e1e_rphy(hw, MII_BMSR, &phy_status); |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 1719 | if (ret_val) |
| 1720 | break; |
Bruce Allan | c2ade1a | 2013-01-16 08:54:35 +0000 | [diff] [blame] | 1721 | if (phy_status & BMSR_ANEGCOMPLETE) |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 1722 | break; |
| 1723 | msleep(100); |
| 1724 | } |
| 1725 | |
Bruce Allan | e921eb1 | 2012-11-28 09:28:37 +0000 | [diff] [blame] | 1726 | /* PHY_AUTO_NEG_TIME expiration doesn't guarantee auto-negotiation |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 1727 | * has completed. |
| 1728 | */ |
| 1729 | return ret_val; |
| 1730 | } |
| 1731 | |
| 1732 | /** |
| 1733 | * e1000e_phy_has_link_generic - Polls PHY for link |
| 1734 | * @hw: pointer to the HW structure |
| 1735 | * @iterations: number of times to poll for link |
| 1736 | * @usec_interval: delay between polling attempts |
| 1737 | * @success: pointer to whether polling was successful or not |
| 1738 | * |
| 1739 | * Polls the PHY status register for link, 'iterations' number of times. |
| 1740 | **/ |
| 1741 | s32 e1000e_phy_has_link_generic(struct e1000_hw *hw, u32 iterations, |
Bruce Allan | 17e813e | 2013-02-20 04:06:01 +0000 | [diff] [blame] | 1742 | u32 usec_interval, bool *success) |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 1743 | { |
| 1744 | s32 ret_val = 0; |
| 1745 | u16 i, phy_status; |
| 1746 | |
| 1747 | for (i = 0; i < iterations; i++) { |
Bruce Allan | c2ade1a | 2013-01-16 08:54:35 +0000 | [diff] [blame] | 1748 | /* Some PHYs require the MII_BMSR register to be read |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 1749 | * twice due to the link bit being sticky. No harm doing |
| 1750 | * it across the board. |
| 1751 | */ |
Bruce Allan | c2ade1a | 2013-01-16 08:54:35 +0000 | [diff] [blame] | 1752 | ret_val = e1e_rphy(hw, MII_BMSR, &phy_status); |
David Ertman | 9e6c3b6 | 2013-12-14 07:18:18 +0000 | [diff] [blame] | 1753 | if (ret_val) { |
Bruce Allan | e921eb1 | 2012-11-28 09:28:37 +0000 | [diff] [blame] | 1754 | /* If the first read fails, another entity may have |
Bruce Allan | 906e8d9 | 2009-07-01 13:28:50 +0000 | [diff] [blame] | 1755 | * ownership of the resources, wait and try again to |
| 1756 | * see if they have relinquished the resources yet. |
| 1757 | */ |
David Ertman | 9e6c3b6 | 2013-12-14 07:18:18 +0000 | [diff] [blame] | 1758 | if (usec_interval >= 1000) |
| 1759 | msleep(usec_interval / 1000); |
| 1760 | else |
| 1761 | udelay(usec_interval); |
| 1762 | } |
Bruce Allan | c2ade1a | 2013-01-16 08:54:35 +0000 | [diff] [blame] | 1763 | ret_val = e1e_rphy(hw, MII_BMSR, &phy_status); |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 1764 | if (ret_val) |
| 1765 | break; |
Bruce Allan | c2ade1a | 2013-01-16 08:54:35 +0000 | [diff] [blame] | 1766 | if (phy_status & BMSR_LSTATUS) |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 1767 | break; |
| 1768 | if (usec_interval >= 1000) |
David Ertman | 9e6c3b6 | 2013-12-14 07:18:18 +0000 | [diff] [blame] | 1769 | msleep(usec_interval / 1000); |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 1770 | else |
| 1771 | udelay(usec_interval); |
| 1772 | } |
| 1773 | |
| 1774 | *success = (i < iterations); |
| 1775 | |
| 1776 | return ret_val; |
| 1777 | } |
| 1778 | |
| 1779 | /** |
| 1780 | * e1000e_get_cable_length_m88 - Determine cable length for m88 PHY |
| 1781 | * @hw: pointer to the HW structure |
| 1782 | * |
| 1783 | * Reads the PHY specific status register to retrieve the cable length |
| 1784 | * information. The cable length is determined by averaging the minimum and |
| 1785 | * maximum values to get the "average" cable length. The m88 PHY has four |
| 1786 | * possible cable length values, which are: |
| 1787 | * Register Value Cable Length |
| 1788 | * 0 < 50 meters |
| 1789 | * 1 50 - 80 meters |
| 1790 | * 2 80 - 110 meters |
| 1791 | * 3 110 - 140 meters |
| 1792 | * 4 > 140 meters |
| 1793 | **/ |
| 1794 | s32 e1000e_get_cable_length_m88(struct e1000_hw *hw) |
| 1795 | { |
| 1796 | struct e1000_phy_info *phy = &hw->phy; |
| 1797 | s32 ret_val; |
| 1798 | u16 phy_data, index; |
| 1799 | |
| 1800 | ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_STATUS, &phy_data); |
| 1801 | if (ret_val) |
Bruce Allan | 5015e53 | 2012-02-08 02:55:56 +0000 | [diff] [blame] | 1802 | return ret_val; |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 1803 | |
Bruce Allan | f0ff439 | 2013-02-20 04:05:39 +0000 | [diff] [blame] | 1804 | index = ((phy_data & M88E1000_PSSR_CABLE_LENGTH) >> |
| 1805 | M88E1000_PSSR_CABLE_LENGTH_SHIFT); |
Bruce Allan | 5015e53 | 2012-02-08 02:55:56 +0000 | [diff] [blame] | 1806 | |
| 1807 | if (index >= M88E1000_CABLE_LENGTH_TABLE_SIZE - 1) |
| 1808 | return -E1000_ERR_PHY; |
Bruce Allan | eb656d4 | 2009-12-01 15:47:02 +0000 | [diff] [blame] | 1809 | |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 1810 | phy->min_cable_length = e1000_m88_cable_length_table[index]; |
Bruce Allan | eb656d4 | 2009-12-01 15:47:02 +0000 | [diff] [blame] | 1811 | phy->max_cable_length = e1000_m88_cable_length_table[index + 1]; |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 1812 | |
| 1813 | phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2; |
| 1814 | |
Bruce Allan | 5015e53 | 2012-02-08 02:55:56 +0000 | [diff] [blame] | 1815 | return 0; |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 1816 | } |
| 1817 | |
| 1818 | /** |
| 1819 | * e1000e_get_cable_length_igp_2 - Determine cable length for igp2 PHY |
| 1820 | * @hw: pointer to the HW structure |
| 1821 | * |
| 1822 | * The automatic gain control (agc) normalizes the amplitude of the |
| 1823 | * received signal, adjusting for the attenuation produced by the |
Auke Kok | 489815c | 2008-02-21 15:11:07 -0800 | [diff] [blame] | 1824 | * cable. By reading the AGC registers, which represent the |
Bruce Allan | 5ff5b66 | 2009-12-01 15:51:11 +0000 | [diff] [blame] | 1825 | * combination of coarse and fine gain value, the value can be put |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 1826 | * into a lookup table to obtain the approximate cable length |
| 1827 | * for each channel. |
| 1828 | **/ |
| 1829 | s32 e1000e_get_cable_length_igp_2(struct e1000_hw *hw) |
| 1830 | { |
| 1831 | struct e1000_phy_info *phy = &hw->phy; |
| 1832 | s32 ret_val; |
| 1833 | u16 phy_data, i, agc_value = 0; |
| 1834 | u16 cur_agc_index, max_agc_index = 0; |
| 1835 | u16 min_agc_index = IGP02E1000_CABLE_LENGTH_TABLE_SIZE - 1; |
Jeff Kirsher | 6674450 | 2010-12-01 19:59:50 +0000 | [diff] [blame] | 1836 | static const u16 agc_reg_array[IGP02E1000_PHY_CHANNEL_NUM] = { |
Bruce Allan | f0ff439 | 2013-02-20 04:05:39 +0000 | [diff] [blame] | 1837 | IGP02E1000_PHY_AGC_A, |
| 1838 | IGP02E1000_PHY_AGC_B, |
| 1839 | IGP02E1000_PHY_AGC_C, |
| 1840 | IGP02E1000_PHY_AGC_D |
Jeff Kirsher | 6674450 | 2010-12-01 19:59:50 +0000 | [diff] [blame] | 1841 | }; |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 1842 | |
| 1843 | /* Read the AGC registers for all channels */ |
| 1844 | for (i = 0; i < IGP02E1000_PHY_CHANNEL_NUM; i++) { |
| 1845 | ret_val = e1e_rphy(hw, agc_reg_array[i], &phy_data); |
| 1846 | if (ret_val) |
| 1847 | return ret_val; |
| 1848 | |
Bruce Allan | e921eb1 | 2012-11-28 09:28:37 +0000 | [diff] [blame] | 1849 | /* Getting bits 15:9, which represent the combination of |
Bruce Allan | 5ff5b66 | 2009-12-01 15:51:11 +0000 | [diff] [blame] | 1850 | * coarse and fine gain values. The result is a number |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 1851 | * that can be put into the lookup table to obtain the |
Bruce Allan | ad68076 | 2008-03-28 09:15:03 -0700 | [diff] [blame] | 1852 | * approximate cable length. |
| 1853 | */ |
Bruce Allan | f0ff439 | 2013-02-20 04:05:39 +0000 | [diff] [blame] | 1854 | cur_agc_index = ((phy_data >> IGP02E1000_AGC_LENGTH_SHIFT) & |
| 1855 | IGP02E1000_AGC_LENGTH_MASK); |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 1856 | |
| 1857 | /* Array index bound check. */ |
| 1858 | if ((cur_agc_index >= IGP02E1000_CABLE_LENGTH_TABLE_SIZE) || |
| 1859 | (cur_agc_index == 0)) |
| 1860 | return -E1000_ERR_PHY; |
| 1861 | |
| 1862 | /* Remove min & max AGC values from calculation. */ |
| 1863 | if (e1000_igp_2_cable_length_table[min_agc_index] > |
| 1864 | e1000_igp_2_cable_length_table[cur_agc_index]) |
| 1865 | min_agc_index = cur_agc_index; |
| 1866 | if (e1000_igp_2_cable_length_table[max_agc_index] < |
| 1867 | e1000_igp_2_cable_length_table[cur_agc_index]) |
| 1868 | max_agc_index = cur_agc_index; |
| 1869 | |
| 1870 | agc_value += e1000_igp_2_cable_length_table[cur_agc_index]; |
| 1871 | } |
| 1872 | |
| 1873 | agc_value -= (e1000_igp_2_cable_length_table[min_agc_index] + |
| 1874 | e1000_igp_2_cable_length_table[max_agc_index]); |
| 1875 | agc_value /= (IGP02E1000_PHY_CHANNEL_NUM - 2); |
| 1876 | |
| 1877 | /* Calculate cable length with the error range of +/- 10 meters. */ |
Bruce Allan | f0ff439 | 2013-02-20 04:05:39 +0000 | [diff] [blame] | 1878 | phy->min_cable_length = (((agc_value - IGP02E1000_AGC_RANGE) > 0) ? |
| 1879 | (agc_value - IGP02E1000_AGC_RANGE) : 0); |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 1880 | phy->max_cable_length = agc_value + IGP02E1000_AGC_RANGE; |
| 1881 | |
| 1882 | phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2; |
| 1883 | |
Bruce Allan | 8260725 | 2012-02-08 02:55:09 +0000 | [diff] [blame] | 1884 | return 0; |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 1885 | } |
| 1886 | |
| 1887 | /** |
| 1888 | * e1000e_get_phy_info_m88 - Retrieve PHY information |
| 1889 | * @hw: pointer to the HW structure |
| 1890 | * |
| 1891 | * Valid for only copper links. Read the PHY status register (sticky read) |
| 1892 | * to verify that link is up. Read the PHY special control register to |
| 1893 | * determine the polarity and 10base-T extended distance. Read the PHY |
| 1894 | * special status register to determine MDI/MDIx and current speed. If |
| 1895 | * speed is 1000, then determine cable length, local and remote receiver. |
| 1896 | **/ |
| 1897 | s32 e1000e_get_phy_info_m88(struct e1000_hw *hw) |
| 1898 | { |
| 1899 | struct e1000_phy_info *phy = &hw->phy; |
Bruce Allan | e80bd1d | 2013-05-01 01:19:46 +0000 | [diff] [blame] | 1900 | s32 ret_val; |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 1901 | u16 phy_data; |
| 1902 | bool link; |
| 1903 | |
Bruce Allan | 0be8401 | 2009-12-02 17:03:18 +0000 | [diff] [blame] | 1904 | if (phy->media_type != e1000_media_type_copper) { |
Bruce Allan | 3bb99fe | 2009-11-20 23:25:07 +0000 | [diff] [blame] | 1905 | e_dbg("Phy info is only valid for copper media\n"); |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 1906 | return -E1000_ERR_CONFIG; |
| 1907 | } |
| 1908 | |
| 1909 | ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link); |
| 1910 | if (ret_val) |
| 1911 | return ret_val; |
| 1912 | |
| 1913 | if (!link) { |
Bruce Allan | 3bb99fe | 2009-11-20 23:25:07 +0000 | [diff] [blame] | 1914 | e_dbg("Phy info is only valid if link is up\n"); |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 1915 | return -E1000_ERR_CONFIG; |
| 1916 | } |
| 1917 | |
| 1918 | ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); |
| 1919 | if (ret_val) |
| 1920 | return ret_val; |
| 1921 | |
Bruce Allan | 04499ec | 2012-04-13 00:08:31 +0000 | [diff] [blame] | 1922 | phy->polarity_correction = !!(phy_data & |
| 1923 | M88E1000_PSCR_POLARITY_REVERSAL); |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 1924 | |
| 1925 | ret_val = e1000_check_polarity_m88(hw); |
| 1926 | if (ret_val) |
| 1927 | return ret_val; |
| 1928 | |
| 1929 | ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_STATUS, &phy_data); |
| 1930 | if (ret_val) |
| 1931 | return ret_val; |
| 1932 | |
Bruce Allan | 04499ec | 2012-04-13 00:08:31 +0000 | [diff] [blame] | 1933 | phy->is_mdix = !!(phy_data & M88E1000_PSSR_MDIX); |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 1934 | |
| 1935 | if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS) { |
Bruce Allan | dde3a57 | 2013-01-05 08:06:24 +0000 | [diff] [blame] | 1936 | ret_val = hw->phy.ops.get_cable_length(hw); |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 1937 | if (ret_val) |
| 1938 | return ret_val; |
| 1939 | |
Bruce Allan | c2ade1a | 2013-01-16 08:54:35 +0000 | [diff] [blame] | 1940 | ret_val = e1e_rphy(hw, MII_STAT1000, &phy_data); |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 1941 | if (ret_val) |
| 1942 | return ret_val; |
| 1943 | |
Bruce Allan | c2ade1a | 2013-01-16 08:54:35 +0000 | [diff] [blame] | 1944 | phy->local_rx = (phy_data & LPA_1000LOCALRXOK) |
| 1945 | ? e1000_1000t_rx_status_ok : e1000_1000t_rx_status_not_ok; |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 1946 | |
Bruce Allan | c2ade1a | 2013-01-16 08:54:35 +0000 | [diff] [blame] | 1947 | phy->remote_rx = (phy_data & LPA_1000REMRXOK) |
| 1948 | ? e1000_1000t_rx_status_ok : e1000_1000t_rx_status_not_ok; |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 1949 | } else { |
| 1950 | /* Set values to "undefined" */ |
| 1951 | phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED; |
| 1952 | phy->local_rx = e1000_1000t_rx_status_undefined; |
| 1953 | phy->remote_rx = e1000_1000t_rx_status_undefined; |
| 1954 | } |
| 1955 | |
| 1956 | return ret_val; |
| 1957 | } |
| 1958 | |
| 1959 | /** |
| 1960 | * e1000e_get_phy_info_igp - Retrieve igp PHY information |
| 1961 | * @hw: pointer to the HW structure |
| 1962 | * |
| 1963 | * Read PHY status to determine if link is up. If link is up, then |
| 1964 | * set/determine 10base-T extended distance and polarity correction. Read |
| 1965 | * PHY port status to determine MDI/MDIx and speed. Based on the speed, |
| 1966 | * determine on the cable length, local and remote receiver. |
| 1967 | **/ |
| 1968 | s32 e1000e_get_phy_info_igp(struct e1000_hw *hw) |
| 1969 | { |
| 1970 | struct e1000_phy_info *phy = &hw->phy; |
| 1971 | s32 ret_val; |
| 1972 | u16 data; |
| 1973 | bool link; |
| 1974 | |
| 1975 | ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link); |
| 1976 | if (ret_val) |
| 1977 | return ret_val; |
| 1978 | |
| 1979 | if (!link) { |
Bruce Allan | 3bb99fe | 2009-11-20 23:25:07 +0000 | [diff] [blame] | 1980 | e_dbg("Phy info is only valid if link is up\n"); |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 1981 | return -E1000_ERR_CONFIG; |
| 1982 | } |
| 1983 | |
Bruce Allan | 564ea9b | 2009-11-20 23:26:44 +0000 | [diff] [blame] | 1984 | phy->polarity_correction = true; |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 1985 | |
| 1986 | ret_val = e1000_check_polarity_igp(hw); |
| 1987 | if (ret_val) |
| 1988 | return ret_val; |
| 1989 | |
| 1990 | ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_STATUS, &data); |
| 1991 | if (ret_val) |
| 1992 | return ret_val; |
| 1993 | |
Bruce Allan | 04499ec | 2012-04-13 00:08:31 +0000 | [diff] [blame] | 1994 | phy->is_mdix = !!(data & IGP01E1000_PSSR_MDIX); |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 1995 | |
| 1996 | if ((data & IGP01E1000_PSSR_SPEED_MASK) == |
| 1997 | IGP01E1000_PSSR_SPEED_1000MBPS) { |
Bruce Allan | dde3a57 | 2013-01-05 08:06:24 +0000 | [diff] [blame] | 1998 | ret_val = phy->ops.get_cable_length(hw); |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 1999 | if (ret_val) |
| 2000 | return ret_val; |
| 2001 | |
Bruce Allan | c2ade1a | 2013-01-16 08:54:35 +0000 | [diff] [blame] | 2002 | ret_val = e1e_rphy(hw, MII_STAT1000, &data); |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 2003 | if (ret_val) |
| 2004 | return ret_val; |
| 2005 | |
Bruce Allan | c2ade1a | 2013-01-16 08:54:35 +0000 | [diff] [blame] | 2006 | phy->local_rx = (data & LPA_1000LOCALRXOK) |
| 2007 | ? e1000_1000t_rx_status_ok : e1000_1000t_rx_status_not_ok; |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 2008 | |
Bruce Allan | c2ade1a | 2013-01-16 08:54:35 +0000 | [diff] [blame] | 2009 | phy->remote_rx = (data & LPA_1000REMRXOK) |
| 2010 | ? e1000_1000t_rx_status_ok : e1000_1000t_rx_status_not_ok; |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 2011 | } else { |
| 2012 | phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED; |
| 2013 | phy->local_rx = e1000_1000t_rx_status_undefined; |
| 2014 | phy->remote_rx = e1000_1000t_rx_status_undefined; |
| 2015 | } |
| 2016 | |
| 2017 | return ret_val; |
| 2018 | } |
| 2019 | |
| 2020 | /** |
Bruce Allan | 0be8401 | 2009-12-02 17:03:18 +0000 | [diff] [blame] | 2021 | * e1000_get_phy_info_ife - Retrieves various IFE PHY states |
| 2022 | * @hw: pointer to the HW structure |
| 2023 | * |
| 2024 | * Populates "phy" structure with various feature states. |
| 2025 | **/ |
| 2026 | s32 e1000_get_phy_info_ife(struct e1000_hw *hw) |
| 2027 | { |
| 2028 | struct e1000_phy_info *phy = &hw->phy; |
| 2029 | s32 ret_val; |
| 2030 | u16 data; |
| 2031 | bool link; |
| 2032 | |
| 2033 | ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link); |
| 2034 | if (ret_val) |
Bruce Allan | 5015e53 | 2012-02-08 02:55:56 +0000 | [diff] [blame] | 2035 | return ret_val; |
Bruce Allan | 0be8401 | 2009-12-02 17:03:18 +0000 | [diff] [blame] | 2036 | |
| 2037 | if (!link) { |
| 2038 | e_dbg("Phy info is only valid if link is up\n"); |
Bruce Allan | 5015e53 | 2012-02-08 02:55:56 +0000 | [diff] [blame] | 2039 | return -E1000_ERR_CONFIG; |
Bruce Allan | 0be8401 | 2009-12-02 17:03:18 +0000 | [diff] [blame] | 2040 | } |
| 2041 | |
| 2042 | ret_val = e1e_rphy(hw, IFE_PHY_SPECIAL_CONTROL, &data); |
| 2043 | if (ret_val) |
Bruce Allan | 5015e53 | 2012-02-08 02:55:56 +0000 | [diff] [blame] | 2044 | return ret_val; |
Bruce Allan | 04499ec | 2012-04-13 00:08:31 +0000 | [diff] [blame] | 2045 | phy->polarity_correction = !(data & IFE_PSC_AUTO_POLARITY_DISABLE); |
Bruce Allan | 0be8401 | 2009-12-02 17:03:18 +0000 | [diff] [blame] | 2046 | |
| 2047 | if (phy->polarity_correction) { |
| 2048 | ret_val = e1000_check_polarity_ife(hw); |
| 2049 | if (ret_val) |
Bruce Allan | 5015e53 | 2012-02-08 02:55:56 +0000 | [diff] [blame] | 2050 | return ret_val; |
Bruce Allan | 0be8401 | 2009-12-02 17:03:18 +0000 | [diff] [blame] | 2051 | } else { |
| 2052 | /* Polarity is forced */ |
Bruce Allan | f0ff439 | 2013-02-20 04:05:39 +0000 | [diff] [blame] | 2053 | phy->cable_polarity = ((data & IFE_PSC_FORCE_POLARITY) |
| 2054 | ? e1000_rev_polarity_reversed |
| 2055 | : e1000_rev_polarity_normal); |
Bruce Allan | 0be8401 | 2009-12-02 17:03:18 +0000 | [diff] [blame] | 2056 | } |
| 2057 | |
| 2058 | ret_val = e1e_rphy(hw, IFE_PHY_MDIX_CONTROL, &data); |
| 2059 | if (ret_val) |
Bruce Allan | 5015e53 | 2012-02-08 02:55:56 +0000 | [diff] [blame] | 2060 | return ret_val; |
Bruce Allan | 0be8401 | 2009-12-02 17:03:18 +0000 | [diff] [blame] | 2061 | |
Bruce Allan | 04499ec | 2012-04-13 00:08:31 +0000 | [diff] [blame] | 2062 | phy->is_mdix = !!(data & IFE_PMC_MDIX_STATUS); |
Bruce Allan | 0be8401 | 2009-12-02 17:03:18 +0000 | [diff] [blame] | 2063 | |
| 2064 | /* The following parameters are undefined for 10/100 operation. */ |
| 2065 | phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED; |
| 2066 | phy->local_rx = e1000_1000t_rx_status_undefined; |
| 2067 | phy->remote_rx = e1000_1000t_rx_status_undefined; |
| 2068 | |
Bruce Allan | 5015e53 | 2012-02-08 02:55:56 +0000 | [diff] [blame] | 2069 | return 0; |
Bruce Allan | 0be8401 | 2009-12-02 17:03:18 +0000 | [diff] [blame] | 2070 | } |
| 2071 | |
| 2072 | /** |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 2073 | * e1000e_phy_sw_reset - PHY software reset |
| 2074 | * @hw: pointer to the HW structure |
| 2075 | * |
| 2076 | * Does a software reset of the PHY by reading the PHY control register and |
| 2077 | * setting/write the control register reset bit to the PHY. |
| 2078 | **/ |
| 2079 | s32 e1000e_phy_sw_reset(struct e1000_hw *hw) |
| 2080 | { |
| 2081 | s32 ret_val; |
| 2082 | u16 phy_ctrl; |
| 2083 | |
Bruce Allan | c2ade1a | 2013-01-16 08:54:35 +0000 | [diff] [blame] | 2084 | ret_val = e1e_rphy(hw, MII_BMCR, &phy_ctrl); |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 2085 | if (ret_val) |
| 2086 | return ret_val; |
| 2087 | |
Bruce Allan | c2ade1a | 2013-01-16 08:54:35 +0000 | [diff] [blame] | 2088 | phy_ctrl |= BMCR_RESET; |
| 2089 | ret_val = e1e_wphy(hw, MII_BMCR, phy_ctrl); |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 2090 | if (ret_val) |
| 2091 | return ret_val; |
| 2092 | |
| 2093 | udelay(1); |
| 2094 | |
| 2095 | return ret_val; |
| 2096 | } |
| 2097 | |
| 2098 | /** |
| 2099 | * e1000e_phy_hw_reset_generic - PHY hardware reset |
| 2100 | * @hw: pointer to the HW structure |
| 2101 | * |
| 2102 | * Verify the reset block is not blocking us from resetting. Acquire |
| 2103 | * semaphore (if necessary) and read/set/write the device control reset |
| 2104 | * bit in the PHY. Wait the appropriate delay time for the device to |
Auke Kok | 489815c | 2008-02-21 15:11:07 -0800 | [diff] [blame] | 2105 | * reset and release the semaphore (if necessary). |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 2106 | **/ |
| 2107 | s32 e1000e_phy_hw_reset_generic(struct e1000_hw *hw) |
| 2108 | { |
| 2109 | struct e1000_phy_info *phy = &hw->phy; |
| 2110 | s32 ret_val; |
| 2111 | u32 ctrl; |
| 2112 | |
Bruce Allan | 470a542 | 2012-05-26 06:08:48 +0000 | [diff] [blame] | 2113 | if (phy->ops.check_reset_block) { |
| 2114 | ret_val = phy->ops.check_reset_block(hw); |
| 2115 | if (ret_val) |
| 2116 | return 0; |
| 2117 | } |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 2118 | |
Bruce Allan | 94d8186 | 2009-11-20 23:25:26 +0000 | [diff] [blame] | 2119 | ret_val = phy->ops.acquire(hw); |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 2120 | if (ret_val) |
| 2121 | return ret_val; |
| 2122 | |
| 2123 | ctrl = er32(CTRL); |
| 2124 | ew32(CTRL, ctrl | E1000_CTRL_PHY_RST); |
| 2125 | e1e_flush(); |
| 2126 | |
| 2127 | udelay(phy->reset_delay_us); |
| 2128 | |
| 2129 | ew32(CTRL, ctrl); |
| 2130 | e1e_flush(); |
| 2131 | |
Bruce Allan | ce43a21 | 2013-02-20 04:06:32 +0000 | [diff] [blame] | 2132 | usleep_range(150, 300); |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 2133 | |
Bruce Allan | 94d8186 | 2009-11-20 23:25:26 +0000 | [diff] [blame] | 2134 | phy->ops.release(hw); |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 2135 | |
Bruce Allan | 84c1bef | 2013-01-05 08:06:19 +0000 | [diff] [blame] | 2136 | return phy->ops.get_cfg_done(hw); |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 2137 | } |
| 2138 | |
| 2139 | /** |
Bruce Allan | fe90849 | 2013-01-05 08:06:14 +0000 | [diff] [blame] | 2140 | * e1000e_get_cfg_done_generic - Generic configuration done |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 2141 | * @hw: pointer to the HW structure |
| 2142 | * |
| 2143 | * Generic function to wait 10 milli-seconds for configuration to complete |
| 2144 | * and return success. |
| 2145 | **/ |
Bruce Allan | 8bb6286 | 2013-01-16 08:46:49 +0000 | [diff] [blame] | 2146 | s32 e1000e_get_cfg_done_generic(struct e1000_hw __always_unused *hw) |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 2147 | { |
| 2148 | mdelay(10); |
Bruce Allan | 3d3a167 | 2012-02-23 03:13:18 +0000 | [diff] [blame] | 2149 | |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 2150 | return 0; |
| 2151 | } |
| 2152 | |
Bruce Allan | f4187b5 | 2008-08-26 18:36:50 -0700 | [diff] [blame] | 2153 | /** |
| 2154 | * e1000e_phy_init_script_igp3 - Inits the IGP3 PHY |
| 2155 | * @hw: pointer to the HW structure |
| 2156 | * |
| 2157 | * Initializes a Intel Gigabit PHY3 when an EEPROM is not present. |
| 2158 | **/ |
| 2159 | s32 e1000e_phy_init_script_igp3(struct e1000_hw *hw) |
| 2160 | { |
Bruce Allan | 3bb99fe | 2009-11-20 23:25:07 +0000 | [diff] [blame] | 2161 | e_dbg("Running IGP 3 PHY init script\n"); |
Bruce Allan | f4187b5 | 2008-08-26 18:36:50 -0700 | [diff] [blame] | 2162 | |
| 2163 | /* PHY init IGP 3 */ |
| 2164 | /* Enable rise/fall, 10-mode work in class-A */ |
| 2165 | e1e_wphy(hw, 0x2F5B, 0x9018); |
| 2166 | /* Remove all caps from Replica path filter */ |
| 2167 | e1e_wphy(hw, 0x2F52, 0x0000); |
| 2168 | /* Bias trimming for ADC, AFE and Driver (Default) */ |
| 2169 | e1e_wphy(hw, 0x2FB1, 0x8B24); |
| 2170 | /* Increase Hybrid poly bias */ |
| 2171 | e1e_wphy(hw, 0x2FB2, 0xF8F0); |
| 2172 | /* Add 4% to Tx amplitude in Gig mode */ |
| 2173 | e1e_wphy(hw, 0x2010, 0x10B0); |
| 2174 | /* Disable trimming (TTT) */ |
| 2175 | e1e_wphy(hw, 0x2011, 0x0000); |
| 2176 | /* Poly DC correction to 94.6% + 2% for all channels */ |
| 2177 | e1e_wphy(hw, 0x20DD, 0x249A); |
| 2178 | /* ABS DC correction to 95.9% */ |
| 2179 | e1e_wphy(hw, 0x20DE, 0x00D3); |
| 2180 | /* BG temp curve trim */ |
| 2181 | e1e_wphy(hw, 0x28B4, 0x04CE); |
| 2182 | /* Increasing ADC OPAMP stage 1 currents to max */ |
| 2183 | e1e_wphy(hw, 0x2F70, 0x29E4); |
| 2184 | /* Force 1000 ( required for enabling PHY regs configuration) */ |
| 2185 | e1e_wphy(hw, 0x0000, 0x0140); |
| 2186 | /* Set upd_freq to 6 */ |
| 2187 | e1e_wphy(hw, 0x1F30, 0x1606); |
| 2188 | /* Disable NPDFE */ |
| 2189 | e1e_wphy(hw, 0x1F31, 0xB814); |
| 2190 | /* Disable adaptive fixed FFE (Default) */ |
| 2191 | e1e_wphy(hw, 0x1F35, 0x002A); |
| 2192 | /* Enable FFE hysteresis */ |
| 2193 | e1e_wphy(hw, 0x1F3E, 0x0067); |
| 2194 | /* Fixed FFE for short cable lengths */ |
| 2195 | e1e_wphy(hw, 0x1F54, 0x0065); |
| 2196 | /* Fixed FFE for medium cable lengths */ |
| 2197 | e1e_wphy(hw, 0x1F55, 0x002A); |
| 2198 | /* Fixed FFE for long cable lengths */ |
| 2199 | e1e_wphy(hw, 0x1F56, 0x002A); |
| 2200 | /* Enable Adaptive Clip Threshold */ |
| 2201 | e1e_wphy(hw, 0x1F72, 0x3FB0); |
| 2202 | /* AHT reset limit to 1 */ |
| 2203 | e1e_wphy(hw, 0x1F76, 0xC0FF); |
| 2204 | /* Set AHT master delay to 127 msec */ |
| 2205 | e1e_wphy(hw, 0x1F77, 0x1DEC); |
| 2206 | /* Set scan bits for AHT */ |
| 2207 | e1e_wphy(hw, 0x1F78, 0xF9EF); |
| 2208 | /* Set AHT Preset bits */ |
| 2209 | e1e_wphy(hw, 0x1F79, 0x0210); |
| 2210 | /* Change integ_factor of channel A to 3 */ |
| 2211 | e1e_wphy(hw, 0x1895, 0x0003); |
| 2212 | /* Change prop_factor of channels BCD to 8 */ |
| 2213 | e1e_wphy(hw, 0x1796, 0x0008); |
| 2214 | /* Change cg_icount + enable integbp for channels BCD */ |
| 2215 | e1e_wphy(hw, 0x1798, 0xD008); |
Bruce Allan | e921eb1 | 2012-11-28 09:28:37 +0000 | [diff] [blame] | 2216 | /* Change cg_icount + enable integbp + change prop_factor_master |
Bruce Allan | f4187b5 | 2008-08-26 18:36:50 -0700 | [diff] [blame] | 2217 | * to 8 for channel A |
| 2218 | */ |
| 2219 | e1e_wphy(hw, 0x1898, 0xD918); |
| 2220 | /* Disable AHT in Slave mode on channel A */ |
| 2221 | e1e_wphy(hw, 0x187A, 0x0800); |
Bruce Allan | e921eb1 | 2012-11-28 09:28:37 +0000 | [diff] [blame] | 2222 | /* Enable LPLU and disable AN to 1000 in non-D0a states, |
Bruce Allan | f4187b5 | 2008-08-26 18:36:50 -0700 | [diff] [blame] | 2223 | * Enable SPD+B2B |
| 2224 | */ |
| 2225 | e1e_wphy(hw, 0x0019, 0x008D); |
| 2226 | /* Enable restart AN on an1000_dis change */ |
| 2227 | e1e_wphy(hw, 0x001B, 0x2080); |
| 2228 | /* Enable wh_fifo read clock in 10/100 modes */ |
| 2229 | e1e_wphy(hw, 0x0014, 0x0045); |
| 2230 | /* Restart AN, Speed selection is 1000 */ |
| 2231 | e1e_wphy(hw, 0x0000, 0x1340); |
| 2232 | |
| 2233 | return 0; |
| 2234 | } |
| 2235 | |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 2236 | /** |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 2237 | * e1000e_get_phy_type_from_id - Get PHY type from id |
| 2238 | * @phy_id: phy_id read from the phy |
| 2239 | * |
| 2240 | * Returns the phy type from the id. |
| 2241 | **/ |
| 2242 | enum e1000_phy_type e1000e_get_phy_type_from_id(u32 phy_id) |
| 2243 | { |
| 2244 | enum e1000_phy_type phy_type = e1000_phy_unknown; |
| 2245 | |
| 2246 | switch (phy_id) { |
| 2247 | case M88E1000_I_PHY_ID: |
| 2248 | case M88E1000_E_PHY_ID: |
| 2249 | case M88E1111_I_PHY_ID: |
| 2250 | case M88E1011_I_PHY_ID: |
| 2251 | phy_type = e1000_phy_m88; |
| 2252 | break; |
Bruce Allan | e80bd1d | 2013-05-01 01:19:46 +0000 | [diff] [blame] | 2253 | case IGP01E1000_I_PHY_ID: /* IGP 1 & 2 share this */ |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 2254 | phy_type = e1000_phy_igp_2; |
| 2255 | break; |
| 2256 | case GG82563_E_PHY_ID: |
| 2257 | phy_type = e1000_phy_gg82563; |
| 2258 | break; |
| 2259 | case IGP03E1000_E_PHY_ID: |
| 2260 | phy_type = e1000_phy_igp_3; |
| 2261 | break; |
| 2262 | case IFE_E_PHY_ID: |
| 2263 | case IFE_PLUS_E_PHY_ID: |
| 2264 | case IFE_C_E_PHY_ID: |
| 2265 | phy_type = e1000_phy_ife; |
| 2266 | break; |
Bruce Allan | 97ac8ca | 2008-04-29 09:16:05 -0700 | [diff] [blame] | 2267 | case BME1000_E_PHY_ID: |
| 2268 | case BME1000_E_PHY_ID_R2: |
| 2269 | phy_type = e1000_phy_bm; |
| 2270 | break; |
Bruce Allan | a4f58f5 | 2009-06-02 11:29:18 +0000 | [diff] [blame] | 2271 | case I82578_E_PHY_ID: |
| 2272 | phy_type = e1000_phy_82578; |
| 2273 | break; |
| 2274 | case I82577_E_PHY_ID: |
| 2275 | phy_type = e1000_phy_82577; |
| 2276 | break; |
Bruce Allan | d3738bb | 2010-06-16 13:27:28 +0000 | [diff] [blame] | 2277 | case I82579_E_PHY_ID: |
| 2278 | phy_type = e1000_phy_82579; |
| 2279 | break; |
Bruce Allan | 2fbe452 | 2012-04-19 03:21:47 +0000 | [diff] [blame] | 2280 | case I217_E_PHY_ID: |
| 2281 | phy_type = e1000_phy_i217; |
| 2282 | break; |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 2283 | default: |
| 2284 | phy_type = e1000_phy_unknown; |
| 2285 | break; |
| 2286 | } |
| 2287 | return phy_type; |
| 2288 | } |
| 2289 | |
| 2290 | /** |
Bruce Allan | 97ac8ca | 2008-04-29 09:16:05 -0700 | [diff] [blame] | 2291 | * e1000e_determine_phy_address - Determines PHY address. |
| 2292 | * @hw: pointer to the HW structure |
| 2293 | * |
| 2294 | * This uses a trial and error method to loop through possible PHY |
| 2295 | * addresses. It tests each by reading the PHY ID registers and |
| 2296 | * checking for a match. |
| 2297 | **/ |
| 2298 | s32 e1000e_determine_phy_address(struct e1000_hw *hw) |
| 2299 | { |
Bruce Allan | 5eb6f3c | 2009-12-02 17:02:43 +0000 | [diff] [blame] | 2300 | u32 phy_addr = 0; |
| 2301 | u32 i; |
Bruce Allan | 97ac8ca | 2008-04-29 09:16:05 -0700 | [diff] [blame] | 2302 | enum e1000_phy_type phy_type = e1000_phy_unknown; |
| 2303 | |
Bruce Allan | 5eb6f3c | 2009-12-02 17:02:43 +0000 | [diff] [blame] | 2304 | hw->phy.id = phy_type; |
| 2305 | |
| 2306 | for (phy_addr = 0; phy_addr < E1000_MAX_PHY_ADDR; phy_addr++) { |
| 2307 | hw->phy.addr = phy_addr; |
| 2308 | i = 0; |
| 2309 | |
| 2310 | do { |
Bruce Allan | 97ac8ca | 2008-04-29 09:16:05 -0700 | [diff] [blame] | 2311 | e1000e_get_phy_id(hw); |
| 2312 | phy_type = e1000e_get_phy_type_from_id(hw->phy.id); |
| 2313 | |
Bruce Allan | e921eb1 | 2012-11-28 09:28:37 +0000 | [diff] [blame] | 2314 | /* If phy_type is valid, break - we found our |
Bruce Allan | 97ac8ca | 2008-04-29 09:16:05 -0700 | [diff] [blame] | 2315 | * PHY address |
| 2316 | */ |
Bruce Allan | e80bd1d | 2013-05-01 01:19:46 +0000 | [diff] [blame] | 2317 | if (phy_type != e1000_phy_unknown) |
Bruce Allan | 5015e53 | 2012-02-08 02:55:56 +0000 | [diff] [blame] | 2318 | return 0; |
| 2319 | |
Bruce Allan | 1bba438 | 2011-03-19 00:27:20 +0000 | [diff] [blame] | 2320 | usleep_range(1000, 2000); |
Bruce Allan | 5eb6f3c | 2009-12-02 17:02:43 +0000 | [diff] [blame] | 2321 | i++; |
| 2322 | } while (i < 10); |
| 2323 | } |
Bruce Allan | 97ac8ca | 2008-04-29 09:16:05 -0700 | [diff] [blame] | 2324 | |
Bruce Allan | 5015e53 | 2012-02-08 02:55:56 +0000 | [diff] [blame] | 2325 | return -E1000_ERR_PHY_TYPE; |
Bruce Allan | 97ac8ca | 2008-04-29 09:16:05 -0700 | [diff] [blame] | 2326 | } |
| 2327 | |
| 2328 | /** |
| 2329 | * e1000_get_phy_addr_for_bm_page - Retrieve PHY page address |
| 2330 | * @page: page to access |
| 2331 | * |
| 2332 | * Returns the phy address for the page requested. |
| 2333 | **/ |
| 2334 | static u32 e1000_get_phy_addr_for_bm_page(u32 page, u32 reg) |
| 2335 | { |
| 2336 | u32 phy_addr = 2; |
| 2337 | |
| 2338 | if ((page >= 768) || (page == 0 && reg == 25) || (reg == 31)) |
| 2339 | phy_addr = 1; |
| 2340 | |
| 2341 | return phy_addr; |
| 2342 | } |
| 2343 | |
| 2344 | /** |
| 2345 | * e1000e_write_phy_reg_bm - Write BM PHY register |
| 2346 | * @hw: pointer to the HW structure |
| 2347 | * @offset: register offset to write to |
| 2348 | * @data: data to write at register offset |
| 2349 | * |
| 2350 | * Acquires semaphore, if necessary, then writes the data to PHY register |
| 2351 | * at the offset. Release any acquired semaphores before exiting. |
| 2352 | **/ |
| 2353 | s32 e1000e_write_phy_reg_bm(struct e1000_hw *hw, u32 offset, u16 data) |
| 2354 | { |
| 2355 | s32 ret_val; |
Bruce Allan | 97ac8ca | 2008-04-29 09:16:05 -0700 | [diff] [blame] | 2356 | u32 page = offset >> IGP_PAGE_SHIFT; |
Bruce Allan | 97ac8ca | 2008-04-29 09:16:05 -0700 | [diff] [blame] | 2357 | |
Bruce Allan | 94d8186 | 2009-11-20 23:25:26 +0000 | [diff] [blame] | 2358 | ret_val = hw->phy.ops.acquire(hw); |
Bruce Allan | 5ccdcec | 2009-10-26 11:24:02 +0000 | [diff] [blame] | 2359 | if (ret_val) |
| 2360 | return ret_val; |
| 2361 | |
Bruce Allan | 97ac8ca | 2008-04-29 09:16:05 -0700 | [diff] [blame] | 2362 | /* Page 800 works differently than the rest so it has its own func */ |
| 2363 | if (page == BM_WUC_PAGE) { |
| 2364 | ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, &data, |
Bruce Allan | 2b6b168 | 2011-05-13 07:20:09 +0000 | [diff] [blame] | 2365 | false, false); |
Bruce Allan | 75ce153 | 2012-02-08 02:54:48 +0000 | [diff] [blame] | 2366 | goto release; |
Bruce Allan | 97ac8ca | 2008-04-29 09:16:05 -0700 | [diff] [blame] | 2367 | } |
| 2368 | |
Bruce Allan | 97ac8ca | 2008-04-29 09:16:05 -0700 | [diff] [blame] | 2369 | hw->phy.addr = e1000_get_phy_addr_for_bm_page(page, offset); |
| 2370 | |
| 2371 | if (offset > MAX_PHY_MULTI_PAGE_REG) { |
Bruce Allan | 90da066 | 2011-01-06 07:02:53 +0000 | [diff] [blame] | 2372 | u32 page_shift, page_select; |
| 2373 | |
Bruce Allan | e921eb1 | 2012-11-28 09:28:37 +0000 | [diff] [blame] | 2374 | /* Page select is register 31 for phy address 1 and 22 for |
Bruce Allan | 97ac8ca | 2008-04-29 09:16:05 -0700 | [diff] [blame] | 2375 | * phy address 2 and 3. Page select is shifted only for |
| 2376 | * phy address 1. |
| 2377 | */ |
| 2378 | if (hw->phy.addr == 1) { |
| 2379 | page_shift = IGP_PAGE_SHIFT; |
| 2380 | page_select = IGP01E1000_PHY_PAGE_SELECT; |
| 2381 | } else { |
| 2382 | page_shift = 0; |
| 2383 | page_select = BM_PHY_PAGE_SELECT; |
| 2384 | } |
| 2385 | |
| 2386 | /* Page is shifted left, PHY expects (page x 32) */ |
| 2387 | ret_val = e1000e_write_phy_reg_mdic(hw, page_select, |
Bruce Allan | f0ff439 | 2013-02-20 04:05:39 +0000 | [diff] [blame] | 2388 | (page << page_shift)); |
Bruce Allan | 5ccdcec | 2009-10-26 11:24:02 +0000 | [diff] [blame] | 2389 | if (ret_val) |
Bruce Allan | 75ce153 | 2012-02-08 02:54:48 +0000 | [diff] [blame] | 2390 | goto release; |
Bruce Allan | 97ac8ca | 2008-04-29 09:16:05 -0700 | [diff] [blame] | 2391 | } |
| 2392 | |
| 2393 | ret_val = e1000e_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset, |
Bruce Allan | f0ff439 | 2013-02-20 04:05:39 +0000 | [diff] [blame] | 2394 | data); |
Bruce Allan | 97ac8ca | 2008-04-29 09:16:05 -0700 | [diff] [blame] | 2395 | |
Bruce Allan | 75ce153 | 2012-02-08 02:54:48 +0000 | [diff] [blame] | 2396 | release: |
Bruce Allan | 94d8186 | 2009-11-20 23:25:26 +0000 | [diff] [blame] | 2397 | hw->phy.ops.release(hw); |
Bruce Allan | 97ac8ca | 2008-04-29 09:16:05 -0700 | [diff] [blame] | 2398 | return ret_val; |
| 2399 | } |
| 2400 | |
| 2401 | /** |
| 2402 | * e1000e_read_phy_reg_bm - Read BM PHY register |
| 2403 | * @hw: pointer to the HW structure |
| 2404 | * @offset: register offset to be read |
| 2405 | * @data: pointer to the read data |
| 2406 | * |
| 2407 | * Acquires semaphore, if necessary, then reads the PHY register at offset |
| 2408 | * and storing the retrieved information in data. Release any acquired |
| 2409 | * semaphores before exiting. |
| 2410 | **/ |
| 2411 | s32 e1000e_read_phy_reg_bm(struct e1000_hw *hw, u32 offset, u16 *data) |
| 2412 | { |
| 2413 | s32 ret_val; |
Bruce Allan | 97ac8ca | 2008-04-29 09:16:05 -0700 | [diff] [blame] | 2414 | u32 page = offset >> IGP_PAGE_SHIFT; |
Bruce Allan | 97ac8ca | 2008-04-29 09:16:05 -0700 | [diff] [blame] | 2415 | |
Bruce Allan | 94d8186 | 2009-11-20 23:25:26 +0000 | [diff] [blame] | 2416 | ret_val = hw->phy.ops.acquire(hw); |
Bruce Allan | 5ccdcec | 2009-10-26 11:24:02 +0000 | [diff] [blame] | 2417 | if (ret_val) |
| 2418 | return ret_val; |
| 2419 | |
Bruce Allan | 97ac8ca | 2008-04-29 09:16:05 -0700 | [diff] [blame] | 2420 | /* Page 800 works differently than the rest so it has its own func */ |
| 2421 | if (page == BM_WUC_PAGE) { |
| 2422 | ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, data, |
Bruce Allan | 2b6b168 | 2011-05-13 07:20:09 +0000 | [diff] [blame] | 2423 | true, false); |
Bruce Allan | 75ce153 | 2012-02-08 02:54:48 +0000 | [diff] [blame] | 2424 | goto release; |
Bruce Allan | 97ac8ca | 2008-04-29 09:16:05 -0700 | [diff] [blame] | 2425 | } |
| 2426 | |
Bruce Allan | 97ac8ca | 2008-04-29 09:16:05 -0700 | [diff] [blame] | 2427 | hw->phy.addr = e1000_get_phy_addr_for_bm_page(page, offset); |
| 2428 | |
| 2429 | if (offset > MAX_PHY_MULTI_PAGE_REG) { |
Bruce Allan | 90da066 | 2011-01-06 07:02:53 +0000 | [diff] [blame] | 2430 | u32 page_shift, page_select; |
| 2431 | |
Bruce Allan | e921eb1 | 2012-11-28 09:28:37 +0000 | [diff] [blame] | 2432 | /* Page select is register 31 for phy address 1 and 22 for |
Bruce Allan | 97ac8ca | 2008-04-29 09:16:05 -0700 | [diff] [blame] | 2433 | * phy address 2 and 3. Page select is shifted only for |
| 2434 | * phy address 1. |
| 2435 | */ |
| 2436 | if (hw->phy.addr == 1) { |
| 2437 | page_shift = IGP_PAGE_SHIFT; |
| 2438 | page_select = IGP01E1000_PHY_PAGE_SELECT; |
| 2439 | } else { |
| 2440 | page_shift = 0; |
| 2441 | page_select = BM_PHY_PAGE_SELECT; |
| 2442 | } |
| 2443 | |
| 2444 | /* Page is shifted left, PHY expects (page x 32) */ |
| 2445 | ret_val = e1000e_write_phy_reg_mdic(hw, page_select, |
Bruce Allan | f0ff439 | 2013-02-20 04:05:39 +0000 | [diff] [blame] | 2446 | (page << page_shift)); |
Bruce Allan | 5ccdcec | 2009-10-26 11:24:02 +0000 | [diff] [blame] | 2447 | if (ret_val) |
Bruce Allan | 75ce153 | 2012-02-08 02:54:48 +0000 | [diff] [blame] | 2448 | goto release; |
Bruce Allan | 97ac8ca | 2008-04-29 09:16:05 -0700 | [diff] [blame] | 2449 | } |
| 2450 | |
| 2451 | ret_val = e1000e_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset, |
Bruce Allan | f0ff439 | 2013-02-20 04:05:39 +0000 | [diff] [blame] | 2452 | data); |
Bruce Allan | 75ce153 | 2012-02-08 02:54:48 +0000 | [diff] [blame] | 2453 | release: |
Bruce Allan | 94d8186 | 2009-11-20 23:25:26 +0000 | [diff] [blame] | 2454 | hw->phy.ops.release(hw); |
Bruce Allan | 97ac8ca | 2008-04-29 09:16:05 -0700 | [diff] [blame] | 2455 | return ret_val; |
| 2456 | } |
| 2457 | |
| 2458 | /** |
Bruce Allan | 4662e82 | 2008-08-26 18:37:06 -0700 | [diff] [blame] | 2459 | * e1000e_read_phy_reg_bm2 - Read BM PHY register |
| 2460 | * @hw: pointer to the HW structure |
| 2461 | * @offset: register offset to be read |
| 2462 | * @data: pointer to the read data |
| 2463 | * |
| 2464 | * Acquires semaphore, if necessary, then reads the PHY register at offset |
| 2465 | * and storing the retrieved information in data. Release any acquired |
| 2466 | * semaphores before exiting. |
| 2467 | **/ |
| 2468 | s32 e1000e_read_phy_reg_bm2(struct e1000_hw *hw, u32 offset, u16 *data) |
| 2469 | { |
| 2470 | s32 ret_val; |
| 2471 | u16 page = (u16)(offset >> IGP_PAGE_SHIFT); |
| 2472 | |
Bruce Allan | 94d8186 | 2009-11-20 23:25:26 +0000 | [diff] [blame] | 2473 | ret_val = hw->phy.ops.acquire(hw); |
Bruce Allan | 5ccdcec | 2009-10-26 11:24:02 +0000 | [diff] [blame] | 2474 | if (ret_val) |
| 2475 | return ret_val; |
| 2476 | |
Bruce Allan | 4662e82 | 2008-08-26 18:37:06 -0700 | [diff] [blame] | 2477 | /* Page 800 works differently than the rest so it has its own func */ |
| 2478 | if (page == BM_WUC_PAGE) { |
| 2479 | ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, data, |
Bruce Allan | 2b6b168 | 2011-05-13 07:20:09 +0000 | [diff] [blame] | 2480 | true, false); |
Bruce Allan | 75ce153 | 2012-02-08 02:54:48 +0000 | [diff] [blame] | 2481 | goto release; |
Bruce Allan | 4662e82 | 2008-08-26 18:37:06 -0700 | [diff] [blame] | 2482 | } |
| 2483 | |
Bruce Allan | 4662e82 | 2008-08-26 18:37:06 -0700 | [diff] [blame] | 2484 | hw->phy.addr = 1; |
| 2485 | |
| 2486 | if (offset > MAX_PHY_MULTI_PAGE_REG) { |
Bruce Allan | 4662e82 | 2008-08-26 18:37:06 -0700 | [diff] [blame] | 2487 | /* Page is shifted left, PHY expects (page x 32) */ |
| 2488 | ret_val = e1000e_write_phy_reg_mdic(hw, BM_PHY_PAGE_SELECT, |
| 2489 | page); |
| 2490 | |
Bruce Allan | 5ccdcec | 2009-10-26 11:24:02 +0000 | [diff] [blame] | 2491 | if (ret_val) |
Bruce Allan | 75ce153 | 2012-02-08 02:54:48 +0000 | [diff] [blame] | 2492 | goto release; |
Bruce Allan | 4662e82 | 2008-08-26 18:37:06 -0700 | [diff] [blame] | 2493 | } |
| 2494 | |
| 2495 | ret_val = e1000e_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset, |
| 2496 | data); |
Bruce Allan | 75ce153 | 2012-02-08 02:54:48 +0000 | [diff] [blame] | 2497 | release: |
Bruce Allan | 94d8186 | 2009-11-20 23:25:26 +0000 | [diff] [blame] | 2498 | hw->phy.ops.release(hw); |
Bruce Allan | 4662e82 | 2008-08-26 18:37:06 -0700 | [diff] [blame] | 2499 | return ret_val; |
| 2500 | } |
| 2501 | |
| 2502 | /** |
| 2503 | * e1000e_write_phy_reg_bm2 - Write BM PHY register |
| 2504 | * @hw: pointer to the HW structure |
| 2505 | * @offset: register offset to write to |
| 2506 | * @data: data to write at register offset |
| 2507 | * |
| 2508 | * Acquires semaphore, if necessary, then writes the data to PHY register |
| 2509 | * at the offset. Release any acquired semaphores before exiting. |
| 2510 | **/ |
| 2511 | s32 e1000e_write_phy_reg_bm2(struct e1000_hw *hw, u32 offset, u16 data) |
| 2512 | { |
| 2513 | s32 ret_val; |
| 2514 | u16 page = (u16)(offset >> IGP_PAGE_SHIFT); |
| 2515 | |
Bruce Allan | 94d8186 | 2009-11-20 23:25:26 +0000 | [diff] [blame] | 2516 | ret_val = hw->phy.ops.acquire(hw); |
Bruce Allan | 5ccdcec | 2009-10-26 11:24:02 +0000 | [diff] [blame] | 2517 | if (ret_val) |
| 2518 | return ret_val; |
| 2519 | |
Bruce Allan | 4662e82 | 2008-08-26 18:37:06 -0700 | [diff] [blame] | 2520 | /* Page 800 works differently than the rest so it has its own func */ |
| 2521 | if (page == BM_WUC_PAGE) { |
| 2522 | ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, &data, |
Bruce Allan | 2b6b168 | 2011-05-13 07:20:09 +0000 | [diff] [blame] | 2523 | false, false); |
Bruce Allan | 75ce153 | 2012-02-08 02:54:48 +0000 | [diff] [blame] | 2524 | goto release; |
Bruce Allan | 4662e82 | 2008-08-26 18:37:06 -0700 | [diff] [blame] | 2525 | } |
| 2526 | |
Bruce Allan | 4662e82 | 2008-08-26 18:37:06 -0700 | [diff] [blame] | 2527 | hw->phy.addr = 1; |
| 2528 | |
| 2529 | if (offset > MAX_PHY_MULTI_PAGE_REG) { |
| 2530 | /* Page is shifted left, PHY expects (page x 32) */ |
| 2531 | ret_val = e1000e_write_phy_reg_mdic(hw, BM_PHY_PAGE_SELECT, |
| 2532 | page); |
| 2533 | |
Bruce Allan | 5ccdcec | 2009-10-26 11:24:02 +0000 | [diff] [blame] | 2534 | if (ret_val) |
Bruce Allan | 75ce153 | 2012-02-08 02:54:48 +0000 | [diff] [blame] | 2535 | goto release; |
Bruce Allan | 4662e82 | 2008-08-26 18:37:06 -0700 | [diff] [blame] | 2536 | } |
| 2537 | |
| 2538 | ret_val = e1000e_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset, |
| 2539 | data); |
| 2540 | |
Bruce Allan | 75ce153 | 2012-02-08 02:54:48 +0000 | [diff] [blame] | 2541 | release: |
Bruce Allan | 94d8186 | 2009-11-20 23:25:26 +0000 | [diff] [blame] | 2542 | hw->phy.ops.release(hw); |
Bruce Allan | 4662e82 | 2008-08-26 18:37:06 -0700 | [diff] [blame] | 2543 | return ret_val; |
| 2544 | } |
| 2545 | |
| 2546 | /** |
Bruce Allan | 2b6b168 | 2011-05-13 07:20:09 +0000 | [diff] [blame] | 2547 | * e1000_enable_phy_wakeup_reg_access_bm - enable access to BM wakeup registers |
| 2548 | * @hw: pointer to the HW structure |
| 2549 | * @phy_reg: pointer to store original contents of BM_WUC_ENABLE_REG |
| 2550 | * |
| 2551 | * Assumes semaphore already acquired and phy_reg points to a valid memory |
| 2552 | * address to store contents of the BM_WUC_ENABLE_REG register. |
| 2553 | **/ |
| 2554 | s32 e1000_enable_phy_wakeup_reg_access_bm(struct e1000_hw *hw, u16 *phy_reg) |
| 2555 | { |
| 2556 | s32 ret_val; |
| 2557 | u16 temp; |
| 2558 | |
| 2559 | /* All page select, port ctrl and wakeup registers use phy address 1 */ |
| 2560 | hw->phy.addr = 1; |
| 2561 | |
| 2562 | /* Select Port Control Registers page */ |
| 2563 | ret_val = e1000_set_page_igp(hw, (BM_PORT_CTRL_PAGE << IGP_PAGE_SHIFT)); |
| 2564 | if (ret_val) { |
| 2565 | e_dbg("Could not set Port Control page\n"); |
Bruce Allan | 5015e53 | 2012-02-08 02:55:56 +0000 | [diff] [blame] | 2566 | return ret_val; |
Bruce Allan | 2b6b168 | 2011-05-13 07:20:09 +0000 | [diff] [blame] | 2567 | } |
| 2568 | |
| 2569 | ret_val = e1000e_read_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, phy_reg); |
| 2570 | if (ret_val) { |
| 2571 | e_dbg("Could not read PHY register %d.%d\n", |
| 2572 | BM_PORT_CTRL_PAGE, BM_WUC_ENABLE_REG); |
Bruce Allan | 5015e53 | 2012-02-08 02:55:56 +0000 | [diff] [blame] | 2573 | return ret_val; |
Bruce Allan | 2b6b168 | 2011-05-13 07:20:09 +0000 | [diff] [blame] | 2574 | } |
| 2575 | |
Bruce Allan | e921eb1 | 2012-11-28 09:28:37 +0000 | [diff] [blame] | 2576 | /* Enable both PHY wakeup mode and Wakeup register page writes. |
Bruce Allan | 2b6b168 | 2011-05-13 07:20:09 +0000 | [diff] [blame] | 2577 | * Prevent a power state change by disabling ME and Host PHY wakeup. |
| 2578 | */ |
| 2579 | temp = *phy_reg; |
| 2580 | temp |= BM_WUC_ENABLE_BIT; |
| 2581 | temp &= ~(BM_WUC_ME_WU_BIT | BM_WUC_HOST_WU_BIT); |
| 2582 | |
| 2583 | ret_val = e1000e_write_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, temp); |
| 2584 | if (ret_val) { |
| 2585 | e_dbg("Could not write PHY register %d.%d\n", |
| 2586 | BM_PORT_CTRL_PAGE, BM_WUC_ENABLE_REG); |
Bruce Allan | 5015e53 | 2012-02-08 02:55:56 +0000 | [diff] [blame] | 2587 | return ret_val; |
Bruce Allan | 2b6b168 | 2011-05-13 07:20:09 +0000 | [diff] [blame] | 2588 | } |
| 2589 | |
Bruce Allan | e921eb1 | 2012-11-28 09:28:37 +0000 | [diff] [blame] | 2590 | /* Select Host Wakeup Registers page - caller now able to write |
Bruce Allan | 5015e53 | 2012-02-08 02:55:56 +0000 | [diff] [blame] | 2591 | * registers on the Wakeup registers page |
| 2592 | */ |
| 2593 | return e1000_set_page_igp(hw, (BM_WUC_PAGE << IGP_PAGE_SHIFT)); |
Bruce Allan | 2b6b168 | 2011-05-13 07:20:09 +0000 | [diff] [blame] | 2594 | } |
| 2595 | |
| 2596 | /** |
| 2597 | * e1000_disable_phy_wakeup_reg_access_bm - disable access to BM wakeup regs |
| 2598 | * @hw: pointer to the HW structure |
| 2599 | * @phy_reg: pointer to original contents of BM_WUC_ENABLE_REG |
| 2600 | * |
| 2601 | * Restore BM_WUC_ENABLE_REG to its original value. |
| 2602 | * |
| 2603 | * Assumes semaphore already acquired and *phy_reg is the contents of the |
| 2604 | * BM_WUC_ENABLE_REG before register(s) on BM_WUC_PAGE were accessed by |
| 2605 | * caller. |
| 2606 | **/ |
| 2607 | s32 e1000_disable_phy_wakeup_reg_access_bm(struct e1000_hw *hw, u16 *phy_reg) |
| 2608 | { |
Bruce Allan | 70806a7 | 2013-01-05 05:08:37 +0000 | [diff] [blame] | 2609 | s32 ret_val; |
Bruce Allan | 2b6b168 | 2011-05-13 07:20:09 +0000 | [diff] [blame] | 2610 | |
| 2611 | /* Select Port Control Registers page */ |
| 2612 | ret_val = e1000_set_page_igp(hw, (BM_PORT_CTRL_PAGE << IGP_PAGE_SHIFT)); |
| 2613 | if (ret_val) { |
| 2614 | e_dbg("Could not set Port Control page\n"); |
Bruce Allan | 5015e53 | 2012-02-08 02:55:56 +0000 | [diff] [blame] | 2615 | return ret_val; |
Bruce Allan | 2b6b168 | 2011-05-13 07:20:09 +0000 | [diff] [blame] | 2616 | } |
| 2617 | |
| 2618 | /* Restore 769.17 to its original value */ |
| 2619 | ret_val = e1000e_write_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, *phy_reg); |
| 2620 | if (ret_val) |
| 2621 | e_dbg("Could not restore PHY register %d.%d\n", |
| 2622 | BM_PORT_CTRL_PAGE, BM_WUC_ENABLE_REG); |
Bruce Allan | 5015e53 | 2012-02-08 02:55:56 +0000 | [diff] [blame] | 2623 | |
Bruce Allan | 2b6b168 | 2011-05-13 07:20:09 +0000 | [diff] [blame] | 2624 | return ret_val; |
| 2625 | } |
| 2626 | |
| 2627 | /** |
| 2628 | * e1000_access_phy_wakeup_reg_bm - Read/write BM PHY wakeup register |
Bruce Allan | 97ac8ca | 2008-04-29 09:16:05 -0700 | [diff] [blame] | 2629 | * @hw: pointer to the HW structure |
| 2630 | * @offset: register offset to be read or written |
| 2631 | * @data: pointer to the data to read or write |
| 2632 | * @read: determines if operation is read or write |
Bruce Allan | 2b6b168 | 2011-05-13 07:20:09 +0000 | [diff] [blame] | 2633 | * @page_set: BM_WUC_PAGE already set and access enabled |
Bruce Allan | 97ac8ca | 2008-04-29 09:16:05 -0700 | [diff] [blame] | 2634 | * |
Bruce Allan | 2b6b168 | 2011-05-13 07:20:09 +0000 | [diff] [blame] | 2635 | * Read the PHY register at offset and store the retrieved information in |
| 2636 | * data, or write data to PHY register at offset. Note the procedure to |
| 2637 | * access the PHY wakeup registers is different than reading the other PHY |
| 2638 | * registers. It works as such: |
| 2639 | * 1) Set 769.17.2 (page 769, register 17, bit 2) = 1 |
Bruce Allan | 97ac8ca | 2008-04-29 09:16:05 -0700 | [diff] [blame] | 2640 | * 2) Set page to 800 for host (801 if we were manageability) |
| 2641 | * 3) Write the address using the address opcode (0x11) |
| 2642 | * 4) Read or write the data using the data opcode (0x12) |
Bruce Allan | 2b6b168 | 2011-05-13 07:20:09 +0000 | [diff] [blame] | 2643 | * 5) Restore 769.17.2 to its original value |
Bruce Allan | 5ccdcec | 2009-10-26 11:24:02 +0000 | [diff] [blame] | 2644 | * |
Bruce Allan | 2b6b168 | 2011-05-13 07:20:09 +0000 | [diff] [blame] | 2645 | * Steps 1 and 2 are done by e1000_enable_phy_wakeup_reg_access_bm() and |
| 2646 | * step 5 is done by e1000_disable_phy_wakeup_reg_access_bm(). |
| 2647 | * |
| 2648 | * Assumes semaphore is already acquired. When page_set==true, assumes |
| 2649 | * the PHY page is set to BM_WUC_PAGE (i.e. a function in the call stack |
| 2650 | * is responsible for calls to e1000_[enable|disable]_phy_wakeup_reg_bm()). |
Bruce Allan | 97ac8ca | 2008-04-29 09:16:05 -0700 | [diff] [blame] | 2651 | **/ |
| 2652 | static s32 e1000_access_phy_wakeup_reg_bm(struct e1000_hw *hw, u32 offset, |
Bruce Allan | 2b6b168 | 2011-05-13 07:20:09 +0000 | [diff] [blame] | 2653 | u16 *data, bool read, bool page_set) |
Bruce Allan | 97ac8ca | 2008-04-29 09:16:05 -0700 | [diff] [blame] | 2654 | { |
| 2655 | s32 ret_val; |
Bruce Allan | a4f58f5 | 2009-06-02 11:29:18 +0000 | [diff] [blame] | 2656 | u16 reg = BM_PHY_REG_NUM(offset); |
Bruce Allan | 2b6b168 | 2011-05-13 07:20:09 +0000 | [diff] [blame] | 2657 | u16 page = BM_PHY_REG_PAGE(offset); |
Bruce Allan | 97ac8ca | 2008-04-29 09:16:05 -0700 | [diff] [blame] | 2658 | u16 phy_reg = 0; |
Bruce Allan | 97ac8ca | 2008-04-29 09:16:05 -0700 | [diff] [blame] | 2659 | |
Bruce Allan | 2b6b168 | 2011-05-13 07:20:09 +0000 | [diff] [blame] | 2660 | /* Gig must be disabled for MDIO accesses to Host Wakeup reg page */ |
Bruce Allan | a4f58f5 | 2009-06-02 11:29:18 +0000 | [diff] [blame] | 2661 | if ((hw->mac.type == e1000_pchlan) && |
Bruce Allan | 2b6b168 | 2011-05-13 07:20:09 +0000 | [diff] [blame] | 2662 | (!(er32(PHY_CTRL) & E1000_PHY_CTRL_GBE_DISABLE))) |
| 2663 | e_dbg("Attempting to access page %d while gig enabled.\n", |
| 2664 | page); |
Bruce Allan | a4f58f5 | 2009-06-02 11:29:18 +0000 | [diff] [blame] | 2665 | |
Bruce Allan | 2b6b168 | 2011-05-13 07:20:09 +0000 | [diff] [blame] | 2666 | if (!page_set) { |
| 2667 | /* Enable access to PHY wakeup registers */ |
| 2668 | ret_val = e1000_enable_phy_wakeup_reg_access_bm(hw, &phy_reg); |
| 2669 | if (ret_val) { |
| 2670 | e_dbg("Could not enable PHY wakeup reg access\n"); |
Bruce Allan | 5015e53 | 2012-02-08 02:55:56 +0000 | [diff] [blame] | 2671 | return ret_val; |
Bruce Allan | 2b6b168 | 2011-05-13 07:20:09 +0000 | [diff] [blame] | 2672 | } |
Bruce Allan | 9b71b41 | 2009-12-01 15:53:07 +0000 | [diff] [blame] | 2673 | } |
Bruce Allan | 97ac8ca | 2008-04-29 09:16:05 -0700 | [diff] [blame] | 2674 | |
Bruce Allan | 2b6b168 | 2011-05-13 07:20:09 +0000 | [diff] [blame] | 2675 | e_dbg("Accessing PHY page %d reg 0x%x\n", page, reg); |
Bruce Allan | 97ac8ca | 2008-04-29 09:16:05 -0700 | [diff] [blame] | 2676 | |
Bruce Allan | 2b6b168 | 2011-05-13 07:20:09 +0000 | [diff] [blame] | 2677 | /* Write the Wakeup register page offset value using opcode 0x11 */ |
Bruce Allan | 97ac8ca | 2008-04-29 09:16:05 -0700 | [diff] [blame] | 2678 | ret_val = e1000e_write_phy_reg_mdic(hw, BM_WUC_ADDRESS_OPCODE, reg); |
Bruce Allan | 9b71b41 | 2009-12-01 15:53:07 +0000 | [diff] [blame] | 2679 | if (ret_val) { |
Bruce Allan | 2b6b168 | 2011-05-13 07:20:09 +0000 | [diff] [blame] | 2680 | e_dbg("Could not write address opcode to page %d\n", page); |
Bruce Allan | 5015e53 | 2012-02-08 02:55:56 +0000 | [diff] [blame] | 2681 | return ret_val; |
Bruce Allan | 9b71b41 | 2009-12-01 15:53:07 +0000 | [diff] [blame] | 2682 | } |
Bruce Allan | 97ac8ca | 2008-04-29 09:16:05 -0700 | [diff] [blame] | 2683 | |
| 2684 | if (read) { |
Bruce Allan | 2b6b168 | 2011-05-13 07:20:09 +0000 | [diff] [blame] | 2685 | /* Read the Wakeup register page value using opcode 0x12 */ |
Bruce Allan | 97ac8ca | 2008-04-29 09:16:05 -0700 | [diff] [blame] | 2686 | ret_val = e1000e_read_phy_reg_mdic(hw, BM_WUC_DATA_OPCODE, |
Bruce Allan | f0ff439 | 2013-02-20 04:05:39 +0000 | [diff] [blame] | 2687 | data); |
Bruce Allan | 97ac8ca | 2008-04-29 09:16:05 -0700 | [diff] [blame] | 2688 | } else { |
Bruce Allan | 2b6b168 | 2011-05-13 07:20:09 +0000 | [diff] [blame] | 2689 | /* Write the Wakeup register page value using opcode 0x12 */ |
Bruce Allan | 97ac8ca | 2008-04-29 09:16:05 -0700 | [diff] [blame] | 2690 | ret_val = e1000e_write_phy_reg_mdic(hw, BM_WUC_DATA_OPCODE, |
| 2691 | *data); |
| 2692 | } |
| 2693 | |
Bruce Allan | 9b71b41 | 2009-12-01 15:53:07 +0000 | [diff] [blame] | 2694 | if (ret_val) { |
Bruce Allan | 2b6b168 | 2011-05-13 07:20:09 +0000 | [diff] [blame] | 2695 | e_dbg("Could not access PHY reg %d.%d\n", page, reg); |
Bruce Allan | 5015e53 | 2012-02-08 02:55:56 +0000 | [diff] [blame] | 2696 | return ret_val; |
Bruce Allan | 9b71b41 | 2009-12-01 15:53:07 +0000 | [diff] [blame] | 2697 | } |
Bruce Allan | 97ac8ca | 2008-04-29 09:16:05 -0700 | [diff] [blame] | 2698 | |
Bruce Allan | 2b6b168 | 2011-05-13 07:20:09 +0000 | [diff] [blame] | 2699 | if (!page_set) |
| 2700 | ret_val = e1000_disable_phy_wakeup_reg_access_bm(hw, &phy_reg); |
Bruce Allan | 97ac8ca | 2008-04-29 09:16:05 -0700 | [diff] [blame] | 2701 | |
Bruce Allan | 97ac8ca | 2008-04-29 09:16:05 -0700 | [diff] [blame] | 2702 | return ret_val; |
| 2703 | } |
| 2704 | |
| 2705 | /** |
Bruce Allan | 17f208d | 2009-12-01 15:47:22 +0000 | [diff] [blame] | 2706 | * e1000_power_up_phy_copper - Restore copper link in case of PHY power down |
| 2707 | * @hw: pointer to the HW structure |
| 2708 | * |
| 2709 | * In the case of a PHY power down to save power, or to turn off link during a |
| 2710 | * driver unload, or wake on lan is not enabled, restore the link to previous |
| 2711 | * settings. |
| 2712 | **/ |
| 2713 | void e1000_power_up_phy_copper(struct e1000_hw *hw) |
| 2714 | { |
| 2715 | u16 mii_reg = 0; |
| 2716 | |
| 2717 | /* The PHY will retain its settings across a power down/up cycle */ |
Bruce Allan | c2ade1a | 2013-01-16 08:54:35 +0000 | [diff] [blame] | 2718 | e1e_rphy(hw, MII_BMCR, &mii_reg); |
| 2719 | mii_reg &= ~BMCR_PDOWN; |
| 2720 | e1e_wphy(hw, MII_BMCR, mii_reg); |
Bruce Allan | 17f208d | 2009-12-01 15:47:22 +0000 | [diff] [blame] | 2721 | } |
| 2722 | |
| 2723 | /** |
| 2724 | * e1000_power_down_phy_copper - Restore copper link in case of PHY power down |
| 2725 | * @hw: pointer to the HW structure |
| 2726 | * |
| 2727 | * In the case of a PHY power down to save power, or to turn off link during a |
| 2728 | * driver unload, or wake on lan is not enabled, restore the link to previous |
| 2729 | * settings. |
| 2730 | **/ |
| 2731 | void e1000_power_down_phy_copper(struct e1000_hw *hw) |
| 2732 | { |
| 2733 | u16 mii_reg = 0; |
| 2734 | |
| 2735 | /* The PHY will retain its settings across a power down/up cycle */ |
Bruce Allan | c2ade1a | 2013-01-16 08:54:35 +0000 | [diff] [blame] | 2736 | e1e_rphy(hw, MII_BMCR, &mii_reg); |
| 2737 | mii_reg |= BMCR_PDOWN; |
| 2738 | e1e_wphy(hw, MII_BMCR, mii_reg); |
Bruce Allan | 1bba438 | 2011-03-19 00:27:20 +0000 | [diff] [blame] | 2739 | usleep_range(1000, 2000); |
Bruce Allan | 17f208d | 2009-12-01 15:47:22 +0000 | [diff] [blame] | 2740 | } |
| 2741 | |
| 2742 | /** |
Bruce Allan | 5ccdcec | 2009-10-26 11:24:02 +0000 | [diff] [blame] | 2743 | * __e1000_read_phy_reg_hv - Read HV PHY register |
Bruce Allan | a4f58f5 | 2009-06-02 11:29:18 +0000 | [diff] [blame] | 2744 | * @hw: pointer to the HW structure |
| 2745 | * @offset: register offset to be read |
| 2746 | * @data: pointer to the read data |
Bruce Allan | 5ccdcec | 2009-10-26 11:24:02 +0000 | [diff] [blame] | 2747 | * @locked: semaphore has already been acquired or not |
Bruce Allan | a4f58f5 | 2009-06-02 11:29:18 +0000 | [diff] [blame] | 2748 | * |
| 2749 | * Acquires semaphore, if necessary, then reads the PHY register at offset |
Bruce Allan | 5ccdcec | 2009-10-26 11:24:02 +0000 | [diff] [blame] | 2750 | * and stores the retrieved information in data. Release any acquired |
Bruce Allan | a4f58f5 | 2009-06-02 11:29:18 +0000 | [diff] [blame] | 2751 | * semaphore before exiting. |
| 2752 | **/ |
Bruce Allan | 5ccdcec | 2009-10-26 11:24:02 +0000 | [diff] [blame] | 2753 | static s32 __e1000_read_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 *data, |
Bruce Allan | 2b6b168 | 2011-05-13 07:20:09 +0000 | [diff] [blame] | 2754 | bool locked, bool page_set) |
Bruce Allan | a4f58f5 | 2009-06-02 11:29:18 +0000 | [diff] [blame] | 2755 | { |
| 2756 | s32 ret_val; |
| 2757 | u16 page = BM_PHY_REG_PAGE(offset); |
| 2758 | u16 reg = BM_PHY_REG_NUM(offset); |
Bruce Allan | 2b6b168 | 2011-05-13 07:20:09 +0000 | [diff] [blame] | 2759 | u32 phy_addr = hw->phy.addr = e1000_get_phy_addr_for_hv_page(page); |
Bruce Allan | a4f58f5 | 2009-06-02 11:29:18 +0000 | [diff] [blame] | 2760 | |
Bruce Allan | 5ccdcec | 2009-10-26 11:24:02 +0000 | [diff] [blame] | 2761 | if (!locked) { |
Bruce Allan | 94d8186 | 2009-11-20 23:25:26 +0000 | [diff] [blame] | 2762 | ret_val = hw->phy.ops.acquire(hw); |
Bruce Allan | 5ccdcec | 2009-10-26 11:24:02 +0000 | [diff] [blame] | 2763 | if (ret_val) |
| 2764 | return ret_val; |
| 2765 | } |
| 2766 | |
Bruce Allan | a4f58f5 | 2009-06-02 11:29:18 +0000 | [diff] [blame] | 2767 | /* Page 800 works differently than the rest so it has its own func */ |
| 2768 | if (page == BM_WUC_PAGE) { |
Bruce Allan | 2b6b168 | 2011-05-13 07:20:09 +0000 | [diff] [blame] | 2769 | ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, data, |
| 2770 | true, page_set); |
Bruce Allan | a4f58f5 | 2009-06-02 11:29:18 +0000 | [diff] [blame] | 2771 | goto out; |
| 2772 | } |
| 2773 | |
| 2774 | if (page > 0 && page < HV_INTC_FC_PAGE_START) { |
| 2775 | ret_val = e1000_access_phy_debug_regs_hv(hw, offset, |
Bruce Allan | f0ff439 | 2013-02-20 04:05:39 +0000 | [diff] [blame] | 2776 | data, true); |
Bruce Allan | a4f58f5 | 2009-06-02 11:29:18 +0000 | [diff] [blame] | 2777 | goto out; |
| 2778 | } |
| 2779 | |
Bruce Allan | 2b6b168 | 2011-05-13 07:20:09 +0000 | [diff] [blame] | 2780 | if (!page_set) { |
| 2781 | if (page == HV_INTC_FC_PAGE_START) |
| 2782 | page = 0; |
Bruce Allan | a4f58f5 | 2009-06-02 11:29:18 +0000 | [diff] [blame] | 2783 | |
Bruce Allan | 2b6b168 | 2011-05-13 07:20:09 +0000 | [diff] [blame] | 2784 | if (reg > MAX_PHY_MULTI_PAGE_REG) { |
| 2785 | /* Page is shifted left, PHY expects (page x 32) */ |
| 2786 | ret_val = e1000_set_page_igp(hw, |
| 2787 | (page << IGP_PAGE_SHIFT)); |
Bruce Allan | a4f58f5 | 2009-06-02 11:29:18 +0000 | [diff] [blame] | 2788 | |
Bruce Allan | 2b6b168 | 2011-05-13 07:20:09 +0000 | [diff] [blame] | 2789 | hw->phy.addr = phy_addr; |
Bruce Allan | a4f58f5 | 2009-06-02 11:29:18 +0000 | [diff] [blame] | 2790 | |
Bruce Allan | 2b6b168 | 2011-05-13 07:20:09 +0000 | [diff] [blame] | 2791 | if (ret_val) |
| 2792 | goto out; |
| 2793 | } |
Bruce Allan | a4f58f5 | 2009-06-02 11:29:18 +0000 | [diff] [blame] | 2794 | } |
| 2795 | |
Bruce Allan | 2b6b168 | 2011-05-13 07:20:09 +0000 | [diff] [blame] | 2796 | e_dbg("reading PHY page %d (or 0x%x shifted) reg 0x%x\n", page, |
| 2797 | page << IGP_PAGE_SHIFT, reg); |
| 2798 | |
Bruce Allan | f0ff439 | 2013-02-20 04:05:39 +0000 | [diff] [blame] | 2799 | ret_val = e1000e_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & reg, data); |
Bruce Allan | a4f58f5 | 2009-06-02 11:29:18 +0000 | [diff] [blame] | 2800 | out: |
Bruce Allan | 5ccdcec | 2009-10-26 11:24:02 +0000 | [diff] [blame] | 2801 | if (!locked) |
Bruce Allan | 94d8186 | 2009-11-20 23:25:26 +0000 | [diff] [blame] | 2802 | hw->phy.ops.release(hw); |
Bruce Allan | 5ccdcec | 2009-10-26 11:24:02 +0000 | [diff] [blame] | 2803 | |
Bruce Allan | a4f58f5 | 2009-06-02 11:29:18 +0000 | [diff] [blame] | 2804 | return ret_val; |
| 2805 | } |
| 2806 | |
| 2807 | /** |
Bruce Allan | 5ccdcec | 2009-10-26 11:24:02 +0000 | [diff] [blame] | 2808 | * e1000_read_phy_reg_hv - Read HV PHY register |
| 2809 | * @hw: pointer to the HW structure |
| 2810 | * @offset: register offset to be read |
| 2811 | * @data: pointer to the read data |
| 2812 | * |
| 2813 | * Acquires semaphore then reads the PHY register at offset and stores |
| 2814 | * the retrieved information in data. Release the acquired semaphore |
| 2815 | * before exiting. |
| 2816 | **/ |
| 2817 | s32 e1000_read_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 *data) |
| 2818 | { |
Bruce Allan | 2b6b168 | 2011-05-13 07:20:09 +0000 | [diff] [blame] | 2819 | return __e1000_read_phy_reg_hv(hw, offset, data, false, false); |
Bruce Allan | 5ccdcec | 2009-10-26 11:24:02 +0000 | [diff] [blame] | 2820 | } |
| 2821 | |
| 2822 | /** |
| 2823 | * e1000_read_phy_reg_hv_locked - Read HV PHY register |
| 2824 | * @hw: pointer to the HW structure |
| 2825 | * @offset: register offset to be read |
| 2826 | * @data: pointer to the read data |
| 2827 | * |
| 2828 | * Reads the PHY register at offset and stores the retrieved information |
| 2829 | * in data. Assumes semaphore already acquired. |
| 2830 | **/ |
| 2831 | s32 e1000_read_phy_reg_hv_locked(struct e1000_hw *hw, u32 offset, u16 *data) |
| 2832 | { |
Bruce Allan | 2b6b168 | 2011-05-13 07:20:09 +0000 | [diff] [blame] | 2833 | return __e1000_read_phy_reg_hv(hw, offset, data, true, false); |
| 2834 | } |
| 2835 | |
| 2836 | /** |
| 2837 | * e1000_read_phy_reg_page_hv - Read HV PHY register |
| 2838 | * @hw: pointer to the HW structure |
| 2839 | * @offset: register offset to write to |
| 2840 | * @data: data to write at register offset |
| 2841 | * |
| 2842 | * Reads the PHY register at offset and stores the retrieved information |
| 2843 | * in data. Assumes semaphore already acquired and page already set. |
| 2844 | **/ |
| 2845 | s32 e1000_read_phy_reg_page_hv(struct e1000_hw *hw, u32 offset, u16 *data) |
| 2846 | { |
| 2847 | return __e1000_read_phy_reg_hv(hw, offset, data, true, true); |
Bruce Allan | 5ccdcec | 2009-10-26 11:24:02 +0000 | [diff] [blame] | 2848 | } |
| 2849 | |
| 2850 | /** |
| 2851 | * __e1000_write_phy_reg_hv - Write HV PHY register |
Bruce Allan | a4f58f5 | 2009-06-02 11:29:18 +0000 | [diff] [blame] | 2852 | * @hw: pointer to the HW structure |
| 2853 | * @offset: register offset to write to |
| 2854 | * @data: data to write at register offset |
Bruce Allan | 5ccdcec | 2009-10-26 11:24:02 +0000 | [diff] [blame] | 2855 | * @locked: semaphore has already been acquired or not |
Bruce Allan | a4f58f5 | 2009-06-02 11:29:18 +0000 | [diff] [blame] | 2856 | * |
| 2857 | * Acquires semaphore, if necessary, then writes the data to PHY register |
| 2858 | * at the offset. Release any acquired semaphores before exiting. |
| 2859 | **/ |
Bruce Allan | 5ccdcec | 2009-10-26 11:24:02 +0000 | [diff] [blame] | 2860 | static s32 __e1000_write_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 data, |
Bruce Allan | 2b6b168 | 2011-05-13 07:20:09 +0000 | [diff] [blame] | 2861 | bool locked, bool page_set) |
Bruce Allan | a4f58f5 | 2009-06-02 11:29:18 +0000 | [diff] [blame] | 2862 | { |
| 2863 | s32 ret_val; |
| 2864 | u16 page = BM_PHY_REG_PAGE(offset); |
| 2865 | u16 reg = BM_PHY_REG_NUM(offset); |
Bruce Allan | 2b6b168 | 2011-05-13 07:20:09 +0000 | [diff] [blame] | 2866 | u32 phy_addr = hw->phy.addr = e1000_get_phy_addr_for_hv_page(page); |
Bruce Allan | a4f58f5 | 2009-06-02 11:29:18 +0000 | [diff] [blame] | 2867 | |
Bruce Allan | 5ccdcec | 2009-10-26 11:24:02 +0000 | [diff] [blame] | 2868 | if (!locked) { |
Bruce Allan | 94d8186 | 2009-11-20 23:25:26 +0000 | [diff] [blame] | 2869 | ret_val = hw->phy.ops.acquire(hw); |
Bruce Allan | 5ccdcec | 2009-10-26 11:24:02 +0000 | [diff] [blame] | 2870 | if (ret_val) |
| 2871 | return ret_val; |
| 2872 | } |
| 2873 | |
Bruce Allan | a4f58f5 | 2009-06-02 11:29:18 +0000 | [diff] [blame] | 2874 | /* Page 800 works differently than the rest so it has its own func */ |
| 2875 | if (page == BM_WUC_PAGE) { |
Bruce Allan | 2b6b168 | 2011-05-13 07:20:09 +0000 | [diff] [blame] | 2876 | ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, &data, |
| 2877 | false, page_set); |
Bruce Allan | a4f58f5 | 2009-06-02 11:29:18 +0000 | [diff] [blame] | 2878 | goto out; |
| 2879 | } |
| 2880 | |
| 2881 | if (page > 0 && page < HV_INTC_FC_PAGE_START) { |
| 2882 | ret_val = e1000_access_phy_debug_regs_hv(hw, offset, |
Bruce Allan | f0ff439 | 2013-02-20 04:05:39 +0000 | [diff] [blame] | 2883 | &data, false); |
Bruce Allan | a4f58f5 | 2009-06-02 11:29:18 +0000 | [diff] [blame] | 2884 | goto out; |
| 2885 | } |
| 2886 | |
Bruce Allan | 2b6b168 | 2011-05-13 07:20:09 +0000 | [diff] [blame] | 2887 | if (!page_set) { |
| 2888 | if (page == HV_INTC_FC_PAGE_START) |
| 2889 | page = 0; |
Bruce Allan | a4f58f5 | 2009-06-02 11:29:18 +0000 | [diff] [blame] | 2890 | |
Bruce Allan | e921eb1 | 2012-11-28 09:28:37 +0000 | [diff] [blame] | 2891 | /* Workaround MDIO accesses being disabled after entering IEEE |
Bruce Allan | 2b6b168 | 2011-05-13 07:20:09 +0000 | [diff] [blame] | 2892 | * Power Down (when bit 11 of the PHY Control register is set) |
| 2893 | */ |
| 2894 | if ((hw->phy.type == e1000_phy_82578) && |
| 2895 | (hw->phy.revision >= 1) && |
| 2896 | (hw->phy.addr == 2) && |
Bruce Allan | 04499ec | 2012-04-13 00:08:31 +0000 | [diff] [blame] | 2897 | !(MAX_PHY_REG_ADDRESS & reg) && (data & (1 << 11))) { |
Bruce Allan | 2b6b168 | 2011-05-13 07:20:09 +0000 | [diff] [blame] | 2898 | u16 data2 = 0x7EFF; |
David Ertman | 6cf08d1 | 2014-04-05 06:07:00 +0000 | [diff] [blame] | 2899 | |
Bruce Allan | 2b6b168 | 2011-05-13 07:20:09 +0000 | [diff] [blame] | 2900 | ret_val = e1000_access_phy_debug_regs_hv(hw, |
| 2901 | (1 << 6) | 0x3, |
| 2902 | &data2, false); |
| 2903 | if (ret_val) |
| 2904 | goto out; |
| 2905 | } |
Bruce Allan | a4f58f5 | 2009-06-02 11:29:18 +0000 | [diff] [blame] | 2906 | |
Bruce Allan | 2b6b168 | 2011-05-13 07:20:09 +0000 | [diff] [blame] | 2907 | if (reg > MAX_PHY_MULTI_PAGE_REG) { |
| 2908 | /* Page is shifted left, PHY expects (page x 32) */ |
| 2909 | ret_val = e1000_set_page_igp(hw, |
| 2910 | (page << IGP_PAGE_SHIFT)); |
| 2911 | |
| 2912 | hw->phy.addr = phy_addr; |
| 2913 | |
| 2914 | if (ret_val) |
| 2915 | goto out; |
| 2916 | } |
Bruce Allan | a4f58f5 | 2009-06-02 11:29:18 +0000 | [diff] [blame] | 2917 | } |
| 2918 | |
Bruce Allan | 2b6b168 | 2011-05-13 07:20:09 +0000 | [diff] [blame] | 2919 | e_dbg("writing PHY page %d (or 0x%x shifted) reg 0x%x\n", page, |
| 2920 | page << IGP_PAGE_SHIFT, reg); |
Bruce Allan | a4f58f5 | 2009-06-02 11:29:18 +0000 | [diff] [blame] | 2921 | |
| 2922 | ret_val = e1000e_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & reg, |
Bruce Allan | f0ff439 | 2013-02-20 04:05:39 +0000 | [diff] [blame] | 2923 | data); |
Bruce Allan | a4f58f5 | 2009-06-02 11:29:18 +0000 | [diff] [blame] | 2924 | |
| 2925 | out: |
Bruce Allan | 5ccdcec | 2009-10-26 11:24:02 +0000 | [diff] [blame] | 2926 | if (!locked) |
Bruce Allan | 94d8186 | 2009-11-20 23:25:26 +0000 | [diff] [blame] | 2927 | hw->phy.ops.release(hw); |
Bruce Allan | 5ccdcec | 2009-10-26 11:24:02 +0000 | [diff] [blame] | 2928 | |
Bruce Allan | a4f58f5 | 2009-06-02 11:29:18 +0000 | [diff] [blame] | 2929 | return ret_val; |
| 2930 | } |
| 2931 | |
| 2932 | /** |
Bruce Allan | 5ccdcec | 2009-10-26 11:24:02 +0000 | [diff] [blame] | 2933 | * e1000_write_phy_reg_hv - Write HV PHY register |
| 2934 | * @hw: pointer to the HW structure |
| 2935 | * @offset: register offset to write to |
| 2936 | * @data: data to write at register offset |
| 2937 | * |
| 2938 | * Acquires semaphore then writes the data to PHY register at the offset. |
| 2939 | * Release the acquired semaphores before exiting. |
| 2940 | **/ |
| 2941 | s32 e1000_write_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 data) |
| 2942 | { |
Bruce Allan | 2b6b168 | 2011-05-13 07:20:09 +0000 | [diff] [blame] | 2943 | return __e1000_write_phy_reg_hv(hw, offset, data, false, false); |
Bruce Allan | 5ccdcec | 2009-10-26 11:24:02 +0000 | [diff] [blame] | 2944 | } |
| 2945 | |
| 2946 | /** |
| 2947 | * e1000_write_phy_reg_hv_locked - Write HV PHY register |
| 2948 | * @hw: pointer to the HW structure |
| 2949 | * @offset: register offset to write to |
| 2950 | * @data: data to write at register offset |
| 2951 | * |
| 2952 | * Writes the data to PHY register at the offset. Assumes semaphore |
| 2953 | * already acquired. |
| 2954 | **/ |
| 2955 | s32 e1000_write_phy_reg_hv_locked(struct e1000_hw *hw, u32 offset, u16 data) |
| 2956 | { |
Bruce Allan | 2b6b168 | 2011-05-13 07:20:09 +0000 | [diff] [blame] | 2957 | return __e1000_write_phy_reg_hv(hw, offset, data, true, false); |
| 2958 | } |
| 2959 | |
| 2960 | /** |
| 2961 | * e1000_write_phy_reg_page_hv - Write HV PHY register |
| 2962 | * @hw: pointer to the HW structure |
| 2963 | * @offset: register offset to write to |
| 2964 | * @data: data to write at register offset |
| 2965 | * |
| 2966 | * Writes the data to PHY register at the offset. Assumes semaphore |
| 2967 | * already acquired and page already set. |
| 2968 | **/ |
| 2969 | s32 e1000_write_phy_reg_page_hv(struct e1000_hw *hw, u32 offset, u16 data) |
| 2970 | { |
| 2971 | return __e1000_write_phy_reg_hv(hw, offset, data, true, true); |
Bruce Allan | 5ccdcec | 2009-10-26 11:24:02 +0000 | [diff] [blame] | 2972 | } |
| 2973 | |
| 2974 | /** |
Uwe Kleine-König | b595076 | 2010-11-01 15:38:34 -0400 | [diff] [blame] | 2975 | * e1000_get_phy_addr_for_hv_page - Get PHY address based on page |
Bruce Allan | a4f58f5 | 2009-06-02 11:29:18 +0000 | [diff] [blame] | 2976 | * @page: page to be accessed |
| 2977 | **/ |
| 2978 | static u32 e1000_get_phy_addr_for_hv_page(u32 page) |
| 2979 | { |
| 2980 | u32 phy_addr = 2; |
| 2981 | |
| 2982 | if (page >= HV_INTC_FC_PAGE_START) |
| 2983 | phy_addr = 1; |
| 2984 | |
| 2985 | return phy_addr; |
| 2986 | } |
| 2987 | |
| 2988 | /** |
| 2989 | * e1000_access_phy_debug_regs_hv - Read HV PHY vendor specific high registers |
| 2990 | * @hw: pointer to the HW structure |
| 2991 | * @offset: register offset to be read or written |
| 2992 | * @data: pointer to the data to be read or written |
Bruce Allan | 2b6b168 | 2011-05-13 07:20:09 +0000 | [diff] [blame] | 2993 | * @read: determines if operation is read or write |
Bruce Allan | a4f58f5 | 2009-06-02 11:29:18 +0000 | [diff] [blame] | 2994 | * |
Bruce Allan | 5ccdcec | 2009-10-26 11:24:02 +0000 | [diff] [blame] | 2995 | * Reads the PHY register at offset and stores the retreived information |
| 2996 | * in data. Assumes semaphore already acquired. Note that the procedure |
Bruce Allan | 2b6b168 | 2011-05-13 07:20:09 +0000 | [diff] [blame] | 2997 | * to access these regs uses the address port and data port to read/write. |
| 2998 | * These accesses done with PHY address 2 and without using pages. |
Bruce Allan | a4f58f5 | 2009-06-02 11:29:18 +0000 | [diff] [blame] | 2999 | **/ |
| 3000 | static s32 e1000_access_phy_debug_regs_hv(struct e1000_hw *hw, u32 offset, |
Bruce Allan | 66501f5 | 2013-02-20 04:05:55 +0000 | [diff] [blame] | 3001 | u16 *data, bool read) |
Bruce Allan | a4f58f5 | 2009-06-02 11:29:18 +0000 | [diff] [blame] | 3002 | { |
| 3003 | s32 ret_val; |
Bruce Allan | 70806a7 | 2013-01-05 05:08:37 +0000 | [diff] [blame] | 3004 | u32 addr_reg; |
| 3005 | u32 data_reg; |
Bruce Allan | a4f58f5 | 2009-06-02 11:29:18 +0000 | [diff] [blame] | 3006 | |
| 3007 | /* This takes care of the difference with desktop vs mobile phy */ |
Bruce Allan | f0ff439 | 2013-02-20 04:05:39 +0000 | [diff] [blame] | 3008 | addr_reg = ((hw->phy.type == e1000_phy_82578) ? |
| 3009 | I82578_ADDR_REG : I82577_ADDR_REG); |
Bruce Allan | a4f58f5 | 2009-06-02 11:29:18 +0000 | [diff] [blame] | 3010 | data_reg = addr_reg + 1; |
| 3011 | |
Bruce Allan | a4f58f5 | 2009-06-02 11:29:18 +0000 | [diff] [blame] | 3012 | /* All operations in this function are phy address 2 */ |
| 3013 | hw->phy.addr = 2; |
| 3014 | |
| 3015 | /* masking with 0x3F to remove the page from offset */ |
| 3016 | ret_val = e1000e_write_phy_reg_mdic(hw, addr_reg, (u16)offset & 0x3F); |
| 3017 | if (ret_val) { |
Bruce Allan | 2b6b168 | 2011-05-13 07:20:09 +0000 | [diff] [blame] | 3018 | e_dbg("Could not write the Address Offset port register\n"); |
Bruce Allan | 5015e53 | 2012-02-08 02:55:56 +0000 | [diff] [blame] | 3019 | return ret_val; |
Bruce Allan | a4f58f5 | 2009-06-02 11:29:18 +0000 | [diff] [blame] | 3020 | } |
| 3021 | |
| 3022 | /* Read or write the data value next */ |
| 3023 | if (read) |
| 3024 | ret_val = e1000e_read_phy_reg_mdic(hw, data_reg, data); |
| 3025 | else |
| 3026 | ret_val = e1000e_write_phy_reg_mdic(hw, data_reg, *data); |
| 3027 | |
Bruce Allan | 5015e53 | 2012-02-08 02:55:56 +0000 | [diff] [blame] | 3028 | if (ret_val) |
Bruce Allan | 2b6b168 | 2011-05-13 07:20:09 +0000 | [diff] [blame] | 3029 | e_dbg("Could not access the Data port register\n"); |
Bruce Allan | a4f58f5 | 2009-06-02 11:29:18 +0000 | [diff] [blame] | 3030 | |
Bruce Allan | a4f58f5 | 2009-06-02 11:29:18 +0000 | [diff] [blame] | 3031 | return ret_val; |
| 3032 | } |
| 3033 | |
| 3034 | /** |
| 3035 | * e1000_link_stall_workaround_hv - Si workaround |
| 3036 | * @hw: pointer to the HW structure |
| 3037 | * |
| 3038 | * This function works around a Si bug where the link partner can get |
| 3039 | * a link up indication before the PHY does. If small packets are sent |
| 3040 | * by the link partner they can be placed in the packet buffer without |
| 3041 | * being properly accounted for by the PHY and will stall preventing |
| 3042 | * further packets from being received. The workaround is to clear the |
| 3043 | * packet buffer after the PHY detects link up. |
| 3044 | **/ |
| 3045 | s32 e1000_link_stall_workaround_hv(struct e1000_hw *hw) |
| 3046 | { |
| 3047 | s32 ret_val = 0; |
| 3048 | u16 data; |
| 3049 | |
| 3050 | if (hw->phy.type != e1000_phy_82578) |
Bruce Allan | 5015e53 | 2012-02-08 02:55:56 +0000 | [diff] [blame] | 3051 | return 0; |
Bruce Allan | a4f58f5 | 2009-06-02 11:29:18 +0000 | [diff] [blame] | 3052 | |
Bruce Allan | e65fa87 | 2009-07-01 13:27:31 +0000 | [diff] [blame] | 3053 | /* Do not apply workaround if in PHY loopback bit 14 set */ |
Bruce Allan | c2ade1a | 2013-01-16 08:54:35 +0000 | [diff] [blame] | 3054 | e1e_rphy(hw, MII_BMCR, &data); |
| 3055 | if (data & BMCR_LOOPBACK) |
Bruce Allan | 5015e53 | 2012-02-08 02:55:56 +0000 | [diff] [blame] | 3056 | return 0; |
Bruce Allan | e65fa87 | 2009-07-01 13:27:31 +0000 | [diff] [blame] | 3057 | |
Bruce Allan | a4f58f5 | 2009-06-02 11:29:18 +0000 | [diff] [blame] | 3058 | /* check if link is up and at 1Gbps */ |
Bruce Allan | 482fed8 | 2011-01-06 14:29:49 +0000 | [diff] [blame] | 3059 | ret_val = e1e_rphy(hw, BM_CS_STATUS, &data); |
Bruce Allan | a4f58f5 | 2009-06-02 11:29:18 +0000 | [diff] [blame] | 3060 | if (ret_val) |
Bruce Allan | 5015e53 | 2012-02-08 02:55:56 +0000 | [diff] [blame] | 3061 | return ret_val; |
Bruce Allan | a4f58f5 | 2009-06-02 11:29:18 +0000 | [diff] [blame] | 3062 | |
Bruce Allan | f0ff439 | 2013-02-20 04:05:39 +0000 | [diff] [blame] | 3063 | data &= (BM_CS_STATUS_LINK_UP | BM_CS_STATUS_RESOLVED | |
| 3064 | BM_CS_STATUS_SPEED_MASK); |
Bruce Allan | a4f58f5 | 2009-06-02 11:29:18 +0000 | [diff] [blame] | 3065 | |
Bruce Allan | 3d3a167 | 2012-02-23 03:13:18 +0000 | [diff] [blame] | 3066 | if (data != (BM_CS_STATUS_LINK_UP | BM_CS_STATUS_RESOLVED | |
| 3067 | BM_CS_STATUS_SPEED_1000)) |
Bruce Allan | 5015e53 | 2012-02-08 02:55:56 +0000 | [diff] [blame] | 3068 | return 0; |
Bruce Allan | a4f58f5 | 2009-06-02 11:29:18 +0000 | [diff] [blame] | 3069 | |
Bruce Allan | bb9c5ee | 2012-02-23 03:31:29 +0000 | [diff] [blame] | 3070 | msleep(200); |
Bruce Allan | a4f58f5 | 2009-06-02 11:29:18 +0000 | [diff] [blame] | 3071 | |
| 3072 | /* flush the packets in the fifo buffer */ |
Bruce Allan | c063f60 | 2013-01-12 07:27:53 +0000 | [diff] [blame] | 3073 | ret_val = e1e_wphy(hw, HV_MUX_DATA_CTRL, |
| 3074 | (HV_MUX_DATA_CTRL_GEN_TO_MAC | |
| 3075 | HV_MUX_DATA_CTRL_FORCE_SPEED)); |
Bruce Allan | a4f58f5 | 2009-06-02 11:29:18 +0000 | [diff] [blame] | 3076 | if (ret_val) |
Bruce Allan | 5015e53 | 2012-02-08 02:55:56 +0000 | [diff] [blame] | 3077 | return ret_val; |
Bruce Allan | a4f58f5 | 2009-06-02 11:29:18 +0000 | [diff] [blame] | 3078 | |
Bruce Allan | 5015e53 | 2012-02-08 02:55:56 +0000 | [diff] [blame] | 3079 | return e1e_wphy(hw, HV_MUX_DATA_CTRL, HV_MUX_DATA_CTRL_GEN_TO_MAC); |
Bruce Allan | a4f58f5 | 2009-06-02 11:29:18 +0000 | [diff] [blame] | 3080 | } |
| 3081 | |
| 3082 | /** |
| 3083 | * e1000_check_polarity_82577 - Checks the polarity. |
| 3084 | * @hw: pointer to the HW structure |
| 3085 | * |
| 3086 | * Success returns 0, Failure returns -E1000_ERR_PHY (-2) |
| 3087 | * |
| 3088 | * Polarity is determined based on the PHY specific status register. |
| 3089 | **/ |
| 3090 | s32 e1000_check_polarity_82577(struct e1000_hw *hw) |
| 3091 | { |
| 3092 | struct e1000_phy_info *phy = &hw->phy; |
| 3093 | s32 ret_val; |
| 3094 | u16 data; |
| 3095 | |
Bruce Allan | 482fed8 | 2011-01-06 14:29:49 +0000 | [diff] [blame] | 3096 | ret_val = e1e_rphy(hw, I82577_PHY_STATUS_2, &data); |
Bruce Allan | a4f58f5 | 2009-06-02 11:29:18 +0000 | [diff] [blame] | 3097 | |
| 3098 | if (!ret_val) |
Bruce Allan | f0ff439 | 2013-02-20 04:05:39 +0000 | [diff] [blame] | 3099 | phy->cable_polarity = ((data & I82577_PHY_STATUS2_REV_POLARITY) |
| 3100 | ? e1000_rev_polarity_reversed |
| 3101 | : e1000_rev_polarity_normal); |
Bruce Allan | a4f58f5 | 2009-06-02 11:29:18 +0000 | [diff] [blame] | 3102 | |
| 3103 | return ret_val; |
| 3104 | } |
| 3105 | |
| 3106 | /** |
| 3107 | * e1000_phy_force_speed_duplex_82577 - Force speed/duplex for I82577 PHY |
| 3108 | * @hw: pointer to the HW structure |
| 3109 | * |
Bruce Allan | eab50ff | 2010-05-10 15:01:30 +0000 | [diff] [blame] | 3110 | * Calls the PHY setup function to force speed and duplex. |
Bruce Allan | a4f58f5 | 2009-06-02 11:29:18 +0000 | [diff] [blame] | 3111 | **/ |
| 3112 | s32 e1000_phy_force_speed_duplex_82577(struct e1000_hw *hw) |
| 3113 | { |
| 3114 | struct e1000_phy_info *phy = &hw->phy; |
| 3115 | s32 ret_val; |
| 3116 | u16 phy_data; |
| 3117 | bool link; |
| 3118 | |
Bruce Allan | c2ade1a | 2013-01-16 08:54:35 +0000 | [diff] [blame] | 3119 | ret_val = e1e_rphy(hw, MII_BMCR, &phy_data); |
Bruce Allan | a4f58f5 | 2009-06-02 11:29:18 +0000 | [diff] [blame] | 3120 | if (ret_val) |
Bruce Allan | 5015e53 | 2012-02-08 02:55:56 +0000 | [diff] [blame] | 3121 | return ret_val; |
Bruce Allan | a4f58f5 | 2009-06-02 11:29:18 +0000 | [diff] [blame] | 3122 | |
| 3123 | e1000e_phy_force_speed_duplex_setup(hw, &phy_data); |
| 3124 | |
Bruce Allan | c2ade1a | 2013-01-16 08:54:35 +0000 | [diff] [blame] | 3125 | ret_val = e1e_wphy(hw, MII_BMCR, phy_data); |
Bruce Allan | a4f58f5 | 2009-06-02 11:29:18 +0000 | [diff] [blame] | 3126 | if (ret_val) |
Bruce Allan | 5015e53 | 2012-02-08 02:55:56 +0000 | [diff] [blame] | 3127 | return ret_val; |
Bruce Allan | a4f58f5 | 2009-06-02 11:29:18 +0000 | [diff] [blame] | 3128 | |
Bruce Allan | a4f58f5 | 2009-06-02 11:29:18 +0000 | [diff] [blame] | 3129 | udelay(1); |
| 3130 | |
| 3131 | if (phy->autoneg_wait_to_complete) { |
Bruce Allan | 3bb99fe | 2009-11-20 23:25:07 +0000 | [diff] [blame] | 3132 | e_dbg("Waiting for forced speed/duplex link on 82577 phy\n"); |
Bruce Allan | a4f58f5 | 2009-06-02 11:29:18 +0000 | [diff] [blame] | 3133 | |
Bruce Allan | 3d3a167 | 2012-02-23 03:13:18 +0000 | [diff] [blame] | 3134 | ret_val = e1000e_phy_has_link_generic(hw, PHY_FORCE_LIMIT, |
| 3135 | 100000, &link); |
Bruce Allan | a4f58f5 | 2009-06-02 11:29:18 +0000 | [diff] [blame] | 3136 | if (ret_val) |
Bruce Allan | 5015e53 | 2012-02-08 02:55:56 +0000 | [diff] [blame] | 3137 | return ret_val; |
Bruce Allan | a4f58f5 | 2009-06-02 11:29:18 +0000 | [diff] [blame] | 3138 | |
| 3139 | if (!link) |
Bruce Allan | 3bb99fe | 2009-11-20 23:25:07 +0000 | [diff] [blame] | 3140 | e_dbg("Link taking longer than expected.\n"); |
Bruce Allan | a4f58f5 | 2009-06-02 11:29:18 +0000 | [diff] [blame] | 3141 | |
| 3142 | /* Try once more */ |
Bruce Allan | 3d3a167 | 2012-02-23 03:13:18 +0000 | [diff] [blame] | 3143 | ret_val = e1000e_phy_has_link_generic(hw, PHY_FORCE_LIMIT, |
| 3144 | 100000, &link); |
Bruce Allan | a4f58f5 | 2009-06-02 11:29:18 +0000 | [diff] [blame] | 3145 | } |
| 3146 | |
Bruce Allan | a4f58f5 | 2009-06-02 11:29:18 +0000 | [diff] [blame] | 3147 | return ret_val; |
| 3148 | } |
| 3149 | |
| 3150 | /** |
| 3151 | * e1000_get_phy_info_82577 - Retrieve I82577 PHY information |
| 3152 | * @hw: pointer to the HW structure |
| 3153 | * |
| 3154 | * Read PHY status to determine if link is up. If link is up, then |
| 3155 | * set/determine 10base-T extended distance and polarity correction. Read |
| 3156 | * PHY port status to determine MDI/MDIx and speed. Based on the speed, |
| 3157 | * determine on the cable length, local and remote receiver. |
| 3158 | **/ |
| 3159 | s32 e1000_get_phy_info_82577(struct e1000_hw *hw) |
| 3160 | { |
| 3161 | struct e1000_phy_info *phy = &hw->phy; |
| 3162 | s32 ret_val; |
| 3163 | u16 data; |
| 3164 | bool link; |
| 3165 | |
| 3166 | ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link); |
| 3167 | if (ret_val) |
Bruce Allan | 5015e53 | 2012-02-08 02:55:56 +0000 | [diff] [blame] | 3168 | return ret_val; |
Bruce Allan | a4f58f5 | 2009-06-02 11:29:18 +0000 | [diff] [blame] | 3169 | |
| 3170 | if (!link) { |
Bruce Allan | 3bb99fe | 2009-11-20 23:25:07 +0000 | [diff] [blame] | 3171 | e_dbg("Phy info is only valid if link is up\n"); |
Bruce Allan | 5015e53 | 2012-02-08 02:55:56 +0000 | [diff] [blame] | 3172 | return -E1000_ERR_CONFIG; |
Bruce Allan | a4f58f5 | 2009-06-02 11:29:18 +0000 | [diff] [blame] | 3173 | } |
| 3174 | |
| 3175 | phy->polarity_correction = true; |
| 3176 | |
| 3177 | ret_val = e1000_check_polarity_82577(hw); |
| 3178 | if (ret_val) |
Bruce Allan | 5015e53 | 2012-02-08 02:55:56 +0000 | [diff] [blame] | 3179 | return ret_val; |
Bruce Allan | a4f58f5 | 2009-06-02 11:29:18 +0000 | [diff] [blame] | 3180 | |
Bruce Allan | 482fed8 | 2011-01-06 14:29:49 +0000 | [diff] [blame] | 3181 | ret_val = e1e_rphy(hw, I82577_PHY_STATUS_2, &data); |
Bruce Allan | a4f58f5 | 2009-06-02 11:29:18 +0000 | [diff] [blame] | 3182 | if (ret_val) |
Bruce Allan | 5015e53 | 2012-02-08 02:55:56 +0000 | [diff] [blame] | 3183 | return ret_val; |
Bruce Allan | a4f58f5 | 2009-06-02 11:29:18 +0000 | [diff] [blame] | 3184 | |
Bruce Allan | 04499ec | 2012-04-13 00:08:31 +0000 | [diff] [blame] | 3185 | phy->is_mdix = !!(data & I82577_PHY_STATUS2_MDIX); |
Bruce Allan | a4f58f5 | 2009-06-02 11:29:18 +0000 | [diff] [blame] | 3186 | |
| 3187 | if ((data & I82577_PHY_STATUS2_SPEED_MASK) == |
| 3188 | I82577_PHY_STATUS2_SPEED_1000MBPS) { |
| 3189 | ret_val = hw->phy.ops.get_cable_length(hw); |
| 3190 | if (ret_val) |
Bruce Allan | 5015e53 | 2012-02-08 02:55:56 +0000 | [diff] [blame] | 3191 | return ret_val; |
Bruce Allan | a4f58f5 | 2009-06-02 11:29:18 +0000 | [diff] [blame] | 3192 | |
Bruce Allan | c2ade1a | 2013-01-16 08:54:35 +0000 | [diff] [blame] | 3193 | ret_val = e1e_rphy(hw, MII_STAT1000, &data); |
Bruce Allan | a4f58f5 | 2009-06-02 11:29:18 +0000 | [diff] [blame] | 3194 | if (ret_val) |
Bruce Allan | 5015e53 | 2012-02-08 02:55:56 +0000 | [diff] [blame] | 3195 | return ret_val; |
Bruce Allan | a4f58f5 | 2009-06-02 11:29:18 +0000 | [diff] [blame] | 3196 | |
Bruce Allan | c2ade1a | 2013-01-16 08:54:35 +0000 | [diff] [blame] | 3197 | phy->local_rx = (data & LPA_1000LOCALRXOK) |
| 3198 | ? e1000_1000t_rx_status_ok : e1000_1000t_rx_status_not_ok; |
Bruce Allan | a4f58f5 | 2009-06-02 11:29:18 +0000 | [diff] [blame] | 3199 | |
Bruce Allan | c2ade1a | 2013-01-16 08:54:35 +0000 | [diff] [blame] | 3200 | phy->remote_rx = (data & LPA_1000REMRXOK) |
| 3201 | ? e1000_1000t_rx_status_ok : e1000_1000t_rx_status_not_ok; |
Bruce Allan | a4f58f5 | 2009-06-02 11:29:18 +0000 | [diff] [blame] | 3202 | } else { |
| 3203 | phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED; |
| 3204 | phy->local_rx = e1000_1000t_rx_status_undefined; |
| 3205 | phy->remote_rx = e1000_1000t_rx_status_undefined; |
| 3206 | } |
| 3207 | |
Bruce Allan | 5015e53 | 2012-02-08 02:55:56 +0000 | [diff] [blame] | 3208 | return 0; |
Bruce Allan | a4f58f5 | 2009-06-02 11:29:18 +0000 | [diff] [blame] | 3209 | } |
| 3210 | |
| 3211 | /** |
| 3212 | * e1000_get_cable_length_82577 - Determine cable length for 82577 PHY |
| 3213 | * @hw: pointer to the HW structure |
| 3214 | * |
| 3215 | * Reads the diagnostic status register and verifies result is valid before |
| 3216 | * placing it in the phy_cable_length field. |
| 3217 | **/ |
| 3218 | s32 e1000_get_cable_length_82577(struct e1000_hw *hw) |
| 3219 | { |
| 3220 | struct e1000_phy_info *phy = &hw->phy; |
| 3221 | s32 ret_val; |
| 3222 | u16 phy_data, length; |
| 3223 | |
Bruce Allan | 482fed8 | 2011-01-06 14:29:49 +0000 | [diff] [blame] | 3224 | ret_val = e1e_rphy(hw, I82577_PHY_DIAG_STATUS, &phy_data); |
Bruce Allan | a4f58f5 | 2009-06-02 11:29:18 +0000 | [diff] [blame] | 3225 | if (ret_val) |
Bruce Allan | 5015e53 | 2012-02-08 02:55:56 +0000 | [diff] [blame] | 3226 | return ret_val; |
Bruce Allan | a4f58f5 | 2009-06-02 11:29:18 +0000 | [diff] [blame] | 3227 | |
Bruce Allan | f0ff439 | 2013-02-20 04:05:39 +0000 | [diff] [blame] | 3228 | length = ((phy_data & I82577_DSTATUS_CABLE_LENGTH) >> |
| 3229 | I82577_DSTATUS_CABLE_LENGTH_SHIFT); |
Bruce Allan | a4f58f5 | 2009-06-02 11:29:18 +0000 | [diff] [blame] | 3230 | |
| 3231 | if (length == E1000_CABLE_LENGTH_UNDEFINED) |
Bruce Allan | 7dbbe5d | 2013-01-05 05:08:31 +0000 | [diff] [blame] | 3232 | return -E1000_ERR_PHY; |
Bruce Allan | a4f58f5 | 2009-06-02 11:29:18 +0000 | [diff] [blame] | 3233 | |
| 3234 | phy->cable_length = length; |
| 3235 | |
Bruce Allan | 5015e53 | 2012-02-08 02:55:56 +0000 | [diff] [blame] | 3236 | return 0; |
Bruce Allan | a4f58f5 | 2009-06-02 11:29:18 +0000 | [diff] [blame] | 3237 | } |