Paolo Ciarrocchi | d441373 | 2008-02-19 23:51:27 +0100 | [diff] [blame] | 1 | /* |
Robert Richter | 6852fd9 | 2008-07-22 21:09:08 +0200 | [diff] [blame] | 2 | * @file op_model_amd.c |
Barry Kasindorf | bd87f1f | 2007-12-18 18:05:58 +0100 | [diff] [blame] | 3 | * athlon / K7 / K8 / Family 10h model-specific MSR operations |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 4 | * |
Robert Richter | ae735e9 | 2008-12-25 17:26:07 +0100 | [diff] [blame] | 5 | * @remark Copyright 2002-2009 OProfile authors |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 6 | * @remark Read the file COPYING |
| 7 | * |
| 8 | * @author John Levon |
| 9 | * @author Philippe Elie |
| 10 | * @author Graydon Hoare |
Robert Richter | adf5ec0 | 2008-07-22 21:08:48 +0200 | [diff] [blame] | 11 | * @author Robert Richter <robert.richter@amd.com> |
Jason Yeh | 4d4036e | 2009-07-08 13:49:38 +0200 | [diff] [blame] | 12 | * @author Barry Kasindorf <barry.kasindorf@amd.com> |
| 13 | * @author Jason Yeh <jason.yeh@amd.com> |
| 14 | * @author Suravee Suthikulpanit <suravee.suthikulpanit@amd.com> |
Robert Richter | ae735e9 | 2008-12-25 17:26:07 +0100 | [diff] [blame] | 15 | */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 16 | |
| 17 | #include <linux/oprofile.h> |
Barry Kasindorf | 56784f1 | 2008-07-22 21:08:55 +0200 | [diff] [blame] | 18 | #include <linux/device.h> |
| 19 | #include <linux/pci.h> |
Jason Yeh | 4d4036e | 2009-07-08 13:49:38 +0200 | [diff] [blame] | 20 | #include <linux/percpu.h> |
Barry Kasindorf | 56784f1 | 2008-07-22 21:08:55 +0200 | [diff] [blame] | 21 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 22 | #include <asm/ptrace.h> |
| 23 | #include <asm/msr.h> |
Don Zickus | 3e4ff11 | 2006-06-26 13:57:01 +0200 | [diff] [blame] | 24 | #include <asm/nmi.h> |
Robert Richter | 013cfc5 | 2010-01-28 18:05:26 +0100 | [diff] [blame] | 25 | #include <asm/apic.h> |
Robert Richter | 64683da | 2010-02-04 10:57:23 +0100 | [diff] [blame] | 26 | #include <asm/processor.h> |
| 27 | #include <asm/cpufeature.h> |
Paolo Ciarrocchi | d441373 | 2008-02-19 23:51:27 +0100 | [diff] [blame] | 28 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 29 | #include "op_x86_model.h" |
| 30 | #include "op_counter.h" |
| 31 | |
Robert Richter | da169f5 | 2010-09-24 15:54:43 +0200 | [diff] [blame^] | 32 | #define NUM_COUNTERS 4 |
| 33 | #define NUM_COUNTERS_F15H 6 |
Jason Yeh | 4d4036e | 2009-07-08 13:49:38 +0200 | [diff] [blame] | 34 | #ifdef CONFIG_OPROFILE_EVENT_MULTIPLEX |
Robert Richter | da169f5 | 2010-09-24 15:54:43 +0200 | [diff] [blame^] | 35 | #define NUM_VIRT_COUNTERS 32 |
Jason Yeh | 4d4036e | 2009-07-08 13:49:38 +0200 | [diff] [blame] | 36 | #else |
Robert Richter | da169f5 | 2010-09-24 15:54:43 +0200 | [diff] [blame^] | 37 | #define NUM_VIRT_COUNTERS 0 |
Jason Yeh | 4d4036e | 2009-07-08 13:49:38 +0200 | [diff] [blame] | 38 | #endif |
| 39 | |
Robert Richter | 3370d35 | 2009-05-25 15:10:32 +0200 | [diff] [blame] | 40 | #define OP_EVENT_MASK 0x0FFF |
Robert Richter | 42399ad | 2009-05-25 17:59:06 +0200 | [diff] [blame] | 41 | #define OP_CTR_OVERFLOW (1ULL<<31) |
Robert Richter | 3370d35 | 2009-05-25 15:10:32 +0200 | [diff] [blame] | 42 | |
| 43 | #define MSR_AMD_EVENTSEL_RESERVED ((0xFFFFFCF0ULL<<32)|(1ULL<<21)) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 44 | |
Robert Richter | da169f5 | 2010-09-24 15:54:43 +0200 | [diff] [blame^] | 45 | static int num_counters; |
| 46 | static unsigned long reset_value[OP_MAX_COUNTER]; |
Robert Richter | 852402c | 2008-07-22 21:09:06 +0200 | [diff] [blame] | 47 | |
Robert Richter | c572ae4 | 2009-06-03 20:10:39 +0200 | [diff] [blame] | 48 | #define IBS_FETCH_SIZE 6 |
| 49 | #define IBS_OP_SIZE 12 |
Barry Kasindorf | 56784f1 | 2008-07-22 21:08:55 +0200 | [diff] [blame] | 50 | |
Robert Richter | 64683da | 2010-02-04 10:57:23 +0100 | [diff] [blame] | 51 | static u32 ibs_caps; |
Barry Kasindorf | 56784f1 | 2008-07-22 21:08:55 +0200 | [diff] [blame] | 52 | |
Robert Richter | 53b39e9 | 2010-09-21 17:58:15 +0200 | [diff] [blame] | 53 | struct ibs_config { |
Barry Kasindorf | 56784f1 | 2008-07-22 21:08:55 +0200 | [diff] [blame] | 54 | unsigned long op_enabled; |
| 55 | unsigned long fetch_enabled; |
| 56 | unsigned long max_cnt_fetch; |
| 57 | unsigned long max_cnt_op; |
| 58 | unsigned long rand_en; |
| 59 | unsigned long dispatched_ops; |
Robert Richter | 25da695 | 2010-09-21 15:49:31 +0200 | [diff] [blame] | 60 | unsigned long branch_target; |
Barry Kasindorf | 56784f1 | 2008-07-22 21:08:55 +0200 | [diff] [blame] | 61 | }; |
| 62 | |
Robert Richter | 53b39e9 | 2010-09-21 17:58:15 +0200 | [diff] [blame] | 63 | struct ibs_state { |
Robert Richter | 25da695 | 2010-09-21 15:49:31 +0200 | [diff] [blame] | 64 | u64 ibs_op_ctl; |
| 65 | int branch_target; |
| 66 | unsigned long sample_size; |
Robert Richter | 53b39e9 | 2010-09-21 17:58:15 +0200 | [diff] [blame] | 67 | }; |
| 68 | |
| 69 | static struct ibs_config ibs_config; |
| 70 | static struct ibs_state ibs_state; |
Paolo Ciarrocchi | d441373 | 2008-02-19 23:51:27 +0100 | [diff] [blame] | 71 | |
Robert Richter | 64683da | 2010-02-04 10:57:23 +0100 | [diff] [blame] | 72 | /* |
| 73 | * IBS cpuid feature detection |
| 74 | */ |
| 75 | |
Robert Richter | 27afdf2 | 2010-10-06 12:27:54 +0200 | [diff] [blame] | 76 | #define IBS_CPUID_FEATURES 0x8000001b |
Robert Richter | 64683da | 2010-02-04 10:57:23 +0100 | [diff] [blame] | 77 | |
| 78 | /* |
| 79 | * Same bit mask as for IBS cpuid feature flags (Fn8000_001B_EAX), but |
| 80 | * bit 0 is used to indicate the existence of IBS. |
| 81 | */ |
Robert Richter | 27afdf2 | 2010-10-06 12:27:54 +0200 | [diff] [blame] | 82 | #define IBS_CAPS_AVAIL (1U<<0) |
Robert Richter | 4ac945f | 2010-09-21 15:58:32 +0200 | [diff] [blame] | 83 | #define IBS_CAPS_FETCHSAM (1U<<1) |
| 84 | #define IBS_CAPS_OPSAM (1U<<2) |
Robert Richter | 27afdf2 | 2010-10-06 12:27:54 +0200 | [diff] [blame] | 85 | #define IBS_CAPS_RDWROPCNT (1U<<3) |
| 86 | #define IBS_CAPS_OPCNT (1U<<4) |
Robert Richter | 25da695 | 2010-09-21 15:49:31 +0200 | [diff] [blame] | 87 | #define IBS_CAPS_BRNTRGT (1U<<5) |
Robert Richter | b47fad3 | 2010-09-22 17:45:39 +0200 | [diff] [blame] | 88 | #define IBS_CAPS_OPCNTEXT (1U<<6) |
Robert Richter | 4ac945f | 2010-09-21 15:58:32 +0200 | [diff] [blame] | 89 | |
| 90 | #define IBS_CAPS_DEFAULT (IBS_CAPS_AVAIL \ |
| 91 | | IBS_CAPS_FETCHSAM \ |
| 92 | | IBS_CAPS_OPSAM) |
Robert Richter | 27afdf2 | 2010-10-06 12:27:54 +0200 | [diff] [blame] | 93 | |
| 94 | /* |
| 95 | * IBS APIC setup |
| 96 | */ |
| 97 | #define IBSCTL 0x1cc |
| 98 | #define IBSCTL_LVT_OFFSET_VALID (1ULL<<8) |
| 99 | #define IBSCTL_LVT_OFFSET_MASK 0x0F |
Robert Richter | 64683da | 2010-02-04 10:57:23 +0100 | [diff] [blame] | 100 | |
Robert Richter | ba52078 | 2010-02-23 15:46:49 +0100 | [diff] [blame] | 101 | /* |
| 102 | * IBS randomization macros |
| 103 | */ |
| 104 | #define IBS_RANDOM_BITS 12 |
| 105 | #define IBS_RANDOM_MASK ((1ULL << IBS_RANDOM_BITS) - 1) |
| 106 | #define IBS_RANDOM_MAXCNT_OFFSET (1ULL << (IBS_RANDOM_BITS - 5)) |
| 107 | |
Robert Richter | 64683da | 2010-02-04 10:57:23 +0100 | [diff] [blame] | 108 | static u32 get_ibs_caps(void) |
| 109 | { |
| 110 | u32 ibs_caps; |
| 111 | unsigned int max_level; |
| 112 | |
| 113 | if (!boot_cpu_has(X86_FEATURE_IBS)) |
| 114 | return 0; |
| 115 | |
| 116 | /* check IBS cpuid feature flags */ |
| 117 | max_level = cpuid_eax(0x80000000); |
| 118 | if (max_level < IBS_CPUID_FEATURES) |
Robert Richter | 4ac945f | 2010-09-21 15:58:32 +0200 | [diff] [blame] | 119 | return IBS_CAPS_DEFAULT; |
Robert Richter | 64683da | 2010-02-04 10:57:23 +0100 | [diff] [blame] | 120 | |
| 121 | ibs_caps = cpuid_eax(IBS_CPUID_FEATURES); |
| 122 | if (!(ibs_caps & IBS_CAPS_AVAIL)) |
| 123 | /* cpuid flags not valid */ |
Robert Richter | 4ac945f | 2010-09-21 15:58:32 +0200 | [diff] [blame] | 124 | return IBS_CAPS_DEFAULT; |
Robert Richter | 64683da | 2010-02-04 10:57:23 +0100 | [diff] [blame] | 125 | |
| 126 | return ibs_caps; |
| 127 | } |
| 128 | |
Suravee Suthikulpanit | f125be1 | 2010-01-18 11:25:45 -0600 | [diff] [blame] | 129 | /* |
| 130 | * 16-bit Linear Feedback Shift Register (LFSR) |
| 131 | * |
| 132 | * 16 14 13 11 |
| 133 | * Feedback polynomial = X + X + X + X + 1 |
| 134 | */ |
| 135 | static unsigned int lfsr_random(void) |
| 136 | { |
| 137 | static unsigned int lfsr_value = 0xF00D; |
| 138 | unsigned int bit; |
| 139 | |
| 140 | /* Compute next bit to shift in */ |
| 141 | bit = ((lfsr_value >> 0) ^ |
| 142 | (lfsr_value >> 2) ^ |
| 143 | (lfsr_value >> 3) ^ |
| 144 | (lfsr_value >> 5)) & 0x0001; |
| 145 | |
| 146 | /* Advance to next register value */ |
| 147 | lfsr_value = (lfsr_value >> 1) | (bit << 15); |
| 148 | |
| 149 | return lfsr_value; |
| 150 | } |
| 151 | |
Robert Richter | ba52078 | 2010-02-23 15:46:49 +0100 | [diff] [blame] | 152 | /* |
| 153 | * IBS software randomization |
| 154 | * |
| 155 | * The IBS periodic op counter is randomized in software. The lower 12 |
| 156 | * bits of the 20 bit counter are randomized. IbsOpCurCnt is |
| 157 | * initialized with a 12 bit random value. |
| 158 | */ |
| 159 | static inline u64 op_amd_randomize_ibs_op(u64 val) |
| 160 | { |
| 161 | unsigned int random = lfsr_random(); |
| 162 | |
| 163 | if (!(ibs_caps & IBS_CAPS_RDWROPCNT)) |
| 164 | /* |
| 165 | * Work around if the hw can not write to IbsOpCurCnt |
| 166 | * |
| 167 | * Randomize the lower 8 bits of the 16 bit |
| 168 | * IbsOpMaxCnt [15:0] value in the range of -128 to |
| 169 | * +127 by adding/subtracting an offset to the |
| 170 | * maximum count (IbsOpMaxCnt). |
| 171 | * |
| 172 | * To avoid over or underflows and protect upper bits |
| 173 | * starting at bit 16, the initial value for |
| 174 | * IbsOpMaxCnt must fit in the range from 0x0081 to |
| 175 | * 0xff80. |
| 176 | */ |
| 177 | val += (s8)(random >> 4); |
| 178 | else |
| 179 | val |= (u64)(random & IBS_RANDOM_MASK) << 32; |
| 180 | |
| 181 | return val; |
| 182 | } |
| 183 | |
Andrew Morton | 4680e64 | 2009-06-23 12:36:08 -0700 | [diff] [blame] | 184 | static inline void |
Robert Richter | 7939d2b | 2008-07-22 21:08:56 +0200 | [diff] [blame] | 185 | op_amd_handle_ibs(struct pt_regs * const regs, |
| 186 | struct op_msrs const * const msrs) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 187 | { |
Robert Richter | c572ae4 | 2009-06-03 20:10:39 +0200 | [diff] [blame] | 188 | u64 val, ctl; |
Robert Richter | 1acda87 | 2009-01-05 10:35:31 +0100 | [diff] [blame] | 189 | struct op_entry entry; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 190 | |
Robert Richter | 64683da | 2010-02-04 10:57:23 +0100 | [diff] [blame] | 191 | if (!ibs_caps) |
Andrew Morton | 4680e64 | 2009-06-23 12:36:08 -0700 | [diff] [blame] | 192 | return; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 193 | |
Robert Richter | 7939d2b | 2008-07-22 21:08:56 +0200 | [diff] [blame] | 194 | if (ibs_config.fetch_enabled) { |
Robert Richter | c572ae4 | 2009-06-03 20:10:39 +0200 | [diff] [blame] | 195 | rdmsrl(MSR_AMD64_IBSFETCHCTL, ctl); |
| 196 | if (ctl & IBS_FETCH_VAL) { |
| 197 | rdmsrl(MSR_AMD64_IBSFETCHLINAD, val); |
| 198 | oprofile_write_reserve(&entry, regs, val, |
Robert Richter | 14f0ca8 | 2009-01-07 21:50:22 +0100 | [diff] [blame] | 199 | IBS_FETCH_CODE, IBS_FETCH_SIZE); |
Robert Richter | 51563a0 | 2009-06-03 20:54:56 +0200 | [diff] [blame] | 200 | oprofile_add_data64(&entry, val); |
| 201 | oprofile_add_data64(&entry, ctl); |
Robert Richter | c572ae4 | 2009-06-03 20:10:39 +0200 | [diff] [blame] | 202 | rdmsrl(MSR_AMD64_IBSFETCHPHYSAD, val); |
Robert Richter | 51563a0 | 2009-06-03 20:54:56 +0200 | [diff] [blame] | 203 | oprofile_add_data64(&entry, val); |
Robert Richter | 14f0ca8 | 2009-01-07 21:50:22 +0100 | [diff] [blame] | 204 | oprofile_write_commit(&entry); |
Barry Kasindorf | 56784f1 | 2008-07-22 21:08:55 +0200 | [diff] [blame] | 205 | |
Robert Richter | fd13f6c | 2008-10-19 21:00:09 +0200 | [diff] [blame] | 206 | /* reenable the IRQ */ |
Robert Richter | a163b10 | 2010-02-25 19:43:07 +0100 | [diff] [blame] | 207 | ctl &= ~(IBS_FETCH_VAL | IBS_FETCH_CNT); |
Robert Richter | c572ae4 | 2009-06-03 20:10:39 +0200 | [diff] [blame] | 208 | ctl |= IBS_FETCH_ENABLE; |
| 209 | wrmsrl(MSR_AMD64_IBSFETCHCTL, ctl); |
Barry Kasindorf | 56784f1 | 2008-07-22 21:08:55 +0200 | [diff] [blame] | 210 | } |
| 211 | } |
| 212 | |
Robert Richter | 7939d2b | 2008-07-22 21:08:56 +0200 | [diff] [blame] | 213 | if (ibs_config.op_enabled) { |
Robert Richter | c572ae4 | 2009-06-03 20:10:39 +0200 | [diff] [blame] | 214 | rdmsrl(MSR_AMD64_IBSOPCTL, ctl); |
| 215 | if (ctl & IBS_OP_VAL) { |
| 216 | rdmsrl(MSR_AMD64_IBSOPRIP, val); |
Robert Richter | 25da695 | 2010-09-21 15:49:31 +0200 | [diff] [blame] | 217 | oprofile_write_reserve(&entry, regs, val, IBS_OP_CODE, |
| 218 | ibs_state.sample_size); |
Robert Richter | 51563a0 | 2009-06-03 20:54:56 +0200 | [diff] [blame] | 219 | oprofile_add_data64(&entry, val); |
Robert Richter | c572ae4 | 2009-06-03 20:10:39 +0200 | [diff] [blame] | 220 | rdmsrl(MSR_AMD64_IBSOPDATA, val); |
Robert Richter | 51563a0 | 2009-06-03 20:54:56 +0200 | [diff] [blame] | 221 | oprofile_add_data64(&entry, val); |
Robert Richter | c572ae4 | 2009-06-03 20:10:39 +0200 | [diff] [blame] | 222 | rdmsrl(MSR_AMD64_IBSOPDATA2, val); |
Robert Richter | 51563a0 | 2009-06-03 20:54:56 +0200 | [diff] [blame] | 223 | oprofile_add_data64(&entry, val); |
Robert Richter | c572ae4 | 2009-06-03 20:10:39 +0200 | [diff] [blame] | 224 | rdmsrl(MSR_AMD64_IBSOPDATA3, val); |
Robert Richter | 51563a0 | 2009-06-03 20:54:56 +0200 | [diff] [blame] | 225 | oprofile_add_data64(&entry, val); |
Robert Richter | c572ae4 | 2009-06-03 20:10:39 +0200 | [diff] [blame] | 226 | rdmsrl(MSR_AMD64_IBSDCLINAD, val); |
Robert Richter | 51563a0 | 2009-06-03 20:54:56 +0200 | [diff] [blame] | 227 | oprofile_add_data64(&entry, val); |
Robert Richter | c572ae4 | 2009-06-03 20:10:39 +0200 | [diff] [blame] | 228 | rdmsrl(MSR_AMD64_IBSDCPHYSAD, val); |
Robert Richter | 51563a0 | 2009-06-03 20:54:56 +0200 | [diff] [blame] | 229 | oprofile_add_data64(&entry, val); |
Robert Richter | 25da695 | 2010-09-21 15:49:31 +0200 | [diff] [blame] | 230 | if (ibs_state.branch_target) { |
| 231 | rdmsrl(MSR_AMD64_IBSBRTARGET, val); |
| 232 | oprofile_add_data(&entry, (unsigned long)val); |
| 233 | } |
Robert Richter | 14f0ca8 | 2009-01-07 21:50:22 +0100 | [diff] [blame] | 234 | oprofile_write_commit(&entry); |
Barry Kasindorf | 56784f1 | 2008-07-22 21:08:55 +0200 | [diff] [blame] | 235 | |
| 236 | /* reenable the IRQ */ |
Robert Richter | 53b39e9 | 2010-09-21 17:58:15 +0200 | [diff] [blame] | 237 | ctl = op_amd_randomize_ibs_op(ibs_state.ibs_op_ctl); |
Robert Richter | c572ae4 | 2009-06-03 20:10:39 +0200 | [diff] [blame] | 238 | wrmsrl(MSR_AMD64_IBSOPCTL, ctl); |
Barry Kasindorf | 56784f1 | 2008-07-22 21:08:55 +0200 | [diff] [blame] | 239 | } |
| 240 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 241 | } |
| 242 | |
Robert Richter | 9063759 | 2009-03-10 19:15:57 +0100 | [diff] [blame] | 243 | static inline void op_amd_start_ibs(void) |
| 244 | { |
Robert Richter | c572ae4 | 2009-06-03 20:10:39 +0200 | [diff] [blame] | 245 | u64 val; |
Robert Richter | 64683da | 2010-02-04 10:57:23 +0100 | [diff] [blame] | 246 | |
| 247 | if (!ibs_caps) |
| 248 | return; |
| 249 | |
Robert Richter | 53b39e9 | 2010-09-21 17:58:15 +0200 | [diff] [blame] | 250 | memset(&ibs_state, 0, sizeof(ibs_state)); |
| 251 | |
Robert Richter | b47fad3 | 2010-09-22 17:45:39 +0200 | [diff] [blame] | 252 | /* |
| 253 | * Note: Since the max count settings may out of range we |
| 254 | * write back the actual used values so that userland can read |
| 255 | * it. |
| 256 | */ |
| 257 | |
Robert Richter | 64683da | 2010-02-04 10:57:23 +0100 | [diff] [blame] | 258 | if (ibs_config.fetch_enabled) { |
Robert Richter | b47fad3 | 2010-09-22 17:45:39 +0200 | [diff] [blame] | 259 | val = ibs_config.max_cnt_fetch >> 4; |
| 260 | val = min(val, IBS_FETCH_MAX_CNT); |
| 261 | ibs_config.max_cnt_fetch = val << 4; |
Robert Richter | c572ae4 | 2009-06-03 20:10:39 +0200 | [diff] [blame] | 262 | val |= ibs_config.rand_en ? IBS_FETCH_RAND_EN : 0; |
| 263 | val |= IBS_FETCH_ENABLE; |
| 264 | wrmsrl(MSR_AMD64_IBSFETCHCTL, val); |
Robert Richter | 9063759 | 2009-03-10 19:15:57 +0100 | [diff] [blame] | 265 | } |
| 266 | |
Robert Richter | 64683da | 2010-02-04 10:57:23 +0100 | [diff] [blame] | 267 | if (ibs_config.op_enabled) { |
Robert Richter | 53b39e9 | 2010-09-21 17:58:15 +0200 | [diff] [blame] | 268 | val = ibs_config.max_cnt_op >> 4; |
Robert Richter | ba52078 | 2010-02-23 15:46:49 +0100 | [diff] [blame] | 269 | if (!(ibs_caps & IBS_CAPS_RDWROPCNT)) { |
| 270 | /* |
| 271 | * IbsOpCurCnt not supported. See |
| 272 | * op_amd_randomize_ibs_op() for details. |
| 273 | */ |
Robert Richter | 53b39e9 | 2010-09-21 17:58:15 +0200 | [diff] [blame] | 274 | val = clamp(val, 0x0081ULL, 0xFF80ULL); |
Robert Richter | b47fad3 | 2010-09-22 17:45:39 +0200 | [diff] [blame] | 275 | ibs_config.max_cnt_op = val << 4; |
Robert Richter | ba52078 | 2010-02-23 15:46:49 +0100 | [diff] [blame] | 276 | } else { |
| 277 | /* |
| 278 | * The start value is randomized with a |
| 279 | * positive offset, we need to compensate it |
| 280 | * with the half of the randomized range. Also |
| 281 | * avoid underflows. |
| 282 | */ |
Robert Richter | b47fad3 | 2010-09-22 17:45:39 +0200 | [diff] [blame] | 283 | val += IBS_RANDOM_MAXCNT_OFFSET; |
| 284 | if (ibs_caps & IBS_CAPS_OPCNTEXT) |
| 285 | val = min(val, IBS_OP_MAX_CNT_EXT); |
| 286 | else |
| 287 | val = min(val, IBS_OP_MAX_CNT); |
| 288 | ibs_config.max_cnt_op = |
| 289 | (val - IBS_RANDOM_MAXCNT_OFFSET) << 4; |
Robert Richter | ba52078 | 2010-02-23 15:46:49 +0100 | [diff] [blame] | 290 | } |
Robert Richter | b47fad3 | 2010-09-22 17:45:39 +0200 | [diff] [blame] | 291 | val = ((val & ~IBS_OP_MAX_CNT) << 4) | (val & IBS_OP_MAX_CNT); |
Robert Richter | 53b39e9 | 2010-09-21 17:58:15 +0200 | [diff] [blame] | 292 | val |= ibs_config.dispatched_ops ? IBS_OP_CNT_CTL : 0; |
| 293 | val |= IBS_OP_ENABLE; |
| 294 | ibs_state.ibs_op_ctl = val; |
Robert Richter | 25da695 | 2010-09-21 15:49:31 +0200 | [diff] [blame] | 295 | ibs_state.sample_size = IBS_OP_SIZE; |
| 296 | if (ibs_config.branch_target) { |
| 297 | ibs_state.branch_target = 1; |
| 298 | ibs_state.sample_size++; |
| 299 | } |
Robert Richter | 53b39e9 | 2010-09-21 17:58:15 +0200 | [diff] [blame] | 300 | val = op_amd_randomize_ibs_op(ibs_state.ibs_op_ctl); |
Robert Richter | c572ae4 | 2009-06-03 20:10:39 +0200 | [diff] [blame] | 301 | wrmsrl(MSR_AMD64_IBSOPCTL, val); |
Robert Richter | 9063759 | 2009-03-10 19:15:57 +0100 | [diff] [blame] | 302 | } |
| 303 | } |
| 304 | |
| 305 | static void op_amd_stop_ibs(void) |
| 306 | { |
Robert Richter | 64683da | 2010-02-04 10:57:23 +0100 | [diff] [blame] | 307 | if (!ibs_caps) |
| 308 | return; |
| 309 | |
| 310 | if (ibs_config.fetch_enabled) |
Robert Richter | 9063759 | 2009-03-10 19:15:57 +0100 | [diff] [blame] | 311 | /* clear max count and enable */ |
Robert Richter | c572ae4 | 2009-06-03 20:10:39 +0200 | [diff] [blame] | 312 | wrmsrl(MSR_AMD64_IBSFETCHCTL, 0); |
Robert Richter | 9063759 | 2009-03-10 19:15:57 +0100 | [diff] [blame] | 313 | |
Robert Richter | 64683da | 2010-02-04 10:57:23 +0100 | [diff] [blame] | 314 | if (ibs_config.op_enabled) |
Robert Richter | 9063759 | 2009-03-10 19:15:57 +0100 | [diff] [blame] | 315 | /* clear max count and enable */ |
Robert Richter | c572ae4 | 2009-06-03 20:10:39 +0200 | [diff] [blame] | 316 | wrmsrl(MSR_AMD64_IBSOPCTL, 0); |
Robert Richter | 9063759 | 2009-03-10 19:15:57 +0100 | [diff] [blame] | 317 | } |
| 318 | |
Robert Richter | 27afdf2 | 2010-10-06 12:27:54 +0200 | [diff] [blame] | 319 | static inline int eilvt_is_available(int offset) |
| 320 | { |
| 321 | /* check if we may assign a vector */ |
| 322 | return !setup_APIC_eilvt(offset, 0, APIC_EILVT_MSG_NMI, 1); |
| 323 | } |
| 324 | |
| 325 | static inline int ibs_eilvt_valid(void) |
| 326 | { |
Robert Richter | 27afdf2 | 2010-10-06 12:27:54 +0200 | [diff] [blame] | 327 | int offset; |
Ingo Molnar | 2c78ffe | 2010-10-25 08:41:09 +0200 | [diff] [blame] | 328 | u64 val; |
Robert Richter | 27afdf2 | 2010-10-06 12:27:54 +0200 | [diff] [blame] | 329 | |
| 330 | rdmsrl(MSR_AMD64_IBSCTL, val); |
Ingo Molnar | 2c78ffe | 2010-10-25 08:41:09 +0200 | [diff] [blame] | 331 | offset = val & IBSCTL_LVT_OFFSET_MASK; |
| 332 | |
Robert Richter | 27afdf2 | 2010-10-06 12:27:54 +0200 | [diff] [blame] | 333 | if (!(val & IBSCTL_LVT_OFFSET_VALID)) { |
Ingo Molnar | 2c78ffe | 2010-10-25 08:41:09 +0200 | [diff] [blame] | 334 | pr_err(FW_BUG "cpu %d, invalid IBS interrupt offset %d (MSR%08X=0x%016llx)\n", |
| 335 | smp_processor_id(), offset, MSR_AMD64_IBSCTL, val); |
Robert Richter | 27afdf2 | 2010-10-06 12:27:54 +0200 | [diff] [blame] | 336 | return 0; |
| 337 | } |
| 338 | |
Ingo Molnar | 2c78ffe | 2010-10-25 08:41:09 +0200 | [diff] [blame] | 339 | if (!eilvt_is_available(offset)) { |
| 340 | pr_err(FW_BUG "cpu %d, IBS interrupt offset %d not available (MSR%08X=0x%016llx)\n", |
| 341 | smp_processor_id(), offset, MSR_AMD64_IBSCTL, val); |
| 342 | return 0; |
| 343 | } |
Robert Richter | 27afdf2 | 2010-10-06 12:27:54 +0200 | [diff] [blame] | 344 | |
Ingo Molnar | 2c78ffe | 2010-10-25 08:41:09 +0200 | [diff] [blame] | 345 | return 1; |
Robert Richter | 27afdf2 | 2010-10-06 12:27:54 +0200 | [diff] [blame] | 346 | } |
| 347 | |
| 348 | static inline int get_ibs_offset(void) |
| 349 | { |
| 350 | u64 val; |
| 351 | |
| 352 | rdmsrl(MSR_AMD64_IBSCTL, val); |
| 353 | if (!(val & IBSCTL_LVT_OFFSET_VALID)) |
| 354 | return -EINVAL; |
| 355 | |
| 356 | return val & IBSCTL_LVT_OFFSET_MASK; |
| 357 | } |
| 358 | |
| 359 | static void setup_APIC_ibs(void) |
| 360 | { |
| 361 | int offset; |
| 362 | |
| 363 | offset = get_ibs_offset(); |
| 364 | if (offset < 0) |
| 365 | goto failed; |
| 366 | |
| 367 | if (!setup_APIC_eilvt(offset, 0, APIC_EILVT_MSG_NMI, 0)) |
| 368 | return; |
| 369 | failed: |
| 370 | pr_warn("oprofile: IBS APIC setup failed on cpu #%d\n", |
| 371 | smp_processor_id()); |
| 372 | } |
| 373 | |
| 374 | static void clear_APIC_ibs(void) |
| 375 | { |
| 376 | int offset; |
| 377 | |
| 378 | offset = get_ibs_offset(); |
| 379 | if (offset >= 0) |
| 380 | setup_APIC_eilvt(offset, 0, APIC_EILVT_MSG_FIX, 1); |
| 381 | } |
| 382 | |
Robert Richter | da759fe | 2010-02-26 10:54:56 +0100 | [diff] [blame] | 383 | #ifdef CONFIG_OPROFILE_EVENT_MULTIPLEX |
| 384 | |
| 385 | static void op_mux_switch_ctrl(struct op_x86_model_spec const *model, |
| 386 | struct op_msrs const * const msrs) |
| 387 | { |
| 388 | u64 val; |
| 389 | int i; |
| 390 | |
| 391 | /* enable active counters */ |
Robert Richter | da169f5 | 2010-09-24 15:54:43 +0200 | [diff] [blame^] | 392 | for (i = 0; i < num_counters; ++i) { |
Robert Richter | da759fe | 2010-02-26 10:54:56 +0100 | [diff] [blame] | 393 | int virt = op_x86_phys_to_virt(i); |
| 394 | if (!reset_value[virt]) |
| 395 | continue; |
| 396 | rdmsrl(msrs->controls[i].addr, val); |
| 397 | val &= model->reserved; |
| 398 | val |= op_x86_get_ctrl(model, &counter_config[virt]); |
| 399 | wrmsrl(msrs->controls[i].addr, val); |
| 400 | } |
| 401 | } |
| 402 | |
| 403 | #endif |
| 404 | |
| 405 | /* functions for op_amd_spec */ |
| 406 | |
| 407 | static void op_amd_shutdown(struct op_msrs const * const msrs) |
| 408 | { |
| 409 | int i; |
| 410 | |
Robert Richter | da169f5 | 2010-09-24 15:54:43 +0200 | [diff] [blame^] | 411 | for (i = 0; i < num_counters; ++i) { |
Robert Richter | da759fe | 2010-02-26 10:54:56 +0100 | [diff] [blame] | 412 | if (!msrs->counters[i].addr) |
| 413 | continue; |
| 414 | release_perfctr_nmi(MSR_K7_PERFCTR0 + i); |
| 415 | release_evntsel_nmi(MSR_K7_EVNTSEL0 + i); |
| 416 | } |
| 417 | } |
| 418 | |
| 419 | static int op_amd_fill_in_addresses(struct op_msrs * const msrs) |
| 420 | { |
| 421 | int i; |
| 422 | |
Robert Richter | da169f5 | 2010-09-24 15:54:43 +0200 | [diff] [blame^] | 423 | for (i = 0; i < num_counters; i++) { |
Robert Richter | da759fe | 2010-02-26 10:54:56 +0100 | [diff] [blame] | 424 | if (!reserve_perfctr_nmi(MSR_K7_PERFCTR0 + i)) |
| 425 | goto fail; |
| 426 | if (!reserve_evntsel_nmi(MSR_K7_EVNTSEL0 + i)) { |
| 427 | release_perfctr_nmi(MSR_K7_PERFCTR0 + i); |
| 428 | goto fail; |
| 429 | } |
| 430 | /* both registers must be reserved */ |
Robert Richter | da169f5 | 2010-09-24 15:54:43 +0200 | [diff] [blame^] | 431 | if (num_counters == NUM_COUNTERS_F15H) { |
| 432 | msrs->counters[i].addr = MSR_F15H_PERF_CTR + (i << 1); |
| 433 | msrs->controls[i].addr = MSR_F15H_PERF_CTL + (i << 1); |
| 434 | } else { |
| 435 | msrs->controls[i].addr = MSR_K7_EVNTSEL0 + i; |
| 436 | msrs->counters[i].addr = MSR_K7_PERFCTR0 + i; |
| 437 | } |
Robert Richter | da759fe | 2010-02-26 10:54:56 +0100 | [diff] [blame] | 438 | continue; |
| 439 | fail: |
| 440 | if (!counter_config[i].enabled) |
| 441 | continue; |
| 442 | op_x86_warn_reserved(i); |
| 443 | op_amd_shutdown(msrs); |
| 444 | return -EBUSY; |
| 445 | } |
| 446 | |
| 447 | return 0; |
| 448 | } |
| 449 | |
| 450 | static void op_amd_setup_ctrs(struct op_x86_model_spec const *model, |
| 451 | struct op_msrs const * const msrs) |
| 452 | { |
| 453 | u64 val; |
| 454 | int i; |
| 455 | |
| 456 | /* setup reset_value */ |
Robert Richter | da169f5 | 2010-09-24 15:54:43 +0200 | [diff] [blame^] | 457 | for (i = 0; i < OP_MAX_COUNTER; ++i) { |
Robert Richter | da759fe | 2010-02-26 10:54:56 +0100 | [diff] [blame] | 458 | if (counter_config[i].enabled |
| 459 | && msrs->counters[op_x86_virt_to_phys(i)].addr) |
| 460 | reset_value[i] = counter_config[i].count; |
| 461 | else |
| 462 | reset_value[i] = 0; |
| 463 | } |
| 464 | |
| 465 | /* clear all counters */ |
Robert Richter | da169f5 | 2010-09-24 15:54:43 +0200 | [diff] [blame^] | 466 | for (i = 0; i < num_counters; ++i) { |
Robert Richter | da759fe | 2010-02-26 10:54:56 +0100 | [diff] [blame] | 467 | if (!msrs->controls[i].addr) |
| 468 | continue; |
| 469 | rdmsrl(msrs->controls[i].addr, val); |
| 470 | if (val & ARCH_PERFMON_EVENTSEL_ENABLE) |
| 471 | op_x86_warn_in_use(i); |
| 472 | val &= model->reserved; |
| 473 | wrmsrl(msrs->controls[i].addr, val); |
| 474 | /* |
| 475 | * avoid a false detection of ctr overflows in NMI |
| 476 | * handler |
| 477 | */ |
| 478 | wrmsrl(msrs->counters[i].addr, -1LL); |
| 479 | } |
| 480 | |
| 481 | /* enable active counters */ |
Robert Richter | da169f5 | 2010-09-24 15:54:43 +0200 | [diff] [blame^] | 482 | for (i = 0; i < num_counters; ++i) { |
Robert Richter | da759fe | 2010-02-26 10:54:56 +0100 | [diff] [blame] | 483 | int virt = op_x86_phys_to_virt(i); |
| 484 | if (!reset_value[virt]) |
| 485 | continue; |
| 486 | |
| 487 | /* setup counter registers */ |
| 488 | wrmsrl(msrs->counters[i].addr, -(u64)reset_value[virt]); |
| 489 | |
| 490 | /* setup control registers */ |
| 491 | rdmsrl(msrs->controls[i].addr, val); |
| 492 | val &= model->reserved; |
| 493 | val |= op_x86_get_ctrl(model, &counter_config[virt]); |
| 494 | wrmsrl(msrs->controls[i].addr, val); |
| 495 | } |
Robert Richter | bae663b | 2010-05-05 17:47:17 +0200 | [diff] [blame] | 496 | |
| 497 | if (ibs_caps) |
Robert Richter | 27afdf2 | 2010-10-06 12:27:54 +0200 | [diff] [blame] | 498 | setup_APIC_ibs(); |
Robert Richter | bae663b | 2010-05-05 17:47:17 +0200 | [diff] [blame] | 499 | } |
| 500 | |
| 501 | static void op_amd_cpu_shutdown(void) |
| 502 | { |
| 503 | if (ibs_caps) |
Robert Richter | 27afdf2 | 2010-10-06 12:27:54 +0200 | [diff] [blame] | 504 | clear_APIC_ibs(); |
Robert Richter | da759fe | 2010-02-26 10:54:56 +0100 | [diff] [blame] | 505 | } |
| 506 | |
Robert Richter | 7939d2b | 2008-07-22 21:08:56 +0200 | [diff] [blame] | 507 | static int op_amd_check_ctrs(struct pt_regs * const regs, |
| 508 | struct op_msrs const * const msrs) |
| 509 | { |
Robert Richter | 42399ad | 2009-05-25 17:59:06 +0200 | [diff] [blame] | 510 | u64 val; |
Robert Richter | 7939d2b | 2008-07-22 21:08:56 +0200 | [diff] [blame] | 511 | int i; |
| 512 | |
Robert Richter | da169f5 | 2010-09-24 15:54:43 +0200 | [diff] [blame^] | 513 | for (i = 0; i < num_counters; ++i) { |
Robert Richter | d8471ad | 2009-07-16 13:04:43 +0200 | [diff] [blame] | 514 | int virt = op_x86_phys_to_virt(i); |
| 515 | if (!reset_value[virt]) |
Robert Richter | 7939d2b | 2008-07-22 21:08:56 +0200 | [diff] [blame] | 516 | continue; |
Robert Richter | 42399ad | 2009-05-25 17:59:06 +0200 | [diff] [blame] | 517 | rdmsrl(msrs->counters[i].addr, val); |
| 518 | /* bit is clear if overflowed: */ |
| 519 | if (val & OP_CTR_OVERFLOW) |
| 520 | continue; |
Robert Richter | d8471ad | 2009-07-16 13:04:43 +0200 | [diff] [blame] | 521 | oprofile_add_sample(regs, virt); |
| 522 | wrmsrl(msrs->counters[i].addr, -(u64)reset_value[virt]); |
Robert Richter | 7939d2b | 2008-07-22 21:08:56 +0200 | [diff] [blame] | 523 | } |
| 524 | |
| 525 | op_amd_handle_ibs(regs, msrs); |
| 526 | |
| 527 | /* See op_model_ppro.c */ |
| 528 | return 1; |
| 529 | } |
Paolo Ciarrocchi | d441373 | 2008-02-19 23:51:27 +0100 | [diff] [blame] | 530 | |
Robert Richter | 6657fe4 | 2008-07-22 21:08:50 +0200 | [diff] [blame] | 531 | static void op_amd_start(struct op_msrs const * const msrs) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 532 | { |
Robert Richter | dea3766 | 2009-05-25 18:11:52 +0200 | [diff] [blame] | 533 | u64 val; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 534 | int i; |
Jason Yeh | 4d4036e | 2009-07-08 13:49:38 +0200 | [diff] [blame] | 535 | |
Robert Richter | da169f5 | 2010-09-24 15:54:43 +0200 | [diff] [blame^] | 536 | for (i = 0; i < num_counters; ++i) { |
Robert Richter | d8471ad | 2009-07-16 13:04:43 +0200 | [diff] [blame] | 537 | if (!reset_value[op_x86_phys_to_virt(i)]) |
| 538 | continue; |
| 539 | rdmsrl(msrs->controls[i].addr, val); |
Robert Richter | bb1165d | 2010-03-01 14:21:23 +0100 | [diff] [blame] | 540 | val |= ARCH_PERFMON_EVENTSEL_ENABLE; |
Robert Richter | d8471ad | 2009-07-16 13:04:43 +0200 | [diff] [blame] | 541 | wrmsrl(msrs->controls[i].addr, val); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 542 | } |
Robert Richter | 852402c | 2008-07-22 21:09:06 +0200 | [diff] [blame] | 543 | |
Robert Richter | 9063759 | 2009-03-10 19:15:57 +0100 | [diff] [blame] | 544 | op_amd_start_ibs(); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 545 | } |
| 546 | |
Robert Richter | 6657fe4 | 2008-07-22 21:08:50 +0200 | [diff] [blame] | 547 | static void op_amd_stop(struct op_msrs const * const msrs) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 548 | { |
Robert Richter | dea3766 | 2009-05-25 18:11:52 +0200 | [diff] [blame] | 549 | u64 val; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 550 | int i; |
| 551 | |
Robert Richter | fd13f6c | 2008-10-19 21:00:09 +0200 | [diff] [blame] | 552 | /* |
| 553 | * Subtle: stop on all counters to avoid race with setting our |
| 554 | * pm callback |
| 555 | */ |
Robert Richter | da169f5 | 2010-09-24 15:54:43 +0200 | [diff] [blame^] | 556 | for (i = 0; i < num_counters; ++i) { |
Robert Richter | d8471ad | 2009-07-16 13:04:43 +0200 | [diff] [blame] | 557 | if (!reset_value[op_x86_phys_to_virt(i)]) |
Don Zickus | cb9c448 | 2006-09-26 10:52:26 +0200 | [diff] [blame] | 558 | continue; |
Robert Richter | dea3766 | 2009-05-25 18:11:52 +0200 | [diff] [blame] | 559 | rdmsrl(msrs->controls[i].addr, val); |
Robert Richter | bb1165d | 2010-03-01 14:21:23 +0100 | [diff] [blame] | 560 | val &= ~ARCH_PERFMON_EVENTSEL_ENABLE; |
Robert Richter | dea3766 | 2009-05-25 18:11:52 +0200 | [diff] [blame] | 561 | wrmsrl(msrs->controls[i].addr, val); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 562 | } |
Barry Kasindorf | 56784f1 | 2008-07-22 21:08:55 +0200 | [diff] [blame] | 563 | |
Robert Richter | 9063759 | 2009-03-10 19:15:57 +0100 | [diff] [blame] | 564 | op_amd_stop_ibs(); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 565 | } |
| 566 | |
Robert Richter | 27afdf2 | 2010-10-06 12:27:54 +0200 | [diff] [blame] | 567 | static int setup_ibs_ctl(int ibs_eilvt_off) |
Robert Richter | 7d77f2d | 2008-07-22 21:08:57 +0200 | [diff] [blame] | 568 | { |
Robert Richter | 7d77f2d | 2008-07-22 21:08:57 +0200 | [diff] [blame] | 569 | struct pci_dev *cpu_cfg; |
| 570 | int nodes; |
| 571 | u32 value = 0; |
Robert Richter | 7d77f2d | 2008-07-22 21:08:57 +0200 | [diff] [blame] | 572 | |
| 573 | nodes = 0; |
| 574 | cpu_cfg = NULL; |
| 575 | do { |
| 576 | cpu_cfg = pci_get_device(PCI_VENDOR_ID_AMD, |
| 577 | PCI_DEVICE_ID_AMD_10H_NB_MISC, |
| 578 | cpu_cfg); |
| 579 | if (!cpu_cfg) |
| 580 | break; |
| 581 | ++nodes; |
| 582 | pci_write_config_dword(cpu_cfg, IBSCTL, ibs_eilvt_off |
Robert Richter | 27afdf2 | 2010-10-06 12:27:54 +0200 | [diff] [blame] | 583 | | IBSCTL_LVT_OFFSET_VALID); |
Robert Richter | 7d77f2d | 2008-07-22 21:08:57 +0200 | [diff] [blame] | 584 | pci_read_config_dword(cpu_cfg, IBSCTL, &value); |
Robert Richter | 27afdf2 | 2010-10-06 12:27:54 +0200 | [diff] [blame] | 585 | if (value != (ibs_eilvt_off | IBSCTL_LVT_OFFSET_VALID)) { |
Robert Richter | 83bd924 | 2008-12-15 15:09:50 +0100 | [diff] [blame] | 586 | pci_dev_put(cpu_cfg); |
Robert Richter | 7d77f2d | 2008-07-22 21:08:57 +0200 | [diff] [blame] | 587 | printk(KERN_DEBUG "Failed to setup IBS LVT offset, " |
Robert Richter | 27afdf2 | 2010-10-06 12:27:54 +0200 | [diff] [blame] | 588 | "IBSCTL = 0x%08x\n", value); |
| 589 | return -EINVAL; |
Robert Richter | 7d77f2d | 2008-07-22 21:08:57 +0200 | [diff] [blame] | 590 | } |
| 591 | } while (1); |
| 592 | |
| 593 | if (!nodes) { |
Robert Richter | 27afdf2 | 2010-10-06 12:27:54 +0200 | [diff] [blame] | 594 | printk(KERN_DEBUG "No CPU node configured for IBS\n"); |
| 595 | return -ENODEV; |
Robert Richter | 7d77f2d | 2008-07-22 21:08:57 +0200 | [diff] [blame] | 596 | } |
| 597 | |
Robert Richter | 7d77f2d | 2008-07-22 21:08:57 +0200 | [diff] [blame] | 598 | return 0; |
| 599 | } |
| 600 | |
Robert Richter | 27afdf2 | 2010-10-06 12:27:54 +0200 | [diff] [blame] | 601 | static int force_ibs_eilvt_setup(void) |
| 602 | { |
| 603 | int i; |
| 604 | int ret; |
| 605 | |
| 606 | /* find the next free available EILVT entry */ |
| 607 | for (i = 1; i < 4; i++) { |
| 608 | if (!eilvt_is_available(i)) |
| 609 | continue; |
| 610 | ret = setup_ibs_ctl(i); |
| 611 | if (ret) |
| 612 | return ret; |
| 613 | return 0; |
| 614 | } |
| 615 | |
| 616 | printk(KERN_DEBUG "No EILVT entry available\n"); |
| 617 | |
| 618 | return -EBUSY; |
| 619 | } |
| 620 | |
| 621 | static int __init_ibs_nmi(void) |
| 622 | { |
| 623 | int ret; |
| 624 | |
| 625 | if (ibs_eilvt_valid()) |
| 626 | return 0; |
| 627 | |
| 628 | ret = force_ibs_eilvt_setup(); |
| 629 | if (ret) |
| 630 | return ret; |
| 631 | |
| 632 | if (!ibs_eilvt_valid()) |
| 633 | return -EFAULT; |
| 634 | |
| 635 | pr_err(FW_BUG "workaround enabled for IBS LVT offset\n"); |
| 636 | |
| 637 | return 0; |
| 638 | } |
| 639 | |
Robert Richter | fd13f6c | 2008-10-19 21:00:09 +0200 | [diff] [blame] | 640 | /* initialize the APIC for the IBS interrupts if available */ |
Robert Richter | bae663b | 2010-05-05 17:47:17 +0200 | [diff] [blame] | 641 | static void init_ibs(void) |
Barry Kasindorf | 56784f1 | 2008-07-22 21:08:55 +0200 | [diff] [blame] | 642 | { |
Robert Richter | 64683da | 2010-02-04 10:57:23 +0100 | [diff] [blame] | 643 | ibs_caps = get_ibs_caps(); |
Barry Kasindorf | 56784f1 | 2008-07-22 21:08:55 +0200 | [diff] [blame] | 644 | |
Robert Richter | 64683da | 2010-02-04 10:57:23 +0100 | [diff] [blame] | 645 | if (!ibs_caps) |
Barry Kasindorf | 56784f1 | 2008-07-22 21:08:55 +0200 | [diff] [blame] | 646 | return; |
| 647 | |
Robert Richter | bae663b | 2010-05-05 17:47:17 +0200 | [diff] [blame] | 648 | if (__init_ibs_nmi()) { |
Robert Richter | 64683da | 2010-02-04 10:57:23 +0100 | [diff] [blame] | 649 | ibs_caps = 0; |
Robert Richter | 852402c | 2008-07-22 21:09:06 +0200 | [diff] [blame] | 650 | return; |
| 651 | } |
| 652 | |
Robert Richter | 64683da | 2010-02-04 10:57:23 +0100 | [diff] [blame] | 653 | printk(KERN_INFO "oprofile: AMD IBS detected (0x%08x)\n", |
| 654 | (unsigned)ibs_caps); |
Barry Kasindorf | 56784f1 | 2008-07-22 21:08:55 +0200 | [diff] [blame] | 655 | } |
| 656 | |
Robert Richter | 25ad2913 | 2008-09-05 17:12:36 +0200 | [diff] [blame] | 657 | static int (*create_arch_files)(struct super_block *sb, struct dentry *root); |
Robert Richter | 270d3e1 | 2008-07-22 21:09:01 +0200 | [diff] [blame] | 658 | |
Robert Richter | 25ad2913 | 2008-09-05 17:12:36 +0200 | [diff] [blame] | 659 | static int setup_ibs_files(struct super_block *sb, struct dentry *root) |
Barry Kasindorf | 56784f1 | 2008-07-22 21:08:55 +0200 | [diff] [blame] | 660 | { |
Barry Kasindorf | 56784f1 | 2008-07-22 21:08:55 +0200 | [diff] [blame] | 661 | struct dentry *dir; |
Robert Richter | 270d3e1 | 2008-07-22 21:09:01 +0200 | [diff] [blame] | 662 | int ret = 0; |
| 663 | |
| 664 | /* architecture specific files */ |
| 665 | if (create_arch_files) |
| 666 | ret = create_arch_files(sb, root); |
| 667 | |
| 668 | if (ret) |
| 669 | return ret; |
Barry Kasindorf | 56784f1 | 2008-07-22 21:08:55 +0200 | [diff] [blame] | 670 | |
Robert Richter | 64683da | 2010-02-04 10:57:23 +0100 | [diff] [blame] | 671 | if (!ibs_caps) |
Robert Richter | 270d3e1 | 2008-07-22 21:09:01 +0200 | [diff] [blame] | 672 | return ret; |
| 673 | |
| 674 | /* model specific files */ |
Barry Kasindorf | 56784f1 | 2008-07-22 21:08:55 +0200 | [diff] [blame] | 675 | |
| 676 | /* setup some reasonable defaults */ |
Robert Richter | 25da695 | 2010-09-21 15:49:31 +0200 | [diff] [blame] | 677 | memset(&ibs_config, 0, sizeof(ibs_config)); |
Barry Kasindorf | 56784f1 | 2008-07-22 21:08:55 +0200 | [diff] [blame] | 678 | ibs_config.max_cnt_fetch = 250000; |
Barry Kasindorf | 56784f1 | 2008-07-22 21:08:55 +0200 | [diff] [blame] | 679 | ibs_config.max_cnt_op = 250000; |
Robert Richter | 2d55a47 | 2008-07-18 17:56:05 +0200 | [diff] [blame] | 680 | |
Robert Richter | 4ac945f | 2010-09-21 15:58:32 +0200 | [diff] [blame] | 681 | if (ibs_caps & IBS_CAPS_FETCHSAM) { |
| 682 | dir = oprofilefs_mkdir(sb, root, "ibs_fetch"); |
| 683 | oprofilefs_create_ulong(sb, dir, "enable", |
| 684 | &ibs_config.fetch_enabled); |
| 685 | oprofilefs_create_ulong(sb, dir, "max_count", |
| 686 | &ibs_config.max_cnt_fetch); |
| 687 | oprofilefs_create_ulong(sb, dir, "rand_enable", |
| 688 | &ibs_config.rand_en); |
| 689 | } |
Robert Richter | 2d55a47 | 2008-07-18 17:56:05 +0200 | [diff] [blame] | 690 | |
Robert Richter | 4ac945f | 2010-09-21 15:58:32 +0200 | [diff] [blame] | 691 | if (ibs_caps & IBS_CAPS_OPSAM) { |
| 692 | dir = oprofilefs_mkdir(sb, root, "ibs_op"); |
| 693 | oprofilefs_create_ulong(sb, dir, "enable", |
| 694 | &ibs_config.op_enabled); |
| 695 | oprofilefs_create_ulong(sb, dir, "max_count", |
| 696 | &ibs_config.max_cnt_op); |
| 697 | if (ibs_caps & IBS_CAPS_OPCNT) |
| 698 | oprofilefs_create_ulong(sb, dir, "dispatched_ops", |
| 699 | &ibs_config.dispatched_ops); |
Robert Richter | 25da695 | 2010-09-21 15:49:31 +0200 | [diff] [blame] | 700 | if (ibs_caps & IBS_CAPS_BRNTRGT) |
| 701 | oprofilefs_create_ulong(sb, dir, "branch_target", |
| 702 | &ibs_config.branch_target); |
Robert Richter | 4ac945f | 2010-09-21 15:58:32 +0200 | [diff] [blame] | 703 | } |
Robert Richter | fc2bd73 | 2008-07-22 21:09:00 +0200 | [diff] [blame] | 704 | |
| 705 | return 0; |
Barry Kasindorf | 56784f1 | 2008-07-22 21:08:55 +0200 | [diff] [blame] | 706 | } |
| 707 | |
Robert Richter | da169f5 | 2010-09-24 15:54:43 +0200 | [diff] [blame^] | 708 | struct op_x86_model_spec op_amd_spec; |
| 709 | |
Robert Richter | adf5ec0 | 2008-07-22 21:08:48 +0200 | [diff] [blame] | 710 | static int op_amd_init(struct oprofile_operations *ops) |
| 711 | { |
Robert Richter | bae663b | 2010-05-05 17:47:17 +0200 | [diff] [blame] | 712 | init_ibs(); |
Robert Richter | 270d3e1 | 2008-07-22 21:09:01 +0200 | [diff] [blame] | 713 | create_arch_files = ops->create_files; |
| 714 | ops->create_files = setup_ibs_files; |
Robert Richter | da169f5 | 2010-09-24 15:54:43 +0200 | [diff] [blame^] | 715 | |
| 716 | if (boot_cpu_data.x86 == 0x15) { |
| 717 | num_counters = NUM_COUNTERS_F15H; |
| 718 | } else { |
| 719 | num_counters = NUM_COUNTERS; |
| 720 | } |
| 721 | |
| 722 | op_amd_spec.num_counters = num_counters; |
| 723 | op_amd_spec.num_controls = num_counters; |
| 724 | op_amd_spec.num_virt_counters = max(num_counters, NUM_VIRT_COUNTERS); |
| 725 | |
Robert Richter | adf5ec0 | 2008-07-22 21:08:48 +0200 | [diff] [blame] | 726 | return 0; |
| 727 | } |
| 728 | |
Robert Richter | 259a83a | 2009-07-09 15:12:35 +0200 | [diff] [blame] | 729 | struct op_x86_model_spec op_amd_spec = { |
Robert Richter | da169f5 | 2010-09-24 15:54:43 +0200 | [diff] [blame^] | 730 | /* num_counters/num_controls filled in at runtime */ |
Robert Richter | 3370d35 | 2009-05-25 15:10:32 +0200 | [diff] [blame] | 731 | .reserved = MSR_AMD_EVENTSEL_RESERVED, |
| 732 | .event_mask = OP_EVENT_MASK, |
| 733 | .init = op_amd_init, |
Robert Richter | c92960f | 2008-09-05 17:12:36 +0200 | [diff] [blame] | 734 | .fill_in_addresses = &op_amd_fill_in_addresses, |
| 735 | .setup_ctrs = &op_amd_setup_ctrs, |
Robert Richter | bae663b | 2010-05-05 17:47:17 +0200 | [diff] [blame] | 736 | .cpu_down = &op_amd_cpu_shutdown, |
Robert Richter | c92960f | 2008-09-05 17:12:36 +0200 | [diff] [blame] | 737 | .check_ctrs = &op_amd_check_ctrs, |
| 738 | .start = &op_amd_start, |
| 739 | .stop = &op_amd_stop, |
Robert Richter | 3370d35 | 2009-05-25 15:10:32 +0200 | [diff] [blame] | 740 | .shutdown = &op_amd_shutdown, |
Jason Yeh | 4d4036e | 2009-07-08 13:49:38 +0200 | [diff] [blame] | 741 | #ifdef CONFIG_OPROFILE_EVENT_MULTIPLEX |
Robert Richter | 7e7478c | 2009-07-16 13:09:53 +0200 | [diff] [blame] | 742 | .switch_ctrl = &op_mux_switch_ctrl, |
Jason Yeh | 4d4036e | 2009-07-08 13:49:38 +0200 | [diff] [blame] | 743 | #endif |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 744 | }; |