Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1 | /* |
| 2 | * Carsten Langgaard, carstenl@mips.com |
| 3 | * Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved. |
| 4 | * |
| 5 | * This program is free software; you can distribute it and/or modify it |
| 6 | * under the terms of the GNU General Public License (Version 2) as |
| 7 | * published by the Free Software Foundation. |
| 8 | * |
| 9 | * This program is distributed in the hope it will be useful, but WITHOUT |
| 10 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
| 11 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
| 12 | * for more details. |
| 13 | * |
| 14 | * You should have received a copy of the GNU General Public License along |
| 15 | * with this program; if not, write to the Free Software Foundation, Inc., |
| 16 | * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. |
| 17 | * |
| 18 | * Setting up the clock on the MIPS boards. |
| 19 | */ |
| 20 | |
| 21 | #include <linux/types.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 22 | #include <linux/init.h> |
| 23 | #include <linux/kernel_stat.h> |
| 24 | #include <linux/sched.h> |
| 25 | #include <linux/spinlock.h> |
| 26 | #include <linux/interrupt.h> |
| 27 | #include <linux/time.h> |
| 28 | #include <linux/timex.h> |
| 29 | #include <linux/mc146818rtc.h> |
| 30 | |
| 31 | #include <asm/mipsregs.h> |
Ralf Baechle | 41c594a | 2006-04-05 09:45:45 +0100 | [diff] [blame] | 32 | #include <asm/mipsmtregs.h> |
Ralf Baechle | e01402b | 2005-07-14 15:57:16 +0000 | [diff] [blame] | 33 | #include <asm/hardirq.h> |
Ralf Baechle | d865bea | 2007-10-11 23:46:10 +0100 | [diff] [blame] | 34 | #include <asm/i8253.h> |
Ralf Baechle | e01402b | 2005-07-14 15:57:16 +0000 | [diff] [blame] | 35 | #include <asm/irq.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 36 | #include <asm/div64.h> |
| 37 | #include <asm/cpu.h> |
| 38 | #include <asm/time.h> |
| 39 | #include <asm/mc146818-time.h> |
Ralf Baechle | e01402b | 2005-07-14 15:57:16 +0000 | [diff] [blame] | 40 | #include <asm/msc01_ic.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 41 | |
| 42 | #include <asm/mips-boards/generic.h> |
| 43 | #include <asm/mips-boards/prom.h> |
Maciej W. Rozycki | fc095a9 | 2006-09-12 19:12:18 +0100 | [diff] [blame] | 44 | |
| 45 | #ifdef CONFIG_MIPS_ATLAS |
| 46 | #include <asm/mips-boards/atlasint.h> |
| 47 | #endif |
| 48 | #ifdef CONFIG_MIPS_MALTA |
Ralf Baechle | e01402b | 2005-07-14 15:57:16 +0000 | [diff] [blame] | 49 | #include <asm/mips-boards/maltaint.h> |
Maciej W. Rozycki | fc095a9 | 2006-09-12 19:12:18 +0100 | [diff] [blame] | 50 | #endif |
Atsushi Nemoto | f75f369 | 2007-01-08 01:27:40 +0900 | [diff] [blame] | 51 | #ifdef CONFIG_MIPS_SEAD |
| 52 | #include <asm/mips-boards/seadint.h> |
| 53 | #endif |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 54 | |
| 55 | unsigned long cpu_khz; |
| 56 | |
Ralf Baechle | e01402b | 2005-07-14 15:57:16 +0000 | [diff] [blame] | 57 | static int mips_cpu_timer_irq; |
Ralf Baechle | 39b8d52 | 2008-04-28 17:14:26 +0100 | [diff] [blame] | 58 | static int mips_cpu_perf_irq; |
Ralf Baechle | 3b1d4ed | 2007-06-20 22:27:10 +0100 | [diff] [blame] | 59 | extern int cp0_perfcount_irq; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 60 | |
Ralf Baechle | 39b8d52 | 2008-04-28 17:14:26 +0100 | [diff] [blame] | 61 | DEFINE_PER_CPU(unsigned int, tickcount); |
| 62 | #define tickcount_this_cpu __get_cpu_var(tickcount) |
| 63 | static unsigned long ledbitmask; |
| 64 | |
Ralf Baechle | 937a801 | 2006-10-07 19:44:33 +0100 | [diff] [blame] | 65 | static void mips_timer_dispatch(void) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 66 | { |
Ralf Baechle | 39b8d52 | 2008-04-28 17:14:26 +0100 | [diff] [blame] | 67 | #if defined(CONFIG_MIPS_MALTA) || defined(CONFIG_MIPS_ATLAS) |
| 68 | /* |
| 69 | * Yes, this is very tacky, won't work as expected with SMTC and |
| 70 | * dyntick will break it, |
| 71 | * but it gives me a nice warm feeling during debug |
| 72 | */ |
| 73 | #define LEDBAR 0xbf000408 |
| 74 | if (tickcount_this_cpu++ >= HZ) { |
| 75 | tickcount_this_cpu = 0; |
| 76 | change_bit(smp_processor_id(), &ledbitmask); |
| 77 | smp_wmb(); /* Make sure every one else sees the change */ |
| 78 | /* This will pick up any recent changes made by other CPU's */ |
| 79 | *(unsigned int *)LEDBAR = ledbitmask; |
| 80 | } |
| 81 | #endif |
Ralf Baechle | 937a801 | 2006-10-07 19:44:33 +0100 | [diff] [blame] | 82 | do_IRQ(mips_cpu_timer_irq); |
Ralf Baechle | e01402b | 2005-07-14 15:57:16 +0000 | [diff] [blame] | 83 | } |
| 84 | |
Chris Dearman | ffe9ee4 | 2007-05-24 22:24:20 +0100 | [diff] [blame] | 85 | static void mips_perf_dispatch(void) |
| 86 | { |
Ralf Baechle | 39b8d52 | 2008-04-28 17:14:26 +0100 | [diff] [blame] | 87 | do_IRQ(mips_cpu_perf_irq); |
Chris Dearman | ffe9ee4 | 2007-05-24 22:24:20 +0100 | [diff] [blame] | 88 | } |
| 89 | |
Ralf Baechle | 41c594a | 2006-04-05 09:45:45 +0100 | [diff] [blame] | 90 | /* |
Ralf Baechle | 224dc50 | 2006-10-21 02:05:20 +0100 | [diff] [blame] | 91 | * Estimate CPU frequency. Sets mips_hpt_frequency as a side-effect |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 92 | */ |
| 93 | static unsigned int __init estimate_cpu_frequency(void) |
| 94 | { |
| 95 | unsigned int prid = read_c0_prid() & 0xffff00; |
| 96 | unsigned int count; |
| 97 | |
Ralf Baechle | 41c594a | 2006-04-05 09:45:45 +0100 | [diff] [blame] | 98 | #if defined(CONFIG_MIPS_SEAD) || defined(CONFIG_MIPS_SIM) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 99 | /* |
| 100 | * The SEAD board doesn't have a real time clock, so we can't |
| 101 | * really calculate the timer frequency |
| 102 | * For now we hardwire the SEAD board frequency to 12MHz. |
| 103 | */ |
Ralf Baechle | 42a3b4f | 2005-09-03 15:56:17 -0700 | [diff] [blame] | 104 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 105 | if ((prid == (PRID_COMP_MIPS | PRID_IMP_20KC)) || |
| 106 | (prid == (PRID_COMP_MIPS | PRID_IMP_25KF))) |
| 107 | count = 12000000; |
| 108 | else |
| 109 | count = 6000000; |
| 110 | #endif |
| 111 | #if defined(CONFIG_MIPS_ATLAS) || defined(CONFIG_MIPS_MALTA) |
Ralf Baechle | e79f55a | 2006-10-31 19:53:15 +0000 | [diff] [blame] | 112 | unsigned long flags; |
Ralf Baechle | 70e46f4 | 2006-10-31 18:33:09 +0000 | [diff] [blame] | 113 | unsigned int start; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 114 | |
| 115 | local_irq_save(flags); |
| 116 | |
| 117 | /* Start counter exactly on falling edge of update flag */ |
| 118 | while (CMOS_READ(RTC_REG_A) & RTC_UIP); |
| 119 | while (!(CMOS_READ(RTC_REG_A) & RTC_UIP)); |
| 120 | |
| 121 | /* Start r4k counter. */ |
Ralf Baechle | 70e46f4 | 2006-10-31 18:33:09 +0000 | [diff] [blame] | 122 | start = read_c0_count(); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 123 | |
| 124 | /* Read counter exactly on falling edge of update flag */ |
| 125 | while (CMOS_READ(RTC_REG_A) & RTC_UIP); |
| 126 | while (!(CMOS_READ(RTC_REG_A) & RTC_UIP)); |
| 127 | |
Ralf Baechle | 70e46f4 | 2006-10-31 18:33:09 +0000 | [diff] [blame] | 128 | count = read_c0_count() - start; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 129 | |
| 130 | /* restore interrupts */ |
| 131 | local_irq_restore(flags); |
| 132 | #endif |
| 133 | |
| 134 | mips_hpt_frequency = count; |
| 135 | if ((prid != (PRID_COMP_MIPS | PRID_IMP_20KC)) && |
| 136 | (prid != (PRID_COMP_MIPS | PRID_IMP_25KF))) |
| 137 | count *= 2; |
| 138 | |
| 139 | count += 5000; /* round */ |
| 140 | count -= count%10000; |
| 141 | |
| 142 | return count; |
| 143 | } |
| 144 | |
Ralf Baechle | 4b55048 | 2007-10-11 23:46:08 +0100 | [diff] [blame] | 145 | unsigned long read_persistent_clock(void) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 146 | { |
| 147 | return mc146818_get_cmos_time(); |
| 148 | } |
| 149 | |
Ralf Baechle | 91a2fcc | 2007-10-11 23:46:09 +0100 | [diff] [blame] | 150 | void __init plat_perf_setup(void) |
Chris Dearman | ffe9ee4 | 2007-05-24 22:24:20 +0100 | [diff] [blame] | 151 | { |
Chris Dearman | ffe9ee4 | 2007-05-24 22:24:20 +0100 | [diff] [blame] | 152 | #ifdef MSC01E_INT_BASE |
| 153 | if (cpu_has_veic) { |
Ralf Baechle | 49a89ef | 2007-10-11 23:46:15 +0100 | [diff] [blame] | 154 | set_vi_handler(MSC01E_INT_PERFCTR, mips_perf_dispatch); |
Ralf Baechle | 39b8d52 | 2008-04-28 17:14:26 +0100 | [diff] [blame] | 155 | mips_cpu_perf_irq = MSC01E_INT_BASE + MSC01E_INT_PERFCTR; |
Chris Dearman | ffe9ee4 | 2007-05-24 22:24:20 +0100 | [diff] [blame] | 156 | } else |
| 157 | #endif |
Ralf Baechle | 3b1d4ed | 2007-06-20 22:27:10 +0100 | [diff] [blame] | 158 | if (cp0_perfcount_irq >= 0) { |
| 159 | if (cpu_has_vint) |
| 160 | set_vi_handler(cp0_perfcount_irq, mips_perf_dispatch); |
Ralf Baechle | 39b8d52 | 2008-04-28 17:14:26 +0100 | [diff] [blame] | 161 | mips_cpu_perf_irq = MIPS_CPU_IRQ_BASE + cp0_perfcount_irq; |
Chris Dearman | ffe9ee4 | 2007-05-24 22:24:20 +0100 | [diff] [blame] | 162 | #ifdef CONFIG_SMP |
Ralf Baechle | 39b8d52 | 2008-04-28 17:14:26 +0100 | [diff] [blame] | 163 | set_irq_handler(mips_cpu_perf_irq, handle_percpu_irq); |
Chris Dearman | ffe9ee4 | 2007-05-24 22:24:20 +0100 | [diff] [blame] | 164 | #endif |
| 165 | } |
| 166 | } |
| 167 | |
Ralf Baechle | 234fcd1 | 2008-03-08 09:56:28 +0000 | [diff] [blame] | 168 | unsigned int __cpuinit get_c0_compare_int(void) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 169 | { |
Chris Dearman | 7b4f4ec | 2007-05-24 22:46:25 +0100 | [diff] [blame] | 170 | #ifdef MSC01E_INT_BASE |
Ralf Baechle | e01402b | 2005-07-14 15:57:16 +0000 | [diff] [blame] | 171 | if (cpu_has_veic) { |
Ralf Baechle | 49a89ef | 2007-10-11 23:46:15 +0100 | [diff] [blame] | 172 | set_vi_handler(MSC01E_INT_CPUCTR, mips_timer_dispatch); |
Ralf Baechle | e01402b | 2005-07-14 15:57:16 +0000 | [diff] [blame] | 173 | mips_cpu_timer_irq = MSC01E_INT_BASE + MSC01E_INT_CPUCTR; |
Ralf Baechle | 38760d4 | 2007-10-29 14:23:43 +0000 | [diff] [blame] | 174 | } else |
Chris Dearman | 7b4f4ec | 2007-05-24 22:46:25 +0100 | [diff] [blame] | 175 | #endif |
| 176 | { |
Chris Dearman | ffe9ee4 | 2007-05-24 22:24:20 +0100 | [diff] [blame] | 177 | if (cpu_has_vint) |
Ralf Baechle | 3b1d4ed | 2007-06-20 22:27:10 +0100 | [diff] [blame] | 178 | set_vi_handler(cp0_compare_irq, mips_timer_dispatch); |
| 179 | mips_cpu_timer_irq = MIPS_CPU_IRQ_BASE + cp0_compare_irq; |
Chris Dearman | ffe9ee4 | 2007-05-24 22:24:20 +0100 | [diff] [blame] | 180 | } |
Ralf Baechle | e01402b | 2005-07-14 15:57:16 +0000 | [diff] [blame] | 181 | |
Ralf Baechle | 38760d4 | 2007-10-29 14:23:43 +0000 | [diff] [blame] | 182 | return mips_cpu_timer_irq; |
| 183 | } |
| 184 | |
| 185 | void __init plat_time_init(void) |
| 186 | { |
| 187 | unsigned int est_freq; |
| 188 | |
| 189 | /* Set Data mode - binary. */ |
| 190 | CMOS_WRITE(CMOS_READ(RTC_CONTROL) | RTC_DM_BINARY, RTC_CONTROL); |
| 191 | |
| 192 | est_freq = estimate_cpu_frequency(); |
| 193 | |
| 194 | printk("CPU frequency %d.%02d MHz\n", est_freq/1000000, |
| 195 | (est_freq%1000000)*100/1000000); |
| 196 | |
| 197 | cpu_khz = est_freq / 1000; |
| 198 | |
| 199 | mips_scroll_message(); |
| 200 | #ifdef CONFIG_I8253 /* Only Malta has a PIT */ |
| 201 | setup_pit_timer(); |
Ralf Baechle | 340ee4b | 2005-08-17 17:44:08 +0000 | [diff] [blame] | 202 | #endif |
Chris Dearman | ffe9ee4 | 2007-05-24 22:24:20 +0100 | [diff] [blame] | 203 | |
Ralf Baechle | 91a2fcc | 2007-10-11 23:46:09 +0100 | [diff] [blame] | 204 | plat_perf_setup(); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 205 | } |