Thierry Reding | d8f4a9e | 2012-11-15 21:28:22 +0000 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (C) 2012 Avionic Design GmbH |
| 3 | * Copyright (C) 2012 NVIDIA CORPORATION. All rights reserved. |
| 4 | * |
| 5 | * This program is free software; you can redistribute it and/or modify |
| 6 | * it under the terms of the GNU General Public License version 2 as |
| 7 | * published by the Free Software Foundation. |
| 8 | */ |
| 9 | |
| 10 | #include <linux/clk.h> |
Thierry Reding | 9eb9b22 | 2013-09-24 16:32:47 +0200 | [diff] [blame] | 11 | #include <linux/debugfs.h> |
Thierry Reding | df06b75 | 2014-06-26 21:41:53 +0200 | [diff] [blame^] | 12 | #include <linux/iommu.h> |
Stephen Warren | ca48080 | 2013-11-06 16:20:54 -0700 | [diff] [blame] | 13 | #include <linux/reset.h> |
Thierry Reding | d8f4a9e | 2012-11-15 21:28:22 +0000 | [diff] [blame] | 14 | |
Thierry Reding | 9c01270 | 2014-07-07 15:32:53 +0200 | [diff] [blame] | 15 | #include <soc/tegra/pmc.h> |
| 16 | |
Arto Merilainen | de2ba66 | 2013-03-22 16:34:08 +0200 | [diff] [blame] | 17 | #include "dc.h" |
| 18 | #include "drm.h" |
| 19 | #include "gem.h" |
Thierry Reding | d8f4a9e | 2012-11-15 21:28:22 +0000 | [diff] [blame] | 20 | |
Thierry Reding | 8620fc6 | 2013-12-12 11:03:59 +0100 | [diff] [blame] | 21 | struct tegra_dc_soc_info { |
| 22 | bool supports_interlacing; |
Thierry Reding | e687651 | 2013-12-20 13:58:33 +0100 | [diff] [blame] | 23 | bool supports_cursor; |
Thierry Reding | c134f01 | 2014-06-03 14:48:12 +0200 | [diff] [blame] | 24 | bool supports_block_linear; |
Thierry Reding | d1f3e1e | 2014-07-11 08:29:14 +0200 | [diff] [blame] | 25 | unsigned int pitch_align; |
Thierry Reding | 9c01270 | 2014-07-07 15:32:53 +0200 | [diff] [blame] | 26 | bool has_powergate; |
Thierry Reding | 8620fc6 | 2013-12-12 11:03:59 +0100 | [diff] [blame] | 27 | }; |
| 28 | |
Thierry Reding | f34bc78 | 2012-11-04 21:47:13 +0100 | [diff] [blame] | 29 | struct tegra_plane { |
| 30 | struct drm_plane base; |
| 31 | unsigned int index; |
Thierry Reding | d8f4a9e | 2012-11-15 21:28:22 +0000 | [diff] [blame] | 32 | }; |
| 33 | |
Thierry Reding | f34bc78 | 2012-11-04 21:47:13 +0100 | [diff] [blame] | 34 | static inline struct tegra_plane *to_tegra_plane(struct drm_plane *plane) |
| 35 | { |
| 36 | return container_of(plane, struct tegra_plane, base); |
| 37 | } |
| 38 | |
Thierry Reding | 10288ee | 2014-03-14 09:54:58 +0100 | [diff] [blame] | 39 | static unsigned int tegra_dc_format(uint32_t format, uint32_t *swap) |
| 40 | { |
| 41 | /* assume no swapping of fetched data */ |
| 42 | if (swap) |
| 43 | *swap = BYTE_SWAP_NOSWAP; |
| 44 | |
| 45 | switch (format) { |
| 46 | case DRM_FORMAT_XBGR8888: |
| 47 | return WIN_COLOR_DEPTH_R8G8B8A8; |
| 48 | |
| 49 | case DRM_FORMAT_XRGB8888: |
| 50 | return WIN_COLOR_DEPTH_B8G8R8A8; |
| 51 | |
| 52 | case DRM_FORMAT_RGB565: |
| 53 | return WIN_COLOR_DEPTH_B5G6R5; |
| 54 | |
| 55 | case DRM_FORMAT_UYVY: |
| 56 | return WIN_COLOR_DEPTH_YCbCr422; |
| 57 | |
| 58 | case DRM_FORMAT_YUYV: |
| 59 | if (swap) |
| 60 | *swap = BYTE_SWAP_SWAP2; |
| 61 | |
| 62 | return WIN_COLOR_DEPTH_YCbCr422; |
| 63 | |
| 64 | case DRM_FORMAT_YUV420: |
| 65 | return WIN_COLOR_DEPTH_YCbCr420P; |
| 66 | |
| 67 | case DRM_FORMAT_YUV422: |
| 68 | return WIN_COLOR_DEPTH_YCbCr422P; |
| 69 | |
| 70 | default: |
| 71 | break; |
| 72 | } |
| 73 | |
| 74 | WARN(1, "unsupported pixel format %u, using default\n", format); |
| 75 | return WIN_COLOR_DEPTH_B8G8R8A8; |
| 76 | } |
| 77 | |
| 78 | static bool tegra_dc_format_is_yuv(unsigned int format, bool *planar) |
| 79 | { |
| 80 | switch (format) { |
| 81 | case WIN_COLOR_DEPTH_YCbCr422: |
| 82 | case WIN_COLOR_DEPTH_YUV422: |
| 83 | if (planar) |
| 84 | *planar = false; |
| 85 | |
| 86 | return true; |
| 87 | |
| 88 | case WIN_COLOR_DEPTH_YCbCr420P: |
| 89 | case WIN_COLOR_DEPTH_YUV420P: |
| 90 | case WIN_COLOR_DEPTH_YCbCr422P: |
| 91 | case WIN_COLOR_DEPTH_YUV422P: |
| 92 | case WIN_COLOR_DEPTH_YCbCr422R: |
| 93 | case WIN_COLOR_DEPTH_YUV422R: |
| 94 | case WIN_COLOR_DEPTH_YCbCr422RA: |
| 95 | case WIN_COLOR_DEPTH_YUV422RA: |
| 96 | if (planar) |
| 97 | *planar = true; |
| 98 | |
| 99 | return true; |
| 100 | } |
| 101 | |
| 102 | return false; |
| 103 | } |
| 104 | |
| 105 | static inline u32 compute_dda_inc(unsigned int in, unsigned int out, bool v, |
| 106 | unsigned int bpp) |
| 107 | { |
| 108 | fixed20_12 outf = dfixed_init(out); |
| 109 | fixed20_12 inf = dfixed_init(in); |
| 110 | u32 dda_inc; |
| 111 | int max; |
| 112 | |
| 113 | if (v) |
| 114 | max = 15; |
| 115 | else { |
| 116 | switch (bpp) { |
| 117 | case 2: |
| 118 | max = 8; |
| 119 | break; |
| 120 | |
| 121 | default: |
| 122 | WARN_ON_ONCE(1); |
| 123 | /* fallthrough */ |
| 124 | case 4: |
| 125 | max = 4; |
| 126 | break; |
| 127 | } |
| 128 | } |
| 129 | |
| 130 | outf.full = max_t(u32, outf.full - dfixed_const(1), dfixed_const(1)); |
| 131 | inf.full -= dfixed_const(1); |
| 132 | |
| 133 | dda_inc = dfixed_div(inf, outf); |
| 134 | dda_inc = min_t(u32, dda_inc, dfixed_const(max)); |
| 135 | |
| 136 | return dda_inc; |
| 137 | } |
| 138 | |
| 139 | static inline u32 compute_initial_dda(unsigned int in) |
| 140 | { |
| 141 | fixed20_12 inf = dfixed_init(in); |
| 142 | return dfixed_frac(inf); |
| 143 | } |
| 144 | |
| 145 | static int tegra_dc_setup_window(struct tegra_dc *dc, unsigned int index, |
| 146 | const struct tegra_dc_window *window) |
| 147 | { |
| 148 | unsigned h_offset, v_offset, h_size, v_size, h_dda, v_dda, bpp; |
| 149 | unsigned long value; |
| 150 | bool yuv, planar; |
| 151 | |
| 152 | /* |
| 153 | * For YUV planar modes, the number of bytes per pixel takes into |
| 154 | * account only the luma component and therefore is 1. |
| 155 | */ |
| 156 | yuv = tegra_dc_format_is_yuv(window->format, &planar); |
| 157 | if (!yuv) |
| 158 | bpp = window->bits_per_pixel / 8; |
| 159 | else |
| 160 | bpp = planar ? 1 : 2; |
| 161 | |
| 162 | value = WINDOW_A_SELECT << index; |
| 163 | tegra_dc_writel(dc, value, DC_CMD_DISPLAY_WINDOW_HEADER); |
| 164 | |
| 165 | tegra_dc_writel(dc, window->format, DC_WIN_COLOR_DEPTH); |
| 166 | tegra_dc_writel(dc, window->swap, DC_WIN_BYTE_SWAP); |
| 167 | |
| 168 | value = V_POSITION(window->dst.y) | H_POSITION(window->dst.x); |
| 169 | tegra_dc_writel(dc, value, DC_WIN_POSITION); |
| 170 | |
| 171 | value = V_SIZE(window->dst.h) | H_SIZE(window->dst.w); |
| 172 | tegra_dc_writel(dc, value, DC_WIN_SIZE); |
| 173 | |
| 174 | h_offset = window->src.x * bpp; |
| 175 | v_offset = window->src.y; |
| 176 | h_size = window->src.w * bpp; |
| 177 | v_size = window->src.h; |
| 178 | |
| 179 | value = V_PRESCALED_SIZE(v_size) | H_PRESCALED_SIZE(h_size); |
| 180 | tegra_dc_writel(dc, value, DC_WIN_PRESCALED_SIZE); |
| 181 | |
| 182 | /* |
| 183 | * For DDA computations the number of bytes per pixel for YUV planar |
| 184 | * modes needs to take into account all Y, U and V components. |
| 185 | */ |
| 186 | if (yuv && planar) |
| 187 | bpp = 2; |
| 188 | |
| 189 | h_dda = compute_dda_inc(window->src.w, window->dst.w, false, bpp); |
| 190 | v_dda = compute_dda_inc(window->src.h, window->dst.h, true, bpp); |
| 191 | |
| 192 | value = V_DDA_INC(v_dda) | H_DDA_INC(h_dda); |
| 193 | tegra_dc_writel(dc, value, DC_WIN_DDA_INC); |
| 194 | |
| 195 | h_dda = compute_initial_dda(window->src.x); |
| 196 | v_dda = compute_initial_dda(window->src.y); |
| 197 | |
| 198 | tegra_dc_writel(dc, h_dda, DC_WIN_H_INITIAL_DDA); |
| 199 | tegra_dc_writel(dc, v_dda, DC_WIN_V_INITIAL_DDA); |
| 200 | |
| 201 | tegra_dc_writel(dc, 0, DC_WIN_UV_BUF_STRIDE); |
| 202 | tegra_dc_writel(dc, 0, DC_WIN_BUF_STRIDE); |
| 203 | |
| 204 | tegra_dc_writel(dc, window->base[0], DC_WINBUF_START_ADDR); |
| 205 | |
| 206 | if (yuv && planar) { |
| 207 | tegra_dc_writel(dc, window->base[1], DC_WINBUF_START_ADDR_U); |
| 208 | tegra_dc_writel(dc, window->base[2], DC_WINBUF_START_ADDR_V); |
| 209 | value = window->stride[1] << 16 | window->stride[0]; |
| 210 | tegra_dc_writel(dc, value, DC_WIN_LINE_STRIDE); |
| 211 | } else { |
| 212 | tegra_dc_writel(dc, window->stride[0], DC_WIN_LINE_STRIDE); |
| 213 | } |
| 214 | |
| 215 | if (window->bottom_up) |
| 216 | v_offset += window->src.h - 1; |
| 217 | |
| 218 | tegra_dc_writel(dc, h_offset, DC_WINBUF_ADDR_H_OFFSET); |
| 219 | tegra_dc_writel(dc, v_offset, DC_WINBUF_ADDR_V_OFFSET); |
| 220 | |
Thierry Reding | c134f01 | 2014-06-03 14:48:12 +0200 | [diff] [blame] | 221 | if (dc->soc->supports_block_linear) { |
| 222 | unsigned long height = window->tiling.value; |
Thierry Reding | 10288ee | 2014-03-14 09:54:58 +0100 | [diff] [blame] | 223 | |
Thierry Reding | c134f01 | 2014-06-03 14:48:12 +0200 | [diff] [blame] | 224 | switch (window->tiling.mode) { |
| 225 | case TEGRA_BO_TILING_MODE_PITCH: |
| 226 | value = DC_WINBUF_SURFACE_KIND_PITCH; |
| 227 | break; |
| 228 | |
| 229 | case TEGRA_BO_TILING_MODE_TILED: |
| 230 | value = DC_WINBUF_SURFACE_KIND_TILED; |
| 231 | break; |
| 232 | |
| 233 | case TEGRA_BO_TILING_MODE_BLOCK: |
| 234 | value = DC_WINBUF_SURFACE_KIND_BLOCK_HEIGHT(height) | |
| 235 | DC_WINBUF_SURFACE_KIND_BLOCK; |
| 236 | break; |
| 237 | } |
| 238 | |
| 239 | tegra_dc_writel(dc, value, DC_WINBUF_SURFACE_KIND); |
| 240 | } else { |
| 241 | switch (window->tiling.mode) { |
| 242 | case TEGRA_BO_TILING_MODE_PITCH: |
| 243 | value = DC_WIN_BUFFER_ADDR_MODE_LINEAR_UV | |
| 244 | DC_WIN_BUFFER_ADDR_MODE_LINEAR; |
| 245 | break; |
| 246 | |
| 247 | case TEGRA_BO_TILING_MODE_TILED: |
| 248 | value = DC_WIN_BUFFER_ADDR_MODE_TILE_UV | |
| 249 | DC_WIN_BUFFER_ADDR_MODE_TILE; |
| 250 | break; |
| 251 | |
| 252 | case TEGRA_BO_TILING_MODE_BLOCK: |
| 253 | DRM_ERROR("hardware doesn't support block linear mode\n"); |
| 254 | return -EINVAL; |
| 255 | } |
| 256 | |
| 257 | tegra_dc_writel(dc, value, DC_WIN_BUFFER_ADDR_MODE); |
| 258 | } |
Thierry Reding | 10288ee | 2014-03-14 09:54:58 +0100 | [diff] [blame] | 259 | |
| 260 | value = WIN_ENABLE; |
| 261 | |
| 262 | if (yuv) { |
| 263 | /* setup default colorspace conversion coefficients */ |
| 264 | tegra_dc_writel(dc, 0x00f0, DC_WIN_CSC_YOF); |
| 265 | tegra_dc_writel(dc, 0x012a, DC_WIN_CSC_KYRGB); |
| 266 | tegra_dc_writel(dc, 0x0000, DC_WIN_CSC_KUR); |
| 267 | tegra_dc_writel(dc, 0x0198, DC_WIN_CSC_KVR); |
| 268 | tegra_dc_writel(dc, 0x039b, DC_WIN_CSC_KUG); |
| 269 | tegra_dc_writel(dc, 0x032f, DC_WIN_CSC_KVG); |
| 270 | tegra_dc_writel(dc, 0x0204, DC_WIN_CSC_KUB); |
| 271 | tegra_dc_writel(dc, 0x0000, DC_WIN_CSC_KVB); |
| 272 | |
| 273 | value |= CSC_ENABLE; |
| 274 | } else if (window->bits_per_pixel < 24) { |
| 275 | value |= COLOR_EXPAND; |
| 276 | } |
| 277 | |
| 278 | if (window->bottom_up) |
| 279 | value |= V_DIRECTION; |
| 280 | |
| 281 | tegra_dc_writel(dc, value, DC_WIN_WIN_OPTIONS); |
| 282 | |
| 283 | /* |
| 284 | * Disable blending and assume Window A is the bottom-most window, |
| 285 | * Window C is the top-most window and Window B is in the middle. |
| 286 | */ |
| 287 | tegra_dc_writel(dc, 0xffff00, DC_WIN_BLEND_NOKEY); |
| 288 | tegra_dc_writel(dc, 0xffff00, DC_WIN_BLEND_1WIN); |
| 289 | |
| 290 | switch (index) { |
| 291 | case 0: |
| 292 | tegra_dc_writel(dc, 0x000000, DC_WIN_BLEND_2WIN_X); |
| 293 | tegra_dc_writel(dc, 0x000000, DC_WIN_BLEND_2WIN_Y); |
| 294 | tegra_dc_writel(dc, 0x000000, DC_WIN_BLEND_3WIN_XY); |
| 295 | break; |
| 296 | |
| 297 | case 1: |
| 298 | tegra_dc_writel(dc, 0xffff00, DC_WIN_BLEND_2WIN_X); |
| 299 | tegra_dc_writel(dc, 0x000000, DC_WIN_BLEND_2WIN_Y); |
| 300 | tegra_dc_writel(dc, 0x000000, DC_WIN_BLEND_3WIN_XY); |
| 301 | break; |
| 302 | |
| 303 | case 2: |
| 304 | tegra_dc_writel(dc, 0xffff00, DC_WIN_BLEND_2WIN_X); |
| 305 | tegra_dc_writel(dc, 0xffff00, DC_WIN_BLEND_2WIN_Y); |
| 306 | tegra_dc_writel(dc, 0xffff00, DC_WIN_BLEND_3WIN_XY); |
| 307 | break; |
| 308 | } |
| 309 | |
| 310 | tegra_dc_writel(dc, WIN_A_UPDATE << index, DC_CMD_STATE_CONTROL); |
| 311 | tegra_dc_writel(dc, WIN_A_ACT_REQ << index, DC_CMD_STATE_CONTROL); |
| 312 | |
| 313 | return 0; |
| 314 | } |
| 315 | |
Thierry Reding | f34bc78 | 2012-11-04 21:47:13 +0100 | [diff] [blame] | 316 | static int tegra_plane_update(struct drm_plane *plane, struct drm_crtc *crtc, |
| 317 | struct drm_framebuffer *fb, int crtc_x, |
| 318 | int crtc_y, unsigned int crtc_w, |
| 319 | unsigned int crtc_h, uint32_t src_x, |
| 320 | uint32_t src_y, uint32_t src_w, uint32_t src_h) |
| 321 | { |
| 322 | struct tegra_plane *p = to_tegra_plane(plane); |
| 323 | struct tegra_dc *dc = to_tegra_dc(crtc); |
| 324 | struct tegra_dc_window window; |
| 325 | unsigned int i; |
Thierry Reding | c134f01 | 2014-06-03 14:48:12 +0200 | [diff] [blame] | 326 | int err; |
Thierry Reding | f34bc78 | 2012-11-04 21:47:13 +0100 | [diff] [blame] | 327 | |
| 328 | memset(&window, 0, sizeof(window)); |
| 329 | window.src.x = src_x >> 16; |
| 330 | window.src.y = src_y >> 16; |
| 331 | window.src.w = src_w >> 16; |
| 332 | window.src.h = src_h >> 16; |
| 333 | window.dst.x = crtc_x; |
| 334 | window.dst.y = crtc_y; |
| 335 | window.dst.w = crtc_w; |
| 336 | window.dst.h = crtc_h; |
Thierry Reding | f925390 | 2014-01-29 20:31:17 +0100 | [diff] [blame] | 337 | window.format = tegra_dc_format(fb->pixel_format, &window.swap); |
Thierry Reding | f34bc78 | 2012-11-04 21:47:13 +0100 | [diff] [blame] | 338 | window.bits_per_pixel = fb->bits_per_pixel; |
Thierry Reding | db7fbdf | 2013-10-07 09:47:58 +0200 | [diff] [blame] | 339 | window.bottom_up = tegra_fb_is_bottom_up(fb); |
Thierry Reding | c134f01 | 2014-06-03 14:48:12 +0200 | [diff] [blame] | 340 | |
| 341 | err = tegra_fb_get_tiling(fb, &window.tiling); |
| 342 | if (err < 0) |
| 343 | return err; |
Thierry Reding | f34bc78 | 2012-11-04 21:47:13 +0100 | [diff] [blame] | 344 | |
| 345 | for (i = 0; i < drm_format_num_planes(fb->pixel_format); i++) { |
Arto Merilainen | de2ba66 | 2013-03-22 16:34:08 +0200 | [diff] [blame] | 346 | struct tegra_bo *bo = tegra_fb_get_plane(fb, i); |
Thierry Reding | f34bc78 | 2012-11-04 21:47:13 +0100 | [diff] [blame] | 347 | |
Arto Merilainen | de2ba66 | 2013-03-22 16:34:08 +0200 | [diff] [blame] | 348 | window.base[i] = bo->paddr + fb->offsets[i]; |
Thierry Reding | f34bc78 | 2012-11-04 21:47:13 +0100 | [diff] [blame] | 349 | |
| 350 | /* |
| 351 | * Tegra doesn't support different strides for U and V planes |
| 352 | * so we display a warning if the user tries to display a |
| 353 | * framebuffer with such a configuration. |
| 354 | */ |
| 355 | if (i >= 2) { |
| 356 | if (fb->pitches[i] != window.stride[1]) |
| 357 | DRM_ERROR("unsupported UV-plane configuration\n"); |
| 358 | } else { |
| 359 | window.stride[i] = fb->pitches[i]; |
| 360 | } |
| 361 | } |
| 362 | |
| 363 | return tegra_dc_setup_window(dc, p->index, &window); |
| 364 | } |
| 365 | |
| 366 | static int tegra_plane_disable(struct drm_plane *plane) |
| 367 | { |
| 368 | struct tegra_dc *dc = to_tegra_dc(plane->crtc); |
| 369 | struct tegra_plane *p = to_tegra_plane(plane); |
| 370 | unsigned long value; |
| 371 | |
Thierry Reding | 2678aeb | 2013-03-18 11:09:13 +0100 | [diff] [blame] | 372 | if (!plane->crtc) |
| 373 | return 0; |
| 374 | |
Thierry Reding | f34bc78 | 2012-11-04 21:47:13 +0100 | [diff] [blame] | 375 | value = WINDOW_A_SELECT << p->index; |
| 376 | tegra_dc_writel(dc, value, DC_CMD_DISPLAY_WINDOW_HEADER); |
| 377 | |
| 378 | value = tegra_dc_readl(dc, DC_WIN_WIN_OPTIONS); |
| 379 | value &= ~WIN_ENABLE; |
| 380 | tegra_dc_writel(dc, value, DC_WIN_WIN_OPTIONS); |
| 381 | |
| 382 | tegra_dc_writel(dc, WIN_A_UPDATE << p->index, DC_CMD_STATE_CONTROL); |
| 383 | tegra_dc_writel(dc, WIN_A_ACT_REQ << p->index, DC_CMD_STATE_CONTROL); |
| 384 | |
| 385 | return 0; |
| 386 | } |
| 387 | |
| 388 | static void tegra_plane_destroy(struct drm_plane *plane) |
| 389 | { |
Thierry Reding | f002abc | 2013-10-14 14:06:02 +0200 | [diff] [blame] | 390 | struct tegra_plane *p = to_tegra_plane(plane); |
| 391 | |
Thierry Reding | f34bc78 | 2012-11-04 21:47:13 +0100 | [diff] [blame] | 392 | tegra_plane_disable(plane); |
| 393 | drm_plane_cleanup(plane); |
Thierry Reding | f002abc | 2013-10-14 14:06:02 +0200 | [diff] [blame] | 394 | kfree(p); |
Thierry Reding | f34bc78 | 2012-11-04 21:47:13 +0100 | [diff] [blame] | 395 | } |
| 396 | |
| 397 | static const struct drm_plane_funcs tegra_plane_funcs = { |
| 398 | .update_plane = tegra_plane_update, |
| 399 | .disable_plane = tegra_plane_disable, |
| 400 | .destroy = tegra_plane_destroy, |
| 401 | }; |
| 402 | |
| 403 | static const uint32_t plane_formats[] = { |
Thierry Reding | dbe4d9a | 2013-03-22 15:37:30 +0100 | [diff] [blame] | 404 | DRM_FORMAT_XBGR8888, |
Thierry Reding | f34bc78 | 2012-11-04 21:47:13 +0100 | [diff] [blame] | 405 | DRM_FORMAT_XRGB8888, |
Thierry Reding | dbe4d9a | 2013-03-22 15:37:30 +0100 | [diff] [blame] | 406 | DRM_FORMAT_RGB565, |
Thierry Reding | f34bc78 | 2012-11-04 21:47:13 +0100 | [diff] [blame] | 407 | DRM_FORMAT_UYVY, |
Thierry Reding | f925390 | 2014-01-29 20:31:17 +0100 | [diff] [blame] | 408 | DRM_FORMAT_YUYV, |
Thierry Reding | f34bc78 | 2012-11-04 21:47:13 +0100 | [diff] [blame] | 409 | DRM_FORMAT_YUV420, |
| 410 | DRM_FORMAT_YUV422, |
| 411 | }; |
| 412 | |
| 413 | static int tegra_dc_add_planes(struct drm_device *drm, struct tegra_dc *dc) |
| 414 | { |
| 415 | unsigned int i; |
| 416 | int err = 0; |
| 417 | |
| 418 | for (i = 0; i < 2; i++) { |
| 419 | struct tegra_plane *plane; |
| 420 | |
Thierry Reding | f002abc | 2013-10-14 14:06:02 +0200 | [diff] [blame] | 421 | plane = kzalloc(sizeof(*plane), GFP_KERNEL); |
Thierry Reding | f34bc78 | 2012-11-04 21:47:13 +0100 | [diff] [blame] | 422 | if (!plane) |
| 423 | return -ENOMEM; |
| 424 | |
| 425 | plane->index = 1 + i; |
| 426 | |
| 427 | err = drm_plane_init(drm, &plane->base, 1 << dc->pipe, |
| 428 | &tegra_plane_funcs, plane_formats, |
| 429 | ARRAY_SIZE(plane_formats), false); |
Thierry Reding | f002abc | 2013-10-14 14:06:02 +0200 | [diff] [blame] | 430 | if (err < 0) { |
| 431 | kfree(plane); |
Thierry Reding | f34bc78 | 2012-11-04 21:47:13 +0100 | [diff] [blame] | 432 | return err; |
Thierry Reding | f002abc | 2013-10-14 14:06:02 +0200 | [diff] [blame] | 433 | } |
Thierry Reding | f34bc78 | 2012-11-04 21:47:13 +0100 | [diff] [blame] | 434 | } |
| 435 | |
| 436 | return 0; |
| 437 | } |
| 438 | |
Thierry Reding | 23fb474 | 2012-11-28 11:38:24 +0100 | [diff] [blame] | 439 | static int tegra_dc_set_base(struct tegra_dc *dc, int x, int y, |
| 440 | struct drm_framebuffer *fb) |
| 441 | { |
Arto Merilainen | de2ba66 | 2013-03-22 16:34:08 +0200 | [diff] [blame] | 442 | struct tegra_bo *bo = tegra_fb_get_plane(fb, 0); |
Thierry Reding | db7fbdf | 2013-10-07 09:47:58 +0200 | [diff] [blame] | 443 | unsigned int h_offset = 0, v_offset = 0; |
Thierry Reding | c134f01 | 2014-06-03 14:48:12 +0200 | [diff] [blame] | 444 | struct tegra_bo_tiling tiling; |
Thierry Reding | f925390 | 2014-01-29 20:31:17 +0100 | [diff] [blame] | 445 | unsigned int format, swap; |
Thierry Reding | 23fb474 | 2012-11-28 11:38:24 +0100 | [diff] [blame] | 446 | unsigned long value; |
Thierry Reding | c134f01 | 2014-06-03 14:48:12 +0200 | [diff] [blame] | 447 | int err; |
| 448 | |
| 449 | err = tegra_fb_get_tiling(fb, &tiling); |
| 450 | if (err < 0) |
| 451 | return err; |
Thierry Reding | 23fb474 | 2012-11-28 11:38:24 +0100 | [diff] [blame] | 452 | |
| 453 | tegra_dc_writel(dc, WINDOW_A_SELECT, DC_CMD_DISPLAY_WINDOW_HEADER); |
| 454 | |
| 455 | value = fb->offsets[0] + y * fb->pitches[0] + |
| 456 | x * fb->bits_per_pixel / 8; |
| 457 | |
Arto Merilainen | de2ba66 | 2013-03-22 16:34:08 +0200 | [diff] [blame] | 458 | tegra_dc_writel(dc, bo->paddr + value, DC_WINBUF_START_ADDR); |
Thierry Reding | 23fb474 | 2012-11-28 11:38:24 +0100 | [diff] [blame] | 459 | tegra_dc_writel(dc, fb->pitches[0], DC_WIN_LINE_STRIDE); |
Thierry Reding | f925390 | 2014-01-29 20:31:17 +0100 | [diff] [blame] | 460 | |
| 461 | format = tegra_dc_format(fb->pixel_format, &swap); |
Thierry Reding | ed683ae | 2013-04-22 21:31:15 +0200 | [diff] [blame] | 462 | tegra_dc_writel(dc, format, DC_WIN_COLOR_DEPTH); |
Thierry Reding | f925390 | 2014-01-29 20:31:17 +0100 | [diff] [blame] | 463 | tegra_dc_writel(dc, swap, DC_WIN_BYTE_SWAP); |
Thierry Reding | 23fb474 | 2012-11-28 11:38:24 +0100 | [diff] [blame] | 464 | |
Thierry Reding | c134f01 | 2014-06-03 14:48:12 +0200 | [diff] [blame] | 465 | if (dc->soc->supports_block_linear) { |
| 466 | unsigned long height = tiling.value; |
Thierry Reding | 773af77 | 2013-10-04 22:34:01 +0200 | [diff] [blame] | 467 | |
Thierry Reding | c134f01 | 2014-06-03 14:48:12 +0200 | [diff] [blame] | 468 | switch (tiling.mode) { |
| 469 | case TEGRA_BO_TILING_MODE_PITCH: |
| 470 | value = DC_WINBUF_SURFACE_KIND_PITCH; |
| 471 | break; |
| 472 | |
| 473 | case TEGRA_BO_TILING_MODE_TILED: |
| 474 | value = DC_WINBUF_SURFACE_KIND_TILED; |
| 475 | break; |
| 476 | |
| 477 | case TEGRA_BO_TILING_MODE_BLOCK: |
| 478 | value = DC_WINBUF_SURFACE_KIND_BLOCK_HEIGHT(height) | |
| 479 | DC_WINBUF_SURFACE_KIND_BLOCK; |
| 480 | break; |
| 481 | } |
| 482 | |
| 483 | tegra_dc_writel(dc, value, DC_WINBUF_SURFACE_KIND); |
| 484 | } else { |
| 485 | switch (tiling.mode) { |
| 486 | case TEGRA_BO_TILING_MODE_PITCH: |
| 487 | value = DC_WIN_BUFFER_ADDR_MODE_LINEAR_UV | |
| 488 | DC_WIN_BUFFER_ADDR_MODE_LINEAR; |
| 489 | break; |
| 490 | |
| 491 | case TEGRA_BO_TILING_MODE_TILED: |
| 492 | value = DC_WIN_BUFFER_ADDR_MODE_TILE_UV | |
| 493 | DC_WIN_BUFFER_ADDR_MODE_TILE; |
| 494 | break; |
| 495 | |
| 496 | case TEGRA_BO_TILING_MODE_BLOCK: |
| 497 | DRM_ERROR("hardware doesn't support block linear mode\n"); |
| 498 | return -EINVAL; |
| 499 | } |
| 500 | |
| 501 | tegra_dc_writel(dc, value, DC_WIN_BUFFER_ADDR_MODE); |
| 502 | } |
Thierry Reding | 773af77 | 2013-10-04 22:34:01 +0200 | [diff] [blame] | 503 | |
Thierry Reding | db7fbdf | 2013-10-07 09:47:58 +0200 | [diff] [blame] | 504 | /* make sure bottom-up buffers are properly displayed */ |
| 505 | if (tegra_fb_is_bottom_up(fb)) { |
| 506 | value = tegra_dc_readl(dc, DC_WIN_WIN_OPTIONS); |
Thierry Reding | eba6650 | 2014-02-25 12:04:06 +0100 | [diff] [blame] | 507 | value |= V_DIRECTION; |
Thierry Reding | db7fbdf | 2013-10-07 09:47:58 +0200 | [diff] [blame] | 508 | tegra_dc_writel(dc, value, DC_WIN_WIN_OPTIONS); |
| 509 | |
| 510 | v_offset += fb->height - 1; |
| 511 | } else { |
| 512 | value = tegra_dc_readl(dc, DC_WIN_WIN_OPTIONS); |
Thierry Reding | eba6650 | 2014-02-25 12:04:06 +0100 | [diff] [blame] | 513 | value &= ~V_DIRECTION; |
Thierry Reding | db7fbdf | 2013-10-07 09:47:58 +0200 | [diff] [blame] | 514 | tegra_dc_writel(dc, value, DC_WIN_WIN_OPTIONS); |
| 515 | } |
| 516 | |
| 517 | tegra_dc_writel(dc, h_offset, DC_WINBUF_ADDR_H_OFFSET); |
| 518 | tegra_dc_writel(dc, v_offset, DC_WINBUF_ADDR_V_OFFSET); |
| 519 | |
Thierry Reding | 23fb474 | 2012-11-28 11:38:24 +0100 | [diff] [blame] | 520 | value = GENERAL_UPDATE | WIN_A_UPDATE; |
| 521 | tegra_dc_writel(dc, value, DC_CMD_STATE_CONTROL); |
| 522 | |
| 523 | value = GENERAL_ACT_REQ | WIN_A_ACT_REQ; |
| 524 | tegra_dc_writel(dc, value, DC_CMD_STATE_CONTROL); |
| 525 | |
| 526 | return 0; |
| 527 | } |
| 528 | |
Thierry Reding | 6e5ff99 | 2012-11-28 11:45:47 +0100 | [diff] [blame] | 529 | void tegra_dc_enable_vblank(struct tegra_dc *dc) |
| 530 | { |
| 531 | unsigned long value, flags; |
| 532 | |
| 533 | spin_lock_irqsave(&dc->lock, flags); |
| 534 | |
| 535 | value = tegra_dc_readl(dc, DC_CMD_INT_MASK); |
| 536 | value |= VBLANK_INT; |
| 537 | tegra_dc_writel(dc, value, DC_CMD_INT_MASK); |
| 538 | |
| 539 | spin_unlock_irqrestore(&dc->lock, flags); |
| 540 | } |
| 541 | |
| 542 | void tegra_dc_disable_vblank(struct tegra_dc *dc) |
| 543 | { |
| 544 | unsigned long value, flags; |
| 545 | |
| 546 | spin_lock_irqsave(&dc->lock, flags); |
| 547 | |
| 548 | value = tegra_dc_readl(dc, DC_CMD_INT_MASK); |
| 549 | value &= ~VBLANK_INT; |
| 550 | tegra_dc_writel(dc, value, DC_CMD_INT_MASK); |
| 551 | |
| 552 | spin_unlock_irqrestore(&dc->lock, flags); |
| 553 | } |
| 554 | |
Thierry Reding | e687651 | 2013-12-20 13:58:33 +0100 | [diff] [blame] | 555 | static int tegra_dc_cursor_set2(struct drm_crtc *crtc, struct drm_file *file, |
| 556 | uint32_t handle, uint32_t width, |
| 557 | uint32_t height, int32_t hot_x, int32_t hot_y) |
| 558 | { |
| 559 | unsigned long value = CURSOR_CLIP_DISPLAY; |
| 560 | struct tegra_dc *dc = to_tegra_dc(crtc); |
| 561 | struct drm_gem_object *gem; |
| 562 | struct tegra_bo *bo = NULL; |
| 563 | |
| 564 | if (!dc->soc->supports_cursor) |
| 565 | return -ENXIO; |
| 566 | |
| 567 | if (width != height) |
| 568 | return -EINVAL; |
| 569 | |
| 570 | switch (width) { |
| 571 | case 32: |
| 572 | value |= CURSOR_SIZE_32x32; |
| 573 | break; |
| 574 | |
| 575 | case 64: |
| 576 | value |= CURSOR_SIZE_64x64; |
| 577 | break; |
| 578 | |
| 579 | case 128: |
| 580 | value |= CURSOR_SIZE_128x128; |
| 581 | |
| 582 | case 256: |
| 583 | value |= CURSOR_SIZE_256x256; |
| 584 | break; |
| 585 | |
| 586 | default: |
| 587 | return -EINVAL; |
| 588 | } |
| 589 | |
| 590 | if (handle) { |
| 591 | gem = drm_gem_object_lookup(crtc->dev, file, handle); |
| 592 | if (!gem) |
| 593 | return -ENOENT; |
| 594 | |
| 595 | bo = to_tegra_bo(gem); |
| 596 | } |
| 597 | |
| 598 | if (bo) { |
| 599 | unsigned long addr = (bo->paddr & 0xfffffc00) >> 10; |
| 600 | #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT |
| 601 | unsigned long high = (bo->paddr & 0xfffffffc) >> 32; |
| 602 | #endif |
| 603 | |
| 604 | tegra_dc_writel(dc, value | addr, DC_DISP_CURSOR_START_ADDR); |
| 605 | |
| 606 | #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT |
| 607 | tegra_dc_writel(dc, high, DC_DISP_CURSOR_START_ADDR_HI); |
| 608 | #endif |
| 609 | |
| 610 | value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS); |
| 611 | value |= CURSOR_ENABLE; |
| 612 | tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS); |
| 613 | |
| 614 | value = tegra_dc_readl(dc, DC_DISP_BLEND_CURSOR_CONTROL); |
| 615 | value &= ~CURSOR_DST_BLEND_MASK; |
| 616 | value &= ~CURSOR_SRC_BLEND_MASK; |
| 617 | value |= CURSOR_MODE_NORMAL; |
| 618 | value |= CURSOR_DST_BLEND_NEG_K1_TIMES_SRC; |
| 619 | value |= CURSOR_SRC_BLEND_K1_TIMES_SRC; |
| 620 | value |= CURSOR_ALPHA; |
| 621 | tegra_dc_writel(dc, value, DC_DISP_BLEND_CURSOR_CONTROL); |
| 622 | } else { |
| 623 | value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS); |
| 624 | value &= ~CURSOR_ENABLE; |
| 625 | tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS); |
| 626 | } |
| 627 | |
| 628 | tegra_dc_writel(dc, CURSOR_ACT_REQ << 8, DC_CMD_STATE_CONTROL); |
| 629 | tegra_dc_writel(dc, CURSOR_ACT_REQ, DC_CMD_STATE_CONTROL); |
| 630 | |
| 631 | tegra_dc_writel(dc, GENERAL_ACT_REQ << 8, DC_CMD_STATE_CONTROL); |
| 632 | tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL); |
| 633 | |
| 634 | return 0; |
| 635 | } |
| 636 | |
| 637 | static int tegra_dc_cursor_move(struct drm_crtc *crtc, int x, int y) |
| 638 | { |
| 639 | struct tegra_dc *dc = to_tegra_dc(crtc); |
| 640 | unsigned long value; |
| 641 | |
| 642 | if (!dc->soc->supports_cursor) |
| 643 | return -ENXIO; |
| 644 | |
| 645 | value = ((y & 0x3fff) << 16) | (x & 0x3fff); |
| 646 | tegra_dc_writel(dc, value, DC_DISP_CURSOR_POSITION); |
| 647 | |
| 648 | tegra_dc_writel(dc, CURSOR_ACT_REQ << 8, DC_CMD_STATE_CONTROL); |
| 649 | tegra_dc_writel(dc, CURSOR_ACT_REQ, DC_CMD_STATE_CONTROL); |
| 650 | |
| 651 | /* XXX: only required on generations earlier than Tegra124? */ |
| 652 | tegra_dc_writel(dc, GENERAL_ACT_REQ << 8, DC_CMD_STATE_CONTROL); |
| 653 | tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL); |
| 654 | |
| 655 | return 0; |
| 656 | } |
| 657 | |
Thierry Reding | 3c03c46 | 2012-11-28 12:00:18 +0100 | [diff] [blame] | 658 | static void tegra_dc_finish_page_flip(struct tegra_dc *dc) |
| 659 | { |
| 660 | struct drm_device *drm = dc->base.dev; |
| 661 | struct drm_crtc *crtc = &dc->base; |
Thierry Reding | 3c03c46 | 2012-11-28 12:00:18 +0100 | [diff] [blame] | 662 | unsigned long flags, base; |
Arto Merilainen | de2ba66 | 2013-03-22 16:34:08 +0200 | [diff] [blame] | 663 | struct tegra_bo *bo; |
Thierry Reding | 3c03c46 | 2012-11-28 12:00:18 +0100 | [diff] [blame] | 664 | |
| 665 | if (!dc->event) |
| 666 | return; |
| 667 | |
Matt Roper | f4510a2 | 2014-04-01 15:22:40 -0700 | [diff] [blame] | 668 | bo = tegra_fb_get_plane(crtc->primary->fb, 0); |
Thierry Reding | 3c03c46 | 2012-11-28 12:00:18 +0100 | [diff] [blame] | 669 | |
| 670 | /* check if new start address has been latched */ |
| 671 | tegra_dc_writel(dc, READ_MUX, DC_CMD_STATE_ACCESS); |
| 672 | base = tegra_dc_readl(dc, DC_WINBUF_START_ADDR); |
| 673 | tegra_dc_writel(dc, 0, DC_CMD_STATE_ACCESS); |
| 674 | |
Matt Roper | f4510a2 | 2014-04-01 15:22:40 -0700 | [diff] [blame] | 675 | if (base == bo->paddr + crtc->primary->fb->offsets[0]) { |
Thierry Reding | 3c03c46 | 2012-11-28 12:00:18 +0100 | [diff] [blame] | 676 | spin_lock_irqsave(&drm->event_lock, flags); |
| 677 | drm_send_vblank_event(drm, dc->pipe, dc->event); |
| 678 | drm_vblank_put(drm, dc->pipe); |
| 679 | dc->event = NULL; |
| 680 | spin_unlock_irqrestore(&drm->event_lock, flags); |
| 681 | } |
| 682 | } |
| 683 | |
| 684 | void tegra_dc_cancel_page_flip(struct drm_crtc *crtc, struct drm_file *file) |
| 685 | { |
| 686 | struct tegra_dc *dc = to_tegra_dc(crtc); |
| 687 | struct drm_device *drm = crtc->dev; |
| 688 | unsigned long flags; |
| 689 | |
| 690 | spin_lock_irqsave(&drm->event_lock, flags); |
| 691 | |
| 692 | if (dc->event && dc->event->base.file_priv == file) { |
| 693 | dc->event->base.destroy(&dc->event->base); |
| 694 | drm_vblank_put(drm, dc->pipe); |
| 695 | dc->event = NULL; |
| 696 | } |
| 697 | |
| 698 | spin_unlock_irqrestore(&drm->event_lock, flags); |
| 699 | } |
| 700 | |
| 701 | static int tegra_dc_page_flip(struct drm_crtc *crtc, struct drm_framebuffer *fb, |
Dave Airlie | a5b6f74 | 2013-09-02 09:47:56 +1000 | [diff] [blame] | 702 | struct drm_pending_vblank_event *event, uint32_t page_flip_flags) |
Thierry Reding | 3c03c46 | 2012-11-28 12:00:18 +0100 | [diff] [blame] | 703 | { |
| 704 | struct tegra_dc *dc = to_tegra_dc(crtc); |
| 705 | struct drm_device *drm = crtc->dev; |
| 706 | |
| 707 | if (dc->event) |
| 708 | return -EBUSY; |
| 709 | |
| 710 | if (event) { |
| 711 | event->pipe = dc->pipe; |
| 712 | dc->event = event; |
| 713 | drm_vblank_get(drm, dc->pipe); |
| 714 | } |
| 715 | |
| 716 | tegra_dc_set_base(dc, 0, 0, fb); |
Matt Roper | f4510a2 | 2014-04-01 15:22:40 -0700 | [diff] [blame] | 717 | crtc->primary->fb = fb; |
Thierry Reding | 3c03c46 | 2012-11-28 12:00:18 +0100 | [diff] [blame] | 718 | |
| 719 | return 0; |
| 720 | } |
| 721 | |
Thierry Reding | f002abc | 2013-10-14 14:06:02 +0200 | [diff] [blame] | 722 | static void drm_crtc_clear(struct drm_crtc *crtc) |
| 723 | { |
| 724 | memset(crtc, 0, sizeof(*crtc)); |
| 725 | } |
| 726 | |
| 727 | static void tegra_dc_destroy(struct drm_crtc *crtc) |
| 728 | { |
| 729 | drm_crtc_cleanup(crtc); |
| 730 | drm_crtc_clear(crtc); |
| 731 | } |
| 732 | |
Thierry Reding | d8f4a9e | 2012-11-15 21:28:22 +0000 | [diff] [blame] | 733 | static const struct drm_crtc_funcs tegra_crtc_funcs = { |
Thierry Reding | e687651 | 2013-12-20 13:58:33 +0100 | [diff] [blame] | 734 | .cursor_set2 = tegra_dc_cursor_set2, |
| 735 | .cursor_move = tegra_dc_cursor_move, |
Thierry Reding | 3c03c46 | 2012-11-28 12:00:18 +0100 | [diff] [blame] | 736 | .page_flip = tegra_dc_page_flip, |
Thierry Reding | d8f4a9e | 2012-11-15 21:28:22 +0000 | [diff] [blame] | 737 | .set_config = drm_crtc_helper_set_config, |
Thierry Reding | f002abc | 2013-10-14 14:06:02 +0200 | [diff] [blame] | 738 | .destroy = tegra_dc_destroy, |
Thierry Reding | d8f4a9e | 2012-11-15 21:28:22 +0000 | [diff] [blame] | 739 | }; |
| 740 | |
Thierry Reding | f34bc78 | 2012-11-04 21:47:13 +0100 | [diff] [blame] | 741 | static void tegra_crtc_disable(struct drm_crtc *crtc) |
Thierry Reding | d8f4a9e | 2012-11-15 21:28:22 +0000 | [diff] [blame] | 742 | { |
Thierry Reding | f002abc | 2013-10-14 14:06:02 +0200 | [diff] [blame] | 743 | struct tegra_dc *dc = to_tegra_dc(crtc); |
Thierry Reding | f34bc78 | 2012-11-04 21:47:13 +0100 | [diff] [blame] | 744 | struct drm_device *drm = crtc->dev; |
| 745 | struct drm_plane *plane; |
| 746 | |
Daniel Vetter | 2b4c366 | 2014-04-23 15:15:32 +0200 | [diff] [blame] | 747 | drm_for_each_legacy_plane(plane, &drm->mode_config.plane_list) { |
Thierry Reding | f34bc78 | 2012-11-04 21:47:13 +0100 | [diff] [blame] | 748 | if (plane->crtc == crtc) { |
| 749 | tegra_plane_disable(plane); |
| 750 | plane->crtc = NULL; |
| 751 | |
| 752 | if (plane->fb) { |
| 753 | drm_framebuffer_unreference(plane->fb); |
| 754 | plane->fb = NULL; |
| 755 | } |
| 756 | } |
| 757 | } |
Thierry Reding | f002abc | 2013-10-14 14:06:02 +0200 | [diff] [blame] | 758 | |
| 759 | drm_vblank_off(drm, dc->pipe); |
Thierry Reding | d8f4a9e | 2012-11-15 21:28:22 +0000 | [diff] [blame] | 760 | } |
| 761 | |
| 762 | static bool tegra_crtc_mode_fixup(struct drm_crtc *crtc, |
| 763 | const struct drm_display_mode *mode, |
| 764 | struct drm_display_mode *adjusted) |
| 765 | { |
| 766 | return true; |
| 767 | } |
| 768 | |
Thierry Reding | d8f4a9e | 2012-11-15 21:28:22 +0000 | [diff] [blame] | 769 | static int tegra_dc_set_timings(struct tegra_dc *dc, |
| 770 | struct drm_display_mode *mode) |
| 771 | { |
Thierry Reding | 0444c0f | 2014-04-16 09:22:38 +0200 | [diff] [blame] | 772 | unsigned int h_ref_to_sync = 1; |
| 773 | unsigned int v_ref_to_sync = 1; |
Thierry Reding | d8f4a9e | 2012-11-15 21:28:22 +0000 | [diff] [blame] | 774 | unsigned long value; |
| 775 | |
| 776 | tegra_dc_writel(dc, 0x0, DC_DISP_DISP_TIMING_OPTIONS); |
| 777 | |
| 778 | value = (v_ref_to_sync << 16) | h_ref_to_sync; |
| 779 | tegra_dc_writel(dc, value, DC_DISP_REF_TO_SYNC); |
| 780 | |
| 781 | value = ((mode->vsync_end - mode->vsync_start) << 16) | |
| 782 | ((mode->hsync_end - mode->hsync_start) << 0); |
| 783 | tegra_dc_writel(dc, value, DC_DISP_SYNC_WIDTH); |
| 784 | |
Thierry Reding | d8f4a9e | 2012-11-15 21:28:22 +0000 | [diff] [blame] | 785 | value = ((mode->vtotal - mode->vsync_end) << 16) | |
| 786 | ((mode->htotal - mode->hsync_end) << 0); |
Lucas Stach | 4049508 | 2012-12-19 21:38:52 +0000 | [diff] [blame] | 787 | tegra_dc_writel(dc, value, DC_DISP_BACK_PORCH); |
| 788 | |
| 789 | value = ((mode->vsync_start - mode->vdisplay) << 16) | |
| 790 | ((mode->hsync_start - mode->hdisplay) << 0); |
Thierry Reding | d8f4a9e | 2012-11-15 21:28:22 +0000 | [diff] [blame] | 791 | tegra_dc_writel(dc, value, DC_DISP_FRONT_PORCH); |
| 792 | |
| 793 | value = (mode->vdisplay << 16) | mode->hdisplay; |
| 794 | tegra_dc_writel(dc, value, DC_DISP_ACTIVE); |
| 795 | |
| 796 | return 0; |
| 797 | } |
| 798 | |
| 799 | static int tegra_crtc_setup_clk(struct drm_crtc *crtc, |
Thierry Reding | dbb3f2f | 2014-03-26 12:32:14 +0100 | [diff] [blame] | 800 | struct drm_display_mode *mode) |
Thierry Reding | d8f4a9e | 2012-11-15 21:28:22 +0000 | [diff] [blame] | 801 | { |
Thierry Reding | 91eded9 | 2014-03-26 13:32:21 +0100 | [diff] [blame] | 802 | unsigned long pclk = mode->clock * 1000; |
Thierry Reding | d8f4a9e | 2012-11-15 21:28:22 +0000 | [diff] [blame] | 803 | struct tegra_dc *dc = to_tegra_dc(crtc); |
| 804 | struct tegra_output *output = NULL; |
| 805 | struct drm_encoder *encoder; |
Thierry Reding | dbb3f2f | 2014-03-26 12:32:14 +0100 | [diff] [blame] | 806 | unsigned int div; |
| 807 | u32 value; |
Thierry Reding | d8f4a9e | 2012-11-15 21:28:22 +0000 | [diff] [blame] | 808 | long err; |
| 809 | |
| 810 | list_for_each_entry(encoder, &crtc->dev->mode_config.encoder_list, head) |
| 811 | if (encoder->crtc == crtc) { |
| 812 | output = encoder_to_output(encoder); |
| 813 | break; |
| 814 | } |
| 815 | |
| 816 | if (!output) |
| 817 | return -ENODEV; |
| 818 | |
| 819 | /* |
Thierry Reding | 91eded9 | 2014-03-26 13:32:21 +0100 | [diff] [blame] | 820 | * This assumes that the parent clock is pll_d_out0 or pll_d2_out |
| 821 | * respectively, each of which divides the base pll_d by 2. |
Thierry Reding | d8f4a9e | 2012-11-15 21:28:22 +0000 | [diff] [blame] | 822 | */ |
Thierry Reding | 91eded9 | 2014-03-26 13:32:21 +0100 | [diff] [blame] | 823 | err = tegra_output_setup_clock(output, dc->clk, pclk, &div); |
Thierry Reding | d8f4a9e | 2012-11-15 21:28:22 +0000 | [diff] [blame] | 824 | if (err < 0) { |
| 825 | dev_err(dc->dev, "failed to setup clock: %ld\n", err); |
| 826 | return err; |
| 827 | } |
| 828 | |
Thierry Reding | 91eded9 | 2014-03-26 13:32:21 +0100 | [diff] [blame] | 829 | DRM_DEBUG_KMS("rate: %lu, div: %u\n", clk_get_rate(dc->clk), div); |
Thierry Reding | dbb3f2f | 2014-03-26 12:32:14 +0100 | [diff] [blame] | 830 | |
| 831 | value = SHIFT_CLK_DIVIDER(div) | PIXEL_CLK_DIVIDER_PCD1; |
| 832 | tegra_dc_writel(dc, value, DC_DISP_DISP_CLOCK_CONTROL); |
Thierry Reding | d8f4a9e | 2012-11-15 21:28:22 +0000 | [diff] [blame] | 833 | |
| 834 | return 0; |
| 835 | } |
| 836 | |
| 837 | static int tegra_crtc_mode_set(struct drm_crtc *crtc, |
| 838 | struct drm_display_mode *mode, |
| 839 | struct drm_display_mode *adjusted, |
| 840 | int x, int y, struct drm_framebuffer *old_fb) |
| 841 | { |
Matt Roper | f4510a2 | 2014-04-01 15:22:40 -0700 | [diff] [blame] | 842 | struct tegra_bo *bo = tegra_fb_get_plane(crtc->primary->fb, 0); |
Thierry Reding | d8f4a9e | 2012-11-15 21:28:22 +0000 | [diff] [blame] | 843 | struct tegra_dc *dc = to_tegra_dc(crtc); |
Thierry Reding | f34bc78 | 2012-11-04 21:47:13 +0100 | [diff] [blame] | 844 | struct tegra_dc_window window; |
Thierry Reding | dbb3f2f | 2014-03-26 12:32:14 +0100 | [diff] [blame] | 845 | u32 value; |
Thierry Reding | d8f4a9e | 2012-11-15 21:28:22 +0000 | [diff] [blame] | 846 | int err; |
| 847 | |
Thierry Reding | 6e5ff99 | 2012-11-28 11:45:47 +0100 | [diff] [blame] | 848 | drm_vblank_pre_modeset(crtc->dev, dc->pipe); |
| 849 | |
Thierry Reding | dbb3f2f | 2014-03-26 12:32:14 +0100 | [diff] [blame] | 850 | err = tegra_crtc_setup_clk(crtc, mode); |
Thierry Reding | d8f4a9e | 2012-11-15 21:28:22 +0000 | [diff] [blame] | 851 | if (err) { |
| 852 | dev_err(dc->dev, "failed to setup clock for CRTC: %d\n", err); |
| 853 | return err; |
| 854 | } |
| 855 | |
| 856 | /* program display mode */ |
| 857 | tegra_dc_set_timings(dc, mode); |
| 858 | |
Thierry Reding | 8620fc6 | 2013-12-12 11:03:59 +0100 | [diff] [blame] | 859 | /* interlacing isn't supported yet, so disable it */ |
| 860 | if (dc->soc->supports_interlacing) { |
| 861 | value = tegra_dc_readl(dc, DC_DISP_INTERLACE_CONTROL); |
| 862 | value &= ~INTERLACE_ENABLE; |
| 863 | tegra_dc_writel(dc, value, DC_DISP_INTERLACE_CONTROL); |
| 864 | } |
| 865 | |
Thierry Reding | d8f4a9e | 2012-11-15 21:28:22 +0000 | [diff] [blame] | 866 | /* setup window parameters */ |
Thierry Reding | f34bc78 | 2012-11-04 21:47:13 +0100 | [diff] [blame] | 867 | memset(&window, 0, sizeof(window)); |
| 868 | window.src.x = 0; |
| 869 | window.src.y = 0; |
| 870 | window.src.w = mode->hdisplay; |
| 871 | window.src.h = mode->vdisplay; |
| 872 | window.dst.x = 0; |
| 873 | window.dst.y = 0; |
| 874 | window.dst.w = mode->hdisplay; |
| 875 | window.dst.h = mode->vdisplay; |
Thierry Reding | f925390 | 2014-01-29 20:31:17 +0100 | [diff] [blame] | 876 | window.format = tegra_dc_format(crtc->primary->fb->pixel_format, |
| 877 | &window.swap); |
Matt Roper | f4510a2 | 2014-04-01 15:22:40 -0700 | [diff] [blame] | 878 | window.bits_per_pixel = crtc->primary->fb->bits_per_pixel; |
| 879 | window.stride[0] = crtc->primary->fb->pitches[0]; |
Arto Merilainen | de2ba66 | 2013-03-22 16:34:08 +0200 | [diff] [blame] | 880 | window.base[0] = bo->paddr; |
Thierry Reding | d8f4a9e | 2012-11-15 21:28:22 +0000 | [diff] [blame] | 881 | |
Thierry Reding | f34bc78 | 2012-11-04 21:47:13 +0100 | [diff] [blame] | 882 | err = tegra_dc_setup_window(dc, 0, &window); |
| 883 | if (err < 0) |
| 884 | dev_err(dc->dev, "failed to enable root plane\n"); |
Thierry Reding | d8f4a9e | 2012-11-15 21:28:22 +0000 | [diff] [blame] | 885 | |
| 886 | return 0; |
| 887 | } |
| 888 | |
Thierry Reding | 23fb474 | 2012-11-28 11:38:24 +0100 | [diff] [blame] | 889 | static int tegra_crtc_mode_set_base(struct drm_crtc *crtc, int x, int y, |
| 890 | struct drm_framebuffer *old_fb) |
| 891 | { |
| 892 | struct tegra_dc *dc = to_tegra_dc(crtc); |
| 893 | |
Matt Roper | f4510a2 | 2014-04-01 15:22:40 -0700 | [diff] [blame] | 894 | return tegra_dc_set_base(dc, x, y, crtc->primary->fb); |
Thierry Reding | 23fb474 | 2012-11-28 11:38:24 +0100 | [diff] [blame] | 895 | } |
| 896 | |
Thierry Reding | d8f4a9e | 2012-11-15 21:28:22 +0000 | [diff] [blame] | 897 | static void tegra_crtc_prepare(struct drm_crtc *crtc) |
| 898 | { |
| 899 | struct tegra_dc *dc = to_tegra_dc(crtc); |
| 900 | unsigned int syncpt; |
| 901 | unsigned long value; |
| 902 | |
| 903 | /* hardware initialization */ |
Stephen Warren | ca48080 | 2013-11-06 16:20:54 -0700 | [diff] [blame] | 904 | reset_control_deassert(dc->rst); |
Thierry Reding | d8f4a9e | 2012-11-15 21:28:22 +0000 | [diff] [blame] | 905 | usleep_range(10000, 20000); |
| 906 | |
| 907 | if (dc->pipe) |
| 908 | syncpt = SYNCPT_VBLANK1; |
| 909 | else |
| 910 | syncpt = SYNCPT_VBLANK0; |
| 911 | |
| 912 | /* initialize display controller */ |
| 913 | tegra_dc_writel(dc, 0x00000100, DC_CMD_GENERAL_INCR_SYNCPT_CNTRL); |
| 914 | tegra_dc_writel(dc, 0x100 | syncpt, DC_CMD_CONT_SYNCPT_VSYNC); |
| 915 | |
| 916 | value = WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT | WIN_A_OF_INT; |
| 917 | tegra_dc_writel(dc, value, DC_CMD_INT_TYPE); |
| 918 | |
| 919 | value = WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT | |
| 920 | WIN_A_OF_INT | WIN_B_OF_INT | WIN_C_OF_INT; |
| 921 | tegra_dc_writel(dc, value, DC_CMD_INT_POLARITY); |
| 922 | |
Thierry Reding | d8f4a9e | 2012-11-15 21:28:22 +0000 | [diff] [blame] | 923 | /* initialize timer */ |
| 924 | value = CURSOR_THRESHOLD(0) | WINDOW_A_THRESHOLD(0x20) | |
| 925 | WINDOW_B_THRESHOLD(0x20) | WINDOW_C_THRESHOLD(0x20); |
| 926 | tegra_dc_writel(dc, value, DC_DISP_DISP_MEM_HIGH_PRIORITY); |
| 927 | |
| 928 | value = CURSOR_THRESHOLD(0) | WINDOW_A_THRESHOLD(1) | |
| 929 | WINDOW_B_THRESHOLD(1) | WINDOW_C_THRESHOLD(1); |
| 930 | tegra_dc_writel(dc, value, DC_DISP_DISP_MEM_HIGH_PRIORITY_TIMER); |
| 931 | |
| 932 | value = VBLANK_INT | WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT; |
Thierry Reding | d8f4a9e | 2012-11-15 21:28:22 +0000 | [diff] [blame] | 933 | tegra_dc_writel(dc, value, DC_CMD_INT_ENABLE); |
Thierry Reding | 6e5ff99 | 2012-11-28 11:45:47 +0100 | [diff] [blame] | 934 | |
| 935 | value = WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT; |
| 936 | tegra_dc_writel(dc, value, DC_CMD_INT_MASK); |
Thierry Reding | d8f4a9e | 2012-11-15 21:28:22 +0000 | [diff] [blame] | 937 | } |
| 938 | |
| 939 | static void tegra_crtc_commit(struct drm_crtc *crtc) |
| 940 | { |
| 941 | struct tegra_dc *dc = to_tegra_dc(crtc); |
Thierry Reding | d8f4a9e | 2012-11-15 21:28:22 +0000 | [diff] [blame] | 942 | unsigned long value; |
| 943 | |
Thierry Reding | 3b9e71e | 2013-01-15 12:21:36 +0100 | [diff] [blame] | 944 | value = GENERAL_UPDATE | WIN_A_UPDATE; |
| 945 | tegra_dc_writel(dc, value, DC_CMD_STATE_CONTROL); |
Thierry Reding | d8f4a9e | 2012-11-15 21:28:22 +0000 | [diff] [blame] | 946 | |
Thierry Reding | 3b9e71e | 2013-01-15 12:21:36 +0100 | [diff] [blame] | 947 | value = GENERAL_ACT_REQ | WIN_A_ACT_REQ; |
Thierry Reding | 6e5ff99 | 2012-11-28 11:45:47 +0100 | [diff] [blame] | 948 | tegra_dc_writel(dc, value, DC_CMD_STATE_CONTROL); |
Thierry Reding | d8f4a9e | 2012-11-15 21:28:22 +0000 | [diff] [blame] | 949 | |
Thierry Reding | 6e5ff99 | 2012-11-28 11:45:47 +0100 | [diff] [blame] | 950 | drm_vblank_post_modeset(crtc->dev, dc->pipe); |
Thierry Reding | d8f4a9e | 2012-11-15 21:28:22 +0000 | [diff] [blame] | 951 | } |
| 952 | |
| 953 | static void tegra_crtc_load_lut(struct drm_crtc *crtc) |
| 954 | { |
| 955 | } |
| 956 | |
| 957 | static const struct drm_crtc_helper_funcs tegra_crtc_helper_funcs = { |
Thierry Reding | f34bc78 | 2012-11-04 21:47:13 +0100 | [diff] [blame] | 958 | .disable = tegra_crtc_disable, |
Thierry Reding | d8f4a9e | 2012-11-15 21:28:22 +0000 | [diff] [blame] | 959 | .mode_fixup = tegra_crtc_mode_fixup, |
| 960 | .mode_set = tegra_crtc_mode_set, |
Thierry Reding | 23fb474 | 2012-11-28 11:38:24 +0100 | [diff] [blame] | 961 | .mode_set_base = tegra_crtc_mode_set_base, |
Thierry Reding | d8f4a9e | 2012-11-15 21:28:22 +0000 | [diff] [blame] | 962 | .prepare = tegra_crtc_prepare, |
| 963 | .commit = tegra_crtc_commit, |
| 964 | .load_lut = tegra_crtc_load_lut, |
| 965 | }; |
| 966 | |
Thierry Reding | 6e5ff99 | 2012-11-28 11:45:47 +0100 | [diff] [blame] | 967 | static irqreturn_t tegra_dc_irq(int irq, void *data) |
Thierry Reding | d8f4a9e | 2012-11-15 21:28:22 +0000 | [diff] [blame] | 968 | { |
| 969 | struct tegra_dc *dc = data; |
| 970 | unsigned long status; |
| 971 | |
| 972 | status = tegra_dc_readl(dc, DC_CMD_INT_STATUS); |
| 973 | tegra_dc_writel(dc, status, DC_CMD_INT_STATUS); |
| 974 | |
| 975 | if (status & FRAME_END_INT) { |
| 976 | /* |
| 977 | dev_dbg(dc->dev, "%s(): frame end\n", __func__); |
| 978 | */ |
| 979 | } |
| 980 | |
| 981 | if (status & VBLANK_INT) { |
| 982 | /* |
| 983 | dev_dbg(dc->dev, "%s(): vertical blank\n", __func__); |
| 984 | */ |
| 985 | drm_handle_vblank(dc->base.dev, dc->pipe); |
Thierry Reding | 3c03c46 | 2012-11-28 12:00:18 +0100 | [diff] [blame] | 986 | tegra_dc_finish_page_flip(dc); |
Thierry Reding | d8f4a9e | 2012-11-15 21:28:22 +0000 | [diff] [blame] | 987 | } |
| 988 | |
| 989 | if (status & (WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT)) { |
| 990 | /* |
| 991 | dev_dbg(dc->dev, "%s(): underflow\n", __func__); |
| 992 | */ |
| 993 | } |
| 994 | |
| 995 | return IRQ_HANDLED; |
| 996 | } |
| 997 | |
| 998 | static int tegra_dc_show_regs(struct seq_file *s, void *data) |
| 999 | { |
| 1000 | struct drm_info_node *node = s->private; |
| 1001 | struct tegra_dc *dc = node->info_ent->data; |
| 1002 | |
| 1003 | #define DUMP_REG(name) \ |
| 1004 | seq_printf(s, "%-40s %#05x %08lx\n", #name, name, \ |
| 1005 | tegra_dc_readl(dc, name)) |
| 1006 | |
| 1007 | DUMP_REG(DC_CMD_GENERAL_INCR_SYNCPT); |
| 1008 | DUMP_REG(DC_CMD_GENERAL_INCR_SYNCPT_CNTRL); |
| 1009 | DUMP_REG(DC_CMD_GENERAL_INCR_SYNCPT_ERROR); |
| 1010 | DUMP_REG(DC_CMD_WIN_A_INCR_SYNCPT); |
| 1011 | DUMP_REG(DC_CMD_WIN_A_INCR_SYNCPT_CNTRL); |
| 1012 | DUMP_REG(DC_CMD_WIN_A_INCR_SYNCPT_ERROR); |
| 1013 | DUMP_REG(DC_CMD_WIN_B_INCR_SYNCPT); |
| 1014 | DUMP_REG(DC_CMD_WIN_B_INCR_SYNCPT_CNTRL); |
| 1015 | DUMP_REG(DC_CMD_WIN_B_INCR_SYNCPT_ERROR); |
| 1016 | DUMP_REG(DC_CMD_WIN_C_INCR_SYNCPT); |
| 1017 | DUMP_REG(DC_CMD_WIN_C_INCR_SYNCPT_CNTRL); |
| 1018 | DUMP_REG(DC_CMD_WIN_C_INCR_SYNCPT_ERROR); |
| 1019 | DUMP_REG(DC_CMD_CONT_SYNCPT_VSYNC); |
| 1020 | DUMP_REG(DC_CMD_DISPLAY_COMMAND_OPTION0); |
| 1021 | DUMP_REG(DC_CMD_DISPLAY_COMMAND); |
| 1022 | DUMP_REG(DC_CMD_SIGNAL_RAISE); |
| 1023 | DUMP_REG(DC_CMD_DISPLAY_POWER_CONTROL); |
| 1024 | DUMP_REG(DC_CMD_INT_STATUS); |
| 1025 | DUMP_REG(DC_CMD_INT_MASK); |
| 1026 | DUMP_REG(DC_CMD_INT_ENABLE); |
| 1027 | DUMP_REG(DC_CMD_INT_TYPE); |
| 1028 | DUMP_REG(DC_CMD_INT_POLARITY); |
| 1029 | DUMP_REG(DC_CMD_SIGNAL_RAISE1); |
| 1030 | DUMP_REG(DC_CMD_SIGNAL_RAISE2); |
| 1031 | DUMP_REG(DC_CMD_SIGNAL_RAISE3); |
| 1032 | DUMP_REG(DC_CMD_STATE_ACCESS); |
| 1033 | DUMP_REG(DC_CMD_STATE_CONTROL); |
| 1034 | DUMP_REG(DC_CMD_DISPLAY_WINDOW_HEADER); |
| 1035 | DUMP_REG(DC_CMD_REG_ACT_CONTROL); |
| 1036 | DUMP_REG(DC_COM_CRC_CONTROL); |
| 1037 | DUMP_REG(DC_COM_CRC_CHECKSUM); |
| 1038 | DUMP_REG(DC_COM_PIN_OUTPUT_ENABLE(0)); |
| 1039 | DUMP_REG(DC_COM_PIN_OUTPUT_ENABLE(1)); |
| 1040 | DUMP_REG(DC_COM_PIN_OUTPUT_ENABLE(2)); |
| 1041 | DUMP_REG(DC_COM_PIN_OUTPUT_ENABLE(3)); |
| 1042 | DUMP_REG(DC_COM_PIN_OUTPUT_POLARITY(0)); |
| 1043 | DUMP_REG(DC_COM_PIN_OUTPUT_POLARITY(1)); |
| 1044 | DUMP_REG(DC_COM_PIN_OUTPUT_POLARITY(2)); |
| 1045 | DUMP_REG(DC_COM_PIN_OUTPUT_POLARITY(3)); |
| 1046 | DUMP_REG(DC_COM_PIN_OUTPUT_DATA(0)); |
| 1047 | DUMP_REG(DC_COM_PIN_OUTPUT_DATA(1)); |
| 1048 | DUMP_REG(DC_COM_PIN_OUTPUT_DATA(2)); |
| 1049 | DUMP_REG(DC_COM_PIN_OUTPUT_DATA(3)); |
| 1050 | DUMP_REG(DC_COM_PIN_INPUT_ENABLE(0)); |
| 1051 | DUMP_REG(DC_COM_PIN_INPUT_ENABLE(1)); |
| 1052 | DUMP_REG(DC_COM_PIN_INPUT_ENABLE(2)); |
| 1053 | DUMP_REG(DC_COM_PIN_INPUT_ENABLE(3)); |
| 1054 | DUMP_REG(DC_COM_PIN_INPUT_DATA(0)); |
| 1055 | DUMP_REG(DC_COM_PIN_INPUT_DATA(1)); |
| 1056 | DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(0)); |
| 1057 | DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(1)); |
| 1058 | DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(2)); |
| 1059 | DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(3)); |
| 1060 | DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(4)); |
| 1061 | DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(5)); |
| 1062 | DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(6)); |
| 1063 | DUMP_REG(DC_COM_PIN_MISC_CONTROL); |
| 1064 | DUMP_REG(DC_COM_PIN_PM0_CONTROL); |
| 1065 | DUMP_REG(DC_COM_PIN_PM0_DUTY_CYCLE); |
| 1066 | DUMP_REG(DC_COM_PIN_PM1_CONTROL); |
| 1067 | DUMP_REG(DC_COM_PIN_PM1_DUTY_CYCLE); |
| 1068 | DUMP_REG(DC_COM_SPI_CONTROL); |
| 1069 | DUMP_REG(DC_COM_SPI_START_BYTE); |
| 1070 | DUMP_REG(DC_COM_HSPI_WRITE_DATA_AB); |
| 1071 | DUMP_REG(DC_COM_HSPI_WRITE_DATA_CD); |
| 1072 | DUMP_REG(DC_COM_HSPI_CS_DC); |
| 1073 | DUMP_REG(DC_COM_SCRATCH_REGISTER_A); |
| 1074 | DUMP_REG(DC_COM_SCRATCH_REGISTER_B); |
| 1075 | DUMP_REG(DC_COM_GPIO_CTRL); |
| 1076 | DUMP_REG(DC_COM_GPIO_DEBOUNCE_COUNTER); |
| 1077 | DUMP_REG(DC_COM_CRC_CHECKSUM_LATCHED); |
| 1078 | DUMP_REG(DC_DISP_DISP_SIGNAL_OPTIONS0); |
| 1079 | DUMP_REG(DC_DISP_DISP_SIGNAL_OPTIONS1); |
| 1080 | DUMP_REG(DC_DISP_DISP_WIN_OPTIONS); |
| 1081 | DUMP_REG(DC_DISP_DISP_MEM_HIGH_PRIORITY); |
| 1082 | DUMP_REG(DC_DISP_DISP_MEM_HIGH_PRIORITY_TIMER); |
| 1083 | DUMP_REG(DC_DISP_DISP_TIMING_OPTIONS); |
| 1084 | DUMP_REG(DC_DISP_REF_TO_SYNC); |
| 1085 | DUMP_REG(DC_DISP_SYNC_WIDTH); |
| 1086 | DUMP_REG(DC_DISP_BACK_PORCH); |
| 1087 | DUMP_REG(DC_DISP_ACTIVE); |
| 1088 | DUMP_REG(DC_DISP_FRONT_PORCH); |
| 1089 | DUMP_REG(DC_DISP_H_PULSE0_CONTROL); |
| 1090 | DUMP_REG(DC_DISP_H_PULSE0_POSITION_A); |
| 1091 | DUMP_REG(DC_DISP_H_PULSE0_POSITION_B); |
| 1092 | DUMP_REG(DC_DISP_H_PULSE0_POSITION_C); |
| 1093 | DUMP_REG(DC_DISP_H_PULSE0_POSITION_D); |
| 1094 | DUMP_REG(DC_DISP_H_PULSE1_CONTROL); |
| 1095 | DUMP_REG(DC_DISP_H_PULSE1_POSITION_A); |
| 1096 | DUMP_REG(DC_DISP_H_PULSE1_POSITION_B); |
| 1097 | DUMP_REG(DC_DISP_H_PULSE1_POSITION_C); |
| 1098 | DUMP_REG(DC_DISP_H_PULSE1_POSITION_D); |
| 1099 | DUMP_REG(DC_DISP_H_PULSE2_CONTROL); |
| 1100 | DUMP_REG(DC_DISP_H_PULSE2_POSITION_A); |
| 1101 | DUMP_REG(DC_DISP_H_PULSE2_POSITION_B); |
| 1102 | DUMP_REG(DC_DISP_H_PULSE2_POSITION_C); |
| 1103 | DUMP_REG(DC_DISP_H_PULSE2_POSITION_D); |
| 1104 | DUMP_REG(DC_DISP_V_PULSE0_CONTROL); |
| 1105 | DUMP_REG(DC_DISP_V_PULSE0_POSITION_A); |
| 1106 | DUMP_REG(DC_DISP_V_PULSE0_POSITION_B); |
| 1107 | DUMP_REG(DC_DISP_V_PULSE0_POSITION_C); |
| 1108 | DUMP_REG(DC_DISP_V_PULSE1_CONTROL); |
| 1109 | DUMP_REG(DC_DISP_V_PULSE1_POSITION_A); |
| 1110 | DUMP_REG(DC_DISP_V_PULSE1_POSITION_B); |
| 1111 | DUMP_REG(DC_DISP_V_PULSE1_POSITION_C); |
| 1112 | DUMP_REG(DC_DISP_V_PULSE2_CONTROL); |
| 1113 | DUMP_REG(DC_DISP_V_PULSE2_POSITION_A); |
| 1114 | DUMP_REG(DC_DISP_V_PULSE3_CONTROL); |
| 1115 | DUMP_REG(DC_DISP_V_PULSE3_POSITION_A); |
| 1116 | DUMP_REG(DC_DISP_M0_CONTROL); |
| 1117 | DUMP_REG(DC_DISP_M1_CONTROL); |
| 1118 | DUMP_REG(DC_DISP_DI_CONTROL); |
| 1119 | DUMP_REG(DC_DISP_PP_CONTROL); |
| 1120 | DUMP_REG(DC_DISP_PP_SELECT_A); |
| 1121 | DUMP_REG(DC_DISP_PP_SELECT_B); |
| 1122 | DUMP_REG(DC_DISP_PP_SELECT_C); |
| 1123 | DUMP_REG(DC_DISP_PP_SELECT_D); |
| 1124 | DUMP_REG(DC_DISP_DISP_CLOCK_CONTROL); |
| 1125 | DUMP_REG(DC_DISP_DISP_INTERFACE_CONTROL); |
| 1126 | DUMP_REG(DC_DISP_DISP_COLOR_CONTROL); |
| 1127 | DUMP_REG(DC_DISP_SHIFT_CLOCK_OPTIONS); |
| 1128 | DUMP_REG(DC_DISP_DATA_ENABLE_OPTIONS); |
| 1129 | DUMP_REG(DC_DISP_SERIAL_INTERFACE_OPTIONS); |
| 1130 | DUMP_REG(DC_DISP_LCD_SPI_OPTIONS); |
| 1131 | DUMP_REG(DC_DISP_BORDER_COLOR); |
| 1132 | DUMP_REG(DC_DISP_COLOR_KEY0_LOWER); |
| 1133 | DUMP_REG(DC_DISP_COLOR_KEY0_UPPER); |
| 1134 | DUMP_REG(DC_DISP_COLOR_KEY1_LOWER); |
| 1135 | DUMP_REG(DC_DISP_COLOR_KEY1_UPPER); |
| 1136 | DUMP_REG(DC_DISP_CURSOR_FOREGROUND); |
| 1137 | DUMP_REG(DC_DISP_CURSOR_BACKGROUND); |
| 1138 | DUMP_REG(DC_DISP_CURSOR_START_ADDR); |
| 1139 | DUMP_REG(DC_DISP_CURSOR_START_ADDR_NS); |
| 1140 | DUMP_REG(DC_DISP_CURSOR_POSITION); |
| 1141 | DUMP_REG(DC_DISP_CURSOR_POSITION_NS); |
| 1142 | DUMP_REG(DC_DISP_INIT_SEQ_CONTROL); |
| 1143 | DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_A); |
| 1144 | DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_B); |
| 1145 | DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_C); |
| 1146 | DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_D); |
| 1147 | DUMP_REG(DC_DISP_DC_MCCIF_FIFOCTRL); |
| 1148 | DUMP_REG(DC_DISP_MCCIF_DISPLAY0A_HYST); |
| 1149 | DUMP_REG(DC_DISP_MCCIF_DISPLAY0B_HYST); |
| 1150 | DUMP_REG(DC_DISP_MCCIF_DISPLAY1A_HYST); |
| 1151 | DUMP_REG(DC_DISP_MCCIF_DISPLAY1B_HYST); |
| 1152 | DUMP_REG(DC_DISP_DAC_CRT_CTRL); |
| 1153 | DUMP_REG(DC_DISP_DISP_MISC_CONTROL); |
| 1154 | DUMP_REG(DC_DISP_SD_CONTROL); |
| 1155 | DUMP_REG(DC_DISP_SD_CSC_COEFF); |
| 1156 | DUMP_REG(DC_DISP_SD_LUT(0)); |
| 1157 | DUMP_REG(DC_DISP_SD_LUT(1)); |
| 1158 | DUMP_REG(DC_DISP_SD_LUT(2)); |
| 1159 | DUMP_REG(DC_DISP_SD_LUT(3)); |
| 1160 | DUMP_REG(DC_DISP_SD_LUT(4)); |
| 1161 | DUMP_REG(DC_DISP_SD_LUT(5)); |
| 1162 | DUMP_REG(DC_DISP_SD_LUT(6)); |
| 1163 | DUMP_REG(DC_DISP_SD_LUT(7)); |
| 1164 | DUMP_REG(DC_DISP_SD_LUT(8)); |
| 1165 | DUMP_REG(DC_DISP_SD_FLICKER_CONTROL); |
| 1166 | DUMP_REG(DC_DISP_DC_PIXEL_COUNT); |
| 1167 | DUMP_REG(DC_DISP_SD_HISTOGRAM(0)); |
| 1168 | DUMP_REG(DC_DISP_SD_HISTOGRAM(1)); |
| 1169 | DUMP_REG(DC_DISP_SD_HISTOGRAM(2)); |
| 1170 | DUMP_REG(DC_DISP_SD_HISTOGRAM(3)); |
| 1171 | DUMP_REG(DC_DISP_SD_HISTOGRAM(4)); |
| 1172 | DUMP_REG(DC_DISP_SD_HISTOGRAM(5)); |
| 1173 | DUMP_REG(DC_DISP_SD_HISTOGRAM(6)); |
| 1174 | DUMP_REG(DC_DISP_SD_HISTOGRAM(7)); |
| 1175 | DUMP_REG(DC_DISP_SD_BL_TF(0)); |
| 1176 | DUMP_REG(DC_DISP_SD_BL_TF(1)); |
| 1177 | DUMP_REG(DC_DISP_SD_BL_TF(2)); |
| 1178 | DUMP_REG(DC_DISP_SD_BL_TF(3)); |
| 1179 | DUMP_REG(DC_DISP_SD_BL_CONTROL); |
| 1180 | DUMP_REG(DC_DISP_SD_HW_K_VALUES); |
| 1181 | DUMP_REG(DC_DISP_SD_MAN_K_VALUES); |
Thierry Reding | e687651 | 2013-12-20 13:58:33 +0100 | [diff] [blame] | 1182 | DUMP_REG(DC_DISP_CURSOR_START_ADDR_HI); |
| 1183 | DUMP_REG(DC_DISP_BLEND_CURSOR_CONTROL); |
Thierry Reding | d8f4a9e | 2012-11-15 21:28:22 +0000 | [diff] [blame] | 1184 | DUMP_REG(DC_WIN_WIN_OPTIONS); |
| 1185 | DUMP_REG(DC_WIN_BYTE_SWAP); |
| 1186 | DUMP_REG(DC_WIN_BUFFER_CONTROL); |
| 1187 | DUMP_REG(DC_WIN_COLOR_DEPTH); |
| 1188 | DUMP_REG(DC_WIN_POSITION); |
| 1189 | DUMP_REG(DC_WIN_SIZE); |
| 1190 | DUMP_REG(DC_WIN_PRESCALED_SIZE); |
| 1191 | DUMP_REG(DC_WIN_H_INITIAL_DDA); |
| 1192 | DUMP_REG(DC_WIN_V_INITIAL_DDA); |
| 1193 | DUMP_REG(DC_WIN_DDA_INC); |
| 1194 | DUMP_REG(DC_WIN_LINE_STRIDE); |
| 1195 | DUMP_REG(DC_WIN_BUF_STRIDE); |
| 1196 | DUMP_REG(DC_WIN_UV_BUF_STRIDE); |
| 1197 | DUMP_REG(DC_WIN_BUFFER_ADDR_MODE); |
| 1198 | DUMP_REG(DC_WIN_DV_CONTROL); |
| 1199 | DUMP_REG(DC_WIN_BLEND_NOKEY); |
| 1200 | DUMP_REG(DC_WIN_BLEND_1WIN); |
| 1201 | DUMP_REG(DC_WIN_BLEND_2WIN_X); |
| 1202 | DUMP_REG(DC_WIN_BLEND_2WIN_Y); |
Thierry Reding | f34bc78 | 2012-11-04 21:47:13 +0100 | [diff] [blame] | 1203 | DUMP_REG(DC_WIN_BLEND_3WIN_XY); |
Thierry Reding | d8f4a9e | 2012-11-15 21:28:22 +0000 | [diff] [blame] | 1204 | DUMP_REG(DC_WIN_HP_FETCH_CONTROL); |
| 1205 | DUMP_REG(DC_WINBUF_START_ADDR); |
| 1206 | DUMP_REG(DC_WINBUF_START_ADDR_NS); |
| 1207 | DUMP_REG(DC_WINBUF_START_ADDR_U); |
| 1208 | DUMP_REG(DC_WINBUF_START_ADDR_U_NS); |
| 1209 | DUMP_REG(DC_WINBUF_START_ADDR_V); |
| 1210 | DUMP_REG(DC_WINBUF_START_ADDR_V_NS); |
| 1211 | DUMP_REG(DC_WINBUF_ADDR_H_OFFSET); |
| 1212 | DUMP_REG(DC_WINBUF_ADDR_H_OFFSET_NS); |
| 1213 | DUMP_REG(DC_WINBUF_ADDR_V_OFFSET); |
| 1214 | DUMP_REG(DC_WINBUF_ADDR_V_OFFSET_NS); |
| 1215 | DUMP_REG(DC_WINBUF_UFLOW_STATUS); |
| 1216 | DUMP_REG(DC_WINBUF_AD_UFLOW_STATUS); |
| 1217 | DUMP_REG(DC_WINBUF_BD_UFLOW_STATUS); |
| 1218 | DUMP_REG(DC_WINBUF_CD_UFLOW_STATUS); |
| 1219 | |
| 1220 | #undef DUMP_REG |
| 1221 | |
| 1222 | return 0; |
| 1223 | } |
| 1224 | |
| 1225 | static struct drm_info_list debugfs_files[] = { |
| 1226 | { "regs", tegra_dc_show_regs, 0, NULL }, |
| 1227 | }; |
| 1228 | |
| 1229 | static int tegra_dc_debugfs_init(struct tegra_dc *dc, struct drm_minor *minor) |
| 1230 | { |
| 1231 | unsigned int i; |
| 1232 | char *name; |
| 1233 | int err; |
| 1234 | |
| 1235 | name = kasprintf(GFP_KERNEL, "dc.%d", dc->pipe); |
| 1236 | dc->debugfs = debugfs_create_dir(name, minor->debugfs_root); |
| 1237 | kfree(name); |
| 1238 | |
| 1239 | if (!dc->debugfs) |
| 1240 | return -ENOMEM; |
| 1241 | |
| 1242 | dc->debugfs_files = kmemdup(debugfs_files, sizeof(debugfs_files), |
| 1243 | GFP_KERNEL); |
| 1244 | if (!dc->debugfs_files) { |
| 1245 | err = -ENOMEM; |
| 1246 | goto remove; |
| 1247 | } |
| 1248 | |
| 1249 | for (i = 0; i < ARRAY_SIZE(debugfs_files); i++) |
| 1250 | dc->debugfs_files[i].data = dc; |
| 1251 | |
| 1252 | err = drm_debugfs_create_files(dc->debugfs_files, |
| 1253 | ARRAY_SIZE(debugfs_files), |
| 1254 | dc->debugfs, minor); |
| 1255 | if (err < 0) |
| 1256 | goto free; |
| 1257 | |
| 1258 | dc->minor = minor; |
| 1259 | |
| 1260 | return 0; |
| 1261 | |
| 1262 | free: |
| 1263 | kfree(dc->debugfs_files); |
| 1264 | dc->debugfs_files = NULL; |
| 1265 | remove: |
| 1266 | debugfs_remove(dc->debugfs); |
| 1267 | dc->debugfs = NULL; |
| 1268 | |
| 1269 | return err; |
| 1270 | } |
| 1271 | |
| 1272 | static int tegra_dc_debugfs_exit(struct tegra_dc *dc) |
| 1273 | { |
| 1274 | drm_debugfs_remove_files(dc->debugfs_files, ARRAY_SIZE(debugfs_files), |
| 1275 | dc->minor); |
| 1276 | dc->minor = NULL; |
| 1277 | |
| 1278 | kfree(dc->debugfs_files); |
| 1279 | dc->debugfs_files = NULL; |
| 1280 | |
| 1281 | debugfs_remove(dc->debugfs); |
| 1282 | dc->debugfs = NULL; |
| 1283 | |
| 1284 | return 0; |
| 1285 | } |
| 1286 | |
Thierry Reding | 53fa7f7 | 2013-09-24 15:35:40 +0200 | [diff] [blame] | 1287 | static int tegra_dc_init(struct host1x_client *client) |
Thierry Reding | d8f4a9e | 2012-11-15 21:28:22 +0000 | [diff] [blame] | 1288 | { |
Thierry Reding | 9910f5c | 2014-05-22 09:57:15 +0200 | [diff] [blame] | 1289 | struct drm_device *drm = dev_get_drvdata(client->parent); |
Thierry Reding | 776dc38 | 2013-10-14 14:43:22 +0200 | [diff] [blame] | 1290 | struct tegra_dc *dc = host1x_client_to_dc(client); |
Thierry Reding | d1f3e1e | 2014-07-11 08:29:14 +0200 | [diff] [blame] | 1291 | struct tegra_drm *tegra = drm->dev_private; |
Thierry Reding | d8f4a9e | 2012-11-15 21:28:22 +0000 | [diff] [blame] | 1292 | int err; |
| 1293 | |
Thierry Reding | df06b75 | 2014-06-26 21:41:53 +0200 | [diff] [blame^] | 1294 | if (tegra->domain) { |
| 1295 | err = iommu_attach_device(tegra->domain, dc->dev); |
| 1296 | if (err < 0) { |
| 1297 | dev_err(dc->dev, "failed to attach to domain: %d\n", |
| 1298 | err); |
| 1299 | return err; |
| 1300 | } |
| 1301 | |
| 1302 | dc->domain = tegra->domain; |
| 1303 | } |
| 1304 | |
Thierry Reding | 9910f5c | 2014-05-22 09:57:15 +0200 | [diff] [blame] | 1305 | drm_crtc_init(drm, &dc->base, &tegra_crtc_funcs); |
Thierry Reding | d8f4a9e | 2012-11-15 21:28:22 +0000 | [diff] [blame] | 1306 | drm_mode_crtc_set_gamma_size(&dc->base, 256); |
| 1307 | drm_crtc_helper_add(&dc->base, &tegra_crtc_helper_funcs); |
| 1308 | |
Thierry Reding | d1f3e1e | 2014-07-11 08:29:14 +0200 | [diff] [blame] | 1309 | /* |
| 1310 | * Keep track of the minimum pitch alignment across all display |
| 1311 | * controllers. |
| 1312 | */ |
| 1313 | if (dc->soc->pitch_align > tegra->pitch_align) |
| 1314 | tegra->pitch_align = dc->soc->pitch_align; |
| 1315 | |
Thierry Reding | 9910f5c | 2014-05-22 09:57:15 +0200 | [diff] [blame] | 1316 | err = tegra_dc_rgb_init(drm, dc); |
Thierry Reding | d8f4a9e | 2012-11-15 21:28:22 +0000 | [diff] [blame] | 1317 | if (err < 0 && err != -ENODEV) { |
| 1318 | dev_err(dc->dev, "failed to initialize RGB output: %d\n", err); |
| 1319 | return err; |
| 1320 | } |
| 1321 | |
Thierry Reding | 9910f5c | 2014-05-22 09:57:15 +0200 | [diff] [blame] | 1322 | err = tegra_dc_add_planes(drm, dc); |
Thierry Reding | f34bc78 | 2012-11-04 21:47:13 +0100 | [diff] [blame] | 1323 | if (err < 0) |
| 1324 | return err; |
| 1325 | |
Thierry Reding | d8f4a9e | 2012-11-15 21:28:22 +0000 | [diff] [blame] | 1326 | if (IS_ENABLED(CONFIG_DEBUG_FS)) { |
Thierry Reding | 9910f5c | 2014-05-22 09:57:15 +0200 | [diff] [blame] | 1327 | err = tegra_dc_debugfs_init(dc, drm->primary); |
Thierry Reding | d8f4a9e | 2012-11-15 21:28:22 +0000 | [diff] [blame] | 1328 | if (err < 0) |
| 1329 | dev_err(dc->dev, "debugfs setup failed: %d\n", err); |
| 1330 | } |
| 1331 | |
Thierry Reding | 6e5ff99 | 2012-11-28 11:45:47 +0100 | [diff] [blame] | 1332 | err = devm_request_irq(dc->dev, dc->irq, tegra_dc_irq, 0, |
Thierry Reding | d8f4a9e | 2012-11-15 21:28:22 +0000 | [diff] [blame] | 1333 | dev_name(dc->dev), dc); |
| 1334 | if (err < 0) { |
| 1335 | dev_err(dc->dev, "failed to request IRQ#%u: %d\n", dc->irq, |
| 1336 | err); |
| 1337 | return err; |
| 1338 | } |
| 1339 | |
| 1340 | return 0; |
| 1341 | } |
| 1342 | |
Thierry Reding | 53fa7f7 | 2013-09-24 15:35:40 +0200 | [diff] [blame] | 1343 | static int tegra_dc_exit(struct host1x_client *client) |
Thierry Reding | d8f4a9e | 2012-11-15 21:28:22 +0000 | [diff] [blame] | 1344 | { |
Thierry Reding | 776dc38 | 2013-10-14 14:43:22 +0200 | [diff] [blame] | 1345 | struct tegra_dc *dc = host1x_client_to_dc(client); |
Thierry Reding | d8f4a9e | 2012-11-15 21:28:22 +0000 | [diff] [blame] | 1346 | int err; |
| 1347 | |
| 1348 | devm_free_irq(dc->dev, dc->irq, dc); |
| 1349 | |
| 1350 | if (IS_ENABLED(CONFIG_DEBUG_FS)) { |
| 1351 | err = tegra_dc_debugfs_exit(dc); |
| 1352 | if (err < 0) |
| 1353 | dev_err(dc->dev, "debugfs cleanup failed: %d\n", err); |
| 1354 | } |
| 1355 | |
| 1356 | err = tegra_dc_rgb_exit(dc); |
| 1357 | if (err) { |
| 1358 | dev_err(dc->dev, "failed to shutdown RGB output: %d\n", err); |
| 1359 | return err; |
| 1360 | } |
| 1361 | |
Thierry Reding | df06b75 | 2014-06-26 21:41:53 +0200 | [diff] [blame^] | 1362 | if (dc->domain) { |
| 1363 | iommu_detach_device(dc->domain, dc->dev); |
| 1364 | dc->domain = NULL; |
| 1365 | } |
| 1366 | |
Thierry Reding | d8f4a9e | 2012-11-15 21:28:22 +0000 | [diff] [blame] | 1367 | return 0; |
| 1368 | } |
| 1369 | |
| 1370 | static const struct host1x_client_ops dc_client_ops = { |
Thierry Reding | 53fa7f7 | 2013-09-24 15:35:40 +0200 | [diff] [blame] | 1371 | .init = tegra_dc_init, |
| 1372 | .exit = tegra_dc_exit, |
Thierry Reding | d8f4a9e | 2012-11-15 21:28:22 +0000 | [diff] [blame] | 1373 | }; |
| 1374 | |
Thierry Reding | 8620fc6 | 2013-12-12 11:03:59 +0100 | [diff] [blame] | 1375 | static const struct tegra_dc_soc_info tegra20_dc_soc_info = { |
| 1376 | .supports_interlacing = false, |
Thierry Reding | e687651 | 2013-12-20 13:58:33 +0100 | [diff] [blame] | 1377 | .supports_cursor = false, |
Thierry Reding | c134f01 | 2014-06-03 14:48:12 +0200 | [diff] [blame] | 1378 | .supports_block_linear = false, |
Thierry Reding | d1f3e1e | 2014-07-11 08:29:14 +0200 | [diff] [blame] | 1379 | .pitch_align = 8, |
Thierry Reding | 9c01270 | 2014-07-07 15:32:53 +0200 | [diff] [blame] | 1380 | .has_powergate = false, |
Thierry Reding | 8620fc6 | 2013-12-12 11:03:59 +0100 | [diff] [blame] | 1381 | }; |
| 1382 | |
| 1383 | static const struct tegra_dc_soc_info tegra30_dc_soc_info = { |
| 1384 | .supports_interlacing = false, |
Thierry Reding | e687651 | 2013-12-20 13:58:33 +0100 | [diff] [blame] | 1385 | .supports_cursor = false, |
Thierry Reding | c134f01 | 2014-06-03 14:48:12 +0200 | [diff] [blame] | 1386 | .supports_block_linear = false, |
Thierry Reding | d1f3e1e | 2014-07-11 08:29:14 +0200 | [diff] [blame] | 1387 | .pitch_align = 8, |
Thierry Reding | 9c01270 | 2014-07-07 15:32:53 +0200 | [diff] [blame] | 1388 | .has_powergate = false, |
Thierry Reding | d1f3e1e | 2014-07-11 08:29:14 +0200 | [diff] [blame] | 1389 | }; |
| 1390 | |
| 1391 | static const struct tegra_dc_soc_info tegra114_dc_soc_info = { |
| 1392 | .supports_interlacing = false, |
| 1393 | .supports_cursor = false, |
| 1394 | .supports_block_linear = false, |
| 1395 | .pitch_align = 64, |
Thierry Reding | 9c01270 | 2014-07-07 15:32:53 +0200 | [diff] [blame] | 1396 | .has_powergate = true, |
Thierry Reding | 8620fc6 | 2013-12-12 11:03:59 +0100 | [diff] [blame] | 1397 | }; |
| 1398 | |
| 1399 | static const struct tegra_dc_soc_info tegra124_dc_soc_info = { |
| 1400 | .supports_interlacing = true, |
Thierry Reding | e687651 | 2013-12-20 13:58:33 +0100 | [diff] [blame] | 1401 | .supports_cursor = true, |
Thierry Reding | c134f01 | 2014-06-03 14:48:12 +0200 | [diff] [blame] | 1402 | .supports_block_linear = true, |
Thierry Reding | d1f3e1e | 2014-07-11 08:29:14 +0200 | [diff] [blame] | 1403 | .pitch_align = 64, |
Thierry Reding | 9c01270 | 2014-07-07 15:32:53 +0200 | [diff] [blame] | 1404 | .has_powergate = true, |
Thierry Reding | 8620fc6 | 2013-12-12 11:03:59 +0100 | [diff] [blame] | 1405 | }; |
| 1406 | |
| 1407 | static const struct of_device_id tegra_dc_of_match[] = { |
| 1408 | { |
| 1409 | .compatible = "nvidia,tegra124-dc", |
| 1410 | .data = &tegra124_dc_soc_info, |
| 1411 | }, { |
Thierry Reding | 9c01270 | 2014-07-07 15:32:53 +0200 | [diff] [blame] | 1412 | .compatible = "nvidia,tegra114-dc", |
| 1413 | .data = &tegra114_dc_soc_info, |
| 1414 | }, { |
Thierry Reding | 8620fc6 | 2013-12-12 11:03:59 +0100 | [diff] [blame] | 1415 | .compatible = "nvidia,tegra30-dc", |
| 1416 | .data = &tegra30_dc_soc_info, |
| 1417 | }, { |
| 1418 | .compatible = "nvidia,tegra20-dc", |
| 1419 | .data = &tegra20_dc_soc_info, |
| 1420 | }, { |
| 1421 | /* sentinel */ |
| 1422 | } |
| 1423 | }; |
Stephen Warren | ef70728 | 2014-06-18 16:21:55 -0600 | [diff] [blame] | 1424 | MODULE_DEVICE_TABLE(of, tegra_dc_of_match); |
Thierry Reding | 8620fc6 | 2013-12-12 11:03:59 +0100 | [diff] [blame] | 1425 | |
Thierry Reding | 13411dd | 2014-01-09 17:08:36 +0100 | [diff] [blame] | 1426 | static int tegra_dc_parse_dt(struct tegra_dc *dc) |
| 1427 | { |
| 1428 | struct device_node *np; |
| 1429 | u32 value = 0; |
| 1430 | int err; |
| 1431 | |
| 1432 | err = of_property_read_u32(dc->dev->of_node, "nvidia,head", &value); |
| 1433 | if (err < 0) { |
| 1434 | dev_err(dc->dev, "missing \"nvidia,head\" property\n"); |
| 1435 | |
| 1436 | /* |
| 1437 | * If the nvidia,head property isn't present, try to find the |
| 1438 | * correct head number by looking up the position of this |
| 1439 | * display controller's node within the device tree. Assuming |
| 1440 | * that the nodes are ordered properly in the DTS file and |
| 1441 | * that the translation into a flattened device tree blob |
| 1442 | * preserves that ordering this will actually yield the right |
| 1443 | * head number. |
| 1444 | * |
| 1445 | * If those assumptions don't hold, this will still work for |
| 1446 | * cases where only a single display controller is used. |
| 1447 | */ |
| 1448 | for_each_matching_node(np, tegra_dc_of_match) { |
| 1449 | if (np == dc->dev->of_node) |
| 1450 | break; |
| 1451 | |
| 1452 | value++; |
| 1453 | } |
| 1454 | } |
| 1455 | |
| 1456 | dc->pipe = value; |
| 1457 | |
| 1458 | return 0; |
| 1459 | } |
| 1460 | |
Thierry Reding | d8f4a9e | 2012-11-15 21:28:22 +0000 | [diff] [blame] | 1461 | static int tegra_dc_probe(struct platform_device *pdev) |
| 1462 | { |
Thierry Reding | 8620fc6 | 2013-12-12 11:03:59 +0100 | [diff] [blame] | 1463 | const struct of_device_id *id; |
Thierry Reding | d8f4a9e | 2012-11-15 21:28:22 +0000 | [diff] [blame] | 1464 | struct resource *regs; |
| 1465 | struct tegra_dc *dc; |
| 1466 | int err; |
| 1467 | |
| 1468 | dc = devm_kzalloc(&pdev->dev, sizeof(*dc), GFP_KERNEL); |
| 1469 | if (!dc) |
| 1470 | return -ENOMEM; |
| 1471 | |
Thierry Reding | 8620fc6 | 2013-12-12 11:03:59 +0100 | [diff] [blame] | 1472 | id = of_match_node(tegra_dc_of_match, pdev->dev.of_node); |
| 1473 | if (!id) |
| 1474 | return -ENODEV; |
| 1475 | |
Thierry Reding | 6e5ff99 | 2012-11-28 11:45:47 +0100 | [diff] [blame] | 1476 | spin_lock_init(&dc->lock); |
Thierry Reding | d8f4a9e | 2012-11-15 21:28:22 +0000 | [diff] [blame] | 1477 | INIT_LIST_HEAD(&dc->list); |
| 1478 | dc->dev = &pdev->dev; |
Thierry Reding | 8620fc6 | 2013-12-12 11:03:59 +0100 | [diff] [blame] | 1479 | dc->soc = id->data; |
Thierry Reding | d8f4a9e | 2012-11-15 21:28:22 +0000 | [diff] [blame] | 1480 | |
Thierry Reding | 13411dd | 2014-01-09 17:08:36 +0100 | [diff] [blame] | 1481 | err = tegra_dc_parse_dt(dc); |
| 1482 | if (err < 0) |
| 1483 | return err; |
| 1484 | |
Thierry Reding | d8f4a9e | 2012-11-15 21:28:22 +0000 | [diff] [blame] | 1485 | dc->clk = devm_clk_get(&pdev->dev, NULL); |
| 1486 | if (IS_ERR(dc->clk)) { |
| 1487 | dev_err(&pdev->dev, "failed to get clock\n"); |
| 1488 | return PTR_ERR(dc->clk); |
| 1489 | } |
| 1490 | |
Stephen Warren | ca48080 | 2013-11-06 16:20:54 -0700 | [diff] [blame] | 1491 | dc->rst = devm_reset_control_get(&pdev->dev, "dc"); |
| 1492 | if (IS_ERR(dc->rst)) { |
| 1493 | dev_err(&pdev->dev, "failed to get reset\n"); |
| 1494 | return PTR_ERR(dc->rst); |
| 1495 | } |
| 1496 | |
Thierry Reding | 9c01270 | 2014-07-07 15:32:53 +0200 | [diff] [blame] | 1497 | if (dc->soc->has_powergate) { |
| 1498 | if (dc->pipe == 0) |
| 1499 | dc->powergate = TEGRA_POWERGATE_DIS; |
| 1500 | else |
| 1501 | dc->powergate = TEGRA_POWERGATE_DISB; |
| 1502 | |
| 1503 | err = tegra_powergate_sequence_power_up(dc->powergate, dc->clk, |
| 1504 | dc->rst); |
| 1505 | if (err < 0) { |
| 1506 | dev_err(&pdev->dev, "failed to power partition: %d\n", |
| 1507 | err); |
| 1508 | return err; |
| 1509 | } |
| 1510 | } else { |
| 1511 | err = clk_prepare_enable(dc->clk); |
| 1512 | if (err < 0) { |
| 1513 | dev_err(&pdev->dev, "failed to enable clock: %d\n", |
| 1514 | err); |
| 1515 | return err; |
| 1516 | } |
| 1517 | |
| 1518 | err = reset_control_deassert(dc->rst); |
| 1519 | if (err < 0) { |
| 1520 | dev_err(&pdev->dev, "failed to deassert reset: %d\n", |
| 1521 | err); |
| 1522 | return err; |
| 1523 | } |
| 1524 | } |
Thierry Reding | d8f4a9e | 2012-11-15 21:28:22 +0000 | [diff] [blame] | 1525 | |
| 1526 | regs = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
Thierry Reding | d4ed602 | 2013-01-21 11:09:02 +0100 | [diff] [blame] | 1527 | dc->regs = devm_ioremap_resource(&pdev->dev, regs); |
| 1528 | if (IS_ERR(dc->regs)) |
| 1529 | return PTR_ERR(dc->regs); |
Thierry Reding | d8f4a9e | 2012-11-15 21:28:22 +0000 | [diff] [blame] | 1530 | |
| 1531 | dc->irq = platform_get_irq(pdev, 0); |
| 1532 | if (dc->irq < 0) { |
| 1533 | dev_err(&pdev->dev, "failed to get IRQ\n"); |
| 1534 | return -ENXIO; |
| 1535 | } |
| 1536 | |
Thierry Reding | 776dc38 | 2013-10-14 14:43:22 +0200 | [diff] [blame] | 1537 | INIT_LIST_HEAD(&dc->client.list); |
| 1538 | dc->client.ops = &dc_client_ops; |
| 1539 | dc->client.dev = &pdev->dev; |
Thierry Reding | d8f4a9e | 2012-11-15 21:28:22 +0000 | [diff] [blame] | 1540 | |
| 1541 | err = tegra_dc_rgb_probe(dc); |
| 1542 | if (err < 0 && err != -ENODEV) { |
| 1543 | dev_err(&pdev->dev, "failed to probe RGB output: %d\n", err); |
| 1544 | return err; |
| 1545 | } |
| 1546 | |
Thierry Reding | 776dc38 | 2013-10-14 14:43:22 +0200 | [diff] [blame] | 1547 | err = host1x_client_register(&dc->client); |
Thierry Reding | d8f4a9e | 2012-11-15 21:28:22 +0000 | [diff] [blame] | 1548 | if (err < 0) { |
| 1549 | dev_err(&pdev->dev, "failed to register host1x client: %d\n", |
| 1550 | err); |
| 1551 | return err; |
| 1552 | } |
| 1553 | |
| 1554 | platform_set_drvdata(pdev, dc); |
| 1555 | |
| 1556 | return 0; |
| 1557 | } |
| 1558 | |
| 1559 | static int tegra_dc_remove(struct platform_device *pdev) |
| 1560 | { |
Thierry Reding | d8f4a9e | 2012-11-15 21:28:22 +0000 | [diff] [blame] | 1561 | struct tegra_dc *dc = platform_get_drvdata(pdev); |
| 1562 | int err; |
| 1563 | |
Thierry Reding | 776dc38 | 2013-10-14 14:43:22 +0200 | [diff] [blame] | 1564 | err = host1x_client_unregister(&dc->client); |
Thierry Reding | d8f4a9e | 2012-11-15 21:28:22 +0000 | [diff] [blame] | 1565 | if (err < 0) { |
| 1566 | dev_err(&pdev->dev, "failed to unregister host1x client: %d\n", |
| 1567 | err); |
| 1568 | return err; |
| 1569 | } |
| 1570 | |
Thierry Reding | 59d29c0 | 2013-10-14 14:26:42 +0200 | [diff] [blame] | 1571 | err = tegra_dc_rgb_remove(dc); |
| 1572 | if (err < 0) { |
| 1573 | dev_err(&pdev->dev, "failed to remove RGB output: %d\n", err); |
| 1574 | return err; |
| 1575 | } |
| 1576 | |
Thierry Reding | 5482d75 | 2014-07-11 08:39:03 +0200 | [diff] [blame] | 1577 | reset_control_assert(dc->rst); |
Thierry Reding | 9c01270 | 2014-07-07 15:32:53 +0200 | [diff] [blame] | 1578 | |
| 1579 | if (dc->soc->has_powergate) |
| 1580 | tegra_powergate_power_off(dc->powergate); |
| 1581 | |
Thierry Reding | d8f4a9e | 2012-11-15 21:28:22 +0000 | [diff] [blame] | 1582 | clk_disable_unprepare(dc->clk); |
| 1583 | |
| 1584 | return 0; |
| 1585 | } |
| 1586 | |
Thierry Reding | d8f4a9e | 2012-11-15 21:28:22 +0000 | [diff] [blame] | 1587 | struct platform_driver tegra_dc_driver = { |
| 1588 | .driver = { |
| 1589 | .name = "tegra-dc", |
| 1590 | .owner = THIS_MODULE, |
| 1591 | .of_match_table = tegra_dc_of_match, |
| 1592 | }, |
| 1593 | .probe = tegra_dc_probe, |
| 1594 | .remove = tegra_dc_remove, |
| 1595 | }; |