Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1 | /* |
| 2 | * Copyright © 2008 Intel Corporation |
| 3 | * |
| 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 5 | * copy of this software and associated documentation files (the "Software"), |
| 6 | * to deal in the Software without restriction, including without limitation |
| 7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| 8 | * and/or sell copies of the Software, and to permit persons to whom the |
| 9 | * Software is furnished to do so, subject to the following conditions: |
| 10 | * |
| 11 | * The above copyright notice and this permission notice (including the next |
| 12 | * paragraph) shall be included in all copies or substantial portions of the |
| 13 | * Software. |
| 14 | * |
| 15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
| 19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
| 20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS |
| 21 | * IN THE SOFTWARE. |
| 22 | * |
| 23 | * Authors: |
| 24 | * Eric Anholt <eric@anholt.net> |
| 25 | * |
| 26 | */ |
| 27 | |
| 28 | #include "drmP.h" |
| 29 | #include "drm.h" |
| 30 | #include "i915_drm.h" |
| 31 | #include "i915_drv.h" |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 32 | #include "i915_trace.h" |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 33 | #include "intel_drv.h" |
Tejun Heo | 5a0e3ad | 2010-03-24 17:04:11 +0900 | [diff] [blame] | 34 | #include <linux/slab.h> |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 35 | #include <linux/swap.h> |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 36 | #include <linux/pci.h> |
Zhenyu Wang | f8f235e | 2010-08-27 11:08:57 +0800 | [diff] [blame] | 37 | #include <linux/intel-gtt.h> |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 38 | |
Daniel Vetter | 0108a3e | 2010-08-07 11:01:21 +0100 | [diff] [blame] | 39 | static uint32_t i915_gem_get_gtt_alignment(struct drm_gem_object *obj); |
Chris Wilson | 2dafb1e | 2010-06-07 14:03:05 +0100 | [diff] [blame] | 40 | static int i915_gem_object_flush_gpu_write_domain(struct drm_gem_object *obj); |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 41 | static void i915_gem_object_flush_gtt_write_domain(struct drm_gem_object *obj); |
| 42 | static void i915_gem_object_flush_cpu_write_domain(struct drm_gem_object *obj); |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 43 | static int i915_gem_object_set_to_cpu_domain(struct drm_gem_object *obj, |
| 44 | int write); |
| 45 | static int i915_gem_object_set_cpu_read_domain_range(struct drm_gem_object *obj, |
| 46 | uint64_t offset, |
| 47 | uint64_t size); |
| 48 | static void i915_gem_object_set_to_full_cpu_read_domain(struct drm_gem_object *obj); |
Daniel Vetter | e35a41d | 2010-02-11 22:13:59 +0100 | [diff] [blame^] | 49 | static int i915_gem_object_wait_rendering(struct drm_gem_object *obj, |
| 50 | bool interruptible); |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 51 | static int i915_gem_object_bind_to_gtt(struct drm_gem_object *obj, |
| 52 | unsigned alignment); |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 53 | static void i915_gem_clear_fence_reg(struct drm_gem_object *obj); |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 54 | static int i915_gem_phys_pwrite(struct drm_device *dev, struct drm_gem_object *obj, |
| 55 | struct drm_i915_gem_pwrite *args, |
| 56 | struct drm_file *file_priv); |
Chris Wilson | be72615 | 2010-07-23 23:18:50 +0100 | [diff] [blame] | 57 | static void i915_gem_free_object_tail(struct drm_gem_object *obj); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 58 | |
Chris Wilson | 3116971 | 2009-09-14 16:50:28 +0100 | [diff] [blame] | 59 | static LIST_HEAD(shrink_list); |
| 60 | static DEFINE_SPINLOCK(shrink_list_lock); |
| 61 | |
Chris Wilson | 7d1c480 | 2010-08-07 21:45:03 +0100 | [diff] [blame] | 62 | static inline bool |
| 63 | i915_gem_object_is_inactive(struct drm_i915_gem_object *obj_priv) |
| 64 | { |
| 65 | return obj_priv->gtt_space && |
| 66 | !obj_priv->active && |
| 67 | obj_priv->pin_count == 0; |
| 68 | } |
| 69 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 70 | int i915_gem_do_init(struct drm_device *dev, unsigned long start, |
| 71 | unsigned long end) |
| 72 | { |
| 73 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 74 | |
| 75 | if (start >= end || |
| 76 | (start & (PAGE_SIZE - 1)) != 0 || |
| 77 | (end & (PAGE_SIZE - 1)) != 0) { |
| 78 | return -EINVAL; |
| 79 | } |
| 80 | |
| 81 | drm_mm_init(&dev_priv->mm.gtt_space, start, |
| 82 | end - start); |
| 83 | |
| 84 | dev->gtt_total = (uint32_t) (end - start); |
| 85 | |
| 86 | return 0; |
| 87 | } |
Keith Packard | 6dbe277 | 2008-10-14 21:41:13 -0700 | [diff] [blame] | 88 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 89 | int |
| 90 | i915_gem_init_ioctl(struct drm_device *dev, void *data, |
| 91 | struct drm_file *file_priv) |
| 92 | { |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 93 | struct drm_i915_gem_init *args = data; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 94 | int ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 95 | |
| 96 | mutex_lock(&dev->struct_mutex); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 97 | ret = i915_gem_do_init(dev, args->gtt_start, args->gtt_end); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 98 | mutex_unlock(&dev->struct_mutex); |
| 99 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 100 | return ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 101 | } |
| 102 | |
Eric Anholt | 5a125c3 | 2008-10-22 21:40:13 -0700 | [diff] [blame] | 103 | int |
| 104 | i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data, |
| 105 | struct drm_file *file_priv) |
| 106 | { |
Eric Anholt | 5a125c3 | 2008-10-22 21:40:13 -0700 | [diff] [blame] | 107 | struct drm_i915_gem_get_aperture *args = data; |
Eric Anholt | 5a125c3 | 2008-10-22 21:40:13 -0700 | [diff] [blame] | 108 | |
| 109 | if (!(dev->driver->driver_features & DRIVER_GEM)) |
| 110 | return -ENODEV; |
| 111 | |
| 112 | args->aper_size = dev->gtt_total; |
Keith Packard | 2678d9d | 2008-11-20 22:54:54 -0800 | [diff] [blame] | 113 | args->aper_available_size = (args->aper_size - |
| 114 | atomic_read(&dev->pin_memory)); |
Eric Anholt | 5a125c3 | 2008-10-22 21:40:13 -0700 | [diff] [blame] | 115 | |
| 116 | return 0; |
| 117 | } |
| 118 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 119 | |
| 120 | /** |
| 121 | * Creates a new mm object and returns a handle to it. |
| 122 | */ |
| 123 | int |
| 124 | i915_gem_create_ioctl(struct drm_device *dev, void *data, |
| 125 | struct drm_file *file_priv) |
| 126 | { |
| 127 | struct drm_i915_gem_create *args = data; |
| 128 | struct drm_gem_object *obj; |
Pekka Paalanen | a1a2d1d | 2009-08-23 12:40:55 +0300 | [diff] [blame] | 129 | int ret; |
| 130 | u32 handle; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 131 | |
| 132 | args->size = roundup(args->size, PAGE_SIZE); |
| 133 | |
| 134 | /* Allocate the new object */ |
Daniel Vetter | ac52bc5 | 2010-04-09 19:05:06 +0000 | [diff] [blame] | 135 | obj = i915_gem_alloc_object(dev, args->size); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 136 | if (obj == NULL) |
| 137 | return -ENOMEM; |
| 138 | |
| 139 | ret = drm_gem_handle_create(file_priv, obj, &handle); |
Chris Wilson | 1dfd975 | 2010-09-06 14:44:14 +0100 | [diff] [blame] | 140 | if (ret) { |
| 141 | drm_gem_object_unreference_unlocked(obj); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 142 | return ret; |
Chris Wilson | 1dfd975 | 2010-09-06 14:44:14 +0100 | [diff] [blame] | 143 | } |
| 144 | |
| 145 | /* Sink the floating reference from kref_init(handlecount) */ |
| 146 | drm_gem_object_handle_unreference_unlocked(obj); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 147 | |
| 148 | args->handle = handle; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 149 | return 0; |
| 150 | } |
| 151 | |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 152 | static inline int |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 153 | fast_shmem_read(struct page **pages, |
| 154 | loff_t page_base, int page_offset, |
| 155 | char __user *data, |
| 156 | int length) |
| 157 | { |
| 158 | char __iomem *vaddr; |
Florian Mickler | 2bc43b5 | 2009-04-06 22:55:41 +0200 | [diff] [blame] | 159 | int unwritten; |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 160 | |
| 161 | vaddr = kmap_atomic(pages[page_base >> PAGE_SHIFT], KM_USER0); |
| 162 | if (vaddr == NULL) |
| 163 | return -ENOMEM; |
Florian Mickler | 2bc43b5 | 2009-04-06 22:55:41 +0200 | [diff] [blame] | 164 | unwritten = __copy_to_user_inatomic(data, vaddr + page_offset, length); |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 165 | kunmap_atomic(vaddr, KM_USER0); |
| 166 | |
Florian Mickler | 2bc43b5 | 2009-04-06 22:55:41 +0200 | [diff] [blame] | 167 | if (unwritten) |
| 168 | return -EFAULT; |
| 169 | |
| 170 | return 0; |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 171 | } |
| 172 | |
Eric Anholt | 280b713 | 2009-03-12 16:56:27 -0700 | [diff] [blame] | 173 | static int i915_gem_object_needs_bit17_swizzle(struct drm_gem_object *obj) |
| 174 | { |
| 175 | drm_i915_private_t *dev_priv = obj->dev->dev_private; |
Daniel Vetter | 23010e4 | 2010-03-08 13:35:02 +0100 | [diff] [blame] | 176 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
Eric Anholt | 280b713 | 2009-03-12 16:56:27 -0700 | [diff] [blame] | 177 | |
| 178 | return dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 && |
| 179 | obj_priv->tiling_mode != I915_TILING_NONE; |
| 180 | } |
| 181 | |
Chris Wilson | 99a03df | 2010-05-27 14:15:34 +0100 | [diff] [blame] | 182 | static inline void |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 183 | slow_shmem_copy(struct page *dst_page, |
| 184 | int dst_offset, |
| 185 | struct page *src_page, |
| 186 | int src_offset, |
| 187 | int length) |
| 188 | { |
| 189 | char *dst_vaddr, *src_vaddr; |
| 190 | |
Chris Wilson | 99a03df | 2010-05-27 14:15:34 +0100 | [diff] [blame] | 191 | dst_vaddr = kmap(dst_page); |
| 192 | src_vaddr = kmap(src_page); |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 193 | |
| 194 | memcpy(dst_vaddr + dst_offset, src_vaddr + src_offset, length); |
| 195 | |
Chris Wilson | 99a03df | 2010-05-27 14:15:34 +0100 | [diff] [blame] | 196 | kunmap(src_page); |
| 197 | kunmap(dst_page); |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 198 | } |
| 199 | |
Chris Wilson | 99a03df | 2010-05-27 14:15:34 +0100 | [diff] [blame] | 200 | static inline void |
Eric Anholt | 280b713 | 2009-03-12 16:56:27 -0700 | [diff] [blame] | 201 | slow_shmem_bit17_copy(struct page *gpu_page, |
| 202 | int gpu_offset, |
| 203 | struct page *cpu_page, |
| 204 | int cpu_offset, |
| 205 | int length, |
| 206 | int is_read) |
| 207 | { |
| 208 | char *gpu_vaddr, *cpu_vaddr; |
| 209 | |
| 210 | /* Use the unswizzled path if this page isn't affected. */ |
| 211 | if ((page_to_phys(gpu_page) & (1 << 17)) == 0) { |
| 212 | if (is_read) |
| 213 | return slow_shmem_copy(cpu_page, cpu_offset, |
| 214 | gpu_page, gpu_offset, length); |
| 215 | else |
| 216 | return slow_shmem_copy(gpu_page, gpu_offset, |
| 217 | cpu_page, cpu_offset, length); |
| 218 | } |
| 219 | |
Chris Wilson | 99a03df | 2010-05-27 14:15:34 +0100 | [diff] [blame] | 220 | gpu_vaddr = kmap(gpu_page); |
| 221 | cpu_vaddr = kmap(cpu_page); |
Eric Anholt | 280b713 | 2009-03-12 16:56:27 -0700 | [diff] [blame] | 222 | |
| 223 | /* Copy the data, XORing A6 with A17 (1). The user already knows he's |
| 224 | * XORing with the other bits (A9 for Y, A9 and A10 for X) |
| 225 | */ |
| 226 | while (length > 0) { |
| 227 | int cacheline_end = ALIGN(gpu_offset + 1, 64); |
| 228 | int this_length = min(cacheline_end - gpu_offset, length); |
| 229 | int swizzled_gpu_offset = gpu_offset ^ 64; |
| 230 | |
| 231 | if (is_read) { |
| 232 | memcpy(cpu_vaddr + cpu_offset, |
| 233 | gpu_vaddr + swizzled_gpu_offset, |
| 234 | this_length); |
| 235 | } else { |
| 236 | memcpy(gpu_vaddr + swizzled_gpu_offset, |
| 237 | cpu_vaddr + cpu_offset, |
| 238 | this_length); |
| 239 | } |
| 240 | cpu_offset += this_length; |
| 241 | gpu_offset += this_length; |
| 242 | length -= this_length; |
| 243 | } |
| 244 | |
Chris Wilson | 99a03df | 2010-05-27 14:15:34 +0100 | [diff] [blame] | 245 | kunmap(cpu_page); |
| 246 | kunmap(gpu_page); |
Eric Anholt | 280b713 | 2009-03-12 16:56:27 -0700 | [diff] [blame] | 247 | } |
| 248 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 249 | /** |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 250 | * This is the fast shmem pread path, which attempts to copy_from_user directly |
| 251 | * from the backing pages of the object to the user's address space. On a |
| 252 | * fault, it fails so we can fall back to i915_gem_shmem_pwrite_slow(). |
| 253 | */ |
| 254 | static int |
| 255 | i915_gem_shmem_pread_fast(struct drm_device *dev, struct drm_gem_object *obj, |
| 256 | struct drm_i915_gem_pread *args, |
| 257 | struct drm_file *file_priv) |
| 258 | { |
Daniel Vetter | 23010e4 | 2010-03-08 13:35:02 +0100 | [diff] [blame] | 259 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 260 | ssize_t remain; |
| 261 | loff_t offset, page_base; |
| 262 | char __user *user_data; |
| 263 | int page_offset, page_length; |
| 264 | int ret; |
| 265 | |
| 266 | user_data = (char __user *) (uintptr_t) args->data_ptr; |
| 267 | remain = args->size; |
| 268 | |
| 269 | mutex_lock(&dev->struct_mutex); |
| 270 | |
Chris Wilson | 4bdadb9 | 2010-01-27 13:36:32 +0000 | [diff] [blame] | 271 | ret = i915_gem_object_get_pages(obj, 0); |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 272 | if (ret != 0) |
| 273 | goto fail_unlock; |
| 274 | |
| 275 | ret = i915_gem_object_set_cpu_read_domain_range(obj, args->offset, |
| 276 | args->size); |
| 277 | if (ret != 0) |
| 278 | goto fail_put_pages; |
| 279 | |
Daniel Vetter | 23010e4 | 2010-03-08 13:35:02 +0100 | [diff] [blame] | 280 | obj_priv = to_intel_bo(obj); |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 281 | offset = args->offset; |
| 282 | |
| 283 | while (remain > 0) { |
| 284 | /* Operation in this page |
| 285 | * |
| 286 | * page_base = page offset within aperture |
| 287 | * page_offset = offset within page |
| 288 | * page_length = bytes to copy for this page |
| 289 | */ |
| 290 | page_base = (offset & ~(PAGE_SIZE-1)); |
| 291 | page_offset = offset & (PAGE_SIZE-1); |
| 292 | page_length = remain; |
| 293 | if ((page_offset + remain) > PAGE_SIZE) |
| 294 | page_length = PAGE_SIZE - page_offset; |
| 295 | |
| 296 | ret = fast_shmem_read(obj_priv->pages, |
| 297 | page_base, page_offset, |
| 298 | user_data, page_length); |
| 299 | if (ret) |
| 300 | goto fail_put_pages; |
| 301 | |
| 302 | remain -= page_length; |
| 303 | user_data += page_length; |
| 304 | offset += page_length; |
| 305 | } |
| 306 | |
| 307 | fail_put_pages: |
| 308 | i915_gem_object_put_pages(obj); |
| 309 | fail_unlock: |
| 310 | mutex_unlock(&dev->struct_mutex); |
| 311 | |
| 312 | return ret; |
| 313 | } |
| 314 | |
Chris Wilson | 07f73f6 | 2009-09-14 16:50:30 +0100 | [diff] [blame] | 315 | static int |
| 316 | i915_gem_object_get_pages_or_evict(struct drm_gem_object *obj) |
| 317 | { |
| 318 | int ret; |
| 319 | |
Chris Wilson | 4bdadb9 | 2010-01-27 13:36:32 +0000 | [diff] [blame] | 320 | ret = i915_gem_object_get_pages(obj, __GFP_NORETRY | __GFP_NOWARN); |
Chris Wilson | 07f73f6 | 2009-09-14 16:50:30 +0100 | [diff] [blame] | 321 | |
| 322 | /* If we've insufficient memory to map in the pages, attempt |
| 323 | * to make some space by throwing out some old buffers. |
| 324 | */ |
| 325 | if (ret == -ENOMEM) { |
| 326 | struct drm_device *dev = obj->dev; |
Chris Wilson | 07f73f6 | 2009-09-14 16:50:30 +0100 | [diff] [blame] | 327 | |
Daniel Vetter | 0108a3e | 2010-08-07 11:01:21 +0100 | [diff] [blame] | 328 | ret = i915_gem_evict_something(dev, obj->size, |
| 329 | i915_gem_get_gtt_alignment(obj)); |
Chris Wilson | 07f73f6 | 2009-09-14 16:50:30 +0100 | [diff] [blame] | 330 | if (ret) |
| 331 | return ret; |
| 332 | |
Chris Wilson | 4bdadb9 | 2010-01-27 13:36:32 +0000 | [diff] [blame] | 333 | ret = i915_gem_object_get_pages(obj, 0); |
Chris Wilson | 07f73f6 | 2009-09-14 16:50:30 +0100 | [diff] [blame] | 334 | } |
| 335 | |
| 336 | return ret; |
| 337 | } |
| 338 | |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 339 | /** |
| 340 | * This is the fallback shmem pread path, which allocates temporary storage |
| 341 | * in kernel space to copy_to_user into outside of the struct_mutex, so we |
| 342 | * can copy out of the object's backing pages while holding the struct mutex |
| 343 | * and not take page faults. |
| 344 | */ |
| 345 | static int |
| 346 | i915_gem_shmem_pread_slow(struct drm_device *dev, struct drm_gem_object *obj, |
| 347 | struct drm_i915_gem_pread *args, |
| 348 | struct drm_file *file_priv) |
| 349 | { |
Daniel Vetter | 23010e4 | 2010-03-08 13:35:02 +0100 | [diff] [blame] | 350 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 351 | struct mm_struct *mm = current->mm; |
| 352 | struct page **user_pages; |
| 353 | ssize_t remain; |
| 354 | loff_t offset, pinned_pages, i; |
| 355 | loff_t first_data_page, last_data_page, num_pages; |
| 356 | int shmem_page_index, shmem_page_offset; |
| 357 | int data_page_index, data_page_offset; |
| 358 | int page_length; |
| 359 | int ret; |
| 360 | uint64_t data_ptr = args->data_ptr; |
Eric Anholt | 280b713 | 2009-03-12 16:56:27 -0700 | [diff] [blame] | 361 | int do_bit17_swizzling; |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 362 | |
| 363 | remain = args->size; |
| 364 | |
| 365 | /* Pin the user pages containing the data. We can't fault while |
| 366 | * holding the struct mutex, yet we want to hold it while |
| 367 | * dereferencing the user data. |
| 368 | */ |
| 369 | first_data_page = data_ptr / PAGE_SIZE; |
| 370 | last_data_page = (data_ptr + args->size - 1) / PAGE_SIZE; |
| 371 | num_pages = last_data_page - first_data_page + 1; |
| 372 | |
Jesse Barnes | 8e7d2b2 | 2009-05-08 16:13:25 -0700 | [diff] [blame] | 373 | user_pages = drm_calloc_large(num_pages, sizeof(struct page *)); |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 374 | if (user_pages == NULL) |
| 375 | return -ENOMEM; |
| 376 | |
| 377 | down_read(&mm->mmap_sem); |
| 378 | pinned_pages = get_user_pages(current, mm, (uintptr_t)args->data_ptr, |
Eric Anholt | e5e9ecd | 2009-04-07 16:01:22 -0700 | [diff] [blame] | 379 | num_pages, 1, 0, user_pages, NULL); |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 380 | up_read(&mm->mmap_sem); |
| 381 | if (pinned_pages < num_pages) { |
| 382 | ret = -EFAULT; |
| 383 | goto fail_put_user_pages; |
| 384 | } |
| 385 | |
Eric Anholt | 280b713 | 2009-03-12 16:56:27 -0700 | [diff] [blame] | 386 | do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj); |
| 387 | |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 388 | mutex_lock(&dev->struct_mutex); |
| 389 | |
Chris Wilson | 07f73f6 | 2009-09-14 16:50:30 +0100 | [diff] [blame] | 390 | ret = i915_gem_object_get_pages_or_evict(obj); |
| 391 | if (ret) |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 392 | goto fail_unlock; |
| 393 | |
| 394 | ret = i915_gem_object_set_cpu_read_domain_range(obj, args->offset, |
| 395 | args->size); |
| 396 | if (ret != 0) |
| 397 | goto fail_put_pages; |
| 398 | |
Daniel Vetter | 23010e4 | 2010-03-08 13:35:02 +0100 | [diff] [blame] | 399 | obj_priv = to_intel_bo(obj); |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 400 | offset = args->offset; |
| 401 | |
| 402 | while (remain > 0) { |
| 403 | /* Operation in this page |
| 404 | * |
| 405 | * shmem_page_index = page number within shmem file |
| 406 | * shmem_page_offset = offset within page in shmem file |
| 407 | * data_page_index = page number in get_user_pages return |
| 408 | * data_page_offset = offset with data_page_index page. |
| 409 | * page_length = bytes to copy for this page |
| 410 | */ |
| 411 | shmem_page_index = offset / PAGE_SIZE; |
| 412 | shmem_page_offset = offset & ~PAGE_MASK; |
| 413 | data_page_index = data_ptr / PAGE_SIZE - first_data_page; |
| 414 | data_page_offset = data_ptr & ~PAGE_MASK; |
| 415 | |
| 416 | page_length = remain; |
| 417 | if ((shmem_page_offset + page_length) > PAGE_SIZE) |
| 418 | page_length = PAGE_SIZE - shmem_page_offset; |
| 419 | if ((data_page_offset + page_length) > PAGE_SIZE) |
| 420 | page_length = PAGE_SIZE - data_page_offset; |
| 421 | |
Eric Anholt | 280b713 | 2009-03-12 16:56:27 -0700 | [diff] [blame] | 422 | if (do_bit17_swizzling) { |
Chris Wilson | 99a03df | 2010-05-27 14:15:34 +0100 | [diff] [blame] | 423 | slow_shmem_bit17_copy(obj_priv->pages[shmem_page_index], |
Eric Anholt | 280b713 | 2009-03-12 16:56:27 -0700 | [diff] [blame] | 424 | shmem_page_offset, |
Chris Wilson | 99a03df | 2010-05-27 14:15:34 +0100 | [diff] [blame] | 425 | user_pages[data_page_index], |
| 426 | data_page_offset, |
| 427 | page_length, |
| 428 | 1); |
| 429 | } else { |
| 430 | slow_shmem_copy(user_pages[data_page_index], |
| 431 | data_page_offset, |
| 432 | obj_priv->pages[shmem_page_index], |
| 433 | shmem_page_offset, |
| 434 | page_length); |
Eric Anholt | 280b713 | 2009-03-12 16:56:27 -0700 | [diff] [blame] | 435 | } |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 436 | |
| 437 | remain -= page_length; |
| 438 | data_ptr += page_length; |
| 439 | offset += page_length; |
| 440 | } |
| 441 | |
| 442 | fail_put_pages: |
| 443 | i915_gem_object_put_pages(obj); |
| 444 | fail_unlock: |
| 445 | mutex_unlock(&dev->struct_mutex); |
| 446 | fail_put_user_pages: |
| 447 | for (i = 0; i < pinned_pages; i++) { |
| 448 | SetPageDirty(user_pages[i]); |
| 449 | page_cache_release(user_pages[i]); |
| 450 | } |
Jesse Barnes | 8e7d2b2 | 2009-05-08 16:13:25 -0700 | [diff] [blame] | 451 | drm_free_large(user_pages); |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 452 | |
| 453 | return ret; |
| 454 | } |
| 455 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 456 | /** |
| 457 | * Reads data from the object referenced by handle. |
| 458 | * |
| 459 | * On error, the contents of *data are undefined. |
| 460 | */ |
| 461 | int |
| 462 | i915_gem_pread_ioctl(struct drm_device *dev, void *data, |
| 463 | struct drm_file *file_priv) |
| 464 | { |
| 465 | struct drm_i915_gem_pread *args = data; |
| 466 | struct drm_gem_object *obj; |
| 467 | struct drm_i915_gem_object *obj_priv; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 468 | int ret; |
| 469 | |
| 470 | obj = drm_gem_object_lookup(dev, file_priv, args->handle); |
| 471 | if (obj == NULL) |
Chris Wilson | bf79cb9 | 2010-08-04 14:19:46 +0100 | [diff] [blame] | 472 | return -ENOENT; |
Daniel Vetter | 23010e4 | 2010-03-08 13:35:02 +0100 | [diff] [blame] | 473 | obj_priv = to_intel_bo(obj); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 474 | |
| 475 | /* Bounds check source. |
| 476 | * |
| 477 | * XXX: This could use review for overflow issues... |
| 478 | */ |
| 479 | if (args->offset > obj->size || args->size > obj->size || |
| 480 | args->offset + args->size > obj->size) { |
Luca Barbieri | bc9025b | 2010-02-09 05:49:12 +0000 | [diff] [blame] | 481 | drm_gem_object_unreference_unlocked(obj); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 482 | return -EINVAL; |
| 483 | } |
| 484 | |
Eric Anholt | 280b713 | 2009-03-12 16:56:27 -0700 | [diff] [blame] | 485 | if (i915_gem_object_needs_bit17_swizzle(obj)) { |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 486 | ret = i915_gem_shmem_pread_slow(dev, obj, args, file_priv); |
Eric Anholt | 280b713 | 2009-03-12 16:56:27 -0700 | [diff] [blame] | 487 | } else { |
| 488 | ret = i915_gem_shmem_pread_fast(dev, obj, args, file_priv); |
| 489 | if (ret != 0) |
| 490 | ret = i915_gem_shmem_pread_slow(dev, obj, args, |
| 491 | file_priv); |
| 492 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 493 | |
Luca Barbieri | bc9025b | 2010-02-09 05:49:12 +0000 | [diff] [blame] | 494 | drm_gem_object_unreference_unlocked(obj); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 495 | |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 496 | return ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 497 | } |
| 498 | |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 499 | /* This is the fast write path which cannot handle |
| 500 | * page faults in the source data |
Linus Torvalds | 9b7530cc | 2008-10-20 14:16:43 -0700 | [diff] [blame] | 501 | */ |
Linus Torvalds | 9b7530cc | 2008-10-20 14:16:43 -0700 | [diff] [blame] | 502 | |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 503 | static inline int |
| 504 | fast_user_write(struct io_mapping *mapping, |
| 505 | loff_t page_base, int page_offset, |
| 506 | char __user *user_data, |
| 507 | int length) |
| 508 | { |
| 509 | char *vaddr_atomic; |
| 510 | unsigned long unwritten; |
| 511 | |
Chris Wilson | fca3ec0 | 2010-08-04 14:34:24 +0100 | [diff] [blame] | 512 | vaddr_atomic = io_mapping_map_atomic_wc(mapping, page_base, KM_USER0); |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 513 | unwritten = __copy_from_user_inatomic_nocache(vaddr_atomic + page_offset, |
| 514 | user_data, length); |
Chris Wilson | fca3ec0 | 2010-08-04 14:34:24 +0100 | [diff] [blame] | 515 | io_mapping_unmap_atomic(vaddr_atomic, KM_USER0); |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 516 | if (unwritten) |
| 517 | return -EFAULT; |
Linus Torvalds | 9b7530cc | 2008-10-20 14:16:43 -0700 | [diff] [blame] | 518 | return 0; |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 519 | } |
| 520 | |
| 521 | /* Here's the write path which can sleep for |
| 522 | * page faults |
| 523 | */ |
| 524 | |
Chris Wilson | ab34c22 | 2010-05-27 14:15:35 +0100 | [diff] [blame] | 525 | static inline void |
Eric Anholt | 3de09aa | 2009-03-09 09:42:23 -0700 | [diff] [blame] | 526 | slow_kernel_write(struct io_mapping *mapping, |
| 527 | loff_t gtt_base, int gtt_offset, |
| 528 | struct page *user_page, int user_offset, |
| 529 | int length) |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 530 | { |
Chris Wilson | ab34c22 | 2010-05-27 14:15:35 +0100 | [diff] [blame] | 531 | char __iomem *dst_vaddr; |
| 532 | char *src_vaddr; |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 533 | |
Chris Wilson | ab34c22 | 2010-05-27 14:15:35 +0100 | [diff] [blame] | 534 | dst_vaddr = io_mapping_map_wc(mapping, gtt_base); |
| 535 | src_vaddr = kmap(user_page); |
| 536 | |
| 537 | memcpy_toio(dst_vaddr + gtt_offset, |
| 538 | src_vaddr + user_offset, |
| 539 | length); |
| 540 | |
| 541 | kunmap(user_page); |
| 542 | io_mapping_unmap(dst_vaddr); |
Linus Torvalds | 9b7530cc | 2008-10-20 14:16:43 -0700 | [diff] [blame] | 543 | } |
| 544 | |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 545 | static inline int |
| 546 | fast_shmem_write(struct page **pages, |
| 547 | loff_t page_base, int page_offset, |
| 548 | char __user *data, |
| 549 | int length) |
| 550 | { |
| 551 | char __iomem *vaddr; |
Dave Airlie | d008877 | 2009-03-28 20:29:48 -0400 | [diff] [blame] | 552 | unsigned long unwritten; |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 553 | |
| 554 | vaddr = kmap_atomic(pages[page_base >> PAGE_SHIFT], KM_USER0); |
| 555 | if (vaddr == NULL) |
| 556 | return -ENOMEM; |
Dave Airlie | d008877 | 2009-03-28 20:29:48 -0400 | [diff] [blame] | 557 | unwritten = __copy_from_user_inatomic(vaddr + page_offset, data, length); |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 558 | kunmap_atomic(vaddr, KM_USER0); |
| 559 | |
Dave Airlie | d008877 | 2009-03-28 20:29:48 -0400 | [diff] [blame] | 560 | if (unwritten) |
| 561 | return -EFAULT; |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 562 | return 0; |
| 563 | } |
| 564 | |
Eric Anholt | 3de09aa | 2009-03-09 09:42:23 -0700 | [diff] [blame] | 565 | /** |
| 566 | * This is the fast pwrite path, where we copy the data directly from the |
| 567 | * user into the GTT, uncached. |
| 568 | */ |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 569 | static int |
Eric Anholt | 3de09aa | 2009-03-09 09:42:23 -0700 | [diff] [blame] | 570 | i915_gem_gtt_pwrite_fast(struct drm_device *dev, struct drm_gem_object *obj, |
| 571 | struct drm_i915_gem_pwrite *args, |
| 572 | struct drm_file *file_priv) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 573 | { |
Daniel Vetter | 23010e4 | 2010-03-08 13:35:02 +0100 | [diff] [blame] | 574 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 575 | drm_i915_private_t *dev_priv = dev->dev_private; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 576 | ssize_t remain; |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 577 | loff_t offset, page_base; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 578 | char __user *user_data; |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 579 | int page_offset, page_length; |
| 580 | int ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 581 | |
| 582 | user_data = (char __user *) (uintptr_t) args->data_ptr; |
| 583 | remain = args->size; |
| 584 | if (!access_ok(VERIFY_READ, user_data, remain)) |
| 585 | return -EFAULT; |
| 586 | |
| 587 | |
| 588 | mutex_lock(&dev->struct_mutex); |
| 589 | ret = i915_gem_object_pin(obj, 0); |
| 590 | if (ret) { |
| 591 | mutex_unlock(&dev->struct_mutex); |
| 592 | return ret; |
| 593 | } |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 594 | ret = i915_gem_object_set_to_gtt_domain(obj, 1); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 595 | if (ret) |
| 596 | goto fail; |
| 597 | |
Daniel Vetter | 23010e4 | 2010-03-08 13:35:02 +0100 | [diff] [blame] | 598 | obj_priv = to_intel_bo(obj); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 599 | offset = obj_priv->gtt_offset + args->offset; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 600 | |
| 601 | while (remain > 0) { |
| 602 | /* Operation in this page |
| 603 | * |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 604 | * page_base = page offset within aperture |
| 605 | * page_offset = offset within page |
| 606 | * page_length = bytes to copy for this page |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 607 | */ |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 608 | page_base = (offset & ~(PAGE_SIZE-1)); |
| 609 | page_offset = offset & (PAGE_SIZE-1); |
| 610 | page_length = remain; |
| 611 | if ((page_offset + remain) > PAGE_SIZE) |
| 612 | page_length = PAGE_SIZE - page_offset; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 613 | |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 614 | ret = fast_user_write (dev_priv->mm.gtt_mapping, page_base, |
| 615 | page_offset, user_data, page_length); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 616 | |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 617 | /* If we get a fault while copying data, then (presumably) our |
Eric Anholt | 3de09aa | 2009-03-09 09:42:23 -0700 | [diff] [blame] | 618 | * source page isn't available. Return the error and we'll |
| 619 | * retry in the slow path. |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 620 | */ |
Eric Anholt | 3de09aa | 2009-03-09 09:42:23 -0700 | [diff] [blame] | 621 | if (ret) |
| 622 | goto fail; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 623 | |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 624 | remain -= page_length; |
| 625 | user_data += page_length; |
| 626 | offset += page_length; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 627 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 628 | |
| 629 | fail: |
| 630 | i915_gem_object_unpin(obj); |
| 631 | mutex_unlock(&dev->struct_mutex); |
| 632 | |
| 633 | return ret; |
| 634 | } |
| 635 | |
Eric Anholt | 3de09aa | 2009-03-09 09:42:23 -0700 | [diff] [blame] | 636 | /** |
| 637 | * This is the fallback GTT pwrite path, which uses get_user_pages to pin |
| 638 | * the memory and maps it using kmap_atomic for copying. |
| 639 | * |
| 640 | * This code resulted in x11perf -rgb10text consuming about 10% more CPU |
| 641 | * than using i915_gem_gtt_pwrite_fast on a G45 (32-bit). |
| 642 | */ |
Eric Anholt | 3043c60 | 2008-10-02 12:24:47 -0700 | [diff] [blame] | 643 | static int |
Eric Anholt | 3de09aa | 2009-03-09 09:42:23 -0700 | [diff] [blame] | 644 | i915_gem_gtt_pwrite_slow(struct drm_device *dev, struct drm_gem_object *obj, |
| 645 | struct drm_i915_gem_pwrite *args, |
| 646 | struct drm_file *file_priv) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 647 | { |
Daniel Vetter | 23010e4 | 2010-03-08 13:35:02 +0100 | [diff] [blame] | 648 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
Eric Anholt | 3de09aa | 2009-03-09 09:42:23 -0700 | [diff] [blame] | 649 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 650 | ssize_t remain; |
| 651 | loff_t gtt_page_base, offset; |
| 652 | loff_t first_data_page, last_data_page, num_pages; |
| 653 | loff_t pinned_pages, i; |
| 654 | struct page **user_pages; |
| 655 | struct mm_struct *mm = current->mm; |
| 656 | int gtt_page_offset, data_page_offset, data_page_index, page_length; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 657 | int ret; |
Eric Anholt | 3de09aa | 2009-03-09 09:42:23 -0700 | [diff] [blame] | 658 | uint64_t data_ptr = args->data_ptr; |
| 659 | |
| 660 | remain = args->size; |
| 661 | |
| 662 | /* Pin the user pages containing the data. We can't fault while |
| 663 | * holding the struct mutex, and all of the pwrite implementations |
| 664 | * want to hold it while dereferencing the user data. |
| 665 | */ |
| 666 | first_data_page = data_ptr / PAGE_SIZE; |
| 667 | last_data_page = (data_ptr + args->size - 1) / PAGE_SIZE; |
| 668 | num_pages = last_data_page - first_data_page + 1; |
| 669 | |
Jesse Barnes | 8e7d2b2 | 2009-05-08 16:13:25 -0700 | [diff] [blame] | 670 | user_pages = drm_calloc_large(num_pages, sizeof(struct page *)); |
Eric Anholt | 3de09aa | 2009-03-09 09:42:23 -0700 | [diff] [blame] | 671 | if (user_pages == NULL) |
| 672 | return -ENOMEM; |
| 673 | |
| 674 | down_read(&mm->mmap_sem); |
| 675 | pinned_pages = get_user_pages(current, mm, (uintptr_t)args->data_ptr, |
| 676 | num_pages, 0, 0, user_pages, NULL); |
| 677 | up_read(&mm->mmap_sem); |
| 678 | if (pinned_pages < num_pages) { |
| 679 | ret = -EFAULT; |
| 680 | goto out_unpin_pages; |
| 681 | } |
| 682 | |
| 683 | mutex_lock(&dev->struct_mutex); |
| 684 | ret = i915_gem_object_pin(obj, 0); |
| 685 | if (ret) |
| 686 | goto out_unlock; |
| 687 | |
| 688 | ret = i915_gem_object_set_to_gtt_domain(obj, 1); |
| 689 | if (ret) |
| 690 | goto out_unpin_object; |
| 691 | |
Daniel Vetter | 23010e4 | 2010-03-08 13:35:02 +0100 | [diff] [blame] | 692 | obj_priv = to_intel_bo(obj); |
Eric Anholt | 3de09aa | 2009-03-09 09:42:23 -0700 | [diff] [blame] | 693 | offset = obj_priv->gtt_offset + args->offset; |
| 694 | |
| 695 | while (remain > 0) { |
| 696 | /* Operation in this page |
| 697 | * |
| 698 | * gtt_page_base = page offset within aperture |
| 699 | * gtt_page_offset = offset within page in aperture |
| 700 | * data_page_index = page number in get_user_pages return |
| 701 | * data_page_offset = offset with data_page_index page. |
| 702 | * page_length = bytes to copy for this page |
| 703 | */ |
| 704 | gtt_page_base = offset & PAGE_MASK; |
| 705 | gtt_page_offset = offset & ~PAGE_MASK; |
| 706 | data_page_index = data_ptr / PAGE_SIZE - first_data_page; |
| 707 | data_page_offset = data_ptr & ~PAGE_MASK; |
| 708 | |
| 709 | page_length = remain; |
| 710 | if ((gtt_page_offset + page_length) > PAGE_SIZE) |
| 711 | page_length = PAGE_SIZE - gtt_page_offset; |
| 712 | if ((data_page_offset + page_length) > PAGE_SIZE) |
| 713 | page_length = PAGE_SIZE - data_page_offset; |
| 714 | |
Chris Wilson | ab34c22 | 2010-05-27 14:15:35 +0100 | [diff] [blame] | 715 | slow_kernel_write(dev_priv->mm.gtt_mapping, |
| 716 | gtt_page_base, gtt_page_offset, |
| 717 | user_pages[data_page_index], |
| 718 | data_page_offset, |
| 719 | page_length); |
Eric Anholt | 3de09aa | 2009-03-09 09:42:23 -0700 | [diff] [blame] | 720 | |
| 721 | remain -= page_length; |
| 722 | offset += page_length; |
| 723 | data_ptr += page_length; |
| 724 | } |
| 725 | |
| 726 | out_unpin_object: |
| 727 | i915_gem_object_unpin(obj); |
| 728 | out_unlock: |
| 729 | mutex_unlock(&dev->struct_mutex); |
| 730 | out_unpin_pages: |
| 731 | for (i = 0; i < pinned_pages; i++) |
| 732 | page_cache_release(user_pages[i]); |
Jesse Barnes | 8e7d2b2 | 2009-05-08 16:13:25 -0700 | [diff] [blame] | 733 | drm_free_large(user_pages); |
Eric Anholt | 3de09aa | 2009-03-09 09:42:23 -0700 | [diff] [blame] | 734 | |
| 735 | return ret; |
| 736 | } |
| 737 | |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 738 | /** |
| 739 | * This is the fast shmem pwrite path, which attempts to directly |
| 740 | * copy_from_user into the kmapped pages backing the object. |
| 741 | */ |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 742 | static int |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 743 | i915_gem_shmem_pwrite_fast(struct drm_device *dev, struct drm_gem_object *obj, |
| 744 | struct drm_i915_gem_pwrite *args, |
| 745 | struct drm_file *file_priv) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 746 | { |
Daniel Vetter | 23010e4 | 2010-03-08 13:35:02 +0100 | [diff] [blame] | 747 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 748 | ssize_t remain; |
| 749 | loff_t offset, page_base; |
| 750 | char __user *user_data; |
| 751 | int page_offset, page_length; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 752 | int ret; |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 753 | |
| 754 | user_data = (char __user *) (uintptr_t) args->data_ptr; |
| 755 | remain = args->size; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 756 | |
| 757 | mutex_lock(&dev->struct_mutex); |
| 758 | |
Chris Wilson | 4bdadb9 | 2010-01-27 13:36:32 +0000 | [diff] [blame] | 759 | ret = i915_gem_object_get_pages(obj, 0); |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 760 | if (ret != 0) |
| 761 | goto fail_unlock; |
| 762 | |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 763 | ret = i915_gem_object_set_to_cpu_domain(obj, 1); |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 764 | if (ret != 0) |
| 765 | goto fail_put_pages; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 766 | |
Daniel Vetter | 23010e4 | 2010-03-08 13:35:02 +0100 | [diff] [blame] | 767 | obj_priv = to_intel_bo(obj); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 768 | offset = args->offset; |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 769 | obj_priv->dirty = 1; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 770 | |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 771 | while (remain > 0) { |
| 772 | /* Operation in this page |
| 773 | * |
| 774 | * page_base = page offset within aperture |
| 775 | * page_offset = offset within page |
| 776 | * page_length = bytes to copy for this page |
| 777 | */ |
| 778 | page_base = (offset & ~(PAGE_SIZE-1)); |
| 779 | page_offset = offset & (PAGE_SIZE-1); |
| 780 | page_length = remain; |
| 781 | if ((page_offset + remain) > PAGE_SIZE) |
| 782 | page_length = PAGE_SIZE - page_offset; |
| 783 | |
| 784 | ret = fast_shmem_write(obj_priv->pages, |
| 785 | page_base, page_offset, |
| 786 | user_data, page_length); |
| 787 | if (ret) |
| 788 | goto fail_put_pages; |
| 789 | |
| 790 | remain -= page_length; |
| 791 | user_data += page_length; |
| 792 | offset += page_length; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 793 | } |
| 794 | |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 795 | fail_put_pages: |
| 796 | i915_gem_object_put_pages(obj); |
| 797 | fail_unlock: |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 798 | mutex_unlock(&dev->struct_mutex); |
| 799 | |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 800 | return ret; |
| 801 | } |
| 802 | |
| 803 | /** |
| 804 | * This is the fallback shmem pwrite path, which uses get_user_pages to pin |
| 805 | * the memory and maps it using kmap_atomic for copying. |
| 806 | * |
| 807 | * This avoids taking mmap_sem for faulting on the user's address while the |
| 808 | * struct_mutex is held. |
| 809 | */ |
| 810 | static int |
| 811 | i915_gem_shmem_pwrite_slow(struct drm_device *dev, struct drm_gem_object *obj, |
| 812 | struct drm_i915_gem_pwrite *args, |
| 813 | struct drm_file *file_priv) |
| 814 | { |
Daniel Vetter | 23010e4 | 2010-03-08 13:35:02 +0100 | [diff] [blame] | 815 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 816 | struct mm_struct *mm = current->mm; |
| 817 | struct page **user_pages; |
| 818 | ssize_t remain; |
| 819 | loff_t offset, pinned_pages, i; |
| 820 | loff_t first_data_page, last_data_page, num_pages; |
| 821 | int shmem_page_index, shmem_page_offset; |
| 822 | int data_page_index, data_page_offset; |
| 823 | int page_length; |
| 824 | int ret; |
| 825 | uint64_t data_ptr = args->data_ptr; |
Eric Anholt | 280b713 | 2009-03-12 16:56:27 -0700 | [diff] [blame] | 826 | int do_bit17_swizzling; |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 827 | |
| 828 | remain = args->size; |
| 829 | |
| 830 | /* Pin the user pages containing the data. We can't fault while |
| 831 | * holding the struct mutex, and all of the pwrite implementations |
| 832 | * want to hold it while dereferencing the user data. |
| 833 | */ |
| 834 | first_data_page = data_ptr / PAGE_SIZE; |
| 835 | last_data_page = (data_ptr + args->size - 1) / PAGE_SIZE; |
| 836 | num_pages = last_data_page - first_data_page + 1; |
| 837 | |
Jesse Barnes | 8e7d2b2 | 2009-05-08 16:13:25 -0700 | [diff] [blame] | 838 | user_pages = drm_calloc_large(num_pages, sizeof(struct page *)); |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 839 | if (user_pages == NULL) |
| 840 | return -ENOMEM; |
| 841 | |
| 842 | down_read(&mm->mmap_sem); |
| 843 | pinned_pages = get_user_pages(current, mm, (uintptr_t)args->data_ptr, |
| 844 | num_pages, 0, 0, user_pages, NULL); |
| 845 | up_read(&mm->mmap_sem); |
| 846 | if (pinned_pages < num_pages) { |
| 847 | ret = -EFAULT; |
| 848 | goto fail_put_user_pages; |
| 849 | } |
| 850 | |
Eric Anholt | 280b713 | 2009-03-12 16:56:27 -0700 | [diff] [blame] | 851 | do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj); |
| 852 | |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 853 | mutex_lock(&dev->struct_mutex); |
| 854 | |
Chris Wilson | 07f73f6 | 2009-09-14 16:50:30 +0100 | [diff] [blame] | 855 | ret = i915_gem_object_get_pages_or_evict(obj); |
| 856 | if (ret) |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 857 | goto fail_unlock; |
| 858 | |
| 859 | ret = i915_gem_object_set_to_cpu_domain(obj, 1); |
| 860 | if (ret != 0) |
| 861 | goto fail_put_pages; |
| 862 | |
Daniel Vetter | 23010e4 | 2010-03-08 13:35:02 +0100 | [diff] [blame] | 863 | obj_priv = to_intel_bo(obj); |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 864 | offset = args->offset; |
| 865 | obj_priv->dirty = 1; |
| 866 | |
| 867 | while (remain > 0) { |
| 868 | /* Operation in this page |
| 869 | * |
| 870 | * shmem_page_index = page number within shmem file |
| 871 | * shmem_page_offset = offset within page in shmem file |
| 872 | * data_page_index = page number in get_user_pages return |
| 873 | * data_page_offset = offset with data_page_index page. |
| 874 | * page_length = bytes to copy for this page |
| 875 | */ |
| 876 | shmem_page_index = offset / PAGE_SIZE; |
| 877 | shmem_page_offset = offset & ~PAGE_MASK; |
| 878 | data_page_index = data_ptr / PAGE_SIZE - first_data_page; |
| 879 | data_page_offset = data_ptr & ~PAGE_MASK; |
| 880 | |
| 881 | page_length = remain; |
| 882 | if ((shmem_page_offset + page_length) > PAGE_SIZE) |
| 883 | page_length = PAGE_SIZE - shmem_page_offset; |
| 884 | if ((data_page_offset + page_length) > PAGE_SIZE) |
| 885 | page_length = PAGE_SIZE - data_page_offset; |
| 886 | |
Eric Anholt | 280b713 | 2009-03-12 16:56:27 -0700 | [diff] [blame] | 887 | if (do_bit17_swizzling) { |
Chris Wilson | 99a03df | 2010-05-27 14:15:34 +0100 | [diff] [blame] | 888 | slow_shmem_bit17_copy(obj_priv->pages[shmem_page_index], |
Eric Anholt | 280b713 | 2009-03-12 16:56:27 -0700 | [diff] [blame] | 889 | shmem_page_offset, |
| 890 | user_pages[data_page_index], |
| 891 | data_page_offset, |
Chris Wilson | 99a03df | 2010-05-27 14:15:34 +0100 | [diff] [blame] | 892 | page_length, |
| 893 | 0); |
| 894 | } else { |
| 895 | slow_shmem_copy(obj_priv->pages[shmem_page_index], |
| 896 | shmem_page_offset, |
| 897 | user_pages[data_page_index], |
| 898 | data_page_offset, |
| 899 | page_length); |
Eric Anholt | 280b713 | 2009-03-12 16:56:27 -0700 | [diff] [blame] | 900 | } |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 901 | |
| 902 | remain -= page_length; |
| 903 | data_ptr += page_length; |
| 904 | offset += page_length; |
| 905 | } |
| 906 | |
| 907 | fail_put_pages: |
| 908 | i915_gem_object_put_pages(obj); |
| 909 | fail_unlock: |
| 910 | mutex_unlock(&dev->struct_mutex); |
| 911 | fail_put_user_pages: |
| 912 | for (i = 0; i < pinned_pages; i++) |
| 913 | page_cache_release(user_pages[i]); |
Jesse Barnes | 8e7d2b2 | 2009-05-08 16:13:25 -0700 | [diff] [blame] | 914 | drm_free_large(user_pages); |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 915 | |
| 916 | return ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 917 | } |
| 918 | |
| 919 | /** |
| 920 | * Writes data to the object referenced by handle. |
| 921 | * |
| 922 | * On error, the contents of the buffer that were to be modified are undefined. |
| 923 | */ |
| 924 | int |
| 925 | i915_gem_pwrite_ioctl(struct drm_device *dev, void *data, |
| 926 | struct drm_file *file_priv) |
| 927 | { |
| 928 | struct drm_i915_gem_pwrite *args = data; |
| 929 | struct drm_gem_object *obj; |
| 930 | struct drm_i915_gem_object *obj_priv; |
| 931 | int ret = 0; |
| 932 | |
| 933 | obj = drm_gem_object_lookup(dev, file_priv, args->handle); |
| 934 | if (obj == NULL) |
Chris Wilson | bf79cb9 | 2010-08-04 14:19:46 +0100 | [diff] [blame] | 935 | return -ENOENT; |
Daniel Vetter | 23010e4 | 2010-03-08 13:35:02 +0100 | [diff] [blame] | 936 | obj_priv = to_intel_bo(obj); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 937 | |
| 938 | /* Bounds check destination. |
| 939 | * |
| 940 | * XXX: This could use review for overflow issues... |
| 941 | */ |
| 942 | if (args->offset > obj->size || args->size > obj->size || |
| 943 | args->offset + args->size > obj->size) { |
Luca Barbieri | bc9025b | 2010-02-09 05:49:12 +0000 | [diff] [blame] | 944 | drm_gem_object_unreference_unlocked(obj); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 945 | return -EINVAL; |
| 946 | } |
| 947 | |
| 948 | /* We can only do the GTT pwrite on untiled buffers, as otherwise |
| 949 | * it would end up going through the fenced access, and we'll get |
| 950 | * different detiling behavior between reading and writing. |
| 951 | * pread/pwrite currently are reading and writing from the CPU |
| 952 | * perspective, requiring manual detiling by the client. |
| 953 | */ |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 954 | if (obj_priv->phys_obj) |
| 955 | ret = i915_gem_phys_pwrite(dev, obj, args, file_priv); |
| 956 | else if (obj_priv->tiling_mode == I915_TILING_NONE && |
Chris Wilson | 9b8c4a0 | 2010-05-27 14:21:01 +0100 | [diff] [blame] | 957 | dev->gtt_total != 0 && |
| 958 | obj->write_domain != I915_GEM_DOMAIN_CPU) { |
Eric Anholt | 3de09aa | 2009-03-09 09:42:23 -0700 | [diff] [blame] | 959 | ret = i915_gem_gtt_pwrite_fast(dev, obj, args, file_priv); |
| 960 | if (ret == -EFAULT) { |
| 961 | ret = i915_gem_gtt_pwrite_slow(dev, obj, args, |
| 962 | file_priv); |
| 963 | } |
Eric Anholt | 280b713 | 2009-03-12 16:56:27 -0700 | [diff] [blame] | 964 | } else if (i915_gem_object_needs_bit17_swizzle(obj)) { |
| 965 | ret = i915_gem_shmem_pwrite_slow(dev, obj, args, file_priv); |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 966 | } else { |
| 967 | ret = i915_gem_shmem_pwrite_fast(dev, obj, args, file_priv); |
| 968 | if (ret == -EFAULT) { |
| 969 | ret = i915_gem_shmem_pwrite_slow(dev, obj, args, |
| 970 | file_priv); |
| 971 | } |
| 972 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 973 | |
| 974 | #if WATCH_PWRITE |
| 975 | if (ret) |
| 976 | DRM_INFO("pwrite failed %d\n", ret); |
| 977 | #endif |
| 978 | |
Luca Barbieri | bc9025b | 2010-02-09 05:49:12 +0000 | [diff] [blame] | 979 | drm_gem_object_unreference_unlocked(obj); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 980 | |
| 981 | return ret; |
| 982 | } |
| 983 | |
| 984 | /** |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 985 | * Called when user space prepares to use an object with the CPU, either |
| 986 | * through the mmap ioctl's mapping or a GTT mapping. |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 987 | */ |
| 988 | int |
| 989 | i915_gem_set_domain_ioctl(struct drm_device *dev, void *data, |
| 990 | struct drm_file *file_priv) |
| 991 | { |
Eric Anholt | a09ba7f | 2009-08-29 12:49:51 -0700 | [diff] [blame] | 992 | struct drm_i915_private *dev_priv = dev->dev_private; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 993 | struct drm_i915_gem_set_domain *args = data; |
| 994 | struct drm_gem_object *obj; |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 995 | struct drm_i915_gem_object *obj_priv; |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 996 | uint32_t read_domains = args->read_domains; |
| 997 | uint32_t write_domain = args->write_domain; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 998 | int ret; |
| 999 | |
| 1000 | if (!(dev->driver->driver_features & DRIVER_GEM)) |
| 1001 | return -ENODEV; |
| 1002 | |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 1003 | /* Only handle setting domains to types used by the CPU. */ |
Chris Wilson | 21d509e | 2009-06-06 09:46:02 +0100 | [diff] [blame] | 1004 | if (write_domain & I915_GEM_GPU_DOMAINS) |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 1005 | return -EINVAL; |
| 1006 | |
Chris Wilson | 21d509e | 2009-06-06 09:46:02 +0100 | [diff] [blame] | 1007 | if (read_domains & I915_GEM_GPU_DOMAINS) |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 1008 | return -EINVAL; |
| 1009 | |
| 1010 | /* Having something in the write domain implies it's in the read |
| 1011 | * domain, and only that read domain. Enforce that in the request. |
| 1012 | */ |
| 1013 | if (write_domain != 0 && read_domains != write_domain) |
| 1014 | return -EINVAL; |
| 1015 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1016 | obj = drm_gem_object_lookup(dev, file_priv, args->handle); |
| 1017 | if (obj == NULL) |
Chris Wilson | bf79cb9 | 2010-08-04 14:19:46 +0100 | [diff] [blame] | 1018 | return -ENOENT; |
Daniel Vetter | 23010e4 | 2010-03-08 13:35:02 +0100 | [diff] [blame] | 1019 | obj_priv = to_intel_bo(obj); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1020 | |
| 1021 | mutex_lock(&dev->struct_mutex); |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 1022 | |
| 1023 | intel_mark_busy(dev, obj); |
| 1024 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1025 | #if WATCH_BUF |
Krzysztof Halasa | cfd43c0 | 2009-06-20 00:31:28 +0200 | [diff] [blame] | 1026 | DRM_INFO("set_domain_ioctl %p(%zd), %08x %08x\n", |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 1027 | obj, obj->size, read_domains, write_domain); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1028 | #endif |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 1029 | if (read_domains & I915_GEM_DOMAIN_GTT) { |
| 1030 | ret = i915_gem_object_set_to_gtt_domain(obj, write_domain != 0); |
Eric Anholt | 0235439 | 2008-11-26 13:58:13 -0800 | [diff] [blame] | 1031 | |
Eric Anholt | a09ba7f | 2009-08-29 12:49:51 -0700 | [diff] [blame] | 1032 | /* Update the LRU on the fence for the CPU access that's |
| 1033 | * about to occur. |
| 1034 | */ |
| 1035 | if (obj_priv->fence_reg != I915_FENCE_REG_NONE) { |
Daniel Vetter | 007cc8a | 2010-04-28 11:02:31 +0200 | [diff] [blame] | 1036 | struct drm_i915_fence_reg *reg = |
| 1037 | &dev_priv->fence_regs[obj_priv->fence_reg]; |
| 1038 | list_move_tail(®->lru_list, |
Eric Anholt | a09ba7f | 2009-08-29 12:49:51 -0700 | [diff] [blame] | 1039 | &dev_priv->mm.fence_list); |
| 1040 | } |
| 1041 | |
Eric Anholt | 0235439 | 2008-11-26 13:58:13 -0800 | [diff] [blame] | 1042 | /* Silently promote "you're not bound, there was nothing to do" |
| 1043 | * to success, since the client was just asking us to |
| 1044 | * make sure everything was done. |
| 1045 | */ |
| 1046 | if (ret == -EINVAL) |
| 1047 | ret = 0; |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 1048 | } else { |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 1049 | ret = i915_gem_object_set_to_cpu_domain(obj, write_domain != 0); |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 1050 | } |
| 1051 | |
Chris Wilson | 7d1c480 | 2010-08-07 21:45:03 +0100 | [diff] [blame] | 1052 | |
| 1053 | /* Maintain LRU order of "inactive" objects */ |
| 1054 | if (ret == 0 && i915_gem_object_is_inactive(obj_priv)) |
| 1055 | list_move_tail(&obj_priv->list, &dev_priv->mm.inactive_list); |
| 1056 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1057 | drm_gem_object_unreference(obj); |
| 1058 | mutex_unlock(&dev->struct_mutex); |
| 1059 | return ret; |
| 1060 | } |
| 1061 | |
| 1062 | /** |
| 1063 | * Called when user space has done writes to this buffer |
| 1064 | */ |
| 1065 | int |
| 1066 | i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data, |
| 1067 | struct drm_file *file_priv) |
| 1068 | { |
| 1069 | struct drm_i915_gem_sw_finish *args = data; |
| 1070 | struct drm_gem_object *obj; |
| 1071 | struct drm_i915_gem_object *obj_priv; |
| 1072 | int ret = 0; |
| 1073 | |
| 1074 | if (!(dev->driver->driver_features & DRIVER_GEM)) |
| 1075 | return -ENODEV; |
| 1076 | |
| 1077 | mutex_lock(&dev->struct_mutex); |
| 1078 | obj = drm_gem_object_lookup(dev, file_priv, args->handle); |
| 1079 | if (obj == NULL) { |
| 1080 | mutex_unlock(&dev->struct_mutex); |
Chris Wilson | bf79cb9 | 2010-08-04 14:19:46 +0100 | [diff] [blame] | 1081 | return -ENOENT; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1082 | } |
| 1083 | |
| 1084 | #if WATCH_BUF |
Krzysztof Halasa | cfd43c0 | 2009-06-20 00:31:28 +0200 | [diff] [blame] | 1085 | DRM_INFO("%s: sw_finish %d (%p %zd)\n", |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1086 | __func__, args->handle, obj, obj->size); |
| 1087 | #endif |
Daniel Vetter | 23010e4 | 2010-03-08 13:35:02 +0100 | [diff] [blame] | 1088 | obj_priv = to_intel_bo(obj); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1089 | |
| 1090 | /* Pinned buffers may be scanout, so flush the cache */ |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 1091 | if (obj_priv->pin_count) |
| 1092 | i915_gem_object_flush_cpu_write_domain(obj); |
| 1093 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1094 | drm_gem_object_unreference(obj); |
| 1095 | mutex_unlock(&dev->struct_mutex); |
| 1096 | return ret; |
| 1097 | } |
| 1098 | |
| 1099 | /** |
| 1100 | * Maps the contents of an object, returning the address it is mapped |
| 1101 | * into. |
| 1102 | * |
| 1103 | * While the mapping holds a reference on the contents of the object, it doesn't |
| 1104 | * imply a ref on the object itself. |
| 1105 | */ |
| 1106 | int |
| 1107 | i915_gem_mmap_ioctl(struct drm_device *dev, void *data, |
| 1108 | struct drm_file *file_priv) |
| 1109 | { |
| 1110 | struct drm_i915_gem_mmap *args = data; |
| 1111 | struct drm_gem_object *obj; |
| 1112 | loff_t offset; |
| 1113 | unsigned long addr; |
| 1114 | |
| 1115 | if (!(dev->driver->driver_features & DRIVER_GEM)) |
| 1116 | return -ENODEV; |
| 1117 | |
| 1118 | obj = drm_gem_object_lookup(dev, file_priv, args->handle); |
| 1119 | if (obj == NULL) |
Chris Wilson | bf79cb9 | 2010-08-04 14:19:46 +0100 | [diff] [blame] | 1120 | return -ENOENT; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1121 | |
| 1122 | offset = args->offset; |
| 1123 | |
| 1124 | down_write(¤t->mm->mmap_sem); |
| 1125 | addr = do_mmap(obj->filp, 0, args->size, |
| 1126 | PROT_READ | PROT_WRITE, MAP_SHARED, |
| 1127 | args->offset); |
| 1128 | up_write(¤t->mm->mmap_sem); |
Luca Barbieri | bc9025b | 2010-02-09 05:49:12 +0000 | [diff] [blame] | 1129 | drm_gem_object_unreference_unlocked(obj); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1130 | if (IS_ERR((void *)addr)) |
| 1131 | return addr; |
| 1132 | |
| 1133 | args->addr_ptr = (uint64_t) addr; |
| 1134 | |
| 1135 | return 0; |
| 1136 | } |
| 1137 | |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1138 | /** |
| 1139 | * i915_gem_fault - fault a page into the GTT |
| 1140 | * vma: VMA in question |
| 1141 | * vmf: fault info |
| 1142 | * |
| 1143 | * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped |
| 1144 | * from userspace. The fault handler takes care of binding the object to |
| 1145 | * the GTT (if needed), allocating and programming a fence register (again, |
| 1146 | * only if needed based on whether the old reg is still valid or the object |
| 1147 | * is tiled) and inserting a new PTE into the faulting process. |
| 1148 | * |
| 1149 | * Note that the faulting process may involve evicting existing objects |
| 1150 | * from the GTT and/or fence registers to make room. So performance may |
| 1151 | * suffer if the GTT working set is large or there are few fence registers |
| 1152 | * left. |
| 1153 | */ |
| 1154 | int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf) |
| 1155 | { |
| 1156 | struct drm_gem_object *obj = vma->vm_private_data; |
| 1157 | struct drm_device *dev = obj->dev; |
Chris Wilson | 7d1c480 | 2010-08-07 21:45:03 +0100 | [diff] [blame] | 1158 | drm_i915_private_t *dev_priv = dev->dev_private; |
Daniel Vetter | 23010e4 | 2010-03-08 13:35:02 +0100 | [diff] [blame] | 1159 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1160 | pgoff_t page_offset; |
| 1161 | unsigned long pfn; |
| 1162 | int ret = 0; |
Jesse Barnes | 0f973f2 | 2009-01-26 17:10:45 -0800 | [diff] [blame] | 1163 | bool write = !!(vmf->flags & FAULT_FLAG_WRITE); |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1164 | |
| 1165 | /* We don't use vmf->pgoff since that has the fake offset */ |
| 1166 | page_offset = ((unsigned long)vmf->virtual_address - vma->vm_start) >> |
| 1167 | PAGE_SHIFT; |
| 1168 | |
| 1169 | /* Now bind it into the GTT if needed */ |
| 1170 | mutex_lock(&dev->struct_mutex); |
| 1171 | if (!obj_priv->gtt_space) { |
Chris Wilson | e67b8ce | 2009-09-14 16:50:26 +0100 | [diff] [blame] | 1172 | ret = i915_gem_object_bind_to_gtt(obj, 0); |
Chris Wilson | c715089 | 2009-09-23 00:43:56 +0100 | [diff] [blame] | 1173 | if (ret) |
| 1174 | goto unlock; |
Kristian Høgsberg | 07f4f3e | 2009-05-27 14:37:28 -0400 | [diff] [blame] | 1175 | |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1176 | ret = i915_gem_object_set_to_gtt_domain(obj, write); |
Chris Wilson | c715089 | 2009-09-23 00:43:56 +0100 | [diff] [blame] | 1177 | if (ret) |
| 1178 | goto unlock; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1179 | } |
| 1180 | |
| 1181 | /* Need a new fence register? */ |
Eric Anholt | a09ba7f | 2009-08-29 12:49:51 -0700 | [diff] [blame] | 1182 | if (obj_priv->tiling_mode != I915_TILING_NONE) { |
Chris Wilson | 8c4b8c3 | 2009-06-17 22:08:52 +0100 | [diff] [blame] | 1183 | ret = i915_gem_object_get_fence_reg(obj); |
Chris Wilson | c715089 | 2009-09-23 00:43:56 +0100 | [diff] [blame] | 1184 | if (ret) |
| 1185 | goto unlock; |
Eric Anholt | d9ddcb9 | 2009-01-27 10:33:49 -0800 | [diff] [blame] | 1186 | } |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1187 | |
Chris Wilson | 7d1c480 | 2010-08-07 21:45:03 +0100 | [diff] [blame] | 1188 | if (i915_gem_object_is_inactive(obj_priv)) |
| 1189 | list_move_tail(&obj_priv->list, &dev_priv->mm.inactive_list); |
| 1190 | |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1191 | pfn = ((dev->agp->base + obj_priv->gtt_offset) >> PAGE_SHIFT) + |
| 1192 | page_offset; |
| 1193 | |
| 1194 | /* Finally, remap it using the new GTT offset */ |
| 1195 | ret = vm_insert_pfn(vma, (unsigned long)vmf->virtual_address, pfn); |
Chris Wilson | c715089 | 2009-09-23 00:43:56 +0100 | [diff] [blame] | 1196 | unlock: |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1197 | mutex_unlock(&dev->struct_mutex); |
| 1198 | |
| 1199 | switch (ret) { |
Chris Wilson | c715089 | 2009-09-23 00:43:56 +0100 | [diff] [blame] | 1200 | case 0: |
| 1201 | case -ERESTARTSYS: |
| 1202 | return VM_FAULT_NOPAGE; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1203 | case -ENOMEM: |
| 1204 | case -EAGAIN: |
| 1205 | return VM_FAULT_OOM; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1206 | default: |
Chris Wilson | c715089 | 2009-09-23 00:43:56 +0100 | [diff] [blame] | 1207 | return VM_FAULT_SIGBUS; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1208 | } |
| 1209 | } |
| 1210 | |
| 1211 | /** |
| 1212 | * i915_gem_create_mmap_offset - create a fake mmap offset for an object |
| 1213 | * @obj: obj in question |
| 1214 | * |
| 1215 | * GEM memory mapping works by handing back to userspace a fake mmap offset |
| 1216 | * it can use in a subsequent mmap(2) call. The DRM core code then looks |
| 1217 | * up the object based on the offset and sets up the various memory mapping |
| 1218 | * structures. |
| 1219 | * |
| 1220 | * This routine allocates and attaches a fake offset for @obj. |
| 1221 | */ |
| 1222 | static int |
| 1223 | i915_gem_create_mmap_offset(struct drm_gem_object *obj) |
| 1224 | { |
| 1225 | struct drm_device *dev = obj->dev; |
| 1226 | struct drm_gem_mm *mm = dev->mm_private; |
Daniel Vetter | 23010e4 | 2010-03-08 13:35:02 +0100 | [diff] [blame] | 1227 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1228 | struct drm_map_list *list; |
Benjamin Herrenschmidt | f77d390 | 2009-02-02 16:55:46 +1100 | [diff] [blame] | 1229 | struct drm_local_map *map; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1230 | int ret = 0; |
| 1231 | |
| 1232 | /* Set the object up for mmap'ing */ |
| 1233 | list = &obj->map_list; |
Eric Anholt | 9a298b2 | 2009-03-24 12:23:04 -0700 | [diff] [blame] | 1234 | list->map = kzalloc(sizeof(struct drm_map_list), GFP_KERNEL); |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1235 | if (!list->map) |
| 1236 | return -ENOMEM; |
| 1237 | |
| 1238 | map = list->map; |
| 1239 | map->type = _DRM_GEM; |
| 1240 | map->size = obj->size; |
| 1241 | map->handle = obj; |
| 1242 | |
| 1243 | /* Get a DRM GEM mmap offset allocated... */ |
| 1244 | list->file_offset_node = drm_mm_search_free(&mm->offset_manager, |
| 1245 | obj->size / PAGE_SIZE, 0, 0); |
| 1246 | if (!list->file_offset_node) { |
| 1247 | DRM_ERROR("failed to allocate offset for bo %d\n", obj->name); |
| 1248 | ret = -ENOMEM; |
| 1249 | goto out_free_list; |
| 1250 | } |
| 1251 | |
| 1252 | list->file_offset_node = drm_mm_get_block(list->file_offset_node, |
| 1253 | obj->size / PAGE_SIZE, 0); |
| 1254 | if (!list->file_offset_node) { |
| 1255 | ret = -ENOMEM; |
| 1256 | goto out_free_list; |
| 1257 | } |
| 1258 | |
| 1259 | list->hash.key = list->file_offset_node->start; |
| 1260 | if (drm_ht_insert_item(&mm->offset_hash, &list->hash)) { |
| 1261 | DRM_ERROR("failed to add to map hash\n"); |
Chris Wilson | 5618ca6 | 2009-12-02 15:15:30 +0000 | [diff] [blame] | 1262 | ret = -ENOMEM; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1263 | goto out_free_mm; |
| 1264 | } |
| 1265 | |
| 1266 | /* By now we should be all set, any drm_mmap request on the offset |
| 1267 | * below will get to our mmap & fault handler */ |
| 1268 | obj_priv->mmap_offset = ((uint64_t) list->hash.key) << PAGE_SHIFT; |
| 1269 | |
| 1270 | return 0; |
| 1271 | |
| 1272 | out_free_mm: |
| 1273 | drm_mm_put_block(list->file_offset_node); |
| 1274 | out_free_list: |
Eric Anholt | 9a298b2 | 2009-03-24 12:23:04 -0700 | [diff] [blame] | 1275 | kfree(list->map); |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1276 | |
| 1277 | return ret; |
| 1278 | } |
| 1279 | |
Chris Wilson | 901782b | 2009-07-10 08:18:50 +0100 | [diff] [blame] | 1280 | /** |
| 1281 | * i915_gem_release_mmap - remove physical page mappings |
| 1282 | * @obj: obj in question |
| 1283 | * |
André Goddard Rosa | af901ca | 2009-11-14 13:09:05 -0200 | [diff] [blame] | 1284 | * Preserve the reservation of the mmapping with the DRM core code, but |
Chris Wilson | 901782b | 2009-07-10 08:18:50 +0100 | [diff] [blame] | 1285 | * relinquish ownership of the pages back to the system. |
| 1286 | * |
| 1287 | * It is vital that we remove the page mapping if we have mapped a tiled |
| 1288 | * object through the GTT and then lose the fence register due to |
| 1289 | * resource pressure. Similarly if the object has been moved out of the |
| 1290 | * aperture, than pages mapped into userspace must be revoked. Removing the |
| 1291 | * mapping will then trigger a page fault on the next user access, allowing |
| 1292 | * fixup by i915_gem_fault(). |
| 1293 | */ |
Eric Anholt | d05ca30 | 2009-07-10 13:02:26 -0700 | [diff] [blame] | 1294 | void |
Chris Wilson | 901782b | 2009-07-10 08:18:50 +0100 | [diff] [blame] | 1295 | i915_gem_release_mmap(struct drm_gem_object *obj) |
| 1296 | { |
| 1297 | struct drm_device *dev = obj->dev; |
Daniel Vetter | 23010e4 | 2010-03-08 13:35:02 +0100 | [diff] [blame] | 1298 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
Chris Wilson | 901782b | 2009-07-10 08:18:50 +0100 | [diff] [blame] | 1299 | |
| 1300 | if (dev->dev_mapping) |
| 1301 | unmap_mapping_range(dev->dev_mapping, |
| 1302 | obj_priv->mmap_offset, obj->size, 1); |
| 1303 | } |
| 1304 | |
Jesse Barnes | ab00b3e | 2009-02-11 14:01:46 -0800 | [diff] [blame] | 1305 | static void |
| 1306 | i915_gem_free_mmap_offset(struct drm_gem_object *obj) |
| 1307 | { |
| 1308 | struct drm_device *dev = obj->dev; |
Daniel Vetter | 23010e4 | 2010-03-08 13:35:02 +0100 | [diff] [blame] | 1309 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
Jesse Barnes | ab00b3e | 2009-02-11 14:01:46 -0800 | [diff] [blame] | 1310 | struct drm_gem_mm *mm = dev->mm_private; |
| 1311 | struct drm_map_list *list; |
| 1312 | |
| 1313 | list = &obj->map_list; |
| 1314 | drm_ht_remove_item(&mm->offset_hash, &list->hash); |
| 1315 | |
| 1316 | if (list->file_offset_node) { |
| 1317 | drm_mm_put_block(list->file_offset_node); |
| 1318 | list->file_offset_node = NULL; |
| 1319 | } |
| 1320 | |
| 1321 | if (list->map) { |
Eric Anholt | 9a298b2 | 2009-03-24 12:23:04 -0700 | [diff] [blame] | 1322 | kfree(list->map); |
Jesse Barnes | ab00b3e | 2009-02-11 14:01:46 -0800 | [diff] [blame] | 1323 | list->map = NULL; |
| 1324 | } |
| 1325 | |
| 1326 | obj_priv->mmap_offset = 0; |
| 1327 | } |
| 1328 | |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1329 | /** |
| 1330 | * i915_gem_get_gtt_alignment - return required GTT alignment for an object |
| 1331 | * @obj: object to check |
| 1332 | * |
| 1333 | * Return the required GTT alignment for an object, taking into account |
| 1334 | * potential fence register mapping if needed. |
| 1335 | */ |
| 1336 | static uint32_t |
| 1337 | i915_gem_get_gtt_alignment(struct drm_gem_object *obj) |
| 1338 | { |
| 1339 | struct drm_device *dev = obj->dev; |
Daniel Vetter | 23010e4 | 2010-03-08 13:35:02 +0100 | [diff] [blame] | 1340 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1341 | int start, i; |
| 1342 | |
| 1343 | /* |
| 1344 | * Minimum alignment is 4k (GTT page size), but might be greater |
| 1345 | * if a fence register is needed for the object. |
| 1346 | */ |
| 1347 | if (IS_I965G(dev) || obj_priv->tiling_mode == I915_TILING_NONE) |
| 1348 | return 4096; |
| 1349 | |
| 1350 | /* |
| 1351 | * Previous chips need to be aligned to the size of the smallest |
| 1352 | * fence register that can contain the object. |
| 1353 | */ |
| 1354 | if (IS_I9XX(dev)) |
| 1355 | start = 1024*1024; |
| 1356 | else |
| 1357 | start = 512*1024; |
| 1358 | |
| 1359 | for (i = start; i < obj->size; i <<= 1) |
| 1360 | ; |
| 1361 | |
| 1362 | return i; |
| 1363 | } |
| 1364 | |
| 1365 | /** |
| 1366 | * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing |
| 1367 | * @dev: DRM device |
| 1368 | * @data: GTT mapping ioctl data |
| 1369 | * @file_priv: GEM object info |
| 1370 | * |
| 1371 | * Simply returns the fake offset to userspace so it can mmap it. |
| 1372 | * The mmap call will end up in drm_gem_mmap(), which will set things |
| 1373 | * up so we can get faults in the handler above. |
| 1374 | * |
| 1375 | * The fault handler will take care of binding the object into the GTT |
| 1376 | * (since it may have been evicted to make room for something), allocating |
| 1377 | * a fence register, and mapping the appropriate aperture address into |
| 1378 | * userspace. |
| 1379 | */ |
| 1380 | int |
| 1381 | i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data, |
| 1382 | struct drm_file *file_priv) |
| 1383 | { |
| 1384 | struct drm_i915_gem_mmap_gtt *args = data; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1385 | struct drm_gem_object *obj; |
| 1386 | struct drm_i915_gem_object *obj_priv; |
| 1387 | int ret; |
| 1388 | |
| 1389 | if (!(dev->driver->driver_features & DRIVER_GEM)) |
| 1390 | return -ENODEV; |
| 1391 | |
| 1392 | obj = drm_gem_object_lookup(dev, file_priv, args->handle); |
| 1393 | if (obj == NULL) |
Chris Wilson | bf79cb9 | 2010-08-04 14:19:46 +0100 | [diff] [blame] | 1394 | return -ENOENT; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1395 | |
| 1396 | mutex_lock(&dev->struct_mutex); |
| 1397 | |
Daniel Vetter | 23010e4 | 2010-03-08 13:35:02 +0100 | [diff] [blame] | 1398 | obj_priv = to_intel_bo(obj); |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1399 | |
Chris Wilson | ab18282 | 2009-09-22 18:46:17 +0100 | [diff] [blame] | 1400 | if (obj_priv->madv != I915_MADV_WILLNEED) { |
| 1401 | DRM_ERROR("Attempting to mmap a purgeable buffer\n"); |
| 1402 | drm_gem_object_unreference(obj); |
| 1403 | mutex_unlock(&dev->struct_mutex); |
| 1404 | return -EINVAL; |
| 1405 | } |
| 1406 | |
| 1407 | |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1408 | if (!obj_priv->mmap_offset) { |
| 1409 | ret = i915_gem_create_mmap_offset(obj); |
Chris Wilson | 13af106 | 2009-02-11 14:26:31 +0000 | [diff] [blame] | 1410 | if (ret) { |
| 1411 | drm_gem_object_unreference(obj); |
| 1412 | mutex_unlock(&dev->struct_mutex); |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1413 | return ret; |
Chris Wilson | 13af106 | 2009-02-11 14:26:31 +0000 | [diff] [blame] | 1414 | } |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1415 | } |
| 1416 | |
| 1417 | args->offset = obj_priv->mmap_offset; |
| 1418 | |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1419 | /* |
| 1420 | * Pull it into the GTT so that we have a page list (makes the |
| 1421 | * initial fault faster and any subsequent flushing possible). |
| 1422 | */ |
| 1423 | if (!obj_priv->agp_mem) { |
Chris Wilson | e67b8ce | 2009-09-14 16:50:26 +0100 | [diff] [blame] | 1424 | ret = i915_gem_object_bind_to_gtt(obj, 0); |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1425 | if (ret) { |
| 1426 | drm_gem_object_unreference(obj); |
| 1427 | mutex_unlock(&dev->struct_mutex); |
| 1428 | return ret; |
| 1429 | } |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1430 | } |
| 1431 | |
| 1432 | drm_gem_object_unreference(obj); |
| 1433 | mutex_unlock(&dev->struct_mutex); |
| 1434 | |
| 1435 | return 0; |
| 1436 | } |
| 1437 | |
Ben Gamari | 6911a9b | 2009-04-02 11:24:54 -0700 | [diff] [blame] | 1438 | void |
Eric Anholt | 856fa19 | 2009-03-19 14:10:50 -0700 | [diff] [blame] | 1439 | i915_gem_object_put_pages(struct drm_gem_object *obj) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1440 | { |
Daniel Vetter | 23010e4 | 2010-03-08 13:35:02 +0100 | [diff] [blame] | 1441 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1442 | int page_count = obj->size / PAGE_SIZE; |
| 1443 | int i; |
| 1444 | |
Eric Anholt | 856fa19 | 2009-03-19 14:10:50 -0700 | [diff] [blame] | 1445 | BUG_ON(obj_priv->pages_refcount == 0); |
Chris Wilson | bb6baf7 | 2009-09-22 14:24:13 +0100 | [diff] [blame] | 1446 | BUG_ON(obj_priv->madv == __I915_MADV_PURGED); |
Eric Anholt | 856fa19 | 2009-03-19 14:10:50 -0700 | [diff] [blame] | 1447 | |
| 1448 | if (--obj_priv->pages_refcount != 0) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1449 | return; |
| 1450 | |
Eric Anholt | 280b713 | 2009-03-12 16:56:27 -0700 | [diff] [blame] | 1451 | if (obj_priv->tiling_mode != I915_TILING_NONE) |
| 1452 | i915_gem_object_save_bit_17_swizzle(obj); |
| 1453 | |
Chris Wilson | 3ef94da | 2009-09-14 16:50:29 +0100 | [diff] [blame] | 1454 | if (obj_priv->madv == I915_MADV_DONTNEED) |
Chris Wilson | 13a05fd | 2009-09-20 23:03:19 +0100 | [diff] [blame] | 1455 | obj_priv->dirty = 0; |
Chris Wilson | 3ef94da | 2009-09-14 16:50:29 +0100 | [diff] [blame] | 1456 | |
| 1457 | for (i = 0; i < page_count; i++) { |
Chris Wilson | 3ef94da | 2009-09-14 16:50:29 +0100 | [diff] [blame] | 1458 | if (obj_priv->dirty) |
| 1459 | set_page_dirty(obj_priv->pages[i]); |
| 1460 | |
| 1461 | if (obj_priv->madv == I915_MADV_WILLNEED) |
Eric Anholt | 856fa19 | 2009-03-19 14:10:50 -0700 | [diff] [blame] | 1462 | mark_page_accessed(obj_priv->pages[i]); |
Chris Wilson | 3ef94da | 2009-09-14 16:50:29 +0100 | [diff] [blame] | 1463 | |
| 1464 | page_cache_release(obj_priv->pages[i]); |
| 1465 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1466 | obj_priv->dirty = 0; |
| 1467 | |
Jesse Barnes | 8e7d2b2 | 2009-05-08 16:13:25 -0700 | [diff] [blame] | 1468 | drm_free_large(obj_priv->pages); |
Eric Anholt | 856fa19 | 2009-03-19 14:10:50 -0700 | [diff] [blame] | 1469 | obj_priv->pages = NULL; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1470 | } |
| 1471 | |
Daniel Vetter | e35a41d | 2010-02-11 22:13:59 +0100 | [diff] [blame^] | 1472 | static uint32_t |
| 1473 | i915_gem_next_request_seqno(struct drm_device *dev) |
| 1474 | { |
| 1475 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 1476 | |
| 1477 | return dev_priv->next_seqno; |
| 1478 | } |
| 1479 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1480 | static void |
Zou Nan hai | 852835f | 2010-05-21 09:08:56 +0800 | [diff] [blame] | 1481 | i915_gem_object_move_to_active(struct drm_gem_object *obj, uint32_t seqno, |
| 1482 | struct intel_ring_buffer *ring) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1483 | { |
| 1484 | struct drm_device *dev = obj->dev; |
| 1485 | drm_i915_private_t *dev_priv = dev->dev_private; |
Daniel Vetter | 23010e4 | 2010-03-08 13:35:02 +0100 | [diff] [blame] | 1486 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
Zou Nan hai | 852835f | 2010-05-21 09:08:56 +0800 | [diff] [blame] | 1487 | BUG_ON(ring == NULL); |
| 1488 | obj_priv->ring = ring; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1489 | |
| 1490 | /* Add a reference if we're newly entering the active list. */ |
| 1491 | if (!obj_priv->active) { |
| 1492 | drm_gem_object_reference(obj); |
| 1493 | obj_priv->active = 1; |
| 1494 | } |
Daniel Vetter | e35a41d | 2010-02-11 22:13:59 +0100 | [diff] [blame^] | 1495 | |
| 1496 | /* Take the seqno of the next request if none is given */ |
| 1497 | if (seqno == 0) |
| 1498 | seqno = i915_gem_next_request_seqno(dev); |
| 1499 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1500 | /* Move from whatever list we were on to the tail of execution. */ |
Carl Worth | 5e118f4 | 2009-03-20 11:54:25 -0700 | [diff] [blame] | 1501 | spin_lock(&dev_priv->mm.active_list_lock); |
Zou Nan hai | 852835f | 2010-05-21 09:08:56 +0800 | [diff] [blame] | 1502 | list_move_tail(&obj_priv->list, &ring->active_list); |
Carl Worth | 5e118f4 | 2009-03-20 11:54:25 -0700 | [diff] [blame] | 1503 | spin_unlock(&dev_priv->mm.active_list_lock); |
Eric Anholt | ce44b0e | 2008-11-06 16:00:31 -0800 | [diff] [blame] | 1504 | obj_priv->last_rendering_seqno = seqno; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1505 | } |
| 1506 | |
Eric Anholt | ce44b0e | 2008-11-06 16:00:31 -0800 | [diff] [blame] | 1507 | static void |
| 1508 | i915_gem_object_move_to_flushing(struct drm_gem_object *obj) |
| 1509 | { |
| 1510 | struct drm_device *dev = obj->dev; |
| 1511 | drm_i915_private_t *dev_priv = dev->dev_private; |
Daniel Vetter | 23010e4 | 2010-03-08 13:35:02 +0100 | [diff] [blame] | 1512 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
Eric Anholt | ce44b0e | 2008-11-06 16:00:31 -0800 | [diff] [blame] | 1513 | |
| 1514 | BUG_ON(!obj_priv->active); |
| 1515 | list_move_tail(&obj_priv->list, &dev_priv->mm.flushing_list); |
| 1516 | obj_priv->last_rendering_seqno = 0; |
| 1517 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1518 | |
Chris Wilson | 963b483 | 2009-09-20 23:03:54 +0100 | [diff] [blame] | 1519 | /* Immediately discard the backing storage */ |
| 1520 | static void |
| 1521 | i915_gem_object_truncate(struct drm_gem_object *obj) |
| 1522 | { |
Daniel Vetter | 23010e4 | 2010-03-08 13:35:02 +0100 | [diff] [blame] | 1523 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
Chris Wilson | bb6baf7 | 2009-09-22 14:24:13 +0100 | [diff] [blame] | 1524 | struct inode *inode; |
Chris Wilson | 963b483 | 2009-09-20 23:03:54 +0100 | [diff] [blame] | 1525 | |
Chris Wilson | ae9fed6 | 2010-08-07 11:01:30 +0100 | [diff] [blame] | 1526 | /* Our goal here is to return as much of the memory as |
| 1527 | * is possible back to the system as we are called from OOM. |
| 1528 | * To do this we must instruct the shmfs to drop all of its |
| 1529 | * backing pages, *now*. Here we mirror the actions taken |
| 1530 | * when by shmem_delete_inode() to release the backing store. |
| 1531 | */ |
Chris Wilson | bb6baf7 | 2009-09-22 14:24:13 +0100 | [diff] [blame] | 1532 | inode = obj->filp->f_path.dentry->d_inode; |
Chris Wilson | ae9fed6 | 2010-08-07 11:01:30 +0100 | [diff] [blame] | 1533 | truncate_inode_pages(inode->i_mapping, 0); |
| 1534 | if (inode->i_op->truncate_range) |
| 1535 | inode->i_op->truncate_range(inode, 0, (loff_t)-1); |
Chris Wilson | bb6baf7 | 2009-09-22 14:24:13 +0100 | [diff] [blame] | 1536 | |
| 1537 | obj_priv->madv = __I915_MADV_PURGED; |
Chris Wilson | 963b483 | 2009-09-20 23:03:54 +0100 | [diff] [blame] | 1538 | } |
| 1539 | |
| 1540 | static inline int |
| 1541 | i915_gem_object_is_purgeable(struct drm_i915_gem_object *obj_priv) |
| 1542 | { |
| 1543 | return obj_priv->madv == I915_MADV_DONTNEED; |
| 1544 | } |
| 1545 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1546 | static void |
| 1547 | i915_gem_object_move_to_inactive(struct drm_gem_object *obj) |
| 1548 | { |
| 1549 | struct drm_device *dev = obj->dev; |
| 1550 | drm_i915_private_t *dev_priv = dev->dev_private; |
Daniel Vetter | 23010e4 | 2010-03-08 13:35:02 +0100 | [diff] [blame] | 1551 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1552 | |
| 1553 | i915_verify_inactive(dev, __FILE__, __LINE__); |
| 1554 | if (obj_priv->pin_count != 0) |
| 1555 | list_del_init(&obj_priv->list); |
| 1556 | else |
| 1557 | list_move_tail(&obj_priv->list, &dev_priv->mm.inactive_list); |
| 1558 | |
Daniel Vetter | 99fcb76 | 2010-02-07 16:20:18 +0100 | [diff] [blame] | 1559 | BUG_ON(!list_empty(&obj_priv->gpu_write_list)); |
| 1560 | |
Eric Anholt | ce44b0e | 2008-11-06 16:00:31 -0800 | [diff] [blame] | 1561 | obj_priv->last_rendering_seqno = 0; |
Zou Nan hai | 852835f | 2010-05-21 09:08:56 +0800 | [diff] [blame] | 1562 | obj_priv->ring = NULL; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1563 | if (obj_priv->active) { |
| 1564 | obj_priv->active = 0; |
| 1565 | drm_gem_object_unreference(obj); |
| 1566 | } |
| 1567 | i915_verify_inactive(dev, __FILE__, __LINE__); |
| 1568 | } |
| 1569 | |
Daniel Vetter | 6356039 | 2010-02-19 11:51:59 +0100 | [diff] [blame] | 1570 | static void |
| 1571 | i915_gem_process_flushing_list(struct drm_device *dev, |
Zou Nan hai | 852835f | 2010-05-21 09:08:56 +0800 | [diff] [blame] | 1572 | uint32_t flush_domains, uint32_t seqno, |
| 1573 | struct intel_ring_buffer *ring) |
Daniel Vetter | 6356039 | 2010-02-19 11:51:59 +0100 | [diff] [blame] | 1574 | { |
| 1575 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 1576 | struct drm_i915_gem_object *obj_priv, *next; |
| 1577 | |
| 1578 | list_for_each_entry_safe(obj_priv, next, |
| 1579 | &dev_priv->mm.gpu_write_list, |
| 1580 | gpu_write_list) { |
Daniel Vetter | a8089e8 | 2010-04-09 19:05:09 +0000 | [diff] [blame] | 1581 | struct drm_gem_object *obj = &obj_priv->base; |
Daniel Vetter | 6356039 | 2010-02-19 11:51:59 +0100 | [diff] [blame] | 1582 | |
| 1583 | if ((obj->write_domain & flush_domains) == |
Zou Nan hai | 852835f | 2010-05-21 09:08:56 +0800 | [diff] [blame] | 1584 | obj->write_domain && |
| 1585 | obj_priv->ring->ring_flag == ring->ring_flag) { |
Daniel Vetter | 6356039 | 2010-02-19 11:51:59 +0100 | [diff] [blame] | 1586 | uint32_t old_write_domain = obj->write_domain; |
| 1587 | |
| 1588 | obj->write_domain = 0; |
| 1589 | list_del_init(&obj_priv->gpu_write_list); |
Zou Nan hai | 852835f | 2010-05-21 09:08:56 +0800 | [diff] [blame] | 1590 | i915_gem_object_move_to_active(obj, seqno, ring); |
Daniel Vetter | 6356039 | 2010-02-19 11:51:59 +0100 | [diff] [blame] | 1591 | |
| 1592 | /* update the fence lru list */ |
Daniel Vetter | 007cc8a | 2010-04-28 11:02:31 +0200 | [diff] [blame] | 1593 | if (obj_priv->fence_reg != I915_FENCE_REG_NONE) { |
| 1594 | struct drm_i915_fence_reg *reg = |
| 1595 | &dev_priv->fence_regs[obj_priv->fence_reg]; |
| 1596 | list_move_tail(®->lru_list, |
Daniel Vetter | 6356039 | 2010-02-19 11:51:59 +0100 | [diff] [blame] | 1597 | &dev_priv->mm.fence_list); |
Daniel Vetter | 007cc8a | 2010-04-28 11:02:31 +0200 | [diff] [blame] | 1598 | } |
Daniel Vetter | 6356039 | 2010-02-19 11:51:59 +0100 | [diff] [blame] | 1599 | |
| 1600 | trace_i915_gem_object_change_domain(obj, |
| 1601 | obj->read_domains, |
| 1602 | old_write_domain); |
| 1603 | } |
| 1604 | } |
| 1605 | } |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 1606 | |
Daniel Vetter | 5a5a0c6 | 2009-09-15 22:57:36 +0200 | [diff] [blame] | 1607 | uint32_t |
Eric Anholt | b962442 | 2009-06-03 07:27:35 +0000 | [diff] [blame] | 1608 | i915_add_request(struct drm_device *dev, struct drm_file *file_priv, |
Zou Nan hai | 852835f | 2010-05-21 09:08:56 +0800 | [diff] [blame] | 1609 | uint32_t flush_domains, struct intel_ring_buffer *ring) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1610 | { |
| 1611 | drm_i915_private_t *dev_priv = dev->dev_private; |
Eric Anholt | b962442 | 2009-06-03 07:27:35 +0000 | [diff] [blame] | 1612 | struct drm_i915_file_private *i915_file_priv = NULL; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1613 | struct drm_i915_gem_request *request; |
| 1614 | uint32_t seqno; |
| 1615 | int was_empty; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1616 | |
Eric Anholt | b962442 | 2009-06-03 07:27:35 +0000 | [diff] [blame] | 1617 | if (file_priv != NULL) |
| 1618 | i915_file_priv = file_priv->driver_priv; |
| 1619 | |
Eric Anholt | 9a298b2 | 2009-03-24 12:23:04 -0700 | [diff] [blame] | 1620 | request = kzalloc(sizeof(*request), GFP_KERNEL); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1621 | if (request == NULL) |
| 1622 | return 0; |
| 1623 | |
Zou Nan hai | 852835f | 2010-05-21 09:08:56 +0800 | [diff] [blame] | 1624 | seqno = ring->add_request(dev, ring, file_priv, flush_domains); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1625 | |
| 1626 | request->seqno = seqno; |
Zou Nan hai | 852835f | 2010-05-21 09:08:56 +0800 | [diff] [blame] | 1627 | request->ring = ring; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1628 | request->emitted_jiffies = jiffies; |
Zou Nan hai | 852835f | 2010-05-21 09:08:56 +0800 | [diff] [blame] | 1629 | was_empty = list_empty(&ring->request_list); |
| 1630 | list_add_tail(&request->list, &ring->request_list); |
| 1631 | |
Eric Anholt | b962442 | 2009-06-03 07:27:35 +0000 | [diff] [blame] | 1632 | if (i915_file_priv) { |
| 1633 | list_add_tail(&request->client_list, |
| 1634 | &i915_file_priv->mm.request_list); |
| 1635 | } else { |
| 1636 | INIT_LIST_HEAD(&request->client_list); |
| 1637 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1638 | |
Eric Anholt | ce44b0e | 2008-11-06 16:00:31 -0800 | [diff] [blame] | 1639 | /* Associate any objects on the flushing list matching the write |
| 1640 | * domain we're flushing with our flush. |
| 1641 | */ |
Daniel Vetter | 6356039 | 2010-02-19 11:51:59 +0100 | [diff] [blame] | 1642 | if (flush_domains != 0) |
Zou Nan hai | 852835f | 2010-05-21 09:08:56 +0800 | [diff] [blame] | 1643 | i915_gem_process_flushing_list(dev, flush_domains, seqno, ring); |
Eric Anholt | ce44b0e | 2008-11-06 16:00:31 -0800 | [diff] [blame] | 1644 | |
Ben Gamari | f65d942 | 2009-09-14 17:48:44 -0400 | [diff] [blame] | 1645 | if (!dev_priv->mm.suspended) { |
| 1646 | mod_timer(&dev_priv->hangcheck_timer, jiffies + DRM_I915_HANGCHECK_PERIOD); |
| 1647 | if (was_empty) |
| 1648 | queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, HZ); |
| 1649 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1650 | return seqno; |
| 1651 | } |
| 1652 | |
| 1653 | /** |
| 1654 | * Command execution barrier |
| 1655 | * |
| 1656 | * Ensures that all commands in the ring are finished |
| 1657 | * before signalling the CPU |
| 1658 | */ |
Eric Anholt | 3043c60 | 2008-10-02 12:24:47 -0700 | [diff] [blame] | 1659 | static uint32_t |
Zou Nan hai | 852835f | 2010-05-21 09:08:56 +0800 | [diff] [blame] | 1660 | i915_retire_commands(struct drm_device *dev, struct intel_ring_buffer *ring) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1661 | { |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1662 | uint32_t flush_domains = 0; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1663 | |
| 1664 | /* The sampler always gets flushed on i965 (sigh) */ |
| 1665 | if (IS_I965G(dev)) |
| 1666 | flush_domains |= I915_GEM_DOMAIN_SAMPLER; |
Zou Nan hai | 852835f | 2010-05-21 09:08:56 +0800 | [diff] [blame] | 1667 | |
| 1668 | ring->flush(dev, ring, |
| 1669 | I915_GEM_DOMAIN_COMMAND, flush_domains); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1670 | return flush_domains; |
| 1671 | } |
| 1672 | |
| 1673 | /** |
| 1674 | * Moves buffers associated only with the given active seqno from the active |
| 1675 | * to inactive list, potentially freeing them. |
| 1676 | */ |
| 1677 | static void |
| 1678 | i915_gem_retire_request(struct drm_device *dev, |
| 1679 | struct drm_i915_gem_request *request) |
| 1680 | { |
| 1681 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 1682 | |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 1683 | trace_i915_gem_request_retire(dev, request->seqno); |
| 1684 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1685 | /* Move any buffers on the active list that are no longer referenced |
| 1686 | * by the ringbuffer to the flushing/inactive lists as appropriate. |
| 1687 | */ |
Carl Worth | 5e118f4 | 2009-03-20 11:54:25 -0700 | [diff] [blame] | 1688 | spin_lock(&dev_priv->mm.active_list_lock); |
Zou Nan hai | 852835f | 2010-05-21 09:08:56 +0800 | [diff] [blame] | 1689 | while (!list_empty(&request->ring->active_list)) { |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1690 | struct drm_gem_object *obj; |
| 1691 | struct drm_i915_gem_object *obj_priv; |
| 1692 | |
Zou Nan hai | 852835f | 2010-05-21 09:08:56 +0800 | [diff] [blame] | 1693 | obj_priv = list_first_entry(&request->ring->active_list, |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1694 | struct drm_i915_gem_object, |
| 1695 | list); |
Daniel Vetter | a8089e8 | 2010-04-09 19:05:09 +0000 | [diff] [blame] | 1696 | obj = &obj_priv->base; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1697 | |
| 1698 | /* If the seqno being retired doesn't match the oldest in the |
| 1699 | * list, then the oldest in the list must still be newer than |
| 1700 | * this seqno. |
| 1701 | */ |
| 1702 | if (obj_priv->last_rendering_seqno != request->seqno) |
Carl Worth | 5e118f4 | 2009-03-20 11:54:25 -0700 | [diff] [blame] | 1703 | goto out; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1704 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1705 | #if WATCH_LRU |
| 1706 | DRM_INFO("%s: retire %d moves to inactive list %p\n", |
| 1707 | __func__, request->seqno, obj); |
| 1708 | #endif |
| 1709 | |
Eric Anholt | ce44b0e | 2008-11-06 16:00:31 -0800 | [diff] [blame] | 1710 | if (obj->write_domain != 0) |
| 1711 | i915_gem_object_move_to_flushing(obj); |
Shaohua Li | 68c8434 | 2009-04-08 10:58:23 +0800 | [diff] [blame] | 1712 | else { |
| 1713 | /* Take a reference on the object so it won't be |
| 1714 | * freed while the spinlock is held. The list |
| 1715 | * protection for this spinlock is safe when breaking |
| 1716 | * the lock like this since the next thing we do |
| 1717 | * is just get the head of the list again. |
| 1718 | */ |
| 1719 | drm_gem_object_reference(obj); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1720 | i915_gem_object_move_to_inactive(obj); |
Shaohua Li | 68c8434 | 2009-04-08 10:58:23 +0800 | [diff] [blame] | 1721 | spin_unlock(&dev_priv->mm.active_list_lock); |
| 1722 | drm_gem_object_unreference(obj); |
| 1723 | spin_lock(&dev_priv->mm.active_list_lock); |
| 1724 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1725 | } |
Carl Worth | 5e118f4 | 2009-03-20 11:54:25 -0700 | [diff] [blame] | 1726 | out: |
| 1727 | spin_unlock(&dev_priv->mm.active_list_lock); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1728 | } |
| 1729 | |
| 1730 | /** |
| 1731 | * Returns true if seq1 is later than seq2. |
| 1732 | */ |
Ben Gamari | 22be172 | 2009-09-14 17:48:43 -0400 | [diff] [blame] | 1733 | bool |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1734 | i915_seqno_passed(uint32_t seq1, uint32_t seq2) |
| 1735 | { |
| 1736 | return (int32_t)(seq1 - seq2) >= 0; |
| 1737 | } |
| 1738 | |
| 1739 | uint32_t |
Zou Nan hai | 852835f | 2010-05-21 09:08:56 +0800 | [diff] [blame] | 1740 | i915_get_gem_seqno(struct drm_device *dev, |
Zou Nan hai | d1b851f | 2010-05-21 09:08:57 +0800 | [diff] [blame] | 1741 | struct intel_ring_buffer *ring) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1742 | { |
Zou Nan hai | 852835f | 2010-05-21 09:08:56 +0800 | [diff] [blame] | 1743 | return ring->get_gem_seqno(dev, ring); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1744 | } |
| 1745 | |
| 1746 | /** |
| 1747 | * This function clears the request list as sequence numbers are passed. |
| 1748 | */ |
Chris Wilson | b09a1fe | 2010-07-23 23:18:49 +0100 | [diff] [blame] | 1749 | static void |
| 1750 | i915_gem_retire_requests_ring(struct drm_device *dev, |
| 1751 | struct intel_ring_buffer *ring) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1752 | { |
| 1753 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 1754 | uint32_t seqno; |
| 1755 | |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 1756 | if (!ring->status_page.page_addr |
Zou Nan hai | 852835f | 2010-05-21 09:08:56 +0800 | [diff] [blame] | 1757 | || list_empty(&ring->request_list)) |
Karsten Wiese | 6c0594a | 2009-02-23 15:07:57 +0100 | [diff] [blame] | 1758 | return; |
| 1759 | |
Zou Nan hai | 852835f | 2010-05-21 09:08:56 +0800 | [diff] [blame] | 1760 | seqno = i915_get_gem_seqno(dev, ring); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1761 | |
Zou Nan hai | 852835f | 2010-05-21 09:08:56 +0800 | [diff] [blame] | 1762 | while (!list_empty(&ring->request_list)) { |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1763 | struct drm_i915_gem_request *request; |
| 1764 | uint32_t retiring_seqno; |
| 1765 | |
Zou Nan hai | 852835f | 2010-05-21 09:08:56 +0800 | [diff] [blame] | 1766 | request = list_first_entry(&ring->request_list, |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1767 | struct drm_i915_gem_request, |
| 1768 | list); |
| 1769 | retiring_seqno = request->seqno; |
| 1770 | |
| 1771 | if (i915_seqno_passed(seqno, retiring_seqno) || |
Ben Gamari | ba1234d | 2009-09-14 17:48:47 -0400 | [diff] [blame] | 1772 | atomic_read(&dev_priv->mm.wedged)) { |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1773 | i915_gem_retire_request(dev, request); |
| 1774 | |
| 1775 | list_del(&request->list); |
Eric Anholt | b962442 | 2009-06-03 07:27:35 +0000 | [diff] [blame] | 1776 | list_del(&request->client_list); |
Eric Anholt | 9a298b2 | 2009-03-24 12:23:04 -0700 | [diff] [blame] | 1777 | kfree(request); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1778 | } else |
| 1779 | break; |
| 1780 | } |
Chris Wilson | 9d34e5d | 2009-09-24 05:26:06 +0100 | [diff] [blame] | 1781 | |
| 1782 | if (unlikely (dev_priv->trace_irq_seqno && |
| 1783 | i915_seqno_passed(dev_priv->trace_irq_seqno, seqno))) { |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 1784 | |
| 1785 | ring->user_irq_put(dev, ring); |
Chris Wilson | 9d34e5d | 2009-09-24 05:26:06 +0100 | [diff] [blame] | 1786 | dev_priv->trace_irq_seqno = 0; |
| 1787 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1788 | } |
| 1789 | |
| 1790 | void |
Chris Wilson | b09a1fe | 2010-07-23 23:18:49 +0100 | [diff] [blame] | 1791 | i915_gem_retire_requests(struct drm_device *dev) |
| 1792 | { |
| 1793 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 1794 | |
Chris Wilson | be72615 | 2010-07-23 23:18:50 +0100 | [diff] [blame] | 1795 | if (!list_empty(&dev_priv->mm.deferred_free_list)) { |
| 1796 | struct drm_i915_gem_object *obj_priv, *tmp; |
| 1797 | |
| 1798 | /* We must be careful that during unbind() we do not |
| 1799 | * accidentally infinitely recurse into retire requests. |
| 1800 | * Currently: |
| 1801 | * retire -> free -> unbind -> wait -> retire_ring |
| 1802 | */ |
| 1803 | list_for_each_entry_safe(obj_priv, tmp, |
| 1804 | &dev_priv->mm.deferred_free_list, |
| 1805 | list) |
| 1806 | i915_gem_free_object_tail(&obj_priv->base); |
| 1807 | } |
| 1808 | |
Chris Wilson | b09a1fe | 2010-07-23 23:18:49 +0100 | [diff] [blame] | 1809 | i915_gem_retire_requests_ring(dev, &dev_priv->render_ring); |
| 1810 | if (HAS_BSD(dev)) |
| 1811 | i915_gem_retire_requests_ring(dev, &dev_priv->bsd_ring); |
| 1812 | } |
| 1813 | |
Daniel Vetter | 75ef9da | 2010-08-21 00:25:16 +0200 | [diff] [blame] | 1814 | static void |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1815 | i915_gem_retire_work_handler(struct work_struct *work) |
| 1816 | { |
| 1817 | drm_i915_private_t *dev_priv; |
| 1818 | struct drm_device *dev; |
| 1819 | |
| 1820 | dev_priv = container_of(work, drm_i915_private_t, |
| 1821 | mm.retire_work.work); |
| 1822 | dev = dev_priv->dev; |
| 1823 | |
| 1824 | mutex_lock(&dev->struct_mutex); |
Chris Wilson | b09a1fe | 2010-07-23 23:18:49 +0100 | [diff] [blame] | 1825 | i915_gem_retire_requests(dev); |
Zou Nan hai | d1b851f | 2010-05-21 09:08:57 +0800 | [diff] [blame] | 1826 | |
Keith Packard | 6dbe277 | 2008-10-14 21:41:13 -0700 | [diff] [blame] | 1827 | if (!dev_priv->mm.suspended && |
Zou Nan hai | d1b851f | 2010-05-21 09:08:57 +0800 | [diff] [blame] | 1828 | (!list_empty(&dev_priv->render_ring.request_list) || |
| 1829 | (HAS_BSD(dev) && |
| 1830 | !list_empty(&dev_priv->bsd_ring.request_list)))) |
Eric Anholt | 9c9fe1f | 2009-08-03 16:09:16 -0700 | [diff] [blame] | 1831 | queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, HZ); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1832 | mutex_unlock(&dev->struct_mutex); |
| 1833 | } |
| 1834 | |
Daniel Vetter | 5a5a0c6 | 2009-09-15 22:57:36 +0200 | [diff] [blame] | 1835 | int |
Zou Nan hai | 852835f | 2010-05-21 09:08:56 +0800 | [diff] [blame] | 1836 | i915_do_wait_request(struct drm_device *dev, uint32_t seqno, |
| 1837 | int interruptible, struct intel_ring_buffer *ring) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1838 | { |
| 1839 | drm_i915_private_t *dev_priv = dev->dev_private; |
Jesse Barnes | 802c7eb | 2009-05-05 16:03:48 -0700 | [diff] [blame] | 1840 | u32 ier; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1841 | int ret = 0; |
| 1842 | |
| 1843 | BUG_ON(seqno == 0); |
| 1844 | |
Daniel Vetter | e35a41d | 2010-02-11 22:13:59 +0100 | [diff] [blame^] | 1845 | if (seqno == dev_priv->next_seqno) { |
| 1846 | seqno = i915_add_request(dev, NULL, 0, ring); |
| 1847 | if (seqno == 0) |
| 1848 | return -ENOMEM; |
| 1849 | } |
| 1850 | |
Ben Gamari | ba1234d | 2009-09-14 17:48:47 -0400 | [diff] [blame] | 1851 | if (atomic_read(&dev_priv->mm.wedged)) |
Ben Gamari | ffed1d0 | 2009-09-14 17:48:41 -0400 | [diff] [blame] | 1852 | return -EIO; |
| 1853 | |
Zou Nan hai | 852835f | 2010-05-21 09:08:56 +0800 | [diff] [blame] | 1854 | if (!i915_seqno_passed(ring->get_gem_seqno(dev, ring), seqno)) { |
Eric Anholt | bad720f | 2009-10-22 16:11:14 -0700 | [diff] [blame] | 1855 | if (HAS_PCH_SPLIT(dev)) |
Zhenyu Wang | 036a4a7 | 2009-06-08 14:40:19 +0800 | [diff] [blame] | 1856 | ier = I915_READ(DEIER) | I915_READ(GTIER); |
| 1857 | else |
| 1858 | ier = I915_READ(IER); |
Jesse Barnes | 802c7eb | 2009-05-05 16:03:48 -0700 | [diff] [blame] | 1859 | if (!ier) { |
| 1860 | DRM_ERROR("something (likely vbetool) disabled " |
| 1861 | "interrupts, re-enabling\n"); |
| 1862 | i915_driver_irq_preinstall(dev); |
| 1863 | i915_driver_irq_postinstall(dev); |
| 1864 | } |
| 1865 | |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 1866 | trace_i915_gem_request_wait_begin(dev, seqno); |
| 1867 | |
Zou Nan hai | 852835f | 2010-05-21 09:08:56 +0800 | [diff] [blame] | 1868 | ring->waiting_gem_seqno = seqno; |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 1869 | ring->user_irq_get(dev, ring); |
Daniel Vetter | 48764bf | 2009-09-15 22:57:32 +0200 | [diff] [blame] | 1870 | if (interruptible) |
Zou Nan hai | 852835f | 2010-05-21 09:08:56 +0800 | [diff] [blame] | 1871 | ret = wait_event_interruptible(ring->irq_queue, |
| 1872 | i915_seqno_passed( |
| 1873 | ring->get_gem_seqno(dev, ring), seqno) |
| 1874 | || atomic_read(&dev_priv->mm.wedged)); |
Daniel Vetter | 48764bf | 2009-09-15 22:57:32 +0200 | [diff] [blame] | 1875 | else |
Zou Nan hai | 852835f | 2010-05-21 09:08:56 +0800 | [diff] [blame] | 1876 | wait_event(ring->irq_queue, |
| 1877 | i915_seqno_passed( |
| 1878 | ring->get_gem_seqno(dev, ring), seqno) |
| 1879 | || atomic_read(&dev_priv->mm.wedged)); |
Daniel Vetter | 48764bf | 2009-09-15 22:57:32 +0200 | [diff] [blame] | 1880 | |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 1881 | ring->user_irq_put(dev, ring); |
Zou Nan hai | 852835f | 2010-05-21 09:08:56 +0800 | [diff] [blame] | 1882 | ring->waiting_gem_seqno = 0; |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 1883 | |
| 1884 | trace_i915_gem_request_wait_end(dev, seqno); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1885 | } |
Ben Gamari | ba1234d | 2009-09-14 17:48:47 -0400 | [diff] [blame] | 1886 | if (atomic_read(&dev_priv->mm.wedged)) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1887 | ret = -EIO; |
| 1888 | |
| 1889 | if (ret && ret != -ERESTARTSYS) |
| 1890 | DRM_ERROR("%s returns %d (awaiting %d at %d)\n", |
Zou Nan hai | 852835f | 2010-05-21 09:08:56 +0800 | [diff] [blame] | 1891 | __func__, ret, seqno, ring->get_gem_seqno(dev, ring)); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1892 | |
| 1893 | /* Directly dispatch request retiring. While we have the work queue |
| 1894 | * to handle this, the waiter on a request often wants an associated |
| 1895 | * buffer to have made it to the inactive list, and we would need |
| 1896 | * a separate wait queue to handle that. |
| 1897 | */ |
| 1898 | if (ret == 0) |
Chris Wilson | b09a1fe | 2010-07-23 23:18:49 +0100 | [diff] [blame] | 1899 | i915_gem_retire_requests_ring(dev, ring); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1900 | |
| 1901 | return ret; |
| 1902 | } |
| 1903 | |
Daniel Vetter | 48764bf | 2009-09-15 22:57:32 +0200 | [diff] [blame] | 1904 | /** |
| 1905 | * Waits for a sequence number to be signaled, and cleans up the |
| 1906 | * request and object lists appropriately for that event. |
| 1907 | */ |
| 1908 | static int |
Zou Nan hai | 852835f | 2010-05-21 09:08:56 +0800 | [diff] [blame] | 1909 | i915_wait_request(struct drm_device *dev, uint32_t seqno, |
| 1910 | struct intel_ring_buffer *ring) |
Daniel Vetter | 48764bf | 2009-09-15 22:57:32 +0200 | [diff] [blame] | 1911 | { |
Zou Nan hai | 852835f | 2010-05-21 09:08:56 +0800 | [diff] [blame] | 1912 | return i915_do_wait_request(dev, seqno, 1, ring); |
Daniel Vetter | 48764bf | 2009-09-15 22:57:32 +0200 | [diff] [blame] | 1913 | } |
| 1914 | |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 1915 | static void |
| 1916 | i915_gem_flush(struct drm_device *dev, |
| 1917 | uint32_t invalidate_domains, |
| 1918 | uint32_t flush_domains) |
| 1919 | { |
| 1920 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 1921 | if (flush_domains & I915_GEM_DOMAIN_CPU) |
| 1922 | drm_agp_chipset_flush(dev); |
| 1923 | dev_priv->render_ring.flush(dev, &dev_priv->render_ring, |
| 1924 | invalidate_domains, |
| 1925 | flush_domains); |
Zou Nan hai | d1b851f | 2010-05-21 09:08:57 +0800 | [diff] [blame] | 1926 | |
| 1927 | if (HAS_BSD(dev)) |
| 1928 | dev_priv->bsd_ring.flush(dev, &dev_priv->bsd_ring, |
| 1929 | invalidate_domains, |
| 1930 | flush_domains); |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 1931 | } |
| 1932 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1933 | /** |
| 1934 | * Ensures that all rendering to the object has completed and the object is |
| 1935 | * safe to unbind from the GTT or access from the CPU. |
| 1936 | */ |
| 1937 | static int |
Daniel Vetter | e35a41d | 2010-02-11 22:13:59 +0100 | [diff] [blame^] | 1938 | i915_gem_object_wait_rendering(struct drm_gem_object *obj, |
| 1939 | bool interruptible) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1940 | { |
| 1941 | struct drm_device *dev = obj->dev; |
Daniel Vetter | 23010e4 | 2010-03-08 13:35:02 +0100 | [diff] [blame] | 1942 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1943 | int ret; |
| 1944 | |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 1945 | /* This function only exists to support waiting for existing rendering, |
| 1946 | * not for emitting required flushes. |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1947 | */ |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 1948 | BUG_ON((obj->write_domain & I915_GEM_GPU_DOMAINS) != 0); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1949 | |
| 1950 | /* If there is rendering queued on the buffer being evicted, wait for |
| 1951 | * it. |
| 1952 | */ |
| 1953 | if (obj_priv->active) { |
| 1954 | #if WATCH_BUF |
| 1955 | DRM_INFO("%s: object %p wait for seqno %08x\n", |
| 1956 | __func__, obj, obj_priv->last_rendering_seqno); |
| 1957 | #endif |
Daniel Vetter | e35a41d | 2010-02-11 22:13:59 +0100 | [diff] [blame^] | 1958 | ret = i915_do_wait_request(dev, |
| 1959 | obj_priv->last_rendering_seqno, |
| 1960 | interruptible, |
| 1961 | obj_priv->ring); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1962 | if (ret != 0) |
| 1963 | return ret; |
| 1964 | } |
| 1965 | |
| 1966 | return 0; |
| 1967 | } |
| 1968 | |
| 1969 | /** |
| 1970 | * Unbinds an object from the GTT aperture. |
| 1971 | */ |
Jesse Barnes | 0f973f2 | 2009-01-26 17:10:45 -0800 | [diff] [blame] | 1972 | int |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1973 | i915_gem_object_unbind(struct drm_gem_object *obj) |
| 1974 | { |
| 1975 | struct drm_device *dev = obj->dev; |
Daniel Vetter | 4a87b8c | 2010-02-19 11:51:57 +0100 | [diff] [blame] | 1976 | drm_i915_private_t *dev_priv = dev->dev_private; |
Daniel Vetter | 23010e4 | 2010-03-08 13:35:02 +0100 | [diff] [blame] | 1977 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1978 | int ret = 0; |
| 1979 | |
| 1980 | #if WATCH_BUF |
| 1981 | DRM_INFO("%s:%d %p\n", __func__, __LINE__, obj); |
| 1982 | DRM_INFO("gtt_space %p\n", obj_priv->gtt_space); |
| 1983 | #endif |
| 1984 | if (obj_priv->gtt_space == NULL) |
| 1985 | return 0; |
| 1986 | |
| 1987 | if (obj_priv->pin_count != 0) { |
| 1988 | DRM_ERROR("Attempting to unbind pinned buffer\n"); |
| 1989 | return -EINVAL; |
| 1990 | } |
| 1991 | |
Eric Anholt | 5323fd0 | 2009-09-09 11:50:45 -0700 | [diff] [blame] | 1992 | /* blow away mappings if mapped through GTT */ |
| 1993 | i915_gem_release_mmap(obj); |
| 1994 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1995 | /* Move the object to the CPU domain to ensure that |
| 1996 | * any possible CPU writes while it's not in the GTT |
| 1997 | * are flushed when we go to remap it. This will |
| 1998 | * also ensure that all pending GPU writes are finished |
| 1999 | * before we unbind. |
| 2000 | */ |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2001 | ret = i915_gem_object_set_to_cpu_domain(obj, 1); |
Chris Wilson | 8dc1775 | 2010-07-23 23:18:51 +0100 | [diff] [blame] | 2002 | if (ret == -ERESTARTSYS) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2003 | return ret; |
Chris Wilson | 8dc1775 | 2010-07-23 23:18:51 +0100 | [diff] [blame] | 2004 | /* Continue on if we fail due to EIO, the GPU is hung so we |
| 2005 | * should be safe and we need to cleanup or else we might |
| 2006 | * cause memory corruption through use-after-free. |
| 2007 | */ |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2008 | |
Daniel Vetter | 96b47b6 | 2009-12-15 17:50:00 +0100 | [diff] [blame] | 2009 | /* release the fence reg _after_ flushing */ |
| 2010 | if (obj_priv->fence_reg != I915_FENCE_REG_NONE) |
| 2011 | i915_gem_clear_fence_reg(obj); |
| 2012 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2013 | if (obj_priv->agp_mem != NULL) { |
| 2014 | drm_unbind_agp(obj_priv->agp_mem); |
| 2015 | drm_free_agp(obj_priv->agp_mem, obj->size / PAGE_SIZE); |
| 2016 | obj_priv->agp_mem = NULL; |
| 2017 | } |
| 2018 | |
Eric Anholt | 856fa19 | 2009-03-19 14:10:50 -0700 | [diff] [blame] | 2019 | i915_gem_object_put_pages(obj); |
Chris Wilson | a32808c | 2009-09-20 21:29:47 +0100 | [diff] [blame] | 2020 | BUG_ON(obj_priv->pages_refcount); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2021 | |
| 2022 | if (obj_priv->gtt_space) { |
| 2023 | atomic_dec(&dev->gtt_count); |
| 2024 | atomic_sub(obj->size, &dev->gtt_memory); |
| 2025 | |
| 2026 | drm_mm_put_block(obj_priv->gtt_space); |
| 2027 | obj_priv->gtt_space = NULL; |
| 2028 | } |
| 2029 | |
| 2030 | /* Remove ourselves from the LRU list if present. */ |
Daniel Vetter | 4a87b8c | 2010-02-19 11:51:57 +0100 | [diff] [blame] | 2031 | spin_lock(&dev_priv->mm.active_list_lock); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2032 | if (!list_empty(&obj_priv->list)) |
| 2033 | list_del_init(&obj_priv->list); |
Daniel Vetter | 4a87b8c | 2010-02-19 11:51:57 +0100 | [diff] [blame] | 2034 | spin_unlock(&dev_priv->mm.active_list_lock); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2035 | |
Chris Wilson | 963b483 | 2009-09-20 23:03:54 +0100 | [diff] [blame] | 2036 | if (i915_gem_object_is_purgeable(obj_priv)) |
| 2037 | i915_gem_object_truncate(obj); |
| 2038 | |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 2039 | trace_i915_gem_object_unbind(obj); |
| 2040 | |
Chris Wilson | 8dc1775 | 2010-07-23 23:18:51 +0100 | [diff] [blame] | 2041 | return ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2042 | } |
| 2043 | |
Chris Wilson | b47eb4a | 2010-08-07 11:01:23 +0100 | [diff] [blame] | 2044 | int |
Daniel Vetter | 4df2faf | 2010-02-19 11:52:00 +0100 | [diff] [blame] | 2045 | i915_gpu_idle(struct drm_device *dev) |
| 2046 | { |
| 2047 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 2048 | bool lists_empty; |
Zou Nan hai | d1b851f | 2010-05-21 09:08:57 +0800 | [diff] [blame] | 2049 | uint32_t seqno1, seqno2; |
Zou Nan hai | 852835f | 2010-05-21 09:08:56 +0800 | [diff] [blame] | 2050 | int ret; |
Daniel Vetter | 4df2faf | 2010-02-19 11:52:00 +0100 | [diff] [blame] | 2051 | |
| 2052 | spin_lock(&dev_priv->mm.active_list_lock); |
Zou Nan hai | d1b851f | 2010-05-21 09:08:57 +0800 | [diff] [blame] | 2053 | lists_empty = (list_empty(&dev_priv->mm.flushing_list) && |
| 2054 | list_empty(&dev_priv->render_ring.active_list) && |
| 2055 | (!HAS_BSD(dev) || |
| 2056 | list_empty(&dev_priv->bsd_ring.active_list))); |
Daniel Vetter | 4df2faf | 2010-02-19 11:52:00 +0100 | [diff] [blame] | 2057 | spin_unlock(&dev_priv->mm.active_list_lock); |
| 2058 | |
| 2059 | if (lists_empty) |
| 2060 | return 0; |
| 2061 | |
| 2062 | /* Flush everything onto the inactive list. */ |
| 2063 | i915_gem_flush(dev, I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS); |
Zou Nan hai | d1b851f | 2010-05-21 09:08:57 +0800 | [diff] [blame] | 2064 | seqno1 = i915_add_request(dev, NULL, I915_GEM_GPU_DOMAINS, |
Zou Nan hai | 852835f | 2010-05-21 09:08:56 +0800 | [diff] [blame] | 2065 | &dev_priv->render_ring); |
Zou Nan hai | d1b851f | 2010-05-21 09:08:57 +0800 | [diff] [blame] | 2066 | if (seqno1 == 0) |
Daniel Vetter | 4df2faf | 2010-02-19 11:52:00 +0100 | [diff] [blame] | 2067 | return -ENOMEM; |
Zou Nan hai | d1b851f | 2010-05-21 09:08:57 +0800 | [diff] [blame] | 2068 | ret = i915_wait_request(dev, seqno1, &dev_priv->render_ring); |
| 2069 | |
| 2070 | if (HAS_BSD(dev)) { |
| 2071 | seqno2 = i915_add_request(dev, NULL, I915_GEM_GPU_DOMAINS, |
| 2072 | &dev_priv->bsd_ring); |
| 2073 | if (seqno2 == 0) |
| 2074 | return -ENOMEM; |
| 2075 | |
| 2076 | ret = i915_wait_request(dev, seqno2, &dev_priv->bsd_ring); |
| 2077 | if (ret) |
| 2078 | return ret; |
| 2079 | } |
| 2080 | |
Daniel Vetter | 4df2faf | 2010-02-19 11:52:00 +0100 | [diff] [blame] | 2081 | |
Zou Nan hai | 852835f | 2010-05-21 09:08:56 +0800 | [diff] [blame] | 2082 | return ret; |
Daniel Vetter | 4df2faf | 2010-02-19 11:52:00 +0100 | [diff] [blame] | 2083 | } |
| 2084 | |
Ben Gamari | 6911a9b | 2009-04-02 11:24:54 -0700 | [diff] [blame] | 2085 | int |
Chris Wilson | 4bdadb9 | 2010-01-27 13:36:32 +0000 | [diff] [blame] | 2086 | i915_gem_object_get_pages(struct drm_gem_object *obj, |
| 2087 | gfp_t gfpmask) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2088 | { |
Daniel Vetter | 23010e4 | 2010-03-08 13:35:02 +0100 | [diff] [blame] | 2089 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2090 | int page_count, i; |
| 2091 | struct address_space *mapping; |
| 2092 | struct inode *inode; |
| 2093 | struct page *page; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2094 | |
Daniel Vetter | 778c354 | 2010-05-13 11:49:44 +0200 | [diff] [blame] | 2095 | BUG_ON(obj_priv->pages_refcount |
| 2096 | == DRM_I915_GEM_OBJECT_MAX_PAGES_REFCOUNT); |
| 2097 | |
Eric Anholt | 856fa19 | 2009-03-19 14:10:50 -0700 | [diff] [blame] | 2098 | if (obj_priv->pages_refcount++ != 0) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2099 | return 0; |
| 2100 | |
| 2101 | /* Get the list of pages out of our struct file. They'll be pinned |
| 2102 | * at this point until we release them. |
| 2103 | */ |
| 2104 | page_count = obj->size / PAGE_SIZE; |
Eric Anholt | 856fa19 | 2009-03-19 14:10:50 -0700 | [diff] [blame] | 2105 | BUG_ON(obj_priv->pages != NULL); |
Jesse Barnes | 8e7d2b2 | 2009-05-08 16:13:25 -0700 | [diff] [blame] | 2106 | obj_priv->pages = drm_calloc_large(page_count, sizeof(struct page *)); |
Eric Anholt | 856fa19 | 2009-03-19 14:10:50 -0700 | [diff] [blame] | 2107 | if (obj_priv->pages == NULL) { |
Eric Anholt | 856fa19 | 2009-03-19 14:10:50 -0700 | [diff] [blame] | 2108 | obj_priv->pages_refcount--; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2109 | return -ENOMEM; |
| 2110 | } |
| 2111 | |
| 2112 | inode = obj->filp->f_path.dentry->d_inode; |
| 2113 | mapping = inode->i_mapping; |
| 2114 | for (i = 0; i < page_count; i++) { |
Chris Wilson | 4bdadb9 | 2010-01-27 13:36:32 +0000 | [diff] [blame] | 2115 | page = read_cache_page_gfp(mapping, i, |
Linus Torvalds | 985b823 | 2010-07-02 10:04:42 +1000 | [diff] [blame] | 2116 | GFP_HIGHUSER | |
Chris Wilson | 4bdadb9 | 2010-01-27 13:36:32 +0000 | [diff] [blame] | 2117 | __GFP_COLD | |
Linus Torvalds | cd9f040 | 2010-07-18 09:44:37 -0700 | [diff] [blame] | 2118 | __GFP_RECLAIMABLE | |
Chris Wilson | 4bdadb9 | 2010-01-27 13:36:32 +0000 | [diff] [blame] | 2119 | gfpmask); |
Chris Wilson | 1f2b101 | 2010-03-12 19:52:55 +0000 | [diff] [blame] | 2120 | if (IS_ERR(page)) |
| 2121 | goto err_pages; |
| 2122 | |
Eric Anholt | 856fa19 | 2009-03-19 14:10:50 -0700 | [diff] [blame] | 2123 | obj_priv->pages[i] = page; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2124 | } |
Eric Anholt | 280b713 | 2009-03-12 16:56:27 -0700 | [diff] [blame] | 2125 | |
| 2126 | if (obj_priv->tiling_mode != I915_TILING_NONE) |
| 2127 | i915_gem_object_do_bit_17_swizzle(obj); |
| 2128 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2129 | return 0; |
Chris Wilson | 1f2b101 | 2010-03-12 19:52:55 +0000 | [diff] [blame] | 2130 | |
| 2131 | err_pages: |
| 2132 | while (i--) |
| 2133 | page_cache_release(obj_priv->pages[i]); |
| 2134 | |
| 2135 | drm_free_large(obj_priv->pages); |
| 2136 | obj_priv->pages = NULL; |
| 2137 | obj_priv->pages_refcount--; |
| 2138 | return PTR_ERR(page); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2139 | } |
| 2140 | |
Eric Anholt | 4e901fd | 2009-10-26 16:44:17 -0700 | [diff] [blame] | 2141 | static void sandybridge_write_fence_reg(struct drm_i915_fence_reg *reg) |
| 2142 | { |
| 2143 | struct drm_gem_object *obj = reg->obj; |
| 2144 | struct drm_device *dev = obj->dev; |
| 2145 | drm_i915_private_t *dev_priv = dev->dev_private; |
Daniel Vetter | 23010e4 | 2010-03-08 13:35:02 +0100 | [diff] [blame] | 2146 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
Eric Anholt | 4e901fd | 2009-10-26 16:44:17 -0700 | [diff] [blame] | 2147 | int regnum = obj_priv->fence_reg; |
| 2148 | uint64_t val; |
| 2149 | |
| 2150 | val = (uint64_t)((obj_priv->gtt_offset + obj->size - 4096) & |
| 2151 | 0xfffff000) << 32; |
| 2152 | val |= obj_priv->gtt_offset & 0xfffff000; |
| 2153 | val |= (uint64_t)((obj_priv->stride / 128) - 1) << |
| 2154 | SANDYBRIDGE_FENCE_PITCH_SHIFT; |
| 2155 | |
| 2156 | if (obj_priv->tiling_mode == I915_TILING_Y) |
| 2157 | val |= 1 << I965_FENCE_TILING_Y_SHIFT; |
| 2158 | val |= I965_FENCE_REG_VALID; |
| 2159 | |
| 2160 | I915_WRITE64(FENCE_REG_SANDYBRIDGE_0 + (regnum * 8), val); |
| 2161 | } |
| 2162 | |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2163 | static void i965_write_fence_reg(struct drm_i915_fence_reg *reg) |
| 2164 | { |
| 2165 | struct drm_gem_object *obj = reg->obj; |
| 2166 | struct drm_device *dev = obj->dev; |
| 2167 | drm_i915_private_t *dev_priv = dev->dev_private; |
Daniel Vetter | 23010e4 | 2010-03-08 13:35:02 +0100 | [diff] [blame] | 2168 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2169 | int regnum = obj_priv->fence_reg; |
| 2170 | uint64_t val; |
| 2171 | |
| 2172 | val = (uint64_t)((obj_priv->gtt_offset + obj->size - 4096) & |
| 2173 | 0xfffff000) << 32; |
| 2174 | val |= obj_priv->gtt_offset & 0xfffff000; |
| 2175 | val |= ((obj_priv->stride / 128) - 1) << I965_FENCE_PITCH_SHIFT; |
| 2176 | if (obj_priv->tiling_mode == I915_TILING_Y) |
| 2177 | val |= 1 << I965_FENCE_TILING_Y_SHIFT; |
| 2178 | val |= I965_FENCE_REG_VALID; |
| 2179 | |
| 2180 | I915_WRITE64(FENCE_REG_965_0 + (regnum * 8), val); |
| 2181 | } |
| 2182 | |
| 2183 | static void i915_write_fence_reg(struct drm_i915_fence_reg *reg) |
| 2184 | { |
| 2185 | struct drm_gem_object *obj = reg->obj; |
| 2186 | struct drm_device *dev = obj->dev; |
| 2187 | drm_i915_private_t *dev_priv = dev->dev_private; |
Daniel Vetter | 23010e4 | 2010-03-08 13:35:02 +0100 | [diff] [blame] | 2188 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2189 | int regnum = obj_priv->fence_reg; |
Jesse Barnes | 0f973f2 | 2009-01-26 17:10:45 -0800 | [diff] [blame] | 2190 | int tile_width; |
Eric Anholt | dc529a4 | 2009-03-10 22:34:49 -0700 | [diff] [blame] | 2191 | uint32_t fence_reg, val; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2192 | uint32_t pitch_val; |
| 2193 | |
| 2194 | if ((obj_priv->gtt_offset & ~I915_FENCE_START_MASK) || |
| 2195 | (obj_priv->gtt_offset & (obj->size - 1))) { |
Linus Torvalds | f06da26 | 2009-02-09 08:57:29 -0800 | [diff] [blame] | 2196 | WARN(1, "%s: object 0x%08x not 1M or size (0x%zx) aligned\n", |
Jesse Barnes | 0f973f2 | 2009-01-26 17:10:45 -0800 | [diff] [blame] | 2197 | __func__, obj_priv->gtt_offset, obj->size); |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2198 | return; |
| 2199 | } |
| 2200 | |
Jesse Barnes | 0f973f2 | 2009-01-26 17:10:45 -0800 | [diff] [blame] | 2201 | if (obj_priv->tiling_mode == I915_TILING_Y && |
| 2202 | HAS_128_BYTE_Y_TILING(dev)) |
| 2203 | tile_width = 128; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2204 | else |
Jesse Barnes | 0f973f2 | 2009-01-26 17:10:45 -0800 | [diff] [blame] | 2205 | tile_width = 512; |
| 2206 | |
| 2207 | /* Note: pitch better be a power of two tile widths */ |
| 2208 | pitch_val = obj_priv->stride / tile_width; |
| 2209 | pitch_val = ffs(pitch_val) - 1; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2210 | |
Daniel Vetter | c36a2a6 | 2010-04-17 15:12:03 +0200 | [diff] [blame] | 2211 | if (obj_priv->tiling_mode == I915_TILING_Y && |
| 2212 | HAS_128_BYTE_Y_TILING(dev)) |
| 2213 | WARN_ON(pitch_val > I830_FENCE_MAX_PITCH_VAL); |
| 2214 | else |
| 2215 | WARN_ON(pitch_val > I915_FENCE_MAX_PITCH_VAL); |
| 2216 | |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2217 | val = obj_priv->gtt_offset; |
| 2218 | if (obj_priv->tiling_mode == I915_TILING_Y) |
| 2219 | val |= 1 << I830_FENCE_TILING_Y_SHIFT; |
| 2220 | val |= I915_FENCE_SIZE_BITS(obj->size); |
| 2221 | val |= pitch_val << I830_FENCE_PITCH_SHIFT; |
| 2222 | val |= I830_FENCE_REG_VALID; |
| 2223 | |
Eric Anholt | dc529a4 | 2009-03-10 22:34:49 -0700 | [diff] [blame] | 2224 | if (regnum < 8) |
| 2225 | fence_reg = FENCE_REG_830_0 + (regnum * 4); |
| 2226 | else |
| 2227 | fence_reg = FENCE_REG_945_8 + ((regnum - 8) * 4); |
| 2228 | I915_WRITE(fence_reg, val); |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2229 | } |
| 2230 | |
| 2231 | static void i830_write_fence_reg(struct drm_i915_fence_reg *reg) |
| 2232 | { |
| 2233 | struct drm_gem_object *obj = reg->obj; |
| 2234 | struct drm_device *dev = obj->dev; |
| 2235 | drm_i915_private_t *dev_priv = dev->dev_private; |
Daniel Vetter | 23010e4 | 2010-03-08 13:35:02 +0100 | [diff] [blame] | 2236 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2237 | int regnum = obj_priv->fence_reg; |
| 2238 | uint32_t val; |
| 2239 | uint32_t pitch_val; |
Daniel Vetter | 8d7773a | 2009-03-29 14:09:41 +0200 | [diff] [blame] | 2240 | uint32_t fence_size_bits; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2241 | |
Daniel Vetter | 8d7773a | 2009-03-29 14:09:41 +0200 | [diff] [blame] | 2242 | if ((obj_priv->gtt_offset & ~I830_FENCE_START_MASK) || |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2243 | (obj_priv->gtt_offset & (obj->size - 1))) { |
Daniel Vetter | 8d7773a | 2009-03-29 14:09:41 +0200 | [diff] [blame] | 2244 | WARN(1, "%s: object 0x%08x not 512K or size aligned\n", |
Jesse Barnes | 0f973f2 | 2009-01-26 17:10:45 -0800 | [diff] [blame] | 2245 | __func__, obj_priv->gtt_offset); |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2246 | return; |
| 2247 | } |
| 2248 | |
Eric Anholt | e76a16d | 2009-05-26 17:44:56 -0700 | [diff] [blame] | 2249 | pitch_val = obj_priv->stride / 128; |
| 2250 | pitch_val = ffs(pitch_val) - 1; |
| 2251 | WARN_ON(pitch_val > I830_FENCE_MAX_PITCH_VAL); |
| 2252 | |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2253 | val = obj_priv->gtt_offset; |
| 2254 | if (obj_priv->tiling_mode == I915_TILING_Y) |
| 2255 | val |= 1 << I830_FENCE_TILING_Y_SHIFT; |
Daniel Vetter | 8d7773a | 2009-03-29 14:09:41 +0200 | [diff] [blame] | 2256 | fence_size_bits = I830_FENCE_SIZE_BITS(obj->size); |
| 2257 | WARN_ON(fence_size_bits & ~0x00000f00); |
| 2258 | val |= fence_size_bits; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2259 | val |= pitch_val << I830_FENCE_PITCH_SHIFT; |
| 2260 | val |= I830_FENCE_REG_VALID; |
| 2261 | |
| 2262 | I915_WRITE(FENCE_REG_830_0 + (regnum * 4), val); |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2263 | } |
| 2264 | |
Daniel Vetter | ae3db24 | 2010-02-19 11:51:58 +0100 | [diff] [blame] | 2265 | static int i915_find_fence_reg(struct drm_device *dev) |
| 2266 | { |
| 2267 | struct drm_i915_fence_reg *reg = NULL; |
| 2268 | struct drm_i915_gem_object *obj_priv = NULL; |
| 2269 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 2270 | struct drm_gem_object *obj = NULL; |
| 2271 | int i, avail, ret; |
| 2272 | |
| 2273 | /* First try to find a free reg */ |
| 2274 | avail = 0; |
| 2275 | for (i = dev_priv->fence_reg_start; i < dev_priv->num_fence_regs; i++) { |
| 2276 | reg = &dev_priv->fence_regs[i]; |
| 2277 | if (!reg->obj) |
| 2278 | return i; |
| 2279 | |
Daniel Vetter | 23010e4 | 2010-03-08 13:35:02 +0100 | [diff] [blame] | 2280 | obj_priv = to_intel_bo(reg->obj); |
Daniel Vetter | ae3db24 | 2010-02-19 11:51:58 +0100 | [diff] [blame] | 2281 | if (!obj_priv->pin_count) |
| 2282 | avail++; |
| 2283 | } |
| 2284 | |
| 2285 | if (avail == 0) |
| 2286 | return -ENOSPC; |
| 2287 | |
| 2288 | /* None available, try to steal one or wait for a user to finish */ |
| 2289 | i = I915_FENCE_REG_NONE; |
Daniel Vetter | 007cc8a | 2010-04-28 11:02:31 +0200 | [diff] [blame] | 2290 | list_for_each_entry(reg, &dev_priv->mm.fence_list, |
| 2291 | lru_list) { |
| 2292 | obj = reg->obj; |
| 2293 | obj_priv = to_intel_bo(obj); |
Daniel Vetter | ae3db24 | 2010-02-19 11:51:58 +0100 | [diff] [blame] | 2294 | |
| 2295 | if (obj_priv->pin_count) |
| 2296 | continue; |
| 2297 | |
| 2298 | /* found one! */ |
| 2299 | i = obj_priv->fence_reg; |
| 2300 | break; |
| 2301 | } |
| 2302 | |
| 2303 | BUG_ON(i == I915_FENCE_REG_NONE); |
| 2304 | |
| 2305 | /* We only have a reference on obj from the active list. put_fence_reg |
| 2306 | * might drop that one, causing a use-after-free in it. So hold a |
| 2307 | * private reference to obj like the other callers of put_fence_reg |
| 2308 | * (set_tiling ioctl) do. */ |
| 2309 | drm_gem_object_reference(obj); |
| 2310 | ret = i915_gem_object_put_fence_reg(obj); |
| 2311 | drm_gem_object_unreference(obj); |
| 2312 | if (ret != 0) |
| 2313 | return ret; |
| 2314 | |
| 2315 | return i; |
| 2316 | } |
| 2317 | |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2318 | /** |
| 2319 | * i915_gem_object_get_fence_reg - set up a fence reg for an object |
| 2320 | * @obj: object to map through a fence reg |
| 2321 | * |
| 2322 | * When mapping objects through the GTT, userspace wants to be able to write |
| 2323 | * to them without having to worry about swizzling if the object is tiled. |
| 2324 | * |
| 2325 | * This function walks the fence regs looking for a free one for @obj, |
| 2326 | * stealing one if it can't find any. |
| 2327 | * |
| 2328 | * It then sets up the reg based on the object's properties: address, pitch |
| 2329 | * and tiling format. |
| 2330 | */ |
Chris Wilson | 8c4b8c3 | 2009-06-17 22:08:52 +0100 | [diff] [blame] | 2331 | int |
| 2332 | i915_gem_object_get_fence_reg(struct drm_gem_object *obj) |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2333 | { |
| 2334 | struct drm_device *dev = obj->dev; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 2335 | struct drm_i915_private *dev_priv = dev->dev_private; |
Daniel Vetter | 23010e4 | 2010-03-08 13:35:02 +0100 | [diff] [blame] | 2336 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2337 | struct drm_i915_fence_reg *reg = NULL; |
Daniel Vetter | ae3db24 | 2010-02-19 11:51:58 +0100 | [diff] [blame] | 2338 | int ret; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2339 | |
Eric Anholt | a09ba7f | 2009-08-29 12:49:51 -0700 | [diff] [blame] | 2340 | /* Just update our place in the LRU if our fence is getting used. */ |
| 2341 | if (obj_priv->fence_reg != I915_FENCE_REG_NONE) { |
Daniel Vetter | 007cc8a | 2010-04-28 11:02:31 +0200 | [diff] [blame] | 2342 | reg = &dev_priv->fence_regs[obj_priv->fence_reg]; |
| 2343 | list_move_tail(®->lru_list, &dev_priv->mm.fence_list); |
Eric Anholt | a09ba7f | 2009-08-29 12:49:51 -0700 | [diff] [blame] | 2344 | return 0; |
| 2345 | } |
| 2346 | |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2347 | switch (obj_priv->tiling_mode) { |
| 2348 | case I915_TILING_NONE: |
| 2349 | WARN(1, "allocating a fence for non-tiled object?\n"); |
| 2350 | break; |
| 2351 | case I915_TILING_X: |
Jesse Barnes | 0f973f2 | 2009-01-26 17:10:45 -0800 | [diff] [blame] | 2352 | if (!obj_priv->stride) |
| 2353 | return -EINVAL; |
| 2354 | WARN((obj_priv->stride & (512 - 1)), |
| 2355 | "object 0x%08x is X tiled but has non-512B pitch\n", |
| 2356 | obj_priv->gtt_offset); |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2357 | break; |
| 2358 | case I915_TILING_Y: |
Jesse Barnes | 0f973f2 | 2009-01-26 17:10:45 -0800 | [diff] [blame] | 2359 | if (!obj_priv->stride) |
| 2360 | return -EINVAL; |
| 2361 | WARN((obj_priv->stride & (128 - 1)), |
| 2362 | "object 0x%08x is Y tiled but has non-128B pitch\n", |
| 2363 | obj_priv->gtt_offset); |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2364 | break; |
| 2365 | } |
| 2366 | |
Daniel Vetter | ae3db24 | 2010-02-19 11:51:58 +0100 | [diff] [blame] | 2367 | ret = i915_find_fence_reg(dev); |
| 2368 | if (ret < 0) |
| 2369 | return ret; |
Chris Wilson | fc7170b | 2009-02-11 14:26:46 +0000 | [diff] [blame] | 2370 | |
Daniel Vetter | ae3db24 | 2010-02-19 11:51:58 +0100 | [diff] [blame] | 2371 | obj_priv->fence_reg = ret; |
| 2372 | reg = &dev_priv->fence_regs[obj_priv->fence_reg]; |
Daniel Vetter | 007cc8a | 2010-04-28 11:02:31 +0200 | [diff] [blame] | 2373 | list_add_tail(®->lru_list, &dev_priv->mm.fence_list); |
Eric Anholt | a09ba7f | 2009-08-29 12:49:51 -0700 | [diff] [blame] | 2374 | |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2375 | reg->obj = obj; |
| 2376 | |
Eric Anholt | 4e901fd | 2009-10-26 16:44:17 -0700 | [diff] [blame] | 2377 | if (IS_GEN6(dev)) |
| 2378 | sandybridge_write_fence_reg(reg); |
| 2379 | else if (IS_I965G(dev)) |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2380 | i965_write_fence_reg(reg); |
| 2381 | else if (IS_I9XX(dev)) |
| 2382 | i915_write_fence_reg(reg); |
| 2383 | else |
| 2384 | i830_write_fence_reg(reg); |
Eric Anholt | d9ddcb9 | 2009-01-27 10:33:49 -0800 | [diff] [blame] | 2385 | |
Daniel Vetter | ae3db24 | 2010-02-19 11:51:58 +0100 | [diff] [blame] | 2386 | trace_i915_gem_object_get_fence(obj, obj_priv->fence_reg, |
| 2387 | obj_priv->tiling_mode); |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 2388 | |
Eric Anholt | d9ddcb9 | 2009-01-27 10:33:49 -0800 | [diff] [blame] | 2389 | return 0; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2390 | } |
| 2391 | |
| 2392 | /** |
| 2393 | * i915_gem_clear_fence_reg - clear out fence register info |
| 2394 | * @obj: object to clear |
| 2395 | * |
| 2396 | * Zeroes out the fence register itself and clears out the associated |
| 2397 | * data structures in dev_priv and obj_priv. |
| 2398 | */ |
| 2399 | static void |
| 2400 | i915_gem_clear_fence_reg(struct drm_gem_object *obj) |
| 2401 | { |
| 2402 | struct drm_device *dev = obj->dev; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 2403 | drm_i915_private_t *dev_priv = dev->dev_private; |
Daniel Vetter | 23010e4 | 2010-03-08 13:35:02 +0100 | [diff] [blame] | 2404 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
Daniel Vetter | 007cc8a | 2010-04-28 11:02:31 +0200 | [diff] [blame] | 2405 | struct drm_i915_fence_reg *reg = |
| 2406 | &dev_priv->fence_regs[obj_priv->fence_reg]; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2407 | |
Eric Anholt | 4e901fd | 2009-10-26 16:44:17 -0700 | [diff] [blame] | 2408 | if (IS_GEN6(dev)) { |
| 2409 | I915_WRITE64(FENCE_REG_SANDYBRIDGE_0 + |
| 2410 | (obj_priv->fence_reg * 8), 0); |
| 2411 | } else if (IS_I965G(dev)) { |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2412 | I915_WRITE64(FENCE_REG_965_0 + (obj_priv->fence_reg * 8), 0); |
Eric Anholt | 4e901fd | 2009-10-26 16:44:17 -0700 | [diff] [blame] | 2413 | } else { |
Eric Anholt | dc529a4 | 2009-03-10 22:34:49 -0700 | [diff] [blame] | 2414 | uint32_t fence_reg; |
| 2415 | |
| 2416 | if (obj_priv->fence_reg < 8) |
| 2417 | fence_reg = FENCE_REG_830_0 + obj_priv->fence_reg * 4; |
| 2418 | else |
| 2419 | fence_reg = FENCE_REG_945_8 + (obj_priv->fence_reg - |
| 2420 | 8) * 4; |
| 2421 | |
| 2422 | I915_WRITE(fence_reg, 0); |
| 2423 | } |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2424 | |
Daniel Vetter | 007cc8a | 2010-04-28 11:02:31 +0200 | [diff] [blame] | 2425 | reg->obj = NULL; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2426 | obj_priv->fence_reg = I915_FENCE_REG_NONE; |
Daniel Vetter | 007cc8a | 2010-04-28 11:02:31 +0200 | [diff] [blame] | 2427 | list_del_init(®->lru_list); |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2428 | } |
| 2429 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2430 | /** |
Chris Wilson | 52dc7d3 | 2009-06-06 09:46:01 +0100 | [diff] [blame] | 2431 | * i915_gem_object_put_fence_reg - waits on outstanding fenced access |
| 2432 | * to the buffer to finish, and then resets the fence register. |
| 2433 | * @obj: tiled object holding a fence register. |
| 2434 | * |
| 2435 | * Zeroes out the fence register itself and clears out the associated |
| 2436 | * data structures in dev_priv and obj_priv. |
| 2437 | */ |
| 2438 | int |
| 2439 | i915_gem_object_put_fence_reg(struct drm_gem_object *obj) |
| 2440 | { |
| 2441 | struct drm_device *dev = obj->dev; |
Daniel Vetter | 23010e4 | 2010-03-08 13:35:02 +0100 | [diff] [blame] | 2442 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
Chris Wilson | 52dc7d3 | 2009-06-06 09:46:01 +0100 | [diff] [blame] | 2443 | |
| 2444 | if (obj_priv->fence_reg == I915_FENCE_REG_NONE) |
| 2445 | return 0; |
| 2446 | |
Daniel Vetter | 10ae9bd | 2010-02-01 13:59:17 +0100 | [diff] [blame] | 2447 | /* If we've changed tiling, GTT-mappings of the object |
| 2448 | * need to re-fault to ensure that the correct fence register |
| 2449 | * setup is in place. |
| 2450 | */ |
| 2451 | i915_gem_release_mmap(obj); |
| 2452 | |
Chris Wilson | 52dc7d3 | 2009-06-06 09:46:01 +0100 | [diff] [blame] | 2453 | /* On the i915, GPU access to tiled buffers is via a fence, |
| 2454 | * therefore we must wait for any outstanding access to complete |
| 2455 | * before clearing the fence. |
| 2456 | */ |
| 2457 | if (!IS_I965G(dev)) { |
| 2458 | int ret; |
| 2459 | |
Chris Wilson | 2dafb1e | 2010-06-07 14:03:05 +0100 | [diff] [blame] | 2460 | ret = i915_gem_object_flush_gpu_write_domain(obj); |
| 2461 | if (ret != 0) |
| 2462 | return ret; |
| 2463 | |
Daniel Vetter | e35a41d | 2010-02-11 22:13:59 +0100 | [diff] [blame^] | 2464 | ret = i915_gem_object_wait_rendering(obj, true); |
Chris Wilson | 52dc7d3 | 2009-06-06 09:46:01 +0100 | [diff] [blame] | 2465 | if (ret != 0) |
| 2466 | return ret; |
| 2467 | } |
| 2468 | |
Daniel Vetter | 4a72661 | 2010-02-01 13:59:16 +0100 | [diff] [blame] | 2469 | i915_gem_object_flush_gtt_write_domain(obj); |
Chris Wilson | 52dc7d3 | 2009-06-06 09:46:01 +0100 | [diff] [blame] | 2470 | i915_gem_clear_fence_reg (obj); |
| 2471 | |
| 2472 | return 0; |
| 2473 | } |
| 2474 | |
| 2475 | /** |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2476 | * Finds free space in the GTT aperture and binds the object there. |
| 2477 | */ |
| 2478 | static int |
| 2479 | i915_gem_object_bind_to_gtt(struct drm_gem_object *obj, unsigned alignment) |
| 2480 | { |
| 2481 | struct drm_device *dev = obj->dev; |
| 2482 | drm_i915_private_t *dev_priv = dev->dev_private; |
Daniel Vetter | 23010e4 | 2010-03-08 13:35:02 +0100 | [diff] [blame] | 2483 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2484 | struct drm_mm_node *free_space; |
Chris Wilson | 4bdadb9 | 2010-01-27 13:36:32 +0000 | [diff] [blame] | 2485 | gfp_t gfpmask = __GFP_NORETRY | __GFP_NOWARN; |
Chris Wilson | 07f73f6 | 2009-09-14 16:50:30 +0100 | [diff] [blame] | 2486 | int ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2487 | |
Chris Wilson | bb6baf7 | 2009-09-22 14:24:13 +0100 | [diff] [blame] | 2488 | if (obj_priv->madv != I915_MADV_WILLNEED) { |
Chris Wilson | 3ef94da | 2009-09-14 16:50:29 +0100 | [diff] [blame] | 2489 | DRM_ERROR("Attempting to bind a purgeable object\n"); |
| 2490 | return -EINVAL; |
| 2491 | } |
| 2492 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2493 | if (alignment == 0) |
Jesse Barnes | 0f973f2 | 2009-01-26 17:10:45 -0800 | [diff] [blame] | 2494 | alignment = i915_gem_get_gtt_alignment(obj); |
Daniel Vetter | 8d7773a | 2009-03-29 14:09:41 +0200 | [diff] [blame] | 2495 | if (alignment & (i915_gem_get_gtt_alignment(obj) - 1)) { |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2496 | DRM_ERROR("Invalid object alignment requested %u\n", alignment); |
| 2497 | return -EINVAL; |
| 2498 | } |
| 2499 | |
Chris Wilson | 654fc60 | 2010-05-27 13:18:21 +0100 | [diff] [blame] | 2500 | /* If the object is bigger than the entire aperture, reject it early |
| 2501 | * before evicting everything in a vain attempt to find space. |
| 2502 | */ |
| 2503 | if (obj->size > dev->gtt_total) { |
| 2504 | DRM_ERROR("Attempting to bind an object larger than the aperture\n"); |
| 2505 | return -E2BIG; |
| 2506 | } |
| 2507 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2508 | search_free: |
| 2509 | free_space = drm_mm_search_free(&dev_priv->mm.gtt_space, |
| 2510 | obj->size, alignment, 0); |
| 2511 | if (free_space != NULL) { |
| 2512 | obj_priv->gtt_space = drm_mm_get_block(free_space, obj->size, |
| 2513 | alignment); |
Daniel Vetter | db3307a | 2010-07-02 15:02:12 +0100 | [diff] [blame] | 2514 | if (obj_priv->gtt_space != NULL) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2515 | obj_priv->gtt_offset = obj_priv->gtt_space->start; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2516 | } |
| 2517 | if (obj_priv->gtt_space == NULL) { |
| 2518 | /* If the gtt is empty and we're still having trouble |
| 2519 | * fitting our object in, we're out of memory. |
| 2520 | */ |
| 2521 | #if WATCH_LRU |
| 2522 | DRM_INFO("%s: GTT full, evicting something\n", __func__); |
| 2523 | #endif |
Daniel Vetter | 0108a3e | 2010-08-07 11:01:21 +0100 | [diff] [blame] | 2524 | ret = i915_gem_evict_something(dev, obj->size, alignment); |
Chris Wilson | 9731129 | 2009-09-21 00:22:34 +0100 | [diff] [blame] | 2525 | if (ret) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2526 | return ret; |
Chris Wilson | 9731129 | 2009-09-21 00:22:34 +0100 | [diff] [blame] | 2527 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2528 | goto search_free; |
| 2529 | } |
| 2530 | |
| 2531 | #if WATCH_BUF |
Krzysztof Halasa | cfd43c0 | 2009-06-20 00:31:28 +0200 | [diff] [blame] | 2532 | DRM_INFO("Binding object of size %zd at 0x%08x\n", |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2533 | obj->size, obj_priv->gtt_offset); |
| 2534 | #endif |
Chris Wilson | 4bdadb9 | 2010-01-27 13:36:32 +0000 | [diff] [blame] | 2535 | ret = i915_gem_object_get_pages(obj, gfpmask); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2536 | if (ret) { |
| 2537 | drm_mm_put_block(obj_priv->gtt_space); |
| 2538 | obj_priv->gtt_space = NULL; |
Chris Wilson | 07f73f6 | 2009-09-14 16:50:30 +0100 | [diff] [blame] | 2539 | |
| 2540 | if (ret == -ENOMEM) { |
| 2541 | /* first try to clear up some space from the GTT */ |
Daniel Vetter | 0108a3e | 2010-08-07 11:01:21 +0100 | [diff] [blame] | 2542 | ret = i915_gem_evict_something(dev, obj->size, |
| 2543 | alignment); |
Chris Wilson | 07f73f6 | 2009-09-14 16:50:30 +0100 | [diff] [blame] | 2544 | if (ret) { |
Chris Wilson | 07f73f6 | 2009-09-14 16:50:30 +0100 | [diff] [blame] | 2545 | /* now try to shrink everyone else */ |
Chris Wilson | 4bdadb9 | 2010-01-27 13:36:32 +0000 | [diff] [blame] | 2546 | if (gfpmask) { |
| 2547 | gfpmask = 0; |
| 2548 | goto search_free; |
Chris Wilson | 07f73f6 | 2009-09-14 16:50:30 +0100 | [diff] [blame] | 2549 | } |
| 2550 | |
| 2551 | return ret; |
| 2552 | } |
| 2553 | |
| 2554 | goto search_free; |
| 2555 | } |
| 2556 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2557 | return ret; |
| 2558 | } |
| 2559 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2560 | /* Create an AGP memory structure pointing at our pages, and bind it |
| 2561 | * into the GTT. |
| 2562 | */ |
| 2563 | obj_priv->agp_mem = drm_agp_bind_pages(dev, |
Eric Anholt | 856fa19 | 2009-03-19 14:10:50 -0700 | [diff] [blame] | 2564 | obj_priv->pages, |
Chris Wilson | 07f73f6 | 2009-09-14 16:50:30 +0100 | [diff] [blame] | 2565 | obj->size >> PAGE_SHIFT, |
Keith Packard | ba1eb1d | 2008-10-14 19:55:10 -0700 | [diff] [blame] | 2566 | obj_priv->gtt_offset, |
| 2567 | obj_priv->agp_type); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2568 | if (obj_priv->agp_mem == NULL) { |
Eric Anholt | 856fa19 | 2009-03-19 14:10:50 -0700 | [diff] [blame] | 2569 | i915_gem_object_put_pages(obj); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2570 | drm_mm_put_block(obj_priv->gtt_space); |
| 2571 | obj_priv->gtt_space = NULL; |
Chris Wilson | 07f73f6 | 2009-09-14 16:50:30 +0100 | [diff] [blame] | 2572 | |
Daniel Vetter | 0108a3e | 2010-08-07 11:01:21 +0100 | [diff] [blame] | 2573 | ret = i915_gem_evict_something(dev, obj->size, alignment); |
Chris Wilson | 9731129 | 2009-09-21 00:22:34 +0100 | [diff] [blame] | 2574 | if (ret) |
Chris Wilson | 07f73f6 | 2009-09-14 16:50:30 +0100 | [diff] [blame] | 2575 | return ret; |
Chris Wilson | 07f73f6 | 2009-09-14 16:50:30 +0100 | [diff] [blame] | 2576 | |
| 2577 | goto search_free; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2578 | } |
| 2579 | atomic_inc(&dev->gtt_count); |
| 2580 | atomic_add(obj->size, &dev->gtt_memory); |
| 2581 | |
Chris Wilson | bf1a109 | 2010-08-07 11:01:20 +0100 | [diff] [blame] | 2582 | /* keep track of bounds object by adding it to the inactive list */ |
| 2583 | list_add_tail(&obj_priv->list, &dev_priv->mm.inactive_list); |
| 2584 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2585 | /* Assert that the object is not currently in any GPU domain. As it |
| 2586 | * wasn't in the GTT, there shouldn't be any way it could have been in |
| 2587 | * a GPU cache |
| 2588 | */ |
Chris Wilson | 21d509e | 2009-06-06 09:46:02 +0100 | [diff] [blame] | 2589 | BUG_ON(obj->read_domains & I915_GEM_GPU_DOMAINS); |
| 2590 | BUG_ON(obj->write_domain & I915_GEM_GPU_DOMAINS); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2591 | |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 2592 | trace_i915_gem_object_bind(obj, obj_priv->gtt_offset); |
| 2593 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2594 | return 0; |
| 2595 | } |
| 2596 | |
| 2597 | void |
| 2598 | i915_gem_clflush_object(struct drm_gem_object *obj) |
| 2599 | { |
Daniel Vetter | 23010e4 | 2010-03-08 13:35:02 +0100 | [diff] [blame] | 2600 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2601 | |
| 2602 | /* If we don't have a page list set up, then we're not pinned |
| 2603 | * to GPU, and we can ignore the cache flush because it'll happen |
| 2604 | * again at bind time. |
| 2605 | */ |
Eric Anholt | 856fa19 | 2009-03-19 14:10:50 -0700 | [diff] [blame] | 2606 | if (obj_priv->pages == NULL) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2607 | return; |
| 2608 | |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 2609 | trace_i915_gem_object_clflush(obj); |
Eric Anholt | cfa16a0 | 2009-05-26 18:46:16 -0700 | [diff] [blame] | 2610 | |
Eric Anholt | 856fa19 | 2009-03-19 14:10:50 -0700 | [diff] [blame] | 2611 | drm_clflush_pages(obj_priv->pages, obj->size / PAGE_SIZE); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2612 | } |
| 2613 | |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2614 | /** Flushes any GPU write domain for the object if it's dirty. */ |
Chris Wilson | 2dafb1e | 2010-06-07 14:03:05 +0100 | [diff] [blame] | 2615 | static int |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2616 | i915_gem_object_flush_gpu_write_domain(struct drm_gem_object *obj) |
| 2617 | { |
| 2618 | struct drm_device *dev = obj->dev; |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 2619 | uint32_t old_write_domain; |
Zou Nan hai | 852835f | 2010-05-21 09:08:56 +0800 | [diff] [blame] | 2620 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2621 | |
| 2622 | if ((obj->write_domain & I915_GEM_GPU_DOMAINS) == 0) |
Chris Wilson | 2dafb1e | 2010-06-07 14:03:05 +0100 | [diff] [blame] | 2623 | return 0; |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2624 | |
| 2625 | /* Queue the GPU write cache flushing we need. */ |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 2626 | old_write_domain = obj->write_domain; |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2627 | i915_gem_flush(dev, 0, obj->write_domain); |
Chris Wilson | 2dafb1e | 2010-06-07 14:03:05 +0100 | [diff] [blame] | 2628 | if (i915_add_request(dev, NULL, obj->write_domain, obj_priv->ring) == 0) |
| 2629 | return -ENOMEM; |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 2630 | |
| 2631 | trace_i915_gem_object_change_domain(obj, |
| 2632 | obj->read_domains, |
| 2633 | old_write_domain); |
Chris Wilson | 2dafb1e | 2010-06-07 14:03:05 +0100 | [diff] [blame] | 2634 | return 0; |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2635 | } |
| 2636 | |
| 2637 | /** Flushes the GTT write domain for the object if it's dirty. */ |
| 2638 | static void |
| 2639 | i915_gem_object_flush_gtt_write_domain(struct drm_gem_object *obj) |
| 2640 | { |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 2641 | uint32_t old_write_domain; |
| 2642 | |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2643 | if (obj->write_domain != I915_GEM_DOMAIN_GTT) |
| 2644 | return; |
| 2645 | |
| 2646 | /* No actual flushing is required for the GTT write domain. Writes |
| 2647 | * to it immediately go to main memory as far as we know, so there's |
| 2648 | * no chipset flush. It also doesn't land in render cache. |
| 2649 | */ |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 2650 | old_write_domain = obj->write_domain; |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2651 | obj->write_domain = 0; |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 2652 | |
| 2653 | trace_i915_gem_object_change_domain(obj, |
| 2654 | obj->read_domains, |
| 2655 | old_write_domain); |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2656 | } |
| 2657 | |
| 2658 | /** Flushes the CPU write domain for the object if it's dirty. */ |
| 2659 | static void |
| 2660 | i915_gem_object_flush_cpu_write_domain(struct drm_gem_object *obj) |
| 2661 | { |
| 2662 | struct drm_device *dev = obj->dev; |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 2663 | uint32_t old_write_domain; |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2664 | |
| 2665 | if (obj->write_domain != I915_GEM_DOMAIN_CPU) |
| 2666 | return; |
| 2667 | |
| 2668 | i915_gem_clflush_object(obj); |
| 2669 | drm_agp_chipset_flush(dev); |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 2670 | old_write_domain = obj->write_domain; |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2671 | obj->write_domain = 0; |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 2672 | |
| 2673 | trace_i915_gem_object_change_domain(obj, |
| 2674 | obj->read_domains, |
| 2675 | old_write_domain); |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2676 | } |
| 2677 | |
Chris Wilson | 2dafb1e | 2010-06-07 14:03:05 +0100 | [diff] [blame] | 2678 | int |
Kristian Høgsberg | 6b95a20 | 2009-11-18 11:25:18 -0500 | [diff] [blame] | 2679 | i915_gem_object_flush_write_domain(struct drm_gem_object *obj) |
| 2680 | { |
Chris Wilson | 2dafb1e | 2010-06-07 14:03:05 +0100 | [diff] [blame] | 2681 | int ret = 0; |
| 2682 | |
Kristian Høgsberg | 6b95a20 | 2009-11-18 11:25:18 -0500 | [diff] [blame] | 2683 | switch (obj->write_domain) { |
| 2684 | case I915_GEM_DOMAIN_GTT: |
| 2685 | i915_gem_object_flush_gtt_write_domain(obj); |
| 2686 | break; |
| 2687 | case I915_GEM_DOMAIN_CPU: |
| 2688 | i915_gem_object_flush_cpu_write_domain(obj); |
| 2689 | break; |
| 2690 | default: |
Chris Wilson | 2dafb1e | 2010-06-07 14:03:05 +0100 | [diff] [blame] | 2691 | ret = i915_gem_object_flush_gpu_write_domain(obj); |
Kristian Høgsberg | 6b95a20 | 2009-11-18 11:25:18 -0500 | [diff] [blame] | 2692 | break; |
| 2693 | } |
Chris Wilson | 2dafb1e | 2010-06-07 14:03:05 +0100 | [diff] [blame] | 2694 | |
| 2695 | return ret; |
Kristian Høgsberg | 6b95a20 | 2009-11-18 11:25:18 -0500 | [diff] [blame] | 2696 | } |
| 2697 | |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 2698 | /** |
| 2699 | * Moves a single object to the GTT read, and possibly write domain. |
| 2700 | * |
| 2701 | * This function returns when the move is complete, including waiting on |
| 2702 | * flushes to occur. |
| 2703 | */ |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 2704 | int |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 2705 | i915_gem_object_set_to_gtt_domain(struct drm_gem_object *obj, int write) |
| 2706 | { |
Daniel Vetter | 23010e4 | 2010-03-08 13:35:02 +0100 | [diff] [blame] | 2707 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 2708 | uint32_t old_write_domain, old_read_domains; |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2709 | int ret; |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 2710 | |
Eric Anholt | 0235439 | 2008-11-26 13:58:13 -0800 | [diff] [blame] | 2711 | /* Not valid to be called on unbound objects. */ |
| 2712 | if (obj_priv->gtt_space == NULL) |
| 2713 | return -EINVAL; |
| 2714 | |
Chris Wilson | 2dafb1e | 2010-06-07 14:03:05 +0100 | [diff] [blame] | 2715 | ret = i915_gem_object_flush_gpu_write_domain(obj); |
| 2716 | if (ret != 0) |
| 2717 | return ret; |
| 2718 | |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 2719 | /* Wait on any GPU rendering and flushing to occur. */ |
Daniel Vetter | e35a41d | 2010-02-11 22:13:59 +0100 | [diff] [blame^] | 2720 | ret = i915_gem_object_wait_rendering(obj, true); |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2721 | if (ret != 0) |
| 2722 | return ret; |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 2723 | |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 2724 | old_write_domain = obj->write_domain; |
| 2725 | old_read_domains = obj->read_domains; |
| 2726 | |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 2727 | /* If we're writing through the GTT domain, then CPU and GPU caches |
| 2728 | * will need to be invalidated at next use. |
| 2729 | */ |
| 2730 | if (write) |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2731 | obj->read_domains &= I915_GEM_DOMAIN_GTT; |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 2732 | |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2733 | i915_gem_object_flush_cpu_write_domain(obj); |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 2734 | |
| 2735 | /* It should now be out of any other write domains, and we can update |
| 2736 | * the domain values for our changes. |
| 2737 | */ |
| 2738 | BUG_ON((obj->write_domain & ~I915_GEM_DOMAIN_GTT) != 0); |
| 2739 | obj->read_domains |= I915_GEM_DOMAIN_GTT; |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2740 | if (write) { |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 2741 | obj->write_domain = I915_GEM_DOMAIN_GTT; |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2742 | obj_priv->dirty = 1; |
| 2743 | } |
| 2744 | |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 2745 | trace_i915_gem_object_change_domain(obj, |
| 2746 | old_read_domains, |
| 2747 | old_write_domain); |
| 2748 | |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2749 | return 0; |
| 2750 | } |
| 2751 | |
Zhenyu Wang | b9241ea | 2009-11-25 13:09:39 +0800 | [diff] [blame] | 2752 | /* |
| 2753 | * Prepare buffer for display plane. Use uninterruptible for possible flush |
| 2754 | * wait, as in modesetting process we're not supposed to be interrupted. |
| 2755 | */ |
| 2756 | int |
| 2757 | i915_gem_object_set_to_display_plane(struct drm_gem_object *obj) |
| 2758 | { |
Daniel Vetter | 23010e4 | 2010-03-08 13:35:02 +0100 | [diff] [blame] | 2759 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
Zhenyu Wang | b9241ea | 2009-11-25 13:09:39 +0800 | [diff] [blame] | 2760 | uint32_t old_write_domain, old_read_domains; |
| 2761 | int ret; |
| 2762 | |
| 2763 | /* Not valid to be called on unbound objects. */ |
| 2764 | if (obj_priv->gtt_space == NULL) |
| 2765 | return -EINVAL; |
| 2766 | |
Chris Wilson | 2dafb1e | 2010-06-07 14:03:05 +0100 | [diff] [blame] | 2767 | ret = i915_gem_object_flush_gpu_write_domain(obj); |
| 2768 | if (ret) |
| 2769 | return ret; |
Zhenyu Wang | b9241ea | 2009-11-25 13:09:39 +0800 | [diff] [blame] | 2770 | |
| 2771 | /* Wait on any GPU rendering and flushing to occur. */ |
Daniel Vetter | e35a41d | 2010-02-11 22:13:59 +0100 | [diff] [blame^] | 2772 | ret = i915_gem_object_wait_rendering(obj, false); |
| 2773 | if (ret != 0) |
| 2774 | return ret; |
Zhenyu Wang | b9241ea | 2009-11-25 13:09:39 +0800 | [diff] [blame] | 2775 | |
Chris Wilson | b118c1e | 2010-05-27 13:18:14 +0100 | [diff] [blame] | 2776 | i915_gem_object_flush_cpu_write_domain(obj); |
| 2777 | |
Zhenyu Wang | b9241ea | 2009-11-25 13:09:39 +0800 | [diff] [blame] | 2778 | old_write_domain = obj->write_domain; |
| 2779 | old_read_domains = obj->read_domains; |
| 2780 | |
Zhenyu Wang | b9241ea | 2009-11-25 13:09:39 +0800 | [diff] [blame] | 2781 | /* It should now be out of any other write domains, and we can update |
| 2782 | * the domain values for our changes. |
| 2783 | */ |
| 2784 | BUG_ON((obj->write_domain & ~I915_GEM_DOMAIN_GTT) != 0); |
Chris Wilson | b118c1e | 2010-05-27 13:18:14 +0100 | [diff] [blame] | 2785 | obj->read_domains = I915_GEM_DOMAIN_GTT; |
Zhenyu Wang | b9241ea | 2009-11-25 13:09:39 +0800 | [diff] [blame] | 2786 | obj->write_domain = I915_GEM_DOMAIN_GTT; |
| 2787 | obj_priv->dirty = 1; |
| 2788 | |
| 2789 | trace_i915_gem_object_change_domain(obj, |
| 2790 | old_read_domains, |
| 2791 | old_write_domain); |
| 2792 | |
| 2793 | return 0; |
| 2794 | } |
| 2795 | |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2796 | /** |
| 2797 | * Moves a single object to the CPU read, and possibly write domain. |
| 2798 | * |
| 2799 | * This function returns when the move is complete, including waiting on |
| 2800 | * flushes to occur. |
| 2801 | */ |
| 2802 | static int |
| 2803 | i915_gem_object_set_to_cpu_domain(struct drm_gem_object *obj, int write) |
| 2804 | { |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 2805 | uint32_t old_write_domain, old_read_domains; |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2806 | int ret; |
| 2807 | |
Chris Wilson | 2dafb1e | 2010-06-07 14:03:05 +0100 | [diff] [blame] | 2808 | ret = i915_gem_object_flush_gpu_write_domain(obj); |
| 2809 | if (ret) |
| 2810 | return ret; |
| 2811 | |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2812 | /* Wait on any GPU rendering and flushing to occur. */ |
Daniel Vetter | e35a41d | 2010-02-11 22:13:59 +0100 | [diff] [blame^] | 2813 | ret = i915_gem_object_wait_rendering(obj, true); |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2814 | if (ret != 0) |
| 2815 | return ret; |
| 2816 | |
| 2817 | i915_gem_object_flush_gtt_write_domain(obj); |
| 2818 | |
| 2819 | /* If we have a partially-valid cache of the object in the CPU, |
| 2820 | * finish invalidating it and free the per-page flags. |
| 2821 | */ |
| 2822 | i915_gem_object_set_to_full_cpu_read_domain(obj); |
| 2823 | |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 2824 | old_write_domain = obj->write_domain; |
| 2825 | old_read_domains = obj->read_domains; |
| 2826 | |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2827 | /* Flush the CPU cache if it's still invalid. */ |
| 2828 | if ((obj->read_domains & I915_GEM_DOMAIN_CPU) == 0) { |
| 2829 | i915_gem_clflush_object(obj); |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2830 | |
| 2831 | obj->read_domains |= I915_GEM_DOMAIN_CPU; |
| 2832 | } |
| 2833 | |
| 2834 | /* It should now be out of any other write domains, and we can update |
| 2835 | * the domain values for our changes. |
| 2836 | */ |
| 2837 | BUG_ON((obj->write_domain & ~I915_GEM_DOMAIN_CPU) != 0); |
| 2838 | |
| 2839 | /* If we're writing through the CPU, then the GPU read domains will |
| 2840 | * need to be invalidated at next use. |
| 2841 | */ |
| 2842 | if (write) { |
| 2843 | obj->read_domains &= I915_GEM_DOMAIN_CPU; |
| 2844 | obj->write_domain = I915_GEM_DOMAIN_CPU; |
| 2845 | } |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 2846 | |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 2847 | trace_i915_gem_object_change_domain(obj, |
| 2848 | old_read_domains, |
| 2849 | old_write_domain); |
| 2850 | |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 2851 | return 0; |
| 2852 | } |
| 2853 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2854 | /* |
| 2855 | * Set the next domain for the specified object. This |
| 2856 | * may not actually perform the necessary flushing/invaliding though, |
| 2857 | * as that may want to be batched with other set_domain operations |
| 2858 | * |
| 2859 | * This is (we hope) the only really tricky part of gem. The goal |
| 2860 | * is fairly simple -- track which caches hold bits of the object |
| 2861 | * and make sure they remain coherent. A few concrete examples may |
| 2862 | * help to explain how it works. For shorthand, we use the notation |
| 2863 | * (read_domains, write_domain), e.g. (CPU, CPU) to indicate the |
| 2864 | * a pair of read and write domain masks. |
| 2865 | * |
| 2866 | * Case 1: the batch buffer |
| 2867 | * |
| 2868 | * 1. Allocated |
| 2869 | * 2. Written by CPU |
| 2870 | * 3. Mapped to GTT |
| 2871 | * 4. Read by GPU |
| 2872 | * 5. Unmapped from GTT |
| 2873 | * 6. Freed |
| 2874 | * |
| 2875 | * Let's take these a step at a time |
| 2876 | * |
| 2877 | * 1. Allocated |
| 2878 | * Pages allocated from the kernel may still have |
| 2879 | * cache contents, so we set them to (CPU, CPU) always. |
| 2880 | * 2. Written by CPU (using pwrite) |
| 2881 | * The pwrite function calls set_domain (CPU, CPU) and |
| 2882 | * this function does nothing (as nothing changes) |
| 2883 | * 3. Mapped by GTT |
| 2884 | * This function asserts that the object is not |
| 2885 | * currently in any GPU-based read or write domains |
| 2886 | * 4. Read by GPU |
| 2887 | * i915_gem_execbuffer calls set_domain (COMMAND, 0). |
| 2888 | * As write_domain is zero, this function adds in the |
| 2889 | * current read domains (CPU+COMMAND, 0). |
| 2890 | * flush_domains is set to CPU. |
| 2891 | * invalidate_domains is set to COMMAND |
| 2892 | * clflush is run to get data out of the CPU caches |
| 2893 | * then i915_dev_set_domain calls i915_gem_flush to |
| 2894 | * emit an MI_FLUSH and drm_agp_chipset_flush |
| 2895 | * 5. Unmapped from GTT |
| 2896 | * i915_gem_object_unbind calls set_domain (CPU, CPU) |
| 2897 | * flush_domains and invalidate_domains end up both zero |
| 2898 | * so no flushing/invalidating happens |
| 2899 | * 6. Freed |
| 2900 | * yay, done |
| 2901 | * |
| 2902 | * Case 2: The shared render buffer |
| 2903 | * |
| 2904 | * 1. Allocated |
| 2905 | * 2. Mapped to GTT |
| 2906 | * 3. Read/written by GPU |
| 2907 | * 4. set_domain to (CPU,CPU) |
| 2908 | * 5. Read/written by CPU |
| 2909 | * 6. Read/written by GPU |
| 2910 | * |
| 2911 | * 1. Allocated |
| 2912 | * Same as last example, (CPU, CPU) |
| 2913 | * 2. Mapped to GTT |
| 2914 | * Nothing changes (assertions find that it is not in the GPU) |
| 2915 | * 3. Read/written by GPU |
| 2916 | * execbuffer calls set_domain (RENDER, RENDER) |
| 2917 | * flush_domains gets CPU |
| 2918 | * invalidate_domains gets GPU |
| 2919 | * clflush (obj) |
| 2920 | * MI_FLUSH and drm_agp_chipset_flush |
| 2921 | * 4. set_domain (CPU, CPU) |
| 2922 | * flush_domains gets GPU |
| 2923 | * invalidate_domains gets CPU |
| 2924 | * wait_rendering (obj) to make sure all drawing is complete. |
| 2925 | * This will include an MI_FLUSH to get the data from GPU |
| 2926 | * to memory |
| 2927 | * clflush (obj) to invalidate the CPU cache |
| 2928 | * Another MI_FLUSH in i915_gem_flush (eliminate this somehow?) |
| 2929 | * 5. Read/written by CPU |
| 2930 | * cache lines are loaded and dirtied |
| 2931 | * 6. Read written by GPU |
| 2932 | * Same as last GPU access |
| 2933 | * |
| 2934 | * Case 3: The constant buffer |
| 2935 | * |
| 2936 | * 1. Allocated |
| 2937 | * 2. Written by CPU |
| 2938 | * 3. Read by GPU |
| 2939 | * 4. Updated (written) by CPU again |
| 2940 | * 5. Read by GPU |
| 2941 | * |
| 2942 | * 1. Allocated |
| 2943 | * (CPU, CPU) |
| 2944 | * 2. Written by CPU |
| 2945 | * (CPU, CPU) |
| 2946 | * 3. Read by GPU |
| 2947 | * (CPU+RENDER, 0) |
| 2948 | * flush_domains = CPU |
| 2949 | * invalidate_domains = RENDER |
| 2950 | * clflush (obj) |
| 2951 | * MI_FLUSH |
| 2952 | * drm_agp_chipset_flush |
| 2953 | * 4. Updated (written) by CPU again |
| 2954 | * (CPU, CPU) |
| 2955 | * flush_domains = 0 (no previous write domain) |
| 2956 | * invalidate_domains = 0 (no new read domains) |
| 2957 | * 5. Read by GPU |
| 2958 | * (CPU+RENDER, 0) |
| 2959 | * flush_domains = CPU |
| 2960 | * invalidate_domains = RENDER |
| 2961 | * clflush (obj) |
| 2962 | * MI_FLUSH |
| 2963 | * drm_agp_chipset_flush |
| 2964 | */ |
Keith Packard | c0d9082 | 2008-11-20 23:11:08 -0800 | [diff] [blame] | 2965 | static void |
Eric Anholt | 8b0e378 | 2009-02-19 14:40:50 -0800 | [diff] [blame] | 2966 | i915_gem_object_set_to_gpu_domain(struct drm_gem_object *obj) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2967 | { |
| 2968 | struct drm_device *dev = obj->dev; |
Chris Wilson | 88f356b | 2010-08-04 13:55:32 +0100 | [diff] [blame] | 2969 | drm_i915_private_t *dev_priv = dev->dev_private; |
Daniel Vetter | 23010e4 | 2010-03-08 13:35:02 +0100 | [diff] [blame] | 2970 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2971 | uint32_t invalidate_domains = 0; |
| 2972 | uint32_t flush_domains = 0; |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 2973 | uint32_t old_read_domains; |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2974 | |
Eric Anholt | 8b0e378 | 2009-02-19 14:40:50 -0800 | [diff] [blame] | 2975 | BUG_ON(obj->pending_read_domains & I915_GEM_DOMAIN_CPU); |
| 2976 | BUG_ON(obj->pending_write_domain == I915_GEM_DOMAIN_CPU); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2977 | |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 2978 | intel_mark_busy(dev, obj); |
| 2979 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2980 | #if WATCH_BUF |
| 2981 | DRM_INFO("%s: object %p read %08x -> %08x write %08x -> %08x\n", |
| 2982 | __func__, obj, |
Eric Anholt | 8b0e378 | 2009-02-19 14:40:50 -0800 | [diff] [blame] | 2983 | obj->read_domains, obj->pending_read_domains, |
| 2984 | obj->write_domain, obj->pending_write_domain); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2985 | #endif |
| 2986 | /* |
| 2987 | * If the object isn't moving to a new write domain, |
| 2988 | * let the object stay in multiple read domains |
| 2989 | */ |
Eric Anholt | 8b0e378 | 2009-02-19 14:40:50 -0800 | [diff] [blame] | 2990 | if (obj->pending_write_domain == 0) |
| 2991 | obj->pending_read_domains |= obj->read_domains; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2992 | else |
| 2993 | obj_priv->dirty = 1; |
| 2994 | |
| 2995 | /* |
| 2996 | * Flush the current write domain if |
| 2997 | * the new read domains don't match. Invalidate |
| 2998 | * any read domains which differ from the old |
| 2999 | * write domain |
| 3000 | */ |
Eric Anholt | 8b0e378 | 2009-02-19 14:40:50 -0800 | [diff] [blame] | 3001 | if (obj->write_domain && |
| 3002 | obj->write_domain != obj->pending_read_domains) { |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3003 | flush_domains |= obj->write_domain; |
Eric Anholt | 8b0e378 | 2009-02-19 14:40:50 -0800 | [diff] [blame] | 3004 | invalidate_domains |= |
| 3005 | obj->pending_read_domains & ~obj->write_domain; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3006 | } |
| 3007 | /* |
| 3008 | * Invalidate any read caches which may have |
| 3009 | * stale data. That is, any new read domains. |
| 3010 | */ |
Eric Anholt | 8b0e378 | 2009-02-19 14:40:50 -0800 | [diff] [blame] | 3011 | invalidate_domains |= obj->pending_read_domains & ~obj->read_domains; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3012 | if ((flush_domains | invalidate_domains) & I915_GEM_DOMAIN_CPU) { |
| 3013 | #if WATCH_BUF |
| 3014 | DRM_INFO("%s: CPU domain flush %08x invalidate %08x\n", |
| 3015 | __func__, flush_domains, invalidate_domains); |
| 3016 | #endif |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3017 | i915_gem_clflush_object(obj); |
| 3018 | } |
| 3019 | |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 3020 | old_read_domains = obj->read_domains; |
| 3021 | |
Eric Anholt | efbeed9 | 2009-02-19 14:54:51 -0800 | [diff] [blame] | 3022 | /* The actual obj->write_domain will be updated with |
| 3023 | * pending_write_domain after we emit the accumulated flush for all |
| 3024 | * of our domain changes in execbuffers (which clears objects' |
| 3025 | * write_domains). So if we have a current write domain that we |
| 3026 | * aren't changing, set pending_write_domain to that. |
| 3027 | */ |
| 3028 | if (flush_domains == 0 && obj->pending_write_domain == 0) |
| 3029 | obj->pending_write_domain = obj->write_domain; |
Eric Anholt | 8b0e378 | 2009-02-19 14:40:50 -0800 | [diff] [blame] | 3030 | obj->read_domains = obj->pending_read_domains; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3031 | |
Chris Wilson | 88f356b | 2010-08-04 13:55:32 +0100 | [diff] [blame] | 3032 | if (flush_domains & I915_GEM_GPU_DOMAINS) { |
| 3033 | if (obj_priv->ring == &dev_priv->render_ring) |
| 3034 | dev_priv->flush_rings |= FLUSH_RENDER_RING; |
| 3035 | else if (obj_priv->ring == &dev_priv->bsd_ring) |
| 3036 | dev_priv->flush_rings |= FLUSH_BSD_RING; |
| 3037 | } |
| 3038 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3039 | dev->invalidate_domains |= invalidate_domains; |
| 3040 | dev->flush_domains |= flush_domains; |
| 3041 | #if WATCH_BUF |
| 3042 | DRM_INFO("%s: read %08x write %08x invalidate %08x flush %08x\n", |
| 3043 | __func__, |
| 3044 | obj->read_domains, obj->write_domain, |
| 3045 | dev->invalidate_domains, dev->flush_domains); |
| 3046 | #endif |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 3047 | |
| 3048 | trace_i915_gem_object_change_domain(obj, |
| 3049 | old_read_domains, |
| 3050 | obj->write_domain); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3051 | } |
| 3052 | |
| 3053 | /** |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3054 | * Moves the object from a partially CPU read to a full one. |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3055 | * |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3056 | * Note that this only resolves i915_gem_object_set_cpu_read_domain_range(), |
| 3057 | * and doesn't handle transitioning from !(read_domains & I915_GEM_DOMAIN_CPU). |
| 3058 | */ |
| 3059 | static void |
| 3060 | i915_gem_object_set_to_full_cpu_read_domain(struct drm_gem_object *obj) |
| 3061 | { |
Daniel Vetter | 23010e4 | 2010-03-08 13:35:02 +0100 | [diff] [blame] | 3062 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3063 | |
| 3064 | if (!obj_priv->page_cpu_valid) |
| 3065 | return; |
| 3066 | |
| 3067 | /* If we're partially in the CPU read domain, finish moving it in. |
| 3068 | */ |
| 3069 | if (obj->read_domains & I915_GEM_DOMAIN_CPU) { |
| 3070 | int i; |
| 3071 | |
| 3072 | for (i = 0; i <= (obj->size - 1) / PAGE_SIZE; i++) { |
| 3073 | if (obj_priv->page_cpu_valid[i]) |
| 3074 | continue; |
Eric Anholt | 856fa19 | 2009-03-19 14:10:50 -0700 | [diff] [blame] | 3075 | drm_clflush_pages(obj_priv->pages + i, 1); |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3076 | } |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3077 | } |
| 3078 | |
| 3079 | /* Free the page_cpu_valid mappings which are now stale, whether |
| 3080 | * or not we've got I915_GEM_DOMAIN_CPU. |
| 3081 | */ |
Eric Anholt | 9a298b2 | 2009-03-24 12:23:04 -0700 | [diff] [blame] | 3082 | kfree(obj_priv->page_cpu_valid); |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3083 | obj_priv->page_cpu_valid = NULL; |
| 3084 | } |
| 3085 | |
| 3086 | /** |
| 3087 | * Set the CPU read domain on a range of the object. |
| 3088 | * |
| 3089 | * The object ends up with I915_GEM_DOMAIN_CPU in its read flags although it's |
| 3090 | * not entirely valid. The page_cpu_valid member of the object flags which |
| 3091 | * pages have been flushed, and will be respected by |
| 3092 | * i915_gem_object_set_to_cpu_domain() if it's called on to get a valid mapping |
| 3093 | * of the whole object. |
| 3094 | * |
| 3095 | * This function returns when the move is complete, including waiting on |
| 3096 | * flushes to occur. |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3097 | */ |
| 3098 | static int |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3099 | i915_gem_object_set_cpu_read_domain_range(struct drm_gem_object *obj, |
| 3100 | uint64_t offset, uint64_t size) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3101 | { |
Daniel Vetter | 23010e4 | 2010-03-08 13:35:02 +0100 | [diff] [blame] | 3102 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 3103 | uint32_t old_read_domains; |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3104 | int i, ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3105 | |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3106 | if (offset == 0 && size == obj->size) |
| 3107 | return i915_gem_object_set_to_cpu_domain(obj, 0); |
| 3108 | |
Chris Wilson | 2dafb1e | 2010-06-07 14:03:05 +0100 | [diff] [blame] | 3109 | ret = i915_gem_object_flush_gpu_write_domain(obj); |
| 3110 | if (ret) |
| 3111 | return ret; |
| 3112 | |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3113 | /* Wait on any GPU rendering and flushing to occur. */ |
Daniel Vetter | e35a41d | 2010-02-11 22:13:59 +0100 | [diff] [blame^] | 3114 | ret = i915_gem_object_wait_rendering(obj, true); |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3115 | if (ret != 0) |
| 3116 | return ret; |
| 3117 | i915_gem_object_flush_gtt_write_domain(obj); |
| 3118 | |
| 3119 | /* If we're already fully in the CPU read domain, we're done. */ |
| 3120 | if (obj_priv->page_cpu_valid == NULL && |
| 3121 | (obj->read_domains & I915_GEM_DOMAIN_CPU) != 0) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3122 | return 0; |
| 3123 | |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3124 | /* Otherwise, create/clear the per-page CPU read domain flag if we're |
| 3125 | * newly adding I915_GEM_DOMAIN_CPU |
| 3126 | */ |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3127 | if (obj_priv->page_cpu_valid == NULL) { |
Eric Anholt | 9a298b2 | 2009-03-24 12:23:04 -0700 | [diff] [blame] | 3128 | obj_priv->page_cpu_valid = kzalloc(obj->size / PAGE_SIZE, |
| 3129 | GFP_KERNEL); |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3130 | if (obj_priv->page_cpu_valid == NULL) |
| 3131 | return -ENOMEM; |
| 3132 | } else if ((obj->read_domains & I915_GEM_DOMAIN_CPU) == 0) |
| 3133 | memset(obj_priv->page_cpu_valid, 0, obj->size / PAGE_SIZE); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3134 | |
| 3135 | /* Flush the cache on any pages that are still invalid from the CPU's |
| 3136 | * perspective. |
| 3137 | */ |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3138 | for (i = offset / PAGE_SIZE; i <= (offset + size - 1) / PAGE_SIZE; |
| 3139 | i++) { |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3140 | if (obj_priv->page_cpu_valid[i]) |
| 3141 | continue; |
| 3142 | |
Eric Anholt | 856fa19 | 2009-03-19 14:10:50 -0700 | [diff] [blame] | 3143 | drm_clflush_pages(obj_priv->pages + i, 1); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3144 | |
| 3145 | obj_priv->page_cpu_valid[i] = 1; |
| 3146 | } |
| 3147 | |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3148 | /* It should now be out of any other write domains, and we can update |
| 3149 | * the domain values for our changes. |
| 3150 | */ |
| 3151 | BUG_ON((obj->write_domain & ~I915_GEM_DOMAIN_CPU) != 0); |
| 3152 | |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 3153 | old_read_domains = obj->read_domains; |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3154 | obj->read_domains |= I915_GEM_DOMAIN_CPU; |
| 3155 | |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 3156 | trace_i915_gem_object_change_domain(obj, |
| 3157 | old_read_domains, |
| 3158 | obj->write_domain); |
| 3159 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3160 | return 0; |
| 3161 | } |
| 3162 | |
| 3163 | /** |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3164 | * Pin an object to the GTT and evaluate the relocations landing in it. |
| 3165 | */ |
| 3166 | static int |
| 3167 | i915_gem_object_pin_and_relocate(struct drm_gem_object *obj, |
| 3168 | struct drm_file *file_priv, |
Jesse Barnes | 76446ca | 2009-12-17 22:05:42 -0500 | [diff] [blame] | 3169 | struct drm_i915_gem_exec_object2 *entry, |
Eric Anholt | 40a5f0d | 2009-03-12 11:23:52 -0700 | [diff] [blame] | 3170 | struct drm_i915_gem_relocation_entry *relocs) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3171 | { |
| 3172 | struct drm_device *dev = obj->dev; |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 3173 | drm_i915_private_t *dev_priv = dev->dev_private; |
Daniel Vetter | 23010e4 | 2010-03-08 13:35:02 +0100 | [diff] [blame] | 3174 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3175 | int i, ret; |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 3176 | void __iomem *reloc_page; |
Jesse Barnes | 76446ca | 2009-12-17 22:05:42 -0500 | [diff] [blame] | 3177 | bool need_fence; |
| 3178 | |
| 3179 | need_fence = entry->flags & EXEC_OBJECT_NEEDS_FENCE && |
| 3180 | obj_priv->tiling_mode != I915_TILING_NONE; |
| 3181 | |
| 3182 | /* Check fence reg constraints and rebind if necessary */ |
Chris Wilson | 808b24d6 | 2010-05-27 13:18:15 +0100 | [diff] [blame] | 3183 | if (need_fence && |
| 3184 | !i915_gem_object_fence_offset_ok(obj, |
| 3185 | obj_priv->tiling_mode)) { |
| 3186 | ret = i915_gem_object_unbind(obj); |
| 3187 | if (ret) |
| 3188 | return ret; |
| 3189 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3190 | |
| 3191 | /* Choose the GTT offset for our buffer and put it there. */ |
| 3192 | ret = i915_gem_object_pin(obj, (uint32_t) entry->alignment); |
| 3193 | if (ret) |
| 3194 | return ret; |
| 3195 | |
Jesse Barnes | 76446ca | 2009-12-17 22:05:42 -0500 | [diff] [blame] | 3196 | /* |
| 3197 | * Pre-965 chips need a fence register set up in order to |
| 3198 | * properly handle blits to/from tiled surfaces. |
| 3199 | */ |
| 3200 | if (need_fence) { |
| 3201 | ret = i915_gem_object_get_fence_reg(obj); |
| 3202 | if (ret != 0) { |
Jesse Barnes | 76446ca | 2009-12-17 22:05:42 -0500 | [diff] [blame] | 3203 | i915_gem_object_unpin(obj); |
| 3204 | return ret; |
| 3205 | } |
| 3206 | } |
| 3207 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3208 | entry->offset = obj_priv->gtt_offset; |
| 3209 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3210 | /* Apply the relocations, using the GTT aperture to avoid cache |
| 3211 | * flushing requirements. |
| 3212 | */ |
| 3213 | for (i = 0; i < entry->relocation_count; i++) { |
Eric Anholt | 40a5f0d | 2009-03-12 11:23:52 -0700 | [diff] [blame] | 3214 | struct drm_i915_gem_relocation_entry *reloc= &relocs[i]; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3215 | struct drm_gem_object *target_obj; |
| 3216 | struct drm_i915_gem_object *target_obj_priv; |
Eric Anholt | 3043c60 | 2008-10-02 12:24:47 -0700 | [diff] [blame] | 3217 | uint32_t reloc_val, reloc_offset; |
| 3218 | uint32_t __iomem *reloc_entry; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3219 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3220 | target_obj = drm_gem_object_lookup(obj->dev, file_priv, |
Eric Anholt | 40a5f0d | 2009-03-12 11:23:52 -0700 | [diff] [blame] | 3221 | reloc->target_handle); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3222 | if (target_obj == NULL) { |
| 3223 | i915_gem_object_unpin(obj); |
Chris Wilson | bf79cb9 | 2010-08-04 14:19:46 +0100 | [diff] [blame] | 3224 | return -ENOENT; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3225 | } |
Daniel Vetter | 23010e4 | 2010-03-08 13:35:02 +0100 | [diff] [blame] | 3226 | target_obj_priv = to_intel_bo(target_obj); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3227 | |
Chris Wilson | 8542a0b | 2009-09-09 21:15:15 +0100 | [diff] [blame] | 3228 | #if WATCH_RELOC |
| 3229 | DRM_INFO("%s: obj %p offset %08x target %d " |
| 3230 | "read %08x write %08x gtt %08x " |
| 3231 | "presumed %08x delta %08x\n", |
| 3232 | __func__, |
| 3233 | obj, |
| 3234 | (int) reloc->offset, |
| 3235 | (int) reloc->target_handle, |
| 3236 | (int) reloc->read_domains, |
| 3237 | (int) reloc->write_domain, |
| 3238 | (int) target_obj_priv->gtt_offset, |
| 3239 | (int) reloc->presumed_offset, |
| 3240 | reloc->delta); |
| 3241 | #endif |
| 3242 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3243 | /* The target buffer should have appeared before us in the |
| 3244 | * exec_object list, so it should have a GTT space bound by now. |
| 3245 | */ |
| 3246 | if (target_obj_priv->gtt_space == NULL) { |
| 3247 | DRM_ERROR("No GTT space found for object %d\n", |
Eric Anholt | 40a5f0d | 2009-03-12 11:23:52 -0700 | [diff] [blame] | 3248 | reloc->target_handle); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3249 | drm_gem_object_unreference(target_obj); |
| 3250 | i915_gem_object_unpin(obj); |
| 3251 | return -EINVAL; |
| 3252 | } |
| 3253 | |
Chris Wilson | 8542a0b | 2009-09-09 21:15:15 +0100 | [diff] [blame] | 3254 | /* Validate that the target is in a valid r/w GPU domain */ |
Daniel Vetter | 16edd55 | 2010-02-19 11:52:02 +0100 | [diff] [blame] | 3255 | if (reloc->write_domain & (reloc->write_domain - 1)) { |
| 3256 | DRM_ERROR("reloc with multiple write domains: " |
| 3257 | "obj %p target %d offset %d " |
| 3258 | "read %08x write %08x", |
| 3259 | obj, reloc->target_handle, |
| 3260 | (int) reloc->offset, |
| 3261 | reloc->read_domains, |
| 3262 | reloc->write_domain); |
| 3263 | return -EINVAL; |
| 3264 | } |
Chris Wilson | 8542a0b | 2009-09-09 21:15:15 +0100 | [diff] [blame] | 3265 | if (reloc->write_domain & I915_GEM_DOMAIN_CPU || |
| 3266 | reloc->read_domains & I915_GEM_DOMAIN_CPU) { |
| 3267 | DRM_ERROR("reloc with read/write CPU domains: " |
| 3268 | "obj %p target %d offset %d " |
| 3269 | "read %08x write %08x", |
| 3270 | obj, reloc->target_handle, |
| 3271 | (int) reloc->offset, |
| 3272 | reloc->read_domains, |
| 3273 | reloc->write_domain); |
| 3274 | drm_gem_object_unreference(target_obj); |
| 3275 | i915_gem_object_unpin(obj); |
| 3276 | return -EINVAL; |
| 3277 | } |
| 3278 | if (reloc->write_domain && target_obj->pending_write_domain && |
| 3279 | reloc->write_domain != target_obj->pending_write_domain) { |
| 3280 | DRM_ERROR("Write domain conflict: " |
| 3281 | "obj %p target %d offset %d " |
| 3282 | "new %08x old %08x\n", |
| 3283 | obj, reloc->target_handle, |
| 3284 | (int) reloc->offset, |
| 3285 | reloc->write_domain, |
| 3286 | target_obj->pending_write_domain); |
| 3287 | drm_gem_object_unreference(target_obj); |
| 3288 | i915_gem_object_unpin(obj); |
| 3289 | return -EINVAL; |
| 3290 | } |
| 3291 | |
| 3292 | target_obj->pending_read_domains |= reloc->read_domains; |
| 3293 | target_obj->pending_write_domain |= reloc->write_domain; |
| 3294 | |
| 3295 | /* If the relocation already has the right value in it, no |
| 3296 | * more work needs to be done. |
| 3297 | */ |
| 3298 | if (target_obj_priv->gtt_offset == reloc->presumed_offset) { |
| 3299 | drm_gem_object_unreference(target_obj); |
| 3300 | continue; |
| 3301 | } |
| 3302 | |
| 3303 | /* Check that the relocation address is valid... */ |
Eric Anholt | 40a5f0d | 2009-03-12 11:23:52 -0700 | [diff] [blame] | 3304 | if (reloc->offset > obj->size - 4) { |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3305 | DRM_ERROR("Relocation beyond object bounds: " |
| 3306 | "obj %p target %d offset %d size %d.\n", |
Eric Anholt | 40a5f0d | 2009-03-12 11:23:52 -0700 | [diff] [blame] | 3307 | obj, reloc->target_handle, |
| 3308 | (int) reloc->offset, (int) obj->size); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3309 | drm_gem_object_unreference(target_obj); |
| 3310 | i915_gem_object_unpin(obj); |
| 3311 | return -EINVAL; |
| 3312 | } |
Eric Anholt | 40a5f0d | 2009-03-12 11:23:52 -0700 | [diff] [blame] | 3313 | if (reloc->offset & 3) { |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3314 | DRM_ERROR("Relocation not 4-byte aligned: " |
| 3315 | "obj %p target %d offset %d.\n", |
Eric Anholt | 40a5f0d | 2009-03-12 11:23:52 -0700 | [diff] [blame] | 3316 | obj, reloc->target_handle, |
| 3317 | (int) reloc->offset); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3318 | drm_gem_object_unreference(target_obj); |
| 3319 | i915_gem_object_unpin(obj); |
| 3320 | return -EINVAL; |
| 3321 | } |
| 3322 | |
Chris Wilson | 8542a0b | 2009-09-09 21:15:15 +0100 | [diff] [blame] | 3323 | /* and points to somewhere within the target object. */ |
Chris Wilson | cd0b9fb | 2009-09-15 23:23:18 +0100 | [diff] [blame] | 3324 | if (reloc->delta >= target_obj->size) { |
| 3325 | DRM_ERROR("Relocation beyond target object bounds: " |
| 3326 | "obj %p target %d delta %d size %d.\n", |
Eric Anholt | 40a5f0d | 2009-03-12 11:23:52 -0700 | [diff] [blame] | 3327 | obj, reloc->target_handle, |
Chris Wilson | cd0b9fb | 2009-09-15 23:23:18 +0100 | [diff] [blame] | 3328 | (int) reloc->delta, (int) target_obj->size); |
Chris Wilson | 491152b | 2009-02-11 14:26:32 +0000 | [diff] [blame] | 3329 | drm_gem_object_unreference(target_obj); |
| 3330 | i915_gem_object_unpin(obj); |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3331 | return -EINVAL; |
| 3332 | } |
| 3333 | |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 3334 | ret = i915_gem_object_set_to_gtt_domain(obj, 1); |
| 3335 | if (ret != 0) { |
| 3336 | drm_gem_object_unreference(target_obj); |
| 3337 | i915_gem_object_unpin(obj); |
| 3338 | return -EINVAL; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3339 | } |
| 3340 | |
| 3341 | /* Map the page containing the relocation we're going to |
| 3342 | * perform. |
| 3343 | */ |
Eric Anholt | 40a5f0d | 2009-03-12 11:23:52 -0700 | [diff] [blame] | 3344 | reloc_offset = obj_priv->gtt_offset + reloc->offset; |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 3345 | reloc_page = io_mapping_map_atomic_wc(dev_priv->mm.gtt_mapping, |
| 3346 | (reloc_offset & |
Chris Wilson | fca3ec0 | 2010-08-04 14:34:24 +0100 | [diff] [blame] | 3347 | ~(PAGE_SIZE - 1)), |
| 3348 | KM_USER0); |
Eric Anholt | 3043c60 | 2008-10-02 12:24:47 -0700 | [diff] [blame] | 3349 | reloc_entry = (uint32_t __iomem *)(reloc_page + |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 3350 | (reloc_offset & (PAGE_SIZE - 1))); |
Eric Anholt | 40a5f0d | 2009-03-12 11:23:52 -0700 | [diff] [blame] | 3351 | reloc_val = target_obj_priv->gtt_offset + reloc->delta; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3352 | |
| 3353 | #if WATCH_BUF |
| 3354 | DRM_INFO("Applied relocation: %p@0x%08x %08x -> %08x\n", |
Eric Anholt | 40a5f0d | 2009-03-12 11:23:52 -0700 | [diff] [blame] | 3355 | obj, (unsigned int) reloc->offset, |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3356 | readl(reloc_entry), reloc_val); |
| 3357 | #endif |
| 3358 | writel(reloc_val, reloc_entry); |
Chris Wilson | fca3ec0 | 2010-08-04 14:34:24 +0100 | [diff] [blame] | 3359 | io_mapping_unmap_atomic(reloc_page, KM_USER0); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3360 | |
Eric Anholt | 40a5f0d | 2009-03-12 11:23:52 -0700 | [diff] [blame] | 3361 | /* The updated presumed offset for this entry will be |
| 3362 | * copied back out to the user. |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3363 | */ |
Eric Anholt | 40a5f0d | 2009-03-12 11:23:52 -0700 | [diff] [blame] | 3364 | reloc->presumed_offset = target_obj_priv->gtt_offset; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3365 | |
| 3366 | drm_gem_object_unreference(target_obj); |
| 3367 | } |
| 3368 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3369 | #if WATCH_BUF |
| 3370 | if (0) |
| 3371 | i915_gem_dump_object(obj, 128, __func__, ~0); |
| 3372 | #endif |
| 3373 | return 0; |
| 3374 | } |
| 3375 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3376 | /* Throttle our rendering by waiting until the ring has completed our requests |
| 3377 | * emitted over 20 msec ago. |
| 3378 | * |
Eric Anholt | b962442 | 2009-06-03 07:27:35 +0000 | [diff] [blame] | 3379 | * Note that if we were to use the current jiffies each time around the loop, |
| 3380 | * we wouldn't escape the function with any frames outstanding if the time to |
| 3381 | * render a frame was over 20ms. |
| 3382 | * |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3383 | * This should get us reasonable parallelism between CPU and GPU but also |
| 3384 | * relatively low latency when blocking on a particular request to finish. |
| 3385 | */ |
| 3386 | static int |
| 3387 | i915_gem_ring_throttle(struct drm_device *dev, struct drm_file *file_priv) |
| 3388 | { |
| 3389 | struct drm_i915_file_private *i915_file_priv = file_priv->driver_priv; |
| 3390 | int ret = 0; |
Eric Anholt | b962442 | 2009-06-03 07:27:35 +0000 | [diff] [blame] | 3391 | unsigned long recent_enough = jiffies - msecs_to_jiffies(20); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3392 | |
| 3393 | mutex_lock(&dev->struct_mutex); |
Eric Anholt | b962442 | 2009-06-03 07:27:35 +0000 | [diff] [blame] | 3394 | while (!list_empty(&i915_file_priv->mm.request_list)) { |
| 3395 | struct drm_i915_gem_request *request; |
| 3396 | |
| 3397 | request = list_first_entry(&i915_file_priv->mm.request_list, |
| 3398 | struct drm_i915_gem_request, |
| 3399 | client_list); |
| 3400 | |
| 3401 | if (time_after_eq(request->emitted_jiffies, recent_enough)) |
| 3402 | break; |
| 3403 | |
Zou Nan hai | 852835f | 2010-05-21 09:08:56 +0800 | [diff] [blame] | 3404 | ret = i915_wait_request(dev, request->seqno, request->ring); |
Eric Anholt | b962442 | 2009-06-03 07:27:35 +0000 | [diff] [blame] | 3405 | if (ret != 0) |
| 3406 | break; |
| 3407 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3408 | mutex_unlock(&dev->struct_mutex); |
Eric Anholt | b962442 | 2009-06-03 07:27:35 +0000 | [diff] [blame] | 3409 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3410 | return ret; |
| 3411 | } |
| 3412 | |
Eric Anholt | 40a5f0d | 2009-03-12 11:23:52 -0700 | [diff] [blame] | 3413 | static int |
Jesse Barnes | 76446ca | 2009-12-17 22:05:42 -0500 | [diff] [blame] | 3414 | i915_gem_get_relocs_from_user(struct drm_i915_gem_exec_object2 *exec_list, |
Eric Anholt | 40a5f0d | 2009-03-12 11:23:52 -0700 | [diff] [blame] | 3415 | uint32_t buffer_count, |
| 3416 | struct drm_i915_gem_relocation_entry **relocs) |
| 3417 | { |
| 3418 | uint32_t reloc_count = 0, reloc_index = 0, i; |
| 3419 | int ret; |
| 3420 | |
| 3421 | *relocs = NULL; |
| 3422 | for (i = 0; i < buffer_count; i++) { |
| 3423 | if (reloc_count + exec_list[i].relocation_count < reloc_count) |
| 3424 | return -EINVAL; |
| 3425 | reloc_count += exec_list[i].relocation_count; |
| 3426 | } |
| 3427 | |
Jesse Barnes | 8e7d2b2 | 2009-05-08 16:13:25 -0700 | [diff] [blame] | 3428 | *relocs = drm_calloc_large(reloc_count, sizeof(**relocs)); |
Jesse Barnes | 76446ca | 2009-12-17 22:05:42 -0500 | [diff] [blame] | 3429 | if (*relocs == NULL) { |
| 3430 | DRM_ERROR("failed to alloc relocs, count %d\n", reloc_count); |
Eric Anholt | 40a5f0d | 2009-03-12 11:23:52 -0700 | [diff] [blame] | 3431 | return -ENOMEM; |
Jesse Barnes | 76446ca | 2009-12-17 22:05:42 -0500 | [diff] [blame] | 3432 | } |
Eric Anholt | 40a5f0d | 2009-03-12 11:23:52 -0700 | [diff] [blame] | 3433 | |
| 3434 | for (i = 0; i < buffer_count; i++) { |
| 3435 | struct drm_i915_gem_relocation_entry __user *user_relocs; |
| 3436 | |
| 3437 | user_relocs = (void __user *)(uintptr_t)exec_list[i].relocs_ptr; |
| 3438 | |
| 3439 | ret = copy_from_user(&(*relocs)[reloc_index], |
| 3440 | user_relocs, |
| 3441 | exec_list[i].relocation_count * |
| 3442 | sizeof(**relocs)); |
| 3443 | if (ret != 0) { |
Jesse Barnes | 8e7d2b2 | 2009-05-08 16:13:25 -0700 | [diff] [blame] | 3444 | drm_free_large(*relocs); |
Eric Anholt | 40a5f0d | 2009-03-12 11:23:52 -0700 | [diff] [blame] | 3445 | *relocs = NULL; |
Florian Mickler | 2bc43b5 | 2009-04-06 22:55:41 +0200 | [diff] [blame] | 3446 | return -EFAULT; |
Eric Anholt | 40a5f0d | 2009-03-12 11:23:52 -0700 | [diff] [blame] | 3447 | } |
| 3448 | |
| 3449 | reloc_index += exec_list[i].relocation_count; |
| 3450 | } |
| 3451 | |
Florian Mickler | 2bc43b5 | 2009-04-06 22:55:41 +0200 | [diff] [blame] | 3452 | return 0; |
Eric Anholt | 40a5f0d | 2009-03-12 11:23:52 -0700 | [diff] [blame] | 3453 | } |
| 3454 | |
| 3455 | static int |
Jesse Barnes | 76446ca | 2009-12-17 22:05:42 -0500 | [diff] [blame] | 3456 | i915_gem_put_relocs_to_user(struct drm_i915_gem_exec_object2 *exec_list, |
Eric Anholt | 40a5f0d | 2009-03-12 11:23:52 -0700 | [diff] [blame] | 3457 | uint32_t buffer_count, |
| 3458 | struct drm_i915_gem_relocation_entry *relocs) |
| 3459 | { |
| 3460 | uint32_t reloc_count = 0, i; |
Florian Mickler | 2bc43b5 | 2009-04-06 22:55:41 +0200 | [diff] [blame] | 3461 | int ret = 0; |
Eric Anholt | 40a5f0d | 2009-03-12 11:23:52 -0700 | [diff] [blame] | 3462 | |
Chris Wilson | 93533c2 | 2010-01-31 10:40:48 +0000 | [diff] [blame] | 3463 | if (relocs == NULL) |
| 3464 | return 0; |
| 3465 | |
Eric Anholt | 40a5f0d | 2009-03-12 11:23:52 -0700 | [diff] [blame] | 3466 | for (i = 0; i < buffer_count; i++) { |
| 3467 | struct drm_i915_gem_relocation_entry __user *user_relocs; |
Florian Mickler | 2bc43b5 | 2009-04-06 22:55:41 +0200 | [diff] [blame] | 3468 | int unwritten; |
Eric Anholt | 40a5f0d | 2009-03-12 11:23:52 -0700 | [diff] [blame] | 3469 | |
| 3470 | user_relocs = (void __user *)(uintptr_t)exec_list[i].relocs_ptr; |
| 3471 | |
Florian Mickler | 2bc43b5 | 2009-04-06 22:55:41 +0200 | [diff] [blame] | 3472 | unwritten = copy_to_user(user_relocs, |
| 3473 | &relocs[reloc_count], |
| 3474 | exec_list[i].relocation_count * |
| 3475 | sizeof(*relocs)); |
| 3476 | |
| 3477 | if (unwritten) { |
| 3478 | ret = -EFAULT; |
| 3479 | goto err; |
Eric Anholt | 40a5f0d | 2009-03-12 11:23:52 -0700 | [diff] [blame] | 3480 | } |
| 3481 | |
| 3482 | reloc_count += exec_list[i].relocation_count; |
| 3483 | } |
| 3484 | |
Florian Mickler | 2bc43b5 | 2009-04-06 22:55:41 +0200 | [diff] [blame] | 3485 | err: |
Jesse Barnes | 8e7d2b2 | 2009-05-08 16:13:25 -0700 | [diff] [blame] | 3486 | drm_free_large(relocs); |
Eric Anholt | 40a5f0d | 2009-03-12 11:23:52 -0700 | [diff] [blame] | 3487 | |
| 3488 | return ret; |
| 3489 | } |
| 3490 | |
Chris Wilson | 83d6079 | 2009-06-06 09:45:57 +0100 | [diff] [blame] | 3491 | static int |
Jesse Barnes | 76446ca | 2009-12-17 22:05:42 -0500 | [diff] [blame] | 3492 | i915_gem_check_execbuffer (struct drm_i915_gem_execbuffer2 *exec, |
Chris Wilson | 83d6079 | 2009-06-06 09:45:57 +0100 | [diff] [blame] | 3493 | uint64_t exec_offset) |
| 3494 | { |
| 3495 | uint32_t exec_start, exec_len; |
| 3496 | |
| 3497 | exec_start = (uint32_t) exec_offset + exec->batch_start_offset; |
| 3498 | exec_len = (uint32_t) exec->batch_len; |
| 3499 | |
| 3500 | if ((exec_start | exec_len) & 0x7) |
| 3501 | return -EINVAL; |
| 3502 | |
| 3503 | if (!exec_start) |
| 3504 | return -EINVAL; |
| 3505 | |
| 3506 | return 0; |
| 3507 | } |
| 3508 | |
Kristian Høgsberg | 6b95a20 | 2009-11-18 11:25:18 -0500 | [diff] [blame] | 3509 | static int |
| 3510 | i915_gem_wait_for_pending_flip(struct drm_device *dev, |
| 3511 | struct drm_gem_object **object_list, |
| 3512 | int count) |
| 3513 | { |
| 3514 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 3515 | struct drm_i915_gem_object *obj_priv; |
| 3516 | DEFINE_WAIT(wait); |
| 3517 | int i, ret = 0; |
| 3518 | |
| 3519 | for (;;) { |
| 3520 | prepare_to_wait(&dev_priv->pending_flip_queue, |
| 3521 | &wait, TASK_INTERRUPTIBLE); |
| 3522 | for (i = 0; i < count; i++) { |
Daniel Vetter | 23010e4 | 2010-03-08 13:35:02 +0100 | [diff] [blame] | 3523 | obj_priv = to_intel_bo(object_list[i]); |
Kristian Høgsberg | 6b95a20 | 2009-11-18 11:25:18 -0500 | [diff] [blame] | 3524 | if (atomic_read(&obj_priv->pending_flip) > 0) |
| 3525 | break; |
| 3526 | } |
| 3527 | if (i == count) |
| 3528 | break; |
| 3529 | |
| 3530 | if (!signal_pending(current)) { |
| 3531 | mutex_unlock(&dev->struct_mutex); |
| 3532 | schedule(); |
| 3533 | mutex_lock(&dev->struct_mutex); |
| 3534 | continue; |
| 3535 | } |
| 3536 | ret = -ERESTARTSYS; |
| 3537 | break; |
| 3538 | } |
| 3539 | finish_wait(&dev_priv->pending_flip_queue, &wait); |
| 3540 | |
| 3541 | return ret; |
| 3542 | } |
| 3543 | |
Chris Wilson | 43b27f4 | 2010-07-02 08:57:15 +0100 | [diff] [blame] | 3544 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3545 | int |
Jesse Barnes | 76446ca | 2009-12-17 22:05:42 -0500 | [diff] [blame] | 3546 | i915_gem_do_execbuffer(struct drm_device *dev, void *data, |
| 3547 | struct drm_file *file_priv, |
| 3548 | struct drm_i915_gem_execbuffer2 *args, |
| 3549 | struct drm_i915_gem_exec_object2 *exec_list) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3550 | { |
| 3551 | drm_i915_private_t *dev_priv = dev->dev_private; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3552 | struct drm_gem_object **object_list = NULL; |
| 3553 | struct drm_gem_object *batch_obj; |
Kristian Høgsberg | b70d11d | 2009-03-03 14:45:57 -0500 | [diff] [blame] | 3554 | struct drm_i915_gem_object *obj_priv; |
Eric Anholt | 201361a | 2009-03-11 12:30:04 -0700 | [diff] [blame] | 3555 | struct drm_clip_rect *cliprects = NULL; |
Chris Wilson | 93533c2 | 2010-01-31 10:40:48 +0000 | [diff] [blame] | 3556 | struct drm_i915_gem_relocation_entry *relocs = NULL; |
Jesse Barnes | 76446ca | 2009-12-17 22:05:42 -0500 | [diff] [blame] | 3557 | int ret = 0, ret2, i, pinned = 0; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3558 | uint64_t exec_offset; |
Eric Anholt | 40a5f0d | 2009-03-12 11:23:52 -0700 | [diff] [blame] | 3559 | uint32_t seqno, flush_domains, reloc_index; |
Kristian Høgsberg | 6b95a20 | 2009-11-18 11:25:18 -0500 | [diff] [blame] | 3560 | int pin_tries, flips; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3561 | |
Zou Nan hai | 852835f | 2010-05-21 09:08:56 +0800 | [diff] [blame] | 3562 | struct intel_ring_buffer *ring = NULL; |
| 3563 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3564 | #if WATCH_EXEC |
| 3565 | DRM_INFO("buffers_ptr %d buffer_count %d len %08x\n", |
| 3566 | (int) args->buffers_ptr, args->buffer_count, args->batch_len); |
| 3567 | #endif |
Zou Nan hai | d1b851f | 2010-05-21 09:08:57 +0800 | [diff] [blame] | 3568 | if (args->flags & I915_EXEC_BSD) { |
| 3569 | if (!HAS_BSD(dev)) { |
| 3570 | DRM_ERROR("execbuf with wrong flag\n"); |
| 3571 | return -EINVAL; |
| 3572 | } |
| 3573 | ring = &dev_priv->bsd_ring; |
| 3574 | } else { |
| 3575 | ring = &dev_priv->render_ring; |
| 3576 | } |
| 3577 | |
Eric Anholt | 4f481ed | 2008-09-10 14:22:49 -0700 | [diff] [blame] | 3578 | if (args->buffer_count < 1) { |
| 3579 | DRM_ERROR("execbuf with %d buffers\n", args->buffer_count); |
| 3580 | return -EINVAL; |
| 3581 | } |
Eric Anholt | c8e0f93 | 2009-11-22 03:49:37 +0100 | [diff] [blame] | 3582 | object_list = drm_malloc_ab(sizeof(*object_list), args->buffer_count); |
Jesse Barnes | 76446ca | 2009-12-17 22:05:42 -0500 | [diff] [blame] | 3583 | if (object_list == NULL) { |
| 3584 | DRM_ERROR("Failed to allocate object list for %d buffers\n", |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3585 | args->buffer_count); |
| 3586 | ret = -ENOMEM; |
| 3587 | goto pre_mutex_err; |
| 3588 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3589 | |
Eric Anholt | 201361a | 2009-03-11 12:30:04 -0700 | [diff] [blame] | 3590 | if (args->num_cliprects != 0) { |
Eric Anholt | 9a298b2 | 2009-03-24 12:23:04 -0700 | [diff] [blame] | 3591 | cliprects = kcalloc(args->num_cliprects, sizeof(*cliprects), |
| 3592 | GFP_KERNEL); |
Owain Ainsworth | a40e8d3 | 2010-02-09 14:25:55 +0000 | [diff] [blame] | 3593 | if (cliprects == NULL) { |
| 3594 | ret = -ENOMEM; |
Eric Anholt | 201361a | 2009-03-11 12:30:04 -0700 | [diff] [blame] | 3595 | goto pre_mutex_err; |
Owain Ainsworth | a40e8d3 | 2010-02-09 14:25:55 +0000 | [diff] [blame] | 3596 | } |
Eric Anholt | 201361a | 2009-03-11 12:30:04 -0700 | [diff] [blame] | 3597 | |
| 3598 | ret = copy_from_user(cliprects, |
| 3599 | (struct drm_clip_rect __user *) |
| 3600 | (uintptr_t) args->cliprects_ptr, |
| 3601 | sizeof(*cliprects) * args->num_cliprects); |
| 3602 | if (ret != 0) { |
| 3603 | DRM_ERROR("copy %d cliprects failed: %d\n", |
| 3604 | args->num_cliprects, ret); |
Dan Carpenter | c877cdc | 2010-06-23 19:03:01 +0200 | [diff] [blame] | 3605 | ret = -EFAULT; |
Eric Anholt | 201361a | 2009-03-11 12:30:04 -0700 | [diff] [blame] | 3606 | goto pre_mutex_err; |
| 3607 | } |
| 3608 | } |
| 3609 | |
Eric Anholt | 40a5f0d | 2009-03-12 11:23:52 -0700 | [diff] [blame] | 3610 | ret = i915_gem_get_relocs_from_user(exec_list, args->buffer_count, |
| 3611 | &relocs); |
| 3612 | if (ret != 0) |
| 3613 | goto pre_mutex_err; |
| 3614 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3615 | mutex_lock(&dev->struct_mutex); |
| 3616 | |
| 3617 | i915_verify_inactive(dev, __FILE__, __LINE__); |
| 3618 | |
Ben Gamari | ba1234d | 2009-09-14 17:48:47 -0400 | [diff] [blame] | 3619 | if (atomic_read(&dev_priv->mm.wedged)) { |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3620 | mutex_unlock(&dev->struct_mutex); |
Chris Wilson | a198bc8 | 2009-02-06 16:55:20 +0000 | [diff] [blame] | 3621 | ret = -EIO; |
| 3622 | goto pre_mutex_err; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3623 | } |
| 3624 | |
| 3625 | if (dev_priv->mm.suspended) { |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3626 | mutex_unlock(&dev->struct_mutex); |
Chris Wilson | a198bc8 | 2009-02-06 16:55:20 +0000 | [diff] [blame] | 3627 | ret = -EBUSY; |
| 3628 | goto pre_mutex_err; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3629 | } |
| 3630 | |
Keith Packard | ac94a96 | 2008-11-20 23:30:27 -0800 | [diff] [blame] | 3631 | /* Look up object handles */ |
Kristian Høgsberg | 6b95a20 | 2009-11-18 11:25:18 -0500 | [diff] [blame] | 3632 | flips = 0; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3633 | for (i = 0; i < args->buffer_count; i++) { |
| 3634 | object_list[i] = drm_gem_object_lookup(dev, file_priv, |
| 3635 | exec_list[i].handle); |
| 3636 | if (object_list[i] == NULL) { |
| 3637 | DRM_ERROR("Invalid object handle %d at index %d\n", |
| 3638 | exec_list[i].handle, i); |
Chris Wilson | 0ce907f | 2010-01-23 20:26:35 +0000 | [diff] [blame] | 3639 | /* prevent error path from reading uninitialized data */ |
| 3640 | args->buffer_count = i + 1; |
Chris Wilson | bf79cb9 | 2010-08-04 14:19:46 +0100 | [diff] [blame] | 3641 | ret = -ENOENT; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3642 | goto err; |
| 3643 | } |
Kristian Høgsberg | b70d11d | 2009-03-03 14:45:57 -0500 | [diff] [blame] | 3644 | |
Daniel Vetter | 23010e4 | 2010-03-08 13:35:02 +0100 | [diff] [blame] | 3645 | obj_priv = to_intel_bo(object_list[i]); |
Kristian Høgsberg | b70d11d | 2009-03-03 14:45:57 -0500 | [diff] [blame] | 3646 | if (obj_priv->in_execbuffer) { |
| 3647 | DRM_ERROR("Object %p appears more than once in object list\n", |
| 3648 | object_list[i]); |
Chris Wilson | 0ce907f | 2010-01-23 20:26:35 +0000 | [diff] [blame] | 3649 | /* prevent error path from reading uninitialized data */ |
| 3650 | args->buffer_count = i + 1; |
Chris Wilson | bf79cb9 | 2010-08-04 14:19:46 +0100 | [diff] [blame] | 3651 | ret = -EINVAL; |
Kristian Høgsberg | b70d11d | 2009-03-03 14:45:57 -0500 | [diff] [blame] | 3652 | goto err; |
| 3653 | } |
| 3654 | obj_priv->in_execbuffer = true; |
Kristian Høgsberg | 6b95a20 | 2009-11-18 11:25:18 -0500 | [diff] [blame] | 3655 | flips += atomic_read(&obj_priv->pending_flip); |
| 3656 | } |
| 3657 | |
| 3658 | if (flips > 0) { |
| 3659 | ret = i915_gem_wait_for_pending_flip(dev, object_list, |
| 3660 | args->buffer_count); |
| 3661 | if (ret) |
| 3662 | goto err; |
Keith Packard | ac94a96 | 2008-11-20 23:30:27 -0800 | [diff] [blame] | 3663 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3664 | |
Keith Packard | ac94a96 | 2008-11-20 23:30:27 -0800 | [diff] [blame] | 3665 | /* Pin and relocate */ |
| 3666 | for (pin_tries = 0; ; pin_tries++) { |
| 3667 | ret = 0; |
Eric Anholt | 40a5f0d | 2009-03-12 11:23:52 -0700 | [diff] [blame] | 3668 | reloc_index = 0; |
| 3669 | |
Keith Packard | ac94a96 | 2008-11-20 23:30:27 -0800 | [diff] [blame] | 3670 | for (i = 0; i < args->buffer_count; i++) { |
| 3671 | object_list[i]->pending_read_domains = 0; |
| 3672 | object_list[i]->pending_write_domain = 0; |
| 3673 | ret = i915_gem_object_pin_and_relocate(object_list[i], |
| 3674 | file_priv, |
Eric Anholt | 40a5f0d | 2009-03-12 11:23:52 -0700 | [diff] [blame] | 3675 | &exec_list[i], |
| 3676 | &relocs[reloc_index]); |
Keith Packard | ac94a96 | 2008-11-20 23:30:27 -0800 | [diff] [blame] | 3677 | if (ret) |
| 3678 | break; |
| 3679 | pinned = i + 1; |
Eric Anholt | 40a5f0d | 2009-03-12 11:23:52 -0700 | [diff] [blame] | 3680 | reloc_index += exec_list[i].relocation_count; |
Keith Packard | ac94a96 | 2008-11-20 23:30:27 -0800 | [diff] [blame] | 3681 | } |
| 3682 | /* success */ |
| 3683 | if (ret == 0) |
| 3684 | break; |
| 3685 | |
| 3686 | /* error other than GTT full, or we've already tried again */ |
Chris Wilson | 2939e1f | 2009-06-06 09:46:03 +0100 | [diff] [blame] | 3687 | if (ret != -ENOSPC || pin_tries >= 1) { |
Chris Wilson | 07f73f6 | 2009-09-14 16:50:30 +0100 | [diff] [blame] | 3688 | if (ret != -ERESTARTSYS) { |
| 3689 | unsigned long long total_size = 0; |
Chris Wilson | 3d1cc47 | 2010-05-27 13:18:19 +0100 | [diff] [blame] | 3690 | int num_fences = 0; |
| 3691 | for (i = 0; i < args->buffer_count; i++) { |
Chris Wilson | 43b27f4 | 2010-07-02 08:57:15 +0100 | [diff] [blame] | 3692 | obj_priv = to_intel_bo(object_list[i]); |
Chris Wilson | 3d1cc47 | 2010-05-27 13:18:19 +0100 | [diff] [blame] | 3693 | |
Chris Wilson | 07f73f6 | 2009-09-14 16:50:30 +0100 | [diff] [blame] | 3694 | total_size += object_list[i]->size; |
Chris Wilson | 3d1cc47 | 2010-05-27 13:18:19 +0100 | [diff] [blame] | 3695 | num_fences += |
| 3696 | exec_list[i].flags & EXEC_OBJECT_NEEDS_FENCE && |
| 3697 | obj_priv->tiling_mode != I915_TILING_NONE; |
| 3698 | } |
| 3699 | DRM_ERROR("Failed to pin buffer %d of %d, total %llu bytes, %d fences: %d\n", |
Chris Wilson | 07f73f6 | 2009-09-14 16:50:30 +0100 | [diff] [blame] | 3700 | pinned+1, args->buffer_count, |
Chris Wilson | 3d1cc47 | 2010-05-27 13:18:19 +0100 | [diff] [blame] | 3701 | total_size, num_fences, |
| 3702 | ret); |
Chris Wilson | 07f73f6 | 2009-09-14 16:50:30 +0100 | [diff] [blame] | 3703 | DRM_ERROR("%d objects [%d pinned], " |
| 3704 | "%d object bytes [%d pinned], " |
| 3705 | "%d/%d gtt bytes\n", |
| 3706 | atomic_read(&dev->object_count), |
| 3707 | atomic_read(&dev->pin_count), |
| 3708 | atomic_read(&dev->object_memory), |
| 3709 | atomic_read(&dev->pin_memory), |
| 3710 | atomic_read(&dev->gtt_memory), |
| 3711 | dev->gtt_total); |
| 3712 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3713 | goto err; |
| 3714 | } |
Keith Packard | ac94a96 | 2008-11-20 23:30:27 -0800 | [diff] [blame] | 3715 | |
| 3716 | /* unpin all of our buffers */ |
| 3717 | for (i = 0; i < pinned; i++) |
| 3718 | i915_gem_object_unpin(object_list[i]); |
Eric Anholt | b117763 | 2008-12-10 10:09:41 -0800 | [diff] [blame] | 3719 | pinned = 0; |
Keith Packard | ac94a96 | 2008-11-20 23:30:27 -0800 | [diff] [blame] | 3720 | |
| 3721 | /* evict everyone we can from the aperture */ |
| 3722 | ret = i915_gem_evict_everything(dev); |
Chris Wilson | 07f73f6 | 2009-09-14 16:50:30 +0100 | [diff] [blame] | 3723 | if (ret && ret != -ENOSPC) |
Keith Packard | ac94a96 | 2008-11-20 23:30:27 -0800 | [diff] [blame] | 3724 | goto err; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3725 | } |
| 3726 | |
| 3727 | /* Set the pending read domains for the batch buffer to COMMAND */ |
| 3728 | batch_obj = object_list[args->buffer_count-1]; |
Chris Wilson | 5f26a2c | 2009-06-06 09:45:58 +0100 | [diff] [blame] | 3729 | if (batch_obj->pending_write_domain) { |
| 3730 | DRM_ERROR("Attempting to use self-modifying batch buffer\n"); |
| 3731 | ret = -EINVAL; |
| 3732 | goto err; |
| 3733 | } |
| 3734 | batch_obj->pending_read_domains |= I915_GEM_DOMAIN_COMMAND; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3735 | |
Chris Wilson | 83d6079 | 2009-06-06 09:45:57 +0100 | [diff] [blame] | 3736 | /* Sanity check the batch buffer, prior to moving objects */ |
| 3737 | exec_offset = exec_list[args->buffer_count - 1].offset; |
| 3738 | ret = i915_gem_check_execbuffer (args, exec_offset); |
| 3739 | if (ret != 0) { |
| 3740 | DRM_ERROR("execbuf with invalid offset/length\n"); |
| 3741 | goto err; |
| 3742 | } |
| 3743 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3744 | i915_verify_inactive(dev, __FILE__, __LINE__); |
| 3745 | |
Keith Packard | 646f0f6 | 2008-11-20 23:23:03 -0800 | [diff] [blame] | 3746 | /* Zero the global flush/invalidate flags. These |
| 3747 | * will be modified as new domains are computed |
| 3748 | * for each object |
| 3749 | */ |
| 3750 | dev->invalidate_domains = 0; |
| 3751 | dev->flush_domains = 0; |
Chris Wilson | 88f356b | 2010-08-04 13:55:32 +0100 | [diff] [blame] | 3752 | dev_priv->flush_rings = 0; |
Keith Packard | 646f0f6 | 2008-11-20 23:23:03 -0800 | [diff] [blame] | 3753 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3754 | for (i = 0; i < args->buffer_count; i++) { |
| 3755 | struct drm_gem_object *obj = object_list[i]; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3756 | |
Keith Packard | 646f0f6 | 2008-11-20 23:23:03 -0800 | [diff] [blame] | 3757 | /* Compute new gpu domains and update invalidate/flush */ |
Eric Anholt | 8b0e378 | 2009-02-19 14:40:50 -0800 | [diff] [blame] | 3758 | i915_gem_object_set_to_gpu_domain(obj); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3759 | } |
| 3760 | |
| 3761 | i915_verify_inactive(dev, __FILE__, __LINE__); |
| 3762 | |
Keith Packard | 646f0f6 | 2008-11-20 23:23:03 -0800 | [diff] [blame] | 3763 | if (dev->invalidate_domains | dev->flush_domains) { |
| 3764 | #if WATCH_EXEC |
| 3765 | DRM_INFO("%s: invalidate_domains %08x flush_domains %08x\n", |
| 3766 | __func__, |
| 3767 | dev->invalidate_domains, |
| 3768 | dev->flush_domains); |
| 3769 | #endif |
| 3770 | i915_gem_flush(dev, |
| 3771 | dev->invalidate_domains, |
| 3772 | dev->flush_domains); |
Chris Wilson | 88f356b | 2010-08-04 13:55:32 +0100 | [diff] [blame] | 3773 | if (dev_priv->flush_rings & FLUSH_RENDER_RING) |
Eric Anholt | b962442 | 2009-06-03 07:27:35 +0000 | [diff] [blame] | 3774 | (void)i915_add_request(dev, file_priv, |
Chris Wilson | 88f356b | 2010-08-04 13:55:32 +0100 | [diff] [blame] | 3775 | dev->flush_domains, |
| 3776 | &dev_priv->render_ring); |
| 3777 | if (dev_priv->flush_rings & FLUSH_BSD_RING) |
| 3778 | (void)i915_add_request(dev, file_priv, |
| 3779 | dev->flush_domains, |
| 3780 | &dev_priv->bsd_ring); |
Keith Packard | 646f0f6 | 2008-11-20 23:23:03 -0800 | [diff] [blame] | 3781 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3782 | |
Eric Anholt | efbeed9 | 2009-02-19 14:54:51 -0800 | [diff] [blame] | 3783 | for (i = 0; i < args->buffer_count; i++) { |
| 3784 | struct drm_gem_object *obj = object_list[i]; |
Daniel Vetter | 23010e4 | 2010-03-08 13:35:02 +0100 | [diff] [blame] | 3785 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 3786 | uint32_t old_write_domain = obj->write_domain; |
Eric Anholt | efbeed9 | 2009-02-19 14:54:51 -0800 | [diff] [blame] | 3787 | |
| 3788 | obj->write_domain = obj->pending_write_domain; |
Daniel Vetter | 99fcb76 | 2010-02-07 16:20:18 +0100 | [diff] [blame] | 3789 | if (obj->write_domain) |
| 3790 | list_move_tail(&obj_priv->gpu_write_list, |
| 3791 | &dev_priv->mm.gpu_write_list); |
| 3792 | else |
| 3793 | list_del_init(&obj_priv->gpu_write_list); |
| 3794 | |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 3795 | trace_i915_gem_object_change_domain(obj, |
| 3796 | obj->read_domains, |
| 3797 | old_write_domain); |
Eric Anholt | efbeed9 | 2009-02-19 14:54:51 -0800 | [diff] [blame] | 3798 | } |
| 3799 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3800 | i915_verify_inactive(dev, __FILE__, __LINE__); |
| 3801 | |
| 3802 | #if WATCH_COHERENCY |
| 3803 | for (i = 0; i < args->buffer_count; i++) { |
| 3804 | i915_gem_object_check_coherency(object_list[i], |
| 3805 | exec_list[i].handle); |
| 3806 | } |
| 3807 | #endif |
| 3808 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3809 | #if WATCH_EXEC |
Ben Gamari | 6911a9b | 2009-04-02 11:24:54 -0700 | [diff] [blame] | 3810 | i915_gem_dump_object(batch_obj, |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3811 | args->batch_len, |
| 3812 | __func__, |
| 3813 | ~0); |
| 3814 | #endif |
| 3815 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3816 | /* Exec the batchbuffer */ |
Zou Nan hai | 852835f | 2010-05-21 09:08:56 +0800 | [diff] [blame] | 3817 | ret = ring->dispatch_gem_execbuffer(dev, ring, args, |
| 3818 | cliprects, exec_offset); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3819 | if (ret) { |
| 3820 | DRM_ERROR("dispatch failed %d\n", ret); |
| 3821 | goto err; |
| 3822 | } |
| 3823 | |
| 3824 | /* |
| 3825 | * Ensure that the commands in the batch buffer are |
| 3826 | * finished before the interrupt fires |
| 3827 | */ |
Zou Nan hai | 852835f | 2010-05-21 09:08:56 +0800 | [diff] [blame] | 3828 | flush_domains = i915_retire_commands(dev, ring); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3829 | |
| 3830 | i915_verify_inactive(dev, __FILE__, __LINE__); |
| 3831 | |
| 3832 | /* |
| 3833 | * Get a seqno representing the execution of the current buffer, |
| 3834 | * which we can wait on. We would like to mitigate these interrupts, |
| 3835 | * likely by only creating seqnos occasionally (so that we have |
| 3836 | * *some* interrupts representing completion of buffers that we can |
| 3837 | * wait on when trying to clear up gtt space). |
| 3838 | */ |
Zou Nan hai | 852835f | 2010-05-21 09:08:56 +0800 | [diff] [blame] | 3839 | seqno = i915_add_request(dev, file_priv, flush_domains, ring); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3840 | BUG_ON(seqno == 0); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3841 | for (i = 0; i < args->buffer_count; i++) { |
| 3842 | struct drm_gem_object *obj = object_list[i]; |
Zou Nan hai | 852835f | 2010-05-21 09:08:56 +0800 | [diff] [blame] | 3843 | obj_priv = to_intel_bo(obj); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3844 | |
Zou Nan hai | 852835f | 2010-05-21 09:08:56 +0800 | [diff] [blame] | 3845 | i915_gem_object_move_to_active(obj, seqno, ring); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3846 | #if WATCH_LRU |
| 3847 | DRM_INFO("%s: move to exec list %p\n", __func__, obj); |
| 3848 | #endif |
| 3849 | } |
| 3850 | #if WATCH_LRU |
| 3851 | i915_dump_lru(dev, __func__); |
| 3852 | #endif |
| 3853 | |
| 3854 | i915_verify_inactive(dev, __FILE__, __LINE__); |
| 3855 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3856 | err: |
Julia Lawall | aad87df | 2008-12-21 16:28:47 +0100 | [diff] [blame] | 3857 | for (i = 0; i < pinned; i++) |
| 3858 | i915_gem_object_unpin(object_list[i]); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3859 | |
Kristian Høgsberg | b70d11d | 2009-03-03 14:45:57 -0500 | [diff] [blame] | 3860 | for (i = 0; i < args->buffer_count; i++) { |
| 3861 | if (object_list[i]) { |
Daniel Vetter | 23010e4 | 2010-03-08 13:35:02 +0100 | [diff] [blame] | 3862 | obj_priv = to_intel_bo(object_list[i]); |
Kristian Høgsberg | b70d11d | 2009-03-03 14:45:57 -0500 | [diff] [blame] | 3863 | obj_priv->in_execbuffer = false; |
| 3864 | } |
Julia Lawall | aad87df | 2008-12-21 16:28:47 +0100 | [diff] [blame] | 3865 | drm_gem_object_unreference(object_list[i]); |
Kristian Høgsberg | b70d11d | 2009-03-03 14:45:57 -0500 | [diff] [blame] | 3866 | } |
Julia Lawall | aad87df | 2008-12-21 16:28:47 +0100 | [diff] [blame] | 3867 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3868 | mutex_unlock(&dev->struct_mutex); |
| 3869 | |
Chris Wilson | 93533c2 | 2010-01-31 10:40:48 +0000 | [diff] [blame] | 3870 | pre_mutex_err: |
Eric Anholt | 40a5f0d | 2009-03-12 11:23:52 -0700 | [diff] [blame] | 3871 | /* Copy the updated relocations out regardless of current error |
| 3872 | * state. Failure to update the relocs would mean that the next |
| 3873 | * time userland calls execbuf, it would do so with presumed offset |
| 3874 | * state that didn't match the actual object state. |
| 3875 | */ |
| 3876 | ret2 = i915_gem_put_relocs_to_user(exec_list, args->buffer_count, |
| 3877 | relocs); |
| 3878 | if (ret2 != 0) { |
| 3879 | DRM_ERROR("Failed to copy relocations back out: %d\n", ret2); |
| 3880 | |
| 3881 | if (ret == 0) |
| 3882 | ret = ret2; |
| 3883 | } |
| 3884 | |
Jesse Barnes | 8e7d2b2 | 2009-05-08 16:13:25 -0700 | [diff] [blame] | 3885 | drm_free_large(object_list); |
Eric Anholt | 9a298b2 | 2009-03-24 12:23:04 -0700 | [diff] [blame] | 3886 | kfree(cliprects); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3887 | |
| 3888 | return ret; |
| 3889 | } |
| 3890 | |
Jesse Barnes | 76446ca | 2009-12-17 22:05:42 -0500 | [diff] [blame] | 3891 | /* |
| 3892 | * Legacy execbuffer just creates an exec2 list from the original exec object |
| 3893 | * list array and passes it to the real function. |
| 3894 | */ |
| 3895 | int |
| 3896 | i915_gem_execbuffer(struct drm_device *dev, void *data, |
| 3897 | struct drm_file *file_priv) |
| 3898 | { |
| 3899 | struct drm_i915_gem_execbuffer *args = data; |
| 3900 | struct drm_i915_gem_execbuffer2 exec2; |
| 3901 | struct drm_i915_gem_exec_object *exec_list = NULL; |
| 3902 | struct drm_i915_gem_exec_object2 *exec2_list = NULL; |
| 3903 | int ret, i; |
| 3904 | |
| 3905 | #if WATCH_EXEC |
| 3906 | DRM_INFO("buffers_ptr %d buffer_count %d len %08x\n", |
| 3907 | (int) args->buffers_ptr, args->buffer_count, args->batch_len); |
| 3908 | #endif |
| 3909 | |
| 3910 | if (args->buffer_count < 1) { |
| 3911 | DRM_ERROR("execbuf with %d buffers\n", args->buffer_count); |
| 3912 | return -EINVAL; |
| 3913 | } |
| 3914 | |
| 3915 | /* Copy in the exec list from userland */ |
| 3916 | exec_list = drm_malloc_ab(sizeof(*exec_list), args->buffer_count); |
| 3917 | exec2_list = drm_malloc_ab(sizeof(*exec2_list), args->buffer_count); |
| 3918 | if (exec_list == NULL || exec2_list == NULL) { |
| 3919 | DRM_ERROR("Failed to allocate exec list for %d buffers\n", |
| 3920 | args->buffer_count); |
| 3921 | drm_free_large(exec_list); |
| 3922 | drm_free_large(exec2_list); |
| 3923 | return -ENOMEM; |
| 3924 | } |
| 3925 | ret = copy_from_user(exec_list, |
| 3926 | (struct drm_i915_relocation_entry __user *) |
| 3927 | (uintptr_t) args->buffers_ptr, |
| 3928 | sizeof(*exec_list) * args->buffer_count); |
| 3929 | if (ret != 0) { |
| 3930 | DRM_ERROR("copy %d exec entries failed %d\n", |
| 3931 | args->buffer_count, ret); |
| 3932 | drm_free_large(exec_list); |
| 3933 | drm_free_large(exec2_list); |
| 3934 | return -EFAULT; |
| 3935 | } |
| 3936 | |
| 3937 | for (i = 0; i < args->buffer_count; i++) { |
| 3938 | exec2_list[i].handle = exec_list[i].handle; |
| 3939 | exec2_list[i].relocation_count = exec_list[i].relocation_count; |
| 3940 | exec2_list[i].relocs_ptr = exec_list[i].relocs_ptr; |
| 3941 | exec2_list[i].alignment = exec_list[i].alignment; |
| 3942 | exec2_list[i].offset = exec_list[i].offset; |
| 3943 | if (!IS_I965G(dev)) |
| 3944 | exec2_list[i].flags = EXEC_OBJECT_NEEDS_FENCE; |
| 3945 | else |
| 3946 | exec2_list[i].flags = 0; |
| 3947 | } |
| 3948 | |
| 3949 | exec2.buffers_ptr = args->buffers_ptr; |
| 3950 | exec2.buffer_count = args->buffer_count; |
| 3951 | exec2.batch_start_offset = args->batch_start_offset; |
| 3952 | exec2.batch_len = args->batch_len; |
| 3953 | exec2.DR1 = args->DR1; |
| 3954 | exec2.DR4 = args->DR4; |
| 3955 | exec2.num_cliprects = args->num_cliprects; |
| 3956 | exec2.cliprects_ptr = args->cliprects_ptr; |
Zou Nan hai | 852835f | 2010-05-21 09:08:56 +0800 | [diff] [blame] | 3957 | exec2.flags = I915_EXEC_RENDER; |
Jesse Barnes | 76446ca | 2009-12-17 22:05:42 -0500 | [diff] [blame] | 3958 | |
| 3959 | ret = i915_gem_do_execbuffer(dev, data, file_priv, &exec2, exec2_list); |
| 3960 | if (!ret) { |
| 3961 | /* Copy the new buffer offsets back to the user's exec list. */ |
| 3962 | for (i = 0; i < args->buffer_count; i++) |
| 3963 | exec_list[i].offset = exec2_list[i].offset; |
| 3964 | /* ... and back out to userspace */ |
| 3965 | ret = copy_to_user((struct drm_i915_relocation_entry __user *) |
| 3966 | (uintptr_t) args->buffers_ptr, |
| 3967 | exec_list, |
| 3968 | sizeof(*exec_list) * args->buffer_count); |
| 3969 | if (ret) { |
| 3970 | ret = -EFAULT; |
| 3971 | DRM_ERROR("failed to copy %d exec entries " |
| 3972 | "back to user (%d)\n", |
| 3973 | args->buffer_count, ret); |
| 3974 | } |
Jesse Barnes | 76446ca | 2009-12-17 22:05:42 -0500 | [diff] [blame] | 3975 | } |
| 3976 | |
| 3977 | drm_free_large(exec_list); |
| 3978 | drm_free_large(exec2_list); |
| 3979 | return ret; |
| 3980 | } |
| 3981 | |
| 3982 | int |
| 3983 | i915_gem_execbuffer2(struct drm_device *dev, void *data, |
| 3984 | struct drm_file *file_priv) |
| 3985 | { |
| 3986 | struct drm_i915_gem_execbuffer2 *args = data; |
| 3987 | struct drm_i915_gem_exec_object2 *exec2_list = NULL; |
| 3988 | int ret; |
| 3989 | |
| 3990 | #if WATCH_EXEC |
| 3991 | DRM_INFO("buffers_ptr %d buffer_count %d len %08x\n", |
| 3992 | (int) args->buffers_ptr, args->buffer_count, args->batch_len); |
| 3993 | #endif |
| 3994 | |
| 3995 | if (args->buffer_count < 1) { |
| 3996 | DRM_ERROR("execbuf2 with %d buffers\n", args->buffer_count); |
| 3997 | return -EINVAL; |
| 3998 | } |
| 3999 | |
| 4000 | exec2_list = drm_malloc_ab(sizeof(*exec2_list), args->buffer_count); |
| 4001 | if (exec2_list == NULL) { |
| 4002 | DRM_ERROR("Failed to allocate exec list for %d buffers\n", |
| 4003 | args->buffer_count); |
| 4004 | return -ENOMEM; |
| 4005 | } |
| 4006 | ret = copy_from_user(exec2_list, |
| 4007 | (struct drm_i915_relocation_entry __user *) |
| 4008 | (uintptr_t) args->buffers_ptr, |
| 4009 | sizeof(*exec2_list) * args->buffer_count); |
| 4010 | if (ret != 0) { |
| 4011 | DRM_ERROR("copy %d exec entries failed %d\n", |
| 4012 | args->buffer_count, ret); |
| 4013 | drm_free_large(exec2_list); |
| 4014 | return -EFAULT; |
| 4015 | } |
| 4016 | |
| 4017 | ret = i915_gem_do_execbuffer(dev, data, file_priv, args, exec2_list); |
| 4018 | if (!ret) { |
| 4019 | /* Copy the new buffer offsets back to the user's exec list. */ |
| 4020 | ret = copy_to_user((struct drm_i915_relocation_entry __user *) |
| 4021 | (uintptr_t) args->buffers_ptr, |
| 4022 | exec2_list, |
| 4023 | sizeof(*exec2_list) * args->buffer_count); |
| 4024 | if (ret) { |
| 4025 | ret = -EFAULT; |
| 4026 | DRM_ERROR("failed to copy %d exec entries " |
| 4027 | "back to user (%d)\n", |
| 4028 | args->buffer_count, ret); |
| 4029 | } |
| 4030 | } |
| 4031 | |
| 4032 | drm_free_large(exec2_list); |
| 4033 | return ret; |
| 4034 | } |
| 4035 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4036 | int |
| 4037 | i915_gem_object_pin(struct drm_gem_object *obj, uint32_t alignment) |
| 4038 | { |
| 4039 | struct drm_device *dev = obj->dev; |
Daniel Vetter | 23010e4 | 2010-03-08 13:35:02 +0100 | [diff] [blame] | 4040 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4041 | int ret; |
| 4042 | |
Daniel Vetter | 778c354 | 2010-05-13 11:49:44 +0200 | [diff] [blame] | 4043 | BUG_ON(obj_priv->pin_count == DRM_I915_GEM_OBJECT_MAX_PIN_COUNT); |
| 4044 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4045 | i915_verify_inactive(dev, __FILE__, __LINE__); |
Chris Wilson | ac0c6b5 | 2010-05-27 13:18:18 +0100 | [diff] [blame] | 4046 | |
| 4047 | if (obj_priv->gtt_space != NULL) { |
| 4048 | if (alignment == 0) |
| 4049 | alignment = i915_gem_get_gtt_alignment(obj); |
| 4050 | if (obj_priv->gtt_offset & (alignment - 1)) { |
Chris Wilson | ae7d49d | 2010-08-04 12:37:41 +0100 | [diff] [blame] | 4051 | WARN(obj_priv->pin_count, |
| 4052 | "bo is already pinned with incorrect alignment:" |
| 4053 | " offset=%x, req.alignment=%x\n", |
| 4054 | obj_priv->gtt_offset, alignment); |
Chris Wilson | ac0c6b5 | 2010-05-27 13:18:18 +0100 | [diff] [blame] | 4055 | ret = i915_gem_object_unbind(obj); |
| 4056 | if (ret) |
| 4057 | return ret; |
| 4058 | } |
| 4059 | } |
| 4060 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4061 | if (obj_priv->gtt_space == NULL) { |
| 4062 | ret = i915_gem_object_bind_to_gtt(obj, alignment); |
Chris Wilson | 9731129 | 2009-09-21 00:22:34 +0100 | [diff] [blame] | 4063 | if (ret) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4064 | return ret; |
Chris Wilson | 22c344e | 2009-02-11 14:26:45 +0000 | [diff] [blame] | 4065 | } |
Jesse Barnes | 76446ca | 2009-12-17 22:05:42 -0500 | [diff] [blame] | 4066 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4067 | obj_priv->pin_count++; |
| 4068 | |
| 4069 | /* If the object is not active and not pending a flush, |
| 4070 | * remove it from the inactive list |
| 4071 | */ |
| 4072 | if (obj_priv->pin_count == 1) { |
| 4073 | atomic_inc(&dev->pin_count); |
| 4074 | atomic_add(obj->size, &dev->pin_memory); |
| 4075 | if (!obj_priv->active && |
Chris Wilson | bf1a109 | 2010-08-07 11:01:20 +0100 | [diff] [blame] | 4076 | (obj->write_domain & I915_GEM_GPU_DOMAINS) == 0) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4077 | list_del_init(&obj_priv->list); |
| 4078 | } |
| 4079 | i915_verify_inactive(dev, __FILE__, __LINE__); |
| 4080 | |
| 4081 | return 0; |
| 4082 | } |
| 4083 | |
| 4084 | void |
| 4085 | i915_gem_object_unpin(struct drm_gem_object *obj) |
| 4086 | { |
| 4087 | struct drm_device *dev = obj->dev; |
| 4088 | drm_i915_private_t *dev_priv = dev->dev_private; |
Daniel Vetter | 23010e4 | 2010-03-08 13:35:02 +0100 | [diff] [blame] | 4089 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4090 | |
| 4091 | i915_verify_inactive(dev, __FILE__, __LINE__); |
| 4092 | obj_priv->pin_count--; |
| 4093 | BUG_ON(obj_priv->pin_count < 0); |
| 4094 | BUG_ON(obj_priv->gtt_space == NULL); |
| 4095 | |
| 4096 | /* If the object is no longer pinned, and is |
| 4097 | * neither active nor being flushed, then stick it on |
| 4098 | * the inactive list |
| 4099 | */ |
| 4100 | if (obj_priv->pin_count == 0) { |
| 4101 | if (!obj_priv->active && |
Chris Wilson | 21d509e | 2009-06-06 09:46:02 +0100 | [diff] [blame] | 4102 | (obj->write_domain & I915_GEM_GPU_DOMAINS) == 0) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4103 | list_move_tail(&obj_priv->list, |
| 4104 | &dev_priv->mm.inactive_list); |
| 4105 | atomic_dec(&dev->pin_count); |
| 4106 | atomic_sub(obj->size, &dev->pin_memory); |
| 4107 | } |
| 4108 | i915_verify_inactive(dev, __FILE__, __LINE__); |
| 4109 | } |
| 4110 | |
| 4111 | int |
| 4112 | i915_gem_pin_ioctl(struct drm_device *dev, void *data, |
| 4113 | struct drm_file *file_priv) |
| 4114 | { |
| 4115 | struct drm_i915_gem_pin *args = data; |
| 4116 | struct drm_gem_object *obj; |
| 4117 | struct drm_i915_gem_object *obj_priv; |
| 4118 | int ret; |
| 4119 | |
| 4120 | mutex_lock(&dev->struct_mutex); |
| 4121 | |
| 4122 | obj = drm_gem_object_lookup(dev, file_priv, args->handle); |
| 4123 | if (obj == NULL) { |
| 4124 | DRM_ERROR("Bad handle in i915_gem_pin_ioctl(): %d\n", |
| 4125 | args->handle); |
| 4126 | mutex_unlock(&dev->struct_mutex); |
Chris Wilson | bf79cb9 | 2010-08-04 14:19:46 +0100 | [diff] [blame] | 4127 | return -ENOENT; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4128 | } |
Daniel Vetter | 23010e4 | 2010-03-08 13:35:02 +0100 | [diff] [blame] | 4129 | obj_priv = to_intel_bo(obj); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4130 | |
Chris Wilson | bb6baf7 | 2009-09-22 14:24:13 +0100 | [diff] [blame] | 4131 | if (obj_priv->madv != I915_MADV_WILLNEED) { |
| 4132 | DRM_ERROR("Attempting to pin a purgeable buffer\n"); |
Chris Wilson | 3ef94da | 2009-09-14 16:50:29 +0100 | [diff] [blame] | 4133 | drm_gem_object_unreference(obj); |
| 4134 | mutex_unlock(&dev->struct_mutex); |
| 4135 | return -EINVAL; |
| 4136 | } |
| 4137 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 4138 | if (obj_priv->pin_filp != NULL && obj_priv->pin_filp != file_priv) { |
| 4139 | DRM_ERROR("Already pinned in i915_gem_pin_ioctl(): %d\n", |
| 4140 | args->handle); |
Chris Wilson | 96dec61 | 2009-02-08 19:08:04 +0000 | [diff] [blame] | 4141 | drm_gem_object_unreference(obj); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4142 | mutex_unlock(&dev->struct_mutex); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 4143 | return -EINVAL; |
| 4144 | } |
| 4145 | |
| 4146 | obj_priv->user_pin_count++; |
| 4147 | obj_priv->pin_filp = file_priv; |
| 4148 | if (obj_priv->user_pin_count == 1) { |
| 4149 | ret = i915_gem_object_pin(obj, args->alignment); |
| 4150 | if (ret != 0) { |
| 4151 | drm_gem_object_unreference(obj); |
| 4152 | mutex_unlock(&dev->struct_mutex); |
| 4153 | return ret; |
| 4154 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4155 | } |
| 4156 | |
| 4157 | /* XXX - flush the CPU caches for pinned objects |
| 4158 | * as the X server doesn't manage domains yet |
| 4159 | */ |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 4160 | i915_gem_object_flush_cpu_write_domain(obj); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4161 | args->offset = obj_priv->gtt_offset; |
| 4162 | drm_gem_object_unreference(obj); |
| 4163 | mutex_unlock(&dev->struct_mutex); |
| 4164 | |
| 4165 | return 0; |
| 4166 | } |
| 4167 | |
| 4168 | int |
| 4169 | i915_gem_unpin_ioctl(struct drm_device *dev, void *data, |
| 4170 | struct drm_file *file_priv) |
| 4171 | { |
| 4172 | struct drm_i915_gem_pin *args = data; |
| 4173 | struct drm_gem_object *obj; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 4174 | struct drm_i915_gem_object *obj_priv; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4175 | |
| 4176 | mutex_lock(&dev->struct_mutex); |
| 4177 | |
| 4178 | obj = drm_gem_object_lookup(dev, file_priv, args->handle); |
| 4179 | if (obj == NULL) { |
| 4180 | DRM_ERROR("Bad handle in i915_gem_unpin_ioctl(): %d\n", |
| 4181 | args->handle); |
| 4182 | mutex_unlock(&dev->struct_mutex); |
Chris Wilson | bf79cb9 | 2010-08-04 14:19:46 +0100 | [diff] [blame] | 4183 | return -ENOENT; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4184 | } |
| 4185 | |
Daniel Vetter | 23010e4 | 2010-03-08 13:35:02 +0100 | [diff] [blame] | 4186 | obj_priv = to_intel_bo(obj); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 4187 | if (obj_priv->pin_filp != file_priv) { |
| 4188 | DRM_ERROR("Not pinned by caller in i915_gem_pin_ioctl(): %d\n", |
| 4189 | args->handle); |
| 4190 | drm_gem_object_unreference(obj); |
| 4191 | mutex_unlock(&dev->struct_mutex); |
| 4192 | return -EINVAL; |
| 4193 | } |
| 4194 | obj_priv->user_pin_count--; |
| 4195 | if (obj_priv->user_pin_count == 0) { |
| 4196 | obj_priv->pin_filp = NULL; |
| 4197 | i915_gem_object_unpin(obj); |
| 4198 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4199 | |
| 4200 | drm_gem_object_unreference(obj); |
| 4201 | mutex_unlock(&dev->struct_mutex); |
| 4202 | return 0; |
| 4203 | } |
| 4204 | |
| 4205 | int |
| 4206 | i915_gem_busy_ioctl(struct drm_device *dev, void *data, |
| 4207 | struct drm_file *file_priv) |
| 4208 | { |
| 4209 | struct drm_i915_gem_busy *args = data; |
| 4210 | struct drm_gem_object *obj; |
| 4211 | struct drm_i915_gem_object *obj_priv; |
| 4212 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4213 | obj = drm_gem_object_lookup(dev, file_priv, args->handle); |
| 4214 | if (obj == NULL) { |
| 4215 | DRM_ERROR("Bad handle in i915_gem_busy_ioctl(): %d\n", |
| 4216 | args->handle); |
Chris Wilson | bf79cb9 | 2010-08-04 14:19:46 +0100 | [diff] [blame] | 4217 | return -ENOENT; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4218 | } |
| 4219 | |
Chris Wilson | b1ce786 | 2009-06-06 09:46:00 +0100 | [diff] [blame] | 4220 | mutex_lock(&dev->struct_mutex); |
Zou Nan hai | d1b851f | 2010-05-21 09:08:57 +0800 | [diff] [blame] | 4221 | |
Chris Wilson | 0be555b | 2010-08-04 15:36:30 +0100 | [diff] [blame] | 4222 | /* Count all active objects as busy, even if they are currently not used |
| 4223 | * by the gpu. Users of this interface expect objects to eventually |
| 4224 | * become non-busy without any further actions, therefore emit any |
| 4225 | * necessary flushes here. |
Eric Anholt | c4de0a5 | 2008-12-14 19:05:04 -0800 | [diff] [blame] | 4226 | */ |
Chris Wilson | 0be555b | 2010-08-04 15:36:30 +0100 | [diff] [blame] | 4227 | obj_priv = to_intel_bo(obj); |
| 4228 | args->busy = obj_priv->active; |
| 4229 | if (args->busy) { |
| 4230 | /* Unconditionally flush objects, even when the gpu still uses this |
| 4231 | * object. Userspace calling this function indicates that it wants to |
| 4232 | * use this buffer rather sooner than later, so issuing the required |
| 4233 | * flush earlier is beneficial. |
| 4234 | */ |
| 4235 | if (obj->write_domain) { |
| 4236 | i915_gem_flush(dev, 0, obj->write_domain); |
| 4237 | (void)i915_add_request(dev, file_priv, obj->write_domain, obj_priv->ring); |
| 4238 | } |
| 4239 | |
| 4240 | /* Update the active list for the hardware's current position. |
| 4241 | * Otherwise this only updates on a delayed timer or when irqs |
| 4242 | * are actually unmasked, and our working set ends up being |
| 4243 | * larger than required. |
| 4244 | */ |
| 4245 | i915_gem_retire_requests_ring(dev, obj_priv->ring); |
| 4246 | |
| 4247 | args->busy = obj_priv->active; |
| 4248 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4249 | |
| 4250 | drm_gem_object_unreference(obj); |
| 4251 | mutex_unlock(&dev->struct_mutex); |
| 4252 | return 0; |
| 4253 | } |
| 4254 | |
| 4255 | int |
| 4256 | i915_gem_throttle_ioctl(struct drm_device *dev, void *data, |
| 4257 | struct drm_file *file_priv) |
| 4258 | { |
| 4259 | return i915_gem_ring_throttle(dev, file_priv); |
| 4260 | } |
| 4261 | |
Chris Wilson | 3ef94da | 2009-09-14 16:50:29 +0100 | [diff] [blame] | 4262 | int |
| 4263 | i915_gem_madvise_ioctl(struct drm_device *dev, void *data, |
| 4264 | struct drm_file *file_priv) |
| 4265 | { |
| 4266 | struct drm_i915_gem_madvise *args = data; |
| 4267 | struct drm_gem_object *obj; |
| 4268 | struct drm_i915_gem_object *obj_priv; |
| 4269 | |
| 4270 | switch (args->madv) { |
| 4271 | case I915_MADV_DONTNEED: |
| 4272 | case I915_MADV_WILLNEED: |
| 4273 | break; |
| 4274 | default: |
| 4275 | return -EINVAL; |
| 4276 | } |
| 4277 | |
| 4278 | obj = drm_gem_object_lookup(dev, file_priv, args->handle); |
| 4279 | if (obj == NULL) { |
| 4280 | DRM_ERROR("Bad handle in i915_gem_madvise_ioctl(): %d\n", |
| 4281 | args->handle); |
Chris Wilson | bf79cb9 | 2010-08-04 14:19:46 +0100 | [diff] [blame] | 4282 | return -ENOENT; |
Chris Wilson | 3ef94da | 2009-09-14 16:50:29 +0100 | [diff] [blame] | 4283 | } |
| 4284 | |
| 4285 | mutex_lock(&dev->struct_mutex); |
Daniel Vetter | 23010e4 | 2010-03-08 13:35:02 +0100 | [diff] [blame] | 4286 | obj_priv = to_intel_bo(obj); |
Chris Wilson | 3ef94da | 2009-09-14 16:50:29 +0100 | [diff] [blame] | 4287 | |
| 4288 | if (obj_priv->pin_count) { |
| 4289 | drm_gem_object_unreference(obj); |
| 4290 | mutex_unlock(&dev->struct_mutex); |
| 4291 | |
| 4292 | DRM_ERROR("Attempted i915_gem_madvise_ioctl() on a pinned object\n"); |
| 4293 | return -EINVAL; |
| 4294 | } |
| 4295 | |
Chris Wilson | bb6baf7 | 2009-09-22 14:24:13 +0100 | [diff] [blame] | 4296 | if (obj_priv->madv != __I915_MADV_PURGED) |
| 4297 | obj_priv->madv = args->madv; |
Chris Wilson | 3ef94da | 2009-09-14 16:50:29 +0100 | [diff] [blame] | 4298 | |
Chris Wilson | 2d7ef39 | 2009-09-20 23:13:10 +0100 | [diff] [blame] | 4299 | /* if the object is no longer bound, discard its backing storage */ |
| 4300 | if (i915_gem_object_is_purgeable(obj_priv) && |
| 4301 | obj_priv->gtt_space == NULL) |
| 4302 | i915_gem_object_truncate(obj); |
| 4303 | |
Chris Wilson | bb6baf7 | 2009-09-22 14:24:13 +0100 | [diff] [blame] | 4304 | args->retained = obj_priv->madv != __I915_MADV_PURGED; |
| 4305 | |
Chris Wilson | 3ef94da | 2009-09-14 16:50:29 +0100 | [diff] [blame] | 4306 | drm_gem_object_unreference(obj); |
| 4307 | mutex_unlock(&dev->struct_mutex); |
| 4308 | |
| 4309 | return 0; |
| 4310 | } |
| 4311 | |
Daniel Vetter | ac52bc5 | 2010-04-09 19:05:06 +0000 | [diff] [blame] | 4312 | struct drm_gem_object * i915_gem_alloc_object(struct drm_device *dev, |
| 4313 | size_t size) |
| 4314 | { |
Daniel Vetter | c397b90 | 2010-04-09 19:05:07 +0000 | [diff] [blame] | 4315 | struct drm_i915_gem_object *obj; |
| 4316 | |
| 4317 | obj = kzalloc(sizeof(*obj), GFP_KERNEL); |
| 4318 | if (obj == NULL) |
| 4319 | return NULL; |
| 4320 | |
| 4321 | if (drm_gem_object_init(dev, &obj->base, size) != 0) { |
| 4322 | kfree(obj); |
| 4323 | return NULL; |
| 4324 | } |
| 4325 | |
| 4326 | obj->base.write_domain = I915_GEM_DOMAIN_CPU; |
| 4327 | obj->base.read_domains = I915_GEM_DOMAIN_CPU; |
| 4328 | |
| 4329 | obj->agp_type = AGP_USER_MEMORY; |
Daniel Vetter | 62b8b21 | 2010-04-09 19:05:08 +0000 | [diff] [blame] | 4330 | obj->base.driver_private = NULL; |
Daniel Vetter | c397b90 | 2010-04-09 19:05:07 +0000 | [diff] [blame] | 4331 | obj->fence_reg = I915_FENCE_REG_NONE; |
| 4332 | INIT_LIST_HEAD(&obj->list); |
| 4333 | INIT_LIST_HEAD(&obj->gpu_write_list); |
Daniel Vetter | c397b90 | 2010-04-09 19:05:07 +0000 | [diff] [blame] | 4334 | obj->madv = I915_MADV_WILLNEED; |
| 4335 | |
| 4336 | trace_i915_gem_object_create(&obj->base); |
| 4337 | |
| 4338 | return &obj->base; |
Daniel Vetter | ac52bc5 | 2010-04-09 19:05:06 +0000 | [diff] [blame] | 4339 | } |
| 4340 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4341 | int i915_gem_init_object(struct drm_gem_object *obj) |
| 4342 | { |
Daniel Vetter | c397b90 | 2010-04-09 19:05:07 +0000 | [diff] [blame] | 4343 | BUG(); |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 4344 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4345 | return 0; |
| 4346 | } |
| 4347 | |
Chris Wilson | be72615 | 2010-07-23 23:18:50 +0100 | [diff] [blame] | 4348 | static void i915_gem_free_object_tail(struct drm_gem_object *obj) |
| 4349 | { |
| 4350 | struct drm_device *dev = obj->dev; |
| 4351 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 4352 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
| 4353 | int ret; |
| 4354 | |
| 4355 | ret = i915_gem_object_unbind(obj); |
| 4356 | if (ret == -ERESTARTSYS) { |
| 4357 | list_move(&obj_priv->list, |
| 4358 | &dev_priv->mm.deferred_free_list); |
| 4359 | return; |
| 4360 | } |
| 4361 | |
| 4362 | if (obj_priv->mmap_offset) |
| 4363 | i915_gem_free_mmap_offset(obj); |
| 4364 | |
| 4365 | drm_gem_object_release(obj); |
| 4366 | |
| 4367 | kfree(obj_priv->page_cpu_valid); |
| 4368 | kfree(obj_priv->bit_17); |
| 4369 | kfree(obj_priv); |
| 4370 | } |
| 4371 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4372 | void i915_gem_free_object(struct drm_gem_object *obj) |
| 4373 | { |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 4374 | struct drm_device *dev = obj->dev; |
Daniel Vetter | 23010e4 | 2010-03-08 13:35:02 +0100 | [diff] [blame] | 4375 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4376 | |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 4377 | trace_i915_gem_object_destroy(obj); |
| 4378 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4379 | while (obj_priv->pin_count > 0) |
| 4380 | i915_gem_object_unpin(obj); |
| 4381 | |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4382 | if (obj_priv->phys_obj) |
| 4383 | i915_gem_detach_phys_object(dev, obj); |
| 4384 | |
Chris Wilson | be72615 | 2010-07-23 23:18:50 +0100 | [diff] [blame] | 4385 | i915_gem_free_object_tail(obj); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4386 | } |
| 4387 | |
Jesse Barnes | 5669fca | 2009-02-17 15:13:31 -0800 | [diff] [blame] | 4388 | int |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4389 | i915_gem_idle(struct drm_device *dev) |
| 4390 | { |
| 4391 | drm_i915_private_t *dev_priv = dev->dev_private; |
Chris Wilson | 29105cc | 2010-01-07 10:39:13 +0000 | [diff] [blame] | 4392 | int ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4393 | |
Keith Packard | 6dbe277 | 2008-10-14 21:41:13 -0700 | [diff] [blame] | 4394 | mutex_lock(&dev->struct_mutex); |
| 4395 | |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 4396 | if (dev_priv->mm.suspended || |
Zou Nan hai | d1b851f | 2010-05-21 09:08:57 +0800 | [diff] [blame] | 4397 | (dev_priv->render_ring.gem_object == NULL) || |
| 4398 | (HAS_BSD(dev) && |
| 4399 | dev_priv->bsd_ring.gem_object == NULL)) { |
Keith Packard | 6dbe277 | 2008-10-14 21:41:13 -0700 | [diff] [blame] | 4400 | mutex_unlock(&dev->struct_mutex); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4401 | return 0; |
Keith Packard | 6dbe277 | 2008-10-14 21:41:13 -0700 | [diff] [blame] | 4402 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4403 | |
Chris Wilson | 29105cc | 2010-01-07 10:39:13 +0000 | [diff] [blame] | 4404 | ret = i915_gpu_idle(dev); |
Keith Packard | 6dbe277 | 2008-10-14 21:41:13 -0700 | [diff] [blame] | 4405 | if (ret) { |
| 4406 | mutex_unlock(&dev->struct_mutex); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4407 | return ret; |
Keith Packard | 6dbe277 | 2008-10-14 21:41:13 -0700 | [diff] [blame] | 4408 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4409 | |
Chris Wilson | 29105cc | 2010-01-07 10:39:13 +0000 | [diff] [blame] | 4410 | /* Under UMS, be paranoid and evict. */ |
| 4411 | if (!drm_core_check_feature(dev, DRIVER_MODESET)) { |
Chris Wilson | b47eb4a | 2010-08-07 11:01:23 +0100 | [diff] [blame] | 4412 | ret = i915_gem_evict_inactive(dev); |
Chris Wilson | 29105cc | 2010-01-07 10:39:13 +0000 | [diff] [blame] | 4413 | if (ret) { |
| 4414 | mutex_unlock(&dev->struct_mutex); |
| 4415 | return ret; |
| 4416 | } |
| 4417 | } |
| 4418 | |
| 4419 | /* Hack! Don't let anybody do execbuf while we don't control the chip. |
| 4420 | * We need to replace this with a semaphore, or something. |
| 4421 | * And not confound mm.suspended! |
| 4422 | */ |
| 4423 | dev_priv->mm.suspended = 1; |
Daniel Vetter | bc0c7f1 | 2010-08-20 18:18:48 +0200 | [diff] [blame] | 4424 | del_timer_sync(&dev_priv->hangcheck_timer); |
Chris Wilson | 29105cc | 2010-01-07 10:39:13 +0000 | [diff] [blame] | 4425 | |
| 4426 | i915_kernel_lost_context(dev); |
Keith Packard | 6dbe277 | 2008-10-14 21:41:13 -0700 | [diff] [blame] | 4427 | i915_gem_cleanup_ringbuffer(dev); |
Chris Wilson | 29105cc | 2010-01-07 10:39:13 +0000 | [diff] [blame] | 4428 | |
Keith Packard | 6dbe277 | 2008-10-14 21:41:13 -0700 | [diff] [blame] | 4429 | mutex_unlock(&dev->struct_mutex); |
| 4430 | |
Chris Wilson | 29105cc | 2010-01-07 10:39:13 +0000 | [diff] [blame] | 4431 | /* Cancel the retire work handler, which should be idle now. */ |
| 4432 | cancel_delayed_work_sync(&dev_priv->mm.retire_work); |
| 4433 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4434 | return 0; |
| 4435 | } |
| 4436 | |
Jesse Barnes | e552eb7 | 2010-04-21 11:39:23 -0700 | [diff] [blame] | 4437 | /* |
| 4438 | * 965+ support PIPE_CONTROL commands, which provide finer grained control |
| 4439 | * over cache flushing. |
| 4440 | */ |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 4441 | static int |
Jesse Barnes | e552eb7 | 2010-04-21 11:39:23 -0700 | [diff] [blame] | 4442 | i915_gem_init_pipe_control(struct drm_device *dev) |
| 4443 | { |
| 4444 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 4445 | struct drm_gem_object *obj; |
| 4446 | struct drm_i915_gem_object *obj_priv; |
| 4447 | int ret; |
| 4448 | |
Eric Anholt | 34dc4d4 | 2010-05-07 14:30:03 -0700 | [diff] [blame] | 4449 | obj = i915_gem_alloc_object(dev, 4096); |
Jesse Barnes | e552eb7 | 2010-04-21 11:39:23 -0700 | [diff] [blame] | 4450 | if (obj == NULL) { |
| 4451 | DRM_ERROR("Failed to allocate seqno page\n"); |
| 4452 | ret = -ENOMEM; |
| 4453 | goto err; |
| 4454 | } |
| 4455 | obj_priv = to_intel_bo(obj); |
| 4456 | obj_priv->agp_type = AGP_USER_CACHED_MEMORY; |
| 4457 | |
| 4458 | ret = i915_gem_object_pin(obj, 4096); |
| 4459 | if (ret) |
| 4460 | goto err_unref; |
| 4461 | |
| 4462 | dev_priv->seqno_gfx_addr = obj_priv->gtt_offset; |
| 4463 | dev_priv->seqno_page = kmap(obj_priv->pages[0]); |
| 4464 | if (dev_priv->seqno_page == NULL) |
| 4465 | goto err_unpin; |
| 4466 | |
| 4467 | dev_priv->seqno_obj = obj; |
| 4468 | memset(dev_priv->seqno_page, 0, PAGE_SIZE); |
| 4469 | |
| 4470 | return 0; |
| 4471 | |
| 4472 | err_unpin: |
| 4473 | i915_gem_object_unpin(obj); |
| 4474 | err_unref: |
| 4475 | drm_gem_object_unreference(obj); |
| 4476 | err: |
| 4477 | return ret; |
| 4478 | } |
| 4479 | |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 4480 | |
| 4481 | static void |
Jesse Barnes | e552eb7 | 2010-04-21 11:39:23 -0700 | [diff] [blame] | 4482 | i915_gem_cleanup_pipe_control(struct drm_device *dev) |
| 4483 | { |
| 4484 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 4485 | struct drm_gem_object *obj; |
| 4486 | struct drm_i915_gem_object *obj_priv; |
| 4487 | |
| 4488 | obj = dev_priv->seqno_obj; |
| 4489 | obj_priv = to_intel_bo(obj); |
| 4490 | kunmap(obj_priv->pages[0]); |
| 4491 | i915_gem_object_unpin(obj); |
| 4492 | drm_gem_object_unreference(obj); |
| 4493 | dev_priv->seqno_obj = NULL; |
| 4494 | |
| 4495 | dev_priv->seqno_page = NULL; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4496 | } |
| 4497 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4498 | int |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 4499 | i915_gem_init_ringbuffer(struct drm_device *dev) |
| 4500 | { |
| 4501 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 4502 | int ret; |
Chris Wilson | 68f95ba | 2010-05-27 13:18:22 +0100 | [diff] [blame] | 4503 | |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 4504 | dev_priv->render_ring = render_ring; |
Chris Wilson | 68f95ba | 2010-05-27 13:18:22 +0100 | [diff] [blame] | 4505 | |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 4506 | if (!I915_NEED_GFX_HWS(dev)) { |
| 4507 | dev_priv->render_ring.status_page.page_addr |
| 4508 | = dev_priv->status_page_dmah->vaddr; |
| 4509 | memset(dev_priv->render_ring.status_page.page_addr, |
| 4510 | 0, PAGE_SIZE); |
| 4511 | } |
Chris Wilson | 68f95ba | 2010-05-27 13:18:22 +0100 | [diff] [blame] | 4512 | |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 4513 | if (HAS_PIPE_CONTROL(dev)) { |
| 4514 | ret = i915_gem_init_pipe_control(dev); |
| 4515 | if (ret) |
| 4516 | return ret; |
| 4517 | } |
Chris Wilson | 68f95ba | 2010-05-27 13:18:22 +0100 | [diff] [blame] | 4518 | |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 4519 | ret = intel_init_ring_buffer(dev, &dev_priv->render_ring); |
Chris Wilson | 68f95ba | 2010-05-27 13:18:22 +0100 | [diff] [blame] | 4520 | if (ret) |
| 4521 | goto cleanup_pipe_control; |
| 4522 | |
| 4523 | if (HAS_BSD(dev)) { |
Zou Nan hai | d1b851f | 2010-05-21 09:08:57 +0800 | [diff] [blame] | 4524 | dev_priv->bsd_ring = bsd_ring; |
| 4525 | ret = intel_init_ring_buffer(dev, &dev_priv->bsd_ring); |
Chris Wilson | 68f95ba | 2010-05-27 13:18:22 +0100 | [diff] [blame] | 4526 | if (ret) |
| 4527 | goto cleanup_render_ring; |
Zou Nan hai | d1b851f | 2010-05-21 09:08:57 +0800 | [diff] [blame] | 4528 | } |
Chris Wilson | 68f95ba | 2010-05-27 13:18:22 +0100 | [diff] [blame] | 4529 | |
Chris Wilson | 6f392d548 | 2010-08-07 11:01:22 +0100 | [diff] [blame] | 4530 | dev_priv->next_seqno = 1; |
| 4531 | |
Chris Wilson | 68f95ba | 2010-05-27 13:18:22 +0100 | [diff] [blame] | 4532 | return 0; |
| 4533 | |
| 4534 | cleanup_render_ring: |
| 4535 | intel_cleanup_ring_buffer(dev, &dev_priv->render_ring); |
| 4536 | cleanup_pipe_control: |
| 4537 | if (HAS_PIPE_CONTROL(dev)) |
| 4538 | i915_gem_cleanup_pipe_control(dev); |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 4539 | return ret; |
| 4540 | } |
| 4541 | |
| 4542 | void |
| 4543 | i915_gem_cleanup_ringbuffer(struct drm_device *dev) |
| 4544 | { |
| 4545 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 4546 | |
| 4547 | intel_cleanup_ring_buffer(dev, &dev_priv->render_ring); |
Zou Nan hai | d1b851f | 2010-05-21 09:08:57 +0800 | [diff] [blame] | 4548 | if (HAS_BSD(dev)) |
| 4549 | intel_cleanup_ring_buffer(dev, &dev_priv->bsd_ring); |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 4550 | if (HAS_PIPE_CONTROL(dev)) |
| 4551 | i915_gem_cleanup_pipe_control(dev); |
| 4552 | } |
| 4553 | |
| 4554 | int |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4555 | i915_gem_entervt_ioctl(struct drm_device *dev, void *data, |
| 4556 | struct drm_file *file_priv) |
| 4557 | { |
| 4558 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 4559 | int ret; |
| 4560 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 4561 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
| 4562 | return 0; |
| 4563 | |
Ben Gamari | ba1234d | 2009-09-14 17:48:47 -0400 | [diff] [blame] | 4564 | if (atomic_read(&dev_priv->mm.wedged)) { |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4565 | DRM_ERROR("Reenabling wedged hardware, good luck\n"); |
Ben Gamari | ba1234d | 2009-09-14 17:48:47 -0400 | [diff] [blame] | 4566 | atomic_set(&dev_priv->mm.wedged, 0); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4567 | } |
| 4568 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4569 | mutex_lock(&dev->struct_mutex); |
Eric Anholt | 9bb2d6f | 2008-12-23 18:42:32 -0800 | [diff] [blame] | 4570 | dev_priv->mm.suspended = 0; |
| 4571 | |
| 4572 | ret = i915_gem_init_ringbuffer(dev); |
Wu Fengguang | d816f6a | 2009-04-18 10:43:32 +0800 | [diff] [blame] | 4573 | if (ret != 0) { |
| 4574 | mutex_unlock(&dev->struct_mutex); |
Eric Anholt | 9bb2d6f | 2008-12-23 18:42:32 -0800 | [diff] [blame] | 4575 | return ret; |
Wu Fengguang | d816f6a | 2009-04-18 10:43:32 +0800 | [diff] [blame] | 4576 | } |
Eric Anholt | 9bb2d6f | 2008-12-23 18:42:32 -0800 | [diff] [blame] | 4577 | |
Carl Worth | 5e118f4 | 2009-03-20 11:54:25 -0700 | [diff] [blame] | 4578 | spin_lock(&dev_priv->mm.active_list_lock); |
Zou Nan hai | 852835f | 2010-05-21 09:08:56 +0800 | [diff] [blame] | 4579 | BUG_ON(!list_empty(&dev_priv->render_ring.active_list)); |
Zou Nan hai | d1b851f | 2010-05-21 09:08:57 +0800 | [diff] [blame] | 4580 | BUG_ON(HAS_BSD(dev) && !list_empty(&dev_priv->bsd_ring.active_list)); |
Carl Worth | 5e118f4 | 2009-03-20 11:54:25 -0700 | [diff] [blame] | 4581 | spin_unlock(&dev_priv->mm.active_list_lock); |
| 4582 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4583 | BUG_ON(!list_empty(&dev_priv->mm.flushing_list)); |
| 4584 | BUG_ON(!list_empty(&dev_priv->mm.inactive_list)); |
Zou Nan hai | 852835f | 2010-05-21 09:08:56 +0800 | [diff] [blame] | 4585 | BUG_ON(!list_empty(&dev_priv->render_ring.request_list)); |
Zou Nan hai | d1b851f | 2010-05-21 09:08:57 +0800 | [diff] [blame] | 4586 | BUG_ON(HAS_BSD(dev) && !list_empty(&dev_priv->bsd_ring.request_list)); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4587 | mutex_unlock(&dev->struct_mutex); |
Kristian Høgsberg | dbb19d3 | 2008-08-20 11:04:27 -0400 | [diff] [blame] | 4588 | |
Chris Wilson | 5f35308 | 2010-06-07 14:03:03 +0100 | [diff] [blame] | 4589 | ret = drm_irq_install(dev); |
| 4590 | if (ret) |
| 4591 | goto cleanup_ringbuffer; |
Kristian Høgsberg | dbb19d3 | 2008-08-20 11:04:27 -0400 | [diff] [blame] | 4592 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4593 | return 0; |
Chris Wilson | 5f35308 | 2010-06-07 14:03:03 +0100 | [diff] [blame] | 4594 | |
| 4595 | cleanup_ringbuffer: |
| 4596 | mutex_lock(&dev->struct_mutex); |
| 4597 | i915_gem_cleanup_ringbuffer(dev); |
| 4598 | dev_priv->mm.suspended = 1; |
| 4599 | mutex_unlock(&dev->struct_mutex); |
| 4600 | |
| 4601 | return ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4602 | } |
| 4603 | |
| 4604 | int |
| 4605 | i915_gem_leavevt_ioctl(struct drm_device *dev, void *data, |
| 4606 | struct drm_file *file_priv) |
| 4607 | { |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 4608 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
| 4609 | return 0; |
| 4610 | |
Kristian Høgsberg | dbb19d3 | 2008-08-20 11:04:27 -0400 | [diff] [blame] | 4611 | drm_irq_uninstall(dev); |
Linus Torvalds | e6890f6 | 2009-09-08 17:09:24 -0700 | [diff] [blame] | 4612 | return i915_gem_idle(dev); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4613 | } |
| 4614 | |
| 4615 | void |
| 4616 | i915_gem_lastclose(struct drm_device *dev) |
| 4617 | { |
| 4618 | int ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4619 | |
Eric Anholt | e806b49 | 2009-01-22 09:56:58 -0800 | [diff] [blame] | 4620 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
| 4621 | return; |
| 4622 | |
Keith Packard | 6dbe277 | 2008-10-14 21:41:13 -0700 | [diff] [blame] | 4623 | ret = i915_gem_idle(dev); |
| 4624 | if (ret) |
| 4625 | DRM_ERROR("failed to idle hardware: %d\n", ret); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4626 | } |
| 4627 | |
| 4628 | void |
| 4629 | i915_gem_load(struct drm_device *dev) |
| 4630 | { |
Grégoire Henry | b5aa8a0 | 2009-06-23 15:41:02 +0200 | [diff] [blame] | 4631 | int i; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4632 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 4633 | |
Carl Worth | 5e118f4 | 2009-03-20 11:54:25 -0700 | [diff] [blame] | 4634 | spin_lock_init(&dev_priv->mm.active_list_lock); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4635 | INIT_LIST_HEAD(&dev_priv->mm.flushing_list); |
Daniel Vetter | 99fcb76 | 2010-02-07 16:20:18 +0100 | [diff] [blame] | 4636 | INIT_LIST_HEAD(&dev_priv->mm.gpu_write_list); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4637 | INIT_LIST_HEAD(&dev_priv->mm.inactive_list); |
Eric Anholt | a09ba7f | 2009-08-29 12:49:51 -0700 | [diff] [blame] | 4638 | INIT_LIST_HEAD(&dev_priv->mm.fence_list); |
Chris Wilson | be72615 | 2010-07-23 23:18:50 +0100 | [diff] [blame] | 4639 | INIT_LIST_HEAD(&dev_priv->mm.deferred_free_list); |
Zou Nan hai | 852835f | 2010-05-21 09:08:56 +0800 | [diff] [blame] | 4640 | INIT_LIST_HEAD(&dev_priv->render_ring.active_list); |
| 4641 | INIT_LIST_HEAD(&dev_priv->render_ring.request_list); |
Zou Nan hai | d1b851f | 2010-05-21 09:08:57 +0800 | [diff] [blame] | 4642 | if (HAS_BSD(dev)) { |
| 4643 | INIT_LIST_HEAD(&dev_priv->bsd_ring.active_list); |
| 4644 | INIT_LIST_HEAD(&dev_priv->bsd_ring.request_list); |
| 4645 | } |
Daniel Vetter | 007cc8a | 2010-04-28 11:02:31 +0200 | [diff] [blame] | 4646 | for (i = 0; i < 16; i++) |
| 4647 | INIT_LIST_HEAD(&dev_priv->fence_regs[i].lru_list); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4648 | INIT_DELAYED_WORK(&dev_priv->mm.retire_work, |
| 4649 | i915_gem_retire_work_handler); |
Chris Wilson | 3116971 | 2009-09-14 16:50:28 +0100 | [diff] [blame] | 4650 | spin_lock(&shrink_list_lock); |
| 4651 | list_add(&dev_priv->mm.shrink_list, &shrink_list); |
| 4652 | spin_unlock(&shrink_list_lock); |
| 4653 | |
Dave Airlie | 9440012 | 2010-07-20 13:15:31 +1000 | [diff] [blame] | 4654 | /* On GEN3 we really need to make sure the ARB C3 LP bit is set */ |
| 4655 | if (IS_GEN3(dev)) { |
| 4656 | u32 tmp = I915_READ(MI_ARB_STATE); |
| 4657 | if (!(tmp & MI_ARB_C3_LP_WRITE_ENABLE)) { |
| 4658 | /* arb state is a masked write, so set bit + bit in mask */ |
| 4659 | tmp = MI_ARB_C3_LP_WRITE_ENABLE | (MI_ARB_C3_LP_WRITE_ENABLE << MI_ARB_MASK_SHIFT); |
| 4660 | I915_WRITE(MI_ARB_STATE, tmp); |
| 4661 | } |
| 4662 | } |
| 4663 | |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 4664 | /* Old X drivers will take 0-2 for front, back, depth buffers */ |
Eric Anholt | b397c83 | 2010-01-26 09:43:10 -0800 | [diff] [blame] | 4665 | if (!drm_core_check_feature(dev, DRIVER_MODESET)) |
| 4666 | dev_priv->fence_reg_start = 3; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 4667 | |
Jesse Barnes | 0f973f2 | 2009-01-26 17:10:45 -0800 | [diff] [blame] | 4668 | if (IS_I965G(dev) || IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 4669 | dev_priv->num_fence_regs = 16; |
| 4670 | else |
| 4671 | dev_priv->num_fence_regs = 8; |
| 4672 | |
Grégoire Henry | b5aa8a0 | 2009-06-23 15:41:02 +0200 | [diff] [blame] | 4673 | /* Initialize fence registers to zero */ |
| 4674 | if (IS_I965G(dev)) { |
| 4675 | for (i = 0; i < 16; i++) |
| 4676 | I915_WRITE64(FENCE_REG_965_0 + (i * 8), 0); |
| 4677 | } else { |
| 4678 | for (i = 0; i < 8; i++) |
| 4679 | I915_WRITE(FENCE_REG_830_0 + (i * 4), 0); |
| 4680 | if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) |
| 4681 | for (i = 0; i < 8; i++) |
| 4682 | I915_WRITE(FENCE_REG_945_8 + (i * 4), 0); |
| 4683 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4684 | i915_gem_detect_bit_6_swizzle(dev); |
Kristian Høgsberg | 6b95a20 | 2009-11-18 11:25:18 -0500 | [diff] [blame] | 4685 | init_waitqueue_head(&dev_priv->pending_flip_queue); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4686 | } |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4687 | |
| 4688 | /* |
| 4689 | * Create a physically contiguous memory object for this object |
| 4690 | * e.g. for cursor + overlay regs |
| 4691 | */ |
| 4692 | int i915_gem_init_phys_object(struct drm_device *dev, |
Chris Wilson | 6eeefaf | 2010-08-07 11:01:39 +0100 | [diff] [blame] | 4693 | int id, int size, int align) |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4694 | { |
| 4695 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 4696 | struct drm_i915_gem_phys_object *phys_obj; |
| 4697 | int ret; |
| 4698 | |
| 4699 | if (dev_priv->mm.phys_objs[id - 1] || !size) |
| 4700 | return 0; |
| 4701 | |
Eric Anholt | 9a298b2 | 2009-03-24 12:23:04 -0700 | [diff] [blame] | 4702 | phys_obj = kzalloc(sizeof(struct drm_i915_gem_phys_object), GFP_KERNEL); |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4703 | if (!phys_obj) |
| 4704 | return -ENOMEM; |
| 4705 | |
| 4706 | phys_obj->id = id; |
| 4707 | |
Chris Wilson | 6eeefaf | 2010-08-07 11:01:39 +0100 | [diff] [blame] | 4708 | phys_obj->handle = drm_pci_alloc(dev, size, align); |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4709 | if (!phys_obj->handle) { |
| 4710 | ret = -ENOMEM; |
| 4711 | goto kfree_obj; |
| 4712 | } |
| 4713 | #ifdef CONFIG_X86 |
| 4714 | set_memory_wc((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE); |
| 4715 | #endif |
| 4716 | |
| 4717 | dev_priv->mm.phys_objs[id - 1] = phys_obj; |
| 4718 | |
| 4719 | return 0; |
| 4720 | kfree_obj: |
Eric Anholt | 9a298b2 | 2009-03-24 12:23:04 -0700 | [diff] [blame] | 4721 | kfree(phys_obj); |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4722 | return ret; |
| 4723 | } |
| 4724 | |
| 4725 | void i915_gem_free_phys_object(struct drm_device *dev, int id) |
| 4726 | { |
| 4727 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 4728 | struct drm_i915_gem_phys_object *phys_obj; |
| 4729 | |
| 4730 | if (!dev_priv->mm.phys_objs[id - 1]) |
| 4731 | return; |
| 4732 | |
| 4733 | phys_obj = dev_priv->mm.phys_objs[id - 1]; |
| 4734 | if (phys_obj->cur_obj) { |
| 4735 | i915_gem_detach_phys_object(dev, phys_obj->cur_obj); |
| 4736 | } |
| 4737 | |
| 4738 | #ifdef CONFIG_X86 |
| 4739 | set_memory_wb((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE); |
| 4740 | #endif |
| 4741 | drm_pci_free(dev, phys_obj->handle); |
| 4742 | kfree(phys_obj); |
| 4743 | dev_priv->mm.phys_objs[id - 1] = NULL; |
| 4744 | } |
| 4745 | |
| 4746 | void i915_gem_free_all_phys_object(struct drm_device *dev) |
| 4747 | { |
| 4748 | int i; |
| 4749 | |
Dave Airlie | 260883c | 2009-01-22 17:58:49 +1000 | [diff] [blame] | 4750 | for (i = I915_GEM_PHYS_CURSOR_0; i <= I915_MAX_PHYS_OBJECT; i++) |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4751 | i915_gem_free_phys_object(dev, i); |
| 4752 | } |
| 4753 | |
| 4754 | void i915_gem_detach_phys_object(struct drm_device *dev, |
| 4755 | struct drm_gem_object *obj) |
| 4756 | { |
| 4757 | struct drm_i915_gem_object *obj_priv; |
| 4758 | int i; |
| 4759 | int ret; |
| 4760 | int page_count; |
| 4761 | |
Daniel Vetter | 23010e4 | 2010-03-08 13:35:02 +0100 | [diff] [blame] | 4762 | obj_priv = to_intel_bo(obj); |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4763 | if (!obj_priv->phys_obj) |
| 4764 | return; |
| 4765 | |
Chris Wilson | 4bdadb9 | 2010-01-27 13:36:32 +0000 | [diff] [blame] | 4766 | ret = i915_gem_object_get_pages(obj, 0); |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4767 | if (ret) |
| 4768 | goto out; |
| 4769 | |
| 4770 | page_count = obj->size / PAGE_SIZE; |
| 4771 | |
| 4772 | for (i = 0; i < page_count; i++) { |
Eric Anholt | 856fa19 | 2009-03-19 14:10:50 -0700 | [diff] [blame] | 4773 | char *dst = kmap_atomic(obj_priv->pages[i], KM_USER0); |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4774 | char *src = obj_priv->phys_obj->handle->vaddr + (i * PAGE_SIZE); |
| 4775 | |
| 4776 | memcpy(dst, src, PAGE_SIZE); |
| 4777 | kunmap_atomic(dst, KM_USER0); |
| 4778 | } |
Eric Anholt | 856fa19 | 2009-03-19 14:10:50 -0700 | [diff] [blame] | 4779 | drm_clflush_pages(obj_priv->pages, page_count); |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4780 | drm_agp_chipset_flush(dev); |
Chris Wilson | d78b47b | 2009-06-17 21:52:49 +0100 | [diff] [blame] | 4781 | |
| 4782 | i915_gem_object_put_pages(obj); |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4783 | out: |
| 4784 | obj_priv->phys_obj->cur_obj = NULL; |
| 4785 | obj_priv->phys_obj = NULL; |
| 4786 | } |
| 4787 | |
| 4788 | int |
| 4789 | i915_gem_attach_phys_object(struct drm_device *dev, |
Chris Wilson | 6eeefaf | 2010-08-07 11:01:39 +0100 | [diff] [blame] | 4790 | struct drm_gem_object *obj, |
| 4791 | int id, |
| 4792 | int align) |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4793 | { |
| 4794 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 4795 | struct drm_i915_gem_object *obj_priv; |
| 4796 | int ret = 0; |
| 4797 | int page_count; |
| 4798 | int i; |
| 4799 | |
| 4800 | if (id > I915_MAX_PHYS_OBJECT) |
| 4801 | return -EINVAL; |
| 4802 | |
Daniel Vetter | 23010e4 | 2010-03-08 13:35:02 +0100 | [diff] [blame] | 4803 | obj_priv = to_intel_bo(obj); |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4804 | |
| 4805 | if (obj_priv->phys_obj) { |
| 4806 | if (obj_priv->phys_obj->id == id) |
| 4807 | return 0; |
| 4808 | i915_gem_detach_phys_object(dev, obj); |
| 4809 | } |
| 4810 | |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4811 | /* create a new object */ |
| 4812 | if (!dev_priv->mm.phys_objs[id - 1]) { |
| 4813 | ret = i915_gem_init_phys_object(dev, id, |
Chris Wilson | 6eeefaf | 2010-08-07 11:01:39 +0100 | [diff] [blame] | 4814 | obj->size, align); |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4815 | if (ret) { |
Linus Torvalds | aeb565d | 2009-01-26 10:01:53 -0800 | [diff] [blame] | 4816 | DRM_ERROR("failed to init phys object %d size: %zu\n", id, obj->size); |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4817 | goto out; |
| 4818 | } |
| 4819 | } |
| 4820 | |
| 4821 | /* bind to the object */ |
| 4822 | obj_priv->phys_obj = dev_priv->mm.phys_objs[id - 1]; |
| 4823 | obj_priv->phys_obj->cur_obj = obj; |
| 4824 | |
Chris Wilson | 4bdadb9 | 2010-01-27 13:36:32 +0000 | [diff] [blame] | 4825 | ret = i915_gem_object_get_pages(obj, 0); |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4826 | if (ret) { |
| 4827 | DRM_ERROR("failed to get page list\n"); |
| 4828 | goto out; |
| 4829 | } |
| 4830 | |
| 4831 | page_count = obj->size / PAGE_SIZE; |
| 4832 | |
| 4833 | for (i = 0; i < page_count; i++) { |
Eric Anholt | 856fa19 | 2009-03-19 14:10:50 -0700 | [diff] [blame] | 4834 | char *src = kmap_atomic(obj_priv->pages[i], KM_USER0); |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4835 | char *dst = obj_priv->phys_obj->handle->vaddr + (i * PAGE_SIZE); |
| 4836 | |
| 4837 | memcpy(dst, src, PAGE_SIZE); |
| 4838 | kunmap_atomic(src, KM_USER0); |
| 4839 | } |
| 4840 | |
Chris Wilson | d78b47b | 2009-06-17 21:52:49 +0100 | [diff] [blame] | 4841 | i915_gem_object_put_pages(obj); |
| 4842 | |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4843 | return 0; |
| 4844 | out: |
| 4845 | return ret; |
| 4846 | } |
| 4847 | |
| 4848 | static int |
| 4849 | i915_gem_phys_pwrite(struct drm_device *dev, struct drm_gem_object *obj, |
| 4850 | struct drm_i915_gem_pwrite *args, |
| 4851 | struct drm_file *file_priv) |
| 4852 | { |
Daniel Vetter | 23010e4 | 2010-03-08 13:35:02 +0100 | [diff] [blame] | 4853 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4854 | void *obj_addr; |
| 4855 | int ret; |
| 4856 | char __user *user_data; |
| 4857 | |
| 4858 | user_data = (char __user *) (uintptr_t) args->data_ptr; |
| 4859 | obj_addr = obj_priv->phys_obj->handle->vaddr + args->offset; |
| 4860 | |
Zhao Yakui | 44d98a6 | 2009-10-09 11:39:40 +0800 | [diff] [blame] | 4861 | DRM_DEBUG_DRIVER("obj_addr %p, %lld\n", obj_addr, args->size); |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4862 | ret = copy_from_user(obj_addr, user_data, args->size); |
| 4863 | if (ret) |
| 4864 | return -EFAULT; |
| 4865 | |
| 4866 | drm_agp_chipset_flush(dev); |
| 4867 | return 0; |
| 4868 | } |
Eric Anholt | b962442 | 2009-06-03 07:27:35 +0000 | [diff] [blame] | 4869 | |
| 4870 | void i915_gem_release(struct drm_device * dev, struct drm_file *file_priv) |
| 4871 | { |
| 4872 | struct drm_i915_file_private *i915_file_priv = file_priv->driver_priv; |
| 4873 | |
| 4874 | /* Clean up our request list when the client is going away, so that |
| 4875 | * later retire_requests won't dereference our soon-to-be-gone |
| 4876 | * file_priv. |
| 4877 | */ |
| 4878 | mutex_lock(&dev->struct_mutex); |
| 4879 | while (!list_empty(&i915_file_priv->mm.request_list)) |
| 4880 | list_del_init(i915_file_priv->mm.request_list.next); |
| 4881 | mutex_unlock(&dev->struct_mutex); |
| 4882 | } |
Chris Wilson | 3116971 | 2009-09-14 16:50:28 +0100 | [diff] [blame] | 4883 | |
Chris Wilson | 3116971 | 2009-09-14 16:50:28 +0100 | [diff] [blame] | 4884 | static int |
Chris Wilson | 1637ef4 | 2010-04-20 17:10:35 +0100 | [diff] [blame] | 4885 | i915_gpu_is_active(struct drm_device *dev) |
| 4886 | { |
| 4887 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 4888 | int lists_empty; |
| 4889 | |
| 4890 | spin_lock(&dev_priv->mm.active_list_lock); |
| 4891 | lists_empty = list_empty(&dev_priv->mm.flushing_list) && |
Zou Nan hai | 852835f | 2010-05-21 09:08:56 +0800 | [diff] [blame] | 4892 | list_empty(&dev_priv->render_ring.active_list); |
Zou Nan hai | d1b851f | 2010-05-21 09:08:57 +0800 | [diff] [blame] | 4893 | if (HAS_BSD(dev)) |
| 4894 | lists_empty &= list_empty(&dev_priv->bsd_ring.active_list); |
Chris Wilson | 1637ef4 | 2010-04-20 17:10:35 +0100 | [diff] [blame] | 4895 | spin_unlock(&dev_priv->mm.active_list_lock); |
| 4896 | |
| 4897 | return !lists_empty; |
| 4898 | } |
| 4899 | |
| 4900 | static int |
Dave Chinner | 7f8275d | 2010-07-19 14:56:17 +1000 | [diff] [blame] | 4901 | i915_gem_shrink(struct shrinker *shrink, int nr_to_scan, gfp_t gfp_mask) |
Chris Wilson | 3116971 | 2009-09-14 16:50:28 +0100 | [diff] [blame] | 4902 | { |
| 4903 | drm_i915_private_t *dev_priv, *next_dev; |
| 4904 | struct drm_i915_gem_object *obj_priv, *next_obj; |
| 4905 | int cnt = 0; |
| 4906 | int would_deadlock = 1; |
| 4907 | |
| 4908 | /* "fast-path" to count number of available objects */ |
| 4909 | if (nr_to_scan == 0) { |
| 4910 | spin_lock(&shrink_list_lock); |
| 4911 | list_for_each_entry(dev_priv, &shrink_list, mm.shrink_list) { |
| 4912 | struct drm_device *dev = dev_priv->dev; |
| 4913 | |
| 4914 | if (mutex_trylock(&dev->struct_mutex)) { |
| 4915 | list_for_each_entry(obj_priv, |
| 4916 | &dev_priv->mm.inactive_list, |
| 4917 | list) |
| 4918 | cnt++; |
| 4919 | mutex_unlock(&dev->struct_mutex); |
| 4920 | } |
| 4921 | } |
| 4922 | spin_unlock(&shrink_list_lock); |
| 4923 | |
| 4924 | return (cnt / 100) * sysctl_vfs_cache_pressure; |
| 4925 | } |
| 4926 | |
| 4927 | spin_lock(&shrink_list_lock); |
| 4928 | |
Chris Wilson | 1637ef4 | 2010-04-20 17:10:35 +0100 | [diff] [blame] | 4929 | rescan: |
Chris Wilson | 3116971 | 2009-09-14 16:50:28 +0100 | [diff] [blame] | 4930 | /* first scan for clean buffers */ |
| 4931 | list_for_each_entry_safe(dev_priv, next_dev, |
| 4932 | &shrink_list, mm.shrink_list) { |
| 4933 | struct drm_device *dev = dev_priv->dev; |
| 4934 | |
| 4935 | if (! mutex_trylock(&dev->struct_mutex)) |
| 4936 | continue; |
| 4937 | |
| 4938 | spin_unlock(&shrink_list_lock); |
Chris Wilson | b09a1fe | 2010-07-23 23:18:49 +0100 | [diff] [blame] | 4939 | i915_gem_retire_requests(dev); |
Zou Nan hai | d1b851f | 2010-05-21 09:08:57 +0800 | [diff] [blame] | 4940 | |
Chris Wilson | 3116971 | 2009-09-14 16:50:28 +0100 | [diff] [blame] | 4941 | list_for_each_entry_safe(obj_priv, next_obj, |
| 4942 | &dev_priv->mm.inactive_list, |
| 4943 | list) { |
| 4944 | if (i915_gem_object_is_purgeable(obj_priv)) { |
Daniel Vetter | a8089e8 | 2010-04-09 19:05:09 +0000 | [diff] [blame] | 4945 | i915_gem_object_unbind(&obj_priv->base); |
Chris Wilson | 3116971 | 2009-09-14 16:50:28 +0100 | [diff] [blame] | 4946 | if (--nr_to_scan <= 0) |
| 4947 | break; |
| 4948 | } |
| 4949 | } |
| 4950 | |
| 4951 | spin_lock(&shrink_list_lock); |
| 4952 | mutex_unlock(&dev->struct_mutex); |
| 4953 | |
Chris Wilson | 963b483 | 2009-09-20 23:03:54 +0100 | [diff] [blame] | 4954 | would_deadlock = 0; |
| 4955 | |
Chris Wilson | 3116971 | 2009-09-14 16:50:28 +0100 | [diff] [blame] | 4956 | if (nr_to_scan <= 0) |
| 4957 | break; |
| 4958 | } |
| 4959 | |
| 4960 | /* second pass, evict/count anything still on the inactive list */ |
| 4961 | list_for_each_entry_safe(dev_priv, next_dev, |
| 4962 | &shrink_list, mm.shrink_list) { |
| 4963 | struct drm_device *dev = dev_priv->dev; |
| 4964 | |
| 4965 | if (! mutex_trylock(&dev->struct_mutex)) |
| 4966 | continue; |
| 4967 | |
| 4968 | spin_unlock(&shrink_list_lock); |
| 4969 | |
| 4970 | list_for_each_entry_safe(obj_priv, next_obj, |
| 4971 | &dev_priv->mm.inactive_list, |
| 4972 | list) { |
| 4973 | if (nr_to_scan > 0) { |
Daniel Vetter | a8089e8 | 2010-04-09 19:05:09 +0000 | [diff] [blame] | 4974 | i915_gem_object_unbind(&obj_priv->base); |
Chris Wilson | 3116971 | 2009-09-14 16:50:28 +0100 | [diff] [blame] | 4975 | nr_to_scan--; |
| 4976 | } else |
| 4977 | cnt++; |
| 4978 | } |
| 4979 | |
| 4980 | spin_lock(&shrink_list_lock); |
| 4981 | mutex_unlock(&dev->struct_mutex); |
| 4982 | |
| 4983 | would_deadlock = 0; |
| 4984 | } |
| 4985 | |
Chris Wilson | 1637ef4 | 2010-04-20 17:10:35 +0100 | [diff] [blame] | 4986 | if (nr_to_scan) { |
| 4987 | int active = 0; |
| 4988 | |
| 4989 | /* |
| 4990 | * We are desperate for pages, so as a last resort, wait |
| 4991 | * for the GPU to finish and discard whatever we can. |
| 4992 | * This has a dramatic impact to reduce the number of |
| 4993 | * OOM-killer events whilst running the GPU aggressively. |
| 4994 | */ |
| 4995 | list_for_each_entry(dev_priv, &shrink_list, mm.shrink_list) { |
| 4996 | struct drm_device *dev = dev_priv->dev; |
| 4997 | |
| 4998 | if (!mutex_trylock(&dev->struct_mutex)) |
| 4999 | continue; |
| 5000 | |
| 5001 | spin_unlock(&shrink_list_lock); |
| 5002 | |
| 5003 | if (i915_gpu_is_active(dev)) { |
| 5004 | i915_gpu_idle(dev); |
| 5005 | active++; |
| 5006 | } |
| 5007 | |
| 5008 | spin_lock(&shrink_list_lock); |
| 5009 | mutex_unlock(&dev->struct_mutex); |
| 5010 | } |
| 5011 | |
| 5012 | if (active) |
| 5013 | goto rescan; |
| 5014 | } |
| 5015 | |
Chris Wilson | 3116971 | 2009-09-14 16:50:28 +0100 | [diff] [blame] | 5016 | spin_unlock(&shrink_list_lock); |
| 5017 | |
| 5018 | if (would_deadlock) |
| 5019 | return -1; |
| 5020 | else if (cnt > 0) |
| 5021 | return (cnt / 100) * sysctl_vfs_cache_pressure; |
| 5022 | else |
| 5023 | return 0; |
| 5024 | } |
| 5025 | |
| 5026 | static struct shrinker shrinker = { |
| 5027 | .shrink = i915_gem_shrink, |
| 5028 | .seeks = DEFAULT_SEEKS, |
| 5029 | }; |
| 5030 | |
| 5031 | __init void |
| 5032 | i915_gem_shrinker_init(void) |
| 5033 | { |
| 5034 | register_shrinker(&shrinker); |
| 5035 | } |
| 5036 | |
| 5037 | __exit void |
| 5038 | i915_gem_shrinker_exit(void) |
| 5039 | { |
| 5040 | unregister_shrinker(&shrinker); |
| 5041 | } |