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Dhaval Patel14d46ce2017-01-17 16:28:12 -08001/*
2 * Copyright (C) 2014-2017 The Linux Foundation. All rights reserved.
3 * Copyright (C) 2013 Red Hat
4 * Author: Rob Clark <robdclark@gmail.com>
Narendra Muppalla1b0b3352015-09-29 10:16:51 -07005 *
Dhaval Patel14d46ce2017-01-17 16:28:12 -08006 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published by
8 * the Free Software Foundation.
Narendra Muppalla1b0b3352015-09-29 10:16:51 -07009 *
Dhaval Patel14d46ce2017-01-17 16:28:12 -080010 * This program is distributed in the hope that it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 *
15 * You should have received a copy of the GNU General Public License along with
16 * this program. If not, see <http://www.gnu.org/licenses/>.
Narendra Muppalla1b0b3352015-09-29 10:16:51 -070017 */
Alan Kwong1a00e4d2016-07-18 09:42:30 -040018
19#define pr_fmt(fmt) "[drm:%s:%d] " fmt, __func__, __LINE__
20
Clarence Ip4ce59322016-06-26 22:27:51 -040021#include <linux/debugfs.h>
Alan Kwong4dd64c82017-02-04 18:41:51 -080022#include <linux/dma-buf.h>
Clarence Ip5e2a9222016-06-26 22:38:24 -040023#include <uapi/drm/sde_drm.h>
Benet Clarkd009b1d2016-06-27 14:45:59 -070024#include <uapi/drm/msm_drm_pp.h>
Clarence Ipaa0faf42016-05-30 12:07:48 -040025
26#include "msm_prop.h"
Jeykumar Sankaran2e655032017-02-04 14:05:45 -080027#include "msm_drv.h"
Clarence Ipaa0faf42016-05-30 12:07:48 -040028
Narendra Muppalla1b0b3352015-09-29 10:16:51 -070029#include "sde_kms.h"
Clarence Ipae4e60c2016-06-26 22:44:04 -040030#include "sde_fence.h"
Clarence Ipc475b082016-06-26 09:27:23 -040031#include "sde_formats.h"
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -040032#include "sde_hw_sspp.h"
Jeykumar Sankaran2e655032017-02-04 14:05:45 -080033#include "sde_hw_catalog_format.h"
Alan Kwong1a00e4d2016-07-18 09:42:30 -040034#include "sde_trace.h"
Dhaval Patel48c76022016-09-01 17:51:23 -070035#include "sde_crtc.h"
Lloyd Atkinson8772e202016-09-26 17:52:16 -040036#include "sde_vbif.h"
Alan Kwong83285fb2016-10-21 20:51:17 -040037#include "sde_plane.h"
Benet Clarkd009b1d2016-06-27 14:45:59 -070038#include "sde_color_processing.h"
Alan Kwong4dd64c82017-02-04 18:41:51 -080039#include "sde_hw_rot.h"
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -040040
Clarence Ip56902792017-03-17 15:22:07 -040041static bool suspend_blank = true;
42module_param(suspend_blank, bool, 0400);
43MODULE_PARM_DESC(suspend_blank,
44 "If set, active planes will force their outputs to black,\n"
45 "by temporarily enabling the color fill, when recovering\n"
46 "from a system resume instead of attempting to display the\n"
47 "last provided frame buffer.");
48
Clarence Ip13a8cf42016-09-29 17:27:47 -040049#define SDE_DEBUG_PLANE(pl, fmt, ...) SDE_DEBUG("plane%d " fmt,\
50 (pl) ? (pl)->base.base.id : -1, ##__VA_ARGS__)
51
52#define SDE_ERROR_PLANE(pl, fmt, ...) SDE_ERROR("plane%d " fmt,\
53 (pl) ? (pl)->base.base.id : -1, ##__VA_ARGS__)
54
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -040055#define DECIMATED_DIMENSION(dim, deci) (((dim) + ((1 << (deci)) - 1)) >> (deci))
56#define PHASE_STEP_SHIFT 21
57#define PHASE_STEP_UNIT_SCALE ((int) (1 << PHASE_STEP_SHIFT))
58#define PHASE_RESIDUAL 15
59
Clarence Ipe78efb72016-06-24 18:35:21 -040060#define SHARP_STRENGTH_DEFAULT 32
61#define SHARP_EDGE_THR_DEFAULT 112
62#define SHARP_SMOOTH_THR_DEFAULT 8
63#define SHARP_NOISE_THR_DEFAULT 2
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -040064
Clarence Ip5e2a9222016-06-26 22:38:24 -040065#define SDE_NAME_SIZE 12
Narendra Muppalla1b0b3352015-09-29 10:16:51 -070066
Clarence Ipcae1bb62016-07-07 12:07:13 -040067#define SDE_PLANE_COLOR_FILL_FLAG BIT(31)
68
Jeykumar Sankaran2e655032017-02-04 14:05:45 -080069/* multirect rect index */
70enum {
71 R0,
72 R1,
73 R_MAX
74};
75
76#define TX_MODE_BUFFER_LINE_THRES 2
77
Clarence Ip282dad62016-09-27 17:07:35 -040078/* dirty bits for update function */
79#define SDE_PLANE_DIRTY_RECTS 0x1
80#define SDE_PLANE_DIRTY_FORMAT 0x2
81#define SDE_PLANE_DIRTY_SHARPEN 0x4
82#define SDE_PLANE_DIRTY_ALL 0xFFFFFFFF
83
Gopikrishnaiah Anandanf4c34292016-10-20 15:42:04 -070084#define SDE_QSEED3_DEFAULT_PRELOAD_H 0x4
85#define SDE_QSEED3_DEFAULT_PRELOAD_V 0x3
86
Alan Kwong4dd64c82017-02-04 18:41:51 -080087#define DEFAULT_REFRESH_RATE 60
88
Alan Kwong1a00e4d2016-07-18 09:42:30 -040089/**
90 * enum sde_plane_qos - Different qos configurations for each pipe
91 *
92 * @SDE_PLANE_QOS_VBLANK_CTRL: Setup VBLANK qos for the pipe.
93 * @SDE_PLANE_QOS_VBLANK_AMORTIZE: Enables Amortization within pipe.
94 * this configuration is mutually exclusive from VBLANK_CTRL.
95 * @SDE_PLANE_QOS_PANIC_CTRL: Setup panic for the pipe.
96 */
97enum sde_plane_qos {
98 SDE_PLANE_QOS_VBLANK_CTRL = BIT(0),
99 SDE_PLANE_QOS_VBLANK_AMORTIZE = BIT(1),
100 SDE_PLANE_QOS_PANIC_CTRL = BIT(2),
101};
102
Clarence Ip5fc00c52016-09-23 15:03:34 -0400103/*
104 * struct sde_plane - local sde plane structure
105 * @csc_cfg: Decoded user configuration for csc
106 * @csc_usr_ptr: Points to csc_cfg if valid user config available
107 * @csc_ptr: Points to sde_csc_cfg structure to use for current
Alan Kwong4dd64c82017-02-04 18:41:51 -0800108 * @catalog: Points to sde catalog structure
109 * @sbuf_mode: force stream buffer mode if set
110 * @sbuf_writeback: fource stream buffer writeback if set
111 * @blob_rot_caps: Pointer to rotator capability blob
Clarence Ip5fc00c52016-09-23 15:03:34 -0400112 */
Narendra Muppalla1b0b3352015-09-29 10:16:51 -0700113struct sde_plane {
114 struct drm_plane base;
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -0400115
116 int mmu_id;
117
Clarence Ip730e7192016-06-26 22:45:09 -0400118 struct mutex lock;
119
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -0400120 enum sde_sspp pipe;
121 uint32_t features; /* capabilities from catalog */
Narendra Muppalla1b0b3352015-09-29 10:16:51 -0700122 uint32_t nformats;
Lloyd Atkinsonfa2489c2016-05-25 15:16:03 -0400123 uint32_t formats[64];
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -0400124
125 struct sde_hw_pipe *pipe_hw;
126 struct sde_hw_pipe_cfg pipe_cfg;
Clarence Ipe78efb72016-06-24 18:35:21 -0400127 struct sde_hw_sharp_cfg sharp_cfg;
abeykun48f407a2016-08-25 12:06:44 -0400128 struct sde_hw_scaler3_cfg *scaler3_cfg;
Alan Kwong1a00e4d2016-07-18 09:42:30 -0400129 struct sde_hw_pipe_qos_cfg pipe_qos_cfg;
Clarence Ipcae1bb62016-07-07 12:07:13 -0400130 uint32_t color_fill;
131 bool is_error;
Alan Kwong1a00e4d2016-07-18 09:42:30 -0400132 bool is_rt_pipe;
Jeykumar Sankaran2e655032017-02-04 14:05:45 -0800133 bool is_virtual;
Alan Kwong4dd64c82017-02-04 18:41:51 -0800134 struct sde_mdss_cfg *catalog;
135 u32 sbuf_mode;
136 u32 sbuf_writeback;
Clarence Ip4ce59322016-06-26 22:27:51 -0400137
Clarence Ipb43d4592016-09-08 14:21:35 -0400138 struct sde_hw_pixel_ext pixel_ext;
139 bool pixel_ext_usr;
140
Clarence Ip373f8592016-05-26 00:58:42 -0400141 struct sde_csc_cfg csc_cfg;
Clarence Ip5fc00c52016-09-23 15:03:34 -0400142 struct sde_csc_cfg *csc_usr_ptr;
Clarence Ip373f8592016-05-26 00:58:42 -0400143 struct sde_csc_cfg *csc_ptr;
144
Clarence Ip4c1d9772016-06-26 09:35:38 -0400145 const struct sde_sspp_sub_blks *pipe_sblk;
146
Clarence Ip5e2a9222016-06-26 22:38:24 -0400147 char pipe_name[SDE_NAME_SIZE];
Clarence Ip4ce59322016-06-26 22:27:51 -0400148
Clarence Ipaa0faf42016-05-30 12:07:48 -0400149 struct msm_property_info property_info;
150 struct msm_property_data property_data[PLANE_PROP_COUNT];
Dhaval Patel4e574842016-08-23 15:11:37 -0700151 struct drm_property_blob *blob_info;
Alan Kwong4dd64c82017-02-04 18:41:51 -0800152 struct drm_property_blob *blob_rot_caps;
Clarence Ip730e7192016-06-26 22:45:09 -0400153
Clarence Ip4ce59322016-06-26 22:27:51 -0400154 /* debugfs related stuff */
155 struct dentry *debugfs_root;
156 struct sde_debugfs_regset32 debugfs_src;
157 struct sde_debugfs_regset32 debugfs_scaler;
158 struct sde_debugfs_regset32 debugfs_csc;
Clarence Ip716ab662017-03-20 06:51:24 -0700159 bool debugfs_default_scale;
Narendra Muppalla1b0b3352015-09-29 10:16:51 -0700160};
Dhaval Patel47302cf2016-08-18 15:04:28 -0700161
Narendra Muppalla1b0b3352015-09-29 10:16:51 -0700162#define to_sde_plane(x) container_of(x, struct sde_plane, base)
163
Alan Kwong4dd64c82017-02-04 18:41:51 -0800164static struct sde_kms *_sde_plane_get_kms(struct drm_plane *plane)
165{
166 struct msm_drm_private *priv;
167
168 if (!plane || !plane->dev)
169 return NULL;
170 priv = plane->dev->dev_private;
171 if (!priv)
172 return NULL;
173 return to_sde_kms(priv->kms);
174}
175
Alan Kwong4aacd532017-02-04 18:51:33 -0800176/**
177 * _sde_plane_get_crtc_state - obtain crtc state attached to given plane state
178 * @pstate: Pointer to drm plane state
179 * return: Pointer to crtc state if success; pointer error, otherwise
180 */
181static struct drm_crtc_state *_sde_plane_get_crtc_state(
182 struct drm_plane_state *pstate)
183{
184 struct drm_crtc_state *cstate;
185
186 if (!pstate || !pstate->crtc)
187 return NULL;
188
189 if (pstate->state)
190 cstate = drm_atomic_get_crtc_state(pstate->state, pstate->crtc);
191 else
192 cstate = pstate->crtc->state;
193
194 return cstate;
195}
196
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -0400197static bool sde_plane_enabled(struct drm_plane_state *state)
198{
Clarence Ipdbde9832016-06-26 09:48:36 -0400199 return state && state->fb && state->crtc;
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -0400200}
201
Alan Kwong4dd64c82017-02-04 18:41:51 -0800202static bool sde_plane_sspp_enabled(struct drm_plane_state *state)
203{
204 return state && to_sde_plane_state(state)->rot.out_fb && state->crtc;
205}
206
207/**
208 * sde_plane_crtc_enabled - determine if crtc of given plane state is enabled
209 * @state: Pointer to drm plane state
210 * return: true if plane and the associated crtc are both enabled
211 */
212static bool sde_plane_crtc_enabled(struct drm_plane_state *state)
213{
214 return sde_plane_enabled(state) && state->crtc->state &&
215 state->crtc->state->active &&
216 state->crtc->state->enable;
217}
218
Alan Kwong1a00e4d2016-07-18 09:42:30 -0400219/**
220 * _sde_plane_calc_fill_level - calculate fill level of the given source format
221 * @plane: Pointer to drm plane
222 * @fmt: Pointer to source buffer format
223 * @src_wdith: width of source buffer
224 * Return: fill level corresponding to the source buffer/format or 0 if error
225 */
226static inline int _sde_plane_calc_fill_level(struct drm_plane *plane,
227 const struct sde_format *fmt, u32 src_width)
228{
229 struct sde_plane *psde;
230 u32 fixed_buff_size;
231 u32 total_fl;
232
233 if (!plane || !fmt) {
234 SDE_ERROR("invalid arguments\n");
235 return 0;
236 }
237
238 psde = to_sde_plane(plane);
239 fixed_buff_size = psde->pipe_sblk->pixel_ram_size;
240
241 if (fmt->fetch_planes == SDE_PLANE_PSEUDO_PLANAR) {
242 if (fmt->chroma_sample == SDE_CHROMA_420) {
243 /* NV12 */
244 total_fl = (fixed_buff_size / 2) /
245 ((src_width + 32) * fmt->bpp);
246 } else {
247 /* non NV12 */
248 total_fl = (fixed_buff_size) /
249 ((src_width + 32) * fmt->bpp);
250 }
251 } else {
252 total_fl = (fixed_buff_size * 2) /
253 ((src_width + 32) * fmt->bpp);
254 }
255
256 SDE_DEBUG("plane%u: pnum:%d fmt:%x w:%u fl:%u\n",
257 plane->base.id, psde->pipe - SSPP_VIG0,
258 fmt->base.pixel_format, src_width, total_fl);
259
260 return total_fl;
261}
262
263/**
264 * _sde_plane_get_qos_lut_linear - get linear LUT mapping
265 * @total_fl: fill level
266 * Return: LUT setting corresponding to the fill level
267 */
268static inline u32 _sde_plane_get_qos_lut_linear(u32 total_fl)
269{
270 u32 qos_lut;
271
272 if (total_fl <= 4)
273 qos_lut = 0x1B;
274 else if (total_fl <= 5)
275 qos_lut = 0x5B;
276 else if (total_fl <= 6)
277 qos_lut = 0x15B;
278 else if (total_fl <= 7)
279 qos_lut = 0x55B;
280 else if (total_fl <= 8)
281 qos_lut = 0x155B;
282 else if (total_fl <= 9)
283 qos_lut = 0x555B;
284 else if (total_fl <= 10)
285 qos_lut = 0x1555B;
286 else if (total_fl <= 11)
287 qos_lut = 0x5555B;
288 else if (total_fl <= 12)
289 qos_lut = 0x15555B;
290 else
291 qos_lut = 0x55555B;
292
293 return qos_lut;
294}
295
296/**
297 * _sde_plane_get_qos_lut_macrotile - get macrotile LUT mapping
298 * @total_fl: fill level
299 * Return: LUT setting corresponding to the fill level
300 */
301static inline u32 _sde_plane_get_qos_lut_macrotile(u32 total_fl)
302{
303 u32 qos_lut;
304
305 if (total_fl <= 10)
306 qos_lut = 0x1AAff;
307 else if (total_fl <= 11)
308 qos_lut = 0x5AAFF;
309 else if (total_fl <= 12)
310 qos_lut = 0x15AAFF;
311 else
312 qos_lut = 0x55AAFF;
313
314 return qos_lut;
315}
316
317/**
Alan Kwong1a00e4d2016-07-18 09:42:30 -0400318 * _sde_plane_set_qos_lut - set QoS LUT of the given plane
319 * @plane: Pointer to drm plane
320 * @fb: Pointer to framebuffer associated with the given plane
321 */
322static void _sde_plane_set_qos_lut(struct drm_plane *plane,
323 struct drm_framebuffer *fb)
324{
325 struct sde_plane *psde;
326 const struct sde_format *fmt = NULL;
327 u32 qos_lut;
328 u32 total_fl = 0;
329
330 if (!plane || !fb) {
331 SDE_ERROR("invalid arguments plane %d fb %d\n",
332 plane != 0, fb != 0);
333 return;
334 }
335
336 psde = to_sde_plane(plane);
337
338 if (!psde->pipe_hw || !psde->pipe_sblk) {
339 SDE_ERROR("invalid arguments\n");
340 return;
341 } else if (!psde->pipe_hw->ops.setup_creq_lut) {
342 return;
343 }
344
345 if (!psde->is_rt_pipe) {
346 qos_lut = psde->pipe_sblk->creq_lut_nrt;
347 } else {
348 fmt = sde_get_sde_format_ext(
349 fb->pixel_format,
350 fb->modifier,
351 drm_format_num_planes(fb->pixel_format));
352 total_fl = _sde_plane_calc_fill_level(plane, fmt,
353 psde->pipe_cfg.src_rect.w);
354
355 if (SDE_FORMAT_IS_LINEAR(fmt))
356 qos_lut = _sde_plane_get_qos_lut_linear(total_fl);
357 else
358 qos_lut = _sde_plane_get_qos_lut_macrotile(total_fl);
359 }
360
361 psde->pipe_qos_cfg.creq_lut = qos_lut;
362
363 trace_sde_perf_set_qos_luts(psde->pipe - SSPP_VIG0,
364 (fmt) ? fmt->base.pixel_format : 0,
365 psde->is_rt_pipe, total_fl, qos_lut,
366 (fmt) ? SDE_FORMAT_IS_LINEAR(fmt) : 0);
367
368 SDE_DEBUG("plane%u: pnum:%d fmt:%x rt:%d fl:%u lut:0x%x\n",
369 plane->base.id,
370 psde->pipe - SSPP_VIG0,
371 (fmt) ? fmt->base.pixel_format : 0,
372 psde->is_rt_pipe, total_fl, qos_lut);
373
374 psde->pipe_hw->ops.setup_creq_lut(psde->pipe_hw, &psde->pipe_qos_cfg);
375}
376
377/**
378 * _sde_plane_set_panic_lut - set danger/safe LUT of the given plane
379 * @plane: Pointer to drm plane
380 * @fb: Pointer to framebuffer associated with the given plane
381 */
382static void _sde_plane_set_danger_lut(struct drm_plane *plane,
383 struct drm_framebuffer *fb)
384{
385 struct sde_plane *psde;
386 const struct sde_format *fmt = NULL;
387 u32 danger_lut, safe_lut;
388
389 if (!plane || !fb) {
390 SDE_ERROR("invalid arguments\n");
391 return;
392 }
393
394 psde = to_sde_plane(plane);
395
396 if (!psde->pipe_hw || !psde->pipe_sblk) {
397 SDE_ERROR("invalid arguments\n");
398 return;
399 } else if (!psde->pipe_hw->ops.setup_danger_safe_lut) {
400 return;
401 }
402
403 if (!psde->is_rt_pipe) {
404 danger_lut = psde->pipe_sblk->danger_lut_nrt;
405 safe_lut = psde->pipe_sblk->safe_lut_nrt;
406 } else {
407 fmt = sde_get_sde_format_ext(
408 fb->pixel_format,
409 fb->modifier,
410 drm_format_num_planes(fb->pixel_format));
411
412 if (SDE_FORMAT_IS_LINEAR(fmt)) {
413 danger_lut = psde->pipe_sblk->danger_lut_linear;
414 safe_lut = psde->pipe_sblk->safe_lut_linear;
415 } else {
416 danger_lut = psde->pipe_sblk->danger_lut_tile;
417 safe_lut = psde->pipe_sblk->safe_lut_tile;
418 }
419 }
420
421 psde->pipe_qos_cfg.danger_lut = danger_lut;
422 psde->pipe_qos_cfg.safe_lut = safe_lut;
423
424 trace_sde_perf_set_danger_luts(psde->pipe - SSPP_VIG0,
425 (fmt) ? fmt->base.pixel_format : 0,
426 (fmt) ? fmt->fetch_mode : 0,
427 psde->pipe_qos_cfg.danger_lut,
428 psde->pipe_qos_cfg.safe_lut);
429
430 SDE_DEBUG("plane%u: pnum:%d fmt:%x mode:%d luts[0x%x, 0x%x]\n",
431 plane->base.id,
432 psde->pipe - SSPP_VIG0,
433 fmt ? fmt->base.pixel_format : 0,
434 fmt ? fmt->fetch_mode : -1,
435 psde->pipe_qos_cfg.danger_lut,
436 psde->pipe_qos_cfg.safe_lut);
437
438 psde->pipe_hw->ops.setup_danger_safe_lut(psde->pipe_hw,
439 &psde->pipe_qos_cfg);
440}
441
442/**
443 * _sde_plane_set_qos_ctrl - set QoS control of the given plane
444 * @plane: Pointer to drm plane
445 * @enable: true to enable QoS control
446 * @flags: QoS control mode (enum sde_plane_qos)
447 */
448static void _sde_plane_set_qos_ctrl(struct drm_plane *plane,
449 bool enable, u32 flags)
450{
451 struct sde_plane *psde;
452
453 if (!plane) {
454 SDE_ERROR("invalid arguments\n");
455 return;
456 }
457
458 psde = to_sde_plane(plane);
459
460 if (!psde->pipe_hw || !psde->pipe_sblk) {
461 SDE_ERROR("invalid arguments\n");
462 return;
463 } else if (!psde->pipe_hw->ops.setup_qos_ctrl) {
464 return;
465 }
466
467 if (flags & SDE_PLANE_QOS_VBLANK_CTRL) {
468 psde->pipe_qos_cfg.creq_vblank = psde->pipe_sblk->creq_vblank;
469 psde->pipe_qos_cfg.danger_vblank =
470 psde->pipe_sblk->danger_vblank;
471 psde->pipe_qos_cfg.vblank_en = enable;
472 }
473
474 if (flags & SDE_PLANE_QOS_VBLANK_AMORTIZE) {
475 /* this feature overrules previous VBLANK_CTRL */
476 psde->pipe_qos_cfg.vblank_en = false;
477 psde->pipe_qos_cfg.creq_vblank = 0; /* clear vblank bits */
478 }
479
480 if (flags & SDE_PLANE_QOS_PANIC_CTRL)
481 psde->pipe_qos_cfg.danger_safe_en = enable;
482
483 if (!psde->is_rt_pipe) {
484 psde->pipe_qos_cfg.vblank_en = false;
485 psde->pipe_qos_cfg.danger_safe_en = false;
486 }
487
Clarence Ip0d0e96d2016-10-24 18:13:13 -0400488 SDE_DEBUG("plane%u: pnum:%d ds:%d vb:%d pri[0x%x, 0x%x] is_rt:%d\n",
Alan Kwong1a00e4d2016-07-18 09:42:30 -0400489 plane->base.id,
490 psde->pipe - SSPP_VIG0,
491 psde->pipe_qos_cfg.danger_safe_en,
492 psde->pipe_qos_cfg.vblank_en,
493 psde->pipe_qos_cfg.creq_vblank,
Clarence Ip0d0e96d2016-10-24 18:13:13 -0400494 psde->pipe_qos_cfg.danger_vblank,
495 psde->is_rt_pipe);
Alan Kwong1a00e4d2016-07-18 09:42:30 -0400496
497 psde->pipe_hw->ops.setup_qos_ctrl(psde->pipe_hw,
498 &psde->pipe_qos_cfg);
499}
500
Alan Kwongf0fd8512016-10-24 21:39:26 -0400501int sde_plane_danger_signal_ctrl(struct drm_plane *plane, bool enable)
502{
503 struct sde_plane *psde;
504 struct msm_drm_private *priv;
505 struct sde_kms *sde_kms;
506
507 if (!plane || !plane->dev) {
508 SDE_ERROR("invalid arguments\n");
509 return -EINVAL;
510 }
511
512 priv = plane->dev->dev_private;
513 if (!priv || !priv->kms) {
514 SDE_ERROR("invalid KMS reference\n");
515 return -EINVAL;
516 }
517
518 sde_kms = to_sde_kms(priv->kms);
519 psde = to_sde_plane(plane);
520
521 if (!psde->is_rt_pipe)
522 goto end;
523
524 sde_power_resource_enable(&priv->phandle, sde_kms->core_client, true);
525
526 _sde_plane_set_qos_ctrl(plane, enable, SDE_PLANE_QOS_PANIC_CTRL);
527
528 sde_power_resource_enable(&priv->phandle, sde_kms->core_client, false);
529
530end:
531 return 0;
532}
533
Alan Kwong5d324e42016-07-28 22:56:18 -0400534/**
535 * _sde_plane_set_ot_limit - set OT limit for the given plane
536 * @plane: Pointer to drm plane
537 * @crtc: Pointer to drm crtc
538 */
539static void _sde_plane_set_ot_limit(struct drm_plane *plane,
540 struct drm_crtc *crtc)
541{
542 struct sde_plane *psde;
543 struct sde_vbif_set_ot_params ot_params;
544 struct msm_drm_private *priv;
545 struct sde_kms *sde_kms;
546
547 if (!plane || !plane->dev || !crtc) {
548 SDE_ERROR("invalid arguments plane %d crtc %d\n",
549 plane != 0, crtc != 0);
550 return;
551 }
552
553 priv = plane->dev->dev_private;
554 if (!priv || !priv->kms) {
555 SDE_ERROR("invalid KMS reference\n");
556 return;
557 }
558
559 sde_kms = to_sde_kms(priv->kms);
560 psde = to_sde_plane(plane);
561 if (!psde->pipe_hw) {
562 SDE_ERROR("invalid pipe reference\n");
563 return;
564 }
565
566 memset(&ot_params, 0, sizeof(ot_params));
567 ot_params.xin_id = psde->pipe_hw->cap->xin_id;
568 ot_params.num = psde->pipe_hw->idx - SSPP_NONE;
569 ot_params.width = psde->pipe_cfg.src_rect.w;
570 ot_params.height = psde->pipe_cfg.src_rect.h;
571 ot_params.is_wfd = !psde->is_rt_pipe;
572 ot_params.frame_rate = crtc->mode.vrefresh;
573 ot_params.vbif_idx = VBIF_RT;
574 ot_params.clk_ctrl = psde->pipe_hw->cap->clk_ctrl;
575 ot_params.rd = true;
576
577 sde_vbif_set_ot_limit(sde_kms, &ot_params);
578}
579
Clarence Ipcae1bb62016-07-07 12:07:13 -0400580/* helper to update a state's input fence pointer from the property */
Clarence Ip13a8cf42016-09-29 17:27:47 -0400581static void _sde_plane_set_input_fence(struct sde_plane *psde,
Clarence Ipae4e60c2016-06-26 22:44:04 -0400582 struct sde_plane_state *pstate, uint64_t fd)
583{
Clarence Ip13a8cf42016-09-29 17:27:47 -0400584 if (!psde || !pstate) {
585 SDE_ERROR("invalid arg(s), plane %d state %d\n",
586 psde != 0, pstate != 0);
Clarence Ipae4e60c2016-06-26 22:44:04 -0400587 return;
Clarence Ip13a8cf42016-09-29 17:27:47 -0400588 }
Clarence Ipae4e60c2016-06-26 22:44:04 -0400589
590 /* clear previous reference */
Clarence Ipcae1bb62016-07-07 12:07:13 -0400591 if (pstate->input_fence)
592 sde_sync_put(pstate->input_fence);
Clarence Ipae4e60c2016-06-26 22:44:04 -0400593
594 /* get fence pointer for later */
Clarence Ipcae1bb62016-07-07 12:07:13 -0400595 pstate->input_fence = sde_sync_get(fd);
Clarence Ipae4e60c2016-06-26 22:44:04 -0400596
Clarence Ip13a8cf42016-09-29 17:27:47 -0400597 SDE_DEBUG_PLANE(psde, "0x%llX\n", fd);
Clarence Ipae4e60c2016-06-26 22:44:04 -0400598}
599
Clarence Ipcae1bb62016-07-07 12:07:13 -0400600int sde_plane_wait_input_fence(struct drm_plane *plane, uint32_t wait_ms)
Clarence Ipae4e60c2016-06-26 22:44:04 -0400601{
Clarence Ipcae1bb62016-07-07 12:07:13 -0400602 struct sde_plane *psde;
Clarence Ipae4e60c2016-06-26 22:44:04 -0400603 struct sde_plane_state *pstate;
Clarence Ip78a04ed2016-10-04 15:57:45 -0400604 uint32_t prefix;
Clarence Ipcae1bb62016-07-07 12:07:13 -0400605 void *input_fence;
Clarence Ipcb410d42016-06-26 22:52:33 -0400606 int ret = -EINVAL;
Dhaval Patel39323d42017-03-01 23:48:24 -0800607 signed long rc;
Clarence Ipae4e60c2016-06-26 22:44:04 -0400608
609 if (!plane) {
Dhaval Patel47302cf2016-08-18 15:04:28 -0700610 SDE_ERROR("invalid plane\n");
Clarence Ipae4e60c2016-06-26 22:44:04 -0400611 } else if (!plane->state) {
Clarence Ip13a8cf42016-09-29 17:27:47 -0400612 SDE_ERROR_PLANE(to_sde_plane(plane), "invalid state\n");
Clarence Ipae4e60c2016-06-26 22:44:04 -0400613 } else {
Clarence Ipcae1bb62016-07-07 12:07:13 -0400614 psde = to_sde_plane(plane);
Clarence Ipae4e60c2016-06-26 22:44:04 -0400615 pstate = to_sde_plane_state(plane->state);
Clarence Ipcae1bb62016-07-07 12:07:13 -0400616 input_fence = pstate->input_fence;
Clarence Ipae4e60c2016-06-26 22:44:04 -0400617
Clarence Ipcae1bb62016-07-07 12:07:13 -0400618 if (input_fence) {
Dhaval Patel39323d42017-03-01 23:48:24 -0800619 psde->is_error = false;
Clarence Ip78a04ed2016-10-04 15:57:45 -0400620 prefix = sde_sync_get_name_prefix(input_fence);
Dhaval Patel39323d42017-03-01 23:48:24 -0800621 rc = sde_sync_wait(input_fence, wait_ms);
Clarence Ip78a04ed2016-10-04 15:57:45 -0400622
Lloyd Atkinson5d40d312016-09-06 08:34:13 -0400623 SDE_EVT32(DRMID(plane), -ret, prefix);
Clarence Ip78a04ed2016-10-04 15:57:45 -0400624
Dhaval Patel39323d42017-03-01 23:48:24 -0800625 switch (rc) {
Clarence Ipcae1bb62016-07-07 12:07:13 -0400626 case 0:
Clarence Ip78a04ed2016-10-04 15:57:45 -0400627 SDE_ERROR_PLANE(psde, "%ums timeout on %08X\n",
628 wait_ms, prefix);
Clarence Ipcae1bb62016-07-07 12:07:13 -0400629 psde->is_error = true;
Dhaval Patel39323d42017-03-01 23:48:24 -0800630 ret = -ETIMEDOUT;
631 break;
632 case -ERESTARTSYS:
633 SDE_ERROR_PLANE(psde,
634 "%ums wait interrupted on %08X\n",
635 wait_ms, prefix);
636 psde->is_error = true;
637 ret = -ERESTARTSYS;
638 break;
639 case -EINVAL:
640 SDE_ERROR_PLANE(psde,
641 "invalid fence param for %08X\n",
642 prefix);
643 psde->is_error = true;
644 ret = -EINVAL;
Clarence Ipcae1bb62016-07-07 12:07:13 -0400645 break;
646 default:
Dhaval Patel39323d42017-03-01 23:48:24 -0800647 SDE_DEBUG_PLANE(psde, "signaled\n");
648 ret = 0;
Clarence Ipcae1bb62016-07-07 12:07:13 -0400649 break;
650 }
Clarence Ipcb410d42016-06-26 22:52:33 -0400651 } else {
652 ret = 0;
653 }
Clarence Ipae4e60c2016-06-26 22:44:04 -0400654 }
Clarence Ipae4e60c2016-06-26 22:44:04 -0400655 return ret;
656}
657
Clarence Ip282dad62016-09-27 17:07:35 -0400658static inline void _sde_plane_set_scanout(struct drm_plane *plane,
Clarence Ip5e2a9222016-06-26 22:38:24 -0400659 struct sde_plane_state *pstate,
Lloyd Atkinsonfa2489c2016-05-25 15:16:03 -0400660 struct sde_hw_pipe_cfg *pipe_cfg,
661 struct drm_framebuffer *fb)
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -0400662{
Clarence Ipae4e60c2016-06-26 22:44:04 -0400663 struct sde_plane *psde;
Clarence Ip282dad62016-09-27 17:07:35 -0400664 int ret;
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -0400665
Clarence Ip13a8cf42016-09-29 17:27:47 -0400666 if (!plane || !pstate || !pipe_cfg || !fb) {
667 SDE_ERROR(
668 "invalid arg(s), plane %d state %d cfg %d fb %d\n",
669 plane != 0, pstate != 0, pipe_cfg != 0, fb != 0);
Clarence Ipae4e60c2016-06-26 22:44:04 -0400670 return;
Clarence Ip13a8cf42016-09-29 17:27:47 -0400671 }
Clarence Ipae4e60c2016-06-26 22:44:04 -0400672
673 psde = to_sde_plane(plane);
Clarence Ipb6eb2362016-09-08 16:18:13 -0400674 if (!psde->pipe_hw) {
675 SDE_ERROR_PLANE(psde, "invalid pipe_hw\n");
Lloyd Atkinsonfa2489c2016-05-25 15:16:03 -0400676 return;
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -0400677 }
Lloyd Atkinsonfa2489c2016-05-25 15:16:03 -0400678
Clarence Ipb6eb2362016-09-08 16:18:13 -0400679 ret = sde_format_populate_layout(psde->mmu_id, fb, &pipe_cfg->layout);
680 if (ret == -EAGAIN)
681 SDE_DEBUG_PLANE(psde, "not updating same src addrs\n");
682 else if (ret)
683 SDE_ERROR_PLANE(psde, "failed to get format layout, %d\n", ret);
684 else if (psde->pipe_hw->ops.setup_sourceaddress)
Jeykumar Sankaran2e655032017-02-04 14:05:45 -0800685 psde->pipe_hw->ops.setup_sourceaddress(psde->pipe_hw, pipe_cfg,
686 pstate->multirect_index);
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -0400687}
688
abeykun48f407a2016-08-25 12:06:44 -0400689static int _sde_plane_setup_scaler3_lut(struct sde_plane *psde,
690 struct sde_plane_state *pstate)
691{
Clarence Ip3bf8d872017-02-16 15:25:38 -0500692 struct sde_hw_scaler3_cfg *cfg;
abeykun48f407a2016-08-25 12:06:44 -0400693 int ret = 0;
694
Clarence Ip3bf8d872017-02-16 15:25:38 -0500695 if (!psde || !psde->scaler3_cfg) {
696 SDE_ERROR("invalid args\n");
697 return -EINVAL;
698 } else if (!pstate) {
699 /* pstate is expected to be null on forced color fill */
700 SDE_DEBUG("null pstate\n");
701 return -EINVAL;
702 }
703
704 cfg = psde->scaler3_cfg;
705
abeykun48f407a2016-08-25 12:06:44 -0400706 cfg->dir_lut = msm_property_get_blob(
707 &psde->property_info,
708 pstate->property_blobs, &cfg->dir_len,
709 PLANE_PROP_SCALER_LUT_ED);
710 cfg->cir_lut = msm_property_get_blob(
711 &psde->property_info,
712 pstate->property_blobs, &cfg->cir_len,
713 PLANE_PROP_SCALER_LUT_CIR);
714 cfg->sep_lut = msm_property_get_blob(
715 &psde->property_info,
716 pstate->property_blobs, &cfg->sep_len,
717 PLANE_PROP_SCALER_LUT_SEP);
718 if (!cfg->dir_lut || !cfg->cir_lut || !cfg->sep_lut)
719 ret = -ENODATA;
720 return ret;
721}
722
Clarence Ipcb410d42016-06-26 22:52:33 -0400723static void _sde_plane_setup_scaler3(struct sde_plane *psde,
Clarence Ip5e2a9222016-06-26 22:38:24 -0400724 uint32_t src_w, uint32_t src_h, uint32_t dst_w, uint32_t dst_h,
725 struct sde_hw_scaler3_cfg *scale_cfg,
Lloyd Atkinson9a673492016-07-05 11:41:57 -0400726 const struct sde_format *fmt,
Clarence Ip5e2a9222016-06-26 22:38:24 -0400727 uint32_t chroma_subsmpl_h, uint32_t chroma_subsmpl_v)
728{
Gopikrishnaiah Anandanf4c34292016-10-20 15:42:04 -0700729 uint32_t decimated, i;
730
731 if (!psde || !scale_cfg || !fmt || !chroma_subsmpl_h ||
732 !chroma_subsmpl_v) {
733 SDE_ERROR("psde %pK scale_cfg %pK fmt %pK smp_h %d smp_v %d\n"
734 , psde, scale_cfg, fmt, chroma_subsmpl_h,
735 chroma_subsmpl_v);
736 return;
737 }
738
739 memset(scale_cfg, 0, sizeof(*scale_cfg));
Clarence Ip716ab662017-03-20 06:51:24 -0700740 memset(&psde->pixel_ext, 0, sizeof(struct sde_hw_pixel_ext));
Gopikrishnaiah Anandanf4c34292016-10-20 15:42:04 -0700741
742 decimated = DECIMATED_DIMENSION(src_w,
743 psde->pipe_cfg.horz_decimation);
744 scale_cfg->phase_step_x[SDE_SSPP_COMP_0] =
745 mult_frac((1 << PHASE_STEP_SHIFT), decimated, dst_w);
746 decimated = DECIMATED_DIMENSION(src_h,
747 psde->pipe_cfg.vert_decimation);
748 scale_cfg->phase_step_y[SDE_SSPP_COMP_0] =
749 mult_frac((1 << PHASE_STEP_SHIFT), decimated, dst_h);
750
751
752 scale_cfg->phase_step_y[SDE_SSPP_COMP_1_2] =
753 scale_cfg->phase_step_y[SDE_SSPP_COMP_0] / chroma_subsmpl_v;
754 scale_cfg->phase_step_x[SDE_SSPP_COMP_1_2] =
755 scale_cfg->phase_step_x[SDE_SSPP_COMP_0] / chroma_subsmpl_h;
756
757 scale_cfg->phase_step_x[SDE_SSPP_COMP_2] =
758 scale_cfg->phase_step_x[SDE_SSPP_COMP_1_2];
759 scale_cfg->phase_step_y[SDE_SSPP_COMP_2] =
760 scale_cfg->phase_step_y[SDE_SSPP_COMP_1_2];
761
762 scale_cfg->phase_step_x[SDE_SSPP_COMP_3] =
763 scale_cfg->phase_step_x[SDE_SSPP_COMP_0];
764 scale_cfg->phase_step_y[SDE_SSPP_COMP_3] =
765 scale_cfg->phase_step_y[SDE_SSPP_COMP_0];
766
767 for (i = 0; i < SDE_MAX_PLANES; i++) {
768 scale_cfg->src_width[i] = DECIMATED_DIMENSION(src_w,
769 psde->pipe_cfg.horz_decimation);
770 scale_cfg->src_height[i] = DECIMATED_DIMENSION(src_h,
771 psde->pipe_cfg.vert_decimation);
772 if (SDE_FORMAT_IS_YUV(fmt))
773 scale_cfg->src_width[i] &= ~0x1;
774 if (i == SDE_SSPP_COMP_1_2 || i == SDE_SSPP_COMP_2) {
775 scale_cfg->src_width[i] /= chroma_subsmpl_h;
776 scale_cfg->src_height[i] /= chroma_subsmpl_v;
777 }
778 scale_cfg->preload_x[i] = SDE_QSEED3_DEFAULT_PRELOAD_H;
779 scale_cfg->preload_y[i] = SDE_QSEED3_DEFAULT_PRELOAD_V;
780 psde->pixel_ext.num_ext_pxls_top[i] =
781 scale_cfg->src_height[i];
782 psde->pixel_ext.num_ext_pxls_left[i] =
783 scale_cfg->src_width[i];
784 }
785 if (!(SDE_FORMAT_IS_YUV(fmt)) && (src_h == dst_h)
786 && (src_w == dst_w))
787 return;
788
789 scale_cfg->dst_width = dst_w;
790 scale_cfg->dst_height = dst_h;
791 scale_cfg->y_rgb_filter_cfg = SDE_SCALE_BIL;
792 scale_cfg->uv_filter_cfg = SDE_SCALE_BIL;
793 scale_cfg->alpha_filter_cfg = SDE_SCALE_ALPHA_BIL;
794 scale_cfg->lut_flag = 0;
795 scale_cfg->blend_cfg = 1;
796 scale_cfg->enable = 1;
Clarence Ip5e2a9222016-06-26 22:38:24 -0400797}
798
Clarence Ipcb410d42016-06-26 22:52:33 -0400799/**
Clarence Ip13a8cf42016-09-29 17:27:47 -0400800 * _sde_plane_setup_scaler2 - determine default scaler phase steps/filter type
Clarence Ipcb410d42016-06-26 22:52:33 -0400801 * @psde: Pointer to SDE plane object
802 * @src: Source size
803 * @dst: Destination size
804 * @phase_steps: Pointer to output array for phase steps
805 * @filter: Pointer to output array for filter type
806 * @fmt: Pointer to format definition
807 * @chroma_subsampling: Subsampling amount for chroma channel
808 *
809 * Returns: 0 on success
810 */
811static int _sde_plane_setup_scaler2(struct sde_plane *psde,
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -0400812 uint32_t src, uint32_t dst, uint32_t *phase_steps,
Lloyd Atkinson9a673492016-07-05 11:41:57 -0400813 enum sde_hw_filter *filter, const struct sde_format *fmt,
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -0400814 uint32_t chroma_subsampling)
815{
Clarence Ipcb410d42016-06-26 22:52:33 -0400816 if (!psde || !phase_steps || !filter || !fmt) {
Clarence Ip13a8cf42016-09-29 17:27:47 -0400817 SDE_ERROR(
818 "invalid arg(s), plane %d phase %d filter %d fmt %d\n",
819 psde != 0, phase_steps != 0, filter != 0, fmt != 0);
Clarence Ipcb410d42016-06-26 22:52:33 -0400820 return -EINVAL;
821 }
822
Clarence Ip4c1d9772016-06-26 09:35:38 -0400823 /* calculate phase steps, leave init phase as zero */
Clarence Ipe78efb72016-06-24 18:35:21 -0400824 phase_steps[SDE_SSPP_COMP_0] =
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -0400825 mult_frac(1 << PHASE_STEP_SHIFT, src, dst);
Clarence Ipe78efb72016-06-24 18:35:21 -0400826 phase_steps[SDE_SSPP_COMP_1_2] =
827 phase_steps[SDE_SSPP_COMP_0] / chroma_subsampling;
828 phase_steps[SDE_SSPP_COMP_2] = phase_steps[SDE_SSPP_COMP_1_2];
829 phase_steps[SDE_SSPP_COMP_3] = phase_steps[SDE_SSPP_COMP_0];
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -0400830
831 /* calculate scaler config, if necessary */
Clarence Ipdbde9832016-06-26 09:48:36 -0400832 if (SDE_FORMAT_IS_YUV(fmt) || src != dst) {
Clarence Ipe78efb72016-06-24 18:35:21 -0400833 filter[SDE_SSPP_COMP_3] =
Lloyd Atkinson9a673492016-07-05 11:41:57 -0400834 (src <= dst) ? SDE_SCALE_FILTER_BIL :
835 SDE_SCALE_FILTER_PCMN;
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -0400836
Clarence Ipdbde9832016-06-26 09:48:36 -0400837 if (SDE_FORMAT_IS_YUV(fmt)) {
Lloyd Atkinson9a673492016-07-05 11:41:57 -0400838 filter[SDE_SSPP_COMP_0] = SDE_SCALE_FILTER_CA;
Clarence Ipe78efb72016-06-24 18:35:21 -0400839 filter[SDE_SSPP_COMP_1_2] = filter[SDE_SSPP_COMP_3];
840 } else {
841 filter[SDE_SSPP_COMP_0] = filter[SDE_SSPP_COMP_3];
842 filter[SDE_SSPP_COMP_1_2] =
Lloyd Atkinson9a673492016-07-05 11:41:57 -0400843 SDE_SCALE_FILTER_NEAREST;
Clarence Ipe78efb72016-06-24 18:35:21 -0400844 }
845 } else {
846 /* disable scaler */
Lloyd Atkinson9a673492016-07-05 11:41:57 -0400847 filter[SDE_SSPP_COMP_0] = SDE_SCALE_FILTER_MAX;
848 filter[SDE_SSPP_COMP_1_2] = SDE_SCALE_FILTER_MAX;
849 filter[SDE_SSPP_COMP_3] = SDE_SCALE_FILTER_MAX;
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -0400850 }
Clarence Ipcb410d42016-06-26 22:52:33 -0400851 return 0;
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -0400852}
853
Clarence Ipcb410d42016-06-26 22:52:33 -0400854/**
855 * _sde_plane_setup_pixel_ext - determine default pixel extension values
856 * @psde: Pointer to SDE plane object
857 * @src: Source size
858 * @dst: Destination size
859 * @decimated_src: Source size after decimation, if any
860 * @phase_steps: Pointer to output array for phase steps
861 * @out_src: Output array for pixel extension values
862 * @out_edge1: Output array for pixel extension first edge
863 * @out_edge2: Output array for pixel extension second edge
864 * @filter: Pointer to array for filter type
865 * @fmt: Pointer to format definition
866 * @chroma_subsampling: Subsampling amount for chroma channel
867 * @post_compare: Whether to chroma subsampled source size for comparisions
868 */
869static void _sde_plane_setup_pixel_ext(struct sde_plane *psde,
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -0400870 uint32_t src, uint32_t dst, uint32_t decimated_src,
871 uint32_t *phase_steps, uint32_t *out_src, int *out_edge1,
Clarence Ipe78efb72016-06-24 18:35:21 -0400872 int *out_edge2, enum sde_hw_filter *filter,
Lloyd Atkinson9a673492016-07-05 11:41:57 -0400873 const struct sde_format *fmt, uint32_t chroma_subsampling,
Clarence Ipe78efb72016-06-24 18:35:21 -0400874 bool post_compare)
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -0400875{
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -0400876 int64_t edge1, edge2, caf;
877 uint32_t src_work;
878 int i, tmp;
879
Clarence Ipcb410d42016-06-26 22:52:33 -0400880 if (psde && phase_steps && out_src && out_edge1 &&
Clarence Ipe78efb72016-06-24 18:35:21 -0400881 out_edge2 && filter && fmt) {
882 /* handle CAF for YUV formats */
Lloyd Atkinson9a673492016-07-05 11:41:57 -0400883 if (SDE_FORMAT_IS_YUV(fmt) && *filter == SDE_SCALE_FILTER_CA)
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -0400884 caf = PHASE_STEP_UNIT_SCALE;
885 else
886 caf = 0;
887
888 for (i = 0; i < SDE_MAX_PLANES; i++) {
889 src_work = decimated_src;
Clarence Ipe78efb72016-06-24 18:35:21 -0400890 if (i == SDE_SSPP_COMP_1_2 || i == SDE_SSPP_COMP_2)
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -0400891 src_work /= chroma_subsampling;
892 if (post_compare)
893 src = src_work;
Clarence Ipdbde9832016-06-26 09:48:36 -0400894 if (!SDE_FORMAT_IS_YUV(fmt) && (src == dst)) {
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -0400895 /* unity */
896 edge1 = 0;
897 edge2 = 0;
898 } else if (dst >= src) {
899 /* upscale */
900 edge1 = (1 << PHASE_RESIDUAL);
901 edge1 -= caf;
902 edge2 = (1 << PHASE_RESIDUAL);
903 edge2 += (dst - 1) * *(phase_steps + i);
904 edge2 -= (src_work - 1) * PHASE_STEP_UNIT_SCALE;
905 edge2 += caf;
906 edge2 = -(edge2);
907 } else {
908 /* downscale */
909 edge1 = 0;
910 edge2 = (dst - 1) * *(phase_steps + i);
911 edge2 -= (src_work - 1) * PHASE_STEP_UNIT_SCALE;
912 edge2 += *(phase_steps + i);
913 edge2 = -(edge2);
914 }
915
916 /* only enable CAF for luma plane */
917 caf = 0;
918
919 /* populate output arrays */
920 *(out_src + i) = src_work;
921
922 /* edge updates taken from __pxl_extn_helper */
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -0400923 if (edge1 >= 0) {
924 tmp = (uint32_t)edge1;
925 tmp >>= PHASE_STEP_SHIFT;
926 *(out_edge1 + i) = -tmp;
927 } else {
928 tmp = (uint32_t)(-edge1);
Clarence Ipe78efb72016-06-24 18:35:21 -0400929 *(out_edge1 + i) =
930 (tmp + PHASE_STEP_UNIT_SCALE - 1) >>
931 PHASE_STEP_SHIFT;
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -0400932 }
933 if (edge2 >= 0) {
934 tmp = (uint32_t)edge2;
935 tmp >>= PHASE_STEP_SHIFT;
936 *(out_edge2 + i) = -tmp;
937 } else {
938 tmp = (uint32_t)(-edge2);
Clarence Ipe78efb72016-06-24 18:35:21 -0400939 *(out_edge2 + i) =
940 (tmp + PHASE_STEP_UNIT_SCALE - 1) >>
941 PHASE_STEP_SHIFT;
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -0400942 }
943 }
944 }
945}
946
Clarence Ip5fc00c52016-09-23 15:03:34 -0400947static inline void _sde_plane_setup_csc(struct sde_plane *psde)
Clarence Ipe78efb72016-06-24 18:35:21 -0400948{
949 static const struct sde_csc_cfg sde_csc_YUV2RGB_601L = {
950 {
Clarence Ip373f8592016-05-26 00:58:42 -0400951 /* S15.16 format */
952 0x00012A00, 0x00000000, 0x00019880,
953 0x00012A00, 0xFFFF9B80, 0xFFFF3000,
954 0x00012A00, 0x00020480, 0x00000000,
Clarence Ipe78efb72016-06-24 18:35:21 -0400955 },
Clarence Ip373f8592016-05-26 00:58:42 -0400956 /* signed bias */
Clarence Ipe78efb72016-06-24 18:35:21 -0400957 { 0xfff0, 0xff80, 0xff80,},
958 { 0x0, 0x0, 0x0,},
Clarence Ip373f8592016-05-26 00:58:42 -0400959 /* unsigned clamp */
Clarence Ipe78efb72016-06-24 18:35:21 -0400960 { 0x10, 0xeb, 0x10, 0xf0, 0x10, 0xf0,},
Clarence Ip373f8592016-05-26 00:58:42 -0400961 { 0x00, 0xff, 0x00, 0xff, 0x00, 0xff,},
Clarence Ipe78efb72016-06-24 18:35:21 -0400962 };
abeykun1c312f62016-08-26 09:47:12 -0400963 static const struct sde_csc_cfg sde_csc10_YUV2RGB_601L = {
964 {
965 /* S15.16 format */
966 0x00012A00, 0x00000000, 0x00019880,
967 0x00012A00, 0xFFFF9B80, 0xFFFF3000,
968 0x00012A00, 0x00020480, 0x00000000,
969 },
970 /* signed bias */
971 { 0xffc0, 0xfe00, 0xfe00,},
972 { 0x0, 0x0, 0x0,},
973 /* unsigned clamp */
974 { 0x40, 0x3ac, 0x40, 0x3c0, 0x40, 0x3c0,},
975 { 0x00, 0x3ff, 0x00, 0x3ff, 0x00, 0x3ff,},
976 };
Clarence Ipe78efb72016-06-24 18:35:21 -0400977
Clarence Ip5fc00c52016-09-23 15:03:34 -0400978 if (!psde) {
979 SDE_ERROR("invalid plane\n");
Clarence Ipaa0faf42016-05-30 12:07:48 -0400980 return;
981 }
Clarence Ip5e2a9222016-06-26 22:38:24 -0400982
Clarence Ipcae1bb62016-07-07 12:07:13 -0400983 /* revert to kernel default if override not available */
Clarence Ip5fc00c52016-09-23 15:03:34 -0400984 if (psde->csc_usr_ptr)
985 psde->csc_ptr = psde->csc_usr_ptr;
abeykun1c312f62016-08-26 09:47:12 -0400986 else if (BIT(SDE_SSPP_CSC_10BIT) & psde->features)
987 psde->csc_ptr = (struct sde_csc_cfg *)&sde_csc10_YUV2RGB_601L;
Clarence Ip5fc00c52016-09-23 15:03:34 -0400988 else
Clarence Ip373f8592016-05-26 00:58:42 -0400989 psde->csc_ptr = (struct sde_csc_cfg *)&sde_csc_YUV2RGB_601L;
Clarence Ip5fc00c52016-09-23 15:03:34 -0400990
Clarence Ip13a8cf42016-09-29 17:27:47 -0400991 SDE_DEBUG_PLANE(psde, "using 0x%X 0x%X 0x%X...\n",
Clarence Ip5fc00c52016-09-23 15:03:34 -0400992 psde->csc_ptr->csc_mv[0],
993 psde->csc_ptr->csc_mv[1],
994 psde->csc_ptr->csc_mv[2]);
Clarence Ipe78efb72016-06-24 18:35:21 -0400995}
996
Benet Clarkeb1b4462016-06-27 14:43:06 -0700997static void sde_color_process_plane_setup(struct drm_plane *plane)
998{
999 struct sde_plane *psde;
1000 struct sde_plane_state *pstate;
1001 uint32_t hue, saturation, value, contrast;
Benet Clarkd009b1d2016-06-27 14:45:59 -07001002 struct drm_msm_memcol *memcol = NULL;
1003 size_t memcol_sz = 0;
Benet Clarkeb1b4462016-06-27 14:43:06 -07001004
1005 psde = to_sde_plane(plane);
1006 pstate = to_sde_plane_state(plane->state);
1007
1008 hue = (uint32_t) sde_plane_get_property(pstate, PLANE_PROP_HUE_ADJUST);
1009 if (psde->pipe_hw->ops.setup_pa_hue)
1010 psde->pipe_hw->ops.setup_pa_hue(psde->pipe_hw, &hue);
1011 saturation = (uint32_t) sde_plane_get_property(pstate,
1012 PLANE_PROP_SATURATION_ADJUST);
1013 if (psde->pipe_hw->ops.setup_pa_sat)
1014 psde->pipe_hw->ops.setup_pa_sat(psde->pipe_hw, &saturation);
1015 value = (uint32_t) sde_plane_get_property(pstate,
1016 PLANE_PROP_VALUE_ADJUST);
1017 if (psde->pipe_hw->ops.setup_pa_val)
1018 psde->pipe_hw->ops.setup_pa_val(psde->pipe_hw, &value);
1019 contrast = (uint32_t) sde_plane_get_property(pstate,
1020 PLANE_PROP_CONTRAST_ADJUST);
1021 if (psde->pipe_hw->ops.setup_pa_cont)
1022 psde->pipe_hw->ops.setup_pa_cont(psde->pipe_hw, &contrast);
Benet Clarkeb1b4462016-06-27 14:43:06 -07001023
Benet Clarkd009b1d2016-06-27 14:45:59 -07001024 if (psde->pipe_hw->ops.setup_pa_memcolor) {
1025 /* Skin memory color setup */
1026 memcol = msm_property_get_blob(&psde->property_info,
1027 pstate->property_blobs,
1028 &memcol_sz,
1029 PLANE_PROP_SKIN_COLOR);
1030 psde->pipe_hw->ops.setup_pa_memcolor(psde->pipe_hw,
1031 MEMCOLOR_SKIN, memcol);
1032
1033 /* Sky memory color setup */
1034 memcol = msm_property_get_blob(&psde->property_info,
1035 pstate->property_blobs,
1036 &memcol_sz,
1037 PLANE_PROP_SKY_COLOR);
1038 psde->pipe_hw->ops.setup_pa_memcolor(psde->pipe_hw,
1039 MEMCOLOR_SKY, memcol);
1040
1041 /* Foliage memory color setup */
1042 memcol = msm_property_get_blob(&psde->property_info,
1043 pstate->property_blobs,
1044 &memcol_sz,
1045 PLANE_PROP_FOLIAGE_COLOR);
1046 psde->pipe_hw->ops.setup_pa_memcolor(psde->pipe_hw,
1047 MEMCOLOR_FOLIAGE, memcol);
1048 }
1049}
Benet Clarkeb1b4462016-06-27 14:43:06 -07001050
Clarence Ipcb410d42016-06-26 22:52:33 -04001051static void _sde_plane_setup_scaler(struct sde_plane *psde,
Lloyd Atkinson9a673492016-07-05 11:41:57 -04001052 const struct sde_format *fmt,
Clarence Ipcb410d42016-06-26 22:52:33 -04001053 struct sde_plane_state *pstate)
Narendra Muppalla1b0b3352015-09-29 10:16:51 -07001054{
Clarence Ipb43d4592016-09-08 14:21:35 -04001055 struct sde_hw_pixel_ext *pe;
Clarence Ipcb410d42016-06-26 22:52:33 -04001056 uint32_t chroma_subsmpl_h, chroma_subsmpl_v;
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001057
Clarence Ipb43d4592016-09-08 14:21:35 -04001058 if (!psde || !fmt) {
1059 SDE_ERROR("invalid arg(s), plane %d fmt %d state %d\n",
1060 psde != 0, fmt != 0, pstate != 0);
Clarence Ipcb410d42016-06-26 22:52:33 -04001061 return;
Clarence Ipb43d4592016-09-08 14:21:35 -04001062 }
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001063
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001064 pe = &(psde->pixel_ext);
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001065
Clarence Ipdedbba92016-09-27 17:43:10 -04001066 psde->pipe_cfg.horz_decimation =
1067 sde_plane_get_property(pstate, PLANE_PROP_H_DECIMATE);
1068 psde->pipe_cfg.vert_decimation =
1069 sde_plane_get_property(pstate, PLANE_PROP_V_DECIMATE);
Clarence Ip04ec67d2016-05-26 01:16:15 -04001070
1071 /* don't chroma subsample if decimating */
1072 chroma_subsmpl_h = psde->pipe_cfg.horz_decimation ? 1 :
Lloyd Atkinson9a673492016-07-05 11:41:57 -04001073 drm_format_horz_chroma_subsampling(fmt->base.pixel_format);
Clarence Ip04ec67d2016-05-26 01:16:15 -04001074 chroma_subsmpl_v = psde->pipe_cfg.vert_decimation ? 1 :
Lloyd Atkinson9a673492016-07-05 11:41:57 -04001075 drm_format_vert_chroma_subsampling(fmt->base.pixel_format);
Clarence Ip04ec67d2016-05-26 01:16:15 -04001076
Clarence Ip5e2a9222016-06-26 22:38:24 -04001077 /* update scaler */
1078 if (psde->features & BIT(SDE_SSPP_SCALER_QSEED3)) {
abeykun48f407a2016-08-25 12:06:44 -04001079 int error;
1080
1081 error = _sde_plane_setup_scaler3_lut(psde, pstate);
Clarence Ip716ab662017-03-20 06:51:24 -07001082 if (error || !psde->pixel_ext_usr ||
1083 psde->debugfs_default_scale) {
Clarence Ipb43d4592016-09-08 14:21:35 -04001084 /* calculate default config for QSEED3 */
Clarence Ipcb410d42016-06-26 22:52:33 -04001085 _sde_plane_setup_scaler3(psde,
1086 psde->pipe_cfg.src_rect.w,
1087 psde->pipe_cfg.src_rect.h,
1088 psde->pipe_cfg.dst_rect.w,
1089 psde->pipe_cfg.dst_rect.h,
abeykun48f407a2016-08-25 12:06:44 -04001090 psde->scaler3_cfg, fmt,
Clarence Ip5e2a9222016-06-26 22:38:24 -04001091 chroma_subsmpl_h, chroma_subsmpl_v);
Clarence Ip5e2a9222016-06-26 22:38:24 -04001092 }
Clarence Ip716ab662017-03-20 06:51:24 -07001093 } else if (!psde->pixel_ext_usr || !pstate ||
1094 psde->debugfs_default_scale) {
Lloyd Atkinsoncd43ca62016-11-29 14:13:11 -05001095 uint32_t deci_dim, i;
1096
Clarence Ipb43d4592016-09-08 14:21:35 -04001097 /* calculate default configuration for QSEED2 */
1098 memset(pe, 0, sizeof(struct sde_hw_pixel_ext));
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001099
Clarence Ip13a8cf42016-09-29 17:27:47 -04001100 SDE_DEBUG_PLANE(psde, "default config\n");
Lloyd Atkinsoncd43ca62016-11-29 14:13:11 -05001101 deci_dim = DECIMATED_DIMENSION(psde->pipe_cfg.src_rect.w,
1102 psde->pipe_cfg.horz_decimation);
Clarence Ipb43d4592016-09-08 14:21:35 -04001103 _sde_plane_setup_scaler2(psde,
Lloyd Atkinsoncd43ca62016-11-29 14:13:11 -05001104 deci_dim,
Clarence Ipb43d4592016-09-08 14:21:35 -04001105 psde->pipe_cfg.dst_rect.w,
1106 pe->phase_step_x,
1107 pe->horz_filter, fmt, chroma_subsmpl_h);
Clarence Ip5e2a9222016-06-26 22:38:24 -04001108
Clarence Ipdbde9832016-06-26 09:48:36 -04001109 if (SDE_FORMAT_IS_YUV(fmt))
Lloyd Atkinsoncd43ca62016-11-29 14:13:11 -05001110 deci_dim &= ~0x1;
Clarence Ipcb410d42016-06-26 22:52:33 -04001111 _sde_plane_setup_pixel_ext(psde, psde->pipe_cfg.src_rect.w,
Lloyd Atkinsoncd43ca62016-11-29 14:13:11 -05001112 psde->pipe_cfg.dst_rect.w, deci_dim,
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001113 pe->phase_step_x,
1114 pe->roi_w,
1115 pe->num_ext_pxls_left,
Clarence Ipe78efb72016-06-24 18:35:21 -04001116 pe->num_ext_pxls_right, pe->horz_filter, fmt,
Clarence Ip5e2a9222016-06-26 22:38:24 -04001117 chroma_subsmpl_h, 0);
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001118
Lloyd Atkinsoncd43ca62016-11-29 14:13:11 -05001119 deci_dim = DECIMATED_DIMENSION(psde->pipe_cfg.src_rect.h,
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001120 psde->pipe_cfg.vert_decimation);
Lloyd Atkinsoncd43ca62016-11-29 14:13:11 -05001121 _sde_plane_setup_scaler2(psde,
1122 deci_dim,
1123 psde->pipe_cfg.dst_rect.h,
1124 pe->phase_step_y,
1125 pe->vert_filter, fmt, chroma_subsmpl_v);
Clarence Ipcb410d42016-06-26 22:52:33 -04001126 _sde_plane_setup_pixel_ext(psde, psde->pipe_cfg.src_rect.h,
Lloyd Atkinsoncd43ca62016-11-29 14:13:11 -05001127 psde->pipe_cfg.dst_rect.h, deci_dim,
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001128 pe->phase_step_y,
1129 pe->roi_h,
1130 pe->num_ext_pxls_top,
Clarence Ipe78efb72016-06-24 18:35:21 -04001131 pe->num_ext_pxls_btm, pe->vert_filter, fmt,
Clarence Ip5e2a9222016-06-26 22:38:24 -04001132 chroma_subsmpl_v, 1);
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001133
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001134 for (i = 0; i < SDE_MAX_PLANES; i++) {
1135 if (pe->num_ext_pxls_left[i] >= 0)
Clarence Ipb43d4592016-09-08 14:21:35 -04001136 pe->left_rpt[i] = pe->num_ext_pxls_left[i];
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001137 else
Clarence Ipb43d4592016-09-08 14:21:35 -04001138 pe->left_ftch[i] = pe->num_ext_pxls_left[i];
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001139
1140 if (pe->num_ext_pxls_right[i] >= 0)
Clarence Ipb43d4592016-09-08 14:21:35 -04001141 pe->right_rpt[i] = pe->num_ext_pxls_right[i];
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001142 else
Clarence Ipb43d4592016-09-08 14:21:35 -04001143 pe->right_ftch[i] = pe->num_ext_pxls_right[i];
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001144
1145 if (pe->num_ext_pxls_top[i] >= 0)
Clarence Ipb43d4592016-09-08 14:21:35 -04001146 pe->top_rpt[i] = pe->num_ext_pxls_top[i];
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001147 else
Clarence Ipb43d4592016-09-08 14:21:35 -04001148 pe->top_ftch[i] = pe->num_ext_pxls_top[i];
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001149
1150 if (pe->num_ext_pxls_btm[i] >= 0)
Clarence Ipb43d4592016-09-08 14:21:35 -04001151 pe->btm_rpt[i] = pe->num_ext_pxls_btm[i];
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001152 else
Clarence Ipb43d4592016-09-08 14:21:35 -04001153 pe->btm_ftch[i] = pe->num_ext_pxls_btm[i];
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001154 }
1155 }
Clarence Ipcb410d42016-06-26 22:52:33 -04001156}
1157
Clarence Ipcae1bb62016-07-07 12:07:13 -04001158/**
1159 * _sde_plane_color_fill - enables color fill on plane
Clarence Ip13a8cf42016-09-29 17:27:47 -04001160 * @psde: Pointer to SDE plane object
Clarence Ipcae1bb62016-07-07 12:07:13 -04001161 * @color: RGB fill color value, [23..16] Blue, [15..8] Green, [7..0] Red
1162 * @alpha: 8-bit fill alpha value, 255 selects 100% alpha
1163 * Returns: 0 on success
1164 */
Clarence Ip13a8cf42016-09-29 17:27:47 -04001165static int _sde_plane_color_fill(struct sde_plane *psde,
Clarence Ipcb410d42016-06-26 22:52:33 -04001166 uint32_t color, uint32_t alpha)
1167{
Lloyd Atkinson9a673492016-07-05 11:41:57 -04001168 const struct sde_format *fmt;
Jeykumar Sankaran2e655032017-02-04 14:05:45 -08001169 const struct drm_plane *plane;
1170 const struct sde_plane_state *pstate;
Clarence Ipcb410d42016-06-26 22:52:33 -04001171
Clarence Ip13a8cf42016-09-29 17:27:47 -04001172 if (!psde) {
Dhaval Patel47302cf2016-08-18 15:04:28 -07001173 SDE_ERROR("invalid plane\n");
Clarence Ipcb410d42016-06-26 22:52:33 -04001174 return -EINVAL;
1175 }
1176
Clarence Ipcb410d42016-06-26 22:52:33 -04001177 if (!psde->pipe_hw) {
Clarence Ip13a8cf42016-09-29 17:27:47 -04001178 SDE_ERROR_PLANE(psde, "invalid plane h/w pointer\n");
Clarence Ipcb410d42016-06-26 22:52:33 -04001179 return -EINVAL;
1180 }
1181
Jeykumar Sankaran2e655032017-02-04 14:05:45 -08001182 plane = &psde->base;
1183 pstate = to_sde_plane_state(plane->state);
1184
Clarence Ip13a8cf42016-09-29 17:27:47 -04001185 SDE_DEBUG_PLANE(psde, "\n");
Clarence Ipcae1bb62016-07-07 12:07:13 -04001186
Clarence Ipcb410d42016-06-26 22:52:33 -04001187 /*
1188 * select fill format to match user property expectation,
1189 * h/w only supports RGB variants
1190 */
Lloyd Atkinson9a673492016-07-05 11:41:57 -04001191 fmt = sde_get_sde_format(DRM_FORMAT_ABGR8888);
Clarence Ipcb410d42016-06-26 22:52:33 -04001192
1193 /* update sspp */
1194 if (fmt && psde->pipe_hw->ops.setup_solidfill) {
1195 psde->pipe_hw->ops.setup_solidfill(psde->pipe_hw,
Jeykumar Sankaran2e655032017-02-04 14:05:45 -08001196 (color & 0xFFFFFF) | ((alpha & 0xFF) << 24),
1197 pstate->multirect_index);
Clarence Ipcb410d42016-06-26 22:52:33 -04001198
1199 /* override scaler/decimation if solid fill */
1200 psde->pipe_cfg.src_rect.x = 0;
1201 psde->pipe_cfg.src_rect.y = 0;
1202 psde->pipe_cfg.src_rect.w = psde->pipe_cfg.dst_rect.w;
1203 psde->pipe_cfg.src_rect.h = psde->pipe_cfg.dst_rect.h;
1204
Clarence Ipcb410d42016-06-26 22:52:33 -04001205 if (psde->pipe_hw->ops.setup_format)
1206 psde->pipe_hw->ops.setup_format(psde->pipe_hw,
Jeykumar Sankaran2e655032017-02-04 14:05:45 -08001207 fmt, SDE_SSPP_SOLID_FILL,
1208 pstate->multirect_index);
Clarence Ipcb410d42016-06-26 22:52:33 -04001209
1210 if (psde->pipe_hw->ops.setup_rects)
1211 psde->pipe_hw->ops.setup_rects(psde->pipe_hw,
Jeykumar Sankaran9fcfa482017-02-16 16:03:14 -08001212 &psde->pipe_cfg,
1213 pstate->multirect_index);
1214
1215 _sde_plane_setup_scaler(psde, fmt, 0);
1216 if (psde->pipe_hw->ops.setup_pe)
1217 psde->pipe_hw->ops.setup_pe(psde->pipe_hw,
1218 &psde->pixel_ext);
Clarence Ipcb410d42016-06-26 22:52:33 -04001219 }
1220
1221 return 0;
1222}
1223
Alan Kwong4dd64c82017-02-04 18:41:51 -08001224/**
Alan Kwong4aacd532017-02-04 18:51:33 -08001225 * sde_plane_rot_calc_prefill - calculate rotator start prefill
Alan Kwong4dd64c82017-02-04 18:41:51 -08001226 * @plane: Pointer to drm plane
1227 * return: prefill time in line
1228 */
1229static u32 sde_plane_rot_calc_prefill(struct drm_plane *plane)
1230{
1231 struct drm_plane_state *state;
1232 struct drm_crtc_state *cstate;
1233 struct sde_plane_state *pstate;
1234 struct sde_plane_rot_state *rstate;
1235 struct sde_kms *sde_kms;
1236 u32 blocksize = 128;
1237 u32 prefill_line = 0;
1238
1239 if (!plane || !plane->state || !plane->state->fb ||
1240 !plane->state->crtc || !plane->state->crtc->state) {
1241 SDE_ERROR("invalid parameters\n");
1242 return 0;
1243 }
1244
1245 sde_kms = _sde_plane_get_kms(plane);
1246 state = plane->state;
1247 cstate = state->crtc->state;
1248 pstate = to_sde_plane_state(state);
1249 rstate = &pstate->rot;
1250
1251 if (!rstate->rot_hw || !rstate->rot_hw->caps || !rstate->out_src_h ||
1252 !sde_kms || !sde_kms->catalog) {
1253 SDE_ERROR("invalid parameters\n");
1254 return 0;
1255 }
1256
Alan Kwong4aacd532017-02-04 18:51:33 -08001257 sde_format_get_block_size(rstate->out_fb_format, &blocksize,
1258 &blocksize);
Alan Kwong4dd64c82017-02-04 18:41:51 -08001259 prefill_line = blocksize + sde_kms->catalog->sbuf_headroom;
1260
1261 SDE_DEBUG("plane%d prefill:%u\n", plane->base.id, prefill_line);
1262
1263 return prefill_line;
1264}
1265
1266/**
1267 * sde_plane_is_sbuf_mode - check if sspp of given plane is in streaming
1268 * buffer mode
1269 * @plane: Pointer to drm plane
1270 * @prefill: Pointer to prefill line count
1271 * return: true if sspp is in stream buffer mode
1272 */
1273bool sde_plane_is_sbuf_mode(struct drm_plane *plane, u32 *prefill)
1274{
1275 struct sde_plane_state *pstate = plane && plane->state ?
1276 to_sde_plane_state(plane->state) : NULL;
1277 struct sde_plane_rot_state *rstate = pstate ? &pstate->rot : NULL;
1278 bool sbuf_mode = rstate ? rstate->out_sbuf : false;
1279
1280 if (prefill && sbuf_mode)
1281 *prefill = sde_plane_rot_calc_prefill(plane);
1282
1283 return sbuf_mode;
1284}
1285
1286/**
1287 * sde_plane_rot_calc_cfg - calculate rotator/sspp configuration by
1288 * enumerating over all planes attached to the same rotator
1289 * @plane: Pointer to drm plane
1290 * @state: Pointer to drm state to be updated
1291 * return: none
1292 */
1293static void sde_plane_rot_calc_cfg(struct drm_plane *plane,
1294 struct drm_plane_state *state)
1295{
1296 struct sde_plane_state *pstate;
1297 struct sde_plane_rot_state *rstate;
1298 struct sde_hw_blk *hw_blk;
1299 struct sde_hw_blk_attachment *attach;
1300 struct drm_rect *in_rot, *out_rot;
1301 u32 dst_x, dst_y, dst_w, dst_h;
1302 int found = 0;
1303 int xpos = 0;
1304
1305 if (!plane || !state || !state->state) {
1306 SDE_ERROR("invalid parameters\n");
1307 return;
1308 }
1309
1310 pstate = to_sde_plane_state(state);
1311 rstate = &pstate->rot;
1312
1313 if (!rstate->rot_hw) {
1314 SDE_ERROR("invalid rotator hw\n");
1315 return;
1316 }
1317
1318 in_rot = &rstate->in_rot_rect;
1319 in_rot->x1 = state->src_x;
1320 in_rot->y1 = state->src_y;
1321 in_rot->x2 = state->src_x + state->src_w;
1322 in_rot->y2 = state->src_y + state->src_h;
1323
1324 out_rot = &rstate->out_rot_rect;
1325 dst_x = sde_plane_get_property(pstate, PLANE_PROP_ROT_DST_X);
1326 dst_y = sde_plane_get_property(pstate, PLANE_PROP_ROT_DST_Y);
1327 dst_w = sde_plane_get_property(pstate, PLANE_PROP_ROT_DST_W);
1328 dst_h = sde_plane_get_property(pstate, PLANE_PROP_ROT_DST_H);
1329
1330 if (!dst_w && !dst_h) {
1331 rstate->out_rot_rect = rstate->in_rot_rect;
1332 drm_rect_rotate(&rstate->out_rot_rect, state->fb->width << 16,
1333 state->fb->height << 16, rstate->in_rotation);
1334 } else {
1335 out_rot->x1 = dst_x;
1336 out_rot->y1 = dst_y;
1337 out_rot->x2 = dst_x + dst_w;
1338 out_rot->y2 = dst_y + dst_h;
1339 }
1340
1341 rstate->out_src_rect = rstate->out_rot_rect;
1342
1343 hw_blk = &rstate->rot_hw->base;
1344
1345 /* enumerating over all planes attached to the same rotator */
1346 list_for_each_entry(attach, &hw_blk->attach_list, list) {
1347 struct drm_plane *attached_plane;
1348 struct drm_plane_state *attached_state;
1349 struct sde_plane_state *attached_pstate;
1350 struct sde_plane_rot_state *attached_rstate;
1351 struct drm_rect attached_out_rect;
1352
1353 if (attach->tag != SDE_TAG_ROT_PLANE)
1354 continue;
1355
1356 attached_plane = attach->value;
1357
1358 found++;
1359
1360 /* skip itself */
1361 if (attached_plane == plane)
1362 continue;
1363
1364 attached_state = drm_atomic_get_existing_plane_state(
1365 state->state, attached_plane);
1366
1367 if (!attached_state)
1368 continue;
1369
1370 attached_pstate = to_sde_plane_state(attached_state);
1371 attached_rstate = &attached_pstate->rot;
1372
1373 /* find bounding rotator source roi */
1374 if (attached_state->src_x < in_rot->x1)
1375 in_rot->x1 = attached_state->src_x;
1376
1377 if (attached_state->src_y < in_rot->y1)
1378 in_rot->y1 = attached_state->src_y;
1379
1380 if (attached_state->src_x + attached_state->src_w > in_rot->x2)
1381 in_rot->x2 = attached_state->src_x +
1382 attached_state->src_w;
1383
1384 if (attached_state->src_y + attached_state->src_h > in_rot->y2)
1385 in_rot->y2 = attached_state->src_y +
1386 attached_state->src_h;
1387
1388 /* find bounding rotator destination roi */
1389 dst_x = sde_plane_get_property(attached_pstate,
1390 PLANE_PROP_ROT_DST_X);
1391 dst_y = sde_plane_get_property(attached_pstate,
1392 PLANE_PROP_ROT_DST_Y);
1393 dst_w = sde_plane_get_property(attached_pstate,
1394 PLANE_PROP_ROT_DST_W);
1395 dst_h = sde_plane_get_property(attached_pstate,
1396 PLANE_PROP_ROT_DST_H);
1397 if (!dst_w && !dst_h) {
1398 attached_out_rect.x1 = attached_state->src_x;
1399 attached_out_rect.y1 = attached_state->src_y;
1400 attached_out_rect.x2 = attached_out_rect.x1 +
1401 attached_state->src_w;
1402 attached_out_rect.y2 = attached_out_rect.y1 +
1403 attached_state->src_h;
1404 drm_rect_rotate(&attached_out_rect,
1405 state->fb->width << 16,
1406 state->fb->height << 16,
1407 rstate->in_rotation);
1408 } else {
1409 attached_out_rect.x1 = dst_x;
1410 attached_out_rect.y1 = dst_y;
1411 attached_out_rect.x2 = dst_x + dst_w;
1412 attached_out_rect.y2 = dst_y + dst_h;
1413 }
1414
1415 /* find relative sspp position */
1416 if (attached_out_rect.x1 < rstate->out_src_rect.x1)
1417 xpos++;
1418
1419 if (attached_out_rect.x1 < out_rot->x1)
1420 out_rot->x1 = attached_out_rect.x1;
1421
1422 if (attached_out_rect.y1 < out_rot->y1)
1423 out_rot->y1 = attached_out_rect.y1;
1424
1425 if (attached_out_rect.x2 > out_rot->x2)
1426 out_rot->x2 = attached_out_rect.x2;
1427
1428 if (attached_out_rect.y2 > out_rot->y2)
1429 out_rot->y2 = attached_out_rect.y2;
1430
1431 SDE_DEBUG("plane%d.%u src_x:%d sspp:%dx%d+%d+%d/%dx%d+%d+%d\n",
1432 attached_plane->base.id,
1433 attached_rstate->sequence_id,
1434 attached_rstate->out_src_rect.x1 >> 16,
1435 attached_state->src_w >> 16,
1436 attached_state->src_h >> 16,
1437 attached_state->src_x >> 16,
1438 attached_state->src_y >> 16,
1439 drm_rect_width(&attached_rstate->out_src_rect) >> 16,
1440 drm_rect_height(&attached_rstate->out_src_rect) >> 16,
1441 attached_rstate->out_src_rect.x1 >> 16,
1442 attached_rstate->out_src_rect.y1 >> 16);
1443 }
1444
1445 rstate->out_xpos = xpos;
1446 rstate->nplane = found;
1447
1448 SDE_DEBUG("plane%d.%u xpos:%d/%d rot:%dx%d+%d+%d/%dx%d+%d+%d\n",
1449 plane->base.id, rstate->sequence_id,
1450 rstate->out_xpos, rstate->nplane,
1451 drm_rect_width(in_rot) >> 16,
1452 drm_rect_height(in_rot) >> 16,
1453 in_rot->x1 >> 16, in_rot->y1 >> 16,
1454 drm_rect_width(&rstate->out_rot_rect) >> 16,
1455 drm_rect_height(&rstate->out_rot_rect) >> 16,
1456 rstate->out_rot_rect.x1 >> 16,
1457 rstate->out_rot_rect.y1 >> 16);
1458}
1459
1460/**
1461 * sde_plane_rot_submit_command - commit given state for the rotator stage
1462 * @plane: Pointer to drm plane
1463 * @state: Pointer to the state to be committed
1464 * @hw_cmd: rotator command type
1465 * return: 0 if success; error code otherwise
1466 */
1467static int sde_plane_rot_submit_command(struct drm_plane *plane,
1468 struct drm_plane_state *state, enum sde_hw_rot_cmd_type hw_cmd)
1469{
1470 struct sde_plane *psde = to_sde_plane(plane);
1471 struct sde_plane_state *pstate = to_sde_plane_state(state);
1472 struct sde_plane_rot_state *rstate = &pstate->rot;
1473 struct sde_hw_rot_cmd *rot_cmd;
Alan Kwong4aacd532017-02-04 18:51:33 -08001474 struct drm_crtc_state *cstate;
1475 struct sde_crtc_state *sde_cstate;
Alan Kwong4dd64c82017-02-04 18:41:51 -08001476 int ret, i;
1477
1478 if (!plane || !state || !state->fb || !rstate->rot_hw) {
1479 SDE_ERROR("invalid parameters\n");
1480 return -EINVAL;
1481 }
1482
Alan Kwong4aacd532017-02-04 18:51:33 -08001483 cstate = _sde_plane_get_crtc_state(state);
1484 if (IS_ERR_OR_NULL(cstate)) {
1485 SDE_ERROR("invalid crtc state %ld\n", PTR_ERR(cstate));
1486 return -EINVAL;
1487 }
1488 sde_cstate = to_sde_crtc_state(cstate);
1489
Alan Kwong4dd64c82017-02-04 18:41:51 -08001490 rot_cmd = &rstate->rot_cmd;
1491
1492 rot_cmd->master = (rstate->out_xpos == 0);
1493 rot_cmd->sequence_id = rstate->sequence_id;
1494 rot_cmd->fps = pstate->base.crtc && pstate->base.crtc->state ?
1495 drm_mode_vrefresh(&pstate->base.crtc->state->adjusted_mode) :
1496 DEFAULT_REFRESH_RATE;
1497 rot_cmd->rot90 = rstate->rot90;
1498 rot_cmd->hflip = rstate->hflip;
1499 rot_cmd->vflip = rstate->vflip;
1500 rot_cmd->secure = state->fb->flags & DRM_MODE_FB_SECURE ? true : false;
Alan Kwong4aacd532017-02-04 18:51:33 -08001501 rot_cmd->prefill_bw = sde_crtc_get_property(sde_cstate,
1502 CRTC_PROP_ROT_PREFILL_BW);
Alan Kwong8c176bf2017-02-09 19:34:32 -08001503 rot_cmd->clkrate = sde_crtc_get_property(sde_cstate,
1504 CRTC_PROP_ROT_CLK);
Alan Kwong4dd64c82017-02-04 18:41:51 -08001505 rot_cmd->dst_writeback = psde->sbuf_writeback;
1506
1507 if (sde_crtc_get_intf_mode(state->crtc) == INTF_MODE_VIDEO)
1508 rot_cmd->video_mode = true;
1509 else
1510 rot_cmd->video_mode = false;
1511
1512 rot_cmd->src_pixel_format = state->fb->pixel_format;
1513 rot_cmd->src_modifier = state->fb->modifier[0];
1514 rot_cmd->src_stride = state->fb->pitches[0];
1515
1516 rot_cmd->src_format = to_sde_format(msm_framebuffer_format(state->fb));
1517 if (!rot_cmd->src_format) {
1518 SDE_ERROR("failed to get src format\n");
1519 return -EINVAL;
1520 }
1521
1522 rot_cmd->src_width = state->fb->width;
1523 rot_cmd->src_height = state->fb->height;
1524 rot_cmd->src_rect_x = rstate->in_rot_rect.x1 >> 16;
1525 rot_cmd->src_rect_y = rstate->in_rot_rect.y1 >> 16;
1526 rot_cmd->src_rect_w = drm_rect_width(&rstate->in_rot_rect) >> 16;
1527 rot_cmd->src_rect_h = drm_rect_height(&rstate->in_rot_rect) >> 16;
1528 rot_cmd->dst_rect_x = rstate->out_rot_rect.x1 >> 16;
1529 rot_cmd->dst_rect_y = rstate->out_rot_rect.y1 >> 16;
1530 rot_cmd->dst_rect_w = drm_rect_width(&rstate->out_rot_rect) >> 16;
1531 rot_cmd->dst_rect_h = drm_rect_height(&rstate->out_rot_rect) >> 16;
1532
1533 if (hw_cmd == SDE_HW_ROT_CMD_COMMIT) {
1534 struct sde_hw_fmt_layout layout;
1535
1536 memset(&layout, 0, sizeof(struct sde_hw_fmt_layout));
1537 sde_format_populate_layout(rstate->mmu_id, state->fb,
1538 &layout);
1539 for (i = 0; i < ARRAY_SIZE(rot_cmd->src_iova); i++) {
1540 rot_cmd->src_iova[i] = layout.plane_addr[i];
1541 rot_cmd->src_len[i] = layout.plane_size[i];
1542 }
1543 rot_cmd->src_planes = layout.num_planes;
1544
1545 memset(&layout, 0, sizeof(struct sde_hw_fmt_layout));
1546 sde_format_populate_layout(rstate->mmu_id, rstate->out_fb,
1547 &layout);
1548 for (i = 0; i < ARRAY_SIZE(rot_cmd->dst_iova); i++) {
1549 rot_cmd->dst_iova[i] = layout.plane_addr[i];
1550 rot_cmd->dst_len[i] = layout.plane_size[i];
1551 }
1552 rot_cmd->dst_planes = layout.num_planes;
1553 }
1554
1555 ret = rstate->rot_hw->ops.commit(rstate->rot_hw, rot_cmd, hw_cmd);
1556 if (ret) {
1557 SDE_ERROR("failed to commit rotator %d\n", ret);
1558 return ret;
1559 }
1560
1561 rstate->out_rotation = rstate->in_rotation;
1562 rstate->out_fb_flags = rot_cmd->dst_modifier ?
1563 DRM_MODE_FB_MODIFIERS : 0;
1564 rstate->out_fb_flags |= rot_cmd->secure ? DRM_MODE_FB_SECURE : 0;
1565 rstate->out_fb_format = rot_cmd->dst_format;
1566 rstate->out_fb_pixel_format = rot_cmd->dst_pixel_format;
1567
1568 for (i = 0; i < ARRAY_SIZE(rstate->out_fb_modifier); i++)
1569 rstate->out_fb_modifier[i] = rot_cmd->dst_modifier;
1570
1571 rstate->out_fb_width = drm_rect_width(&rstate->out_rot_rect) >> 16;
1572 rstate->out_fb_height = drm_rect_height(&rstate->out_rot_rect) >> 16;
1573 rstate->out_src_x = rstate->out_src_rect.x1 - rstate->out_rot_rect.x1;
1574 rstate->out_src_y = rstate->out_src_rect.y1 - rstate->out_rot_rect.y1;
1575 rstate->out_src_w = drm_rect_width(&rstate->out_src_rect);
1576 rstate->out_src_h = drm_rect_height(&rstate->out_src_rect);
1577
1578 if (rot_cmd->rot90)
1579 rstate->out_rotation &= ~DRM_ROTATE_90;
1580
1581 if (rot_cmd->hflip)
1582 rstate->out_rotation &= ~DRM_REFLECT_X;
1583
1584 if (rot_cmd->vflip)
1585 rstate->out_rotation &= ~DRM_REFLECT_Y;
1586
1587 SDE_DEBUG(
1588 "plane%d.%d rot:%d/%c%c%c%c/%dx%d/%c%c%c%c/%llx/%dx%d+%d+%d\n",
1589 plane->base.id, rstate->sequence_id, hw_cmd,
1590 rot_cmd->rot90 ? 'r' : '_',
1591 rot_cmd->hflip ? 'h' : '_',
1592 rot_cmd->vflip ? 'v' : '_',
1593 rot_cmd->video_mode ? 'V' : 'C',
1594 state->fb->width, state->fb->height,
1595 state->fb->pixel_format >> 0,
1596 state->fb->pixel_format >> 8,
1597 state->fb->pixel_format >> 16,
1598 state->fb->pixel_format >> 24,
1599 state->fb->modifier[0],
1600 drm_rect_width(&rstate->in_rot_rect) >> 16,
1601 drm_rect_height(&rstate->in_rot_rect) >> 16,
1602 rstate->in_rot_rect.x1 >> 16,
1603 rstate->in_rot_rect.y1 >> 16);
1604
1605 SDE_DEBUG("plane%d.%d sspp:%d/%x/%dx%d/%c%c%c%c/%llx/%dx%d+%d+%d\n",
1606 plane->base.id, rstate->sequence_id, hw_cmd,
1607 rstate->out_rotation,
1608 rstate->out_fb_width, rstate->out_fb_height,
1609 rstate->out_fb_pixel_format >> 0,
1610 rstate->out_fb_pixel_format >> 8,
1611 rstate->out_fb_pixel_format >> 16,
1612 rstate->out_fb_pixel_format >> 24,
1613 rstate->out_fb_modifier[0],
1614 rstate->out_src_w >> 16, rstate->out_src_h >> 16,
1615 rstate->out_src_x >> 16, rstate->out_src_y >> 16);
1616
1617 return ret;
1618}
1619
1620/**
1621 * sde_plane_rot_prepare_fb - prepare framebuffer of the new state
1622 * for rotator (pre-sspp) stage
1623 * @plane: Pointer to drm plane
1624 * @new_state: Pointer to new drm plane state
1625 * return: 0 if success; error code otherwise
1626 */
1627static int sde_plane_rot_prepare_fb(struct drm_plane *plane,
1628 struct drm_plane_state *new_state)
1629{
1630 struct drm_framebuffer *fb = new_state->fb;
1631 struct sde_plane_state *new_pstate = to_sde_plane_state(new_state);
1632 struct sde_plane_rot_state *new_rstate = &new_pstate->rot;
1633 int ret;
1634
1635 SDE_DEBUG("plane%d.%d FB[%u] sbuf:%d rot:%d crtc:%d\n",
1636 plane->base.id,
1637 new_rstate->sequence_id, fb ? fb->base.id : 0,
1638 !!new_rstate->out_sbuf, !!new_rstate->rot_hw,
1639 sde_plane_crtc_enabled(new_state));
1640
1641 if (!new_rstate->out_sbuf || !new_rstate->rot_hw)
1642 return 0;
1643
1644 /* need to re-calc based on all newly validated plane states */
1645 sde_plane_rot_calc_cfg(plane, new_state);
1646
1647 /* check if stream buffer is already attached to rotator */
1648 if (sde_plane_enabled(new_state)) {
1649 struct sde_kms_fbo *fbo;
1650 struct drm_framebuffer *fb;
1651
1652 fbo = sde_hw_blk_lookup_value(&new_rstate->rot_hw->base,
1653 SDE_TAG_ROT_OUT_FBO, 0);
1654 fb = sde_hw_blk_lookup_value(&new_rstate->rot_hw->base,
1655 SDE_TAG_ROT_OUT_FB, 0);
1656 if (fb && fbo) {
1657 SDE_DEBUG("plane%d.%d get fb/fbo\n", plane->base.id,
1658 new_rstate->sequence_id);
1659
1660 new_rstate->out_fbo = fbo;
1661 sde_kms_fbo_reference(new_rstate->out_fbo);
1662 sde_hw_blk_attach(&new_rstate->rot_hw->base,
1663 SDE_TAG_ROT_OUT_FBO,
1664 new_rstate->out_fbo);
1665
1666 new_rstate->out_fb = fb;
1667 drm_framebuffer_reference(new_rstate->out_fb);
1668 sde_hw_blk_attach(&new_rstate->rot_hw->base,
1669 SDE_TAG_ROT_OUT_FB,
1670 new_rstate->out_fb);
1671 }
1672 }
1673
1674 /* release buffer if output format configuration changes */
1675 if (new_rstate->out_fb &&
1676 ((new_rstate->out_fb_height != new_rstate->out_fb->height) ||
1677 (new_rstate->out_fb_width != new_rstate->out_fb->width) ||
1678 (new_rstate->out_fb_pixel_format !=
1679 new_rstate->out_fb->pixel_format) ||
1680 (new_rstate->out_fb_modifier[0] !=
1681 new_rstate->out_fb->modifier[0]) ||
1682 (new_rstate->out_fb_flags != new_rstate->out_fb->flags))) {
1683
1684 SDE_DEBUG("plane%d.%d release fb/fbo\n", plane->base.id,
1685 new_rstate->sequence_id);
1686
1687 sde_hw_blk_detach(&new_rstate->rot_hw->base,
1688 SDE_TAG_ROT_OUT_FB, new_rstate->out_fb);
1689 drm_framebuffer_unreference(new_rstate->out_fb);
1690 new_rstate->out_fb = NULL;
1691 sde_hw_blk_detach(&new_rstate->rot_hw->base,
1692 SDE_TAG_ROT_OUT_FBO, new_rstate->out_fbo);
1693 sde_kms_fbo_unreference(new_rstate->out_fbo);
1694 new_rstate->out_fbo = NULL;
1695 }
1696
1697 /* create new stream buffer if it is not available */
1698 if (sde_plane_enabled(new_state) && !new_rstate->out_fb) {
1699 u32 fb_w = drm_rect_width(&new_rstate->out_rot_rect) >> 16;
1700 u32 fb_h = drm_rect_height(&new_rstate->out_rot_rect) >> 16;
1701
1702 SDE_DEBUG("plane%d.%d allocate fb/fbo\n", plane->base.id,
1703 new_rstate->sequence_id);
1704
1705 if (new_state->fb->flags & DRM_MODE_FB_SECURE)
1706 new_rstate->mmu_id = MSM_SMMU_DOMAIN_SECURE;
1707 else
1708 new_rstate->mmu_id = MSM_SMMU_DOMAIN_UNSECURE;
1709
1710 /* check if out_fb is already attached to rotator */
1711 new_rstate->out_fbo = sde_kms_fbo_alloc(plane->dev, fb_w, fb_h,
1712 new_rstate->out_fb_pixel_format,
1713 new_rstate->out_fb_modifier,
1714 new_rstate->out_fb_flags);
1715 if (!new_rstate->out_fbo) {
1716 SDE_ERROR("failed to allocate inline buffer object\n");
1717 ret = -EINVAL;
1718 goto error_create_fbo;
1719 }
1720
1721 sde_hw_blk_attach(&new_rstate->rot_hw->base,
1722 SDE_TAG_ROT_OUT_FBO, new_rstate->out_fbo);
1723
1724 new_rstate->out_fb = sde_kms_fbo_create_fb(plane->dev,
1725 new_rstate->out_fbo);
1726 if (!new_rstate->out_fb) {
1727 SDE_ERROR("failed to create inline framebuffer\n");
1728 ret = -EINVAL;
1729 goto error_create_fb;
1730 }
1731
1732 sde_hw_blk_attach(&new_rstate->rot_hw->base,
1733 SDE_TAG_ROT_OUT_FB, new_rstate->out_fb);
1734 }
1735
1736 /* prepare rotator input buffer */
1737 ret = msm_framebuffer_prepare(new_state->fb, new_rstate->mmu_id);
1738 if (ret) {
1739 SDE_ERROR("failed to prepare input framebuffer\n");
1740 goto error_prepare_input_buffer;
1741 }
1742
1743 /* prepare rotator output buffer */
1744 if (sde_plane_enabled(new_state) && new_rstate->out_fb) {
1745 SDE_DEBUG("plane%d.%d prepare fb/fbo\n", plane->base.id,
1746 new_rstate->sequence_id);
1747
1748 ret = msm_framebuffer_prepare(new_rstate->out_fb,
1749 new_rstate->mmu_id);
1750 if (ret) {
1751 SDE_ERROR("failed to prepare inline framebuffer\n");
1752 goto error_prepare_output_buffer;
1753 }
1754 }
1755
1756 return 0;
1757
1758error_prepare_output_buffer:
1759 msm_framebuffer_cleanup(new_state->fb, new_rstate->mmu_id);
1760error_prepare_input_buffer:
1761 sde_hw_blk_detach(&new_rstate->rot_hw->base, SDE_TAG_ROT_OUT_FB,
1762 new_rstate->out_fb);
1763 drm_framebuffer_unreference(new_rstate->out_fb);
1764 new_rstate->out_fb = NULL;
1765error_create_fb:
1766 sde_hw_blk_detach(&new_rstate->rot_hw->base, SDE_TAG_ROT_OUT_FBO,
1767 new_rstate->out_fbo);
1768 sde_kms_fbo_unreference(new_rstate->out_fbo);
1769 new_rstate->out_fbo = NULL;
1770error_create_fbo:
1771 return ret;
1772}
1773
1774/**
1775 * sde_plane_rot_cleanup_fb - cleanup framebuffer of previous state for the
1776 * rotator (pre-sspp) stage
1777 * @plane: Pointer to drm plane
1778 * @old_state: Pointer to previous drm plane state
1779 * return: none
1780 */
1781static void sde_plane_rot_cleanup_fb(struct drm_plane *plane,
1782 struct drm_plane_state *old_state)
1783{
1784 struct sde_plane_state *old_pstate = to_sde_plane_state(old_state);
1785 struct sde_plane_rot_state *old_rstate = &old_pstate->rot;
1786 struct sde_hw_rot_cmd *cmd = &old_rstate->rot_cmd;
1787 int ret;
1788
1789 SDE_DEBUG("plane%d.%d FB[%u] sbuf:%d rot:%d crtc:%d\n", plane->base.id,
1790 old_rstate->sequence_id, old_state->fb->base.id,
1791 !!old_rstate->out_sbuf, !!old_rstate->rot_hw,
1792 sde_plane_crtc_enabled(old_state));
1793
1794 if (!old_rstate->out_sbuf || !old_rstate->rot_hw)
1795 return;
1796
1797 if (sde_plane_crtc_enabled(old_state)) {
1798 ret = old_rstate->rot_hw->ops.commit(old_rstate->rot_hw, cmd,
1799 SDE_HW_ROT_CMD_CLEANUP);
1800 if (ret)
1801 SDE_ERROR("failed to cleanup rotator buffers\n");
1802 }
1803
1804 if (sde_plane_enabled(old_state)) {
1805 if (old_rstate->out_fb) {
1806 msm_framebuffer_cleanup(old_rstate->out_fb,
1807 old_rstate->mmu_id);
1808 sde_hw_blk_detach(&old_rstate->rot_hw->base,
1809 SDE_TAG_ROT_OUT_FB,
1810 old_rstate->out_fb);
1811 drm_framebuffer_unreference(old_rstate->out_fb);
1812 old_rstate->out_fb = NULL;
1813 sde_hw_blk_detach(&old_rstate->rot_hw->base,
1814 SDE_TAG_ROT_OUT_FBO,
1815 old_rstate->out_fbo);
1816 sde_kms_fbo_unreference(old_rstate->out_fbo);
1817 old_rstate->out_fbo = NULL;
1818 }
1819
1820 msm_framebuffer_cleanup(old_state->fb, old_rstate->mmu_id);
1821 }
1822}
1823
1824/**
1825 * sde_plane_rot_atomic_check - verify rotator update of the given state
1826 * @plane: Pointer to drm plane
1827 * @state: Pointer to drm plane state to be validated
1828 * return: 0 if success; error code otherwise
1829 */
1830static int sde_plane_rot_atomic_check(struct drm_plane *plane,
1831 struct drm_plane_state *state)
1832{
1833 struct sde_plane *psde;
1834 struct sde_plane_state *pstate, *old_pstate;
1835 struct sde_plane_rot_state *rstate, *old_rstate;
1836 struct sde_hw_blk *hw_blk;
1837 int i, ret = 0;
1838
1839 if (!plane || !state) {
1840 SDE_ERROR("invalid plane/state\n");
1841 return -EINVAL;
1842 }
1843
1844 psde = to_sde_plane(plane);
1845 pstate = to_sde_plane_state(state);
1846 old_pstate = to_sde_plane_state(plane->state);
1847 rstate = &pstate->rot;
1848 old_rstate = &old_pstate->rot;
1849
1850 SDE_DEBUG("plane%d.%d FB[%u] sbuf:%d rot:%d crtc:%d\n", plane->base.id,
1851 rstate->sequence_id, state->fb ? state->fb->base.id : 0,
1852 !!rstate->out_sbuf, !!rstate->rot_hw,
1853 sde_plane_crtc_enabled(state));
1854
1855 rstate->in_rotation = drm_rotation_simplify(
1856 sde_plane_get_property(pstate, PLANE_PROP_ROTATION),
1857 DRM_ROTATE_90 | DRM_REFLECT_X | DRM_REFLECT_Y);
1858 rstate->rot90 = rstate->in_rotation & DRM_ROTATE_90 ? true : false;
1859 rstate->hflip = rstate->in_rotation & DRM_REFLECT_X ? true : false;
1860 rstate->vflip = rstate->in_rotation & DRM_REFLECT_Y ? true : false;
1861 rstate->out_sbuf = psde->sbuf_mode || rstate->rot90;
1862
1863 if ((!sde_plane_enabled(state) || !rstate->out_sbuf) &&
1864 rstate->rot_hw) {
1865
1866 SDE_DEBUG("plane%d.%d release rotator\n",
1867 plane->base.id, rstate->sequence_id);
1868
1869 sde_hw_blk_detach(&rstate->rot_hw->base, SDE_TAG_ROT_IN_FB,
1870 rstate->in_fb);
1871 rstate->in_fb = NULL;
1872 sde_hw_blk_detach(&rstate->rot_hw->base, SDE_TAG_ROT_PLANE,
1873 plane);
1874 sde_hw_rot_put(rstate->rot_hw);
1875 rstate->rot_hw = NULL;
1876
1877 } else if (sde_plane_enabled(state) && rstate->out_sbuf &&
1878 !rstate->rot_hw) {
1879
1880 SDE_DEBUG("plane%d.%d allocate rotator\n",
1881 plane->base.id, rstate->sequence_id);
1882
1883 hw_blk = sde_hw_blk_lookup_blk(SDE_TAG_ROT_IN_FB, state->fb,
1884 SDE_HW_BLK_ROT);
1885 if (hw_blk)
1886 rstate->rot_hw = to_sde_hw_rot(hw_blk);
1887 else
1888 rstate->rot_hw = sde_hw_rot_get(NULL);
1889
1890 if (!rstate->rot_hw) {
1891 SDE_ERROR("plane%d no available rotator\n",
1892 plane->base.id);
1893 return -EINVAL;
1894 }
1895
1896 if (!rstate->rot_hw->ops.commit) {
1897 SDE_ERROR("plane%d invalid rotator ops\n",
1898 plane->base.id);
1899 sde_hw_rot_put(rstate->rot_hw);
1900 rstate->rot_hw = NULL;
1901 return -EINVAL;
1902 }
1903
1904 rstate->in_fb = state->fb;
1905 sde_hw_blk_attach(&rstate->rot_hw->base, SDE_TAG_ROT_IN_FB,
1906 rstate->in_fb);
1907 sde_hw_blk_attach(&rstate->rot_hw->base, SDE_TAG_ROT_PLANE,
1908 plane);
1909
1910 } else if (sde_plane_enabled(state) && rstate->out_sbuf &&
1911 (rstate->in_fb != state->fb)) {
1912
1913 SDE_DEBUG("plane%d.%d update fb\n",
1914 plane->base.id, rstate->sequence_id);
1915
1916 sde_hw_blk_detach(&rstate->rot_hw->base, SDE_TAG_ROT_IN_FB,
1917 rstate->in_fb);
1918 rstate->in_fb = state->fb;
1919 sde_hw_blk_attach(&rstate->rot_hw->base, SDE_TAG_ROT_IN_FB,
1920 rstate->in_fb);
1921 }
1922
1923 if (sde_plane_enabled(state) && rstate->out_sbuf && rstate->rot_hw) {
1924
1925 SDE_DEBUG("plane%d.%d use rotator\n",
1926 plane->base.id, rstate->sequence_id);
1927
1928 sde_plane_rot_calc_cfg(plane, state);
1929
1930 ret = sde_plane_rot_submit_command(plane, state,
1931 SDE_HW_ROT_CMD_VALIDATE);
1932
1933 } else if (sde_plane_enabled(state)) {
1934
1935 SDE_DEBUG("plane%d.%d bypass rotator\n", plane->base.id,
1936 rstate->sequence_id);
1937
1938 /* bypass rotator - initialize output setting as input */
1939 rstate->out_rotation = rstate->in_rotation;
1940 rstate->out_fb_pixel_format = state->fb->pixel_format;
1941
1942 for (i = 0.; i < ARRAY_SIZE(rstate->out_fb_modifier); i++)
1943 rstate->out_fb_modifier[i] = state->fb->modifier[i];
1944
1945 rstate->out_fb_flags = state->fb->flags;
1946 rstate->out_fb_width = state->fb->width;
1947 rstate->out_fb_height = state->fb->height;
1948 rstate->out_src_x = state->src_x;
1949 rstate->out_src_y = state->src_y;
1950 rstate->out_src_w = state->src_w;
1951 rstate->out_src_h = state->src_h;
1952
1953 rstate->out_fb_format = NULL;
1954 rstate->out_sbuf = false;
1955 rstate->out_fb = state->fb;
1956 }
1957
1958 return ret;
1959}
1960
1961/**
1962 * sde_plane_rot_atomic_update - perform atomic update for rotator stage
1963 * @plane: Pointer to drm plane
1964 * @old_state: Pointer to previous state
1965 * return: none
1966 */
1967static void sde_plane_rot_atomic_update(struct drm_plane *plane,
1968 struct drm_plane_state *old_state)
1969{
1970 struct drm_plane_state *state;
1971 struct sde_plane_state *pstate;
1972 struct sde_plane_rot_state *rstate;
1973
1974 if (!plane || !plane->state) {
1975 SDE_ERROR("invalid plane/state\n");
1976 return;
1977 }
1978
1979 state = plane->state;
1980 pstate = to_sde_plane_state(state);
1981 rstate = &pstate->rot;
1982
1983 SDE_DEBUG("plane%d.%d sbuf:%d rot:%d crtc:%d\n", plane->base.id,
1984 rstate->sequence_id,
1985 !!rstate->out_sbuf, !!rstate->rot_hw,
1986 sde_plane_crtc_enabled(plane->state));
1987
1988 if (!sde_plane_crtc_enabled(state))
1989 return;
1990
1991 if (!rstate->out_sbuf || !rstate->rot_hw)
1992 return;
1993
1994 sde_plane_rot_submit_command(plane, state, SDE_HW_ROT_CMD_COMMIT);
1995}
1996
1997/**
1998 * sde_plane_rot_destroy_state - destroy state for rotator stage
1999 * @plane: Pointer to drm plane
2000 * @state: Pointer to state to be destroyed
2001 * return: none
2002 */
2003static void sde_plane_rot_destroy_state(struct drm_plane *plane,
2004 struct drm_plane_state *state)
2005{
2006 struct sde_plane_state *pstate = to_sde_plane_state(state);
2007 struct sde_plane_rot_state *rstate = &pstate->rot;
2008
2009 SDE_DEBUG("plane%d.%d sbuf:%d rot:%d crtc:%d\n", plane->base.id,
2010 rstate->sequence_id,
2011 !!rstate->out_sbuf, !!rstate->rot_hw,
2012 sde_plane_crtc_enabled(state));
2013
2014 if (rstate->rot_hw) {
2015 sde_hw_blk_detach(&rstate->rot_hw->base, SDE_TAG_ROT_IN_FB,
2016 rstate->in_fb);
2017 rstate->in_fb = NULL;
2018 sde_hw_blk_detach(&rstate->rot_hw->base, SDE_TAG_ROT_PLANE,
2019 plane);
2020 sde_hw_rot_put(rstate->rot_hw);
2021 rstate->rot_hw = NULL;
2022 }
2023}
2024
2025/**
2026 * sde_plane_rot_duplicate_state - duplicate state for rotator stage
2027 * @plane: Pointer to drm plane
2028 * @new_state: Pointer to duplicated state
2029 * return: 0 if success; error code otherwise
2030 */
2031static int sde_plane_rot_duplicate_state(struct drm_plane *plane,
2032 struct drm_plane_state *new_state)
2033{
2034 struct sde_plane_state *pstate = to_sde_plane_state(new_state);
2035 struct sde_plane_rot_state *rstate = &pstate->rot;
2036
2037 rstate->sequence_id++;
2038
2039 SDE_DEBUG("plane%d.%d sbuf:%d rot:%d\n", plane->base.id,
2040 rstate->sequence_id,
2041 !!rstate->out_sbuf, !!rstate->rot_hw);
2042
2043 if (rstate->rot_hw) {
2044 sde_hw_blk_attach(&rstate->rot_hw->base, SDE_TAG_ROT_IN_FB,
2045 rstate->in_fb);
2046 sde_hw_blk_attach(&rstate->rot_hw->base, SDE_TAG_ROT_PLANE,
2047 plane);
2048 sde_hw_rot_get(rstate->rot_hw);
2049 }
2050
2051 rstate->out_fb = NULL;
2052 rstate->out_fbo = NULL;
2053
2054 return 0;
2055}
2056
2057/**
2058 * sde_plane_rot_install_caps - install plane rotator capabilities
2059 * @plane: Pointer to drm plane
2060 * return: none
2061 */
2062static void sde_plane_rot_install_caps(struct drm_plane *plane)
2063{
2064 struct sde_plane *psde = to_sde_plane(plane);
2065 const struct sde_format_extended *format_list;
2066 struct sde_kms_info *info;
2067 struct sde_hw_rot *rot_hw;
2068 const char *downscale_caps;
2069
2070 if (!psde->catalog || !(psde->features & BIT(SDE_SSPP_SBUF)) ||
2071 !psde->catalog->rot_count)
2072 return;
2073
2074 if (psde->blob_rot_caps)
2075 return;
2076
2077 info = kzalloc(sizeof(struct sde_kms_info), GFP_KERNEL);
2078 if (!info)
2079 return;
2080
2081 rot_hw = sde_hw_rot_get(NULL);
2082 if (!rot_hw || !rot_hw->ops.get_format_caps ||
2083 !rot_hw->ops.get_downscale_caps) {
2084 SDE_ERROR("invalid rotator hw\n");
2085 goto error_rot;
2086 }
2087
2088 sde_kms_info_reset(info);
2089
2090 format_list = rot_hw->ops.get_format_caps(rot_hw);
2091 if (format_list) {
2092 sde_kms_info_start(info, "pixel_formats");
2093 while (format_list->fourcc_format) {
2094 sde_kms_info_append_format(info,
2095 format_list->fourcc_format,
2096 format_list->modifier);
2097 ++format_list;
2098 }
2099 sde_kms_info_stop(info);
2100 }
2101
2102 downscale_caps = rot_hw->ops.get_downscale_caps(rot_hw);
2103 if (downscale_caps) {
2104 sde_kms_info_start(info, "downscale_ratios");
2105 sde_kms_info_append(info, downscale_caps);
2106 sde_kms_info_stop(info);
2107 }
2108
2109 if (rot_hw->ops.get_cache_size)
2110 sde_kms_info_add_keyint(info, "cache_size",
2111 rot_hw->ops.get_cache_size(rot_hw));
2112
2113 msm_property_set_blob(&psde->property_info, &psde->blob_rot_caps,
2114 info->data, info->len, PLANE_PROP_ROT_CAPS_V1);
2115
2116 sde_hw_rot_put(rot_hw);
2117error_rot:
2118 kfree(info);
2119}
2120
2121/**
2122 * sde_plane_rot_install_properties - install plane rotator properties
2123 * @plane: Pointer to drm plane
2124 * @catalog: Pointer to mdss configuration
2125 * return: none
2126 */
2127static void sde_plane_rot_install_properties(struct drm_plane *plane,
2128 struct sde_mdss_cfg *catalog)
2129{
2130 struct sde_plane *psde = to_sde_plane(plane);
2131 unsigned long supported_rotations = DRM_REFLECT_X | DRM_REFLECT_Y;
2132
2133 if (!plane || !psde) {
2134 SDE_ERROR("invalid plane\n");
2135 return;
2136 } else if (!catalog) {
2137 SDE_ERROR("invalid catalog\n");
2138 return;
2139 }
2140
2141 if ((psde->features & BIT(SDE_SSPP_SBUF)) && catalog->rot_count)
2142 supported_rotations |= DRM_ROTATE_0 | DRM_ROTATE_90 |
2143 DRM_ROTATE_180 | DRM_ROTATE_270;
2144
2145 msm_property_install_rotation(&psde->property_info,
2146 supported_rotations, PLANE_PROP_ROTATION);
2147
2148 if (!(psde->features & BIT(SDE_SSPP_SBUF)) || !catalog->rot_count)
2149 return;
2150
2151 msm_property_install_range(&psde->property_info, "rot_dst_x",
2152 0, 0, U64_MAX, 0, PLANE_PROP_ROT_DST_X);
2153 msm_property_install_range(&psde->property_info, "rot_dst_y",
2154 0, 0, U64_MAX, 0, PLANE_PROP_ROT_DST_Y);
2155 msm_property_install_range(&psde->property_info, "rot_dst_w",
2156 0, 0, U64_MAX, 0, PLANE_PROP_ROT_DST_W);
2157 msm_property_install_range(&psde->property_info, "rot_dst_h",
2158 0, 0, U64_MAX, 0, PLANE_PROP_ROT_DST_H);
2159 msm_property_install_blob(&psde->property_info, "rot_caps_v1",
2160 DRM_MODE_PROP_IMMUTABLE, PLANE_PROP_ROT_CAPS_V1);
2161}
2162
2163static int sde_plane_sspp_atomic_update(struct drm_plane *plane,
Dhaval Patel47302cf2016-08-18 15:04:28 -07002164 struct drm_plane_state *state)
Clarence Ipcb410d42016-06-26 22:52:33 -04002165{
Clarence Ipc47a0692016-10-11 10:54:17 -04002166 uint32_t nplanes, src_flags;
Clarence Ipcb410d42016-06-26 22:52:33 -04002167 struct sde_plane *psde;
2168 struct sde_plane_state *pstate;
Alan Kwong4dd64c82017-02-04 18:41:51 -08002169 struct sde_plane_rot_state *rstate;
Lloyd Atkinson9a673492016-07-05 11:41:57 -04002170 const struct sde_format *fmt;
Dhaval Patel47302cf2016-08-18 15:04:28 -07002171 struct drm_crtc *crtc;
2172 struct drm_framebuffer *fb;
2173 struct sde_rect src, dst;
2174 bool q16_data = true;
Clarence Ip282dad62016-09-27 17:07:35 -04002175 int idx;
Clarence Ipcb410d42016-06-26 22:52:33 -04002176
Clarence Ip13a8cf42016-09-29 17:27:47 -04002177 if (!plane) {
Clarence Ip282dad62016-09-27 17:07:35 -04002178 SDE_ERROR("invalid plane\n");
2179 return -EINVAL;
2180 } else if (!plane->state) {
2181 SDE_ERROR("invalid plane state\n");
Clarence Ipcb410d42016-06-26 22:52:33 -04002182 return -EINVAL;
2183 }
2184
2185 psde = to_sde_plane(plane);
2186 pstate = to_sde_plane_state(plane->state);
Alan Kwong4dd64c82017-02-04 18:41:51 -08002187 rstate = &pstate->rot;
Clarence Ipcb410d42016-06-26 22:52:33 -04002188
Dhaval Patel47302cf2016-08-18 15:04:28 -07002189 crtc = state->crtc;
Alan Kwong4dd64c82017-02-04 18:41:51 -08002190 fb = rstate->out_fb;
Dhaval Patel47302cf2016-08-18 15:04:28 -07002191 if (!crtc || !fb) {
Clarence Ip13a8cf42016-09-29 17:27:47 -04002192 SDE_ERROR_PLANE(psde, "invalid crtc %d or fb %d\n",
2193 crtc != 0, fb != 0);
Dhaval Patel47302cf2016-08-18 15:04:28 -07002194 return -EINVAL;
2195 }
Lloyd Atkinson9a673492016-07-05 11:41:57 -04002196 fmt = to_sde_format(msm_framebuffer_format(fb));
Lloyd Atkinsonfa2489c2016-05-25 15:16:03 -04002197 nplanes = fmt->num_planes;
Clarence Ipcb410d42016-06-26 22:52:33 -04002198
Alan Kwong4dd64c82017-02-04 18:41:51 -08002199 SDE_DEBUG(
2200 "plane%d.%d sspp:%dx%d/%c%c%c%c/%llx/%dx%d+%d+%d/%x crtc:%dx%d+%d+%d\n",
2201 plane->base.id, rstate->sequence_id,
2202 rstate->out_fb_width, rstate->out_fb_height,
2203 rstate->out_fb_pixel_format >> 0,
2204 rstate->out_fb_pixel_format >> 8,
2205 rstate->out_fb_pixel_format >> 16,
2206 rstate->out_fb_pixel_format >> 24,
2207 rstate->out_fb_modifier[0],
2208 rstate->out_src_w >> 16, rstate->out_src_h >> 16,
2209 rstate->out_src_x >> 16, rstate->out_src_y >> 16,
2210 rstate->out_rotation,
2211 state->crtc_w, state->crtc_h,
2212 state->crtc_x, state->crtc_y);
2213
Clarence Ip282dad62016-09-27 17:07:35 -04002214 /* determine what needs to be refreshed */
2215 while ((idx = msm_property_pop_dirty(&psde->property_info)) >= 0) {
2216 switch (idx) {
Clarence Ipb43d4592016-09-08 14:21:35 -04002217 case PLANE_PROP_SCALER_V1:
abeykun48f407a2016-08-25 12:06:44 -04002218 case PLANE_PROP_SCALER_V2:
Clarence Ipdedbba92016-09-27 17:43:10 -04002219 case PLANE_PROP_H_DECIMATE:
2220 case PLANE_PROP_V_DECIMATE:
2221 case PLANE_PROP_SRC_CONFIG:
2222 case PLANE_PROP_ZPOS:
Veera Sundaram Sankaran02dd6ac2016-12-22 15:08:29 -08002223 case PLANE_PROP_EXCL_RECT_V1:
Clarence Ip282dad62016-09-27 17:07:35 -04002224 pstate->dirty |= SDE_PLANE_DIRTY_RECTS;
2225 break;
Clarence Ip5fc00c52016-09-23 15:03:34 -04002226 case PLANE_PROP_CSC_V1:
Clarence Ip282dad62016-09-27 17:07:35 -04002227 pstate->dirty |= SDE_PLANE_DIRTY_FORMAT;
2228 break;
2229 case PLANE_PROP_COLOR_FILL:
2230 /* potentially need to refresh everything */
2231 pstate->dirty = SDE_PLANE_DIRTY_ALL;
2232 break;
2233 case PLANE_PROP_ROTATION:
2234 pstate->dirty |= SDE_PLANE_DIRTY_FORMAT;
2235 break;
Clarence Ip282dad62016-09-27 17:07:35 -04002236 case PLANE_PROP_INFO:
2237 case PLANE_PROP_ALPHA:
2238 case PLANE_PROP_INPUT_FENCE:
2239 case PLANE_PROP_BLEND_OP:
2240 /* no special action required */
2241 break;
Alan Kwong4dd64c82017-02-04 18:41:51 -08002242 case PLANE_PROP_ROT_DST_X:
2243 case PLANE_PROP_ROT_DST_Y:
2244 case PLANE_PROP_ROT_DST_W:
2245 case PLANE_PROP_ROT_DST_H:
2246 /* handled by rotator atomic update */
2247 break;
Clarence Ip282dad62016-09-27 17:07:35 -04002248 default:
2249 /* unknown property, refresh everything */
2250 pstate->dirty |= SDE_PLANE_DIRTY_ALL;
2251 SDE_ERROR("executing full mode set, prp_idx %d\n", idx);
2252 break;
2253 }
Clarence Ipcb410d42016-06-26 22:52:33 -04002254 }
2255
Clarence Ip282dad62016-09-27 17:07:35 -04002256 if (pstate->dirty & SDE_PLANE_DIRTY_RECTS)
2257 memset(&(psde->pipe_cfg), 0, sizeof(struct sde_hw_pipe_cfg));
Clarence Ipcb410d42016-06-26 22:52:33 -04002258
2259 _sde_plane_set_scanout(plane, pstate, &psde->pipe_cfg, fb);
2260
Clarence Ip282dad62016-09-27 17:07:35 -04002261 /* early out if nothing dirty */
2262 if (!pstate->dirty)
2263 return 0;
2264 pstate->pending = true;
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04002265
Dhaval Patel4d424602017-02-18 19:40:14 -08002266 psde->is_rt_pipe = (sde_crtc_get_client_type(crtc) != NRT_CLIENT);
Clarence Ip282dad62016-09-27 17:07:35 -04002267 _sde_plane_set_qos_ctrl(plane, false, SDE_PLANE_QOS_PANIC_CTRL);
2268
2269 /* update roi config */
2270 if (pstate->dirty & SDE_PLANE_DIRTY_RECTS) {
Alan Kwong4dd64c82017-02-04 18:41:51 -08002271 POPULATE_RECT(&src, rstate->out_src_x, rstate->out_src_y,
2272 rstate->out_src_w, rstate->out_src_h, q16_data);
Clarence Ip282dad62016-09-27 17:07:35 -04002273 POPULATE_RECT(&dst, state->crtc_x, state->crtc_y,
2274 state->crtc_w, state->crtc_h, !q16_data);
2275
Clarence Ip13a8cf42016-09-29 17:27:47 -04002276 SDE_DEBUG_PLANE(psde,
Alan Kwong4dd64c82017-02-04 18:41:51 -08002277 "FB[%u] %u,%u,%ux%u->crtc%u %d,%d,%ux%u, %c%c%c%c ubwc %d\n",
Clarence Ip282dad62016-09-27 17:07:35 -04002278 fb->base.id, src.x, src.y, src.w, src.h,
2279 crtc->base.id, dst.x, dst.y, dst.w, dst.h,
Alan Kwong4dd64c82017-02-04 18:41:51 -08002280 fmt->base.pixel_format >> 0,
2281 fmt->base.pixel_format >> 8,
2282 fmt->base.pixel_format >> 16,
2283 fmt->base.pixel_format >> 24,
Clarence Ip282dad62016-09-27 17:07:35 -04002284 SDE_FORMAT_IS_UBWC(fmt));
2285
2286 if (sde_plane_get_property(pstate, PLANE_PROP_SRC_CONFIG) &
2287 BIT(SDE_DRM_DEINTERLACE)) {
Clarence Ip13a8cf42016-09-29 17:27:47 -04002288 SDE_DEBUG_PLANE(psde, "deinterlace\n");
Clarence Ip282dad62016-09-27 17:07:35 -04002289 for (idx = 0; idx < SDE_MAX_PLANES; ++idx)
2290 psde->pipe_cfg.layout.plane_pitch[idx] <<= 1;
2291 src.h /= 2;
2292 src.y = DIV_ROUND_UP(src.y, 2);
2293 src.y &= ~0x1;
2294 }
2295
2296 psde->pipe_cfg.src_rect = src;
2297 psde->pipe_cfg.dst_rect = dst;
2298
2299 /* check for color fill */
2300 psde->color_fill = (uint32_t)sde_plane_get_property(pstate,
2301 PLANE_PROP_COLOR_FILL);
2302 if (psde->color_fill & SDE_PLANE_COLOR_FILL_FLAG) {
2303 /* skip remaining processing on color fill */
2304 pstate->dirty = 0x0;
2305 } else if (psde->pipe_hw->ops.setup_rects) {
Clarence Ip282dad62016-09-27 17:07:35 -04002306 psde->pipe_hw->ops.setup_rects(psde->pipe_hw,
Jeykumar Sankaran9fcfa482017-02-16 16:03:14 -08002307 &psde->pipe_cfg,
2308 pstate->multirect_index);
Clarence Ip282dad62016-09-27 17:07:35 -04002309 }
Veera Sundaram Sankaran02dd6ac2016-12-22 15:08:29 -08002310
Jeykumar Sankaran9fcfa482017-02-16 16:03:14 -08002311 _sde_plane_setup_scaler(psde, fmt, pstate);
2312 if (psde->pipe_hw->ops.setup_pe)
2313 psde->pipe_hw->ops.setup_pe(psde->pipe_hw,
2314 &psde->pixel_ext);
2315
2316 if (psde->pipe_hw->ops.setup_scaler)
2317 psde->pipe_hw->ops.setup_scaler(psde->pipe_hw,
2318 &psde->pipe_cfg, &psde->pixel_ext,
2319 psde->scaler3_cfg);
2320
Veera Sundaram Sankaran02dd6ac2016-12-22 15:08:29 -08002321 /* update excl rect */
2322 if (psde->pipe_hw->ops.setup_excl_rect)
2323 psde->pipe_hw->ops.setup_excl_rect(psde->pipe_hw,
Jeykumar Sankaran2e655032017-02-04 14:05:45 -08002324 &pstate->excl_rect,
2325 pstate->multirect_index);
2326
2327 if (psde->pipe_hw->ops.setup_multirect)
2328 psde->pipe_hw->ops.setup_multirect(
2329 psde->pipe_hw,
2330 pstate->multirect_index,
2331 pstate->multirect_mode);
Dhaval Patel48c76022016-09-01 17:51:23 -07002332 }
2333
Clarence Ip282dad62016-09-27 17:07:35 -04002334 if ((pstate->dirty & SDE_PLANE_DIRTY_FORMAT) &&
2335 psde->pipe_hw->ops.setup_format) {
2336 src_flags = 0x0;
Alan Kwong4dd64c82017-02-04 18:41:51 -08002337 SDE_DEBUG_PLANE(psde, "rotation 0x%X\n", rstate->out_rotation);
2338 if (rstate->out_rotation & DRM_REFLECT_X)
Clarence Ip282dad62016-09-27 17:07:35 -04002339 src_flags |= SDE_SSPP_FLIP_LR;
Alan Kwong4dd64c82017-02-04 18:41:51 -08002340 if (rstate->out_rotation & DRM_REFLECT_Y)
Clarence Ip282dad62016-09-27 17:07:35 -04002341 src_flags |= SDE_SSPP_FLIP_UD;
2342
2343 /* update format */
Jeykumar Sankaran2e655032017-02-04 14:05:45 -08002344 psde->pipe_hw->ops.setup_format(psde->pipe_hw, fmt, src_flags,
2345 pstate->multirect_index);
Clarence Ip282dad62016-09-27 17:07:35 -04002346
Alan Kwong4dd64c82017-02-04 18:41:51 -08002347 if (psde->pipe_hw->ops.setup_sys_cache) {
2348 if (rstate->out_sbuf) {
2349 if (rstate->nplane < 2)
2350 pstate->sc_cfg.op_mode =
2351 SDE_PIPE_SC_OP_MODE_INLINE_SINGLE;
2352 else if (rstate->out_xpos == 0)
2353 pstate->sc_cfg.op_mode =
2354 SDE_PIPE_SC_OP_MODE_INLINE_LEFT;
2355 else
2356 pstate->sc_cfg.op_mode =
2357 SDE_PIPE_SC_OP_MODE_INLINE_RIGHT;
2358
2359 pstate->sc_cfg.rd_en = true;
2360 pstate->sc_cfg.rd_scid =
2361 rstate->rot_hw->caps->scid;
2362 pstate->sc_cfg.rd_noallocate = true;
2363 pstate->sc_cfg.rd_op_type =
2364 SDE_PIPE_SC_RD_OP_TYPE_CACHEABLE;
2365 } else {
2366 pstate->sc_cfg.op_mode =
2367 SDE_PIPE_SC_OP_MODE_OFFLINE;
2368 pstate->sc_cfg.rd_en = false;
2369 pstate->sc_cfg.rd_scid = 0;
2370 pstate->sc_cfg.rd_noallocate = false;
2371 pstate->sc_cfg.rd_op_type =
2372 SDE_PIPE_SC_RD_OP_TYPE_CACHEABLE;
2373 }
2374
2375 psde->pipe_hw->ops.setup_sys_cache(
2376 psde->pipe_hw, &pstate->sc_cfg);
2377 }
2378
Clarence Ip282dad62016-09-27 17:07:35 -04002379 /* update csc */
2380 if (SDE_FORMAT_IS_YUV(fmt))
Clarence Ip5fc00c52016-09-23 15:03:34 -04002381 _sde_plane_setup_csc(psde);
Clarence Ip282dad62016-09-27 17:07:35 -04002382 else
2383 psde->csc_ptr = 0;
2384 }
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04002385
Benet Clarkeb1b4462016-06-27 14:43:06 -07002386 sde_color_process_plane_setup(plane);
2387
Clarence Ipe78efb72016-06-24 18:35:21 -04002388 /* update sharpening */
Clarence Ip282dad62016-09-27 17:07:35 -04002389 if ((pstate->dirty & SDE_PLANE_DIRTY_SHARPEN) &&
2390 psde->pipe_hw->ops.setup_sharpening) {
2391 psde->sharp_cfg.strength = SHARP_STRENGTH_DEFAULT;
2392 psde->sharp_cfg.edge_thr = SHARP_EDGE_THR_DEFAULT;
2393 psde->sharp_cfg.smooth_thr = SHARP_SMOOTH_THR_DEFAULT;
2394 psde->sharp_cfg.noise_thr = SHARP_NOISE_THR_DEFAULT;
Clarence Ipe78efb72016-06-24 18:35:21 -04002395
Clarence Ipe78efb72016-06-24 18:35:21 -04002396 psde->pipe_hw->ops.setup_sharpening(psde->pipe_hw,
Clarence Ip282dad62016-09-27 17:07:35 -04002397 &psde->sharp_cfg);
2398 }
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04002399
Alan Kwong1a00e4d2016-07-18 09:42:30 -04002400 _sde_plane_set_qos_lut(plane, fb);
2401 _sde_plane_set_danger_lut(plane, fb);
2402
Alan Kwong5d324e42016-07-28 22:56:18 -04002403 if (plane->type != DRM_PLANE_TYPE_CURSOR) {
Alan Kwong1a00e4d2016-07-18 09:42:30 -04002404 _sde_plane_set_qos_ctrl(plane, true, SDE_PLANE_QOS_PANIC_CTRL);
Alan Kwong5d324e42016-07-28 22:56:18 -04002405 _sde_plane_set_ot_limit(plane, crtc);
2406 }
Alan Kwong1a00e4d2016-07-18 09:42:30 -04002407
Clarence Ip282dad62016-09-27 17:07:35 -04002408 /* clear dirty */
2409 pstate->dirty = 0x0;
2410
Jeykumar Sankaran2e655032017-02-04 14:05:45 -08002411 /* clear multirect mode*/
2412 pstate->multirect_index = SDE_SSPP_RECT_SOLO;
2413 pstate->multirect_mode = SDE_SSPP_MULTIRECT_NONE;
2414 return 0;
2415}
2416
2417int sde_plane_validate_multirect_v2(struct sde_multirect_plane_states *plane)
2418{
2419 struct sde_plane_state *pstate[R_MAX];
2420 const struct drm_plane_state *drm_state[R_MAX];
2421 struct sde_rect src[R_MAX], dst[R_MAX];
2422 struct sde_plane *sde_plane[R_MAX];
2423 const struct sde_format *fmt[R_MAX];
2424 bool q16_data = true;
2425 int i, max_sspp_linewidth;
2426 int buffer_lines = TX_MODE_BUFFER_LINE_THRES;
2427
2428 for (i = 0; i < R_MAX; i++) {
2429 const struct msm_format *msm_fmt;
2430
2431 drm_state[i] = i ? plane->r1 : plane->r0;
2432 pstate[i] = to_sde_plane_state(drm_state[i]);
2433 sde_plane[i] = to_sde_plane(drm_state[i]->plane);
2434
2435 if (pstate[i] == NULL) {
2436 SDE_ERROR("SDE plane state of plane id %d is NULL\n",
2437 drm_state[i]->plane->base.id);
2438 return -EINVAL;
2439 }
2440
2441 POPULATE_RECT(&src[i], drm_state[i]->src_x, drm_state[i]->src_y,
2442 drm_state[i]->src_w, drm_state[i]->src_h, q16_data);
2443 POPULATE_RECT(&dst[i], drm_state[i]->crtc_x,
2444 drm_state[i]->crtc_y, drm_state[i]->crtc_w,
2445 drm_state[i]->crtc_h, !q16_data);
2446
2447 if (src[i].w != dst[i].w || src[i].h != dst[i].h) {
2448 SDE_ERROR_PLANE(sde_plane[i],
2449 "scaling is not supported in multirect mode\n");
2450 return -EINVAL;
2451 }
2452
2453 msm_fmt = msm_framebuffer_format(drm_state[i]->fb);
2454 fmt[i] = to_sde_format(msm_fmt);
2455 if (SDE_FORMAT_IS_YUV(fmt[i])) {
2456 SDE_ERROR_PLANE(sde_plane[i],
2457 "Unsupported format for multirect mode\n");
2458 return -EINVAL;
2459 }
2460 }
2461
2462 max_sspp_linewidth = sde_plane[R0]->pipe_sblk->maxlinewidth;
2463
2464 /* Validate RECT's and set the mode */
2465
2466 /* Prefer PARALLEL FETCH Mode over TIME_MX Mode */
2467 if (src[R0].w <= max_sspp_linewidth/2 &&
2468 src[R1].w <= max_sspp_linewidth/2) {
2469 if (dst[R0].x <= dst[R1].x) {
2470 pstate[R0]->multirect_index = SDE_SSPP_RECT_0;
2471 pstate[R1]->multirect_index = SDE_SSPP_RECT_1;
2472 } else {
2473 pstate[R0]->multirect_index = SDE_SSPP_RECT_1;
2474 pstate[R1]->multirect_index = SDE_SSPP_RECT_0;
2475 }
2476
2477 pstate[R0]->multirect_mode = SDE_SSPP_MULTIRECT_PARALLEL;
2478 pstate[R1]->multirect_mode = SDE_SSPP_MULTIRECT_PARALLEL;
2479 goto done;
2480 }
2481
2482 /* TIME_MX Mode */
2483 if (SDE_FORMAT_IS_UBWC(fmt[R0]))
2484 buffer_lines = 2 * fmt[R0]->tile_height;
2485
2486 if (dst[R1].y >= dst[R0].y + dst[R0].h + buffer_lines) {
2487 pstate[R0]->multirect_index = SDE_SSPP_RECT_0;
2488 pstate[R1]->multirect_index = SDE_SSPP_RECT_1;
2489 } else if (dst[R0].y >= dst[R1].y + dst[R1].h + buffer_lines) {
2490 pstate[R0]->multirect_index = SDE_SSPP_RECT_1;
2491 pstate[R1]->multirect_index = SDE_SSPP_RECT_0;
2492 } else {
2493 SDE_ERROR(
2494 "No multirect mode possible for the planes (%d - %d)\n",
2495 drm_state[R0]->plane->base.id,
2496 drm_state[R1]->plane->base.id);
2497 return -EINVAL;
2498 }
2499
2500 pstate[R0]->multirect_mode = SDE_SSPP_MULTIRECT_TIME_MX;
2501 pstate[R1]->multirect_mode = SDE_SSPP_MULTIRECT_TIME_MX;
2502done:
Clarence Ip5e2a9222016-06-26 22:38:24 -04002503 return 0;
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04002504}
2505
Alan Kwong4dd64c82017-02-04 18:41:51 -08002506/**
2507 * sde_plane_get_ctl_flush - get control flush for the given plane
2508 * @plane: Pointer to drm plane structure
2509 * @ctl: Pointer to hardware control driver
2510 * @flush: Pointer to flush control word
2511 */
2512void sde_plane_get_ctl_flush(struct drm_plane *plane, struct sde_hw_ctl *ctl,
2513 u32 *flush)
2514{
2515 struct sde_plane_state *pstate;
2516 struct sde_plane_rot_state *rstate;
2517 u32 bitmask;
2518
2519 if (!plane || !flush) {
2520 SDE_ERROR("invalid parameters\n");
2521 return;
2522 }
2523
2524 pstate = to_sde_plane_state(plane->state);
2525 rstate = &pstate->rot;
2526
2527 bitmask = ctl->ops.get_bitmask_sspp(ctl, sde_plane_pipe(plane));
2528
2529 if (sde_plane_is_sbuf_mode(plane, NULL) && rstate->rot_hw &&
2530 ctl->ops.get_bitmask_rot)
2531 ctl->ops.get_bitmask_rot(ctl, &bitmask, rstate->rot_hw->idx);
2532
2533 *flush = bitmask;
2534}
2535
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04002536static int sde_plane_prepare_fb(struct drm_plane *plane,
Dhaval Patel04c7e8e2016-09-26 20:14:31 -07002537 struct drm_plane_state *new_state)
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04002538{
2539 struct drm_framebuffer *fb = new_state->fb;
2540 struct sde_plane *psde = to_sde_plane(plane);
Alan Kwong4dd64c82017-02-04 18:41:51 -08002541 struct sde_plane_rot_state *new_rstate;
2542 int ret;
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04002543
2544 if (!new_state->fb)
2545 return 0;
2546
Clarence Ip13a8cf42016-09-29 17:27:47 -04002547 SDE_DEBUG_PLANE(psde, "FB[%u]\n", fb->base.id);
Alan Kwong4dd64c82017-02-04 18:41:51 -08002548
2549 ret = sde_plane_rot_prepare_fb(plane, new_state);
2550 if (ret) {
2551 SDE_ERROR("failed to prepare rot framebuffer\n");
2552 return ret;
2553 }
2554
2555 new_rstate = &to_sde_plane_state(new_state)->rot;
2556
2557 ret = msm_framebuffer_prepare(new_rstate->out_fb, new_rstate->mmu_id);
2558 if (ret) {
2559 SDE_ERROR("failed to prepare framebuffer\n");
2560 return ret;
2561 }
2562
2563 return 0;
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04002564}
2565
2566static void sde_plane_cleanup_fb(struct drm_plane *plane,
Dhaval Patel04c7e8e2016-09-26 20:14:31 -07002567 struct drm_plane_state *old_state)
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04002568{
Alan Kwong4dd64c82017-02-04 18:41:51 -08002569 struct sde_plane *psde = to_sde_plane(plane);
2570 struct sde_plane_rot_state *old_rstate;
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04002571
Alan Kwong4dd64c82017-02-04 18:41:51 -08002572 if (!old_state->fb)
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04002573 return;
2574
Alan Kwong4dd64c82017-02-04 18:41:51 -08002575 SDE_DEBUG_PLANE(psde, "FB[%u]\n", old_state->fb->base.id);
2576
2577 old_rstate = &to_sde_plane_state(old_state)->rot;
2578
2579 msm_framebuffer_cleanup(old_rstate->out_fb, old_rstate->mmu_id);
2580
2581 sde_plane_rot_cleanup_fb(plane, old_state);
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04002582}
2583
Alan Kwong4dd64c82017-02-04 18:41:51 -08002584static void _sde_plane_sspp_atomic_check_mode_changed(struct sde_plane *psde,
Lloyd Atkinsonfa2489c2016-05-25 15:16:03 -04002585 struct drm_plane_state *state,
2586 struct drm_plane_state *old_state)
2587{
2588 struct sde_plane_state *pstate = to_sde_plane_state(state);
Veera Sundaram Sankaran02dd6ac2016-12-22 15:08:29 -08002589 struct sde_plane_state *old_pstate = to_sde_plane_state(old_state);
Alan Kwong4dd64c82017-02-04 18:41:51 -08002590 struct sde_plane_rot_state *rstate = &pstate->rot;
2591 struct sde_plane_rot_state *old_rstate = &old_pstate->rot;
2592 struct drm_framebuffer *fb, *old_fb;
Lloyd Atkinsonfa2489c2016-05-25 15:16:03 -04002593
Dhaval Patel47302cf2016-08-18 15:04:28 -07002594 /* no need to check it again */
Clarence Ip282dad62016-09-27 17:07:35 -04002595 if (pstate->dirty == SDE_PLANE_DIRTY_ALL)
Dhaval Patel47302cf2016-08-18 15:04:28 -07002596 return;
2597
Clarence Ip282dad62016-09-27 17:07:35 -04002598 if (!sde_plane_enabled(state) || !sde_plane_enabled(old_state)
2599 || psde->is_error) {
Clarence Ip13a8cf42016-09-29 17:27:47 -04002600 SDE_DEBUG_PLANE(psde,
2601 "enabling/disabling full modeset required\n");
Clarence Ip282dad62016-09-27 17:07:35 -04002602 pstate->dirty |= SDE_PLANE_DIRTY_ALL;
Lloyd Atkinsonfa2489c2016-05-25 15:16:03 -04002603 } else if (to_sde_plane_state(old_state)->pending) {
Clarence Ip13a8cf42016-09-29 17:27:47 -04002604 SDE_DEBUG_PLANE(psde, "still pending\n");
Clarence Ip282dad62016-09-27 17:07:35 -04002605 pstate->dirty |= SDE_PLANE_DIRTY_ALL;
Alan Kwong4dd64c82017-02-04 18:41:51 -08002606 } else if (rstate->out_src_w != old_rstate->out_src_w ||
2607 rstate->out_src_h != old_rstate->out_src_h ||
2608 rstate->out_src_x != old_rstate->out_src_x ||
2609 rstate->out_src_y != old_rstate->out_src_y) {
Clarence Ip13a8cf42016-09-29 17:27:47 -04002610 SDE_DEBUG_PLANE(psde, "src rect updated\n");
Clarence Ip282dad62016-09-27 17:07:35 -04002611 pstate->dirty |= SDE_PLANE_DIRTY_RECTS;
Dhaval Patel47302cf2016-08-18 15:04:28 -07002612 } else if (state->crtc_w != old_state->crtc_w ||
2613 state->crtc_h != old_state->crtc_h ||
2614 state->crtc_x != old_state->crtc_x ||
2615 state->crtc_y != old_state->crtc_y) {
Clarence Ip13a8cf42016-09-29 17:27:47 -04002616 SDE_DEBUG_PLANE(psde, "crtc rect updated\n");
Clarence Ip282dad62016-09-27 17:07:35 -04002617 pstate->dirty |= SDE_PLANE_DIRTY_RECTS;
Veera Sundaram Sankaran02dd6ac2016-12-22 15:08:29 -08002618 } else if (pstate->excl_rect.w != old_pstate->excl_rect.w ||
2619 pstate->excl_rect.h != old_pstate->excl_rect.h ||
2620 pstate->excl_rect.x != old_pstate->excl_rect.x ||
2621 pstate->excl_rect.y != old_pstate->excl_rect.y) {
2622 SDE_DEBUG_PLANE(psde, "excl rect updated\n");
2623 pstate->dirty |= SDE_PLANE_DIRTY_RECTS;
Jeykumar Sankaran2e655032017-02-04 14:05:45 -08002624 } else if (pstate->multirect_index != old_pstate->multirect_index ||
2625 pstate->multirect_mode != old_pstate->multirect_mode) {
2626 SDE_DEBUG_PLANE(psde, "multirect config updated\n");
2627 pstate->dirty |= SDE_PLANE_DIRTY_RECTS;
Clarence Ip282dad62016-09-27 17:07:35 -04002628 }
2629
Alan Kwong4dd64c82017-02-04 18:41:51 -08002630 fb = rstate->out_fb;
2631 old_fb = old_rstate->out_fb;
2632
2633 if (!fb || !old_fb) {
Clarence Ip13a8cf42016-09-29 17:27:47 -04002634 SDE_DEBUG_PLANE(psde, "can't compare fb handles\n");
Alan Kwong4dd64c82017-02-04 18:41:51 -08002635 } else if (fb->pixel_format != old_fb->pixel_format) {
Clarence Ip13a8cf42016-09-29 17:27:47 -04002636 SDE_DEBUG_PLANE(psde, "format change\n");
Clarence Ip282dad62016-09-27 17:07:35 -04002637 pstate->dirty |= SDE_PLANE_DIRTY_FORMAT | SDE_PLANE_DIRTY_RECTS;
Dhaval Patel47302cf2016-08-18 15:04:28 -07002638 } else {
Alan Kwong4dd64c82017-02-04 18:41:51 -08002639 uint64_t *new_mods = fb->modifier;
2640 uint64_t *old_mods = old_fb->modifier;
2641 uint32_t *new_pitches = fb->pitches;
2642 uint32_t *old_pitches = old_fb->pitches;
2643 uint32_t *new_offset = fb->offsets;
2644 uint32_t *old_offset = old_fb->offsets;
Lloyd Atkinsonfa2489c2016-05-25 15:16:03 -04002645 int i;
2646
Alan Kwong4dd64c82017-02-04 18:41:51 -08002647 for (i = 0; i < ARRAY_SIZE(fb->modifier); i++) {
Lloyd Atkinsonfa2489c2016-05-25 15:16:03 -04002648 if (new_mods[i] != old_mods[i]) {
Clarence Ip13a8cf42016-09-29 17:27:47 -04002649 SDE_DEBUG_PLANE(psde,
2650 "format modifiers change\"\
Dhaval Patel47302cf2016-08-18 15:04:28 -07002651 plane:%d new_mode:%llu old_mode:%llu\n",
Clarence Ip13a8cf42016-09-29 17:27:47 -04002652 i, new_mods[i], old_mods[i]);
Clarence Ip282dad62016-09-27 17:07:35 -04002653 pstate->dirty |= SDE_PLANE_DIRTY_FORMAT |
2654 SDE_PLANE_DIRTY_RECTS;
Lloyd Atkinsonfa2489c2016-05-25 15:16:03 -04002655 break;
2656 }
2657 }
Alan Kwong4dd64c82017-02-04 18:41:51 -08002658 for (i = 0; i < ARRAY_SIZE(fb->pitches); i++) {
Lloyd Atkinson3ab9ef72016-07-14 17:42:41 -04002659 if (new_pitches[i] != old_pitches[i]) {
Clarence Ip13a8cf42016-09-29 17:27:47 -04002660 SDE_DEBUG_PLANE(psde,
2661 "pitches change plane:%d\"\
Dhaval Patel47302cf2016-08-18 15:04:28 -07002662 old_pitches:%u new_pitches:%u\n",
Clarence Ip13a8cf42016-09-29 17:27:47 -04002663 i, old_pitches[i], new_pitches[i]);
Clarence Ip282dad62016-09-27 17:07:35 -04002664 pstate->dirty |= SDE_PLANE_DIRTY_RECTS;
Lloyd Atkinson3ab9ef72016-07-14 17:42:41 -04002665 break;
2666 }
2667 }
Alan Kwong4dd64c82017-02-04 18:41:51 -08002668 for (i = 0; i < ARRAY_SIZE(fb->offsets); i++) {
Dhaval Patel47302cf2016-08-18 15:04:28 -07002669 if (new_offset[i] != old_offset[i]) {
Clarence Ip13a8cf42016-09-29 17:27:47 -04002670 SDE_DEBUG_PLANE(psde,
2671 "offset change plane:%d\"\
Dhaval Patel47302cf2016-08-18 15:04:28 -07002672 old_offset:%u new_offset:%u\n",
Clarence Ip13a8cf42016-09-29 17:27:47 -04002673 i, old_offset[i], new_offset[i]);
Clarence Ip282dad62016-09-27 17:07:35 -04002674 pstate->dirty |= SDE_PLANE_DIRTY_FORMAT |
2675 SDE_PLANE_DIRTY_RECTS;
Dhaval Patel47302cf2016-08-18 15:04:28 -07002676 break;
2677 }
2678 }
Lloyd Atkinson3ab9ef72016-07-14 17:42:41 -04002679 }
Lloyd Atkinsonfa2489c2016-05-25 15:16:03 -04002680}
2681
Alan Kwong4dd64c82017-02-04 18:41:51 -08002682static int sde_plane_sspp_atomic_check(struct drm_plane *plane,
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04002683 struct drm_plane_state *state)
2684{
Clarence Ipdedbba92016-09-27 17:43:10 -04002685 int ret = 0;
Clarence Ipdbde9832016-06-26 09:48:36 -04002686 struct sde_plane *psde;
2687 struct sde_plane_state *pstate;
Alan Kwong4dd64c82017-02-04 18:41:51 -08002688 struct sde_plane_rot_state *rstate;
Lloyd Atkinson9a673492016-07-05 11:41:57 -04002689 const struct sde_format *fmt;
Dhaval Patel47302cf2016-08-18 15:04:28 -07002690 struct sde_rect src, dst;
Clarence Ipdbde9832016-06-26 09:48:36 -04002691 uint32_t deci_w, deci_h, src_deci_w, src_deci_h;
Dhaval Patel47302cf2016-08-18 15:04:28 -07002692 uint32_t max_upscale, max_downscale, min_src_size, max_linewidth;
2693 bool q16_data = true;
Clarence Ipdbde9832016-06-26 09:48:36 -04002694
2695 if (!plane || !state) {
Clarence Ip13a8cf42016-09-29 17:27:47 -04002696 SDE_ERROR("invalid arg(s), plane %d state %d\n",
2697 plane != 0, state != 0);
Clarence Ipdbde9832016-06-26 09:48:36 -04002698 ret = -EINVAL;
2699 goto exit;
2700 }
2701
2702 psde = to_sde_plane(plane);
2703 pstate = to_sde_plane_state(state);
Alan Kwong4dd64c82017-02-04 18:41:51 -08002704 rstate = &pstate->rot;
Clarence Ipdbde9832016-06-26 09:48:36 -04002705
2706 if (!psde->pipe_sblk) {
Clarence Ip13a8cf42016-09-29 17:27:47 -04002707 SDE_ERROR_PLANE(psde, "invalid catalog\n");
Clarence Ipdbde9832016-06-26 09:48:36 -04002708 ret = -EINVAL;
2709 goto exit;
2710 }
2711
Clarence Ipdedbba92016-09-27 17:43:10 -04002712 deci_w = sde_plane_get_property(pstate, PLANE_PROP_H_DECIMATE);
2713 deci_h = sde_plane_get_property(pstate, PLANE_PROP_V_DECIMATE);
Clarence Ipdbde9832016-06-26 09:48:36 -04002714
2715 /* src values are in Q16 fixed point, convert to integer */
Alan Kwong4dd64c82017-02-04 18:41:51 -08002716 POPULATE_RECT(&src, rstate->out_src_x, rstate->out_src_y,
2717 rstate->out_src_w, rstate->out_src_h, q16_data);
Dhaval Patel47302cf2016-08-18 15:04:28 -07002718 POPULATE_RECT(&dst, state->crtc_x, state->crtc_y, state->crtc_w,
2719 state->crtc_h, !q16_data);
Clarence Ipdbde9832016-06-26 09:48:36 -04002720
Dhaval Patel47302cf2016-08-18 15:04:28 -07002721 src_deci_w = DECIMATED_DIMENSION(src.w, deci_w);
2722 src_deci_h = DECIMATED_DIMENSION(src.h, deci_h);
Clarence Ipdbde9832016-06-26 09:48:36 -04002723
Dhaval Patel47302cf2016-08-18 15:04:28 -07002724 max_upscale = psde->pipe_sblk->maxupscale;
2725 max_downscale = psde->pipe_sblk->maxdwnscale;
2726 max_linewidth = psde->pipe_sblk->maxlinewidth;
Clarence Ipdbde9832016-06-26 09:48:36 -04002727
Clarence Ip13a8cf42016-09-29 17:27:47 -04002728 SDE_DEBUG_PLANE(psde, "check %d -> %d\n",
Dhaval Patel47302cf2016-08-18 15:04:28 -07002729 sde_plane_enabled(plane->state), sde_plane_enabled(state));
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04002730
Dhaval Patel47302cf2016-08-18 15:04:28 -07002731 if (!sde_plane_enabled(state))
2732 goto modeset_update;
Clarence Ipdbde9832016-06-26 09:48:36 -04002733
Alan Kwong4dd64c82017-02-04 18:41:51 -08002734 SDE_DEBUG(
2735 "plane%d.%u sspp:%x/%dx%d/%c%c%c%c/%llx/%dx%d+%d+%d crtc:%dx%d+%d+%d\n",
2736 plane->base.id, rstate->sequence_id,
2737 rstate->out_rotation,
2738 rstate->out_fb_width, rstate->out_fb_height,
2739 rstate->out_fb_pixel_format >> 0,
2740 rstate->out_fb_pixel_format >> 8,
2741 rstate->out_fb_pixel_format >> 16,
2742 rstate->out_fb_pixel_format >> 24,
2743 rstate->out_fb_modifier[0],
2744 rstate->out_src_w >> 16, rstate->out_src_h >> 16,
2745 rstate->out_src_x >> 16, rstate->out_src_y >> 16,
2746 state->crtc_w, state->crtc_h,
2747 state->crtc_x, state->crtc_y);
2748
Dhaval Patel47302cf2016-08-18 15:04:28 -07002749 fmt = to_sde_format(msm_framebuffer_format(state->fb));
2750
2751 min_src_size = SDE_FORMAT_IS_YUV(fmt) ? 2 : 1;
2752
2753 if (SDE_FORMAT_IS_YUV(fmt) &&
2754 (!(psde->features & SDE_SSPP_SCALER) ||
abeykun1c312f62016-08-26 09:47:12 -04002755 !(psde->features & (BIT(SDE_SSPP_CSC)
2756 | BIT(SDE_SSPP_CSC_10BIT))))) {
Clarence Ip13a8cf42016-09-29 17:27:47 -04002757 SDE_ERROR_PLANE(psde,
2758 "plane doesn't have scaler/csc for yuv\n");
Dhaval Patel47302cf2016-08-18 15:04:28 -07002759 ret = -EINVAL;
2760
2761 /* check src bounds */
Alan Kwong4dd64c82017-02-04 18:41:51 -08002762 } else if (rstate->out_fb_width > MAX_IMG_WIDTH ||
2763 rstate->out_fb_height > MAX_IMG_HEIGHT ||
Dhaval Patel47302cf2016-08-18 15:04:28 -07002764 src.w < min_src_size || src.h < min_src_size ||
Alan Kwong4dd64c82017-02-04 18:41:51 -08002765 CHECK_LAYER_BOUNDS(src.x, src.w, rstate->out_fb_width) ||
2766 CHECK_LAYER_BOUNDS(src.y, src.h, rstate->out_fb_height)) {
Clarence Ip13a8cf42016-09-29 17:27:47 -04002767 SDE_ERROR_PLANE(psde, "invalid source %u, %u, %ux%u\n",
Dhaval Patel47302cf2016-08-18 15:04:28 -07002768 src.x, src.y, src.w, src.h);
2769 ret = -E2BIG;
2770
2771 /* valid yuv image */
2772 } else if (SDE_FORMAT_IS_YUV(fmt) && ((src.x & 0x1) || (src.y & 0x1) ||
2773 (src.w & 0x1) || (src.h & 0x1))) {
Clarence Ip13a8cf42016-09-29 17:27:47 -04002774 SDE_ERROR_PLANE(psde, "invalid yuv source %u, %u, %ux%u\n",
Dhaval Patel47302cf2016-08-18 15:04:28 -07002775 src.x, src.y, src.w, src.h);
2776 ret = -EINVAL;
2777
2778 /* min dst support */
2779 } else if (dst.w < 0x1 || dst.h < 0x1) {
Clarence Ip13a8cf42016-09-29 17:27:47 -04002780 SDE_ERROR_PLANE(psde, "invalid dest rect %u, %u, %ux%u\n",
Dhaval Patel47302cf2016-08-18 15:04:28 -07002781 dst.x, dst.y, dst.w, dst.h);
2782 ret = -EINVAL;
2783
2784 /* decimation validation */
2785 } else if (deci_w || deci_h) {
2786 if ((deci_w > psde->pipe_sblk->maxhdeciexp) ||
2787 (deci_h > psde->pipe_sblk->maxvdeciexp)) {
Clarence Ip13a8cf42016-09-29 17:27:47 -04002788 SDE_ERROR_PLANE(psde,
2789 "too much decimation requested\n");
Clarence Ipdbde9832016-06-26 09:48:36 -04002790 ret = -EINVAL;
Dhaval Patel47302cf2016-08-18 15:04:28 -07002791 } else if (fmt->fetch_mode != SDE_FETCH_LINEAR) {
Clarence Ip13a8cf42016-09-29 17:27:47 -04002792 SDE_ERROR_PLANE(psde,
2793 "decimation requires linear fetch\n");
Clarence Ipdbde9832016-06-26 09:48:36 -04002794 ret = -EINVAL;
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04002795 }
2796
Dhaval Patel47302cf2016-08-18 15:04:28 -07002797 } else if (!(psde->features & SDE_SSPP_SCALER) &&
2798 ((src.w != dst.w) || (src.h != dst.h))) {
Clarence Ip13a8cf42016-09-29 17:27:47 -04002799 SDE_ERROR_PLANE(psde,
2800 "pipe doesn't support scaling %ux%u->%ux%u\n",
Dhaval Patel47302cf2016-08-18 15:04:28 -07002801 src.w, src.h, dst.w, dst.h);
2802 ret = -EINVAL;
2803
2804 /* check decimated source width */
2805 } else if (src_deci_w > max_linewidth) {
Clarence Ip13a8cf42016-09-29 17:27:47 -04002806 SDE_ERROR_PLANE(psde,
2807 "invalid src w:%u, deci w:%u, line w:%u\n",
Dhaval Patel47302cf2016-08-18 15:04:28 -07002808 src.w, src_deci_w, max_linewidth);
2809 ret = -E2BIG;
2810
2811 /* check max scaler capability */
2812 } else if (((src_deci_w * max_upscale) < dst.w) ||
2813 ((src_deci_h * max_upscale) < dst.h) ||
2814 ((dst.w * max_downscale) < src_deci_w) ||
2815 ((dst.h * max_downscale) < src_deci_h)) {
Clarence Ip13a8cf42016-09-29 17:27:47 -04002816 SDE_ERROR_PLANE(psde,
2817 "too much scaling requested %ux%u->%ux%u\n",
Dhaval Patel47302cf2016-08-18 15:04:28 -07002818 src_deci_w, src_deci_h, dst.w, dst.h);
2819 ret = -E2BIG;
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04002820 }
2821
Veera Sundaram Sankaran02dd6ac2016-12-22 15:08:29 -08002822 /* check excl rect configs */
2823 if (pstate->excl_rect.w && pstate->excl_rect.h) {
2824 struct sde_rect intersect;
2825
2826 /*
2827 * Check exclusion rect against src rect.
2828 * Cropping is not required as hardware will consider only the
2829 * intersecting region with the src rect.
2830 */
2831 sde_kms_rect_intersect(&intersect, &src, &pstate->excl_rect);
2832 if (!intersect.w || !intersect.h || SDE_FORMAT_IS_YUV(fmt)) {
2833 SDE_ERROR_PLANE(psde,
2834 "invalid excl_rect:{%d,%d,%d,%d} src:{%d,%d,%d,%d}, fmt:%s\n",
2835 pstate->excl_rect.x, pstate->excl_rect.y,
2836 pstate->excl_rect.w, pstate->excl_rect.h,
2837 src.x, src.y, src.w, src.h,
2838 drm_get_format_name(fmt->base.pixel_format));
2839 ret = -EINVAL;
2840 }
2841 }
2842
Dhaval Patel47302cf2016-08-18 15:04:28 -07002843modeset_update:
Lloyd Atkinsonfa2489c2016-05-25 15:16:03 -04002844 if (!ret)
Alan Kwong4dd64c82017-02-04 18:41:51 -08002845 _sde_plane_sspp_atomic_check_mode_changed(psde,
2846 state, plane->state);
2847exit:
2848 return ret;
2849}
2850
2851static int sde_plane_atomic_check(struct drm_plane *plane,
2852 struct drm_plane_state *state)
2853{
2854 int ret = 0;
2855 struct sde_plane *psde;
2856 struct sde_plane_state *pstate;
2857
2858 if (!plane || !state) {
2859 SDE_ERROR("invalid arg(s), plane %d state %d\n",
2860 plane != 0, state != 0);
2861 ret = -EINVAL;
2862 goto exit;
2863 }
2864
2865 psde = to_sde_plane(plane);
2866 pstate = to_sde_plane_state(state);
2867
2868 SDE_DEBUG_PLANE(psde, "\n");
2869
2870 ret = sde_plane_rot_atomic_check(plane, state);
2871 if (ret)
2872 goto exit;
2873
2874 ret = sde_plane_sspp_atomic_check(plane, state);
2875
Clarence Ipdbde9832016-06-26 09:48:36 -04002876exit:
2877 return ret;
2878}
2879
Clarence Ipcae1bb62016-07-07 12:07:13 -04002880/**
2881 * sde_plane_flush - final plane operations before commit flush
2882 * @plane: Pointer to drm plane structure
2883 */
2884void sde_plane_flush(struct drm_plane *plane)
Clarence Ipdbde9832016-06-26 09:48:36 -04002885{
Clarence Ipcae1bb62016-07-07 12:07:13 -04002886 struct sde_plane *psde;
2887
Clarence Ip13a8cf42016-09-29 17:27:47 -04002888 if (!plane) {
2889 SDE_ERROR("invalid plane\n");
Clarence Ipcae1bb62016-07-07 12:07:13 -04002890 return;
Clarence Ip13a8cf42016-09-29 17:27:47 -04002891 }
Clarence Ipcae1bb62016-07-07 12:07:13 -04002892
2893 psde = to_sde_plane(plane);
2894
2895 /*
2896 * These updates have to be done immediately before the plane flush
2897 * timing, and may not be moved to the atomic_update/mode_set functions.
2898 */
2899 if (psde->is_error)
Clarence Ip3bf8d872017-02-16 15:25:38 -05002900 /* force white frame with 100% alpha pipe output on error */
2901 _sde_plane_color_fill(psde, 0xFFFFFF, 0xFF);
Clarence Ipcae1bb62016-07-07 12:07:13 -04002902 else if (psde->color_fill & SDE_PLANE_COLOR_FILL_FLAG)
2903 /* force 100% alpha */
Clarence Ip13a8cf42016-09-29 17:27:47 -04002904 _sde_plane_color_fill(psde, psde->color_fill, 0xFF);
Clarence Ipcae1bb62016-07-07 12:07:13 -04002905 else if (psde->pipe_hw && psde->csc_ptr && psde->pipe_hw->ops.setup_csc)
2906 psde->pipe_hw->ops.setup_csc(psde->pipe_hw, psde->csc_ptr);
2907
Clarence Ip56902792017-03-17 15:22:07 -04002908 /* force black color fill during suspend */
2909 if (msm_is_suspend_state(plane->dev) && suspend_blank)
2910 _sde_plane_color_fill(psde, 0x0, 0x0);
2911
Clarence Ipcae1bb62016-07-07 12:07:13 -04002912 /* flag h/w flush complete */
2913 if (plane->state)
Clarence Ipdbde9832016-06-26 09:48:36 -04002914 to_sde_plane_state(plane->state)->pending = false;
Narendra Muppalla1b0b3352015-09-29 10:16:51 -07002915}
2916
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04002917static void sde_plane_atomic_update(struct drm_plane *plane,
Clarence Ipe78efb72016-06-24 18:35:21 -04002918 struct drm_plane_state *old_state)
Narendra Muppalla1b0b3352015-09-29 10:16:51 -07002919{
Clarence Ip13a8cf42016-09-29 17:27:47 -04002920 struct sde_plane *psde;
Clarence Ip5e2a9222016-06-26 22:38:24 -04002921 struct drm_plane_state *state;
2922 struct sde_plane_state *pstate;
Alan Kwong4dd64c82017-02-04 18:41:51 -08002923 struct sde_plane_state *old_pstate;
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04002924
Clarence Ip13a8cf42016-09-29 17:27:47 -04002925 if (!plane) {
2926 SDE_ERROR("invalid plane\n");
2927 return;
2928 } else if (!plane->state) {
2929 SDE_ERROR("invalid plane state\n");
Clarence Ip5e2a9222016-06-26 22:38:24 -04002930 return;
2931 }
2932
Clarence Ip13a8cf42016-09-29 17:27:47 -04002933 psde = to_sde_plane(plane);
2934 psde->is_error = false;
Clarence Ip5e2a9222016-06-26 22:38:24 -04002935 state = plane->state;
2936 pstate = to_sde_plane_state(state);
Alan Kwong4dd64c82017-02-04 18:41:51 -08002937 old_pstate = to_sde_plane_state(old_state);
Clarence Ip5e2a9222016-06-26 22:38:24 -04002938
Clarence Ip13a8cf42016-09-29 17:27:47 -04002939 SDE_DEBUG_PLANE(psde, "\n");
Clarence Ipae4e60c2016-06-26 22:44:04 -04002940
Alan Kwong4dd64c82017-02-04 18:41:51 -08002941 sde_plane_rot_atomic_update(plane, old_state);
2942
2943 if (!sde_plane_sspp_enabled(state)) {
Clarence Ip5e2a9222016-06-26 22:38:24 -04002944 pstate->pending = true;
Clarence Ip282dad62016-09-27 17:07:35 -04002945 } else {
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04002946 int ret;
2947
Alan Kwong4dd64c82017-02-04 18:41:51 -08002948 ret = sde_plane_sspp_atomic_update(plane, state);
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04002949 /* atomic_check should have ensured that this doesn't fail */
2950 WARN_ON(ret < 0);
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04002951 }
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04002952}
2953
Dhaval Patel47302cf2016-08-18 15:04:28 -07002954
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04002955/* helper to install properties which are common to planes and crtcs */
Dhaval Patel47302cf2016-08-18 15:04:28 -07002956static void _sde_plane_install_properties(struct drm_plane *plane,
Jeykumar Sankaran2e655032017-02-04 14:05:45 -08002957 struct sde_mdss_cfg *catalog, u32 master_plane_id)
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04002958{
Clarence Ip5e2a9222016-06-26 22:38:24 -04002959 static const struct drm_prop_enum_list e_blend_op[] = {
2960 {SDE_DRM_BLEND_OP_NOT_DEFINED, "not_defined"},
2961 {SDE_DRM_BLEND_OP_OPAQUE, "opaque"},
2962 {SDE_DRM_BLEND_OP_PREMULTIPLIED, "premultiplied"},
2963 {SDE_DRM_BLEND_OP_COVERAGE, "coverage"}
2964 };
2965 static const struct drm_prop_enum_list e_src_config[] = {
2966 {SDE_DRM_DEINTERLACE, "deinterlace"}
2967 };
Clarence Ipea3d6262016-07-15 16:20:11 -04002968 const struct sde_format_extended *format_list;
Dhaval Patel4e574842016-08-23 15:11:37 -07002969 struct sde_kms_info *info;
Clarence Ip5e2a9222016-06-26 22:38:24 -04002970 struct sde_plane *psde = to_sde_plane(plane);
Clarence Ipc47a0692016-10-11 10:54:17 -04002971 int zpos_max = 255;
2972 int zpos_def = 0;
Benet Clarkeb1b4462016-06-27 14:43:06 -07002973 char feature_name[256];
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04002974
Clarence Ip13a8cf42016-09-29 17:27:47 -04002975 if (!plane || !psde) {
2976 SDE_ERROR("invalid plane\n");
2977 return;
2978 } else if (!psde->pipe_hw || !psde->pipe_sblk) {
2979 SDE_ERROR("invalid plane, pipe_hw %d pipe_sblk %d\n",
2980 psde->pipe_hw != 0, psde->pipe_sblk != 0);
Clarence Ip5e2a9222016-06-26 22:38:24 -04002981 return;
Clarence Ipc47a0692016-10-11 10:54:17 -04002982 } else if (!catalog) {
2983 SDE_ERROR("invalid catalog\n");
2984 return;
Clarence Ip5e2a9222016-06-26 22:38:24 -04002985 }
2986
Alan Kwong4dd64c82017-02-04 18:41:51 -08002987 psde->catalog = catalog;
2988
Clarence Ipc47a0692016-10-11 10:54:17 -04002989 if (sde_is_custom_client()) {
Clarence Ip649989a2016-10-21 14:28:34 -04002990 if (catalog->mixer_count && catalog->mixer &&
2991 catalog->mixer[0].sblk->maxblendstages) {
2992 zpos_max = catalog->mixer[0].sblk->maxblendstages - 1;
2993 if (zpos_max > SDE_STAGE_MAX - SDE_STAGE_0 - 1)
2994 zpos_max = SDE_STAGE_MAX - SDE_STAGE_0 - 1;
2995 }
Clarence Ipc47a0692016-10-11 10:54:17 -04002996 } else if (plane->type != DRM_PLANE_TYPE_PRIMARY) {
2997 /* reserve zpos == 0 for primary planes */
2998 zpos_def = drm_plane_index(plane) + 1;
2999 }
3000
3001 msm_property_install_range(&psde->property_info, "zpos",
3002 0x0, 0, zpos_max, zpos_def, PLANE_PROP_ZPOS);
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04003003
Lloyd Atkinson38ad8c92016-07-06 10:39:32 -04003004 msm_property_install_range(&psde->property_info, "alpha",
Dhaval Patel47302cf2016-08-18 15:04:28 -07003005 0x0, 0, 255, 255, PLANE_PROP_ALPHA);
Clarence Ip5e2a9222016-06-26 22:38:24 -04003006
Dhaval Patel47302cf2016-08-18 15:04:28 -07003007 /* linux default file descriptor range on each process */
Clarence Ipcae1bb62016-07-07 12:07:13 -04003008 msm_property_install_range(&psde->property_info, "input_fence",
Dhaval Patel4e574842016-08-23 15:11:37 -07003009 0x0, 0, INR_OPEN_MAX, 0, PLANE_PROP_INPUT_FENCE);
Clarence Ip5e2a9222016-06-26 22:38:24 -04003010
Jeykumar Sankaran2e655032017-02-04 14:05:45 -08003011 if (!master_plane_id) {
3012 if (psde->pipe_sblk->maxhdeciexp) {
3013 msm_property_install_range(&psde->property_info,
3014 "h_decimate", 0x0, 0,
3015 psde->pipe_sblk->maxhdeciexp, 0,
3016 PLANE_PROP_H_DECIMATE);
3017 }
Clarence Ipdedbba92016-09-27 17:43:10 -04003018
Jeykumar Sankaran2e655032017-02-04 14:05:45 -08003019 if (psde->pipe_sblk->maxvdeciexp) {
3020 msm_property_install_range(&psde->property_info,
3021 "v_decimate", 0x0, 0,
3022 psde->pipe_sblk->maxvdeciexp, 0,
3023 PLANE_PROP_V_DECIMATE);
3024 }
Clarence Ipdedbba92016-09-27 17:43:10 -04003025
Jeykumar Sankaran2e655032017-02-04 14:05:45 -08003026 if (psde->features & BIT(SDE_SSPP_SCALER_QSEED3)) {
3027 msm_property_install_volatile_range(
3028 &psde->property_info, "scaler_v2",
3029 0x0, 0, ~0, 0, PLANE_PROP_SCALER_V2);
3030 msm_property_install_blob(&psde->property_info,
3031 "lut_ed", 0, PLANE_PROP_SCALER_LUT_ED);
3032 msm_property_install_blob(&psde->property_info,
3033 "lut_cir", 0,
3034 PLANE_PROP_SCALER_LUT_CIR);
3035 msm_property_install_blob(&psde->property_info,
3036 "lut_sep", 0,
3037 PLANE_PROP_SCALER_LUT_SEP);
3038 } else if (psde->features & SDE_SSPP_SCALER) {
3039 msm_property_install_volatile_range(
3040 &psde->property_info, "scaler_v1", 0x0,
3041 0, ~0, 0, PLANE_PROP_SCALER_V1);
3042 }
Clarence Ipb43d4592016-09-08 14:21:35 -04003043
Dhaval Patel0aee0972017-02-08 19:00:58 -08003044 if (psde->features & BIT(SDE_SSPP_CSC) ||
3045 psde->features & BIT(SDE_SSPP_CSC_10BIT))
Jeykumar Sankaran2e655032017-02-04 14:05:45 -08003046 msm_property_install_volatile_range(
3047 &psde->property_info, "csc_v1", 0x0,
3048 0, ~0, 0, PLANE_PROP_CSC_V1);
Clarence Ip5fc00c52016-09-23 15:03:34 -04003049
Jeykumar Sankaran2e655032017-02-04 14:05:45 -08003050 if (psde->features & BIT(SDE_SSPP_HSIC)) {
3051 snprintf(feature_name, sizeof(feature_name), "%s%d",
3052 "SDE_SSPP_HUE_V",
3053 psde->pipe_sblk->hsic_blk.version >> 16);
3054 msm_property_install_range(&psde->property_info,
3055 feature_name, 0, 0, 0xFFFFFFFF, 0,
3056 PLANE_PROP_HUE_ADJUST);
3057 snprintf(feature_name, sizeof(feature_name), "%s%d",
3058 "SDE_SSPP_SATURATION_V",
3059 psde->pipe_sblk->hsic_blk.version >> 16);
3060 msm_property_install_range(&psde->property_info,
3061 feature_name, 0, 0, 0xFFFFFFFF, 0,
3062 PLANE_PROP_SATURATION_ADJUST);
3063 snprintf(feature_name, sizeof(feature_name), "%s%d",
3064 "SDE_SSPP_VALUE_V",
3065 psde->pipe_sblk->hsic_blk.version >> 16);
3066 msm_property_install_range(&psde->property_info,
3067 feature_name, 0, 0, 0xFFFFFFFF, 0,
3068 PLANE_PROP_VALUE_ADJUST);
3069 snprintf(feature_name, sizeof(feature_name), "%s%d",
3070 "SDE_SSPP_CONTRAST_V",
3071 psde->pipe_sblk->hsic_blk.version >> 16);
3072 msm_property_install_range(&psde->property_info,
3073 feature_name, 0, 0, 0xFFFFFFFF, 0,
3074 PLANE_PROP_CONTRAST_ADJUST);
3075 }
Benet Clarkeb1b4462016-06-27 14:43:06 -07003076 }
3077
Veera Sundaram Sankaran02dd6ac2016-12-22 15:08:29 -08003078 if (psde->features & BIT(SDE_SSPP_EXCL_RECT))
3079 msm_property_install_volatile_range(&psde->property_info,
3080 "excl_rect_v1", 0x0, 0, ~0, 0, PLANE_PROP_EXCL_RECT_V1);
3081
Alan Kwong4dd64c82017-02-04 18:41:51 -08003082 sde_plane_rot_install_properties(plane, catalog);
Clarence Ip5e2a9222016-06-26 22:38:24 -04003083
Lloyd Atkinson38ad8c92016-07-06 10:39:32 -04003084 msm_property_install_enum(&psde->property_info, "blend_op", 0x0, 0,
Dhaval Patel47302cf2016-08-18 15:04:28 -07003085 e_blend_op, ARRAY_SIZE(e_blend_op), PLANE_PROP_BLEND_OP);
Clarence Ip5e2a9222016-06-26 22:38:24 -04003086
Dhaval Patel47302cf2016-08-18 15:04:28 -07003087 msm_property_install_enum(&psde->property_info, "src_config", 0x0, 1,
3088 e_src_config, ARRAY_SIZE(e_src_config), PLANE_PROP_SRC_CONFIG);
3089
3090 if (psde->pipe_hw->ops.setup_solidfill)
3091 msm_property_install_range(&psde->property_info, "color_fill",
3092 0, 0, 0xFFFFFFFF, 0, PLANE_PROP_COLOR_FILL);
3093
Dhaval Patel4e574842016-08-23 15:11:37 -07003094 info = kzalloc(sizeof(struct sde_kms_info), GFP_KERNEL);
Clarence Ip13a8cf42016-09-29 17:27:47 -04003095 if (!info) {
3096 SDE_ERROR("failed to allocate info memory\n");
Dhaval Patel4e574842016-08-23 15:11:37 -07003097 return;
Clarence Ip13a8cf42016-09-29 17:27:47 -04003098 }
Dhaval Patel4e574842016-08-23 15:11:37 -07003099
3100 msm_property_install_blob(&psde->property_info, "capabilities",
3101 DRM_MODE_PROP_IMMUTABLE, PLANE_PROP_INFO);
3102 sde_kms_info_reset(info);
3103
Clarence Ipea3d6262016-07-15 16:20:11 -04003104 format_list = psde->pipe_sblk->format_list;
Jeykumar Sankaran2e655032017-02-04 14:05:45 -08003105
3106 if (master_plane_id) {
3107 sde_kms_info_add_keyint(info, "primary_smart_plane_id",
3108 master_plane_id);
3109 format_list = plane_formats;
3110 }
3111
Clarence Ipea3d6262016-07-15 16:20:11 -04003112 if (format_list) {
Clarence Ipea3d6262016-07-15 16:20:11 -04003113 sde_kms_info_start(info, "pixel_formats");
3114 while (format_list->fourcc_format) {
3115 sde_kms_info_append_format(info,
3116 format_list->fourcc_format,
3117 format_list->modifier);
3118 ++format_list;
3119 }
3120 sde_kms_info_stop(info);
Clarence Ipea3d6262016-07-15 16:20:11 -04003121 }
Dhaval Patel4e574842016-08-23 15:11:37 -07003122
3123 sde_kms_info_add_keyint(info, "max_linewidth",
3124 psde->pipe_sblk->maxlinewidth);
3125 sde_kms_info_add_keyint(info, "max_upscale",
3126 psde->pipe_sblk->maxupscale);
3127 sde_kms_info_add_keyint(info, "max_downscale",
3128 psde->pipe_sblk->maxdwnscale);
3129 sde_kms_info_add_keyint(info, "max_horizontal_deci",
3130 psde->pipe_sblk->maxhdeciexp);
3131 sde_kms_info_add_keyint(info, "max_vertical_deci",
3132 psde->pipe_sblk->maxvdeciexp);
3133 msm_property_set_blob(&psde->property_info, &psde->blob_info,
3134 info->data, info->len, PLANE_PROP_INFO);
3135
3136 kfree(info);
Benet Clarkd009b1d2016-06-27 14:45:59 -07003137
3138 if (psde->features & BIT(SDE_SSPP_MEMCOLOR)) {
3139 snprintf(feature_name, sizeof(feature_name), "%s%d",
3140 "SDE_SSPP_SKIN_COLOR_V",
3141 psde->pipe_sblk->memcolor_blk.version >> 16);
3142 msm_property_install_blob(&psde->property_info, feature_name, 0,
3143 PLANE_PROP_SKIN_COLOR);
3144 snprintf(feature_name, sizeof(feature_name), "%s%d",
3145 "SDE_SSPP_SKY_COLOR_V",
3146 psde->pipe_sblk->memcolor_blk.version >> 16);
3147 msm_property_install_blob(&psde->property_info, feature_name, 0,
3148 PLANE_PROP_SKY_COLOR);
3149 snprintf(feature_name, sizeof(feature_name), "%s%d",
3150 "SDE_SSPP_FOLIAGE_COLOR_V",
3151 psde->pipe_sblk->memcolor_blk.version >> 16);
3152 msm_property_install_blob(&psde->property_info, feature_name, 0,
3153 PLANE_PROP_FOLIAGE_COLOR);
3154 }
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04003155}
3156
Clarence Ip5fc00c52016-09-23 15:03:34 -04003157static inline void _sde_plane_set_csc_v1(struct sde_plane *psde, void *usr_ptr)
3158{
3159 struct sde_drm_csc_v1 csc_v1;
3160 int i;
3161
3162 if (!psde) {
3163 SDE_ERROR("invalid plane\n");
3164 return;
3165 }
3166
3167 psde->csc_usr_ptr = NULL;
3168 if (!usr_ptr) {
Clarence Ip13a8cf42016-09-29 17:27:47 -04003169 SDE_DEBUG_PLANE(psde, "csc data removed\n");
Clarence Ip5fc00c52016-09-23 15:03:34 -04003170 return;
3171 }
3172
3173 if (copy_from_user(&csc_v1, usr_ptr, sizeof(csc_v1))) {
Clarence Ip13a8cf42016-09-29 17:27:47 -04003174 SDE_ERROR_PLANE(psde, "failed to copy csc data\n");
Clarence Ip5fc00c52016-09-23 15:03:34 -04003175 return;
3176 }
3177
Clarence Ipb43d4592016-09-08 14:21:35 -04003178 /* populate from user space */
Clarence Ip5fc00c52016-09-23 15:03:34 -04003179 for (i = 0; i < SDE_CSC_MATRIX_COEFF_SIZE; ++i)
3180 psde->csc_cfg.csc_mv[i] = csc_v1.ctm_coeff[i] >> 16;
3181 for (i = 0; i < SDE_CSC_BIAS_SIZE; ++i) {
3182 psde->csc_cfg.csc_pre_bv[i] = csc_v1.pre_bias[i];
3183 psde->csc_cfg.csc_post_bv[i] = csc_v1.post_bias[i];
3184 }
3185 for (i = 0; i < SDE_CSC_CLAMP_SIZE; ++i) {
3186 psde->csc_cfg.csc_pre_lv[i] = csc_v1.pre_clamp[i];
3187 psde->csc_cfg.csc_post_lv[i] = csc_v1.post_clamp[i];
3188 }
3189 psde->csc_usr_ptr = &psde->csc_cfg;
3190}
3191
Clarence Ipb43d4592016-09-08 14:21:35 -04003192static inline void _sde_plane_set_scaler_v1(struct sde_plane *psde, void *usr)
3193{
3194 struct sde_drm_scaler_v1 scale_v1;
3195 struct sde_hw_pixel_ext *pe;
3196 int i;
3197
3198 if (!psde) {
3199 SDE_ERROR("invalid plane\n");
3200 return;
3201 }
3202
3203 psde->pixel_ext_usr = false;
3204 if (!usr) {
Clarence Ip13a8cf42016-09-29 17:27:47 -04003205 SDE_DEBUG_PLANE(psde, "scale data removed\n");
Clarence Ipb43d4592016-09-08 14:21:35 -04003206 return;
3207 }
3208
3209 if (copy_from_user(&scale_v1, usr, sizeof(scale_v1))) {
Clarence Ip13a8cf42016-09-29 17:27:47 -04003210 SDE_ERROR_PLANE(psde, "failed to copy scale data\n");
Clarence Ipb43d4592016-09-08 14:21:35 -04003211 return;
3212 }
3213
3214 /* populate from user space */
3215 pe = &(psde->pixel_ext);
3216 memset(pe, 0, sizeof(struct sde_hw_pixel_ext));
3217 for (i = 0; i < SDE_MAX_PLANES; i++) {
3218 pe->init_phase_x[i] = scale_v1.init_phase_x[i];
3219 pe->phase_step_x[i] = scale_v1.phase_step_x[i];
3220 pe->init_phase_y[i] = scale_v1.init_phase_y[i];
3221 pe->phase_step_y[i] = scale_v1.phase_step_y[i];
3222
3223 pe->horz_filter[i] = scale_v1.horz_filter[i];
3224 pe->vert_filter[i] = scale_v1.vert_filter[i];
3225 }
3226 for (i = 0; i < SDE_MAX_PLANES; i++) {
abeykun41060122016-11-28 13:02:01 -05003227 pe->left_ftch[i] = scale_v1.pe.left_ftch[i];
3228 pe->right_ftch[i] = scale_v1.pe.right_ftch[i];
3229 pe->left_rpt[i] = scale_v1.pe.left_rpt[i];
3230 pe->right_rpt[i] = scale_v1.pe.right_rpt[i];
3231 pe->roi_w[i] = scale_v1.pe.num_ext_pxls_lr[i];
Clarence Ipb43d4592016-09-08 14:21:35 -04003232
abeykun41060122016-11-28 13:02:01 -05003233 pe->top_ftch[i] = scale_v1.pe.top_ftch[i];
3234 pe->btm_ftch[i] = scale_v1.pe.btm_ftch[i];
3235 pe->top_rpt[i] = scale_v1.pe.top_rpt[i];
3236 pe->btm_rpt[i] = scale_v1.pe.btm_rpt[i];
3237 pe->roi_h[i] = scale_v1.pe.num_ext_pxls_tb[i];
Clarence Ipb43d4592016-09-08 14:21:35 -04003238 }
abeykun41060122016-11-28 13:02:01 -05003239
Clarence Ipb43d4592016-09-08 14:21:35 -04003240 psde->pixel_ext_usr = true;
3241
Clarence Ip13a8cf42016-09-29 17:27:47 -04003242 SDE_DEBUG_PLANE(psde, "user property data copied\n");
Clarence Ipb43d4592016-09-08 14:21:35 -04003243}
3244
abeykun48f407a2016-08-25 12:06:44 -04003245static inline void _sde_plane_set_scaler_v2(struct sde_plane *psde,
3246 struct sde_plane_state *pstate, void *usr)
3247{
3248 struct sde_drm_scaler_v2 scale_v2;
3249 struct sde_hw_pixel_ext *pe;
3250 int i;
3251 struct sde_hw_scaler3_cfg *cfg;
3252
3253 if (!psde) {
3254 SDE_ERROR("invalid plane\n");
3255 return;
3256 }
3257
3258 cfg = psde->scaler3_cfg;
3259 psde->pixel_ext_usr = false;
3260 if (!usr) {
3261 SDE_DEBUG_PLANE(psde, "scale data removed\n");
3262 return;
3263 }
3264
3265 if (copy_from_user(&scale_v2, usr, sizeof(scale_v2))) {
3266 SDE_ERROR_PLANE(psde, "failed to copy scale data\n");
3267 return;
3268 }
3269
3270 /* populate from user space */
3271 pe = &(psde->pixel_ext);
3272 memset(pe, 0, sizeof(struct sde_hw_pixel_ext));
3273 cfg->enable = scale_v2.enable;
3274 cfg->dir_en = scale_v2.dir_en;
3275 for (i = 0; i < SDE_MAX_PLANES; i++) {
3276 cfg->init_phase_x[i] = scale_v2.init_phase_x[i];
3277 cfg->phase_step_x[i] = scale_v2.phase_step_x[i];
3278 cfg->init_phase_y[i] = scale_v2.init_phase_y[i];
3279 cfg->phase_step_y[i] = scale_v2.phase_step_y[i];
3280
3281 cfg->preload_x[i] = scale_v2.preload_x[i];
3282 cfg->preload_y[i] = scale_v2.preload_y[i];
3283 cfg->src_width[i] = scale_v2.src_width[i];
3284 cfg->src_height[i] = scale_v2.src_height[i];
3285 }
3286 cfg->dst_width = scale_v2.dst_width;
3287 cfg->dst_height = scale_v2.dst_height;
3288
3289 cfg->y_rgb_filter_cfg = scale_v2.y_rgb_filter_cfg;
3290 cfg->uv_filter_cfg = scale_v2.uv_filter_cfg;
3291 cfg->alpha_filter_cfg = scale_v2.alpha_filter_cfg;
3292 cfg->blend_cfg = scale_v2.blend_cfg;
3293
3294 cfg->lut_flag = scale_v2.lut_flag;
3295 cfg->dir_lut_idx = scale_v2.dir_lut_idx;
3296 cfg->y_rgb_cir_lut_idx = scale_v2.y_rgb_cir_lut_idx;
3297 cfg->uv_cir_lut_idx = scale_v2.uv_cir_lut_idx;
3298 cfg->y_rgb_sep_lut_idx = scale_v2.y_rgb_sep_lut_idx;
3299 cfg->uv_sep_lut_idx = scale_v2.uv_sep_lut_idx;
3300
3301 cfg->de.enable = scale_v2.de.enable;
3302 cfg->de.sharpen_level1 = scale_v2.de.sharpen_level1;
3303 cfg->de.sharpen_level2 = scale_v2.de.sharpen_level2;
3304 cfg->de.clip = scale_v2.de.clip;
3305 cfg->de.limit = scale_v2.de.limit;
3306 cfg->de.thr_quiet = scale_v2.de.thr_quiet;
3307 cfg->de.thr_dieout = scale_v2.de.thr_dieout;
3308 cfg->de.thr_low = scale_v2.de.thr_low;
3309 cfg->de.thr_high = scale_v2.de.thr_high;
3310 cfg->de.prec_shift = scale_v2.de.prec_shift;
3311 for (i = 0; i < SDE_MAX_DE_CURVES; i++) {
3312 cfg->de.adjust_a[i] = scale_v2.de.adjust_a[i];
3313 cfg->de.adjust_b[i] = scale_v2.de.adjust_b[i];
3314 cfg->de.adjust_c[i] = scale_v2.de.adjust_c[i];
3315 }
3316 for (i = 0; i < SDE_MAX_PLANES; i++) {
abeykun41060122016-11-28 13:02:01 -05003317 pe->left_ftch[i] = scale_v2.pe.left_ftch[i];
3318 pe->right_ftch[i] = scale_v2.pe.right_ftch[i];
3319 pe->left_rpt[i] = scale_v2.pe.left_rpt[i];
3320 pe->right_rpt[i] = scale_v2.pe.right_rpt[i];
3321 pe->roi_w[i] = scale_v2.pe.num_ext_pxls_lr[i];
abeykun48f407a2016-08-25 12:06:44 -04003322
abeykun41060122016-11-28 13:02:01 -05003323 pe->top_ftch[i] = scale_v2.pe.top_ftch[i];
3324 pe->btm_ftch[i] = scale_v2.pe.btm_ftch[i];
3325 pe->top_rpt[i] = scale_v2.pe.top_rpt[i];
3326 pe->btm_rpt[i] = scale_v2.pe.btm_rpt[i];
3327 pe->roi_h[i] = scale_v2.pe.num_ext_pxls_tb[i];
abeykun48f407a2016-08-25 12:06:44 -04003328 }
3329 psde->pixel_ext_usr = true;
3330
3331 SDE_DEBUG_PLANE(psde, "user property data copied\n");
3332}
3333
Veera Sundaram Sankaran02dd6ac2016-12-22 15:08:29 -08003334static void _sde_plane_set_excl_rect_v1(struct sde_plane *psde,
3335 struct sde_plane_state *pstate, void *usr_ptr)
3336{
3337 struct drm_clip_rect excl_rect_v1;
3338
3339 if (!psde) {
3340 SDE_ERROR("invalid plane\n");
3341 return;
3342 }
3343
3344 if (!usr_ptr) {
3345 SDE_DEBUG_PLANE(psde, "excl rect data removed\n");
3346 return;
3347 }
3348
3349 if (copy_from_user(&excl_rect_v1, usr_ptr, sizeof(excl_rect_v1))) {
3350 SDE_ERROR_PLANE(psde, "failed to copy excl rect data\n");
3351 return;
3352 }
3353
3354 /* populate from user space */
3355 pstate->excl_rect.x = excl_rect_v1.x1;
3356 pstate->excl_rect.y = excl_rect_v1.y1;
3357 pstate->excl_rect.w = excl_rect_v1.x2 - excl_rect_v1.x1 + 1;
3358 pstate->excl_rect.h = excl_rect_v1.y2 - excl_rect_v1.y1 + 1;
3359}
3360
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04003361static int sde_plane_atomic_set_property(struct drm_plane *plane,
3362 struct drm_plane_state *state, struct drm_property *property,
3363 uint64_t val)
3364{
Clarence Ip13a8cf42016-09-29 17:27:47 -04003365 struct sde_plane *psde = plane ? to_sde_plane(plane) : NULL;
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04003366 struct sde_plane_state *pstate;
Clarence Ipe78efb72016-06-24 18:35:21 -04003367 int idx, ret = -EINVAL;
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04003368
Clarence Ip13a8cf42016-09-29 17:27:47 -04003369 SDE_DEBUG_PLANE(psde, "\n");
Clarence Ipaa0faf42016-05-30 12:07:48 -04003370
3371 if (!plane) {
Dhaval Patel47302cf2016-08-18 15:04:28 -07003372 SDE_ERROR("invalid plane\n");
Clarence Ipaa0faf42016-05-30 12:07:48 -04003373 } else if (!state) {
Clarence Ip13a8cf42016-09-29 17:27:47 -04003374 SDE_ERROR_PLANE(psde, "invalid state\n");
Clarence Ip730e7192016-06-26 22:45:09 -04003375 } else {
Clarence Ip4c1d9772016-06-26 09:35:38 -04003376 pstate = to_sde_plane_state(state);
Clarence Ipaa0faf42016-05-30 12:07:48 -04003377 ret = msm_property_atomic_set(&psde->property_info,
3378 pstate->property_values, pstate->property_blobs,
3379 property, val);
3380 if (!ret) {
3381 idx = msm_property_index(&psde->property_info,
3382 property);
Clarence Ip5fc00c52016-09-23 15:03:34 -04003383 switch (idx) {
3384 case PLANE_PROP_INPUT_FENCE:
Clarence Ip13a8cf42016-09-29 17:27:47 -04003385 _sde_plane_set_input_fence(psde, pstate, val);
Clarence Ip5fc00c52016-09-23 15:03:34 -04003386 break;
3387 case PLANE_PROP_CSC_V1:
3388 _sde_plane_set_csc_v1(psde, (void *)val);
3389 break;
Clarence Ipb43d4592016-09-08 14:21:35 -04003390 case PLANE_PROP_SCALER_V1:
3391 _sde_plane_set_scaler_v1(psde, (void *)val);
3392 break;
abeykun48f407a2016-08-25 12:06:44 -04003393 case PLANE_PROP_SCALER_V2:
3394 _sde_plane_set_scaler_v2(psde, pstate,
3395 (void *)val);
3396 break;
Veera Sundaram Sankaran02dd6ac2016-12-22 15:08:29 -08003397 case PLANE_PROP_EXCL_RECT_V1:
3398 _sde_plane_set_excl_rect_v1(psde, pstate,
3399 (void *)val);
3400 break;
Clarence Ip5fc00c52016-09-23 15:03:34 -04003401 default:
3402 /* nothing to do */
3403 break;
3404 }
Clarence Ipe78efb72016-06-24 18:35:21 -04003405 }
3406 }
3407
Alan Kwong4dd64c82017-02-04 18:41:51 -08003408 SDE_DEBUG_PLANE(psde, "%s[%d] <= 0x%llx ret=%d\n",
3409 property->name, property->base.id, val, ret);
3410
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04003411 return ret;
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04003412}
3413
3414static int sde_plane_set_property(struct drm_plane *plane,
3415 struct drm_property *property, uint64_t val)
3416{
Clarence Ip13a8cf42016-09-29 17:27:47 -04003417 SDE_DEBUG("\n");
Clarence Ip4c1d9772016-06-26 09:35:38 -04003418
Clarence Ipae4e60c2016-06-26 22:44:04 -04003419 return sde_plane_atomic_set_property(plane,
3420 plane->state, property, val);
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04003421}
3422
3423static int sde_plane_atomic_get_property(struct drm_plane *plane,
3424 const struct drm_plane_state *state,
3425 struct drm_property *property, uint64_t *val)
3426{
Clarence Ip13a8cf42016-09-29 17:27:47 -04003427 struct sde_plane *psde = plane ? to_sde_plane(plane) : NULL;
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04003428 struct sde_plane_state *pstate;
Clarence Ipaa0faf42016-05-30 12:07:48 -04003429 int ret = -EINVAL;
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04003430
Clarence Ipaa0faf42016-05-30 12:07:48 -04003431 if (!plane) {
Dhaval Patel47302cf2016-08-18 15:04:28 -07003432 SDE_ERROR("invalid plane\n");
Clarence Ipaa0faf42016-05-30 12:07:48 -04003433 } else if (!state) {
Dhaval Patel47302cf2016-08-18 15:04:28 -07003434 SDE_ERROR("invalid state\n");
Clarence Ipaa0faf42016-05-30 12:07:48 -04003435 } else {
Clarence Ip13a8cf42016-09-29 17:27:47 -04003436 SDE_DEBUG_PLANE(psde, "\n");
Clarence Ip4c1d9772016-06-26 09:35:38 -04003437 pstate = to_sde_plane_state(state);
Alan Kwong4dd64c82017-02-04 18:41:51 -08003438 sde_plane_rot_install_caps(plane);
Clarence Ipaa0faf42016-05-30 12:07:48 -04003439 ret = msm_property_atomic_get(&psde->property_info,
3440 pstate->property_values, pstate->property_blobs,
3441 property, val);
Clarence Ipe78efb72016-06-24 18:35:21 -04003442 }
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04003443
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04003444 return ret;
Narendra Muppalla1b0b3352015-09-29 10:16:51 -07003445}
3446
3447static void sde_plane_destroy(struct drm_plane *plane)
3448{
Clarence Ip13a8cf42016-09-29 17:27:47 -04003449 struct sde_plane *psde = plane ? to_sde_plane(plane) : NULL;
Narendra Muppalla1b0b3352015-09-29 10:16:51 -07003450
Clarence Ip13a8cf42016-09-29 17:27:47 -04003451 SDE_DEBUG_PLANE(psde, "\n");
Narendra Muppalla1b0b3352015-09-29 10:16:51 -07003452
Clarence Ip13a8cf42016-09-29 17:27:47 -04003453 if (psde) {
Alan Kwong1a00e4d2016-07-18 09:42:30 -04003454 _sde_plane_set_qos_ctrl(plane, false, SDE_PLANE_QOS_PANIC_CTRL);
3455
Dhaval Patel4e574842016-08-23 15:11:37 -07003456 if (psde->blob_info)
3457 drm_property_unreference_blob(psde->blob_info);
Clarence Ipaa0faf42016-05-30 12:07:48 -04003458 msm_property_destroy(&psde->property_info);
Clarence Ip730e7192016-06-26 22:45:09 -04003459 mutex_destroy(&psde->lock);
3460
Clarence Ip4ce59322016-06-26 22:27:51 -04003461 drm_plane_helper_disable(plane);
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04003462
Clarence Ip4ce59322016-06-26 22:27:51 -04003463 /* this will destroy the states as well */
3464 drm_plane_cleanup(plane);
3465
Clarence Ip4c1d9772016-06-26 09:35:38 -04003466 if (psde->pipe_hw)
3467 sde_hw_sspp_destroy(psde->pipe_hw);
3468
Clarence Ip4ce59322016-06-26 22:27:51 -04003469 kfree(psde);
3470 }
Narendra Muppalla1b0b3352015-09-29 10:16:51 -07003471}
3472
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04003473static void sde_plane_destroy_state(struct drm_plane *plane,
3474 struct drm_plane_state *state)
Narendra Muppalla1b0b3352015-09-29 10:16:51 -07003475{
Clarence Ipaa0faf42016-05-30 12:07:48 -04003476 struct sde_plane *psde;
Clarence Ipe78efb72016-06-24 18:35:21 -04003477 struct sde_plane_state *pstate;
Clarence Ipe78efb72016-06-24 18:35:21 -04003478
Clarence Ipae4e60c2016-06-26 22:44:04 -04003479 if (!plane || !state) {
Clarence Ip13a8cf42016-09-29 17:27:47 -04003480 SDE_ERROR("invalid arg(s), plane %d state %d\n",
3481 plane != 0, state != 0);
Clarence Ipae4e60c2016-06-26 22:44:04 -04003482 return;
3483 }
3484
Clarence Ipaa0faf42016-05-30 12:07:48 -04003485 psde = to_sde_plane(plane);
Clarence Ip730e7192016-06-26 22:45:09 -04003486 pstate = to_sde_plane_state(state);
3487
Clarence Ip13a8cf42016-09-29 17:27:47 -04003488 SDE_DEBUG_PLANE(psde, "\n");
Clarence Ip730e7192016-06-26 22:45:09 -04003489
Alan Kwong4dd64c82017-02-04 18:41:51 -08003490 sde_plane_rot_destroy_state(plane, &pstate->base);
3491
Clarence Ipe78efb72016-06-24 18:35:21 -04003492 /* remove ref count for frame buffers */
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04003493 if (state->fb)
3494 drm_framebuffer_unreference(state->fb);
3495
Clarence Ipae4e60c2016-06-26 22:44:04 -04003496 /* remove ref count for fence */
Clarence Ipcae1bb62016-07-07 12:07:13 -04003497 if (pstate->input_fence)
3498 sde_sync_put(pstate->input_fence);
Clarence Ipae4e60c2016-06-26 22:44:04 -04003499
Clarence Ipaa0faf42016-05-30 12:07:48 -04003500 /* destroy value helper */
3501 msm_property_destroy_state(&psde->property_info, pstate,
3502 pstate->property_values, pstate->property_blobs);
Narendra Muppalla1b0b3352015-09-29 10:16:51 -07003503}
3504
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04003505static struct drm_plane_state *
3506sde_plane_duplicate_state(struct drm_plane *plane)
Narendra Muppalla1b0b3352015-09-29 10:16:51 -07003507{
Clarence Ipaa0faf42016-05-30 12:07:48 -04003508 struct sde_plane *psde;
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04003509 struct sde_plane_state *pstate;
Clarence Ip730e7192016-06-26 22:45:09 -04003510 struct sde_plane_state *old_state;
Clarence Ip17e908b2016-09-29 15:58:00 -04003511 uint64_t input_fence_default;
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04003512
Clarence Ip13a8cf42016-09-29 17:27:47 -04003513 if (!plane) {
3514 SDE_ERROR("invalid plane\n");
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04003515 return NULL;
Clarence Ip13a8cf42016-09-29 17:27:47 -04003516 } else if (!plane->state) {
3517 SDE_ERROR("invalid plane state\n");
3518 return NULL;
3519 }
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04003520
Clarence Ip730e7192016-06-26 22:45:09 -04003521 old_state = to_sde_plane_state(plane->state);
Clarence Ipaa0faf42016-05-30 12:07:48 -04003522 psde = to_sde_plane(plane);
3523 pstate = msm_property_alloc_state(&psde->property_info);
Clarence Ip13a8cf42016-09-29 17:27:47 -04003524 if (!pstate) {
3525 SDE_ERROR_PLANE(psde, "failed to allocate state\n");
Clarence Ip730e7192016-06-26 22:45:09 -04003526 return NULL;
Clarence Ip13a8cf42016-09-29 17:27:47 -04003527 }
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04003528
Clarence Ip13a8cf42016-09-29 17:27:47 -04003529 SDE_DEBUG_PLANE(psde, "\n");
Clarence Ipaa0faf42016-05-30 12:07:48 -04003530
3531 /* duplicate value helper */
3532 msm_property_duplicate_state(&psde->property_info, old_state, pstate,
3533 pstate->property_values, pstate->property_blobs);
Clarence Ipae4e60c2016-06-26 22:44:04 -04003534
Clarence Ip730e7192016-06-26 22:45:09 -04003535 /* add ref count for frame buffer */
3536 if (pstate->base.fb)
3537 drm_framebuffer_reference(pstate->base.fb);
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04003538
Clarence Ip17e908b2016-09-29 15:58:00 -04003539 /* clear out any input fence */
3540 pstate->input_fence = 0;
3541 input_fence_default = msm_property_get_default(
3542 &psde->property_info, PLANE_PROP_INPUT_FENCE);
3543 msm_property_set_property(&psde->property_info, pstate->property_values,
3544 PLANE_PROP_INPUT_FENCE, input_fence_default);
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04003545
Clarence Ip282dad62016-09-27 17:07:35 -04003546 pstate->dirty = 0x0;
Clarence Ip730e7192016-06-26 22:45:09 -04003547 pstate->pending = false;
3548
Alan Kwong4dd64c82017-02-04 18:41:51 -08003549 sde_plane_rot_duplicate_state(plane, &pstate->base);
3550
Clarence Ip730e7192016-06-26 22:45:09 -04003551 return &pstate->base;
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04003552}
3553
3554static void sde_plane_reset(struct drm_plane *plane)
3555{
Clarence Ipae4e60c2016-06-26 22:44:04 -04003556 struct sde_plane *psde;
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04003557 struct sde_plane_state *pstate;
3558
Clarence Ipae4e60c2016-06-26 22:44:04 -04003559 if (!plane) {
Dhaval Patel47302cf2016-08-18 15:04:28 -07003560 SDE_ERROR("invalid plane\n");
Clarence Ipae4e60c2016-06-26 22:44:04 -04003561 return;
3562 }
3563
Clarence Ip730e7192016-06-26 22:45:09 -04003564 psde = to_sde_plane(plane);
Clarence Ip13a8cf42016-09-29 17:27:47 -04003565 SDE_DEBUG_PLANE(psde, "\n");
Clarence Ip730e7192016-06-26 22:45:09 -04003566
Clarence Ipae4e60c2016-06-26 22:44:04 -04003567 /* remove previous state, if present */
Clarence Ipaa0faf42016-05-30 12:07:48 -04003568 if (plane->state) {
Clarence Ipae4e60c2016-06-26 22:44:04 -04003569 sde_plane_destroy_state(plane, plane->state);
Clarence Ipaa0faf42016-05-30 12:07:48 -04003570 plane->state = 0;
Clarence Ipae4e60c2016-06-26 22:44:04 -04003571 }
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04003572
Clarence Ipaa0faf42016-05-30 12:07:48 -04003573 pstate = msm_property_alloc_state(&psde->property_info);
Clarence Ip13a8cf42016-09-29 17:27:47 -04003574 if (!pstate) {
3575 SDE_ERROR_PLANE(psde, "failed to allocate state\n");
Clarence Ipaa0faf42016-05-30 12:07:48 -04003576 return;
Clarence Ip13a8cf42016-09-29 17:27:47 -04003577 }
Clarence Ip730e7192016-06-26 22:45:09 -04003578
Clarence Ipaa0faf42016-05-30 12:07:48 -04003579 /* reset value helper */
3580 msm_property_reset_state(&psde->property_info, pstate,
3581 pstate->property_values, pstate->property_blobs);
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04003582
3583 pstate->base.plane = plane;
3584
3585 plane->state = &pstate->base;
Narendra Muppalla1b0b3352015-09-29 10:16:51 -07003586}
3587
Lloyd Atkinsonb020e0f2017-03-14 08:05:18 -07003588#ifdef CONFIG_DEBUG_FS
Alan Kwongf0fd8512016-10-24 21:39:26 -04003589static ssize_t _sde_plane_danger_read(struct file *file,
3590 char __user *buff, size_t count, loff_t *ppos)
3591{
3592 struct sde_kms *kms = file->private_data;
3593 struct sde_mdss_cfg *cfg = kms->catalog;
3594 int len = 0;
3595 char buf[40] = {'\0'};
3596
3597 if (!cfg)
3598 return -ENODEV;
3599
3600 if (*ppos)
3601 return 0; /* the end */
3602
3603 len = snprintf(buf, sizeof(buf), "%d\n", !kms->has_danger_ctrl);
3604 if (len < 0 || len >= sizeof(buf))
3605 return 0;
3606
3607 if ((count < sizeof(buf)) || copy_to_user(buff, buf, len))
3608 return -EFAULT;
3609
3610 *ppos += len; /* increase offset */
3611
3612 return len;
3613}
3614
3615static void _sde_plane_set_danger_state(struct sde_kms *kms, bool enable)
3616{
3617 struct drm_plane *plane;
3618
3619 drm_for_each_plane(plane, kms->dev) {
3620 if (plane->fb && plane->state) {
3621 sde_plane_danger_signal_ctrl(plane, enable);
3622 SDE_DEBUG("plane:%d img:%dx%d ",
3623 plane->base.id, plane->fb->width,
3624 plane->fb->height);
3625 SDE_DEBUG("src[%d,%d,%d,%d] dst[%d,%d,%d,%d]\n",
3626 plane->state->src_x >> 16,
3627 plane->state->src_y >> 16,
3628 plane->state->src_w >> 16,
3629 plane->state->src_h >> 16,
3630 plane->state->crtc_x, plane->state->crtc_y,
3631 plane->state->crtc_w, plane->state->crtc_h);
3632 } else {
3633 SDE_DEBUG("Inactive plane:%d\n", plane->base.id);
3634 }
3635 }
3636}
3637
3638static ssize_t _sde_plane_danger_write(struct file *file,
3639 const char __user *user_buf, size_t count, loff_t *ppos)
3640{
3641 struct sde_kms *kms = file->private_data;
3642 struct sde_mdss_cfg *cfg = kms->catalog;
3643 int disable_panic;
3644 char buf[10];
3645
3646 if (!cfg)
3647 return -EFAULT;
3648
3649 if (count >= sizeof(buf))
3650 return -EFAULT;
3651
3652 if (copy_from_user(buf, user_buf, count))
3653 return -EFAULT;
3654
3655 buf[count] = 0; /* end of string */
3656
3657 if (kstrtoint(buf, 0, &disable_panic))
3658 return -EFAULT;
3659
3660 if (disable_panic) {
3661 /* Disable panic signal for all active pipes */
3662 SDE_DEBUG("Disabling danger:\n");
3663 _sde_plane_set_danger_state(kms, false);
3664 kms->has_danger_ctrl = false;
3665 } else {
3666 /* Enable panic signal for all active pipes */
3667 SDE_DEBUG("Enabling danger:\n");
3668 kms->has_danger_ctrl = true;
3669 _sde_plane_set_danger_state(kms, true);
3670 }
3671
3672 return count;
3673}
3674
3675static const struct file_operations sde_plane_danger_enable = {
3676 .open = simple_open,
3677 .read = _sde_plane_danger_read,
3678 .write = _sde_plane_danger_write,
3679};
3680
Lloyd Atkinsonb020e0f2017-03-14 08:05:18 -07003681static int _sde_plane_init_debugfs(struct drm_plane *plane)
Clarence Ip4ce59322016-06-26 22:27:51 -04003682{
Lloyd Atkinsonb020e0f2017-03-14 08:05:18 -07003683 struct sde_plane *psde;
3684 struct sde_kms *kms;
3685 struct msm_drm_private *priv;
Clarence Ip4ce59322016-06-26 22:27:51 -04003686 const struct sde_sspp_sub_blks *sblk = 0;
3687 const struct sde_sspp_cfg *cfg = 0;
3688
Lloyd Atkinsonb020e0f2017-03-14 08:05:18 -07003689 if (!plane || !plane->dev) {
3690 SDE_ERROR("invalid arguments\n");
3691 return -EINVAL;
3692 }
3693
3694 priv = plane->dev->dev_private;
3695 if (!priv || !priv->kms) {
3696 SDE_ERROR("invalid KMS reference\n");
3697 return -EINVAL;
3698 }
3699
3700 kms = to_sde_kms(priv->kms);
3701 psde = to_sde_plane(plane);
3702
Clarence Ip4ce59322016-06-26 22:27:51 -04003703 if (psde && psde->pipe_hw)
3704 cfg = psde->pipe_hw->cap;
3705 if (cfg)
3706 sblk = cfg->sblk;
3707
Lloyd Atkinsonb020e0f2017-03-14 08:05:18 -07003708 if (!sblk)
3709 return 0;
Clarence Ip4ce59322016-06-26 22:27:51 -04003710
Lloyd Atkinsonb020e0f2017-03-14 08:05:18 -07003711 /* create overall sub-directory for the pipe */
3712 psde->debugfs_root =
3713 debugfs_create_dir(psde->pipe_name,
3714 sde_debugfs_get_root(kms));
Clarence Ip4ce59322016-06-26 22:27:51 -04003715
Lloyd Atkinsonb020e0f2017-03-14 08:05:18 -07003716 if (!psde->debugfs_root)
3717 return -ENOMEM;
Clarence Ip4ce59322016-06-26 22:27:51 -04003718
Lloyd Atkinsonb020e0f2017-03-14 08:05:18 -07003719 /* don't error check these */
3720 debugfs_create_x32("features", 0644,
3721 psde->debugfs_root, &psde->features);
Alan Kwongf0fd8512016-10-24 21:39:26 -04003722
Lloyd Atkinsonb020e0f2017-03-14 08:05:18 -07003723 /* add register dump support */
3724 sde_debugfs_setup_regset32(&psde->debugfs_src,
3725 sblk->src_blk.base + cfg->base,
3726 sblk->src_blk.len,
3727 kms);
3728 sde_debugfs_create_regset32("src_blk", 0444,
3729 psde->debugfs_root, &psde->debugfs_src);
Alan Kwongf0fd8512016-10-24 21:39:26 -04003730
Lloyd Atkinsonb020e0f2017-03-14 08:05:18 -07003731 if (cfg->features & BIT(SDE_SSPP_SCALER_QSEED3) ||
3732 cfg->features & BIT(SDE_SSPP_SCALER_QSEED2)) {
3733 sde_debugfs_setup_regset32(&psde->debugfs_scaler,
3734 sblk->scaler_blk.base + cfg->base,
3735 sblk->scaler_blk.len,
3736 kms);
3737 sde_debugfs_create_regset32("scaler_blk", 0444,
3738 psde->debugfs_root,
3739 &psde->debugfs_scaler);
Clarence Ip716ab662017-03-20 06:51:24 -07003740 debugfs_create_bool("default_scaling",
3741 0644,
3742 psde->debugfs_root,
3743 &psde->debugfs_default_scale);
Clarence Ip4ce59322016-06-26 22:27:51 -04003744 }
Lloyd Atkinsonb020e0f2017-03-14 08:05:18 -07003745
3746 if (cfg->features & BIT(SDE_SSPP_CSC) ||
3747 cfg->features & BIT(SDE_SSPP_CSC_10BIT)) {
3748 sde_debugfs_setup_regset32(&psde->debugfs_csc,
3749 sblk->csc_blk.base + cfg->base,
3750 sblk->csc_blk.len,
3751 kms);
3752 sde_debugfs_create_regset32("csc_blk", 0444,
3753 psde->debugfs_root, &psde->debugfs_csc);
3754 }
3755
3756 debugfs_create_u32("xin_id",
3757 0444,
3758 psde->debugfs_root,
3759 (u32 *) &cfg->xin_id);
3760 debugfs_create_u32("clk_ctrl",
3761 0444,
3762 psde->debugfs_root,
3763 (u32 *) &cfg->clk_ctrl);
3764 debugfs_create_x32("creq_vblank",
3765 0644,
3766 psde->debugfs_root,
3767 (u32 *) &sblk->creq_vblank);
3768 debugfs_create_x32("danger_vblank",
3769 0644,
3770 psde->debugfs_root,
3771 (u32 *) &sblk->danger_vblank);
3772
3773 debugfs_create_file("disable_danger",
3774 0644,
3775 psde->debugfs_root,
3776 kms, &sde_plane_danger_enable);
Alan Kwong4dd64c82017-02-04 18:41:51 -08003777 debugfs_create_u32("sbuf_mode",
3778 0644,
3779 psde->debugfs_root, &psde->sbuf_mode);
3780 debugfs_create_u32("sbuf_writeback",
3781 0644,
3782 psde->debugfs_root,
3783 &psde->sbuf_writeback);
Lloyd Atkinsonb020e0f2017-03-14 08:05:18 -07003784
3785 return 0;
3786}
3787
3788static void _sde_plane_destroy_debugfs(struct drm_plane *plane)
3789{
3790 struct sde_plane *psde;
3791
3792 if (!plane)
3793 return;
3794 psde = to_sde_plane(plane);
3795
3796 debugfs_remove_recursive(psde->debugfs_root);
3797}
3798#else
3799static int _sde_plane_init_debugfs(struct drm_plane *plane)
3800{
3801 return 0;
3802}
3803static void _sde_plane_destroy_debugfs(struct drm_plane *plane)
3804{
3805}
3806#endif
3807
3808static int sde_plane_late_register(struct drm_plane *plane)
3809{
3810 return _sde_plane_init_debugfs(plane);
3811}
3812
3813static void sde_plane_early_unregister(struct drm_plane *plane)
3814{
3815 _sde_plane_destroy_debugfs(plane);
3816}
3817
3818static const struct drm_plane_funcs sde_plane_funcs = {
3819 .update_plane = drm_atomic_helper_update_plane,
3820 .disable_plane = drm_atomic_helper_disable_plane,
3821 .destroy = sde_plane_destroy,
3822 .set_property = sde_plane_set_property,
3823 .atomic_set_property = sde_plane_atomic_set_property,
3824 .atomic_get_property = sde_plane_atomic_get_property,
3825 .reset = sde_plane_reset,
3826 .atomic_duplicate_state = sde_plane_duplicate_state,
3827 .atomic_destroy_state = sde_plane_destroy_state,
3828 .late_register = sde_plane_late_register,
3829 .early_unregister = sde_plane_early_unregister,
3830};
3831
3832static const struct drm_plane_helper_funcs sde_plane_helper_funcs = {
3833 .prepare_fb = sde_plane_prepare_fb,
3834 .cleanup_fb = sde_plane_cleanup_fb,
3835 .atomic_check = sde_plane_atomic_check,
3836 .atomic_update = sde_plane_atomic_update,
3837};
3838
3839enum sde_sspp sde_plane_pipe(struct drm_plane *plane)
3840{
3841 return plane ? to_sde_plane(plane)->pipe : SSPP_NONE;
3842}
3843
3844bool is_sde_plane_virtual(struct drm_plane *plane)
3845{
3846 return plane ? to_sde_plane(plane)->is_virtual : false;
Clarence Ip4ce59322016-06-26 22:27:51 -04003847}
3848
Narendra Muppalla1b0b3352015-09-29 10:16:51 -07003849/* initialize plane */
Clarence Ipe78efb72016-06-24 18:35:21 -04003850struct drm_plane *sde_plane_init(struct drm_device *dev,
Clarence Ip2bbf7b32016-09-23 15:07:16 -04003851 uint32_t pipe, bool primary_plane,
Jeykumar Sankaran2e655032017-02-04 14:05:45 -08003852 unsigned long possible_crtcs, u32 master_plane_id)
Narendra Muppalla1b0b3352015-09-29 10:16:51 -07003853{
3854 struct drm_plane *plane = NULL;
Jeykumar Sankaran2e655032017-02-04 14:05:45 -08003855 const struct sde_format_extended *format_list;
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04003856 struct sde_plane *psde;
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04003857 struct msm_drm_private *priv;
3858 struct sde_kms *kms;
Narendra Muppalla1b0b3352015-09-29 10:16:51 -07003859 enum drm_plane_type type;
Clarence Ipc47a0692016-10-11 10:54:17 -04003860 int ret = -EINVAL;
Clarence Ip4c1d9772016-06-26 09:35:38 -04003861
3862 if (!dev) {
Dhaval Patel47302cf2016-08-18 15:04:28 -07003863 SDE_ERROR("[%u]device is NULL\n", pipe);
Clarence Ip4c1d9772016-06-26 09:35:38 -04003864 goto exit;
3865 }
Narendra Muppalla1b0b3352015-09-29 10:16:51 -07003866
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04003867 priv = dev->dev_private;
Ben Chan78647cd2016-06-26 22:02:47 -04003868 if (!priv) {
Dhaval Patel47302cf2016-08-18 15:04:28 -07003869 SDE_ERROR("[%u]private data is NULL\n", pipe);
Ben Chan78647cd2016-06-26 22:02:47 -04003870 goto exit;
3871 }
3872
3873 if (!priv->kms) {
Dhaval Patel47302cf2016-08-18 15:04:28 -07003874 SDE_ERROR("[%u]invalid KMS reference\n", pipe);
Ben Chan78647cd2016-06-26 22:02:47 -04003875 goto exit;
3876 }
3877 kms = to_sde_kms(priv->kms);
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04003878
Clarence Ip4c1d9772016-06-26 09:35:38 -04003879 if (!kms->catalog) {
Dhaval Patel47302cf2016-08-18 15:04:28 -07003880 SDE_ERROR("[%u]invalid catalog reference\n", pipe);
Clarence Ip4c1d9772016-06-26 09:35:38 -04003881 goto exit;
3882 }
3883
Clarence Ip4ce59322016-06-26 22:27:51 -04003884 /* create and zero local structure */
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04003885 psde = kzalloc(sizeof(*psde), GFP_KERNEL);
3886 if (!psde) {
Dhaval Patel47302cf2016-08-18 15:04:28 -07003887 SDE_ERROR("[%u]failed to allocate local plane struct\n", pipe);
Narendra Muppalla1b0b3352015-09-29 10:16:51 -07003888 ret = -ENOMEM;
Clarence Ip4c1d9772016-06-26 09:35:38 -04003889 goto exit;
Narendra Muppalla1b0b3352015-09-29 10:16:51 -07003890 }
3891
Clarence Ip4c1d9772016-06-26 09:35:38 -04003892 /* cache local stuff for later */
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04003893 plane = &psde->base;
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04003894 psde->pipe = pipe;
Alan Kwong112a84f2016-05-24 20:49:21 -04003895 psde->mmu_id = kms->mmu_id[MSM_SMMU_DOMAIN_UNSECURE];
Jeykumar Sankaran2e655032017-02-04 14:05:45 -08003896 psde->is_virtual = (master_plane_id != 0);
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04003897
Clarence Ip4c1d9772016-06-26 09:35:38 -04003898 /* initialize underlying h/w driver */
3899 psde->pipe_hw = sde_hw_sspp_init(pipe, kms->mmio, kms->catalog);
3900 if (IS_ERR(psde->pipe_hw)) {
Dhaval Patel47302cf2016-08-18 15:04:28 -07003901 SDE_ERROR("[%u]SSPP init failed\n", pipe);
Clarence Ip4c1d9772016-06-26 09:35:38 -04003902 ret = PTR_ERR(psde->pipe_hw);
3903 goto clean_plane;
3904 } else if (!psde->pipe_hw->cap || !psde->pipe_hw->cap->sblk) {
Dhaval Patel47302cf2016-08-18 15:04:28 -07003905 SDE_ERROR("[%u]SSPP init returned invalid cfg\n", pipe);
Clarence Ip4c1d9772016-06-26 09:35:38 -04003906 goto clean_sspp;
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04003907 }
Clarence Ip4c1d9772016-06-26 09:35:38 -04003908
3909 /* cache features mask for later */
3910 psde->features = psde->pipe_hw->cap->features;
3911 psde->pipe_sblk = psde->pipe_hw->cap->sblk;
Clarence Ipea3d6262016-07-15 16:20:11 -04003912 if (!psde->pipe_sblk) {
Clarence Ip13a8cf42016-09-29 17:27:47 -04003913 SDE_ERROR("[%u]invalid sblk\n", pipe);
Clarence Ipea3d6262016-07-15 16:20:11 -04003914 goto clean_sspp;
3915 }
Clarence Ip4c1d9772016-06-26 09:35:38 -04003916
abeykun48f407a2016-08-25 12:06:44 -04003917 if (psde->features & BIT(SDE_SSPP_SCALER_QSEED3)) {
3918 psde->scaler3_cfg = kzalloc(sizeof(struct sde_hw_scaler3_cfg),
3919 GFP_KERNEL);
3920 if (!psde->scaler3_cfg) {
3921 SDE_ERROR("[%u]failed to allocate scale struct\n",
3922 pipe);
3923 ret = -ENOMEM;
3924 goto clean_sspp;
3925 }
3926 }
3927
Jeykumar Sankaran2e655032017-02-04 14:05:45 -08003928 format_list = psde->pipe_sblk->format_list;
3929
3930 if (master_plane_id)
3931 format_list = plane_formats;
3932
3933 psde->nformats = sde_populate_formats(plane_formats,
3934 psde->formats,
3935 0,
3936 ARRAY_SIZE(psde->formats));
Narendra Muppalla1b0b3352015-09-29 10:16:51 -07003937
Clarence Ip4c1d9772016-06-26 09:35:38 -04003938 if (!psde->nformats) {
Dhaval Patel47302cf2016-08-18 15:04:28 -07003939 SDE_ERROR("[%u]no valid formats for plane\n", pipe);
Clarence Ip4c1d9772016-06-26 09:35:38 -04003940 goto clean_sspp;
3941 }
3942
3943 if (psde->features & BIT(SDE_SSPP_CURSOR))
3944 type = DRM_PLANE_TYPE_CURSOR;
3945 else if (primary_plane)
3946 type = DRM_PLANE_TYPE_PRIMARY;
3947 else
3948 type = DRM_PLANE_TYPE_OVERLAY;
Dhaval Patel04c7e8e2016-09-26 20:14:31 -07003949 ret = drm_universal_plane_init(dev, plane, 0xff, &sde_plane_funcs,
3950 psde->formats, psde->nformats,
3951 type, NULL);
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04003952 if (ret)
Clarence Ip4c1d9772016-06-26 09:35:38 -04003953 goto clean_sspp;
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04003954
Clarence Ip4c1d9772016-06-26 09:35:38 -04003955 /* success! finalize initialization */
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04003956 drm_plane_helper_add(plane, &sde_plane_helper_funcs);
Narendra Muppalla1b0b3352015-09-29 10:16:51 -07003957
Clarence Ipaa0faf42016-05-30 12:07:48 -04003958 msm_property_init(&psde->property_info, &plane->base, dev,
3959 priv->plane_property, psde->property_data,
3960 PLANE_PROP_COUNT, PLANE_PROP_BLOBCOUNT,
3961 sizeof(struct sde_plane_state));
3962
Jeykumar Sankaran2e655032017-02-04 14:05:45 -08003963 _sde_plane_install_properties(plane, kms->catalog, master_plane_id);
Clarence Ip5e2a9222016-06-26 22:38:24 -04003964
Clarence Ip4ce59322016-06-26 22:27:51 -04003965 /* save user friendly pipe name for later */
Clarence Ip5e2a9222016-06-26 22:38:24 -04003966 snprintf(psde->pipe_name, SDE_NAME_SIZE, "plane%u", plane->base.id);
Clarence Ip4ce59322016-06-26 22:27:51 -04003967
Clarence Ip730e7192016-06-26 22:45:09 -04003968 mutex_init(&psde->lock);
3969
Dhaval Patel82c8dbc2017-02-18 23:15:10 -08003970 SDE_DEBUG("%s created for pipe %u\n", psde->pipe_name, pipe);
Narendra Muppalla1b0b3352015-09-29 10:16:51 -07003971 return plane;
3972
Clarence Ip4c1d9772016-06-26 09:35:38 -04003973clean_sspp:
3974 if (psde && psde->pipe_hw)
3975 sde_hw_sspp_destroy(psde->pipe_hw);
abeykun48f407a2016-08-25 12:06:44 -04003976
3977 if (psde && psde->scaler3_cfg)
3978 kfree(psde->scaler3_cfg);
Clarence Ip4c1d9772016-06-26 09:35:38 -04003979clean_plane:
3980 kfree(psde);
Ben Chan78647cd2016-06-26 22:02:47 -04003981exit:
Narendra Muppalla1b0b3352015-09-29 10:16:51 -07003982 return ERR_PTR(ret);
3983}