Russell King | f27ecac | 2005-08-18 21:31:00 +0100 | [diff] [blame] | 1 | /* |
Russell King | f27ecac | 2005-08-18 21:31:00 +0100 | [diff] [blame] | 2 | * Copyright (C) 2002 ARM Limited, All Rights Reserved. |
| 3 | * |
| 4 | * This program is free software; you can redistribute it and/or modify |
| 5 | * it under the terms of the GNU General Public License version 2 as |
| 6 | * published by the Free Software Foundation. |
| 7 | * |
| 8 | * Interrupt architecture for the GIC: |
| 9 | * |
| 10 | * o There is one Interrupt Distributor, which receives interrupts |
| 11 | * from system devices and sends them to the Interrupt Controllers. |
| 12 | * |
| 13 | * o There is one CPU Interface per CPU, which sends interrupts sent |
| 14 | * by the Distributor, and interrupts generated locally, to the |
Catalin Marinas | b3a1bde | 2007-02-14 19:14:56 +0100 | [diff] [blame] | 15 | * associated CPU. The base address of the CPU interface is usually |
| 16 | * aliased so that the same address points to different chips depending |
| 17 | * on the CPU it is accessed from. |
Russell King | f27ecac | 2005-08-18 21:31:00 +0100 | [diff] [blame] | 18 | * |
| 19 | * Note that IRQs 0-31 are special - they are local to each CPU. |
| 20 | * As such, the enable set/clear, pending set/clear and active bit |
| 21 | * registers are banked per-cpu for these sources. |
| 22 | */ |
| 23 | #include <linux/init.h> |
| 24 | #include <linux/kernel.h> |
Rob Herring | f37a53c | 2011-10-21 17:14:27 -0500 | [diff] [blame] | 25 | #include <linux/err.h> |
Arnd Bergmann | 7e1efcf | 2011-11-01 00:28:37 +0100 | [diff] [blame] | 26 | #include <linux/module.h> |
Russell King | f27ecac | 2005-08-18 21:31:00 +0100 | [diff] [blame] | 27 | #include <linux/list.h> |
| 28 | #include <linux/smp.h> |
Catalin Marinas | c011470 | 2013-01-14 18:05:37 +0000 | [diff] [blame] | 29 | #include <linux/cpu.h> |
Colin Cross | 254056f | 2011-02-10 12:54:10 -0800 | [diff] [blame] | 30 | #include <linux/cpu_pm.h> |
Catalin Marinas | dcb86e8 | 2005-08-31 21:45:14 +0100 | [diff] [blame] | 31 | #include <linux/cpumask.h> |
Russell King | fced80c | 2008-09-06 12:10:45 +0100 | [diff] [blame] | 32 | #include <linux/io.h> |
Rob Herring | b3f7ed0 | 2011-09-28 21:27:52 -0500 | [diff] [blame] | 33 | #include <linux/of.h> |
| 34 | #include <linux/of_address.h> |
| 35 | #include <linux/of_irq.h> |
Tomasz Nowicki | d60fc38 | 2015-03-24 14:02:49 +0000 | [diff] [blame] | 36 | #include <linux/acpi.h> |
Rob Herring | 4294f8ba | 2011-09-28 21:25:31 -0500 | [diff] [blame] | 37 | #include <linux/irqdomain.h> |
Marc Zyngier | 292b293 | 2011-07-20 16:24:14 +0100 | [diff] [blame] | 38 | #include <linux/interrupt.h> |
| 39 | #include <linux/percpu.h> |
| 40 | #include <linux/slab.h> |
Joel Porquet | 41a83e0 | 2015-07-07 17:11:46 -0400 | [diff] [blame] | 41 | #include <linux/irqchip.h> |
Catalin Marinas | de88cbb | 2013-01-18 15:31:37 +0000 | [diff] [blame] | 42 | #include <linux/irqchip/chained_irq.h> |
Rob Herring | 520f7bd | 2012-12-27 13:10:24 -0600 | [diff] [blame] | 43 | #include <linux/irqchip/arm-gic.h> |
Tomasz Nowicki | d60fc38 | 2015-03-24 14:02:49 +0000 | [diff] [blame] | 44 | #include <linux/irqchip/arm-gic-acpi.h> |
Russell King | f27ecac | 2005-08-18 21:31:00 +0100 | [diff] [blame] | 45 | |
Tomasz Figa | 29e697b | 2014-07-17 17:23:44 +0200 | [diff] [blame] | 46 | #include <asm/cputype.h> |
Russell King | f27ecac | 2005-08-18 21:31:00 +0100 | [diff] [blame] | 47 | #include <asm/irq.h> |
Marc Zyngier | 562e002 | 2011-09-06 09:56:17 +0100 | [diff] [blame] | 48 | #include <asm/exception.h> |
Will Deacon | eb50439 | 2012-01-20 12:01:12 +0100 | [diff] [blame] | 49 | #include <asm/smp_plat.h> |
Marc Zyngier | 0b996fd | 2015-08-26 17:00:44 +0100 | [diff] [blame] | 50 | #include <asm/virt.h> |
Russell King | f27ecac | 2005-08-18 21:31:00 +0100 | [diff] [blame] | 51 | |
Marc Zyngier | d51d0af | 2014-06-30 16:01:30 +0100 | [diff] [blame] | 52 | #include "irq-gic-common.h" |
Russell King | f27ecac | 2005-08-18 21:31:00 +0100 | [diff] [blame] | 53 | |
Marc Zyngier | 76e52dd | 2015-09-30 12:01:16 +0100 | [diff] [blame] | 54 | #ifdef CONFIG_ARM64 |
| 55 | #include <asm/cpufeature.h> |
| 56 | |
| 57 | static void gic_check_cpu_features(void) |
| 58 | { |
| 59 | WARN_TAINT_ONCE(cpus_have_cap(ARM64_HAS_SYSREG_GIC_CPUIF), |
| 60 | TAINT_CPU_OUT_OF_SPEC, |
| 61 | "GICv3 system registers enabled, broken firmware!\n"); |
| 62 | } |
| 63 | #else |
| 64 | #define gic_check_cpu_features() do { } while(0) |
| 65 | #endif |
| 66 | |
Marc Zyngier | db0d4db | 2011-11-12 16:09:49 +0000 | [diff] [blame] | 67 | union gic_base { |
| 68 | void __iomem *common_base; |
Stephen Boyd | 6859358 | 2014-03-04 17:02:01 -0800 | [diff] [blame] | 69 | void __percpu * __iomem *percpu_base; |
Marc Zyngier | db0d4db | 2011-11-12 16:09:49 +0000 | [diff] [blame] | 70 | }; |
| 71 | |
| 72 | struct gic_chip_data { |
Marc Zyngier | db0d4db | 2011-11-12 16:09:49 +0000 | [diff] [blame] | 73 | union gic_base dist_base; |
| 74 | union gic_base cpu_base; |
| 75 | #ifdef CONFIG_CPU_PM |
| 76 | u32 saved_spi_enable[DIV_ROUND_UP(1020, 32)]; |
| 77 | u32 saved_spi_conf[DIV_ROUND_UP(1020, 16)]; |
| 78 | u32 saved_spi_target[DIV_ROUND_UP(1020, 4)]; |
| 79 | u32 __percpu *saved_ppi_enable; |
| 80 | u32 __percpu *saved_ppi_conf; |
| 81 | #endif |
Grant Likely | 7529495 | 2012-02-14 14:06:57 -0700 | [diff] [blame] | 82 | struct irq_domain *domain; |
Marc Zyngier | db0d4db | 2011-11-12 16:09:49 +0000 | [diff] [blame] | 83 | unsigned int gic_irqs; |
| 84 | #ifdef CONFIG_GIC_NON_BANKED |
| 85 | void __iomem *(*get_base)(union gic_base *); |
| 86 | #endif |
| 87 | }; |
| 88 | |
Thomas Gleixner | bd31b85 | 2009-07-03 08:44:46 -0500 | [diff] [blame] | 89 | static DEFINE_RAW_SPINLOCK(irq_controller_lock); |
Russell King | f27ecac | 2005-08-18 21:31:00 +0100 | [diff] [blame] | 90 | |
Santosh Shilimkar | d7ed36a | 2011-03-02 08:03:22 +0100 | [diff] [blame] | 91 | /* |
Nicolas Pitre | 384a290 | 2012-04-11 18:55:48 -0400 | [diff] [blame] | 92 | * The GIC mapping of CPU interfaces does not necessarily match |
| 93 | * the logical CPU numbering. Let's use a mapping as returned |
| 94 | * by the GIC itself. |
| 95 | */ |
| 96 | #define NR_GIC_CPU_IF 8 |
| 97 | static u8 gic_cpu_map[NR_GIC_CPU_IF] __read_mostly; |
| 98 | |
Marc Zyngier | 0b996fd | 2015-08-26 17:00:44 +0100 | [diff] [blame] | 99 | static struct static_key supports_deactivate = STATIC_KEY_INIT_TRUE; |
| 100 | |
Catalin Marinas | b3a1bde | 2007-02-14 19:14:56 +0100 | [diff] [blame] | 101 | #ifndef MAX_GIC_NR |
| 102 | #define MAX_GIC_NR 1 |
| 103 | #endif |
| 104 | |
Russell King | bef8f9e | 2010-12-04 16:50:58 +0000 | [diff] [blame] | 105 | static struct gic_chip_data gic_data[MAX_GIC_NR] __read_mostly; |
Catalin Marinas | b3a1bde | 2007-02-14 19:14:56 +0100 | [diff] [blame] | 106 | |
Marc Zyngier | db0d4db | 2011-11-12 16:09:49 +0000 | [diff] [blame] | 107 | #ifdef CONFIG_GIC_NON_BANKED |
| 108 | static void __iomem *gic_get_percpu_base(union gic_base *base) |
| 109 | { |
Christoph Lameter | 513d1a2 | 2014-09-02 10:00:07 -0500 | [diff] [blame] | 110 | return raw_cpu_read(*base->percpu_base); |
Marc Zyngier | db0d4db | 2011-11-12 16:09:49 +0000 | [diff] [blame] | 111 | } |
| 112 | |
| 113 | static void __iomem *gic_get_common_base(union gic_base *base) |
| 114 | { |
| 115 | return base->common_base; |
| 116 | } |
| 117 | |
| 118 | static inline void __iomem *gic_data_dist_base(struct gic_chip_data *data) |
| 119 | { |
| 120 | return data->get_base(&data->dist_base); |
| 121 | } |
| 122 | |
| 123 | static inline void __iomem *gic_data_cpu_base(struct gic_chip_data *data) |
| 124 | { |
| 125 | return data->get_base(&data->cpu_base); |
| 126 | } |
| 127 | |
| 128 | static inline void gic_set_base_accessor(struct gic_chip_data *data, |
| 129 | void __iomem *(*f)(union gic_base *)) |
| 130 | { |
| 131 | data->get_base = f; |
| 132 | } |
| 133 | #else |
| 134 | #define gic_data_dist_base(d) ((d)->dist_base.common_base) |
| 135 | #define gic_data_cpu_base(d) ((d)->cpu_base.common_base) |
Sachin Kamat | 46f101d | 2013-03-13 15:05:15 +0530 | [diff] [blame] | 136 | #define gic_set_base_accessor(d, f) |
Marc Zyngier | db0d4db | 2011-11-12 16:09:49 +0000 | [diff] [blame] | 137 | #endif |
| 138 | |
Lennert Buytenhek | 7d1f428 | 2010-11-29 10:18:20 +0100 | [diff] [blame] | 139 | static inline void __iomem *gic_dist_base(struct irq_data *d) |
Catalin Marinas | b3a1bde | 2007-02-14 19:14:56 +0100 | [diff] [blame] | 140 | { |
Lennert Buytenhek | 7d1f428 | 2010-11-29 10:18:20 +0100 | [diff] [blame] | 141 | struct gic_chip_data *gic_data = irq_data_get_irq_chip_data(d); |
Marc Zyngier | db0d4db | 2011-11-12 16:09:49 +0000 | [diff] [blame] | 142 | return gic_data_dist_base(gic_data); |
Catalin Marinas | b3a1bde | 2007-02-14 19:14:56 +0100 | [diff] [blame] | 143 | } |
| 144 | |
Lennert Buytenhek | 7d1f428 | 2010-11-29 10:18:20 +0100 | [diff] [blame] | 145 | static inline void __iomem *gic_cpu_base(struct irq_data *d) |
Catalin Marinas | b3a1bde | 2007-02-14 19:14:56 +0100 | [diff] [blame] | 146 | { |
Lennert Buytenhek | 7d1f428 | 2010-11-29 10:18:20 +0100 | [diff] [blame] | 147 | struct gic_chip_data *gic_data = irq_data_get_irq_chip_data(d); |
Marc Zyngier | db0d4db | 2011-11-12 16:09:49 +0000 | [diff] [blame] | 148 | return gic_data_cpu_base(gic_data); |
Catalin Marinas | b3a1bde | 2007-02-14 19:14:56 +0100 | [diff] [blame] | 149 | } |
| 150 | |
Lennert Buytenhek | 7d1f428 | 2010-11-29 10:18:20 +0100 | [diff] [blame] | 151 | static inline unsigned int gic_irq(struct irq_data *d) |
Catalin Marinas | b3a1bde | 2007-02-14 19:14:56 +0100 | [diff] [blame] | 152 | { |
Rob Herring | 4294f8ba | 2011-09-28 21:25:31 -0500 | [diff] [blame] | 153 | return d->hwirq; |
Catalin Marinas | b3a1bde | 2007-02-14 19:14:56 +0100 | [diff] [blame] | 154 | } |
| 155 | |
Marc Zyngier | 01f779f | 2015-08-26 17:00:45 +0100 | [diff] [blame] | 156 | static inline bool cascading_gic_irq(struct irq_data *d) |
| 157 | { |
| 158 | void *data = irq_data_get_irq_handler_data(d); |
| 159 | |
| 160 | /* |
Thomas Gleixner | 71466535 | 2015-09-15 12:37:36 +0200 | [diff] [blame] | 161 | * If handler_data is set, this is a cascading interrupt, and |
| 162 | * it cannot possibly be forwarded. |
Marc Zyngier | 01f779f | 2015-08-26 17:00:45 +0100 | [diff] [blame] | 163 | */ |
Thomas Gleixner | 71466535 | 2015-09-15 12:37:36 +0200 | [diff] [blame] | 164 | return data != NULL; |
Marc Zyngier | 01f779f | 2015-08-26 17:00:45 +0100 | [diff] [blame] | 165 | } |
| 166 | |
Russell King | f27ecac | 2005-08-18 21:31:00 +0100 | [diff] [blame] | 167 | /* |
| 168 | * Routines to acknowledge, disable and enable interrupts |
Russell King | f27ecac | 2005-08-18 21:31:00 +0100 | [diff] [blame] | 169 | */ |
Marc Zyngier | 5671780 | 2015-03-18 11:01:23 +0000 | [diff] [blame] | 170 | static void gic_poke_irq(struct irq_data *d, u32 offset) |
Russell King | f27ecac | 2005-08-18 21:31:00 +0100 | [diff] [blame] | 171 | { |
Rob Herring | 4294f8ba | 2011-09-28 21:25:31 -0500 | [diff] [blame] | 172 | u32 mask = 1 << (gic_irq(d) % 32); |
Marc Zyngier | 5671780 | 2015-03-18 11:01:23 +0000 | [diff] [blame] | 173 | writel_relaxed(mask, gic_dist_base(d) + offset + (gic_irq(d) / 32) * 4); |
| 174 | } |
| 175 | |
| 176 | static int gic_peek_irq(struct irq_data *d, u32 offset) |
| 177 | { |
| 178 | u32 mask = 1 << (gic_irq(d) % 32); |
| 179 | return !!(readl_relaxed(gic_dist_base(d) + offset + (gic_irq(d) / 32) * 4) & mask); |
| 180 | } |
| 181 | |
| 182 | static void gic_mask_irq(struct irq_data *d) |
| 183 | { |
Marc Zyngier | 5671780 | 2015-03-18 11:01:23 +0000 | [diff] [blame] | 184 | gic_poke_irq(d, GIC_DIST_ENABLE_CLEAR); |
Russell King | f27ecac | 2005-08-18 21:31:00 +0100 | [diff] [blame] | 185 | } |
| 186 | |
Marc Zyngier | 0b996fd | 2015-08-26 17:00:44 +0100 | [diff] [blame] | 187 | static void gic_eoimode1_mask_irq(struct irq_data *d) |
| 188 | { |
| 189 | gic_mask_irq(d); |
Marc Zyngier | 01f779f | 2015-08-26 17:00:45 +0100 | [diff] [blame] | 190 | /* |
| 191 | * When masking a forwarded interrupt, make sure it is |
| 192 | * deactivated as well. |
| 193 | * |
| 194 | * This ensures that an interrupt that is getting |
| 195 | * disabled/masked will not get "stuck", because there is |
| 196 | * noone to deactivate it (guest is being terminated). |
| 197 | */ |
Thomas Gleixner | 71466535 | 2015-09-15 12:37:36 +0200 | [diff] [blame] | 198 | if (irqd_is_forwarded_to_vcpu(d)) |
Marc Zyngier | 01f779f | 2015-08-26 17:00:45 +0100 | [diff] [blame] | 199 | gic_poke_irq(d, GIC_DIST_ACTIVE_CLEAR); |
Marc Zyngier | 0b996fd | 2015-08-26 17:00:44 +0100 | [diff] [blame] | 200 | } |
| 201 | |
Lennert Buytenhek | 7d1f428 | 2010-11-29 10:18:20 +0100 | [diff] [blame] | 202 | static void gic_unmask_irq(struct irq_data *d) |
Russell King | f27ecac | 2005-08-18 21:31:00 +0100 | [diff] [blame] | 203 | { |
Marc Zyngier | 5671780 | 2015-03-18 11:01:23 +0000 | [diff] [blame] | 204 | gic_poke_irq(d, GIC_DIST_ENABLE_SET); |
Russell King | f27ecac | 2005-08-18 21:31:00 +0100 | [diff] [blame] | 205 | } |
| 206 | |
Will Deacon | 1a01753 | 2011-02-09 12:01:12 +0000 | [diff] [blame] | 207 | static void gic_eoi_irq(struct irq_data *d) |
| 208 | { |
Santosh Shilimkar | 6ac77e4 | 2011-03-28 19:27:46 +0530 | [diff] [blame] | 209 | writel_relaxed(gic_irq(d), gic_cpu_base(d) + GIC_CPU_EOI); |
Will Deacon | 1a01753 | 2011-02-09 12:01:12 +0000 | [diff] [blame] | 210 | } |
| 211 | |
Marc Zyngier | 0b996fd | 2015-08-26 17:00:44 +0100 | [diff] [blame] | 212 | static void gic_eoimode1_eoi_irq(struct irq_data *d) |
| 213 | { |
Marc Zyngier | 01f779f | 2015-08-26 17:00:45 +0100 | [diff] [blame] | 214 | /* Do not deactivate an IRQ forwarded to a vcpu. */ |
Thomas Gleixner | 71466535 | 2015-09-15 12:37:36 +0200 | [diff] [blame] | 215 | if (irqd_is_forwarded_to_vcpu(d)) |
Marc Zyngier | 01f779f | 2015-08-26 17:00:45 +0100 | [diff] [blame] | 216 | return; |
| 217 | |
Marc Zyngier | 0b996fd | 2015-08-26 17:00:44 +0100 | [diff] [blame] | 218 | writel_relaxed(gic_irq(d), gic_cpu_base(d) + GIC_CPU_DEACTIVATE); |
| 219 | } |
| 220 | |
Marc Zyngier | 5671780 | 2015-03-18 11:01:23 +0000 | [diff] [blame] | 221 | static int gic_irq_set_irqchip_state(struct irq_data *d, |
| 222 | enum irqchip_irq_state which, bool val) |
| 223 | { |
| 224 | u32 reg; |
| 225 | |
| 226 | switch (which) { |
| 227 | case IRQCHIP_STATE_PENDING: |
| 228 | reg = val ? GIC_DIST_PENDING_SET : GIC_DIST_PENDING_CLEAR; |
| 229 | break; |
| 230 | |
| 231 | case IRQCHIP_STATE_ACTIVE: |
| 232 | reg = val ? GIC_DIST_ACTIVE_SET : GIC_DIST_ACTIVE_CLEAR; |
| 233 | break; |
| 234 | |
| 235 | case IRQCHIP_STATE_MASKED: |
| 236 | reg = val ? GIC_DIST_ENABLE_CLEAR : GIC_DIST_ENABLE_SET; |
| 237 | break; |
| 238 | |
| 239 | default: |
| 240 | return -EINVAL; |
| 241 | } |
| 242 | |
| 243 | gic_poke_irq(d, reg); |
| 244 | return 0; |
| 245 | } |
| 246 | |
| 247 | static int gic_irq_get_irqchip_state(struct irq_data *d, |
| 248 | enum irqchip_irq_state which, bool *val) |
| 249 | { |
| 250 | switch (which) { |
| 251 | case IRQCHIP_STATE_PENDING: |
| 252 | *val = gic_peek_irq(d, GIC_DIST_PENDING_SET); |
| 253 | break; |
| 254 | |
| 255 | case IRQCHIP_STATE_ACTIVE: |
| 256 | *val = gic_peek_irq(d, GIC_DIST_ACTIVE_SET); |
| 257 | break; |
| 258 | |
| 259 | case IRQCHIP_STATE_MASKED: |
| 260 | *val = !gic_peek_irq(d, GIC_DIST_ENABLE_SET); |
| 261 | break; |
| 262 | |
| 263 | default: |
| 264 | return -EINVAL; |
| 265 | } |
| 266 | |
| 267 | return 0; |
| 268 | } |
| 269 | |
Lennert Buytenhek | 7d1f428 | 2010-11-29 10:18:20 +0100 | [diff] [blame] | 270 | static int gic_set_type(struct irq_data *d, unsigned int type) |
Rabin Vincent | 5c0c1f0 | 2010-05-28 04:37:38 +0100 | [diff] [blame] | 271 | { |
Lennert Buytenhek | 7d1f428 | 2010-11-29 10:18:20 +0100 | [diff] [blame] | 272 | void __iomem *base = gic_dist_base(d); |
| 273 | unsigned int gicirq = gic_irq(d); |
Rabin Vincent | 5c0c1f0 | 2010-05-28 04:37:38 +0100 | [diff] [blame] | 274 | |
| 275 | /* Interrupt configuration for SGIs can't be changed */ |
| 276 | if (gicirq < 16) |
| 277 | return -EINVAL; |
| 278 | |
Liviu Dudau | fb7e7de | 2015-01-20 16:52:59 +0000 | [diff] [blame] | 279 | /* SPIs have restrictions on the supported types */ |
| 280 | if (gicirq >= 32 && type != IRQ_TYPE_LEVEL_HIGH && |
| 281 | type != IRQ_TYPE_EDGE_RISING) |
Rabin Vincent | 5c0c1f0 | 2010-05-28 04:37:38 +0100 | [diff] [blame] | 282 | return -EINVAL; |
| 283 | |
Marc Zyngier | 1dcc73d | 2015-04-22 18:20:04 +0100 | [diff] [blame] | 284 | return gic_configure_irq(gicirq, type, base, NULL); |
Santosh Shilimkar | d7ed36a | 2011-03-02 08:03:22 +0100 | [diff] [blame] | 285 | } |
| 286 | |
Marc Zyngier | 01f779f | 2015-08-26 17:00:45 +0100 | [diff] [blame] | 287 | static int gic_irq_set_vcpu_affinity(struct irq_data *d, void *vcpu) |
| 288 | { |
| 289 | /* Only interrupts on the primary GIC can be forwarded to a vcpu. */ |
| 290 | if (cascading_gic_irq(d)) |
| 291 | return -EINVAL; |
| 292 | |
Thomas Gleixner | 71466535 | 2015-09-15 12:37:36 +0200 | [diff] [blame] | 293 | if (vcpu) |
| 294 | irqd_set_forwarded_to_vcpu(d); |
| 295 | else |
| 296 | irqd_clr_forwarded_to_vcpu(d); |
Marc Zyngier | 01f779f | 2015-08-26 17:00:45 +0100 | [diff] [blame] | 297 | return 0; |
| 298 | } |
| 299 | |
Catalin Marinas | a06f546 | 2005-09-30 16:07:05 +0100 | [diff] [blame] | 300 | #ifdef CONFIG_SMP |
Russell King | c191789 | 2011-01-23 12:12:01 +0000 | [diff] [blame] | 301 | static int gic_set_affinity(struct irq_data *d, const struct cpumask *mask_val, |
| 302 | bool force) |
Russell King | f27ecac | 2005-08-18 21:31:00 +0100 | [diff] [blame] | 303 | { |
Lennert Buytenhek | 7d1f428 | 2010-11-29 10:18:20 +0100 | [diff] [blame] | 304 | void __iomem *reg = gic_dist_base(d) + GIC_DIST_TARGET + (gic_irq(d) & ~3); |
Thomas Gleixner | ffde1de | 2014-04-16 14:36:44 +0000 | [diff] [blame] | 305 | unsigned int cpu, shift = (gic_irq(d) % 4) * 8; |
Russell King | c191789 | 2011-01-23 12:12:01 +0000 | [diff] [blame] | 306 | u32 val, mask, bit; |
Marc Zyngier | cf61387 | 2015-03-06 16:37:44 +0000 | [diff] [blame] | 307 | unsigned long flags; |
Russell King | c191789 | 2011-01-23 12:12:01 +0000 | [diff] [blame] | 308 | |
Thomas Gleixner | ffde1de | 2014-04-16 14:36:44 +0000 | [diff] [blame] | 309 | if (!force) |
| 310 | cpu = cpumask_any_and(mask_val, cpu_online_mask); |
| 311 | else |
| 312 | cpu = cpumask_first(mask_val); |
| 313 | |
Nicolas Pitre | 384a290 | 2012-04-11 18:55:48 -0400 | [diff] [blame] | 314 | if (cpu >= NR_GIC_CPU_IF || cpu >= nr_cpu_ids) |
Russell King | c191789 | 2011-01-23 12:12:01 +0000 | [diff] [blame] | 315 | return -EINVAL; |
| 316 | |
Marc Zyngier | cf61387 | 2015-03-06 16:37:44 +0000 | [diff] [blame] | 317 | raw_spin_lock_irqsave(&irq_controller_lock, flags); |
Russell King | c191789 | 2011-01-23 12:12:01 +0000 | [diff] [blame] | 318 | mask = 0xff << shift; |
Nicolas Pitre | 384a290 | 2012-04-11 18:55:48 -0400 | [diff] [blame] | 319 | bit = gic_cpu_map[cpu] << shift; |
Santosh Shilimkar | 6ac77e4 | 2011-03-28 19:27:46 +0530 | [diff] [blame] | 320 | val = readl_relaxed(reg) & ~mask; |
| 321 | writel_relaxed(val | bit, reg); |
Marc Zyngier | cf61387 | 2015-03-06 16:37:44 +0000 | [diff] [blame] | 322 | raw_spin_unlock_irqrestore(&irq_controller_lock, flags); |
Yinghai Lu | d5dedd4 | 2009-04-27 17:59:21 -0700 | [diff] [blame] | 323 | |
Russell King | 5dfc54e | 2011-07-21 15:00:57 +0100 | [diff] [blame] | 324 | return IRQ_SET_MASK_OK; |
Russell King | f27ecac | 2005-08-18 21:31:00 +0100 | [diff] [blame] | 325 | } |
Catalin Marinas | a06f546 | 2005-09-30 16:07:05 +0100 | [diff] [blame] | 326 | #endif |
Russell King | f27ecac | 2005-08-18 21:31:00 +0100 | [diff] [blame] | 327 | |
Stephen Boyd | 8783dd3 | 2014-03-04 16:40:30 -0800 | [diff] [blame] | 328 | static void __exception_irq_entry gic_handle_irq(struct pt_regs *regs) |
Marc Zyngier | 562e002 | 2011-09-06 09:56:17 +0100 | [diff] [blame] | 329 | { |
| 330 | u32 irqstat, irqnr; |
| 331 | struct gic_chip_data *gic = &gic_data[0]; |
| 332 | void __iomem *cpu_base = gic_data_cpu_base(gic); |
| 333 | |
| 334 | do { |
| 335 | irqstat = readl_relaxed(cpu_base + GIC_CPU_INTACK); |
Haojian Zhuang | b8802f7 | 2014-05-11 16:05:58 +0800 | [diff] [blame] | 336 | irqnr = irqstat & GICC_IAR_INT_ID_MASK; |
Marc Zyngier | 562e002 | 2011-09-06 09:56:17 +0100 | [diff] [blame] | 337 | |
| 338 | if (likely(irqnr > 15 && irqnr < 1021)) { |
Marc Zyngier | 0b996fd | 2015-08-26 17:00:44 +0100 | [diff] [blame] | 339 | if (static_key_true(&supports_deactivate)) |
| 340 | writel_relaxed(irqstat, cpu_base + GIC_CPU_EOI); |
Marc Zyngier | 60031b4 | 2014-08-26 11:03:20 +0100 | [diff] [blame] | 341 | handle_domain_irq(gic->domain, irqnr, regs); |
Marc Zyngier | 562e002 | 2011-09-06 09:56:17 +0100 | [diff] [blame] | 342 | continue; |
| 343 | } |
| 344 | if (irqnr < 16) { |
| 345 | writel_relaxed(irqstat, cpu_base + GIC_CPU_EOI); |
Marc Zyngier | 0b996fd | 2015-08-26 17:00:44 +0100 | [diff] [blame] | 346 | if (static_key_true(&supports_deactivate)) |
| 347 | writel_relaxed(irqstat, cpu_base + GIC_CPU_DEACTIVATE); |
Marc Zyngier | 562e002 | 2011-09-06 09:56:17 +0100 | [diff] [blame] | 348 | #ifdef CONFIG_SMP |
| 349 | handle_IPI(irqnr, regs); |
| 350 | #endif |
| 351 | continue; |
| 352 | } |
| 353 | break; |
| 354 | } while (1); |
| 355 | } |
| 356 | |
Thomas Gleixner | bd0b9ac | 2015-09-14 10:42:37 +0200 | [diff] [blame] | 357 | static void gic_handle_cascade_irq(struct irq_desc *desc) |
Catalin Marinas | b3a1bde | 2007-02-14 19:14:56 +0100 | [diff] [blame] | 358 | { |
Jiang Liu | 5b29264 | 2015-06-04 12:13:20 +0800 | [diff] [blame] | 359 | struct gic_chip_data *chip_data = irq_desc_get_handler_data(desc); |
| 360 | struct irq_chip *chip = irq_desc_get_chip(desc); |
Russell King | 0f347bb | 2007-05-17 10:11:34 +0100 | [diff] [blame] | 361 | unsigned int cascade_irq, gic_irq; |
Catalin Marinas | b3a1bde | 2007-02-14 19:14:56 +0100 | [diff] [blame] | 362 | unsigned long status; |
| 363 | |
Will Deacon | 1a01753 | 2011-02-09 12:01:12 +0000 | [diff] [blame] | 364 | chained_irq_enter(chip, desc); |
Catalin Marinas | b3a1bde | 2007-02-14 19:14:56 +0100 | [diff] [blame] | 365 | |
Thomas Gleixner | bd31b85 | 2009-07-03 08:44:46 -0500 | [diff] [blame] | 366 | raw_spin_lock(&irq_controller_lock); |
Marc Zyngier | db0d4db | 2011-11-12 16:09:49 +0000 | [diff] [blame] | 367 | status = readl_relaxed(gic_data_cpu_base(chip_data) + GIC_CPU_INTACK); |
Thomas Gleixner | bd31b85 | 2009-07-03 08:44:46 -0500 | [diff] [blame] | 368 | raw_spin_unlock(&irq_controller_lock); |
Catalin Marinas | b3a1bde | 2007-02-14 19:14:56 +0100 | [diff] [blame] | 369 | |
Feng Kan | e5f8153 | 2014-07-30 14:56:58 -0700 | [diff] [blame] | 370 | gic_irq = (status & GICC_IAR_INT_ID_MASK); |
| 371 | if (gic_irq == GICC_INT_SPURIOUS) |
Catalin Marinas | b3a1bde | 2007-02-14 19:14:56 +0100 | [diff] [blame] | 372 | goto out; |
Catalin Marinas | b3a1bde | 2007-02-14 19:14:56 +0100 | [diff] [blame] | 373 | |
Grant Likely | 7529495 | 2012-02-14 14:06:57 -0700 | [diff] [blame] | 374 | cascade_irq = irq_find_mapping(chip_data->domain, gic_irq); |
| 375 | if (unlikely(gic_irq < 32 || gic_irq > 1020)) |
Thomas Gleixner | bd0b9ac | 2015-09-14 10:42:37 +0200 | [diff] [blame] | 376 | handle_bad_irq(desc); |
Russell King | 0f347bb | 2007-05-17 10:11:34 +0100 | [diff] [blame] | 377 | else |
| 378 | generic_handle_irq(cascade_irq); |
Catalin Marinas | b3a1bde | 2007-02-14 19:14:56 +0100 | [diff] [blame] | 379 | |
| 380 | out: |
Will Deacon | 1a01753 | 2011-02-09 12:01:12 +0000 | [diff] [blame] | 381 | chained_irq_exit(chip, desc); |
Catalin Marinas | b3a1bde | 2007-02-14 19:14:56 +0100 | [diff] [blame] | 382 | } |
| 383 | |
David Brownell | 38c677c | 2006-08-01 22:26:25 +0100 | [diff] [blame] | 384 | static struct irq_chip gic_chip = { |
Lennert Buytenhek | 7d1f428 | 2010-11-29 10:18:20 +0100 | [diff] [blame] | 385 | .name = "GIC", |
Lennert Buytenhek | 7d1f428 | 2010-11-29 10:18:20 +0100 | [diff] [blame] | 386 | .irq_mask = gic_mask_irq, |
| 387 | .irq_unmask = gic_unmask_irq, |
Will Deacon | 1a01753 | 2011-02-09 12:01:12 +0000 | [diff] [blame] | 388 | .irq_eoi = gic_eoi_irq, |
Lennert Buytenhek | 7d1f428 | 2010-11-29 10:18:20 +0100 | [diff] [blame] | 389 | .irq_set_type = gic_set_type, |
Russell King | f27ecac | 2005-08-18 21:31:00 +0100 | [diff] [blame] | 390 | #ifdef CONFIG_SMP |
Russell King | c191789 | 2011-01-23 12:12:01 +0000 | [diff] [blame] | 391 | .irq_set_affinity = gic_set_affinity, |
Russell King | f27ecac | 2005-08-18 21:31:00 +0100 | [diff] [blame] | 392 | #endif |
Marc Zyngier | 5671780 | 2015-03-18 11:01:23 +0000 | [diff] [blame] | 393 | .irq_get_irqchip_state = gic_irq_get_irqchip_state, |
| 394 | .irq_set_irqchip_state = gic_irq_set_irqchip_state, |
Sudeep Holla | aec89ef | 2015-07-15 15:38:28 +0100 | [diff] [blame] | 395 | .flags = IRQCHIP_SET_TYPE_MASKED | |
| 396 | IRQCHIP_SKIP_SET_WAKE | |
| 397 | IRQCHIP_MASK_ON_SUSPEND, |
Russell King | f27ecac | 2005-08-18 21:31:00 +0100 | [diff] [blame] | 398 | }; |
| 399 | |
Marc Zyngier | 0b996fd | 2015-08-26 17:00:44 +0100 | [diff] [blame] | 400 | static struct irq_chip gic_eoimode1_chip = { |
| 401 | .name = "GICv2", |
| 402 | .irq_mask = gic_eoimode1_mask_irq, |
| 403 | .irq_unmask = gic_unmask_irq, |
| 404 | .irq_eoi = gic_eoimode1_eoi_irq, |
| 405 | .irq_set_type = gic_set_type, |
| 406 | #ifdef CONFIG_SMP |
| 407 | .irq_set_affinity = gic_set_affinity, |
| 408 | #endif |
| 409 | .irq_get_irqchip_state = gic_irq_get_irqchip_state, |
| 410 | .irq_set_irqchip_state = gic_irq_set_irqchip_state, |
Marc Zyngier | 01f779f | 2015-08-26 17:00:45 +0100 | [diff] [blame] | 411 | .irq_set_vcpu_affinity = gic_irq_set_vcpu_affinity, |
Marc Zyngier | 0b996fd | 2015-08-26 17:00:44 +0100 | [diff] [blame] | 412 | .flags = IRQCHIP_SET_TYPE_MASKED | |
| 413 | IRQCHIP_SKIP_SET_WAKE | |
| 414 | IRQCHIP_MASK_ON_SUSPEND, |
| 415 | }; |
| 416 | |
Catalin Marinas | b3a1bde | 2007-02-14 19:14:56 +0100 | [diff] [blame] | 417 | void __init gic_cascade_irq(unsigned int gic_nr, unsigned int irq) |
| 418 | { |
| 419 | if (gic_nr >= MAX_GIC_NR) |
| 420 | BUG(); |
Thomas Gleixner | 4d83fcf | 2015-06-21 21:10:53 +0200 | [diff] [blame] | 421 | irq_set_chained_handler_and_data(irq, gic_handle_cascade_irq, |
| 422 | &gic_data[gic_nr]); |
Catalin Marinas | b3a1bde | 2007-02-14 19:14:56 +0100 | [diff] [blame] | 423 | } |
| 424 | |
Russell King | 2bb3135 | 2013-01-30 23:49:57 +0000 | [diff] [blame] | 425 | static u8 gic_get_cpumask(struct gic_chip_data *gic) |
| 426 | { |
| 427 | void __iomem *base = gic_data_dist_base(gic); |
| 428 | u32 mask, i; |
| 429 | |
| 430 | for (i = mask = 0; i < 32; i += 4) { |
| 431 | mask = readl_relaxed(base + GIC_DIST_TARGET + i); |
| 432 | mask |= mask >> 16; |
| 433 | mask |= mask >> 8; |
| 434 | if (mask) |
| 435 | break; |
| 436 | } |
| 437 | |
Stephen Boyd | 6e3aca4 | 2015-03-11 23:21:31 -0700 | [diff] [blame] | 438 | if (!mask && num_possible_cpus() > 1) |
Russell King | 2bb3135 | 2013-01-30 23:49:57 +0000 | [diff] [blame] | 439 | pr_crit("GIC CPU mask not found - kernel will fail to boot.\n"); |
| 440 | |
| 441 | return mask; |
| 442 | } |
| 443 | |
Jon Hunter | 4c2880b | 2015-07-31 09:44:12 +0100 | [diff] [blame] | 444 | static void gic_cpu_if_up(struct gic_chip_data *gic) |
Feng Kan | 3228950 | 2014-07-30 14:56:59 -0700 | [diff] [blame] | 445 | { |
Jon Hunter | 4c2880b | 2015-07-31 09:44:12 +0100 | [diff] [blame] | 446 | void __iomem *cpu_base = gic_data_cpu_base(gic); |
Feng Kan | 3228950 | 2014-07-30 14:56:59 -0700 | [diff] [blame] | 447 | u32 bypass = 0; |
Marc Zyngier | 0b996fd | 2015-08-26 17:00:44 +0100 | [diff] [blame] | 448 | u32 mode = 0; |
| 449 | |
| 450 | if (static_key_true(&supports_deactivate)) |
| 451 | mode = GIC_CPU_CTRL_EOImodeNS; |
Feng Kan | 3228950 | 2014-07-30 14:56:59 -0700 | [diff] [blame] | 452 | |
| 453 | /* |
| 454 | * Preserve bypass disable bits to be written back later |
| 455 | */ |
| 456 | bypass = readl(cpu_base + GIC_CPU_CTRL); |
| 457 | bypass &= GICC_DIS_BYPASS_MASK; |
| 458 | |
Marc Zyngier | 0b996fd | 2015-08-26 17:00:44 +0100 | [diff] [blame] | 459 | writel_relaxed(bypass | mode | GICC_ENABLE, cpu_base + GIC_CPU_CTRL); |
Feng Kan | 3228950 | 2014-07-30 14:56:59 -0700 | [diff] [blame] | 460 | } |
| 461 | |
| 462 | |
Rob Herring | 4294f8ba | 2011-09-28 21:25:31 -0500 | [diff] [blame] | 463 | static void __init gic_dist_init(struct gic_chip_data *gic) |
Russell King | f27ecac | 2005-08-18 21:31:00 +0100 | [diff] [blame] | 464 | { |
Grant Likely | 7529495 | 2012-02-14 14:06:57 -0700 | [diff] [blame] | 465 | unsigned int i; |
Will Deacon | 267840f | 2011-08-23 22:20:03 +0100 | [diff] [blame] | 466 | u32 cpumask; |
Rob Herring | 4294f8ba | 2011-09-28 21:25:31 -0500 | [diff] [blame] | 467 | unsigned int gic_irqs = gic->gic_irqs; |
Marc Zyngier | db0d4db | 2011-11-12 16:09:49 +0000 | [diff] [blame] | 468 | void __iomem *base = gic_data_dist_base(gic); |
Russell King | f27ecac | 2005-08-18 21:31:00 +0100 | [diff] [blame] | 469 | |
Feng Kan | e5f8153 | 2014-07-30 14:56:58 -0700 | [diff] [blame] | 470 | writel_relaxed(GICD_DISABLE, base + GIC_DIST_CTRL); |
Russell King | f27ecac | 2005-08-18 21:31:00 +0100 | [diff] [blame] | 471 | |
| 472 | /* |
Russell King | f27ecac | 2005-08-18 21:31:00 +0100 | [diff] [blame] | 473 | * Set all global interrupts to this CPU only. |
| 474 | */ |
Russell King | 2bb3135 | 2013-01-30 23:49:57 +0000 | [diff] [blame] | 475 | cpumask = gic_get_cpumask(gic); |
| 476 | cpumask |= cpumask << 8; |
| 477 | cpumask |= cpumask << 16; |
Pawel Moll | e6afec9 | 2010-11-26 13:45:43 +0100 | [diff] [blame] | 478 | for (i = 32; i < gic_irqs; i += 4) |
Santosh Shilimkar | 6ac77e4 | 2011-03-28 19:27:46 +0530 | [diff] [blame] | 479 | writel_relaxed(cpumask, base + GIC_DIST_TARGET + i * 4 / 4); |
Russell King | f27ecac | 2005-08-18 21:31:00 +0100 | [diff] [blame] | 480 | |
Marc Zyngier | d51d0af | 2014-06-30 16:01:30 +0100 | [diff] [blame] | 481 | gic_dist_config(base, gic_irqs, NULL); |
Russell King | f27ecac | 2005-08-18 21:31:00 +0100 | [diff] [blame] | 482 | |
Feng Kan | e5f8153 | 2014-07-30 14:56:58 -0700 | [diff] [blame] | 483 | writel_relaxed(GICD_ENABLE, base + GIC_DIST_CTRL); |
Russell King | f27ecac | 2005-08-18 21:31:00 +0100 | [diff] [blame] | 484 | } |
| 485 | |
Paul Gortmaker | 8c37bb3 | 2013-06-19 11:32:08 -0400 | [diff] [blame] | 486 | static void gic_cpu_init(struct gic_chip_data *gic) |
Russell King | f27ecac | 2005-08-18 21:31:00 +0100 | [diff] [blame] | 487 | { |
Marc Zyngier | db0d4db | 2011-11-12 16:09:49 +0000 | [diff] [blame] | 488 | void __iomem *dist_base = gic_data_dist_base(gic); |
| 489 | void __iomem *base = gic_data_cpu_base(gic); |
Nicolas Pitre | 384a290 | 2012-04-11 18:55:48 -0400 | [diff] [blame] | 490 | unsigned int cpu_mask, cpu = smp_processor_id(); |
Russell King | 9395f6e | 2010-11-11 23:10:30 +0000 | [diff] [blame] | 491 | int i; |
| 492 | |
Russell King | 9395f6e | 2010-11-11 23:10:30 +0000 | [diff] [blame] | 493 | /* |
Jon Hunter | 567e5a0 | 2015-07-31 09:44:11 +0100 | [diff] [blame] | 494 | * Setting up the CPU map is only relevant for the primary GIC |
| 495 | * because any nested/secondary GICs do not directly interface |
| 496 | * with the CPU(s). |
Nicolas Pitre | 384a290 | 2012-04-11 18:55:48 -0400 | [diff] [blame] | 497 | */ |
Jon Hunter | 567e5a0 | 2015-07-31 09:44:11 +0100 | [diff] [blame] | 498 | if (gic == &gic_data[0]) { |
| 499 | /* |
| 500 | * Get what the GIC says our CPU mask is. |
| 501 | */ |
| 502 | BUG_ON(cpu >= NR_GIC_CPU_IF); |
| 503 | cpu_mask = gic_get_cpumask(gic); |
| 504 | gic_cpu_map[cpu] = cpu_mask; |
Nicolas Pitre | 384a290 | 2012-04-11 18:55:48 -0400 | [diff] [blame] | 505 | |
Jon Hunter | 567e5a0 | 2015-07-31 09:44:11 +0100 | [diff] [blame] | 506 | /* |
| 507 | * Clear our mask from the other map entries in case they're |
| 508 | * still undefined. |
| 509 | */ |
| 510 | for (i = 0; i < NR_GIC_CPU_IF; i++) |
| 511 | if (i != cpu) |
| 512 | gic_cpu_map[i] &= ~cpu_mask; |
| 513 | } |
Nicolas Pitre | 384a290 | 2012-04-11 18:55:48 -0400 | [diff] [blame] | 514 | |
Marc Zyngier | d51d0af | 2014-06-30 16:01:30 +0100 | [diff] [blame] | 515 | gic_cpu_config(dist_base, NULL); |
Russell King | 9395f6e | 2010-11-11 23:10:30 +0000 | [diff] [blame] | 516 | |
Feng Kan | e5f8153 | 2014-07-30 14:56:58 -0700 | [diff] [blame] | 517 | writel_relaxed(GICC_INT_PRI_THRESHOLD, base + GIC_CPU_PRIMASK); |
Jon Hunter | 4c2880b | 2015-07-31 09:44:12 +0100 | [diff] [blame] | 518 | gic_cpu_if_up(gic); |
Russell King | f27ecac | 2005-08-18 21:31:00 +0100 | [diff] [blame] | 519 | } |
| 520 | |
Jon Hunter | 4c2880b | 2015-07-31 09:44:12 +0100 | [diff] [blame] | 521 | int gic_cpu_if_down(unsigned int gic_nr) |
Nicolas Pitre | 10d9eb8 | 2013-03-19 23:59:04 -0400 | [diff] [blame] | 522 | { |
Jon Hunter | 4c2880b | 2015-07-31 09:44:12 +0100 | [diff] [blame] | 523 | void __iomem *cpu_base; |
Feng Kan | 3228950 | 2014-07-30 14:56:59 -0700 | [diff] [blame] | 524 | u32 val = 0; |
| 525 | |
Jon Hunter | 4c2880b | 2015-07-31 09:44:12 +0100 | [diff] [blame] | 526 | if (gic_nr >= MAX_GIC_NR) |
| 527 | return -EINVAL; |
| 528 | |
| 529 | cpu_base = gic_data_cpu_base(&gic_data[gic_nr]); |
Feng Kan | 3228950 | 2014-07-30 14:56:59 -0700 | [diff] [blame] | 530 | val = readl(cpu_base + GIC_CPU_CTRL); |
| 531 | val &= ~GICC_ENABLE; |
| 532 | writel_relaxed(val, cpu_base + GIC_CPU_CTRL); |
Jon Hunter | 4c2880b | 2015-07-31 09:44:12 +0100 | [diff] [blame] | 533 | |
| 534 | return 0; |
Nicolas Pitre | 10d9eb8 | 2013-03-19 23:59:04 -0400 | [diff] [blame] | 535 | } |
| 536 | |
Colin Cross | 254056f | 2011-02-10 12:54:10 -0800 | [diff] [blame] | 537 | #ifdef CONFIG_CPU_PM |
| 538 | /* |
| 539 | * Saves the GIC distributor registers during suspend or idle. Must be called |
| 540 | * with interrupts disabled but before powering down the GIC. After calling |
| 541 | * this function, no interrupts will be delivered by the GIC, and another |
| 542 | * platform-specific wakeup source must be enabled. |
| 543 | */ |
| 544 | static void gic_dist_save(unsigned int gic_nr) |
| 545 | { |
| 546 | unsigned int gic_irqs; |
| 547 | void __iomem *dist_base; |
| 548 | int i; |
| 549 | |
| 550 | if (gic_nr >= MAX_GIC_NR) |
| 551 | BUG(); |
| 552 | |
| 553 | gic_irqs = gic_data[gic_nr].gic_irqs; |
Marc Zyngier | db0d4db | 2011-11-12 16:09:49 +0000 | [diff] [blame] | 554 | dist_base = gic_data_dist_base(&gic_data[gic_nr]); |
Colin Cross | 254056f | 2011-02-10 12:54:10 -0800 | [diff] [blame] | 555 | |
| 556 | if (!dist_base) |
| 557 | return; |
| 558 | |
| 559 | for (i = 0; i < DIV_ROUND_UP(gic_irqs, 16); i++) |
| 560 | gic_data[gic_nr].saved_spi_conf[i] = |
| 561 | readl_relaxed(dist_base + GIC_DIST_CONFIG + i * 4); |
| 562 | |
| 563 | for (i = 0; i < DIV_ROUND_UP(gic_irqs, 4); i++) |
| 564 | gic_data[gic_nr].saved_spi_target[i] = |
| 565 | readl_relaxed(dist_base + GIC_DIST_TARGET + i * 4); |
| 566 | |
| 567 | for (i = 0; i < DIV_ROUND_UP(gic_irqs, 32); i++) |
| 568 | gic_data[gic_nr].saved_spi_enable[i] = |
| 569 | readl_relaxed(dist_base + GIC_DIST_ENABLE_SET + i * 4); |
| 570 | } |
| 571 | |
| 572 | /* |
| 573 | * Restores the GIC distributor registers during resume or when coming out of |
| 574 | * idle. Must be called before enabling interrupts. If a level interrupt |
| 575 | * that occured while the GIC was suspended is still present, it will be |
| 576 | * handled normally, but any edge interrupts that occured will not be seen by |
| 577 | * the GIC and need to be handled by the platform-specific wakeup source. |
| 578 | */ |
| 579 | static void gic_dist_restore(unsigned int gic_nr) |
| 580 | { |
| 581 | unsigned int gic_irqs; |
| 582 | unsigned int i; |
| 583 | void __iomem *dist_base; |
| 584 | |
| 585 | if (gic_nr >= MAX_GIC_NR) |
| 586 | BUG(); |
| 587 | |
| 588 | gic_irqs = gic_data[gic_nr].gic_irqs; |
Marc Zyngier | db0d4db | 2011-11-12 16:09:49 +0000 | [diff] [blame] | 589 | dist_base = gic_data_dist_base(&gic_data[gic_nr]); |
Colin Cross | 254056f | 2011-02-10 12:54:10 -0800 | [diff] [blame] | 590 | |
| 591 | if (!dist_base) |
| 592 | return; |
| 593 | |
Feng Kan | e5f8153 | 2014-07-30 14:56:58 -0700 | [diff] [blame] | 594 | writel_relaxed(GICD_DISABLE, dist_base + GIC_DIST_CTRL); |
Colin Cross | 254056f | 2011-02-10 12:54:10 -0800 | [diff] [blame] | 595 | |
| 596 | for (i = 0; i < DIV_ROUND_UP(gic_irqs, 16); i++) |
| 597 | writel_relaxed(gic_data[gic_nr].saved_spi_conf[i], |
| 598 | dist_base + GIC_DIST_CONFIG + i * 4); |
| 599 | |
| 600 | for (i = 0; i < DIV_ROUND_UP(gic_irqs, 4); i++) |
Feng Kan | e5f8153 | 2014-07-30 14:56:58 -0700 | [diff] [blame] | 601 | writel_relaxed(GICD_INT_DEF_PRI_X4, |
Colin Cross | 254056f | 2011-02-10 12:54:10 -0800 | [diff] [blame] | 602 | dist_base + GIC_DIST_PRI + i * 4); |
| 603 | |
| 604 | for (i = 0; i < DIV_ROUND_UP(gic_irqs, 4); i++) |
| 605 | writel_relaxed(gic_data[gic_nr].saved_spi_target[i], |
| 606 | dist_base + GIC_DIST_TARGET + i * 4); |
| 607 | |
| 608 | for (i = 0; i < DIV_ROUND_UP(gic_irqs, 32); i++) |
| 609 | writel_relaxed(gic_data[gic_nr].saved_spi_enable[i], |
| 610 | dist_base + GIC_DIST_ENABLE_SET + i * 4); |
| 611 | |
Feng Kan | e5f8153 | 2014-07-30 14:56:58 -0700 | [diff] [blame] | 612 | writel_relaxed(GICD_ENABLE, dist_base + GIC_DIST_CTRL); |
Colin Cross | 254056f | 2011-02-10 12:54:10 -0800 | [diff] [blame] | 613 | } |
| 614 | |
| 615 | static void gic_cpu_save(unsigned int gic_nr) |
| 616 | { |
| 617 | int i; |
| 618 | u32 *ptr; |
| 619 | void __iomem *dist_base; |
| 620 | void __iomem *cpu_base; |
| 621 | |
| 622 | if (gic_nr >= MAX_GIC_NR) |
| 623 | BUG(); |
| 624 | |
Marc Zyngier | db0d4db | 2011-11-12 16:09:49 +0000 | [diff] [blame] | 625 | dist_base = gic_data_dist_base(&gic_data[gic_nr]); |
| 626 | cpu_base = gic_data_cpu_base(&gic_data[gic_nr]); |
Colin Cross | 254056f | 2011-02-10 12:54:10 -0800 | [diff] [blame] | 627 | |
| 628 | if (!dist_base || !cpu_base) |
| 629 | return; |
| 630 | |
Christoph Lameter | 532d0d0 | 2014-08-17 12:30:39 -0500 | [diff] [blame] | 631 | ptr = raw_cpu_ptr(gic_data[gic_nr].saved_ppi_enable); |
Colin Cross | 254056f | 2011-02-10 12:54:10 -0800 | [diff] [blame] | 632 | for (i = 0; i < DIV_ROUND_UP(32, 32); i++) |
| 633 | ptr[i] = readl_relaxed(dist_base + GIC_DIST_ENABLE_SET + i * 4); |
| 634 | |
Christoph Lameter | 532d0d0 | 2014-08-17 12:30:39 -0500 | [diff] [blame] | 635 | ptr = raw_cpu_ptr(gic_data[gic_nr].saved_ppi_conf); |
Colin Cross | 254056f | 2011-02-10 12:54:10 -0800 | [diff] [blame] | 636 | for (i = 0; i < DIV_ROUND_UP(32, 16); i++) |
| 637 | ptr[i] = readl_relaxed(dist_base + GIC_DIST_CONFIG + i * 4); |
| 638 | |
| 639 | } |
| 640 | |
| 641 | static void gic_cpu_restore(unsigned int gic_nr) |
| 642 | { |
| 643 | int i; |
| 644 | u32 *ptr; |
| 645 | void __iomem *dist_base; |
| 646 | void __iomem *cpu_base; |
| 647 | |
| 648 | if (gic_nr >= MAX_GIC_NR) |
| 649 | BUG(); |
| 650 | |
Marc Zyngier | db0d4db | 2011-11-12 16:09:49 +0000 | [diff] [blame] | 651 | dist_base = gic_data_dist_base(&gic_data[gic_nr]); |
| 652 | cpu_base = gic_data_cpu_base(&gic_data[gic_nr]); |
Colin Cross | 254056f | 2011-02-10 12:54:10 -0800 | [diff] [blame] | 653 | |
| 654 | if (!dist_base || !cpu_base) |
| 655 | return; |
| 656 | |
Christoph Lameter | 532d0d0 | 2014-08-17 12:30:39 -0500 | [diff] [blame] | 657 | ptr = raw_cpu_ptr(gic_data[gic_nr].saved_ppi_enable); |
Colin Cross | 254056f | 2011-02-10 12:54:10 -0800 | [diff] [blame] | 658 | for (i = 0; i < DIV_ROUND_UP(32, 32); i++) |
| 659 | writel_relaxed(ptr[i], dist_base + GIC_DIST_ENABLE_SET + i * 4); |
| 660 | |
Christoph Lameter | 532d0d0 | 2014-08-17 12:30:39 -0500 | [diff] [blame] | 661 | ptr = raw_cpu_ptr(gic_data[gic_nr].saved_ppi_conf); |
Colin Cross | 254056f | 2011-02-10 12:54:10 -0800 | [diff] [blame] | 662 | for (i = 0; i < DIV_ROUND_UP(32, 16); i++) |
| 663 | writel_relaxed(ptr[i], dist_base + GIC_DIST_CONFIG + i * 4); |
| 664 | |
| 665 | for (i = 0; i < DIV_ROUND_UP(32, 4); i++) |
Feng Kan | e5f8153 | 2014-07-30 14:56:58 -0700 | [diff] [blame] | 666 | writel_relaxed(GICD_INT_DEF_PRI_X4, |
| 667 | dist_base + GIC_DIST_PRI + i * 4); |
Colin Cross | 254056f | 2011-02-10 12:54:10 -0800 | [diff] [blame] | 668 | |
Feng Kan | e5f8153 | 2014-07-30 14:56:58 -0700 | [diff] [blame] | 669 | writel_relaxed(GICC_INT_PRI_THRESHOLD, cpu_base + GIC_CPU_PRIMASK); |
Jon Hunter | 4c2880b | 2015-07-31 09:44:12 +0100 | [diff] [blame] | 670 | gic_cpu_if_up(&gic_data[gic_nr]); |
Colin Cross | 254056f | 2011-02-10 12:54:10 -0800 | [diff] [blame] | 671 | } |
| 672 | |
| 673 | static int gic_notifier(struct notifier_block *self, unsigned long cmd, void *v) |
| 674 | { |
| 675 | int i; |
| 676 | |
| 677 | for (i = 0; i < MAX_GIC_NR; i++) { |
Marc Zyngier | db0d4db | 2011-11-12 16:09:49 +0000 | [diff] [blame] | 678 | #ifdef CONFIG_GIC_NON_BANKED |
| 679 | /* Skip over unused GICs */ |
| 680 | if (!gic_data[i].get_base) |
| 681 | continue; |
| 682 | #endif |
Colin Cross | 254056f | 2011-02-10 12:54:10 -0800 | [diff] [blame] | 683 | switch (cmd) { |
| 684 | case CPU_PM_ENTER: |
| 685 | gic_cpu_save(i); |
| 686 | break; |
| 687 | case CPU_PM_ENTER_FAILED: |
| 688 | case CPU_PM_EXIT: |
| 689 | gic_cpu_restore(i); |
| 690 | break; |
| 691 | case CPU_CLUSTER_PM_ENTER: |
| 692 | gic_dist_save(i); |
| 693 | break; |
| 694 | case CPU_CLUSTER_PM_ENTER_FAILED: |
| 695 | case CPU_CLUSTER_PM_EXIT: |
| 696 | gic_dist_restore(i); |
| 697 | break; |
| 698 | } |
| 699 | } |
| 700 | |
| 701 | return NOTIFY_OK; |
| 702 | } |
| 703 | |
| 704 | static struct notifier_block gic_notifier_block = { |
| 705 | .notifier_call = gic_notifier, |
| 706 | }; |
| 707 | |
| 708 | static void __init gic_pm_init(struct gic_chip_data *gic) |
| 709 | { |
| 710 | gic->saved_ppi_enable = __alloc_percpu(DIV_ROUND_UP(32, 32) * 4, |
| 711 | sizeof(u32)); |
| 712 | BUG_ON(!gic->saved_ppi_enable); |
| 713 | |
| 714 | gic->saved_ppi_conf = __alloc_percpu(DIV_ROUND_UP(32, 16) * 4, |
| 715 | sizeof(u32)); |
| 716 | BUG_ON(!gic->saved_ppi_conf); |
| 717 | |
Marc Zyngier | abdd7b9 | 2011-11-25 17:58:19 +0100 | [diff] [blame] | 718 | if (gic == &gic_data[0]) |
| 719 | cpu_pm_register_notifier(&gic_notifier_block); |
Colin Cross | 254056f | 2011-02-10 12:54:10 -0800 | [diff] [blame] | 720 | } |
| 721 | #else |
| 722 | static void __init gic_pm_init(struct gic_chip_data *gic) |
| 723 | { |
| 724 | } |
| 725 | #endif |
| 726 | |
Rob Herring | b1cffeb | 2012-11-26 15:05:48 -0600 | [diff] [blame] | 727 | #ifdef CONFIG_SMP |
Stephen Boyd | 6859358 | 2014-03-04 17:02:01 -0800 | [diff] [blame] | 728 | static void gic_raise_softirq(const struct cpumask *mask, unsigned int irq) |
Rob Herring | b1cffeb | 2012-11-26 15:05:48 -0600 | [diff] [blame] | 729 | { |
| 730 | int cpu; |
Nicolas Pitre | 1a6b69b | 2012-04-12 01:40:31 -0400 | [diff] [blame] | 731 | unsigned long flags, map = 0; |
| 732 | |
| 733 | raw_spin_lock_irqsave(&irq_controller_lock, flags); |
Rob Herring | b1cffeb | 2012-11-26 15:05:48 -0600 | [diff] [blame] | 734 | |
| 735 | /* Convert our logical CPU mask into a physical one. */ |
| 736 | for_each_cpu(cpu, mask) |
Javi Merino | 91bdf0d | 2013-02-19 13:52:22 +0000 | [diff] [blame] | 737 | map |= gic_cpu_map[cpu]; |
Rob Herring | b1cffeb | 2012-11-26 15:05:48 -0600 | [diff] [blame] | 738 | |
| 739 | /* |
| 740 | * Ensure that stores to Normal memory are visible to the |
Will Deacon | 8adbf57 | 2014-02-20 17:42:07 +0000 | [diff] [blame] | 741 | * other CPUs before they observe us issuing the IPI. |
Rob Herring | b1cffeb | 2012-11-26 15:05:48 -0600 | [diff] [blame] | 742 | */ |
Will Deacon | 8adbf57 | 2014-02-20 17:42:07 +0000 | [diff] [blame] | 743 | dmb(ishst); |
Rob Herring | b1cffeb | 2012-11-26 15:05:48 -0600 | [diff] [blame] | 744 | |
| 745 | /* this always happens on GIC0 */ |
| 746 | writel_relaxed(map << 16 | irq, gic_data_dist_base(&gic_data[0]) + GIC_DIST_SOFTINT); |
Nicolas Pitre | 1a6b69b | 2012-04-12 01:40:31 -0400 | [diff] [blame] | 747 | |
| 748 | raw_spin_unlock_irqrestore(&irq_controller_lock, flags); |
| 749 | } |
| 750 | #endif |
| 751 | |
| 752 | #ifdef CONFIG_BL_SWITCHER |
| 753 | /* |
Nicolas Pitre | 14d2ca6 | 2012-11-28 18:48:19 -0500 | [diff] [blame] | 754 | * gic_send_sgi - send a SGI directly to given CPU interface number |
| 755 | * |
| 756 | * cpu_id: the ID for the destination CPU interface |
| 757 | * irq: the IPI number to send a SGI for |
| 758 | */ |
| 759 | void gic_send_sgi(unsigned int cpu_id, unsigned int irq) |
| 760 | { |
| 761 | BUG_ON(cpu_id >= NR_GIC_CPU_IF); |
| 762 | cpu_id = 1 << cpu_id; |
| 763 | /* this always happens on GIC0 */ |
| 764 | writel_relaxed((cpu_id << 16) | irq, gic_data_dist_base(&gic_data[0]) + GIC_DIST_SOFTINT); |
| 765 | } |
| 766 | |
| 767 | /* |
Nicolas Pitre | ed96762 | 2012-07-05 21:33:26 -0400 | [diff] [blame] | 768 | * gic_get_cpu_id - get the CPU interface ID for the specified CPU |
| 769 | * |
| 770 | * @cpu: the logical CPU number to get the GIC ID for. |
| 771 | * |
| 772 | * Return the CPU interface ID for the given logical CPU number, |
| 773 | * or -1 if the CPU number is too large or the interface ID is |
| 774 | * unknown (more than one bit set). |
| 775 | */ |
| 776 | int gic_get_cpu_id(unsigned int cpu) |
| 777 | { |
| 778 | unsigned int cpu_bit; |
| 779 | |
| 780 | if (cpu >= NR_GIC_CPU_IF) |
| 781 | return -1; |
| 782 | cpu_bit = gic_cpu_map[cpu]; |
| 783 | if (cpu_bit & (cpu_bit - 1)) |
| 784 | return -1; |
| 785 | return __ffs(cpu_bit); |
| 786 | } |
| 787 | |
| 788 | /* |
Nicolas Pitre | 1a6b69b | 2012-04-12 01:40:31 -0400 | [diff] [blame] | 789 | * gic_migrate_target - migrate IRQs to another CPU interface |
| 790 | * |
| 791 | * @new_cpu_id: the CPU target ID to migrate IRQs to |
| 792 | * |
| 793 | * Migrate all peripheral interrupts with a target matching the current CPU |
| 794 | * to the interface corresponding to @new_cpu_id. The CPU interface mapping |
| 795 | * is also updated. Targets to other CPU interfaces are unchanged. |
| 796 | * This must be called with IRQs locally disabled. |
| 797 | */ |
| 798 | void gic_migrate_target(unsigned int new_cpu_id) |
| 799 | { |
| 800 | unsigned int cur_cpu_id, gic_irqs, gic_nr = 0; |
| 801 | void __iomem *dist_base; |
| 802 | int i, ror_val, cpu = smp_processor_id(); |
| 803 | u32 val, cur_target_mask, active_mask; |
| 804 | |
| 805 | if (gic_nr >= MAX_GIC_NR) |
| 806 | BUG(); |
| 807 | |
| 808 | dist_base = gic_data_dist_base(&gic_data[gic_nr]); |
| 809 | if (!dist_base) |
| 810 | return; |
| 811 | gic_irqs = gic_data[gic_nr].gic_irqs; |
| 812 | |
| 813 | cur_cpu_id = __ffs(gic_cpu_map[cpu]); |
| 814 | cur_target_mask = 0x01010101 << cur_cpu_id; |
| 815 | ror_val = (cur_cpu_id - new_cpu_id) & 31; |
| 816 | |
| 817 | raw_spin_lock(&irq_controller_lock); |
| 818 | |
| 819 | /* Update the target interface for this logical CPU */ |
| 820 | gic_cpu_map[cpu] = 1 << new_cpu_id; |
| 821 | |
| 822 | /* |
| 823 | * Find all the peripheral interrupts targetting the current |
| 824 | * CPU interface and migrate them to the new CPU interface. |
| 825 | * We skip DIST_TARGET 0 to 7 as they are read-only. |
| 826 | */ |
| 827 | for (i = 8; i < DIV_ROUND_UP(gic_irqs, 4); i++) { |
| 828 | val = readl_relaxed(dist_base + GIC_DIST_TARGET + i * 4); |
| 829 | active_mask = val & cur_target_mask; |
| 830 | if (active_mask) { |
| 831 | val &= ~active_mask; |
| 832 | val |= ror32(active_mask, ror_val); |
| 833 | writel_relaxed(val, dist_base + GIC_DIST_TARGET + i*4); |
| 834 | } |
| 835 | } |
| 836 | |
| 837 | raw_spin_unlock(&irq_controller_lock); |
| 838 | |
| 839 | /* |
| 840 | * Now let's migrate and clear any potential SGIs that might be |
| 841 | * pending for us (cur_cpu_id). Since GIC_DIST_SGI_PENDING_SET |
| 842 | * is a banked register, we can only forward the SGI using |
| 843 | * GIC_DIST_SOFTINT. The original SGI source is lost but Linux |
| 844 | * doesn't use that information anyway. |
| 845 | * |
| 846 | * For the same reason we do not adjust SGI source information |
| 847 | * for previously sent SGIs by us to other CPUs either. |
| 848 | */ |
| 849 | for (i = 0; i < 16; i += 4) { |
| 850 | int j; |
| 851 | val = readl_relaxed(dist_base + GIC_DIST_SGI_PENDING_SET + i); |
| 852 | if (!val) |
| 853 | continue; |
| 854 | writel_relaxed(val, dist_base + GIC_DIST_SGI_PENDING_CLEAR + i); |
| 855 | for (j = i; j < i + 4; j++) { |
| 856 | if (val & 0xff) |
| 857 | writel_relaxed((1 << (new_cpu_id + 16)) | j, |
| 858 | dist_base + GIC_DIST_SOFTINT); |
| 859 | val >>= 8; |
| 860 | } |
| 861 | } |
Rob Herring | b1cffeb | 2012-11-26 15:05:48 -0600 | [diff] [blame] | 862 | } |
Nicolas Pitre | eeb4465 | 2012-11-28 18:17:25 -0500 | [diff] [blame] | 863 | |
| 864 | /* |
| 865 | * gic_get_sgir_physaddr - get the physical address for the SGI register |
| 866 | * |
| 867 | * REturn the physical address of the SGI register to be used |
| 868 | * by some early assembly code when the kernel is not yet available. |
| 869 | */ |
| 870 | static unsigned long gic_dist_physaddr; |
| 871 | |
| 872 | unsigned long gic_get_sgir_physaddr(void) |
| 873 | { |
| 874 | if (!gic_dist_physaddr) |
| 875 | return 0; |
| 876 | return gic_dist_physaddr + GIC_DIST_SOFTINT; |
| 877 | } |
| 878 | |
| 879 | void __init gic_init_physaddr(struct device_node *node) |
| 880 | { |
| 881 | struct resource res; |
| 882 | if (of_address_to_resource(node, 0, &res) == 0) { |
| 883 | gic_dist_physaddr = res.start; |
| 884 | pr_info("GIC physical location is %#lx\n", gic_dist_physaddr); |
| 885 | } |
| 886 | } |
| 887 | |
| 888 | #else |
| 889 | #define gic_init_physaddr(node) do { } while (0) |
Rob Herring | b1cffeb | 2012-11-26 15:05:48 -0600 | [diff] [blame] | 890 | #endif |
| 891 | |
Grant Likely | 7529495 | 2012-02-14 14:06:57 -0700 | [diff] [blame] | 892 | static int gic_irq_domain_map(struct irq_domain *d, unsigned int irq, |
| 893 | irq_hw_number_t hw) |
| 894 | { |
Marc Zyngier | 0b996fd | 2015-08-26 17:00:44 +0100 | [diff] [blame] | 895 | struct irq_chip *chip = &gic_chip; |
| 896 | |
| 897 | if (static_key_true(&supports_deactivate)) { |
| 898 | if (d->host_data == (void *)&gic_data[0]) |
| 899 | chip = &gic_eoimode1_chip; |
| 900 | } |
| 901 | |
Grant Likely | 7529495 | 2012-02-14 14:06:57 -0700 | [diff] [blame] | 902 | if (hw < 32) { |
| 903 | irq_set_percpu_devid(irq); |
Marc Zyngier | 0b996fd | 2015-08-26 17:00:44 +0100 | [diff] [blame] | 904 | irq_domain_set_info(d, irq, hw, chip, d->host_data, |
Yingjoe Chen | 9a1091e | 2014-11-25 16:04:19 +0800 | [diff] [blame] | 905 | handle_percpu_devid_irq, NULL, NULL); |
Rob Herring | d17cab4 | 2015-08-29 18:01:22 -0500 | [diff] [blame] | 906 | irq_set_status_flags(irq, IRQ_NOAUTOEN); |
Grant Likely | 7529495 | 2012-02-14 14:06:57 -0700 | [diff] [blame] | 907 | } else { |
Marc Zyngier | 0b996fd | 2015-08-26 17:00:44 +0100 | [diff] [blame] | 908 | irq_domain_set_info(d, irq, hw, chip, d->host_data, |
Yingjoe Chen | 9a1091e | 2014-11-25 16:04:19 +0800 | [diff] [blame] | 909 | handle_fasteoi_irq, NULL, NULL); |
Rob Herring | d17cab4 | 2015-08-29 18:01:22 -0500 | [diff] [blame] | 910 | irq_set_probe(irq); |
Grant Likely | 7529495 | 2012-02-14 14:06:57 -0700 | [diff] [blame] | 911 | } |
Grant Likely | 7529495 | 2012-02-14 14:06:57 -0700 | [diff] [blame] | 912 | return 0; |
| 913 | } |
| 914 | |
Sricharan R | 006e983 | 2013-12-03 15:57:22 +0530 | [diff] [blame] | 915 | static void gic_irq_domain_unmap(struct irq_domain *d, unsigned int irq) |
| 916 | { |
Sricharan R | 006e983 | 2013-12-03 15:57:22 +0530 | [diff] [blame] | 917 | } |
| 918 | |
Grant Likely | 7bb69ba | 2012-02-14 14:06:48 -0700 | [diff] [blame] | 919 | static int gic_irq_domain_xlate(struct irq_domain *d, |
| 920 | struct device_node *controller, |
| 921 | const u32 *intspec, unsigned int intsize, |
| 922 | unsigned long *out_hwirq, unsigned int *out_type) |
Rob Herring | b3f7ed0 | 2011-09-28 21:27:52 -0500 | [diff] [blame] | 923 | { |
Sricharan R | 006e983 | 2013-12-03 15:57:22 +0530 | [diff] [blame] | 924 | unsigned long ret = 0; |
| 925 | |
Marc Zyngier | 5d4c9bc | 2015-10-13 12:51:29 +0100 | [diff] [blame] | 926 | if (irq_domain_get_of_node(d) != controller) |
Rob Herring | b3f7ed0 | 2011-09-28 21:27:52 -0500 | [diff] [blame] | 927 | return -EINVAL; |
| 928 | if (intsize < 3) |
| 929 | return -EINVAL; |
| 930 | |
| 931 | /* Get the interrupt number and add 16 to skip over SGIs */ |
| 932 | *out_hwirq = intspec[1] + 16; |
| 933 | |
| 934 | /* For SPIs, we need to add 16 more to get the GIC irq ID number */ |
Marc Zyngier | a5561c3 | 2015-03-11 15:43:46 +0000 | [diff] [blame] | 935 | if (!intspec[0]) |
| 936 | *out_hwirq += 16; |
Rob Herring | b3f7ed0 | 2011-09-28 21:27:52 -0500 | [diff] [blame] | 937 | |
| 938 | *out_type = intspec[2] & IRQ_TYPE_SENSE_MASK; |
Sricharan R | 006e983 | 2013-12-03 15:57:22 +0530 | [diff] [blame] | 939 | |
| 940 | return ret; |
Rob Herring | b3f7ed0 | 2011-09-28 21:27:52 -0500 | [diff] [blame] | 941 | } |
Rob Herring | b3f7ed0 | 2011-09-28 21:27:52 -0500 | [diff] [blame] | 942 | |
Marc Zyngier | f833f57 | 2015-10-13 12:51:33 +0100 | [diff] [blame] | 943 | static int gic_irq_domain_translate(struct irq_domain *d, |
| 944 | struct irq_fwspec *fwspec, |
| 945 | unsigned long *hwirq, |
| 946 | unsigned int *type) |
| 947 | { |
| 948 | if (is_of_node(fwspec->fwnode)) { |
| 949 | if (fwspec->param_count < 3) |
| 950 | return -EINVAL; |
| 951 | |
| 952 | /* Get the interrupt number and add 16 to skip over SGIs */ |
| 953 | *hwirq = fwspec->param[1] + 16; |
| 954 | |
| 955 | /* |
| 956 | * For SPIs, we need to add 16 more to get the GIC irq |
| 957 | * ID number |
| 958 | */ |
| 959 | if (!fwspec->param[0]) |
| 960 | *hwirq += 16; |
| 961 | |
| 962 | *type = fwspec->param[2] & IRQ_TYPE_SENSE_MASK; |
| 963 | return 0; |
| 964 | } |
| 965 | |
| 966 | return -EINVAL; |
| 967 | } |
| 968 | |
Catalin Marinas | c011470 | 2013-01-14 18:05:37 +0000 | [diff] [blame] | 969 | #ifdef CONFIG_SMP |
Paul Gortmaker | 8c37bb3 | 2013-06-19 11:32:08 -0400 | [diff] [blame] | 970 | static int gic_secondary_init(struct notifier_block *nfb, unsigned long action, |
| 971 | void *hcpu) |
Catalin Marinas | c011470 | 2013-01-14 18:05:37 +0000 | [diff] [blame] | 972 | { |
Shawn Guo | 8b6fd65 | 2013-06-12 19:30:27 +0800 | [diff] [blame] | 973 | if (action == CPU_STARTING || action == CPU_STARTING_FROZEN) |
Catalin Marinas | c011470 | 2013-01-14 18:05:37 +0000 | [diff] [blame] | 974 | gic_cpu_init(&gic_data[0]); |
| 975 | return NOTIFY_OK; |
| 976 | } |
| 977 | |
| 978 | /* |
| 979 | * Notifier for enabling the GIC CPU interface. Set an arbitrarily high |
| 980 | * priority because the GIC needs to be up before the ARM generic timers. |
| 981 | */ |
Paul Gortmaker | 8c37bb3 | 2013-06-19 11:32:08 -0400 | [diff] [blame] | 982 | static struct notifier_block gic_cpu_notifier = { |
Catalin Marinas | c011470 | 2013-01-14 18:05:37 +0000 | [diff] [blame] | 983 | .notifier_call = gic_secondary_init, |
| 984 | .priority = 100, |
| 985 | }; |
| 986 | #endif |
| 987 | |
Yingjoe Chen | 9a1091e | 2014-11-25 16:04:19 +0800 | [diff] [blame] | 988 | static int gic_irq_domain_alloc(struct irq_domain *domain, unsigned int virq, |
| 989 | unsigned int nr_irqs, void *arg) |
| 990 | { |
| 991 | int i, ret; |
| 992 | irq_hw_number_t hwirq; |
| 993 | unsigned int type = IRQ_TYPE_NONE; |
Marc Zyngier | f833f57 | 2015-10-13 12:51:33 +0100 | [diff] [blame] | 994 | struct irq_fwspec *fwspec = arg; |
Yingjoe Chen | 9a1091e | 2014-11-25 16:04:19 +0800 | [diff] [blame] | 995 | |
Marc Zyngier | f833f57 | 2015-10-13 12:51:33 +0100 | [diff] [blame] | 996 | ret = gic_irq_domain_translate(domain, fwspec, &hwirq, &type); |
Yingjoe Chen | 9a1091e | 2014-11-25 16:04:19 +0800 | [diff] [blame] | 997 | if (ret) |
| 998 | return ret; |
| 999 | |
| 1000 | for (i = 0; i < nr_irqs; i++) |
| 1001 | gic_irq_domain_map(domain, virq + i, hwirq + i); |
| 1002 | |
| 1003 | return 0; |
| 1004 | } |
| 1005 | |
| 1006 | static const struct irq_domain_ops gic_irq_domain_hierarchy_ops = { |
Marc Zyngier | f833f57 | 2015-10-13 12:51:33 +0100 | [diff] [blame] | 1007 | .translate = gic_irq_domain_translate, |
Yingjoe Chen | 9a1091e | 2014-11-25 16:04:19 +0800 | [diff] [blame] | 1008 | .alloc = gic_irq_domain_alloc, |
| 1009 | .free = irq_domain_free_irqs_top, |
| 1010 | }; |
| 1011 | |
Stephen Boyd | 6859358 | 2014-03-04 17:02:01 -0800 | [diff] [blame] | 1012 | static const struct irq_domain_ops gic_irq_domain_ops = { |
Grant Likely | 7529495 | 2012-02-14 14:06:57 -0700 | [diff] [blame] | 1013 | .map = gic_irq_domain_map, |
Sricharan R | 006e983 | 2013-12-03 15:57:22 +0530 | [diff] [blame] | 1014 | .unmap = gic_irq_domain_unmap, |
Grant Likely | 7bb69ba | 2012-02-14 14:06:48 -0700 | [diff] [blame] | 1015 | .xlate = gic_irq_domain_xlate, |
Rob Herring | 4294f8ba | 2011-09-28 21:25:31 -0500 | [diff] [blame] | 1016 | }; |
| 1017 | |
Marc Zyngier | 4a6ac30 | 2015-09-01 10:08:53 +0100 | [diff] [blame] | 1018 | static void __init __gic_init_bases(unsigned int gic_nr, int irq_start, |
Marc Zyngier | db0d4db | 2011-11-12 16:09:49 +0000 | [diff] [blame] | 1019 | void __iomem *dist_base, void __iomem *cpu_base, |
Grant Likely | 7529495 | 2012-02-14 14:06:57 -0700 | [diff] [blame] | 1020 | u32 percpu_offset, struct device_node *node) |
Russell King | b580b89 | 2010-12-04 15:55:14 +0000 | [diff] [blame] | 1021 | { |
Grant Likely | 7529495 | 2012-02-14 14:06:57 -0700 | [diff] [blame] | 1022 | irq_hw_number_t hwirq_base; |
Russell King | bef8f9e | 2010-12-04 16:50:58 +0000 | [diff] [blame] | 1023 | struct gic_chip_data *gic; |
Nicolas Pitre | 384a290 | 2012-04-11 18:55:48 -0400 | [diff] [blame] | 1024 | int gic_irqs, irq_base, i; |
Russell King | bef8f9e | 2010-12-04 16:50:58 +0000 | [diff] [blame] | 1025 | |
| 1026 | BUG_ON(gic_nr >= MAX_GIC_NR); |
| 1027 | |
Marc Zyngier | 76e52dd | 2015-09-30 12:01:16 +0100 | [diff] [blame] | 1028 | gic_check_cpu_features(); |
| 1029 | |
Russell King | bef8f9e | 2010-12-04 16:50:58 +0000 | [diff] [blame] | 1030 | gic = &gic_data[gic_nr]; |
Marc Zyngier | db0d4db | 2011-11-12 16:09:49 +0000 | [diff] [blame] | 1031 | #ifdef CONFIG_GIC_NON_BANKED |
| 1032 | if (percpu_offset) { /* Frankein-GIC without banked registers... */ |
| 1033 | unsigned int cpu; |
| 1034 | |
| 1035 | gic->dist_base.percpu_base = alloc_percpu(void __iomem *); |
| 1036 | gic->cpu_base.percpu_base = alloc_percpu(void __iomem *); |
| 1037 | if (WARN_ON(!gic->dist_base.percpu_base || |
| 1038 | !gic->cpu_base.percpu_base)) { |
| 1039 | free_percpu(gic->dist_base.percpu_base); |
| 1040 | free_percpu(gic->cpu_base.percpu_base); |
| 1041 | return; |
| 1042 | } |
| 1043 | |
| 1044 | for_each_possible_cpu(cpu) { |
Tomasz Figa | 29e697b | 2014-07-17 17:23:44 +0200 | [diff] [blame] | 1045 | u32 mpidr = cpu_logical_map(cpu); |
| 1046 | u32 core_id = MPIDR_AFFINITY_LEVEL(mpidr, 0); |
| 1047 | unsigned long offset = percpu_offset * core_id; |
Marc Zyngier | db0d4db | 2011-11-12 16:09:49 +0000 | [diff] [blame] | 1048 | *per_cpu_ptr(gic->dist_base.percpu_base, cpu) = dist_base + offset; |
| 1049 | *per_cpu_ptr(gic->cpu_base.percpu_base, cpu) = cpu_base + offset; |
| 1050 | } |
| 1051 | |
| 1052 | gic_set_base_accessor(gic, gic_get_percpu_base); |
| 1053 | } else |
| 1054 | #endif |
| 1055 | { /* Normal, sane GIC... */ |
| 1056 | WARN(percpu_offset, |
| 1057 | "GIC_NON_BANKED not enabled, ignoring %08x offset!", |
| 1058 | percpu_offset); |
| 1059 | gic->dist_base.common_base = dist_base; |
| 1060 | gic->cpu_base.common_base = cpu_base; |
| 1061 | gic_set_base_accessor(gic, gic_get_common_base); |
| 1062 | } |
Russell King | bef8f9e | 2010-12-04 16:50:58 +0000 | [diff] [blame] | 1063 | |
Rob Herring | 4294f8ba | 2011-09-28 21:25:31 -0500 | [diff] [blame] | 1064 | /* |
Rob Herring | 4294f8ba | 2011-09-28 21:25:31 -0500 | [diff] [blame] | 1065 | * Find out how many interrupts are supported. |
| 1066 | * The GIC only supports up to 1020 interrupt sources. |
| 1067 | */ |
Marc Zyngier | db0d4db | 2011-11-12 16:09:49 +0000 | [diff] [blame] | 1068 | gic_irqs = readl_relaxed(gic_data_dist_base(gic) + GIC_DIST_CTR) & 0x1f; |
Rob Herring | 4294f8ba | 2011-09-28 21:25:31 -0500 | [diff] [blame] | 1069 | gic_irqs = (gic_irqs + 1) * 32; |
| 1070 | if (gic_irqs > 1020) |
| 1071 | gic_irqs = 1020; |
| 1072 | gic->gic_irqs = gic_irqs; |
| 1073 | |
Yingjoe Chen | 9a1091e | 2014-11-25 16:04:19 +0800 | [diff] [blame] | 1074 | if (node) { /* DT case */ |
Marc Zyngier | a5561c3 | 2015-03-11 15:43:46 +0000 | [diff] [blame] | 1075 | gic->domain = irq_domain_add_linear(node, gic_irqs, |
| 1076 | &gic_irq_domain_hierarchy_ops, |
| 1077 | gic); |
Yingjoe Chen | 9a1091e | 2014-11-25 16:04:19 +0800 | [diff] [blame] | 1078 | } else { /* Non-DT case */ |
| 1079 | /* |
| 1080 | * For primary GICs, skip over SGIs. |
| 1081 | * For secondary GICs, skip over PPIs, too. |
| 1082 | */ |
| 1083 | if (gic_nr == 0 && (irq_start & 31) > 0) { |
| 1084 | hwirq_base = 16; |
| 1085 | if (irq_start != -1) |
| 1086 | irq_start = (irq_start & ~31) + 16; |
| 1087 | } else { |
| 1088 | hwirq_base = 32; |
| 1089 | } |
| 1090 | |
| 1091 | gic_irqs -= hwirq_base; /* calculate # of irqs to allocate */ |
| 1092 | |
Sricharan R | 006e983 | 2013-12-03 15:57:22 +0530 | [diff] [blame] | 1093 | irq_base = irq_alloc_descs(irq_start, 16, gic_irqs, |
| 1094 | numa_node_id()); |
| 1095 | if (IS_ERR_VALUE(irq_base)) { |
| 1096 | WARN(1, "Cannot allocate irq_descs @ IRQ%d, assuming pre-allocated\n", |
| 1097 | irq_start); |
| 1098 | irq_base = irq_start; |
| 1099 | } |
| 1100 | |
| 1101 | gic->domain = irq_domain_add_legacy(node, gic_irqs, irq_base, |
| 1102 | hwirq_base, &gic_irq_domain_ops, gic); |
Rob Herring | f37a53c | 2011-10-21 17:14:27 -0500 | [diff] [blame] | 1103 | } |
Sricharan R | 006e983 | 2013-12-03 15:57:22 +0530 | [diff] [blame] | 1104 | |
Grant Likely | 7529495 | 2012-02-14 14:06:57 -0700 | [diff] [blame] | 1105 | if (WARN_ON(!gic->domain)) |
| 1106 | return; |
Russell King | bef8f9e | 2010-12-04 16:50:58 +0000 | [diff] [blame] | 1107 | |
Mark Rutland | 08332df | 2013-11-28 14:21:40 +0000 | [diff] [blame] | 1108 | if (gic_nr == 0) { |
Jon Hunter | 567e5a0 | 2015-07-31 09:44:11 +0100 | [diff] [blame] | 1109 | /* |
| 1110 | * Initialize the CPU interface map to all CPUs. |
| 1111 | * It will be refined as each CPU probes its ID. |
| 1112 | * This is only necessary for the primary GIC. |
| 1113 | */ |
| 1114 | for (i = 0; i < NR_GIC_CPU_IF; i++) |
| 1115 | gic_cpu_map[i] = 0xff; |
Rob Herring | b1cffeb | 2012-11-26 15:05:48 -0600 | [diff] [blame] | 1116 | #ifdef CONFIG_SMP |
Mark Rutland | 08332df | 2013-11-28 14:21:40 +0000 | [diff] [blame] | 1117 | set_smp_cross_call(gic_raise_softirq); |
| 1118 | register_cpu_notifier(&gic_cpu_notifier); |
Rob Herring | b1cffeb | 2012-11-26 15:05:48 -0600 | [diff] [blame] | 1119 | #endif |
Mark Rutland | 08332df | 2013-11-28 14:21:40 +0000 | [diff] [blame] | 1120 | set_handle_irq(gic_handle_irq); |
Marc Zyngier | 0b996fd | 2015-08-26 17:00:44 +0100 | [diff] [blame] | 1121 | if (static_key_true(&supports_deactivate)) |
| 1122 | pr_info("GIC: Using split EOI/Deactivate mode\n"); |
Mark Rutland | 08332df | 2013-11-28 14:21:40 +0000 | [diff] [blame] | 1123 | } |
Rob Herring | cfed7d6 | 2012-11-03 12:59:51 -0500 | [diff] [blame] | 1124 | |
Rob Herring | 4294f8ba | 2011-09-28 21:25:31 -0500 | [diff] [blame] | 1125 | gic_dist_init(gic); |
Russell King | bef8f9e | 2010-12-04 16:50:58 +0000 | [diff] [blame] | 1126 | gic_cpu_init(gic); |
Colin Cross | 254056f | 2011-02-10 12:54:10 -0800 | [diff] [blame] | 1127 | gic_pm_init(gic); |
Russell King | b580b89 | 2010-12-04 15:55:14 +0000 | [diff] [blame] | 1128 | } |
| 1129 | |
Marc Zyngier | e81a7cd | 2015-10-13 12:51:39 +0100 | [diff] [blame^] | 1130 | void __init gic_init(unsigned int gic_nr, int irq_start, |
| 1131 | void __iomem *dist_base, void __iomem *cpu_base) |
Marc Zyngier | 4a6ac30 | 2015-09-01 10:08:53 +0100 | [diff] [blame] | 1132 | { |
| 1133 | /* |
| 1134 | * Non-DT/ACPI systems won't run a hypervisor, so let's not |
| 1135 | * bother with these... |
| 1136 | */ |
| 1137 | static_key_slow_dec(&supports_deactivate); |
Marc Zyngier | e81a7cd | 2015-10-13 12:51:39 +0100 | [diff] [blame^] | 1138 | __gic_init_bases(gic_nr, irq_start, dist_base, cpu_base, 0, NULL); |
Marc Zyngier | 4a6ac30 | 2015-09-01 10:08:53 +0100 | [diff] [blame] | 1139 | } |
| 1140 | |
Rob Herring | b3f7ed0 | 2011-09-28 21:27:52 -0500 | [diff] [blame] | 1141 | #ifdef CONFIG_OF |
Sachin Kamat | 46f101d | 2013-03-13 15:05:15 +0530 | [diff] [blame] | 1142 | static int gic_cnt __initdata; |
Rob Herring | b3f7ed0 | 2011-09-28 21:27:52 -0500 | [diff] [blame] | 1143 | |
Marc Zyngier | 12e1406 | 2015-09-13 12:14:31 +0100 | [diff] [blame] | 1144 | static bool gic_check_eoimode(struct device_node *node, void __iomem **base) |
| 1145 | { |
| 1146 | struct resource cpuif_res; |
| 1147 | |
| 1148 | of_address_to_resource(node, 1, &cpuif_res); |
| 1149 | |
| 1150 | if (!is_hyp_mode_available()) |
| 1151 | return false; |
| 1152 | if (resource_size(&cpuif_res) < SZ_8K) |
| 1153 | return false; |
| 1154 | if (resource_size(&cpuif_res) == SZ_128K) { |
| 1155 | u32 val_low, val_high; |
| 1156 | |
| 1157 | /* |
| 1158 | * Verify that we have the first 4kB of a GIC400 |
| 1159 | * aliased over the first 64kB by checking the |
| 1160 | * GICC_IIDR register on both ends. |
| 1161 | */ |
| 1162 | val_low = readl_relaxed(*base + GIC_CPU_IDENT); |
| 1163 | val_high = readl_relaxed(*base + GIC_CPU_IDENT + 0xf000); |
| 1164 | if ((val_low & 0xffff0fff) != 0x0202043B || |
| 1165 | val_low != val_high) |
| 1166 | return false; |
| 1167 | |
| 1168 | /* |
| 1169 | * Move the base up by 60kB, so that we have a 8kB |
| 1170 | * contiguous region, which allows us to use GICC_DIR |
| 1171 | * at its normal offset. Please pass me that bucket. |
| 1172 | */ |
| 1173 | *base += 0xf000; |
| 1174 | cpuif_res.start += 0xf000; |
| 1175 | pr_warn("GIC: Adjusting CPU interface base to %pa", |
| 1176 | &cpuif_res.start); |
| 1177 | } |
| 1178 | |
| 1179 | return true; |
| 1180 | } |
| 1181 | |
Stephen Boyd | 6859358 | 2014-03-04 17:02:01 -0800 | [diff] [blame] | 1182 | static int __init |
| 1183 | gic_of_init(struct device_node *node, struct device_node *parent) |
Rob Herring | b3f7ed0 | 2011-09-28 21:27:52 -0500 | [diff] [blame] | 1184 | { |
| 1185 | void __iomem *cpu_base; |
| 1186 | void __iomem *dist_base; |
Marc Zyngier | db0d4db | 2011-11-12 16:09:49 +0000 | [diff] [blame] | 1187 | u32 percpu_offset; |
Rob Herring | b3f7ed0 | 2011-09-28 21:27:52 -0500 | [diff] [blame] | 1188 | int irq; |
Rob Herring | b3f7ed0 | 2011-09-28 21:27:52 -0500 | [diff] [blame] | 1189 | |
| 1190 | if (WARN_ON(!node)) |
| 1191 | return -ENODEV; |
| 1192 | |
| 1193 | dist_base = of_iomap(node, 0); |
| 1194 | WARN(!dist_base, "unable to map gic dist registers\n"); |
| 1195 | |
| 1196 | cpu_base = of_iomap(node, 1); |
| 1197 | WARN(!cpu_base, "unable to map gic cpu registers\n"); |
| 1198 | |
Marc Zyngier | 0b996fd | 2015-08-26 17:00:44 +0100 | [diff] [blame] | 1199 | /* |
| 1200 | * Disable split EOI/Deactivate if either HYP is not available |
| 1201 | * or the CPU interface is too small. |
| 1202 | */ |
Marc Zyngier | 12e1406 | 2015-09-13 12:14:31 +0100 | [diff] [blame] | 1203 | if (gic_cnt == 0 && !gic_check_eoimode(node, &cpu_base)) |
Marc Zyngier | 0b996fd | 2015-08-26 17:00:44 +0100 | [diff] [blame] | 1204 | static_key_slow_dec(&supports_deactivate); |
| 1205 | |
Marc Zyngier | db0d4db | 2011-11-12 16:09:49 +0000 | [diff] [blame] | 1206 | if (of_property_read_u32(node, "cpu-offset", &percpu_offset)) |
| 1207 | percpu_offset = 0; |
| 1208 | |
Marc Zyngier | 4a6ac30 | 2015-09-01 10:08:53 +0100 | [diff] [blame] | 1209 | __gic_init_bases(gic_cnt, -1, dist_base, cpu_base, percpu_offset, node); |
Nicolas Pitre | eeb4465 | 2012-11-28 18:17:25 -0500 | [diff] [blame] | 1210 | if (!gic_cnt) |
| 1211 | gic_init_physaddr(node); |
Rob Herring | b3f7ed0 | 2011-09-28 21:27:52 -0500 | [diff] [blame] | 1212 | |
| 1213 | if (parent) { |
| 1214 | irq = irq_of_parse_and_map(node, 0); |
| 1215 | gic_cascade_irq(gic_cnt, irq); |
| 1216 | } |
Suravee Suthikulpanit | 853a33c | 2014-11-25 18:47:22 +0000 | [diff] [blame] | 1217 | |
| 1218 | if (IS_ENABLED(CONFIG_ARM_GIC_V2M)) |
| 1219 | gicv2m_of_init(node, gic_data[gic_cnt].domain); |
| 1220 | |
Rob Herring | b3f7ed0 | 2011-09-28 21:27:52 -0500 | [diff] [blame] | 1221 | gic_cnt++; |
| 1222 | return 0; |
| 1223 | } |
Suravee Suthikulpanit | 144cb08 | 2014-07-15 00:03:03 +0200 | [diff] [blame] | 1224 | IRQCHIP_DECLARE(gic_400, "arm,gic-400", gic_of_init); |
Linus Walleij | fa6e2ee | 2014-10-01 09:29:22 +0200 | [diff] [blame] | 1225 | IRQCHIP_DECLARE(arm11mp_gic, "arm,arm11mp-gic", gic_of_init); |
| 1226 | IRQCHIP_DECLARE(arm1176jzf_dc_gic, "arm,arm1176jzf-devchip-gic", gic_of_init); |
Rob Herring | 81243e4 | 2012-11-20 21:21:40 -0600 | [diff] [blame] | 1227 | IRQCHIP_DECLARE(cortex_a15_gic, "arm,cortex-a15-gic", gic_of_init); |
| 1228 | IRQCHIP_DECLARE(cortex_a9_gic, "arm,cortex-a9-gic", gic_of_init); |
Matthias Brugger | a97e8027 | 2014-07-03 13:58:52 +0200 | [diff] [blame] | 1229 | IRQCHIP_DECLARE(cortex_a7_gic, "arm,cortex-a7-gic", gic_of_init); |
Rob Herring | 81243e4 | 2012-11-20 21:21:40 -0600 | [diff] [blame] | 1230 | IRQCHIP_DECLARE(msm_8660_qgic, "qcom,msm-8660-qgic", gic_of_init); |
| 1231 | IRQCHIP_DECLARE(msm_qgic2, "qcom,msm-qgic2", gic_of_init); |
Geert Uytterhoeven | 8709b9e | 2015-09-14 22:06:43 +0200 | [diff] [blame] | 1232 | IRQCHIP_DECLARE(pl390, "arm,pl390", gic_of_init); |
Rob Herring | 81243e4 | 2012-11-20 21:21:40 -0600 | [diff] [blame] | 1233 | |
Rob Herring | b3f7ed0 | 2011-09-28 21:27:52 -0500 | [diff] [blame] | 1234 | #endif |
Tomasz Nowicki | d60fc38 | 2015-03-24 14:02:49 +0000 | [diff] [blame] | 1235 | |
| 1236 | #ifdef CONFIG_ACPI |
| 1237 | static phys_addr_t dist_phy_base, cpu_phy_base __initdata; |
| 1238 | |
| 1239 | static int __init |
| 1240 | gic_acpi_parse_madt_cpu(struct acpi_subtable_header *header, |
| 1241 | const unsigned long end) |
| 1242 | { |
| 1243 | struct acpi_madt_generic_interrupt *processor; |
| 1244 | phys_addr_t gic_cpu_base; |
| 1245 | static int cpu_base_assigned; |
| 1246 | |
| 1247 | processor = (struct acpi_madt_generic_interrupt *)header; |
| 1248 | |
Al Stone | 99e3e3a | 2015-07-06 17:16:48 -0600 | [diff] [blame] | 1249 | if (BAD_MADT_GICC_ENTRY(processor, end)) |
Tomasz Nowicki | d60fc38 | 2015-03-24 14:02:49 +0000 | [diff] [blame] | 1250 | return -EINVAL; |
| 1251 | |
| 1252 | /* |
| 1253 | * There is no support for non-banked GICv1/2 register in ACPI spec. |
| 1254 | * All CPU interface addresses have to be the same. |
| 1255 | */ |
| 1256 | gic_cpu_base = processor->base_address; |
| 1257 | if (cpu_base_assigned && gic_cpu_base != cpu_phy_base) |
| 1258 | return -EINVAL; |
| 1259 | |
| 1260 | cpu_phy_base = gic_cpu_base; |
| 1261 | cpu_base_assigned = 1; |
| 1262 | return 0; |
| 1263 | } |
| 1264 | |
| 1265 | static int __init |
| 1266 | gic_acpi_parse_madt_distributor(struct acpi_subtable_header *header, |
| 1267 | const unsigned long end) |
| 1268 | { |
| 1269 | struct acpi_madt_generic_distributor *dist; |
| 1270 | |
| 1271 | dist = (struct acpi_madt_generic_distributor *)header; |
| 1272 | |
| 1273 | if (BAD_MADT_ENTRY(dist, end)) |
| 1274 | return -EINVAL; |
| 1275 | |
| 1276 | dist_phy_base = dist->base_address; |
| 1277 | return 0; |
| 1278 | } |
| 1279 | |
| 1280 | int __init |
| 1281 | gic_v2_acpi_init(struct acpi_table_header *table) |
| 1282 | { |
| 1283 | void __iomem *cpu_base, *dist_base; |
| 1284 | int count; |
| 1285 | |
| 1286 | /* Collect CPU base addresses */ |
| 1287 | count = acpi_parse_entries(ACPI_SIG_MADT, |
| 1288 | sizeof(struct acpi_table_madt), |
| 1289 | gic_acpi_parse_madt_cpu, table, |
| 1290 | ACPI_MADT_TYPE_GENERIC_INTERRUPT, 0); |
| 1291 | if (count <= 0) { |
| 1292 | pr_err("No valid GICC entries exist\n"); |
| 1293 | return -EINVAL; |
| 1294 | } |
| 1295 | |
| 1296 | /* |
| 1297 | * Find distributor base address. We expect one distributor entry since |
| 1298 | * ACPI 5.1 spec neither support multi-GIC instances nor GIC cascade. |
| 1299 | */ |
| 1300 | count = acpi_parse_entries(ACPI_SIG_MADT, |
| 1301 | sizeof(struct acpi_table_madt), |
| 1302 | gic_acpi_parse_madt_distributor, table, |
| 1303 | ACPI_MADT_TYPE_GENERIC_DISTRIBUTOR, 0); |
| 1304 | if (count <= 0) { |
| 1305 | pr_err("No valid GICD entries exist\n"); |
| 1306 | return -EINVAL; |
| 1307 | } else if (count > 1) { |
| 1308 | pr_err("More than one GICD entry detected\n"); |
| 1309 | return -EINVAL; |
| 1310 | } |
| 1311 | |
| 1312 | cpu_base = ioremap(cpu_phy_base, ACPI_GIC_CPU_IF_MEM_SIZE); |
| 1313 | if (!cpu_base) { |
| 1314 | pr_err("Unable to map GICC registers\n"); |
| 1315 | return -ENOMEM; |
| 1316 | } |
| 1317 | |
| 1318 | dist_base = ioremap(dist_phy_base, ACPI_GICV2_DIST_MEM_SIZE); |
| 1319 | if (!dist_base) { |
| 1320 | pr_err("Unable to map GICD registers\n"); |
| 1321 | iounmap(cpu_base); |
| 1322 | return -ENOMEM; |
| 1323 | } |
| 1324 | |
| 1325 | /* |
Marc Zyngier | 0b996fd | 2015-08-26 17:00:44 +0100 | [diff] [blame] | 1326 | * Disable split EOI/Deactivate if HYP is not available. ACPI |
| 1327 | * guarantees that we'll always have a GICv2, so the CPU |
| 1328 | * interface will always be the right size. |
| 1329 | */ |
| 1330 | if (!is_hyp_mode_available()) |
| 1331 | static_key_slow_dec(&supports_deactivate); |
| 1332 | |
| 1333 | /* |
Tomasz Nowicki | d60fc38 | 2015-03-24 14:02:49 +0000 | [diff] [blame] | 1334 | * Initialize zero GIC instance (no multi-GIC support). Also, set GIC |
| 1335 | * as default IRQ domain to allow for GSI registration and GSI to IRQ |
| 1336 | * number translation (see acpi_register_gsi() and acpi_gsi_to_irq()). |
| 1337 | */ |
Marc Zyngier | 4a6ac30 | 2015-09-01 10:08:53 +0100 | [diff] [blame] | 1338 | __gic_init_bases(0, -1, dist_base, cpu_base, 0, NULL); |
Tomasz Nowicki | d60fc38 | 2015-03-24 14:02:49 +0000 | [diff] [blame] | 1339 | irq_set_default_host(gic_data[0].domain); |
Lorenzo Pieralisi | d8f4f16 | 2015-03-24 17:58:51 +0000 | [diff] [blame] | 1340 | |
| 1341 | acpi_irq_model = ACPI_IRQ_MODEL_GIC; |
Tomasz Nowicki | d60fc38 | 2015-03-24 14:02:49 +0000 | [diff] [blame] | 1342 | return 0; |
| 1343 | } |
| 1344 | #endif |