blob: e7599e760aef3ae76e8247bf3c01cc5f9432efcf [file] [log] [blame]
Rajendra Nayak99e6a4d2008-10-08 17:30:58 +05301/*
2 * linux/arch/arm/mach-omap2/cpuidle34xx.c
3 *
4 * OMAP3 CPU IDLE Routines
5 *
6 * Copyright (C) 2008 Texas Instruments, Inc.
7 * Rajendra Nayak <rnayak@ti.com>
8 *
9 * Copyright (C) 2007 Texas Instruments, Inc.
10 * Karthik Dasu <karthik-dp@ti.com>
11 *
12 * Copyright (C) 2006 Nokia Corporation
13 * Tony Lindgren <tony@atomide.com>
14 *
15 * Copyright (C) 2005 Texas Instruments, Inc.
16 * Richard Woodruff <r-woodruff2@ti.com>
17 *
18 * Based on pm.c for omap2
19 *
20 * This program is free software; you can redistribute it and/or modify
21 * it under the terms of the GNU General Public License version 2 as
22 * published by the Free Software Foundation.
23 */
24
Tero Kristocf228542009-03-20 15:21:02 +020025#include <linux/sched.h>
Rajendra Nayak99e6a4d2008-10-08 17:30:58 +053026#include <linux/cpuidle.h>
Kevin Hilman5698eb42011-11-07 15:58:40 -080027#include <linux/export.h>
Santosh Shilimkarff819da2011-09-03 22:38:27 +053028#include <linux/cpu_pm.h>
Rajendra Nayak99e6a4d2008-10-08 17:30:58 +053029
30#include <plat/prcm.h>
Rajendra Nayak20b01662008-10-08 17:31:22 +053031#include <plat/irqs.h>
Paul Walmsley72e06d02010-12-21 21:05:16 -070032#include "powerdomain.h"
Paul Walmsley1540f2142010-12-21 21:05:15 -070033#include "clockdomain.h"
Rajendra Nayak99e6a4d2008-10-08 17:30:58 +053034
Kevin Hilmanc98e2232008-10-28 17:30:07 -070035#include "pm.h"
Paul Walmsley4814ced2010-10-08 11:40:20 -060036#include "control.h"
Santosh Shilimkarba8bb182011-12-05 09:46:24 +010037#include "common.h"
Kevin Hilmanc98e2232008-10-28 17:30:07 -070038
Rajendra Nayak99e6a4d2008-10-08 17:30:58 +053039#ifdef CONFIG_CPU_IDLE
40
Jean Pihetbadc3032011-05-09 12:02:14 +020041/* Mach specific information to be recorded in the C-state driver_data */
42struct omap3_idle_statedata {
43 u32 mpu_state;
44 u32 core_state;
Jean Pihetbadc3032011-05-09 12:02:14 +020045};
Daniel Lezcano0c2487f2012-04-24 16:05:33 +020046
Daniel Lezcano88c377dd2012-04-24 16:05:34 +020047struct omap3_idle_statedata omap3_idle_data[] = {
48 {
49 .mpu_state = PWRDM_POWER_ON,
50 .core_state = PWRDM_POWER_ON,
51 },
52 {
53 .mpu_state = PWRDM_POWER_ON,
54 .core_state = PWRDM_POWER_ON,
55 },
56 {
57 .mpu_state = PWRDM_POWER_RET,
58 .core_state = PWRDM_POWER_ON,
59 },
60 {
61 .mpu_state = PWRDM_POWER_OFF,
62 .core_state = PWRDM_POWER_ON,
63 },
64 {
65 .mpu_state = PWRDM_POWER_RET,
66 .core_state = PWRDM_POWER_RET,
67 },
68 {
69 .mpu_state = PWRDM_POWER_OFF,
70 .core_state = PWRDM_POWER_RET,
71 },
72 {
73 .mpu_state = PWRDM_POWER_OFF,
74 .core_state = PWRDM_POWER_OFF,
75 },
76};
Jean Pihetbadc3032011-05-09 12:02:14 +020077
78struct powerdomain *mpu_pd, *core_pd, *per_pd, *cam_pd;
Kevin Hilmanbb4de3d2009-12-15 16:37:18 -080079
Peter 'p2' De Schrijver06d8f062009-03-13 18:19:16 +020080static int _cpuidle_allow_idle(struct powerdomain *pwrdm,
81 struct clockdomain *clkdm)
82{
Rajendra Nayak5cd19372011-02-25 16:06:48 -070083 clkdm_allow_idle(clkdm);
Peter 'p2' De Schrijver06d8f062009-03-13 18:19:16 +020084 return 0;
85}
86
87static int _cpuidle_deny_idle(struct powerdomain *pwrdm,
88 struct clockdomain *clkdm)
89{
Rajendra Nayak5cd19372011-02-25 16:06:48 -070090 clkdm_deny_idle(clkdm);
Peter 'p2' De Schrijver06d8f062009-03-13 18:19:16 +020091 return 0;
92}
93
Robert Lee6da45dc2012-03-20 15:22:46 -050094static int __omap3_enter_idle(struct cpuidle_device *dev,
Deepthi Dharwar46bcfad2011-10-28 16:20:42 +053095 struct cpuidle_driver *drv,
Deepthi Dharware978aa72011-10-28 16:20:09 +053096 int index)
Rajendra Nayak99e6a4d2008-10-08 17:30:58 +053097{
Daniel Lezcano6622ac52012-04-24 16:05:35 +020098 struct omap3_idle_statedata *cx = &omap3_idle_data[index];
Kevin Hilmanc98e2232008-10-28 17:30:07 -070099 u32 mpu_state = cx->mpu_state, core_state = cx->core_state;
Rajendra Nayak99e6a4d2008-10-08 17:30:58 +0530100
Rajendra Nayak99e6a4d2008-10-08 17:30:58 +0530101 local_fiq_disable();
102
Jouni Hogander71391782008-10-28 10:59:05 +0200103 pwrdm_set_next_pwrst(mpu_pd, mpu_state);
104 pwrdm_set_next_pwrst(core_pd, core_state);
Rajendra Nayak20b01662008-10-08 17:31:22 +0530105
Tero Kristocf228542009-03-20 15:21:02 +0200106 if (omap_irq_pending() || need_resched())
Rajendra Nayak20b01662008-10-08 17:31:22 +0530107 goto return_sleep_time;
Rajendra Nayak99e6a4d2008-10-08 17:30:58 +0530108
Jean Pihetbadc3032011-05-09 12:02:14 +0200109 /* Deny idle for C1 */
Deepthi Dharware978aa72011-10-28 16:20:09 +0530110 if (index == 0) {
Peter 'p2' De Schrijver06d8f062009-03-13 18:19:16 +0200111 pwrdm_for_each_clkdm(mpu_pd, _cpuidle_deny_idle);
112 pwrdm_for_each_clkdm(core_pd, _cpuidle_deny_idle);
113 }
114
Santosh Shilimkarff819da2011-09-03 22:38:27 +0530115 /*
116 * Call idle CPU PM enter notifier chain so that
117 * VFP context is saved.
118 */
119 if (mpu_state == PWRDM_POWER_OFF)
120 cpu_pm_enter();
121
Rajendra Nayak99e6a4d2008-10-08 17:30:58 +0530122 /* Execute ARM wfi */
123 omap_sram_idle();
124
Santosh Shilimkarff819da2011-09-03 22:38:27 +0530125 /*
126 * Call idle CPU PM enter notifier chain to restore
127 * VFP context.
128 */
129 if (pwrdm_read_prev_pwrst(mpu_pd) == PWRDM_POWER_OFF)
130 cpu_pm_exit();
131
Jean Pihetbadc3032011-05-09 12:02:14 +0200132 /* Re-allow idle for C1 */
Deepthi Dharware978aa72011-10-28 16:20:09 +0530133 if (index == 0) {
Peter 'p2' De Schrijver06d8f062009-03-13 18:19:16 +0200134 pwrdm_for_each_clkdm(mpu_pd, _cpuidle_allow_idle);
135 pwrdm_for_each_clkdm(core_pd, _cpuidle_allow_idle);
136 }
137
Rajendra Nayak20b01662008-10-08 17:31:22 +0530138return_sleep_time:
Rajendra Nayak99e6a4d2008-10-08 17:30:58 +0530139
Rajendra Nayak99e6a4d2008-10-08 17:30:58 +0530140 local_fiq_enable();
141
Deepthi Dharware978aa72011-10-28 16:20:09 +0530142 return index;
Rajendra Nayak99e6a4d2008-10-08 17:30:58 +0530143}
144
145/**
Robert Lee6da45dc2012-03-20 15:22:46 -0500146 * omap3_enter_idle - Programs OMAP3 to enter the specified state
147 * @dev: cpuidle device
148 * @drv: cpuidle driver
149 * @index: the index of state to be entered
150 *
151 * Called from the CPUidle framework to program the device to the
152 * specified target state selected by the governor.
153 */
154static inline int omap3_enter_idle(struct cpuidle_device *dev,
155 struct cpuidle_driver *drv,
156 int index)
157{
158 return cpuidle_wrap_enter(dev, drv, index, __omap3_enter_idle);
159}
160
161/**
Jean Pihet04908912011-05-09 12:02:16 +0200162 * next_valid_state - Find next valid C-state
Sanjeev Premi6af83b32010-01-28 23:16:43 +0530163 * @dev: cpuidle device
Deepthi Dharwar46bcfad2011-10-28 16:20:42 +0530164 * @drv: cpuidle driver
Deepthi Dharware978aa72011-10-28 16:20:09 +0530165 * @index: Index of currently selected c-state
Sanjeev Premi6af83b32010-01-28 23:16:43 +0530166 *
Deepthi Dharware978aa72011-10-28 16:20:09 +0530167 * If the state corresponding to index is valid, index is returned back
168 * to the caller. Else, this function searches for a lower c-state which is
169 * still valid (as defined in omap3_power_states[]) and returns its index.
Jean Pihet04908912011-05-09 12:02:16 +0200170 *
171 * A state is valid if the 'valid' field is enabled and
172 * if it satisfies the enable_off_mode condition.
Sanjeev Premi6af83b32010-01-28 23:16:43 +0530173 */
Deepthi Dharware978aa72011-10-28 16:20:09 +0530174static int next_valid_state(struct cpuidle_device *dev,
Daniel Lezcanoe92a4582012-04-24 16:05:36 +0200175 struct cpuidle_driver *drv, int index)
Sanjeev Premi6af83b32010-01-28 23:16:43 +0530176{
Daniel Lezcano6622ac52012-04-24 16:05:35 +0200177 struct omap3_idle_statedata *cx = &omap3_idle_data[index];
Jean Pihet04908912011-05-09 12:02:16 +0200178 u32 mpu_deepest_state = PWRDM_POWER_RET;
179 u32 core_deepest_state = PWRDM_POWER_RET;
Daniel Lezcanoe92a4582012-04-24 16:05:36 +0200180 int idx;
Deepthi Dharware978aa72011-10-28 16:20:09 +0530181 int next_index = -1;
Jean Pihet04908912011-05-09 12:02:16 +0200182
183 if (enable_off_mode) {
184 mpu_deepest_state = PWRDM_POWER_OFF;
185 /*
186 * Erratum i583: valable for ES rev < Es1.2 on 3630.
187 * CORE OFF mode is not supported in a stable form, restrict
188 * instead the CORE state to RET.
189 */
190 if (!IS_PM34XX_ERRATUM(PM_SDRC_WAKEUP_ERRATUM_i583))
191 core_deepest_state = PWRDM_POWER_OFF;
192 }
Sanjeev Premi6af83b32010-01-28 23:16:43 +0530193
194 /* Check if current state is valid */
Daniel Lezcanof79b5d82012-04-24 16:05:32 +0200195 if ((cx->mpu_state >= mpu_deepest_state) &&
Daniel Lezcanoe92a4582012-04-24 16:05:36 +0200196 (cx->core_state >= core_deepest_state))
Deepthi Dharware978aa72011-10-28 16:20:09 +0530197 return index;
Sanjeev Premi6af83b32010-01-28 23:16:43 +0530198
Daniel Lezcanoe92a4582012-04-24 16:05:36 +0200199 /*
200 * Drop to next valid state.
201 * Start search from the next (lower) state.
202 */
203 for (idx = index - 1; idx >= 0; idx--) {
204 cx = &omap3_idle_data[idx];
205 if ((cx->mpu_state >= mpu_deepest_state) &&
206 (cx->core_state >= core_deepest_state)) {
207 next_index = idx;
208 break;
Sanjeev Premi6af83b32010-01-28 23:16:43 +0530209 }
Sanjeev Premi6af83b32010-01-28 23:16:43 +0530210 }
211
Daniel Lezcanoe92a4582012-04-24 16:05:36 +0200212 /*
213 * C1 is always valid.
214 * So, no need to check for 'next_index == -1' outside
215 * this loop.
216 */
217
Deepthi Dharware978aa72011-10-28 16:20:09 +0530218 return next_index;
Sanjeev Premi6af83b32010-01-28 23:16:43 +0530219}
220
221/**
Rajendra Nayak99e6a4d2008-10-08 17:30:58 +0530222 * omap3_enter_idle_bm - Checks for any bus activity
223 * @dev: cpuidle device
Deepthi Dharwar46bcfad2011-10-28 16:20:42 +0530224 * @drv: cpuidle driver
Deepthi Dharware978aa72011-10-28 16:20:09 +0530225 * @index: array index of target state to be programmed
Rajendra Nayak99e6a4d2008-10-08 17:30:58 +0530226 *
Jean Pihetbadc3032011-05-09 12:02:14 +0200227 * This function checks for any pending activity and then programs
228 * the device to the specified or a safer state.
Rajendra Nayak99e6a4d2008-10-08 17:30:58 +0530229 */
230static int omap3_enter_idle_bm(struct cpuidle_device *dev,
Deepthi Dharwar46bcfad2011-10-28 16:20:42 +0530231 struct cpuidle_driver *drv,
Deepthi Dharware978aa72011-10-28 16:20:09 +0530232 int index)
Rajendra Nayak99e6a4d2008-10-08 17:30:58 +0530233{
Deepthi Dharware978aa72011-10-28 16:20:09 +0530234 int new_state_idx;
Jean Pihetc6cd91d2011-05-09 12:02:15 +0200235 u32 core_next_state, per_next_state = 0, per_saved_state = 0, cam_state;
Jean Pihetbadc3032011-05-09 12:02:14 +0200236 struct omap3_idle_statedata *cx;
Kevin Hilmane7410cf2010-09-08 16:37:42 -0700237 int ret;
Kevin Hilman0f724ed2008-10-28 17:32:11 -0700238
Kevin Hilmane7410cf2010-09-08 16:37:42 -0700239 /*
240 * Prevent idle completely if CAM is active.
241 * CAM does not have wakeup capability in OMAP3.
242 */
243 cam_state = pwrdm_read_pwrst(cam_pd);
244 if (cam_state == PWRDM_POWER_ON) {
Deepthi Dharwar46bcfad2011-10-28 16:20:42 +0530245 new_state_idx = drv->safe_state_index;
Kevin Hilmane7410cf2010-09-08 16:37:42 -0700246 goto select_state;
247 }
248
249 /*
Jean Pihetc6cd91d2011-05-09 12:02:15 +0200250 * FIXME: we currently manage device-specific idle states
251 * for PER and CORE in combination with CPU-specific
252 * idle states. This is wrong, and device-specific
253 * idle management needs to be separated out into
254 * its own code.
255 */
256
257 /*
Kevin Hilmane7410cf2010-09-08 16:37:42 -0700258 * Prevent PER off if CORE is not in retention or off as this
259 * would disable PER wakeups completely.
260 */
Daniel Lezcano6622ac52012-04-24 16:05:35 +0200261 cx = &omap3_idle_data[index];
Jean Pihetc6cd91d2011-05-09 12:02:15 +0200262 core_next_state = cx->core_state;
Kevin Hilmane7410cf2010-09-08 16:37:42 -0700263 per_next_state = per_saved_state = pwrdm_read_next_pwrst(per_pd);
264 if ((per_next_state == PWRDM_POWER_OFF) &&
Kevin Hilman65707fb2010-10-01 08:35:47 -0700265 (core_next_state > PWRDM_POWER_RET))
Kevin Hilmane7410cf2010-09-08 16:37:42 -0700266 per_next_state = PWRDM_POWER_RET;
Kevin Hilmane7410cf2010-09-08 16:37:42 -0700267
268 /* Are we changing PER target state? */
269 if (per_next_state != per_saved_state)
270 pwrdm_set_next_pwrst(per_pd, per_next_state);
271
Deepthi Dharwar46bcfad2011-10-28 16:20:42 +0530272 new_state_idx = next_valid_state(dev, drv, index);
Jean Pihetc6cd91d2011-05-09 12:02:15 +0200273
Kevin Hilmane7410cf2010-09-08 16:37:42 -0700274select_state:
Deepthi Dharwar46bcfad2011-10-28 16:20:42 +0530275 ret = omap3_enter_idle(dev, drv, new_state_idx);
Kevin Hilmane7410cf2010-09-08 16:37:42 -0700276
277 /* Restore original PER state if it was modified */
278 if (per_next_state != per_saved_state)
279 pwrdm_set_next_pwrst(per_pd, per_saved_state);
280
281 return ret;
Rajendra Nayak99e6a4d2008-10-08 17:30:58 +0530282}
283
284DEFINE_PER_CPU(struct cpuidle_device, omap3_idle_dev);
285
Rajendra Nayak99e6a4d2008-10-08 17:30:58 +0530286struct cpuidle_driver omap3_idle_driver = {
287 .name = "omap3_idle",
288 .owner = THIS_MODULE,
Daniel Lezcano200dd522012-04-24 16:05:30 +0200289 .states = {
290 {
291 .enter = omap3_enter_idle,
292 .exit_latency = 2 + 2,
293 .target_residency = 5,
294 .flags = CPUIDLE_FLAG_TIME_VALID,
295 .name = "C1",
296 .desc = "MPU ON + CORE ON",
297 },
298 {
299 .enter = omap3_enter_idle_bm,
300 .exit_latency = 10 + 10,
301 .target_residency = 30,
302 .flags = CPUIDLE_FLAG_TIME_VALID,
303 .name = "C2",
304 .desc = "MPU ON + CORE ON",
305 },
306 {
307 .enter = omap3_enter_idle_bm,
308 .exit_latency = 50 + 50,
309 .target_residency = 300,
310 .flags = CPUIDLE_FLAG_TIME_VALID,
311 .name = "C3",
312 .desc = "MPU RET + CORE ON",
313 },
314 {
315 .enter = omap3_enter_idle_bm,
316 .exit_latency = 1500 + 1800,
317 .target_residency = 4000,
318 .flags = CPUIDLE_FLAG_TIME_VALID,
319 .name = "C4",
320 .desc = "MPU OFF + CORE ON",
321 },
322 {
323 .enter = omap3_enter_idle_bm,
324 .exit_latency = 2500 + 7500,
325 .target_residency = 12000,
326 .flags = CPUIDLE_FLAG_TIME_VALID,
327 .name = "C5",
328 .desc = "MPU RET + CORE RET",
329 },
330 {
331 .enter = omap3_enter_idle_bm,
332 .exit_latency = 3000 + 8500,
333 .target_residency = 15000,
334 .flags = CPUIDLE_FLAG_TIME_VALID,
335 .name = "C6",
336 .desc = "MPU OFF + CORE RET",
337 },
338 {
339 .enter = omap3_enter_idle_bm,
340 .exit_latency = 10000 + 30000,
341 .target_residency = 30000,
342 .flags = CPUIDLE_FLAG_TIME_VALID,
343 .name = "C7",
344 .desc = "MPU OFF + CORE OFF",
345 },
346 },
Daniel Lezcano88c377dd2012-04-24 16:05:34 +0200347 .state_count = ARRAY_SIZE(omap3_idle_data),
Daniel Lezcano200dd522012-04-24 16:05:30 +0200348 .safe_state_index = 0,
Rajendra Nayak99e6a4d2008-10-08 17:30:58 +0530349};
350
351/**
352 * omap3_idle_init - Init routine for OMAP3 idle
353 *
Jean Pihetbadc3032011-05-09 12:02:14 +0200354 * Registers the OMAP3 specific cpuidle driver to the cpuidle
Rajendra Nayak99e6a4d2008-10-08 17:30:58 +0530355 * framework with the valid set of states.
356 */
Kalle Jokiniemi03433712008-09-26 11:04:20 +0300357int __init omap3_idle_init(void)
Rajendra Nayak99e6a4d2008-10-08 17:30:58 +0530358{
Rajendra Nayak99e6a4d2008-10-08 17:30:58 +0530359 struct cpuidle_device *dev;
360
361 mpu_pd = pwrdm_lookup("mpu_pwrdm");
Rajendra Nayak20b01662008-10-08 17:31:22 +0530362 core_pd = pwrdm_lookup("core_pwrdm");
Kevin Hilmane7410cf2010-09-08 16:37:42 -0700363 per_pd = pwrdm_lookup("per_pwrdm");
364 cam_pd = pwrdm_lookup("cam_pwrdm");
Rajendra Nayak99e6a4d2008-10-08 17:30:58 +0530365
Daniel Lezcano6622ac52012-04-24 16:05:35 +0200366 cpuidle_register_driver(&omap3_idle_driver);
Deepthi Dharwar46bcfad2011-10-28 16:20:42 +0530367
Rajendra Nayak99e6a4d2008-10-08 17:30:58 +0530368 dev = &per_cpu(omap3_idle_dev, smp_processor_id());
Daniel Lezcano6622ac52012-04-24 16:05:35 +0200369 dev->cpu = 0;
Deepthi Dharwar46bcfad2011-10-28 16:20:42 +0530370
Rajendra Nayak99e6a4d2008-10-08 17:30:58 +0530371 if (cpuidle_register_device(dev)) {
372 printk(KERN_ERR "%s: CPUidle register device failed\n",
373 __func__);
374 return -EIO;
375 }
376
377 return 0;
378}
Kalle Jokiniemi03433712008-09-26 11:04:20 +0300379#else
380int __init omap3_idle_init(void)
381{
382 return 0;
383}
Rajendra Nayak99e6a4d2008-10-08 17:30:58 +0530384#endif /* CONFIG_CPU_IDLE */