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gerrit-public.fairphone.software / kernel / msm-4.9 / eeb25fd5913961562f1f4197b5485cafa54f4fe1 / . / arch / arm / boot / dts / omap2.dtsi
blob: 4aac404608cb07bb765eec24633c2240f0401bfb [file] [log] [blame]
Tony Lindgrenf20b9332011-12-16 14:13:09 -0800[diff] [blame]1/*
2 * Device Tree Source for OMAP2 SoC
3 *
4 * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
5 *
6 * This file is licensed under the terms of the GNU General Public License
7 * version 2. This program is licensed "as is" without any warranty of any
8 * kind, whether express or implied.
9 */
10
11/include/ "skeleton.dtsi"
12
13/ {
14 compatible = "ti,omap2430", "ti,omap2420", "ti,omap2";
Benoit Cousson4c94ac22012-10-24 10:47:52 +0200[diff] [blame]15 interrupt-parent = <&intc>;
Tony Lindgrenf20b9332011-12-16 14:13:09 -0800[diff] [blame]16
17 aliases {
18 serial0 = &uart1;
19 serial1 = &uart2;
20 serial2 = &uart3;
21 };
22
23 cpus {
Lorenzo Pieralisieeb25fd2013-04-18 18:35:59 +0100[diff] [blame^]24 #address-cells = <0>;
25 #size-cells = <0>;
26
27 cpu {
Tony Lindgrenf20b9332011-12-16 14:13:09 -0800[diff] [blame]28 compatible = "arm,arm1136jf-s";
Lorenzo Pieralisieeb25fd2013-04-18 18:35:59 +0100[diff] [blame^]29 device_type = "cpu";
Tony Lindgrenf20b9332011-12-16 14:13:09 -0800[diff] [blame]30 };
31 };
32
Jon Hunter9b07b472012-10-18 09:28:52 -0500[diff] [blame]33 pmu {
34 compatible = "arm,arm1136-pmu";
35 interrupts = <3>;
36 };
37
Tony Lindgrenf20b9332011-12-16 14:13:09 -0800[diff] [blame]38 soc {
39 compatible = "ti,omap-infra";
40 mpu {
41 compatible = "ti,omap2-mpu";
42 ti,hwmods = "mpu";
43 };
44 };
45
46 ocp {
47 compatible = "simple-bus";
48 #address-cells = <1>;
49 #size-cells = <1>;
50 ranges;
51 ti,hwmods = "l3_main";
52
53 intc: interrupt-controller@1 {
54 compatible = "ti,omap2-intc";
55 interrupt-controller;
56 #interrupt-cells = <1>;
Jon Hunter95dca122012-06-12 19:40:46 -0500[diff] [blame]57 ti,intc-size = <96>;
58 reg = <0x480FE000 0x1000>;
Tony Lindgrenf20b9332011-12-16 14:13:09 -0800[diff] [blame]59 };
60
Jon Hunter2c2dc542012-04-26 13:47:59 -0500[diff] [blame]61 sdma: dma-controller@48056000 {
62 compatible = "ti,omap2430-sdma", "ti,omap2420-sdma";
63 reg = <0x48056000 0x1000>;
64 interrupts = <12>,
65 <13>,
66 <14>,
67 <15>;
68 #dma-cells = <1>;
69 #dma-channels = <32>;
70 #dma-requests = <64>;
71 };
72
Tony Lindgrenf20b9332011-12-16 14:13:09 -0800[diff] [blame]73 uart1: serial@4806a000 {
74 compatible = "ti,omap2-uart";
75 ti,hwmods = "uart1";
76 clock-frequency = <48000000>;
77 };
78
79 uart2: serial@4806c000 {
80 compatible = "ti,omap2-uart";
81 ti,hwmods = "uart2";
82 clock-frequency = <48000000>;
83 };
84
85 uart3: serial@4806e000 {
86 compatible = "ti,omap2-uart";
87 ti,hwmods = "uart3";
88 clock-frequency = <48000000>;
89 };
Jon Hunterfab8ad02012-10-19 09:59:00 -0500[diff] [blame]90
91 timer2: timer@4802a000 {
Jon Hunter002e1ec2013-03-19 12:38:18 -0500[diff] [blame]92 compatible = "ti,omap2420-timer";
Jon Hunterfab8ad02012-10-19 09:59:00 -0500[diff] [blame]93 reg = <0x4802a000 0x400>;
94 interrupts = <38>;
95 ti,hwmods = "timer2";
96 };
97
98 timer3: timer@48078000 {
Jon Hunter002e1ec2013-03-19 12:38:18 -0500[diff] [blame]99 compatible = "ti,omap2420-timer";
Jon Hunterfab8ad02012-10-19 09:59:00 -0500[diff] [blame]100 reg = <0x48078000 0x400>;
101 interrupts = <39>;
102 ti,hwmods = "timer3";
103 };
104
105 timer4: timer@4807a000 {
Jon Hunter002e1ec2013-03-19 12:38:18 -0500[diff] [blame]106 compatible = "ti,omap2420-timer";
Jon Hunterfab8ad02012-10-19 09:59:00 -0500[diff] [blame]107 reg = <0x4807a000 0x400>;
108 interrupts = <40>;
109 ti,hwmods = "timer4";
110 };
111
112 timer5: timer@4807c000 {
Jon Hunter002e1ec2013-03-19 12:38:18 -0500[diff] [blame]113 compatible = "ti,omap2420-timer";
Jon Hunterfab8ad02012-10-19 09:59:00 -0500[diff] [blame]114 reg = <0x4807c000 0x400>;
115 interrupts = <41>;
116 ti,hwmods = "timer5";
117 ti,timer-dsp;
118 };
119
120 timer6: timer@4807e000 {
Jon Hunter002e1ec2013-03-19 12:38:18 -0500[diff] [blame]121 compatible = "ti,omap2420-timer";
Jon Hunterfab8ad02012-10-19 09:59:00 -0500[diff] [blame]122 reg = <0x4807e000 0x400>;
123 interrupts = <42>;
124 ti,hwmods = "timer6";
125 ti,timer-dsp;
126 };
127
128 timer7: timer@48080000 {
Jon Hunter002e1ec2013-03-19 12:38:18 -0500[diff] [blame]129 compatible = "ti,omap2420-timer";
Jon Hunterfab8ad02012-10-19 09:59:00 -0500[diff] [blame]130 reg = <0x48080000 0x400>;
131 interrupts = <43>;
132 ti,hwmods = "timer7";
133 ti,timer-dsp;
134 };
135
136 timer8: timer@48082000 {
Jon Hunter002e1ec2013-03-19 12:38:18 -0500[diff] [blame]137 compatible = "ti,omap2420-timer";
Jon Hunterfab8ad02012-10-19 09:59:00 -0500[diff] [blame]138 reg = <0x48082000 0x400>;
139 interrupts = <44>;
140 ti,hwmods = "timer8";
141 ti,timer-dsp;
142 };
143
144 timer9: timer@48084000 {
Jon Hunter002e1ec2013-03-19 12:38:18 -0500[diff] [blame]145 compatible = "ti,omap2420-timer";
Jon Hunterfab8ad02012-10-19 09:59:00 -0500[diff] [blame]146 reg = <0x48084000 0x400>;
147 interrupts = <45>;
148 ti,hwmods = "timer9";
149 ti,timer-pwm;
150 };
151
152 timer10: timer@48086000 {
Jon Hunter002e1ec2013-03-19 12:38:18 -0500[diff] [blame]153 compatible = "ti,omap2420-timer";
Jon Hunterfab8ad02012-10-19 09:59:00 -0500[diff] [blame]154 reg = <0x48086000 0x400>;
155 interrupts = <46>;
156 ti,hwmods = "timer10";
157 ti,timer-pwm;
158 };
159
160 timer11: timer@48088000 {
Jon Hunter002e1ec2013-03-19 12:38:18 -0500[diff] [blame]161 compatible = "ti,omap2420-timer";
Jon Hunterfab8ad02012-10-19 09:59:00 -0500[diff] [blame]162 reg = <0x48088000 0x400>;
163 interrupts = <47>;
164 ti,hwmods = "timer11";
165 ti,timer-pwm;
166 };
167
168 timer12: timer@4808a000 {
Jon Hunter002e1ec2013-03-19 12:38:18 -0500[diff] [blame]169 compatible = "ti,omap2420-timer";
Jon Hunterfab8ad02012-10-19 09:59:00 -0500[diff] [blame]170 reg = <0x4808a000 0x400>;
171 interrupts = <48>;
172 ti,hwmods = "timer12";
173 ti,timer-pwm;
174 };
Tony Lindgrenf20b9332011-12-16 14:13:09 -0800[diff] [blame]175 };
176};